/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Instruction Enum Values and Descriptors                             *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM

namespace llvm::R600 {

  enum {
    PHI                                   = 0, // Target.td:1200
    INLINEASM                             = 1, // Target.td:1206
    INLINEASM_BR                          = 2, // Target.td:1212
    CFI_INSTRUCTION                       = 3, // Target.td:1221
    EH_LABEL                              = 4, // Target.td:1230
    GC_LABEL                              = 5, // Target.td:1239
    ANNOTATION_LABEL                      = 6, // Target.td:1248
    KILL                                  = 7, // Target.td:1256
    EXTRACT_SUBREG                        = 8, // Target.td:1263
    INSERT_SUBREG                         = 9, // Target.td:1269
    IMPLICIT_DEF                          = 10, // Target.td:1276
    INIT_UNDEF                            = 11, // Target.td:1285
    SUBREG_TO_REG                         = 12, // Target.td:1292
    COPY_TO_REGCLASS                      = 13, // Target.td:1298
    DBG_VALUE                             = 14, // Target.td:1305
    DBG_VALUE_LIST                        = 15, // Target.td:1312
    DBG_INSTR_REF                         = 16, // Target.td:1319
    DBG_PHI                               = 17, // Target.td:1326
    DBG_LABEL                             = 18, // Target.td:1333
    REG_SEQUENCE                          = 19, // Target.td:1340
    COPY                                  = 20, // Target.td:1347
    COPY_LANEMASK                         = 21, // Target.td:1355
    BUNDLE                                = 22, // Target.td:1362
    LIFETIME_START                        = 23, // Target.td:1368
    LIFETIME_END                          = 24, // Target.td:1375
    PSEUDO_PROBE                          = 25, // Target.td:1382
    ARITH_FENCE                           = 26, // Target.td:1389
    STACKMAP                              = 27, // Target.td:1398
    FENTRY_CALL                           = 28, // Target.td:1533
    PATCHPOINT                            = 29, // Target.td:1406
    LOAD_STACK_GUARD                      = 30, // Target.td:1424
    PREALLOCATED_SETUP                    = 31, // Target.td:1432
    PREALLOCATED_ARG                      = 32, // Target.td:1438
    STATEPOINT                            = 33, // Target.td:1415
    LOCAL_ESCAPE                          = 34, // Target.td:1444
    FAULTING_OP                           = 35, // Target.td:1453
    PATCHABLE_OP                          = 36, // Target.td:1473
    PATCHABLE_FUNCTION_ENTER              = 37, // Target.td:1481
    PATCHABLE_RET                         = 38, // Target.td:1488
    PATCHABLE_FUNCTION_EXIT               = 39, // Target.td:1497
    PATCHABLE_TAIL_CALL                   = 40, // Target.td:1505
    PATCHABLE_EVENT_CALL                  = 41, // Target.td:1513
    PATCHABLE_TYPED_EVENT_CALL            = 42, // Target.td:1523
    ICALL_BRANCH_FUNNEL                   = 43, // Target.td:1543
    FAKE_USE                              = 44, // Target.td:1463
    MEMBARRIER                            = 45, // Target.td:1549
    JUMP_TABLE_DEBUG_INFO                 = 46, // Target.td:1557
    RELOC_NONE                            = 47, // Target.td:1565
    CONVERGENCECTRL_ENTRY                 = 48, // Target.td:1576
    CONVERGENCECTRL_ANCHOR                = 49, // Target.td:1572
    CONVERGENCECTRL_LOOP                  = 50, // Target.td:1580
    CONVERGENCECTRL_GLUE                  = 51, // Target.td:1584
    G_ASSERT_SEXT                         = 52, // GenericOpcodes.td:1859
    G_ASSERT_ZEXT                         = 53, // GenericOpcodes.td:1851
    G_ASSERT_ALIGN                        = 54, // GenericOpcodes.td:1866
    G_ADD                                 = 55, // GenericOpcodes.td:294
    G_SUB                                 = 56, // GenericOpcodes.td:302
    G_MUL                                 = 57, // GenericOpcodes.td:310
    G_SDIV                                = 58, // GenericOpcodes.td:318
    G_UDIV                                = 59, // GenericOpcodes.td:326
    G_SREM                                = 60, // GenericOpcodes.td:334
    G_UREM                                = 61, // GenericOpcodes.td:342
    G_SDIVREM                             = 62, // GenericOpcodes.td:350
    G_UDIVREM                             = 63, // GenericOpcodes.td:358
    G_AND                                 = 64, // GenericOpcodes.td:366
    G_OR                                  = 65, // GenericOpcodes.td:374
    G_XOR                                 = 66, // GenericOpcodes.td:382
    G_ABDS                                = 67, // GenericOpcodes.td:411
    G_ABDU                                = 68, // GenericOpcodes.td:419
    G_UAVGFLOOR                           = 69, // GenericOpcodes.td:427
    G_UAVGCEIL                            = 70, // GenericOpcodes.td:434
    G_SAVGFLOOR                           = 71, // GenericOpcodes.td:441
    G_SAVGCEIL                            = 72, // GenericOpcodes.td:448
    G_IMPLICIT_DEF                        = 73, // GenericOpcodes.td:110
    G_PHI                                 = 74, // GenericOpcodes.td:116
    G_FRAME_INDEX                         = 75, // GenericOpcodes.td:122
    G_GLOBAL_VALUE                        = 76, // GenericOpcodes.td:128
    G_PTRAUTH_GLOBAL_VALUE                = 77, // GenericOpcodes.td:134
    G_CONSTANT_POOL                       = 78, // GenericOpcodes.td:140
    G_EXTRACT                             = 79, // GenericOpcodes.td:1466
    G_UNMERGE_VALUES                      = 80, // GenericOpcodes.td:1478
    G_INSERT                              = 81, // GenericOpcodes.td:1486
    G_MERGE_VALUES                        = 82, // GenericOpcodes.td:1496
    G_BUILD_VECTOR                        = 83, // GenericOpcodes.td:1515
    G_BUILD_VECTOR_TRUNC                  = 84, // GenericOpcodes.td:1524
    G_CONCAT_VECTORS                      = 85, // GenericOpcodes.td:1531
    G_PTRTOINT                            = 86, // GenericOpcodes.td:152
    G_INTTOPTR                            = 87, // GenericOpcodes.td:146
    G_BITCAST                             = 88, // GenericOpcodes.td:158
    G_FREEZE                              = 89, // GenericOpcodes.td:271
    G_CONSTANT_FOLD_BARRIER               = 90, // GenericOpcodes.td:1873
    G_INTRINSIC_FPTRUNC_ROUND             = 91, // GenericOpcodes.td:1257
    G_INTRINSIC_TRUNC                     = 92, // GenericOpcodes.td:1263
    G_INTRINSIC_ROUND                     = 93, // GenericOpcodes.td:1269
    G_INTRINSIC_LRINT                     = 94, // GenericOpcodes.td:1275
    G_INTRINSIC_LLRINT                    = 95, // GenericOpcodes.td:1281
    G_INTRINSIC_ROUNDEVEN                 = 96, // GenericOpcodes.td:1287
    G_READCYCLECOUNTER                    = 97, // GenericOpcodes.td:1293
    G_READSTEADYCOUNTER                   = 98, // GenericOpcodes.td:1299
    G_LOAD                                = 99, // GenericOpcodes.td:1326
    G_SEXTLOAD                            = 100, // GenericOpcodes.td:1334
    G_ZEXTLOAD                            = 101, // GenericOpcodes.td:1342
    G_INDEXED_LOAD                        = 102, // GenericOpcodes.td:1352
    G_INDEXED_SEXTLOAD                    = 103, // GenericOpcodes.td:1360
    G_INDEXED_ZEXTLOAD                    = 104, // GenericOpcodes.td:1368
    G_STORE                               = 105, // GenericOpcodes.td:1376
    G_INDEXED_STORE                       = 106, // GenericOpcodes.td:1384
    G_ATOMIC_CMPXCHG_WITH_SUCCESS         = 107, // GenericOpcodes.td:1394
    G_ATOMIC_CMPXCHG                      = 108, // GenericOpcodes.td:1404
    G_ATOMICRMW_XCHG                      = 109, // GenericOpcodes.td:1422
    G_ATOMICRMW_ADD                       = 110, // GenericOpcodes.td:1423
    G_ATOMICRMW_SUB                       = 111, // GenericOpcodes.td:1424
    G_ATOMICRMW_AND                       = 112, // GenericOpcodes.td:1425
    G_ATOMICRMW_NAND                      = 113, // GenericOpcodes.td:1426
    G_ATOMICRMW_OR                        = 114, // GenericOpcodes.td:1427
    G_ATOMICRMW_XOR                       = 115, // GenericOpcodes.td:1428
    G_ATOMICRMW_MAX                       = 116, // GenericOpcodes.td:1429
    G_ATOMICRMW_MIN                       = 117, // GenericOpcodes.td:1430
    G_ATOMICRMW_UMAX                      = 118, // GenericOpcodes.td:1431
    G_ATOMICRMW_UMIN                      = 119, // GenericOpcodes.td:1432
    G_ATOMICRMW_FADD                      = 120, // GenericOpcodes.td:1433
    G_ATOMICRMW_FSUB                      = 121, // GenericOpcodes.td:1434
    G_ATOMICRMW_FMAX                      = 122, // GenericOpcodes.td:1435
    G_ATOMICRMW_FMIN                      = 123, // GenericOpcodes.td:1436
    G_ATOMICRMW_FMAXIMUM                  = 124, // GenericOpcodes.td:1437
    G_ATOMICRMW_FMINIMUM                  = 125, // GenericOpcodes.td:1438
    G_ATOMICRMW_UINC_WRAP                 = 126, // GenericOpcodes.td:1439
    G_ATOMICRMW_UDEC_WRAP                 = 127, // GenericOpcodes.td:1440
    G_ATOMICRMW_USUB_COND                 = 128, // GenericOpcodes.td:1441
    G_ATOMICRMW_USUB_SAT                  = 129, // GenericOpcodes.td:1442
    G_FENCE                               = 130, // GenericOpcodes.td:1444
    G_PREFETCH                            = 131, // GenericOpcodes.td:1451
    G_BRCOND                              = 132, // GenericOpcodes.td:1586
    G_BRINDIRECT                          = 133, // GenericOpcodes.td:1595
    G_INVOKE_REGION_START                 = 134, // GenericOpcodes.td:1618
    G_INTRINSIC                           = 135, // GenericOpcodes.td:1538
    G_INTRINSIC_W_SIDE_EFFECTS            = 136, // GenericOpcodes.td:1545
    G_INTRINSIC_CONVERGENT                = 137, // GenericOpcodes.td:1554
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1562
    G_ANYEXT                              = 139, // GenericOpcodes.td:44
    G_TRUNC                               = 140, // GenericOpcodes.td:83
    G_TRUNC_SSAT_S                        = 141, // GenericOpcodes.td:90
    G_TRUNC_SSAT_U                        = 142, // GenericOpcodes.td:97
    G_TRUNC_USAT_U                        = 143, // GenericOpcodes.td:104
    G_CONSTANT                            = 144, // GenericOpcodes.td:165
    G_FCONSTANT                           = 145, // GenericOpcodes.td:172
    G_VASTART                             = 146, // GenericOpcodes.td:178
    G_VAARG                               = 147, // GenericOpcodes.td:185
    G_SEXT                                = 148, // GenericOpcodes.td:52
    G_SEXT_INREG                          = 149, // GenericOpcodes.td:66
    G_ZEXT                                = 150, // GenericOpcodes.td:74
    G_SHL                                 = 151, // GenericOpcodes.td:390
    G_LSHR                                = 152, // GenericOpcodes.td:397
    G_ASHR                                = 153, // GenericOpcodes.td:404
    G_FSHL                                = 154, // GenericOpcodes.td:456
    G_FSHR                                = 155, // GenericOpcodes.td:464
    G_ROTR                                = 156, // GenericOpcodes.td:471
    G_ROTL                                = 157, // GenericOpcodes.td:478
    G_ICMP                                = 158, // GenericOpcodes.td:485
    G_FCMP                                = 159, // GenericOpcodes.td:492
    G_SCMP                                = 160, // GenericOpcodes.td:499
    G_UCMP                                = 161, // GenericOpcodes.td:506
    G_SELECT                              = 162, // GenericOpcodes.td:513
    G_UADDO                               = 163, // GenericOpcodes.td:578
    G_UADDE                               = 164, // GenericOpcodes.td:586
    G_USUBO                               = 165, // GenericOpcodes.td:608
    G_USUBE                               = 166, // GenericOpcodes.td:614
    G_SADDO                               = 167, // GenericOpcodes.td:593
    G_SADDE                               = 168, // GenericOpcodes.td:601
    G_SSUBO                               = 169, // GenericOpcodes.td:621
    G_SSUBE                               = 170, // GenericOpcodes.td:628
    G_UMULO                               = 171, // GenericOpcodes.td:635
    G_SMULO                               = 172, // GenericOpcodes.td:643
    G_UMULH                               = 173, // GenericOpcodes.td:652
    G_SMULH                               = 174, // GenericOpcodes.td:661
    G_UADDSAT                             = 175, // GenericOpcodes.td:673
    G_SADDSAT                             = 176, // GenericOpcodes.td:681
    G_USUBSAT                             = 177, // GenericOpcodes.td:689
    G_SSUBSAT                             = 178, // GenericOpcodes.td:697
    G_USHLSAT                             = 179, // GenericOpcodes.td:705
    G_SSHLSAT                             = 180, // GenericOpcodes.td:713
    G_SMULFIX                             = 181, // GenericOpcodes.td:725
    G_UMULFIX                             = 182, // GenericOpcodes.td:732
    G_SMULFIXSAT                          = 183, // GenericOpcodes.td:742
    G_UMULFIXSAT                          = 184, // GenericOpcodes.td:749
    G_SDIVFIX                             = 185, // GenericOpcodes.td:760
    G_UDIVFIX                             = 186, // GenericOpcodes.td:767
    G_SDIVFIXSAT                          = 187, // GenericOpcodes.td:777
    G_UDIVFIXSAT                          = 188, // GenericOpcodes.td:784
    G_FADD                                = 189, // GenericOpcodes.td:957
    G_FSUB                                = 190, // GenericOpcodes.td:965
    G_FMUL                                = 191, // GenericOpcodes.td:973
    G_FMA                                 = 192, // GenericOpcodes.td:982
    G_FMAD                                = 193, // GenericOpcodes.td:991
    G_FDIV                                = 194, // GenericOpcodes.td:999
    G_FREM                                = 195, // GenericOpcodes.td:1006
    G_FMODF                               = 196, // GenericOpcodes.td:1013
    G_FPOW                                = 197, // GenericOpcodes.td:1020
    G_FPOWI                               = 198, // GenericOpcodes.td:1027
    G_FEXP                                = 199, // GenericOpcodes.td:1034
    G_FEXP2                               = 200, // GenericOpcodes.td:1041
    G_FEXP10                              = 201, // GenericOpcodes.td:1048
    G_FLOG                                = 202, // GenericOpcodes.td:1055
    G_FLOG2                               = 203, // GenericOpcodes.td:1062
    G_FLOG10                              = 204, // GenericOpcodes.td:1069
    G_FLDEXP                              = 205, // GenericOpcodes.td:1076
    G_FFREXP                              = 206, // GenericOpcodes.td:1083
    G_FNEG                                = 207, // GenericOpcodes.td:795
    G_FPEXT                               = 208, // GenericOpcodes.td:801
    G_FPTRUNC                             = 209, // GenericOpcodes.td:807
    G_FPTOSI                              = 210, // GenericOpcodes.td:813
    G_FPTOUI                              = 211, // GenericOpcodes.td:819
    G_SITOFP                              = 212, // GenericOpcodes.td:825
    G_UITOFP                              = 213, // GenericOpcodes.td:831
    G_FPTOSI_SAT                          = 214, // GenericOpcodes.td:837
    G_FPTOUI_SAT                          = 215, // GenericOpcodes.td:843
    G_FABS                                = 216, // GenericOpcodes.td:849
    G_FCOPYSIGN                           = 217, // GenericOpcodes.td:855
    G_IS_FPCLASS                          = 218, // GenericOpcodes.td:868
    G_FCANONICALIZE                       = 219, // GenericOpcodes.td:861
    G_FMINNUM                             = 220, // GenericOpcodes.td:881
    G_FMAXNUM                             = 221, // GenericOpcodes.td:888
    G_FMINNUM_IEEE                        = 222, // GenericOpcodes.td:906
    G_FMAXNUM_IEEE                        = 223, // GenericOpcodes.td:913
    G_FMINIMUM                            = 224, // GenericOpcodes.td:923
    G_FMAXIMUM                            = 225, // GenericOpcodes.td:930
    G_FMINIMUMNUM                         = 226, // GenericOpcodes.td:938
    G_FMAXIMUMNUM                         = 227, // GenericOpcodes.td:945
    G_GET_FPENV                           = 228, // GenericOpcodes.td:1213
    G_SET_FPENV                           = 229, // GenericOpcodes.td:1220
    G_RESET_FPENV                         = 230, // GenericOpcodes.td:1227
    G_GET_FPMODE                          = 231, // GenericOpcodes.td:1234
    G_SET_FPMODE                          = 232, // GenericOpcodes.td:1241
    G_RESET_FPMODE                        = 233, // GenericOpcodes.td:1248
    G_GET_ROUNDING                        = 234, // GenericOpcodes.td:1305
    G_SET_ROUNDING                        = 235, // GenericOpcodes.td:1311
    G_PTR_ADD                             = 236, // GenericOpcodes.td:520
    G_PTRMASK                             = 237, // GenericOpcodes.td:528
    G_SMIN                                = 238, // GenericOpcodes.td:535
    G_SMAX                                = 239, // GenericOpcodes.td:543
    G_UMIN                                = 240, // GenericOpcodes.td:551
    G_UMAX                                = 241, // GenericOpcodes.td:559
    G_ABS                                 = 242, // GenericOpcodes.td:567
    G_LROUND                              = 243, // GenericOpcodes.td:277
    G_LLROUND                             = 244, // GenericOpcodes.td:283
    G_BR                                  = 245, // GenericOpcodes.td:1576
    G_BRJT                                = 246, // GenericOpcodes.td:1606
    G_VSCALE                              = 247, // GenericOpcodes.td:1506
    G_INSERT_SUBVECTOR                    = 248, // GenericOpcodes.td:1650
    G_EXTRACT_SUBVECTOR                   = 249, // GenericOpcodes.td:1657
    G_INSERT_VECTOR_ELT                   = 250, // GenericOpcodes.td:1664
    G_EXTRACT_VECTOR_ELT                  = 251, // GenericOpcodes.td:1671
    G_SHUFFLE_VECTOR                      = 252, // GenericOpcodes.td:1681
    G_SPLAT_VECTOR                        = 253, // GenericOpcodes.td:1688
    G_STEP_VECTOR                         = 254, // GenericOpcodes.td:1695
    G_VECTOR_COMPRESS                     = 255, // GenericOpcodes.td:1702
    G_CTTZ                                = 256, // GenericOpcodes.td:205
    G_CTTZ_ZERO_UNDEF                     = 257, // GenericOpcodes.td:211
    G_CTLZ                                = 258, // GenericOpcodes.td:193
    G_CTLZ_ZERO_UNDEF                     = 259, // GenericOpcodes.td:199
    G_CTPOP                               = 260, // GenericOpcodes.td:217
    G_BSWAP                               = 261, // GenericOpcodes.td:223
    G_BITREVERSE                          = 262, // GenericOpcodes.td:229
    G_FCEIL                               = 263, // GenericOpcodes.td:1090
    G_FCOS                                = 264, // GenericOpcodes.td:1097
    G_FSIN                                = 265, // GenericOpcodes.td:1104
    G_FSINCOS                             = 266, // GenericOpcodes.td:1111
    G_FTAN                                = 267, // GenericOpcodes.td:1118
    G_FACOS                               = 268, // GenericOpcodes.td:1125
    G_FASIN                               = 269, // GenericOpcodes.td:1132
    G_FATAN                               = 270, // GenericOpcodes.td:1139
    G_FATAN2                              = 271, // GenericOpcodes.td:1146
    G_FCOSH                               = 272, // GenericOpcodes.td:1153
    G_FSINH                               = 273, // GenericOpcodes.td:1160
    G_FTANH                               = 274, // GenericOpcodes.td:1167
    G_FSQRT                               = 275, // GenericOpcodes.td:1177
    G_FFLOOR                              = 276, // GenericOpcodes.td:1184
    G_FRINT                               = 277, // GenericOpcodes.td:1191
    G_FNEARBYINT                          = 278, // GenericOpcodes.td:1198
    G_ADDRSPACE_CAST                      = 279, // GenericOpcodes.td:235
    G_BLOCK_ADDR                          = 280, // GenericOpcodes.td:241
    G_JUMP_TABLE                          = 281, // GenericOpcodes.td:247
    G_DYN_STACKALLOC                      = 282, // GenericOpcodes.td:253
    G_STACKSAVE                           = 283, // GenericOpcodes.td:259
    G_STACKRESTORE                        = 284, // GenericOpcodes.td:265
    G_STRICT_FADD                         = 285, // GenericOpcodes.td:1752
    G_STRICT_FSUB                         = 286, // GenericOpcodes.td:1753
    G_STRICT_FMUL                         = 287, // GenericOpcodes.td:1754
    G_STRICT_FDIV                         = 288, // GenericOpcodes.td:1755
    G_STRICT_FREM                         = 289, // GenericOpcodes.td:1756
    G_STRICT_FMA                          = 290, // GenericOpcodes.td:1757
    G_STRICT_FSQRT                        = 291, // GenericOpcodes.td:1758
    G_STRICT_FLDEXP                       = 292, // GenericOpcodes.td:1759
    G_READ_REGISTER                       = 293, // GenericOpcodes.td:1625
    G_WRITE_REGISTER                      = 294, // GenericOpcodes.td:1635
    G_MEMCPY                              = 295, // GenericOpcodes.td:1765
    G_MEMCPY_INLINE                       = 296, // GenericOpcodes.td:1773
    G_MEMMOVE                             = 297, // GenericOpcodes.td:1781
    G_MEMSET                              = 298, // GenericOpcodes.td:1789
    G_BZERO                               = 299, // GenericOpcodes.td:1796
    G_TRAP                                = 300, // GenericOpcodes.td:1806
    G_DEBUGTRAP                           = 301, // GenericOpcodes.td:1813
    G_UBSANTRAP                           = 302, // GenericOpcodes.td:1819
    G_VECREDUCE_SEQ_FADD                  = 303, // GenericOpcodes.td:1718
    G_VECREDUCE_SEQ_FMUL                  = 304, // GenericOpcodes.td:1724
    G_VECREDUCE_FADD                      = 305, // GenericOpcodes.td:1730
    G_VECREDUCE_FMUL                      = 306, // GenericOpcodes.td:1731
    G_VECREDUCE_FMAX                      = 307, // GenericOpcodes.td:1733
    G_VECREDUCE_FMIN                      = 308, // GenericOpcodes.td:1734
    G_VECREDUCE_FMAXIMUM                  = 309, // GenericOpcodes.td:1735
    G_VECREDUCE_FMINIMUM                  = 310, // GenericOpcodes.td:1736
    G_VECREDUCE_ADD                       = 311, // GenericOpcodes.td:1738
    G_VECREDUCE_MUL                       = 312, // GenericOpcodes.td:1739
    G_VECREDUCE_AND                       = 313, // GenericOpcodes.td:1740
    G_VECREDUCE_OR                        = 314, // GenericOpcodes.td:1741
    G_VECREDUCE_XOR                       = 315, // GenericOpcodes.td:1742
    G_VECREDUCE_SMAX                      = 316, // GenericOpcodes.td:1743
    G_VECREDUCE_SMIN                      = 317, // GenericOpcodes.td:1744
    G_VECREDUCE_UMAX                      = 318, // GenericOpcodes.td:1745
    G_VECREDUCE_UMIN                      = 319, // GenericOpcodes.td:1746
    G_SBFX                                = 320, // GenericOpcodes.td:1831
    G_UBFX                                = 321, // GenericOpcodes.td:1839
    BRANCH                                = 322, // R600Instructions.td:1594
    BRANCH_COND_f32                       = 323, // R600Instructions.td:1567
    BRANCH_COND_i32                       = 324, // R600Instructions.td:1563
    BREAK                                 = 325, // R600Instructions.td:1608
    BREAKC_f32                            = 326, // R600Instructions.td:1584
    BREAKC_i32                            = 327, // R600Instructions.td:1582
    BREAK_LOGICALNZ_f32                   = 328, // R600Instructions.td:1577
    BREAK_LOGICALNZ_i32                   = 329, // R600Instructions.td:1575
    BREAK_LOGICALZ_f32                    = 330, // R600Instructions.td:1577
    BREAK_LOGICALZ_i32                    = 331, // R600Instructions.td:1575
    CONST_COPY                            = 332, // R600Instructions.td:1439
    CONTINUE                              = 333, // R600Instructions.td:1610
    CONTINUEC_f32                         = 334, // R600Instructions.td:1584
    CONTINUEC_i32                         = 335, // R600Instructions.td:1582
    CONTINUE_LOGICALNZ_f32                = 336, // R600Instructions.td:1577
    CONTINUE_LOGICALNZ_i32                = 337, // R600Instructions.td:1575
    CONTINUE_LOGICALZ_f32                 = 338, // R600Instructions.td:1577
    CONTINUE_LOGICALZ_i32                 = 339, // R600Instructions.td:1575
    CUBE_eg_pseudo                        = 340, // R600Instructions.td:1074
    CUBE_r600_pseudo                      = 341, // R600Instructions.td:1074
    DEFAULT                               = 342, // R600Instructions.td:1612
    DOT_4                                 = 343, // R600Instructions.td:1061
    DUMMY_CHAIN                           = 344, // R600Instructions.td:792
    ELSE                                  = 345, // R600Instructions.td:1614
    END                                   = 346, // R600Instructions.td:1620
    ENDFUNC                               = 347, // R600Instructions.td:1622
    ENDIF                                 = 348, // R600Instructions.td:1624
    ENDLOOP                               = 349, // R600Instructions.td:1628
    ENDMAIN                               = 350, // R600Instructions.td:1618
    ENDSWITCH                             = 351, // R600Instructions.td:1616
    FABS_R600                             = 352, // R600Instructions.td:1204
    FNEG_R600                             = 353, // R600Instructions.td:1205
    FUNC                                  = 354, // R600Instructions.td:1630
    IFC_f32                               = 355, // R600Instructions.td:1584
    IFC_i32                               = 356, // R600Instructions.td:1582
    IF_LOGICALNZ_f32                      = 357, // R600Instructions.td:1577
    IF_LOGICALNZ_i32                      = 358, // R600Instructions.td:1575
    IF_LOGICALZ_f32                       = 359, // R600Instructions.td:1577
    IF_LOGICALZ_i32                       = 360, // R600Instructions.td:1575
    IF_PREDICATE_SET                      = 361, // R600Instructions.td:1604
    JUMP                                  = 362, // R600Instructions.td:1385
    JUMP_COND                             = 363, // R600Instructions.td:1378
    MASK_WRITE                            = 364, // R600Instructions.td:1402
    MOV_IMM_F32                           = 365, // R600Instructions.td:827
    MOV_IMM_GLOBAL_ADDR                   = 366, // R600Instructions.td:820
    MOV_IMM_I32                           = 367, // R600Instructions.td:814
    PRED_X                                = 368, // R600Instructions.td:1370
    R600_EXTRACT_ELT_V2                   = 369, // R600Instructions.td:1677
    R600_EXTRACT_ELT_V4                   = 370, // R600Instructions.td:1678
    R600_INSERT_ELT_V2                    = 371, // R600Instructions.td:1680
    R600_INSERT_ELT_V4                    = 372, // R600Instructions.td:1681
    R600_RegisterLoad                     = 373, // R600Instructions.td:698
    R600_RegisterStore                    = 374, // R600Instructions.td:707
    RETDYN                                = 375, // R600Instructions.td:1632
    RETURN                                = 376, // R600Instructions.td:88
    TXD                                   = 377, // R600Instructions.td:1413
    TXD_SHADOW                            = 378, // R600Instructions.td:1422
    WHILELOOP                             = 379, // R600Instructions.td:1626
    ADD                                   = 380, // R600Instructions.td:721
    ADDC_UINT                             = 381, // EvergreenInstructions.td:526
    ADD_INT                               = 382, // R600Instructions.td:848
    ALU_CLAUSE                            = 383, // R600Instructions.td:646
    AND_INT                               = 384, // R600Instructions.td:844
    ASHR_eg                               = 385, // EvergreenInstructions.td:511
    ASHR_r600                             = 386, // R600Instructions.td:1253
    BCNT_INT                              = 387, // EvergreenInstructions.td:531
    BFE_INT_eg                            = 388, // EvergreenInstructions.td:370
    BFE_UINT_eg                           = 389, // EvergreenInstructions.td:365
    BFI_INT_eg                            = 390, // EvergreenInstructions.td:411
    BFM_INT_eg                            = 391, // EvergreenInstructions.td:492
    BIT_ALIGN_INT_eg                      = 392, // EvergreenInstructions.td:503
    CEIL                                  = 393, // R600Instructions.td:781
    CF_ALU                                = 394, // R600Instructions.td:631
    CF_ALU_BREAK                          = 395, // R600Instructions.td:635
    CF_ALU_CONTINUE                       = 396, // R600Instructions.td:634
    CF_ALU_ELSE_AFTER                     = 397, // R600Instructions.td:636
    CF_ALU_POP_AFTER                      = 398, // R600Instructions.td:633
    CF_ALU_PUSH_BEFORE                    = 399, // R600Instructions.td:632
    CF_CALL_FS_EG                         = 400, // EvergreenInstructions.td:853
    CF_CALL_FS_R600                       = 401, // R600Instructions.td:1325
    CF_CONTINUE_EG                        = 402, // EvergreenInstructions.td:836
    CF_CONTINUE_R600                      = 403, // R600Instructions.td:1307
    CF_ELSE_EG                            = 404, // EvergreenInstructions.td:849
    CF_ELSE_R600                          = 405, // R600Instructions.td:1321
    CF_END_CM                             = 406, // CaymanInstructions.td:66
    CF_END_EG                             = 407, // EvergreenInstructions.td:862
    CF_END_R600                           = 408, // R600Instructions.td:1334
    CF_JUMP_EG                            = 409, // EvergreenInstructions.td:841
    CF_JUMP_R600                          = 410, // R600Instructions.td:1312
    CF_PUSH_EG                            = 411, // EvergreenInstructions.td:845
    CF_PUSH_ELSE_R600                     = 412, // R600Instructions.td:1316
    CF_TC_EG                              = 413, // EvergreenInstructions.td:814
    CF_TC_R600                            = 414, // R600Instructions.td:1285
    CF_VC_EG                              = 415, // EvergreenInstructions.td:818
    CF_VC_R600                            = 416, // R600Instructions.td:1289
    CNDE_INT                              = 417, // R600Instructions.td:890
    CNDE_eg                               = 418, // EvergreenInstructions.td:514
    CNDE_r600                             = 419, // R600Instructions.td:1235
    CNDGE_INT                             = 420, // R600Instructions.td:895
    CNDGE_eg                              = 421, // EvergreenInstructions.td:516
    CNDGE_r600                            = 422, // R600Instructions.td:1237
    CNDGT_INT                             = 423, // R600Instructions.td:900
    CNDGT_eg                              = 424, // EvergreenInstructions.td:515
    CNDGT_r600                            = 425, // R600Instructions.td:1236
    COS_cm                                = 426, // CaymanInstructions.td:48
    COS_eg                                = 427, // EvergreenInstructions.td:132
    COS_r600                              = 428, // R600Instructions.td:1252
    COS_r700                              = 429, // R700Instructions.td:19
    CUBE_eg_real                          = 430, // R600Instructions.td:1085
    CUBE_r600_real                        = 431, // R600Instructions.td:1085
    DOT4_eg                               = 432, // EvergreenInstructions.td:522
    DOT4_r600                             = 433, // R600Instructions.td:1238
    EG_ExportBuf                          = 434, // EvergreenInstructions.td:804
    EG_ExportSwz                          = 435, // EvergreenInstructions.td:794
    END_LOOP_EG                           = 436, // EvergreenInstructions.td:827
    END_LOOP_R600                         = 437, // R600Instructions.td:1298
    EXP_IEEE_cm                           = 438, // CaymanInstructions.td:43
    EXP_IEEE_eg                           = 439, // EvergreenInstructions.td:125
    EXP_IEEE_r600                         = 440, // R600Instructions.td:1240
    FETCH_CLAUSE                          = 441, // R600Instructions.td:638
    FFBH_UINT                             = 442, // EvergreenInstructions.td:532
    FFBL_INT                              = 443, // EvergreenInstructions.td:533
    FLOOR                                 = 444, // R600Instructions.td:783
    FLT16_TO_FLT32                        = 445, // EvergreenInstructions.td:530
    FLT32_TO_FLT16                        = 446, // EvergreenInstructions.td:529
    FLT_TO_INT_eg                         = 447, // EvergreenInstructions.td:539
    FLT_TO_INT_r600                       = 448, // R600Instructions.td:1247
    FLT_TO_UINT_eg                        = 449, // EvergreenInstructions.td:546
    FLT_TO_UINT_r600                      = 450, // R600Instructions.td:1249
    FMA_eg                                = 451, // EvergreenInstructions.td:510
    FRACT                                 = 452, // R600Instructions.td:779
    GROUP_BARRIER                         = 453, // EvergreenInstructions.td:552
    INTERP_LOAD_P0                        = 454, // R600Instructions.td:445
    INTERP_PAIR_XY                        = 455, // R600Instructions.td:367
    INTERP_PAIR_ZW                        = 456, // R600Instructions.td:373
    INTERP_VEC_LOAD                       = 457, // R600Instructions.td:430
    INTERP_XY                             = 458, // R600Instructions.td:437
    INTERP_ZW                             = 459, // R600Instructions.td:441
    INT_TO_FLT_eg                         = 460, // EvergreenInstructions.td:544
    INT_TO_FLT_r600                       = 461, // R600Instructions.td:1248
    KILLGT                                = 462, // R600Instructions.td:840
    LDS_ADD                               = 463, // EvergreenInstructions.td:690
    LDS_ADD_RET                           = 464, // EvergreenInstructions.td:710
    LDS_AND                               = 465, // EvergreenInstructions.td:692
    LDS_AND_RET                           = 466, // EvergreenInstructions.td:716
    LDS_BYTE_READ_RET                     = 467, // EvergreenInstructions.td:746
    LDS_BYTE_WRITE                        = 468, // EvergreenInstructions.td:704
    LDS_CMPST                             = 469, // EvergreenInstructions.td:696
    LDS_CMPST_RET                         = 470, // EvergreenInstructions.td:740
    LDS_MAX_INT                           = 471, // EvergreenInstructions.td:698
    LDS_MAX_INT_RET                       = 472, // EvergreenInstructions.td:728
    LDS_MAX_UINT                          = 473, // EvergreenInstructions.td:700
    LDS_MAX_UINT_RET                      = 474, // EvergreenInstructions.td:734
    LDS_MIN_INT                           = 475, // EvergreenInstructions.td:697
    LDS_MIN_INT_RET                       = 476, // EvergreenInstructions.td:725
    LDS_MIN_UINT                          = 477, // EvergreenInstructions.td:699
    LDS_MIN_UINT_RET                      = 478, // EvergreenInstructions.td:731
    LDS_OR                                = 479, // EvergreenInstructions.td:693
    LDS_OR_RET                            = 480, // EvergreenInstructions.td:719
    LDS_READ_RET                          = 481, // EvergreenInstructions.td:743
    LDS_SHORT_READ_RET                    = 482, // EvergreenInstructions.td:752
    LDS_SHORT_WRITE                       = 483, // EvergreenInstructions.td:707
    LDS_SUB                               = 484, // EvergreenInstructions.td:691
    LDS_SUB_RET                           = 485, // EvergreenInstructions.td:713
    LDS_UBYTE_READ_RET                    = 486, // EvergreenInstructions.td:749
    LDS_USHORT_READ_RET                   = 487, // EvergreenInstructions.td:755
    LDS_WRITE                             = 488, // EvergreenInstructions.td:701
    LDS_WRXCHG                            = 489, // EvergreenInstructions.td:695
    LDS_WRXCHG_RET                        = 490, // EvergreenInstructions.td:737
    LDS_XOR                               = 491, // EvergreenInstructions.td:694
    LDS_XOR_RET                           = 492, // EvergreenInstructions.td:722
    LITERALS                              = 493, // R600Instructions.td:654
    LOG_CLAMPED_eg                        = 494, // EvergreenInstructions.td:518
    LOG_CLAMPED_r600                      = 495, // R600Instructions.td:1241
    LOG_IEEE_cm                           = 496, // CaymanInstructions.td:44
    LOG_IEEE_eg                           = 497, // EvergreenInstructions.td:126
    LOG_IEEE_r600                         = 498, // R600Instructions.td:1242
    LOOP_BREAK_EG                         = 499, // EvergreenInstructions.td:831
    LOOP_BREAK_R600                       = 500, // R600Instructions.td:1302
    LSHL_eg                               = 501, // EvergreenInstructions.td:513
    LSHL_r600                             = 502, // R600Instructions.td:1255
    LSHR_eg                               = 503, // EvergreenInstructions.td:512
    LSHR_r600                             = 504, // R600Instructions.td:1254
    MAX                                   = 505, // R600Instructions.td:726
    MAX_DX10                              = 506, // R600Instructions.td:731
    MAX_INT                               = 507, // R600Instructions.td:850
    MAX_UINT                              = 508, // R600Instructions.td:852
    MIN                                   = 509, // R600Instructions.td:727
    MIN_DX10                              = 510, // R600Instructions.td:732
    MIN_INT                               = 511, // R600Instructions.td:851
    MIN_UINT                              = 512, // R600Instructions.td:853
    MOV                                   = 513, // R600Instructions.td:785
    MOVA_INT_eg                           = 514, // EvergreenInstructions.td:536
    MUL                                   = 515, // R600Instructions.td:723
    MULADD_IEEE_eg                        = 516, // EvergreenInstructions.td:509
    MULADD_IEEE_r600                      = 517, // R600Instructions.td:1234
    MULADD_INT24_cm                       = 518, // CaymanInstructions.td:22
    MULADD_UINT24_eg                      = 519, // EvergreenInstructions.td:497
    MULADD_eg                             = 520, // EvergreenInstructions.td:508
    MULADD_r600                           = 521, // R600Instructions.td:1233
    MULHI_INT_cm                          = 522, // CaymanInstructions.td:36
    MULHI_INT_cm24                        = 523, // CaymanInstructions.td:39
    MULHI_INT_eg                          = 524, // EvergreenInstructions.td:118
    MULHI_INT_r600                        = 525, // R600Instructions.td:1257
    MULHI_UINT24_eg                       = 526, // EvergreenInstructions.td:121
    MULHI_UINT_cm                         = 527, // CaymanInstructions.td:38
    MULHI_UINT_cm24                       = 528, // CaymanInstructions.td:40
    MULHI_UINT_eg                         = 529, // EvergreenInstructions.td:120
    MULHI_UINT_r600                       = 530, // R600Instructions.td:1259
    MULLO_INT_cm                          = 531, // CaymanInstructions.td:35
    MULLO_INT_eg                          = 532, // EvergreenInstructions.td:117
    MULLO_INT_r600                        = 533, // R600Instructions.td:1256
    MULLO_UINT_cm                         = 534, // CaymanInstructions.td:37
    MULLO_UINT_eg                         = 535, // EvergreenInstructions.td:119
    MULLO_UINT_r600                       = 536, // R600Instructions.td:1258
    MUL_IEEE                              = 537, // R600Instructions.td:724
    MUL_INT24_cm                          = 538, // CaymanInstructions.td:25
    MUL_LIT_eg                            = 539, // EvergreenInstructions.td:517
    MUL_LIT_r600                          = 540, // R600Instructions.td:1232
    MUL_UINT24_eg                         = 541, // EvergreenInstructions.td:519
    NOT_INT                               = 542, // R600Instructions.td:847
    OR_INT                                = 543, // R600Instructions.td:845
    PAD                                   = 544, // R600Instructions.td:666
    POP_EG                                = 545, // EvergreenInstructions.td:858
    POP_R600                              = 546, // R600Instructions.td:1330
    PRED_SETE                             = 547, // R600Instructions.td:833
    PRED_SETE_INT                         = 548, // R600Instructions.td:885
    PRED_SETGE                            = 549, // R600Instructions.td:835
    PRED_SETGE_INT                        = 550, // R600Instructions.td:887
    PRED_SETGT                            = 551, // R600Instructions.td:834
    PRED_SETGT_INT                        = 552, // R600Instructions.td:886
    PRED_SETNE                            = 553, // R600Instructions.td:836
    PRED_SETNE_INT                        = 554, // R600Instructions.td:888
    R600_ExportBuf                        = 555, // R600Instructions.td:1276
    R600_ExportSwz                        = 556, // R600Instructions.td:1267
    RAT_ATOMIC_ADD_NORET                  = 557, // EvergreenInstructions.td:82
    RAT_ATOMIC_ADD_RTN                    = 558, // EvergreenInstructions.td:78
    RAT_ATOMIC_AND_NORET                  = 559, // EvergreenInstructions.td:82
    RAT_ATOMIC_AND_RTN                    = 560, // EvergreenInstructions.td:78
    RAT_ATOMIC_CMPXCHG_INT_NORET          = 561, // EvergreenInstructions.td:82
    RAT_ATOMIC_CMPXCHG_INT_RTN            = 562, // EvergreenInstructions.td:78
    RAT_ATOMIC_DEC_UINT_NORET             = 563, // EvergreenInstructions.td:82
    RAT_ATOMIC_DEC_UINT_RTN               = 564, // EvergreenInstructions.td:78
    RAT_ATOMIC_INC_UINT_NORET             = 565, // EvergreenInstructions.td:82
    RAT_ATOMIC_INC_UINT_RTN               = 566, // EvergreenInstructions.td:78
    RAT_ATOMIC_MAX_INT_NORET              = 567, // EvergreenInstructions.td:82
    RAT_ATOMIC_MAX_INT_RTN                = 568, // EvergreenInstructions.td:78
    RAT_ATOMIC_MAX_UINT_NORET             = 569, // EvergreenInstructions.td:82
    RAT_ATOMIC_MAX_UINT_RTN               = 570, // EvergreenInstructions.td:78
    RAT_ATOMIC_MIN_INT_NORET              = 571, // EvergreenInstructions.td:82
    RAT_ATOMIC_MIN_INT_RTN                = 572, // EvergreenInstructions.td:78
    RAT_ATOMIC_MIN_UINT_NORET             = 573, // EvergreenInstructions.td:82
    RAT_ATOMIC_MIN_UINT_RTN               = 574, // EvergreenInstructions.td:78
    RAT_ATOMIC_OR_NORET                   = 575, // EvergreenInstructions.td:82
    RAT_ATOMIC_OR_RTN                     = 576, // EvergreenInstructions.td:78
    RAT_ATOMIC_RSUB_NORET                 = 577, // EvergreenInstructions.td:82
    RAT_ATOMIC_RSUB_RTN                   = 578, // EvergreenInstructions.td:78
    RAT_ATOMIC_SUB_NORET                  = 579, // EvergreenInstructions.td:82
    RAT_ATOMIC_SUB_RTN                    = 580, // EvergreenInstructions.td:78
    RAT_ATOMIC_XCHG_INT_NORET             = 581, // EvergreenInstructions.td:82
    RAT_ATOMIC_XCHG_INT_RTN               = 582, // EvergreenInstructions.td:78
    RAT_ATOMIC_XOR_NORET                  = 583, // EvergreenInstructions.td:82
    RAT_ATOMIC_XOR_RTN                    = 584, // EvergreenInstructions.td:78
    RAT_MSKOR                             = 585, // EvergreenInstructions.td:67
    RAT_STORE_DWORD128                    = 586, // CaymanInstructions.td:84
    RAT_STORE_DWORD32                     = 587, // CaymanInstructions.td:82
    RAT_STORE_DWORD64                     = 588, // CaymanInstructions.td:83
    RAT_STORE_TYPED_cm                    = 589, // CaymanInstructions.td:86
    RAT_STORE_TYPED_eg                    = 590, // EvergreenInstructions.td:164
    RAT_WRITE_CACHELESS_128_eg            = 591, // EvergreenInstructions.td:158
    RAT_WRITE_CACHELESS_32_eg             = 592, // EvergreenInstructions.td:144
    RAT_WRITE_CACHELESS_64_eg             = 593, // EvergreenInstructions.td:151
    RECIPSQRT_CLAMPED_cm                  = 594, // CaymanInstructions.td:42
    RECIPSQRT_CLAMPED_eg                  = 595, // EvergreenInstructions.td:124
    RECIPSQRT_CLAMPED_r600                = 596, // R600Instructions.td:1245
    RECIPSQRT_IEEE_cm                     = 597, // CaymanInstructions.td:46
    RECIPSQRT_IEEE_eg                     = 598, // EvergreenInstructions.td:128
    RECIPSQRT_IEEE_r600                   = 599, // R600Instructions.td:1246
    RECIP_CLAMPED_cm                      = 600, // CaymanInstructions.td:45
    RECIP_CLAMPED_eg                      = 601, // EvergreenInstructions.td:127
    RECIP_CLAMPED_r600                    = 602, // R600Instructions.td:1243
    RECIP_IEEE_cm                         = 603, // CaymanInstructions.td:33
    RECIP_IEEE_eg                         = 604, // EvergreenInstructions.td:114
    RECIP_IEEE_r600                       = 605, // R600Instructions.td:1244
    RECIP_UINT_eg                         = 606, // EvergreenInstructions.td:123
    RECIP_UINT_r600                       = 607, // R600Instructions.td:1260
    RNDNE                                 = 608, // R600Instructions.td:782
    SETE                                  = 609, // R600Instructions.td:737
    SETE_DX10                             = 610, // R600Instructions.td:757
    SETE_INT                              = 611, // R600Instructions.td:855
    SETGE_DX10                            = 612, // R600Instructions.td:767
    SETGE_INT                             = 613, // R600Instructions.td:865
    SETGE_UINT                            = 614, // R600Instructions.td:880
    SETGT_DX10                            = 615, // R600Instructions.td:762
    SETGT_INT                             = 616, // R600Instructions.td:860
    SETGT_UINT                            = 617, // R600Instructions.td:875
    SETNE_DX10                            = 618, // R600Instructions.td:773
    SETNE_INT                             = 619, // R600Instructions.td:870
    SGE                                   = 620, // R600Instructions.td:747
    SGT                                   = 621, // R600Instructions.td:742
    SIN_cm                                = 622, // CaymanInstructions.td:47
    SIN_eg                                = 623, // EvergreenInstructions.td:131
    SIN_r600                              = 624, // R600Instructions.td:1251
    SIN_r700                              = 625, // R700Instructions.td:18
    SNE                                   = 626, // R600Instructions.td:752
    SUBB_UINT                             = 627, // EvergreenInstructions.td:527
    SUB_INT                               = 628, // R600Instructions.td:849
    TEX_GET_GRADIENTS_H                   = 629, // R600Instructions.td:959
    TEX_GET_GRADIENTS_V                   = 630, // R600Instructions.td:960
    TEX_GET_TEXTURE_RESINFO               = 631, // R600Instructions.td:958
    TEX_LD                                = 632, // R600Instructions.td:954
    TEX_LDPTR                             = 633, // R600Instructions.td:955
    TEX_SAMPLE                            = 634, // R600Instructions.td:948
    TEX_SAMPLE_C                          = 635, // R600Instructions.td:949
    TEX_SAMPLE_C_G                        = 636, // R600Instructions.td:964
    TEX_SAMPLE_C_L                        = 637, // R600Instructions.td:951
    TEX_SAMPLE_C_LB                       = 638, // R600Instructions.td:953
    TEX_SAMPLE_G                          = 639, // R600Instructions.td:963
    TEX_SAMPLE_L                          = 640, // R600Instructions.td:950
    TEX_SAMPLE_LB                         = 641, // R600Instructions.td:952
    TEX_SET_GRADIENTS_H                   = 642, // R600Instructions.td:961
    TEX_SET_GRADIENTS_V                   = 643, // R600Instructions.td:962
    TEX_VTX_CONSTBUF                      = 644, // R600Instructions.td:1451
    TEX_VTX_TEXBUF                        = 645, // R600Instructions.td:1505
    TRUNC                                 = 646, // R600Instructions.td:780
    UINT_TO_FLT_eg                        = 647, // EvergreenInstructions.td:550
    UINT_TO_FLT_r600                      = 648, // R600Instructions.td:1250
    VTX_READ_128_cm                       = 649, // CaymanInstructions.td:162
    VTX_READ_128_eg                       = 650, // EvergreenInstructions.td:240
    VTX_READ_16_cm                        = 651, // CaymanInstructions.td:120
    VTX_READ_16_eg                        = 652, // EvergreenInstructions.td:195
    VTX_READ_32_cm                        = 653, // CaymanInstructions.td:131
    VTX_READ_32_eg                        = 654, // EvergreenInstructions.td:207
    VTX_READ_64_cm                        = 655, // CaymanInstructions.td:151
    VTX_READ_64_eg                        = 656, // EvergreenInstructions.td:228
    VTX_READ_8_cm                         = 657, // CaymanInstructions.td:109
    VTX_READ_8_eg                         = 658, // EvergreenInstructions.td:183
    WHILE_LOOP_EG                         = 659, // EvergreenInstructions.td:822
    WHILE_LOOP_R600                       = 660, // R600Instructions.td:1293
    XOR_INT                               = 661, // R600Instructions.td:846
    INSTRUCTION_LIST_END = 662
  };

} // namespace llvm::R600

#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM

namespace llvm::R600::Sched {

  enum {
    NoInstrModel	= 0,
    NullALU	= 1,
    VecALU	= 2,
    AnyALU	= 3,
    TransALU	= 4,
    XALU	= 5,
    SCHED_LIST_END = 6
  };

} // namespace llvm::R600::Sched

#endif // GET_INSTRINFO_SCHED_ENUM

#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

namespace llvm {

struct R600InstrTable {
  MCInstrDesc Insts[662];
  static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
  MCPhysReg ImplicitOps[1];
  char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
  MCOperandInfo OperandInfo[465];
};
} // namespace llvm

#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC

namespace llvm {

static_assert((sizeof R600InstrTable::ImplicitOps + sizeof R600InstrTable::Padding) % sizeof(MCOperandInfo) == 0);
static constexpr unsigned R600OpInfoBase = (sizeof R600InstrTable::ImplicitOps + sizeof R600InstrTable::Padding) / sizeof(MCOperandInfo);

extern const R600InstrTable R600Descs = {
  {
    { 661,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // XOR_INT
    { 660,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // WHILE_LOOP_R600
    { 659,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // WHILE_LOOP_EG
    { 658,	4,	1,	0,	1,	0,	0,	R600OpInfoBase + 453,	0,	0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // VTX_READ_8_eg
    { 657,	4,	1,	0,	1,	0,	0,	R600OpInfoBase + 453,	0,	0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // VTX_READ_8_cm
    { 656,	4,	1,	0,	1,	0,	0,	R600OpInfoBase + 461,	0,	0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // VTX_READ_64_eg
    { 655,	4,	1,	0,	1,	0,	0,	R600OpInfoBase + 461,	0,	0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // VTX_READ_64_cm
    { 654,	4,	1,	0,	1,	0,	0,	R600OpInfoBase + 457,	0,	0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // VTX_READ_32_eg
    { 653,	4,	1,	0,	1,	0,	0,	R600OpInfoBase + 457,	0,	0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // VTX_READ_32_cm
    { 652,	4,	1,	0,	1,	0,	0,	R600OpInfoBase + 453,	0,	0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // VTX_READ_16_eg
    { 651,	4,	1,	0,	1,	0,	0,	R600OpInfoBase + 453,	0,	0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // VTX_READ_16_cm
    { 650,	4,	1,	0,	1,	0,	0,	R600OpInfoBase + 449,	0,	0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // VTX_READ_128_eg
    { 649,	4,	1,	0,	1,	0,	0,	R600OpInfoBase + 449,	0,	0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // VTX_READ_128_cm
    { 648,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // UINT_TO_FLT_r600
    { 647,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // UINT_TO_FLT_eg
    { 646,	14,	1,	0,	3,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // TRUNC
    { 645,	4,	1,	0,	1,	0,	0,	R600OpInfoBase + 449,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x1000ULL },  // TEX_VTX_TEXBUF
    { 644,	4,	1,	0,	1,	0,	0,	R600OpInfoBase + 449,	0,	0, 0x1000ULL },  // TEX_VTX_CONSTBUF
    { 643,	19,	1,	0,	1,	0,	0,	R600OpInfoBase + 430,	0,	0, 0x2000ULL },  // TEX_SET_GRADIENTS_V
    { 642,	19,	1,	0,	1,	0,	0,	R600OpInfoBase + 430,	0,	0, 0x2000ULL },  // TEX_SET_GRADIENTS_H
    { 641,	19,	1,	0,	1,	0,	0,	R600OpInfoBase + 430,	0,	0, 0x2000ULL },  // TEX_SAMPLE_LB
    { 640,	19,	1,	0,	1,	0,	0,	R600OpInfoBase + 430,	0,	0, 0x2000ULL },  // TEX_SAMPLE_L
    { 639,	19,	1,	0,	1,	0,	0,	R600OpInfoBase + 430,	0,	0, 0x2000ULL },  // TEX_SAMPLE_G
    { 638,	19,	1,	0,	1,	0,	0,	R600OpInfoBase + 430,	0,	0, 0x2000ULL },  // TEX_SAMPLE_C_LB
    { 637,	19,	1,	0,	1,	0,	0,	R600OpInfoBase + 430,	0,	0, 0x2000ULL },  // TEX_SAMPLE_C_L
    { 636,	19,	1,	0,	1,	0,	0,	R600OpInfoBase + 430,	0,	0, 0x2000ULL },  // TEX_SAMPLE_C_G
    { 635,	19,	1,	0,	1,	0,	0,	R600OpInfoBase + 430,	0,	0, 0x2000ULL },  // TEX_SAMPLE_C
    { 634,	19,	1,	0,	1,	0,	0,	R600OpInfoBase + 430,	0,	0, 0x2000ULL },  // TEX_SAMPLE
    { 633,	19,	1,	0,	1,	0,	0,	R600OpInfoBase + 430,	0,	0, 0x2000ULL },  // TEX_LDPTR
    { 632,	19,	1,	0,	1,	0,	0,	R600OpInfoBase + 430,	0,	0, 0x2000ULL },  // TEX_LD
    { 631,	19,	1,	0,	1,	0,	0,	R600OpInfoBase + 430,	0,	0, 0x2000ULL },  // TEX_GET_TEXTURE_RESINFO
    { 630,	19,	1,	0,	1,	0,	0,	R600OpInfoBase + 430,	0,	0, 0x2000ULL },  // TEX_GET_GRADIENTS_V
    { 629,	19,	1,	0,	1,	0,	0,	R600OpInfoBase + 430,	0,	0, 0x2000ULL },  // TEX_GET_GRADIENTS_H
    { 628,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // SUB_INT
    { 627,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // SUBB_UINT
    { 626,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // SNE
    { 625,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4610ULL },  // SIN_r700
    { 624,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4610ULL },  // SIN_r600
    { 623,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4610ULL },  // SIN_eg
    { 622,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4650ULL },  // SIN_cm
    { 621,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // SGT
    { 620,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // SGE
    { 619,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // SETNE_INT
    { 618,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // SETNE_DX10
    { 617,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // SETGT_UINT
    { 616,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // SETGT_INT
    { 615,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // SETGT_DX10
    { 614,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // SETGE_UINT
    { 613,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // SETGE_INT
    { 612,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // SETGE_DX10
    { 611,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // SETE_INT
    { 610,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // SETE_DX10
    { 609,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // SETE
    { 608,	14,	1,	0,	3,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // RNDNE
    { 607,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // RECIP_UINT_r600
    { 606,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // RECIP_UINT_eg
    { 605,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // RECIP_IEEE_r600
    { 604,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // RECIP_IEEE_eg
    { 603,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4640ULL },  // RECIP_IEEE_cm
    { 602,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // RECIP_CLAMPED_r600
    { 601,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // RECIP_CLAMPED_eg
    { 600,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4640ULL },  // RECIP_CLAMPED_cm
    { 599,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // RECIPSQRT_IEEE_r600
    { 598,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // RECIPSQRT_IEEE_eg
    { 597,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4640ULL },  // RECIPSQRT_IEEE_cm
    { 596,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // RECIPSQRT_CLAMPED_r600
    { 595,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // RECIPSQRT_CLAMPED_eg
    { 594,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4640ULL },  // RECIPSQRT_CLAMPED_cm
    { 593,	3,	0,	0,	1,	0,	0,	R600OpInfoBase + 427,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL },  // RAT_WRITE_CACHELESS_64_eg
    { 592,	3,	0,	0,	1,	0,	0,	R600OpInfoBase + 424,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL },  // RAT_WRITE_CACHELESS_32_eg
    { 591,	3,	0,	0,	1,	0,	0,	R600OpInfoBase + 421,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL },  // RAT_WRITE_CACHELESS_128_eg
    { 590,	4,	0,	0,	1,	0,	0,	R600OpInfoBase + 417,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_STORE_TYPED_eg
    { 589,	4,	0,	0,	1,	0,	0,	R600OpInfoBase + 417,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_STORE_TYPED_cm
    { 588,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 415,	0,	0|(1ULL<<MCID::MayStore), 0x20000ULL },  // RAT_STORE_DWORD64
    { 587,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 413,	0,	0|(1ULL<<MCID::MayStore), 0x20000ULL },  // RAT_STORE_DWORD32
    { 586,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 411,	0,	0|(1ULL<<MCID::MayStore), 0x20000ULL },  // RAT_STORE_DWORD128
    { 585,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 411,	0,	0|(1ULL<<MCID::MayStore), 0x20000ULL },  // RAT_MSKOR
    { 584,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_XOR_RTN
    { 583,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_XOR_NORET
    { 582,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_XCHG_INT_RTN
    { 581,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_XCHG_INT_NORET
    { 580,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_SUB_RTN
    { 579,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_SUB_NORET
    { 578,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_RSUB_RTN
    { 577,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_RSUB_NORET
    { 576,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_OR_RTN
    { 575,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_OR_NORET
    { 574,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_MIN_UINT_RTN
    { 573,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_MIN_UINT_NORET
    { 572,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_MIN_INT_RTN
    { 571,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_MIN_INT_NORET
    { 570,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_MAX_UINT_RTN
    { 569,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_MAX_UINT_NORET
    { 568,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_MAX_INT_RTN
    { 567,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_MAX_INT_NORET
    { 566,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_INC_UINT_RTN
    { 565,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_INC_UINT_NORET
    { 564,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_DEC_UINT_RTN
    { 563,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_DEC_UINT_NORET
    { 562,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_CMPXCHG_INT_RTN
    { 561,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_CMPXCHG_INT_NORET
    { 560,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_AND_RTN
    { 559,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_AND_NORET
    { 558,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_ADD_RTN
    { 557,	3,	1,	0,	1,	0,	0,	R600OpInfoBase + 408,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // RAT_ATOMIC_ADD_NORET
    { 556,	9,	0,	0,	1,	0,	0,	R600OpInfoBase + 336,	0,	0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // R600_ExportSwz
    { 555,	7,	0,	0,	1,	0,	0,	R600OpInfoBase + 329,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // R600_ExportBuf
    { 554,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // PRED_SETNE_INT
    { 553,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // PRED_SETNE
    { 552,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // PRED_SETGT_INT
    { 551,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // PRED_SETGT
    { 550,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // PRED_SETGE_INT
    { 549,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // PRED_SETGE
    { 548,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // PRED_SETE_INT
    { 547,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // PRED_SETE
    { 546,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 24,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // POP_R600
    { 545,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 24,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // POP_EG
    { 544,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // PAD
    { 543,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // OR_INT
    { 542,	14,	1,	0,	3,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // NOT_INT
    { 541,	21,	1,	0,	2,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MUL_UINT24_eg
    { 540,	19,	1,	0,	3,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // MUL_LIT_r600
    { 539,	19,	1,	0,	3,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // MUL_LIT_eg
    { 538,	21,	1,	0,	2,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MUL_INT24_cm
    { 537,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MUL_IEEE
    { 536,	21,	1,	0,	4,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MULLO_UINT_r600
    { 535,	21,	1,	0,	4,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MULLO_UINT_eg
    { 534,	21,	1,	0,	4,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a40ULL },  // MULLO_UINT_cm
    { 533,	21,	1,	0,	4,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MULLO_INT_r600
    { 532,	21,	1,	0,	4,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MULLO_INT_eg
    { 531,	21,	1,	0,	4,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a40ULL },  // MULLO_INT_cm
    { 530,	21,	1,	0,	4,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MULHI_UINT_r600
    { 529,	21,	1,	0,	4,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MULHI_UINT_eg
    { 528,	21,	1,	0,	2,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a40ULL },  // MULHI_UINT_cm24
    { 527,	21,	1,	0,	4,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a40ULL },  // MULHI_UINT_cm
    { 526,	21,	1,	0,	2,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MULHI_UINT24_eg
    { 525,	21,	1,	0,	4,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MULHI_INT_r600
    { 524,	21,	1,	0,	4,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MULHI_INT_eg
    { 523,	21,	1,	0,	2,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a40ULL },  // MULHI_INT_cm24
    { 522,	21,	1,	0,	4,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a40ULL },  // MULHI_INT_cm
    { 521,	19,	1,	0,	3,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // MULADD_r600
    { 520,	19,	1,	0,	3,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // MULADD_eg
    { 519,	19,	1,	0,	2,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // MULADD_UINT24_eg
    { 518,	19,	1,	0,	2,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // MULADD_INT24_cm
    { 517,	19,	1,	0,	3,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // MULADD_IEEE_r600
    { 516,	19,	1,	0,	3,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // MULADD_IEEE_eg
    { 515,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MUL
    { 514,	14,	1,	0,	2,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4600ULL },  // MOVA_INT_eg
    { 513,	14,	1,	0,	3,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // MOV
    { 512,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MIN_UINT
    { 511,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MIN_INT
    { 510,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MIN_DX10
    { 509,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MIN
    { 508,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MAX_UINT
    { 507,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MAX_INT
    { 506,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MAX_DX10
    { 505,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // MAX
    { 504,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // LSHR_r600
    { 503,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // LSHR_eg
    { 502,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // LSHL_r600
    { 501,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // LSHL_eg
    { 500,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // LOOP_BREAK_R600
    { 499,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // LOOP_BREAK_EG
    { 498,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // LOG_IEEE_r600
    { 497,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // LOG_IEEE_eg
    { 496,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4640ULL },  // LOG_IEEE_cm
    { 495,	14,	1,	0,	3,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // LOG_CLAMPED_r600
    { 494,	14,	1,	0,	3,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // LOG_CLAMPED_eg
    { 493,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 13,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // LITERALS
    { 492,	10,	1,	0,	5,	0,	0,	R600OpInfoBase + 366,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // LDS_XOR_RET
    { 491,	9,	0,	0,	5,	0,	0,	R600OpInfoBase + 357,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // LDS_XOR
    { 490,	10,	1,	0,	5,	0,	0,	R600OpInfoBase + 366,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // LDS_WRXCHG_RET
    { 489,	9,	0,	0,	5,	0,	0,	R600OpInfoBase + 357,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // LDS_WRXCHG
    { 488,	9,	0,	0,	5,	0,	0,	R600OpInfoBase + 357,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL },  // LDS_WRITE
    { 487,	7,	1,	0,	5,	0,	0,	R600OpInfoBase + 376,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL },  // LDS_USHORT_READ_RET
    { 486,	7,	1,	0,	5,	0,	0,	R600OpInfoBase + 376,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL },  // LDS_UBYTE_READ_RET
    { 485,	10,	1,	0,	5,	0,	0,	R600OpInfoBase + 366,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // LDS_SUB_RET
    { 484,	9,	0,	0,	5,	0,	0,	R600OpInfoBase + 357,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // LDS_SUB
    { 483,	9,	0,	0,	5,	0,	0,	R600OpInfoBase + 357,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL },  // LDS_SHORT_WRITE
    { 482,	7,	1,	0,	5,	0,	0,	R600OpInfoBase + 376,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL },  // LDS_SHORT_READ_RET
    { 481,	7,	1,	0,	5,	0,	0,	R600OpInfoBase + 376,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL },  // LDS_READ_RET
    { 480,	10,	1,	0,	5,	0,	0,	R600OpInfoBase + 366,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // LDS_OR_RET
    { 479,	9,	0,	0,	5,	0,	0,	R600OpInfoBase + 357,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // LDS_OR
    { 478,	10,	1,	0,	5,	0,	0,	R600OpInfoBase + 366,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // LDS_MIN_UINT_RET
    { 477,	9,	0,	0,	5,	0,	0,	R600OpInfoBase + 357,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // LDS_MIN_UINT
    { 476,	10,	1,	0,	5,	0,	0,	R600OpInfoBase + 366,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // LDS_MIN_INT_RET
    { 475,	9,	0,	0,	5,	0,	0,	R600OpInfoBase + 357,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // LDS_MIN_INT
    { 474,	10,	1,	0,	5,	0,	0,	R600OpInfoBase + 366,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // LDS_MAX_UINT_RET
    { 473,	9,	0,	0,	5,	0,	0,	R600OpInfoBase + 357,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // LDS_MAX_UINT
    { 472,	10,	1,	0,	5,	0,	0,	R600OpInfoBase + 366,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // LDS_MAX_INT_RET
    { 471,	9,	0,	0,	5,	0,	0,	R600OpInfoBase + 357,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // LDS_MAX_INT
    { 470,	13,	1,	0,	5,	0,	0,	R600OpInfoBase + 395,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x44200ULL },  // LDS_CMPST_RET
    { 469,	12,	0,	0,	5,	0,	0,	R600OpInfoBase + 383,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44200ULL },  // LDS_CMPST
    { 468,	9,	0,	0,	5,	0,	0,	R600OpInfoBase + 357,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL },  // LDS_BYTE_WRITE
    { 467,	7,	1,	0,	5,	0,	0,	R600OpInfoBase + 376,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL },  // LDS_BYTE_READ_RET
    { 466,	10,	1,	0,	5,	0,	0,	R600OpInfoBase + 366,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // LDS_AND_RET
    { 465,	9,	0,	0,	5,	0,	0,	R600OpInfoBase + 357,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // LDS_AND
    { 464,	10,	1,	0,	5,	0,	0,	R600OpInfoBase + 366,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // LDS_ADD_RET
    { 463,	9,	0,	0,	5,	0,	0,	R600OpInfoBase + 357,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // LDS_ADD
    { 462,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4a00ULL },  // KILLGT
    { 461,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // INT_TO_FLT_r600
    { 460,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // INT_TO_FLT_eg
    { 459,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // INTERP_ZW
    { 458,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // INTERP_XY
    { 457,	2,	1,	0,	1,	0,	0,	R600OpInfoBase + 355,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // INTERP_VEC_LOAD
    { 456,	5,	2,	0,	1,	0,	0,	R600OpInfoBase + 350,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // INTERP_PAIR_ZW
    { 455,	5,	2,	0,	1,	0,	0,	R600OpInfoBase + 345,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // INTERP_PAIR_XY
    { 454,	14,	1,	0,	3,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // INTERP_LOAD_P0
    { 453,	0,	0,	0,	3,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000ULL },  // GROUP_BARRIER
    { 452,	14,	1,	0,	3,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // FRACT
    { 451,	19,	1,	0,	2,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // FMA_eg
    { 450,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // FLT_TO_UINT_r600
    { 449,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // FLT_TO_UINT_eg
    { 448,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // FLT_TO_INT_r600
    { 447,	14,	1,	0,	3,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // FLT_TO_INT_eg
    { 446,	14,	1,	0,	2,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // FLT32_TO_FLT16
    { 445,	14,	1,	0,	2,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // FLT16_TO_FLT32
    { 444,	14,	1,	0,	3,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // FLOOR
    { 443,	14,	1,	0,	2,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // FFBL_INT
    { 442,	14,	1,	0,	2,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // FFBH_UINT
    { 441,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // FETCH_CLAUSE
    { 440,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // EXP_IEEE_r600
    { 439,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // EXP_IEEE_eg
    { 438,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4640ULL },  // EXP_IEEE_cm
    { 437,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // END_LOOP_R600
    { 436,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // END_LOOP_EG
    { 435,	9,	0,	0,	1,	0,	0,	R600OpInfoBase + 336,	0,	0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // EG_ExportSwz
    { 434,	7,	0,	0,	1,	0,	0,	R600OpInfoBase + 329,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // EG_ExportBuf
    { 433,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // DOT4_r600
    { 432,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // DOT4_eg
    { 431,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // CUBE_r600_real
    { 430,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // CUBE_eg_real
    { 429,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4610ULL },  // COS_r700
    { 428,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4610ULL },  // COS_r600
    { 427,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4610ULL },  // COS_eg
    { 426,	14,	1,	0,	4,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4650ULL },  // COS_cm
    { 425,	19,	1,	0,	2,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // CNDGT_r600
    { 424,	19,	1,	0,	2,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // CNDGT_eg
    { 423,	19,	1,	0,	3,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // CNDGT_INT
    { 422,	19,	1,	0,	2,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // CNDGE_r600
    { 421,	19,	1,	0,	2,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // CNDGE_eg
    { 420,	19,	1,	0,	3,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // CNDGE_INT
    { 419,	19,	1,	0,	3,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // CNDE_r600
    { 418,	19,	1,	0,	3,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // CNDE_eg
    { 417,	19,	1,	0,	3,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // CNDE_INT
    { 416,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 24,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_VC_R600
    { 415,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 24,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_VC_EG
    { 414,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 24,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_TC_R600
    { 413,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 24,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_TC_EG
    { 412,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_PUSH_ELSE_R600
    { 411,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 24,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_PUSH_EG
    { 410,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 24,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_JUMP_R600
    { 409,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 24,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_JUMP_EG
    { 408,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_END_R600
    { 407,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_END_EG
    { 406,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_END_CM
    { 405,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 24,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_ELSE_R600
    { 404,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 24,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_ELSE_EG
    { 403,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_CONTINUE_R600
    { 402,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_CONTINUE_EG
    { 401,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_CALL_FS_R600
    { 400,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_CALL_FS_EG
    { 399,	9,	0,	0,	1,	0,	0,	R600OpInfoBase + 320,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_ALU_PUSH_BEFORE
    { 398,	9,	0,	0,	1,	0,	0,	R600OpInfoBase + 320,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_ALU_POP_AFTER
    { 397,	9,	0,	0,	1,	0,	0,	R600OpInfoBase + 320,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_ALU_ELSE_AFTER
    { 396,	9,	0,	0,	1,	0,	0,	R600OpInfoBase + 320,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_ALU_CONTINUE
    { 395,	9,	0,	0,	1,	0,	0,	R600OpInfoBase + 320,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_ALU_BREAK
    { 394,	9,	0,	0,	1,	0,	0,	R600OpInfoBase + 320,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // CF_ALU
    { 393,	14,	1,	0,	3,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // CEIL
    { 392,	19,	1,	0,	2,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // BIT_ALIGN_INT_eg
    { 391,	21,	1,	0,	2,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // BFM_INT_eg
    { 390,	19,	1,	0,	2,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // BFI_INT_eg
    { 389,	19,	1,	0,	2,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // BFE_UINT_eg
    { 388,	19,	1,	0,	2,	0,	0,	R600OpInfoBase + 301,	0,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // BFE_INT_eg
    { 387,	14,	1,	0,	2,	0,	0,	R600OpInfoBase + 287,	0,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // BCNT_INT
    { 386,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // ASHR_r600
    { 385,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // ASHR_eg
    { 384,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // AND_INT
    { 383,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // ALU_CLAUSE
    { 382,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // ADD_INT
    { 381,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // ADDC_UINT
    { 380,	21,	1,	0,	3,	0,	0,	R600OpInfoBase + 266,	0,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // ADD
    { 379,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // WHILELOOP
    { 378,	7,	1,	0,	1,	0,	0,	R600OpInfoBase + 259,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL },  // TXD_SHADOW
    { 377,	7,	1,	0,	1,	0,	0,	R600OpInfoBase + 259,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL },  // TXD
    { 376,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic), 0x0ULL },  // RETURN
    { 375,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // RETDYN
    { 374,	4,	0,	0,	1,	0,	0,	R600OpInfoBase + 255,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000000000000000ULL },  // R600_RegisterStore
    { 373,	4,	1,	0,	1,	0,	0,	R600OpInfoBase + 255,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8000000000000000ULL },  // R600_RegisterLoad
    { 372,	4,	1,	0,	3,	0,	0,	R600OpInfoBase + 251,	0,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // R600_INSERT_ELT_V4
    { 371,	4,	1,	0,	3,	0,	0,	R600OpInfoBase + 247,	0,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // R600_INSERT_ELT_V2
    { 370,	3,	1,	0,	3,	0,	0,	R600OpInfoBase + 244,	0,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // R600_EXTRACT_ELT_V4
    { 369,	3,	1,	0,	3,	0,	0,	R600OpInfoBase + 241,	0,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // R600_EXTRACT_ELT_V2
    { 368,	4,	1,	0,	1,	0,	0,	R600OpInfoBase + 237,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL },  // PRED_X
    { 367,	2,	1,	0,	1,	0,	0,	R600OpInfoBase + 160,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // MOV_IMM_I32
    { 366,	2,	1,	0,	1,	0,	0,	R600OpInfoBase + 160,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // MOV_IMM_GLOBAL_ADDR
    { 365,	2,	1,	0,	1,	0,	0,	R600OpInfoBase + 160,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // MOV_IMM_F32
    { 364,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 159,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // MASK_WRITE
    { 363,	2,	0,	0,	3,	0,	0,	R600OpInfoBase + 235,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // JUMP_COND
    { 362,	1,	0,	0,	3,	0,	0,	R600OpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // JUMP
    { 361,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 159,	0,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // IF_PREDICATE_SET
    { 360,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 159,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // IF_LOGICALZ_i32
    { 359,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 159,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // IF_LOGICALZ_f32
    { 358,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 159,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // IF_LOGICALNZ_i32
    { 357,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 159,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // IF_LOGICALNZ_f32
    { 356,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 157,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // IFC_i32
    { 355,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 157,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // IFC_f32
    { 354,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // FUNC
    { 353,	2,	1,	0,	1,	0,	0,	R600OpInfoBase + 157,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // FNEG_R600
    { 352,	2,	1,	0,	1,	0,	0,	R600OpInfoBase + 157,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // FABS_R600
    { 351,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // ENDSWITCH
    { 350,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // ENDMAIN
    { 349,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // ENDLOOP
    { 348,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // ENDIF
    { 347,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // ENDFUNC
    { 346,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // END
    { 345,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // ELSE
    { 344,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // DUMMY_CHAIN
    { 343,	71,	1,	0,	3,	0,	0,	R600OpInfoBase + 164,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL },  // DOT_4
    { 342,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // DEFAULT
    { 341,	2,	1,	0,	2,	0,	0,	R600OpInfoBase + 162,	0,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // CUBE_r600_pseudo
    { 340,	2,	1,	0,	2,	0,	0,	R600OpInfoBase + 162,	0,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // CUBE_eg_pseudo
    { 339,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 159,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // CONTINUE_LOGICALZ_i32
    { 338,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 159,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // CONTINUE_LOGICALZ_f32
    { 337,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 159,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // CONTINUE_LOGICALNZ_i32
    { 336,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 159,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // CONTINUE_LOGICALNZ_f32
    { 335,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 157,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // CONTINUEC_i32
    { 334,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 157,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // CONTINUEC_f32
    { 333,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // CONTINUE
    { 332,	2,	1,	0,	1,	0,	0,	R600OpInfoBase + 160,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // CONST_COPY
    { 331,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 159,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // BREAK_LOGICALZ_i32
    { 330,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 159,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // BREAK_LOGICALZ_f32
    { 329,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 159,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // BREAK_LOGICALNZ_i32
    { 328,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 159,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // BREAK_LOGICALNZ_f32
    { 327,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 157,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // BREAKC_i32
    { 326,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 157,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // BREAKC_f32
    { 325,	0,	0,	0,	1,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // BREAK
    { 324,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 155,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // BRANCH_COND_i32
    { 323,	2,	0,	0,	1,	0,	0,	R600OpInfoBase + 155,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // BRANCH_COND_f32
    { 322,	1,	0,	0,	1,	0,	0,	R600OpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // BRANCH
    { 321,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 151,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_UBFX
    { 320,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 151,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SBFX
    { 319,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_VECREDUCE_UMIN
    { 318,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_VECREDUCE_UMAX
    { 317,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_VECREDUCE_SMIN
    { 316,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_VECREDUCE_SMAX
    { 315,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_VECREDUCE_XOR
    { 314,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_VECREDUCE_OR
    { 313,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_VECREDUCE_AND
    { 312,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_VECREDUCE_MUL
    { 311,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_VECREDUCE_ADD
    { 310,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_VECREDUCE_FMINIMUM
    { 309,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_VECREDUCE_FMAXIMUM
    { 308,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_VECREDUCE_FMIN
    { 307,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_VECREDUCE_FMAX
    { 306,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_VECREDUCE_FMUL
    { 305,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_VECREDUCE_FADD
    { 304,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 134,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_VECREDUCE_SEQ_FMUL
    { 303,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 134,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_VECREDUCE_SEQ_FADD
    { 302,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_UBSANTRAP
    { 301,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_DEBUGTRAP
    { 300,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_TRAP
    { 299,	3,	0,	0,	0,	0,	0,	R600OpInfoBase + 61,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_BZERO
    { 298,	4,	0,	0,	0,	0,	0,	R600OpInfoBase + 147,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_MEMSET
    { 297,	4,	0,	0,	0,	0,	0,	R600OpInfoBase + 147,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_MEMMOVE
    { 296,	3,	0,	0,	0,	0,	0,	R600OpInfoBase + 134,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_MEMCPY_INLINE
    { 295,	4,	0,	0,	0,	0,	0,	R600OpInfoBase + 147,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_MEMCPY
    { 294,	2,	0,	0,	0,	0,	0,	R600OpInfoBase + 145,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL },  // G_WRITE_REGISTER
    { 293,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL },  // G_READ_REGISTER
    { 292,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_STRICT_FLDEXP
    { 291,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_STRICT_FSQRT
    { 290,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 49,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_STRICT_FMA
    { 289,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_STRICT_FREM
    { 288,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_STRICT_FDIV
    { 287,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_STRICT_FMUL
    { 286,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_STRICT_FSUB
    { 285,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_STRICT_FADD
    { 284,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_STACKRESTORE
    { 283,	1,	1,	0,	0,	0,	0,	R600OpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_STACKSAVE
    { 282,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 72,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_DYN_STACKALLOC
    { 281,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_JUMP_TABLE
    { 280,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_BLOCK_ADDR
    { 279,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_ADDRSPACE_CAST
    { 278,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FNEARBYINT
    { 277,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FRINT
    { 276,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FFLOOR
    { 275,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FSQRT
    { 274,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FTANH
    { 273,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FSINH
    { 272,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FCOSH
    { 271,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FATAN2
    { 270,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FATAN
    { 269,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FASIN
    { 268,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FACOS
    { 267,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FTAN
    { 266,	3,	2,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FSINCOS
    { 265,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FSIN
    { 264,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FCOS
    { 263,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FCEIL
    { 262,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_BITREVERSE
    { 261,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_BSWAP
    { 260,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_CTPOP
    { 259,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_CTLZ_ZERO_UNDEF
    { 258,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_CTLZ
    { 257,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_CTTZ_ZERO_UNDEF
    { 256,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_CTTZ
    { 255,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 141,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_VECTOR_COMPRESS
    { 254,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_STEP_VECTOR
    { 253,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SPLAT_VECTOR
    { 252,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 137,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SHUFFLE_VECTOR
    { 251,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 134,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_EXTRACT_VECTOR_ELT
    { 250,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 130,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_INSERT_VECTOR_ELT
    { 249,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 61,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_EXTRACT_SUBVECTOR
    { 248,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 66,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_INSERT_SUBVECTOR
    { 247,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_VSCALE
    { 246,	3,	0,	0,	0,	0,	0,	R600OpInfoBase + 127,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // G_BRJT
    { 245,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // G_BR
    { 244,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_LLROUND
    { 243,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_LROUND
    { 242,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_ABS
    { 241,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_UMAX
    { 240,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_UMIN
    { 239,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_SMAX
    { 238,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_SMIN
    { 237,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_PTRMASK
    { 236,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_PTR_ADD
    { 235,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_SET_ROUNDING
    { 234,	1,	1,	0,	0,	0,	0,	R600OpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_GET_ROUNDING
    { 233,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_RESET_FPMODE
    { 232,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_SET_FPMODE
    { 231,	1,	1,	0,	0,	0,	0,	R600OpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_GET_FPMODE
    { 230,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_RESET_FPENV
    { 229,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_SET_FPENV
    { 228,	1,	1,	0,	0,	0,	0,	R600OpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_GET_FPENV
    { 227,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_FMAXIMUMNUM
    { 226,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_FMINIMUMNUM
    { 225,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_FMAXIMUM
    { 224,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_FMINIMUM
    { 223,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_FMAXNUM_IEEE
    { 222,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_FMINNUM_IEEE
    { 221,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_FMAXNUM
    { 220,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_FMINNUM
    { 219,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FCANONICALIZE
    { 218,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 101,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_IS_FPCLASS
    { 217,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FCOPYSIGN
    { 216,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FABS
    { 215,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FPTOUI_SAT
    { 214,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FPTOSI_SAT
    { 213,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_UITOFP
    { 212,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SITOFP
    { 211,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FPTOUI
    { 210,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FPTOSI
    { 209,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FPTRUNC
    { 208,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FPEXT
    { 207,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FNEG
    { 206,	3,	2,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FFREXP
    { 205,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FLDEXP
    { 204,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FLOG10
    { 203,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FLOG2
    { 202,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FLOG
    { 201,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FEXP10
    { 200,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FEXP2
    { 199,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FEXP
    { 198,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FPOWI
    { 197,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FPOW
    { 196,	3,	2,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FMODF
    { 195,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FREM
    { 194,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FDIV
    { 193,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 49,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FMAD
    { 192,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 49,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FMA
    { 191,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_FMUL
    { 190,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FSUB
    { 189,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_FADD
    { 188,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_UDIVFIXSAT
    { 187,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SDIVFIXSAT
    { 186,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_UDIVFIX
    { 185,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SDIVFIX
    { 184,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_UMULFIXSAT
    { 183,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_SMULFIXSAT
    { 182,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_UMULFIX
    { 181,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_SMULFIX
    { 180,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SSHLSAT
    { 179,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_USHLSAT
    { 178,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SSUBSAT
    { 177,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_USUBSAT
    { 176,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_SADDSAT
    { 175,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_UADDSAT
    { 174,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_SMULH
    { 173,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_UMULH
    { 172,	4,	2,	0,	0,	0,	0,	R600OpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_SMULO
    { 171,	4,	2,	0,	0,	0,	0,	R600OpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_UMULO
    { 170,	5,	2,	0,	0,	0,	0,	R600OpInfoBase + 118,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SSUBE
    { 169,	4,	2,	0,	0,	0,	0,	R600OpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SSUBO
    { 168,	5,	2,	0,	0,	0,	0,	R600OpInfoBase + 118,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SADDE
    { 167,	4,	2,	0,	0,	0,	0,	R600OpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_SADDO
    { 166,	5,	2,	0,	0,	0,	0,	R600OpInfoBase + 118,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_USUBE
    { 165,	4,	2,	0,	0,	0,	0,	R600OpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_USUBO
    { 164,	5,	2,	0,	0,	0,	0,	R600OpInfoBase + 118,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_UADDE
    { 163,	4,	2,	0,	0,	0,	0,	R600OpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_UADDO
    { 162,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SELECT
    { 161,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 115,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_UCMP
    { 160,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 115,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SCMP
    { 159,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 111,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FCMP
    { 158,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 111,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_ICMP
    { 157,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_ROTL
    { 156,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_ROTR
    { 155,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 107,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FSHR
    { 154,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 107,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FSHL
    { 153,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_ASHR
    { 152,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_LSHR
    { 151,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SHL
    { 150,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_ZEXT
    { 149,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 43,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SEXT_INREG
    { 148,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SEXT
    { 147,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 101,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_VAARG
    { 146,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_VASTART
    { 145,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FCONSTANT
    { 144,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_CONSTANT
    { 143,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_TRUNC_USAT_U
    { 142,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_TRUNC_SSAT_U
    { 141,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_TRUNC_SSAT_S
    { 140,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_TRUNC
    { 139,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_ANYEXT
    { 138,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL },  // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
    { 137,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL },  // G_INTRINSIC_CONVERGENT
    { 136,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_INTRINSIC_W_SIDE_EFFECTS
    { 135,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // G_INTRINSIC
    { 134,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // G_INVOKE_REGION_START
    { 133,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // G_BRINDIRECT
    { 132,	2,	0,	0,	0,	0,	0,	R600OpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL },  // G_BRCOND
    { 131,	4,	0,	0,	0,	0,	0,	R600OpInfoBase + 97,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_PREFETCH
    { 130,	2,	0,	0,	0,	0,	0,	R600OpInfoBase + 24,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_FENCE
    { 129,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_USUB_SAT
    { 128,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_USUB_COND
    { 127,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_UDEC_WRAP
    { 126,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_UINC_WRAP
    { 125,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_FMINIMUM
    { 124,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_FMAXIMUM
    { 123,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_FMIN
    { 122,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_FMAX
    { 121,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_FSUB
    { 120,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_FADD
    { 119,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_UMIN
    { 118,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_UMAX
    { 117,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_MIN
    { 116,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_MAX
    { 115,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_XOR
    { 114,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_OR
    { 113,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_NAND
    { 112,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_AND
    { 111,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_SUB
    { 110,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_ADD
    { 109,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMICRMW_XCHG
    { 108,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMIC_CMPXCHG
    { 107,	5,	2,	0,	0,	0,	0,	R600OpInfoBase + 85,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_ATOMIC_CMPXCHG_WITH_SUCCESS
    { 106,	5,	1,	0,	0,	0,	0,	R600OpInfoBase + 80,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_INDEXED_STORE
    { 105,	2,	0,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // G_STORE
    { 104,	5,	2,	0,	0,	0,	0,	R600OpInfoBase + 75,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // G_INDEXED_ZEXTLOAD
    { 103,	5,	2,	0,	0,	0,	0,	R600OpInfoBase + 75,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // G_INDEXED_SEXTLOAD
    { 102,	5,	2,	0,	0,	0,	0,	R600OpInfoBase + 75,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // G_INDEXED_LOAD
    { 101,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // G_ZEXTLOAD
    { 100,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // G_SEXTLOAD
    { 99,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // G_LOAD
    { 98,	1,	1,	0,	0,	0,	0,	R600OpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_READSTEADYCOUNTER
    { 97,	1,	1,	0,	0,	0,	0,	R600OpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // G_READCYCLECOUNTER
    { 96,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_INTRINSIC_ROUNDEVEN
    { 95,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_INTRINSIC_LLRINT
    { 94,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_INTRINSIC_LRINT
    { 93,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_INTRINSIC_ROUND
    { 92,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_INTRINSIC_TRUNC
    { 91,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 72,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_INTRINSIC_FPTRUNC_ROUND
    { 90,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_CONSTANT_FOLD_BARRIER
    { 89,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FREEZE
    { 88,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_BITCAST
    { 87,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_INTTOPTR
    { 86,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_PTRTOINT
    { 85,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // G_CONCAT_VECTORS
    { 84,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // G_BUILD_VECTOR_TRUNC
    { 83,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // G_BUILD_VECTOR
    { 82,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // G_MERGE_VALUES
    { 81,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 66,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_INSERT
    { 80,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // G_UNMERGE_VALUES
    { 79,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 61,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_EXTRACT
    { 78,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_CONSTANT_POOL
    { 77,	5,	1,	0,	0,	0,	0,	R600OpInfoBase + 56,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_PTRAUTH_GLOBAL_VALUE
    { 76,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_GLOBAL_VALUE
    { 75,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_FRAME_INDEX
    { 74,	1,	1,	0,	0,	0,	0,	R600OpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // G_PHI
    { 73,	1,	1,	0,	0,	0,	0,	R600OpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_IMPLICIT_DEF
    { 72,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SAVGCEIL
    { 71,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SAVGFLOOR
    { 70,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_UAVGCEIL
    { 69,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_UAVGFLOOR
    { 68,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_ABDU
    { 67,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_ABDS
    { 66,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_XOR
    { 65,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_OR
    { 64,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_AND
    { 63,	4,	2,	0,	0,	0,	0,	R600OpInfoBase + 49,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_UDIVREM
    { 62,	4,	2,	0,	0,	0,	0,	R600OpInfoBase + 49,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SDIVREM
    { 61,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_UREM
    { 60,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SREM
    { 59,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_UDIV
    { 58,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SDIV
    { 57,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_MUL
    { 56,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_SUB
    { 55,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // G_ADD
    { 54,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 43,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_ASSERT_ALIGN
    { 53,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 43,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_ASSERT_ZEXT
    { 52,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 43,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // G_ASSERT_SEXT
    { 51,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL },  // CONVERGENCECTRL_GLUE
    { 50,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 13,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL },  // CONVERGENCECTRL_LOOP
    { 49,	1,	1,	0,	0,	0,	0,	R600OpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL },  // CONVERGENCECTRL_ANCHOR
    { 48,	1,	1,	0,	0,	0,	0,	R600OpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL },  // CONVERGENCECTRL_ENTRY
    { 47,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // RELOC_NONE
    { 46,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // JUMP_TABLE_DEBUG_INFO
    { 45,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // MEMBARRIER
    { 44,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // FAKE_USE
    { 43,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // ICALL_BRANCH_FUNNEL
    { 42,	3,	0,	0,	0,	0,	0,	R600OpInfoBase + 40,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // anonymous_14469
    { 41,	2,	0,	0,	0,	0,	0,	R600OpInfoBase + 38,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // anonymous_14468
    { 40,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // PATCHABLE_TAIL_CALL
    { 39,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // PATCHABLE_FUNCTION_EXIT
    { 38,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // PATCHABLE_RET
    { 37,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // PATCHABLE_FUNCTION_ENTER
    { 36,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // PATCHABLE_OP
    { 35,	1,	1,	0,	0,	0,	0,	R600OpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // FAULTING_OP
    { 34,	2,	0,	0,	0,	0,	0,	R600OpInfoBase + 36,	0,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // LOCAL_ESCAPE
    { 33,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // STATEPOINT
    { 32,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 33,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // anonymous_14467
    { 31,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // PREALLOCATED_SETUP
    { 30,	1,	1,	0,	0,	0,	0,	R600OpInfoBase + 32,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL },  // anonymous_14196
    { 29,	6,	1,	0,	0,	0,	0,	R600OpInfoBase + 26,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // PATCHPOINT
    { 28,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // FENTRY_CALL
    { 27,	2,	0,	0,	0,	0,	0,	R600OpInfoBase + 24,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // STACKMAP
    { 26,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 22,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // ARITH_FENCE
    { 25,	4,	0,	0,	0,	0,	0,	R600OpInfoBase + 18,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // PSEUDO_PROBE
    { 24,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // LIFETIME_END
    { 23,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // LIFETIME_START
    { 22,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // BUNDLE
    { 21,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 15,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // COPY_LANEMASK
    { 20,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 13,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // COPY
    { 19,	2,	1,	0,	0,	0,	0,	R600OpInfoBase + 13,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // REG_SEQUENCE
    { 18,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // DBG_LABEL
    { 17,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // DBG_PHI
    { 16,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // DBG_INSTR_REF
    { 15,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // DBG_VALUE_LIST
    { 14,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // DBG_VALUE
    { 13,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 2,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // COPY_TO_REGCLASS
    { 12,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 9,	0,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // SUBREG_TO_REG
    { 11,	1,	1,	0,	0,	0,	0,	R600OpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // INIT_UNDEF
    { 10,	1,	1,	0,	0,	0,	0,	R600OpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // IMPLICIT_DEF
    { 9,	4,	1,	0,	0,	0,	0,	R600OpInfoBase + 5,	0,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // INSERT_SUBREG
    { 8,	3,	1,	0,	0,	0,	0,	R600OpInfoBase + 2,	0,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // EXTRACT_SUBREG
    { 7,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // KILL
    { 6,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL },  // ANNOTATION_LABEL
    { 5,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL },  // GC_LABEL
    { 4,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL },  // EH_LABEL
    { 3,	1,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL },  // CFI_INSTRUCTION
    { 2,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // INLINEASM_BR
    { 1,	0,	0,	0,	0,	0,	0,	R600OpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // INLINEASM
    { 0,	1,	1,	0,	0,	0,	0,	R600OpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // PHI
  }, {
    /* 0 */
  }, {
    0
  }, {
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 1 */
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 15 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 18 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
    /* 24 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 26 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 32 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 33 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 38 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 40 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 54 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 70 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 75 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 80 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 85 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 118 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 141 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 145 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 151 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 155 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 157 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 159 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 160 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 162 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 164 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 235 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 237 */ { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 241 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 244 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 247 */ { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 251 */ { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 255 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 259 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 266 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 287 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 301 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 320 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 329 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 336 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 345 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 350 */ { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 355 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 357 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 366 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 376 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 383 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 395 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 408 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 411 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 413 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 415 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 417 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 421 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 424 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 427 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 430 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 449 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 453 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 457 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 461 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
  }
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char R600InstrNameData[] = {
  /* 0 */ "CF_TC_R600\000"
  /* 11 */ "CF_VC_R600\000"
  /* 22 */ "CF_END_R600\000"
  /* 34 */ "CF_ELSE_R600\000"
  /* 47 */ "CF_PUSH_ELSE_R600\000"
  /* 65 */ "CF_CONTINUE_R600\000"
  /* 82 */ "FNEG_R600\000"
  /* 92 */ "LOOP_BREAK_R600\000"
  /* 108 */ "CF_JUMP_R600\000"
  /* 121 */ "END_LOOP_R600\000"
  /* 135 */ "WHILE_LOOP_R600\000"
  /* 151 */ "POP_R600\000"
  /* 160 */ "FABS_R600\000"
  /* 170 */ "CF_CALL_FS_R600\000"
  /* 186 */ "DOT4_r600\000"
  /* 196 */ "MULADD_r600\000"
  /* 208 */ "LOG_CLAMPED_r600\000"
  /* 225 */ "RECIP_CLAMPED_r600\000"
  /* 244 */ "RECIPSQRT_CLAMPED_r600\000"
  /* 267 */ "CNDE_r600\000"
  /* 277 */ "MULADD_IEEE_r600\000"
  /* 294 */ "LOG_IEEE_r600\000"
  /* 308 */ "RECIP_IEEE_r600\000"
  /* 324 */ "EXP_IEEE_r600\000"
  /* 338 */ "RECIPSQRT_IEEE_r600\000"
  /* 358 */ "CNDGE_r600\000"
  /* 369 */ "LSHL_r600\000"
  /* 379 */ "SIN_r600\000"
  /* 388 */ "ASHR_r600\000"
  /* 398 */ "LSHR_r600\000"
  /* 408 */ "COS_r600\000"
  /* 417 */ "CNDGT_r600\000"
  /* 428 */ "MUL_LIT_r600\000"
  /* 441 */ "UINT_TO_FLT_r600\000"
  /* 458 */ "MULHI_UINT_r600\000"
  /* 474 */ "MULLO_UINT_r600\000"
  /* 490 */ "FLT_TO_UINT_r600\000"
  /* 507 */ "RECIP_UINT_r600\000"
  /* 523 */ "MULHI_INT_r600\000"
  /* 538 */ "MULLO_INT_r600\000"
  /* 553 */ "FLT_TO_INT_r600\000"
  /* 569 */ "SIN_r700\000"
  /* 578 */ "COS_r700\000"
  /* 587 */ "G_FLOG10\000"
  /* 596 */ "G_FEXP10\000"
  /* 605 */ "SETGE_DX10\000"
  /* 616 */ "SETNE_DX10\000"
  /* 627 */ "SETE_DX10\000"
  /* 637 */ "MIN_DX10\000"
  /* 646 */ "SETGT_DX10\000"
  /* 657 */ "MAX_DX10\000"
  /* 666 */ "INTERP_LOAD_P0\000"
  /* 681 */ "RAT_STORE_DWORD32\000"
  /* 699 */ "MOV_IMM_F32\000"
  /* 711 */ "MOV_IMM_I32\000"
  /* 723 */ "FLT16_TO_FLT32\000"
  /* 738 */ "CONTINUEC_f32\000"
  /* 752 */ "IFC_f32\000"
  /* 760 */ "BREAKC_f32\000"
  /* 771 */ "BRANCH_COND_f32\000"
  /* 787 */ "CONTINUE_LOGICALZ_f32\000"
  /* 809 */ "IF_LOGICALZ_f32\000"
  /* 825 */ "BREAK_LOGICALZ_f32\000"
  /* 844 */ "CONTINUE_LOGICALNZ_f32\000"
  /* 867 */ "IF_LOGICALNZ_f32\000"
  /* 884 */ "BREAK_LOGICALNZ_f32\000"
  /* 904 */ "CONTINUEC_i32\000"
  /* 918 */ "IFC_i32\000"
  /* 926 */ "BREAKC_i32\000"
  /* 937 */ "BRANCH_COND_i32\000"
  /* 953 */ "CONTINUE_LOGICALZ_i32\000"
  /* 975 */ "IF_LOGICALZ_i32\000"
  /* 991 */ "BREAK_LOGICALZ_i32\000"
  /* 1010 */ "CONTINUE_LOGICALNZ_i32\000"
  /* 1033 */ "IF_LOGICALNZ_i32\000"
  /* 1050 */ "BREAK_LOGICALNZ_i32\000"
  /* 1070 */ "G_FLOG2\000"
  /* 1078 */ "G_FATAN2\000"
  /* 1087 */ "G_FEXP2\000"
  /* 1095 */ "R600_EXTRACT_ELT_V2\000"
  /* 1115 */ "R600_INSERT_ELT_V2\000"
  /* 1134 */ "MULHI_UINT_cm24\000"
  /* 1150 */ "MULHI_INT_cm24\000"
  /* 1165 */ "RAT_STORE_DWORD64\000"
  /* 1183 */ "R600_EXTRACT_ELT_V4\000"
  /* 1203 */ "R600_INSERT_ELT_V4\000"
  /* 1222 */ "DOT_4\000"
  /* 1228 */ "FLT32_TO_FLT16\000"
  /* 1243 */ "RAT_STORE_DWORD128\000"
  /* 1262 */ "G_FMA\000"
  /* 1268 */ "G_STRICT_FMA\000"
  /* 1281 */ "TEX_SAMPLE_C_LB\000"
  /* 1297 */ "TEX_SAMPLE_LB\000"
  /* 1311 */ "G_FSUB\000"
  /* 1318 */ "G_STRICT_FSUB\000"
  /* 1332 */ "G_ATOMICRMW_FSUB\000"
  /* 1349 */ "G_SUB\000"
  /* 1355 */ "LDS_SUB\000"
  /* 1363 */ "G_ATOMICRMW_SUB\000"
  /* 1379 */ "G_INTRINSIC\000"
  /* 1391 */ "ENDFUNC\000"
  /* 1399 */ "G_FPTRUNC\000"
  /* 1409 */ "G_INTRINSIC_TRUNC\000"
  /* 1427 */ "G_TRUNC\000"
  /* 1435 */ "G_BUILD_VECTOR_TRUNC\000"
  /* 1456 */ "G_DYN_STACKALLOC\000"
  /* 1473 */ "TEX_SAMPLE_C\000"
  /* 1486 */ "G_FMAD\000"
  /* 1493 */ "G_INDEXED_SEXTLOAD\000"
  /* 1512 */ "G_SEXTLOAD\000"
  /* 1523 */ "G_INDEXED_ZEXTLOAD\000"
  /* 1542 */ "G_ZEXTLOAD\000"
  /* 1553 */ "INTERP_VEC_LOAD\000"
  /* 1569 */ "G_INDEXED_LOAD\000"
  /* 1584 */ "G_LOAD\000"
  /* 1591 */ "PAD\000"
  /* 1595 */ "G_VECREDUCE_FADD\000"
  /* 1612 */ "G_FADD\000"
  /* 1619 */ "G_VECREDUCE_SEQ_FADD\000"
  /* 1640 */ "G_STRICT_FADD\000"
  /* 1654 */ "G_ATOMICRMW_FADD\000"
  /* 1671 */ "G_VECREDUCE_ADD\000"
  /* 1687 */ "G_ADD\000"
  /* 1693 */ "G_PTR_ADD\000"
  /* 1703 */ "LDS_ADD\000"
  /* 1711 */ "G_ATOMICRMW_ADD\000"
  /* 1727 */ "TEX_LD\000"
  /* 1734 */ "G_ATOMICRMW_NAND\000"
  /* 1751 */ "G_VECREDUCE_AND\000"
  /* 1767 */ "G_AND\000"
  /* 1773 */ "LDS_AND\000"
  /* 1781 */ "G_ATOMICRMW_AND\000"
  /* 1797 */ "LIFETIME_END\000"
  /* 1810 */ "G_BRCOND\000"
  /* 1819 */ "G_ATOMICRMW_USUB_COND\000"
  /* 1841 */ "JUMP_COND\000"
  /* 1851 */ "G_LLROUND\000"
  /* 1861 */ "G_LROUND\000"
  /* 1870 */ "G_INTRINSIC_ROUND\000"
  /* 1888 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
  /* 1914 */ "LOAD_STACK_GUARD\000"
  /* 1931 */ "TXD\000"
  /* 1935 */ "PSEUDO_PROBE\000"
  /* 1948 */ "G_SSUBE\000"
  /* 1956 */ "G_USUBE\000"
  /* 1964 */ "G_FENCE\000"
  /* 1972 */ "ARITH_FENCE\000"
  /* 1984 */ "REG_SEQUENCE\000"
  /* 1997 */ "G_SADDE\000"
  /* 2005 */ "G_UADDE\000"
  /* 2013 */ "G_GET_FPMODE\000"
  /* 2026 */ "G_RESET_FPMODE\000"
  /* 2041 */ "G_SET_FPMODE\000"
  /* 2054 */ "MUL_IEEE\000"
  /* 2063 */ "G_FMINNUM_IEEE\000"
  /* 2078 */ "G_FMAXNUM_IEEE\000"
  /* 2093 */ "SGE\000"
  /* 2097 */ "PRED_SETGE\000"
  /* 2108 */ "G_VSCALE\000"
  /* 2117 */ "G_JUMP_TABLE\000"
  /* 2130 */ "BUNDLE\000"
  /* 2137 */ "TEX_SAMPLE\000"
  /* 2148 */ "RNDNE\000"
  /* 2154 */ "G_MEMCPY_INLINE\000"
  /* 2170 */ "RELOC_NONE\000"
  /* 2181 */ "SNE\000"
  /* 2185 */ "PRED_SETNE\000"
  /* 2196 */ "LOCAL_ESCAPE\000"
  /* 2209 */ "CF_ALU_PUSH_BEFORE\000"
  /* 2228 */ "G_STACKRESTORE\000"
  /* 2243 */ "G_INDEXED_STORE\000"
  /* 2259 */ "G_STORE\000"
  /* 2267 */ "ELSE\000"
  /* 2272 */ "G_BITREVERSE\000"
  /* 2285 */ "FETCH_CLAUSE\000"
  /* 2298 */ "ALU_CLAUSE\000"
  /* 2309 */ "FAKE_USE\000"
  /* 2318 */ "PRED_SETE\000"
  /* 2328 */ "LDS_BYTE_WRITE\000"
  /* 2343 */ "MASK_WRITE\000"
  /* 2354 */ "LDS_WRITE\000"
  /* 2364 */ "LDS_SHORT_WRITE\000"
  /* 2380 */ "DBG_VALUE\000"
  /* 2390 */ "G_GLOBAL_VALUE\000"
  /* 2405 */ "G_PTRAUTH_GLOBAL_VALUE\000"
  /* 2428 */ "CONVERGENCECTRL_GLUE\000"
  /* 2449 */ "CF_ALU_CONTINUE\000"
  /* 2465 */ "G_STACKSAVE\000"
  /* 2477 */ "G_MEMMOVE\000"
  /* 2487 */ "G_FREEZE\000"
  /* 2496 */ "G_FCANONICALIZE\000"
  /* 2512 */ "G_FMODF\000"
  /* 2520 */ "G_CTLZ_ZERO_UNDEF\000"
  /* 2538 */ "G_CTTZ_ZERO_UNDEF\000"
  /* 2556 */ "INIT_UNDEF\000"
  /* 2567 */ "G_IMPLICIT_DEF\000"
  /* 2582 */ "DBG_INSTR_REF\000"
  /* 2596 */ "ENDIF\000"
  /* 2602 */ "TEX_VTX_CONSTBUF\000"
  /* 2619 */ "TEX_VTX_TEXBUF\000"
  /* 2634 */ "G_FNEG\000"
  /* 2641 */ "EXTRACT_SUBREG\000"
  /* 2656 */ "INSERT_SUBREG\000"
  /* 2670 */ "G_SEXT_INREG\000"
  /* 2683 */ "SUBREG_TO_REG\000"
  /* 2697 */ "CF_TC_EG\000"
  /* 2706 */ "CF_VC_EG\000"
  /* 2715 */ "CF_END_EG\000"
  /* 2725 */ "CF_ELSE_EG\000"
  /* 2736 */ "CF_CONTINUE_EG\000"
  /* 2751 */ "CF_PUSH_EG\000"
  /* 2762 */ "LOOP_BREAK_EG\000"
  /* 2776 */ "CF_JUMP_EG\000"
  /* 2787 */ "END_LOOP_EG\000"
  /* 2799 */ "WHILE_LOOP_EG\000"
  /* 2813 */ "POP_EG\000"
  /* 2820 */ "CF_CALL_FS_EG\000"
  /* 2834 */ "G_ATOMIC_CMPXCHG\000"
  /* 2851 */ "LDS_WRXCHG\000"
  /* 2862 */ "G_ATOMICRMW_XCHG\000"
  /* 2879 */ "G_GET_ROUNDING\000"
  /* 2894 */ "G_SET_ROUNDING\000"
  /* 2909 */ "G_FLOG\000"
  /* 2916 */ "G_VAARG\000"
  /* 2924 */ "PREALLOCATED_ARG\000"
  /* 2941 */ "TEX_SAMPLE_C_G\000"
  /* 2956 */ "TEX_SAMPLE_G\000"
  /* 2969 */ "BRANCH\000"
  /* 2976 */ "G_PREFETCH\000"
  /* 2987 */ "ENDSWITCH\000"
  /* 2997 */ "G_SMULH\000"
  /* 3005 */ "G_UMULH\000"
  /* 3013 */ "G_FTANH\000"
  /* 3021 */ "G_FSINH\000"
  /* 3029 */ "G_FCOSH\000"
  /* 3037 */ "TEX_GET_GRADIENTS_H\000"
  /* 3057 */ "TEX_SET_GRADIENTS_H\000"
  /* 3077 */ "DBG_PHI\000"
  /* 3085 */ "G_FPTOSI\000"
  /* 3094 */ "G_FPTOUI\000"
  /* 3103 */ "G_FPOWI\000"
  /* 3111 */ "CF_ALU_BREAK\000"
  /* 3124 */ "COPY_LANEMASK\000"
  /* 3138 */ "G_PTRMASK\000"
  /* 3148 */ "GC_LABEL\000"
  /* 3157 */ "DBG_LABEL\000"
  /* 3167 */ "EH_LABEL\000"
  /* 3176 */ "ANNOTATION_LABEL\000"
  /* 3193 */ "ICALL_BRANCH_FUNNEL\000"
  /* 3213 */ "G_FSHL\000"
  /* 3220 */ "G_SHL\000"
  /* 3226 */ "G_FCEIL\000"
  /* 3234 */ "G_SAVGCEIL\000"
  /* 3245 */ "G_UAVGCEIL\000"
  /* 3256 */ "PATCHABLE_TAIL_CALL\000"
  /* 3276 */ "PATCHABLE_TYPED_EVENT_CALL\000"
  /* 3303 */ "PATCHABLE_EVENT_CALL\000"
  /* 3324 */ "FENTRY_CALL\000"
  /* 3336 */ "KILL\000"
  /* 3341 */ "G_CONSTANT_POOL\000"
  /* 3357 */ "G_ROTL\000"
  /* 3364 */ "G_VECREDUCE_FMUL\000"
  /* 3381 */ "G_FMUL\000"
  /* 3388 */ "G_VECREDUCE_SEQ_FMUL\000"
  /* 3409 */ "G_STRICT_FMUL\000"
  /* 3423 */ "G_VECREDUCE_MUL\000"
  /* 3439 */ "G_MUL\000"
  /* 3445 */ "TEX_SAMPLE_C_L\000"
  /* 3460 */ "TEX_SAMPLE_L\000"
  /* 3473 */ "CF_END_CM\000"
  /* 3483 */ "G_FREM\000"
  /* 3490 */ "G_STRICT_FREM\000"
  /* 3504 */ "G_SREM\000"
  /* 3511 */ "G_UREM\000"
  /* 3518 */ "G_SDIVREM\000"
  /* 3528 */ "G_UDIVREM\000"
  /* 3538 */ "INLINEASM\000"
  /* 3548 */ "G_VECREDUCE_FMINIMUM\000"
  /* 3569 */ "G_FMINIMUM\000"
  /* 3580 */ "G_ATOMICRMW_FMINIMUM\000"
  /* 3601 */ "G_VECREDUCE_FMAXIMUM\000"
  /* 3622 */ "G_FMAXIMUM\000"
  /* 3633 */ "G_ATOMICRMW_FMAXIMUM\000"
  /* 3654 */ "G_FMINIMUMNUM\000"
  /* 3668 */ "G_FMAXIMUMNUM\000"
  /* 3682 */ "G_FMINNUM\000"
  /* 3692 */ "G_FMAXNUM\000"
  /* 3702 */ "G_FATAN\000"
  /* 3710 */ "G_FTAN\000"
  /* 3717 */ "G_INTRINSIC_ROUNDEVEN\000"
  /* 3739 */ "G_ASSERT_ALIGN\000"
  /* 3754 */ "G_FCOPYSIGN\000"
  /* 3766 */ "DUMMY_CHAIN\000"
  /* 3778 */ "ENDMAIN\000"
  /* 3786 */ "G_VECREDUCE_FMIN\000"
  /* 3803 */ "G_ATOMICRMW_FMIN\000"
  /* 3820 */ "G_VECREDUCE_SMIN\000"
  /* 3837 */ "G_SMIN\000"
  /* 3844 */ "G_VECREDUCE_UMIN\000"
  /* 3861 */ "G_UMIN\000"
  /* 3868 */ "G_ATOMICRMW_UMIN\000"
  /* 3885 */ "G_ATOMICRMW_MIN\000"
  /* 3901 */ "G_FASIN\000"
  /* 3909 */ "G_FSIN\000"
  /* 3916 */ "CFI_INSTRUCTION\000"
  /* 3932 */ "RETURN\000"
  /* 3939 */ "RAT_ATOMIC_RSUB_RTN\000"
  /* 3959 */ "RAT_ATOMIC_SUB_RTN\000"
  /* 3978 */ "RAT_ATOMIC_ADD_RTN\000"
  /* 3997 */ "RAT_ATOMIC_AND_RTN\000"
  /* 4016 */ "RAT_ATOMIC_XOR_RTN\000"
  /* 4035 */ "RAT_ATOMIC_OR_RTN\000"
  /* 4053 */ "RAT_ATOMIC_DEC_UINT_RTN\000"
  /* 4077 */ "RAT_ATOMIC_INC_UINT_RTN\000"
  /* 4101 */ "RAT_ATOMIC_MIN_UINT_RTN\000"
  /* 4125 */ "RAT_ATOMIC_MAX_UINT_RTN\000"
  /* 4149 */ "RAT_ATOMIC_CMPXCHG_INT_RTN\000"
  /* 4176 */ "RAT_ATOMIC_XCHG_INT_RTN\000"
  /* 4200 */ "RAT_ATOMIC_MIN_INT_RTN\000"
  /* 4223 */ "RAT_ATOMIC_MAX_INT_RTN\000"
  /* 4246 */ "RETDYN\000"
  /* 4253 */ "G_SSUBO\000"
  /* 4261 */ "G_USUBO\000"
  /* 4269 */ "G_SADDO\000"
  /* 4277 */ "G_UADDO\000"
  /* 4285 */ "TEX_GET_TEXTURE_RESINFO\000"
  /* 4309 */ "JUMP_TABLE_DEBUG_INFO\000"
  /* 4331 */ "G_SMULO\000"
  /* 4339 */ "G_UMULO\000"
  /* 4347 */ "G_BZERO\000"
  /* 4355 */ "STACKMAP\000"
  /* 4364 */ "G_DEBUGTRAP\000"
  /* 4376 */ "G_UBSANTRAP\000"
  /* 4388 */ "G_TRAP\000"
  /* 4395 */ "G_ATOMICRMW_UDEC_WRAP\000"
  /* 4417 */ "G_ATOMICRMW_UINC_WRAP\000"
  /* 4439 */ "G_BSWAP\000"
  /* 4447 */ "G_SITOFP\000"
  /* 4456 */ "G_UITOFP\000"
  /* 4465 */ "G_FCMP\000"
  /* 4472 */ "G_ICMP\000"
  /* 4479 */ "G_SCMP\000"
  /* 4486 */ "G_UCMP\000"
  /* 4493 */ "JUMP\000"
  /* 4498 */ "ENDLOOP\000"
  /* 4506 */ "WHILELOOP\000"
  /* 4516 */ "CONVERGENCECTRL_LOOP\000"
  /* 4537 */ "G_CTPOP\000"
  /* 4545 */ "PATCHABLE_OP\000"
  /* 4558 */ "FAULTING_OP\000"
  /* 4570 */ "PREALLOCATED_SETUP\000"
  /* 4589 */ "G_FLDEXP\000"
  /* 4598 */ "G_STRICT_FLDEXP\000"
  /* 4614 */ "G_FEXP\000"
  /* 4621 */ "G_FFREXP\000"
  /* 4630 */ "G_BR\000"
  /* 4635 */ "INLINEASM_BR\000"
  /* 4648 */ "G_BLOCK_ADDR\000"
  /* 4661 */ "MOV_IMM_GLOBAL_ADDR\000"
  /* 4681 */ "MEMBARRIER\000"
  /* 4692 */ "G_CONSTANT_FOLD_BARRIER\000"
  /* 4716 */ "GROUP_BARRIER\000"
  /* 4730 */ "CF_ALU_ELSE_AFTER\000"
  /* 4748 */ "CF_ALU_POP_AFTER\000"
  /* 4765 */ "PATCHABLE_FUNCTION_ENTER\000"
  /* 4790 */ "G_READCYCLECOUNTER\000"
  /* 4809 */ "G_READSTEADYCOUNTER\000"
  /* 4829 */ "G_READ_REGISTER\000"
  /* 4845 */ "G_WRITE_REGISTER\000"
  /* 4862 */ "G_ASHR\000"
  /* 4869 */ "G_FSHR\000"
  /* 4876 */ "G_LSHR\000"
  /* 4883 */ "CONVERGENCECTRL_ANCHOR\000"
  /* 4906 */ "RAT_MSKOR\000"
  /* 4916 */ "G_FFLOOR\000"
  /* 4925 */ "G_SAVGFLOOR\000"
  /* 4937 */ "G_UAVGFLOOR\000"
  /* 4949 */ "G_EXTRACT_SUBVECTOR\000"
  /* 4969 */ "G_INSERT_SUBVECTOR\000"
  /* 4988 */ "G_BUILD_VECTOR\000"
  /* 5003 */ "G_SHUFFLE_VECTOR\000"
  /* 5020 */ "G_STEP_VECTOR\000"
  /* 5034 */ "G_SPLAT_VECTOR\000"
  /* 5049 */ "G_VECREDUCE_XOR\000"
  /* 5065 */ "G_XOR\000"
  /* 5071 */ "LDS_XOR\000"
  /* 5079 */ "G_ATOMICRMW_XOR\000"
  /* 5095 */ "G_VECREDUCE_OR\000"
  /* 5110 */ "G_OR\000"
  /* 5115 */ "LDS_OR\000"
  /* 5122 */ "G_ATOMICRMW_OR\000"
  /* 5137 */ "G_ROTR\000"
  /* 5144 */ "TEX_LDPTR\000"
  /* 5154 */ "G_INTTOPTR\000"
  /* 5165 */ "G_FABS\000"
  /* 5172 */ "G_ABS\000"
  /* 5178 */ "G_ABDS\000"
  /* 5185 */ "G_UNMERGE_VALUES\000"
  /* 5202 */ "G_MERGE_VALUES\000"
  /* 5217 */ "LITERALS\000"
  /* 5226 */ "G_FACOS\000"
  /* 5234 */ "G_FCOS\000"
  /* 5241 */ "G_FSINCOS\000"
  /* 5251 */ "G_CONCAT_VECTORS\000"
  /* 5268 */ "COPY_TO_REGCLASS\000"
  /* 5285 */ "G_IS_FPCLASS\000"
  /* 5298 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
  /* 5328 */ "G_VECTOR_COMPRESS\000"
  /* 5346 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
  /* 5373 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
  /* 5411 */ "G_TRUNC_SSAT_S\000"
  /* 5426 */ "G_SSUBSAT\000"
  /* 5436 */ "G_USUBSAT\000"
  /* 5446 */ "G_SADDSAT\000"
  /* 5456 */ "G_UADDSAT\000"
  /* 5466 */ "G_SSHLSAT\000"
  /* 5476 */ "G_USHLSAT\000"
  /* 5486 */ "G_SMULFIXSAT\000"
  /* 5499 */ "G_UMULFIXSAT\000"
  /* 5512 */ "G_SDIVFIXSAT\000"
  /* 5525 */ "G_UDIVFIXSAT\000"
  /* 5538 */ "G_ATOMICRMW_USUB_SAT\000"
  /* 5559 */ "G_FPTOSI_SAT\000"
  /* 5572 */ "G_FPTOUI_SAT\000"
  /* 5585 */ "FRACT\000"
  /* 5591 */ "G_EXTRACT\000"
  /* 5601 */ "G_SELECT\000"
  /* 5610 */ "G_BRINDIRECT\000"
  /* 5623 */ "RAT_ATOMIC_RSUB_NORET\000"
  /* 5645 */ "RAT_ATOMIC_SUB_NORET\000"
  /* 5666 */ "RAT_ATOMIC_ADD_NORET\000"
  /* 5687 */ "RAT_ATOMIC_AND_NORET\000"
  /* 5708 */ "RAT_ATOMIC_XOR_NORET\000"
  /* 5729 */ "RAT_ATOMIC_OR_NORET\000"
  /* 5749 */ "RAT_ATOMIC_DEC_UINT_NORET\000"
  /* 5775 */ "RAT_ATOMIC_INC_UINT_NORET\000"
  /* 5801 */ "RAT_ATOMIC_MIN_UINT_NORET\000"
  /* 5827 */ "RAT_ATOMIC_MAX_UINT_NORET\000"
  /* 5853 */ "RAT_ATOMIC_CMPXCHG_INT_NORET\000"
  /* 5882 */ "RAT_ATOMIC_XCHG_INT_NORET\000"
  /* 5908 */ "RAT_ATOMIC_MIN_INT_NORET\000"
  /* 5933 */ "RAT_ATOMIC_MAX_INT_NORET\000"
  /* 5958 */ "LDS_SUB_RET\000"
  /* 5970 */ "LDS_UBYTE_READ_RET\000"
  /* 5989 */ "LDS_BYTE_READ_RET\000"
  /* 6007 */ "LDS_READ_RET\000"
  /* 6020 */ "LDS_USHORT_READ_RET\000"
  /* 6040 */ "LDS_SHORT_READ_RET\000"
  /* 6059 */ "LDS_ADD_RET\000"
  /* 6071 */ "LDS_AND_RET\000"
  /* 6083 */ "PATCHABLE_RET\000"
  /* 6097 */ "LDS_WRXCHG_RET\000"
  /* 6112 */ "LDS_XOR_RET\000"
  /* 6124 */ "LDS_OR_RET\000"
  /* 6135 */ "LDS_MIN_UINT_RET\000"
  /* 6152 */ "LDS_MAX_UINT_RET\000"
  /* 6169 */ "LDS_MIN_INT_RET\000"
  /* 6185 */ "LDS_MAX_INT_RET\000"
  /* 6201 */ "LDS_CMPST_RET\000"
  /* 6215 */ "G_MEMSET\000"
  /* 6224 */ "IF_PREDICATE_SET\000"
  /* 6241 */ "KILLGT\000"
  /* 6248 */ "SGT\000"
  /* 6252 */ "PRED_SETGT\000"
  /* 6263 */ "PATCHABLE_FUNCTION_EXIT\000"
  /* 6287 */ "G_BRJT\000"
  /* 6294 */ "G_EXTRACT_VECTOR_ELT\000"
  /* 6315 */ "G_INSERT_VECTOR_ELT\000"
  /* 6335 */ "DEFAULT\000"
  /* 6343 */ "G_FCONSTANT\000"
  /* 6355 */ "G_CONSTANT\000"
  /* 6366 */ "G_INTRINSIC_CONVERGENT\000"
  /* 6389 */ "STATEPOINT\000"
  /* 6400 */ "PATCHPOINT\000"
  /* 6411 */ "G_PTRTOINT\000"
  /* 6422 */ "G_FRINT\000"
  /* 6430 */ "G_INTRINSIC_LLRINT\000"
  /* 6449 */ "G_INTRINSIC_LRINT\000"
  /* 6467 */ "SUBB_UINT\000"
  /* 6477 */ "ADDC_UINT\000"
  /* 6487 */ "SETGE_UINT\000"
  /* 6498 */ "FFBH_UINT\000"
  /* 6508 */ "LDS_MIN_UINT\000"
  /* 6521 */ "SETGT_UINT\000"
  /* 6532 */ "LDS_MAX_UINT\000"
  /* 6545 */ "G_FNEARBYINT\000"
  /* 6558 */ "SUB_INT\000"
  /* 6566 */ "ADD_INT\000"
  /* 6574 */ "AND_INT\000"
  /* 6582 */ "CNDE_INT\000"
  /* 6591 */ "CNDGE_INT\000"
  /* 6601 */ "PRED_SETGE_INT\000"
  /* 6616 */ "PRED_SETNE_INT\000"
  /* 6631 */ "PRED_SETE_INT\000"
  /* 6645 */ "FFBL_INT\000"
  /* 6654 */ "LDS_MIN_INT\000"
  /* 6666 */ "XOR_INT\000"
  /* 6674 */ "CNDGT_INT\000"
  /* 6684 */ "PRED_SETGT_INT\000"
  /* 6699 */ "BCNT_INT\000"
  /* 6708 */ "NOT_INT\000"
  /* 6716 */ "LDS_MAX_INT\000"
  /* 6728 */ "G_VASTART\000"
  /* 6738 */ "LIFETIME_START\000"
  /* 6753 */ "G_INVOKE_REGION_START\000"
  /* 6775 */ "G_INSERT\000"
  /* 6784 */ "G_FSQRT\000"
  /* 6792 */ "G_STRICT_FSQRT\000"
  /* 6807 */ "G_BITCAST\000"
  /* 6817 */ "G_ADDRSPACE_CAST\000"
  /* 6834 */ "DBG_VALUE_LIST\000"
  /* 6849 */ "LDS_CMPST\000"
  /* 6859 */ "G_FPEXT\000"
  /* 6867 */ "G_SEXT\000"
  /* 6874 */ "G_ASSERT_SEXT\000"
  /* 6888 */ "G_ANYEXT\000"
  /* 6897 */ "G_ZEXT\000"
  /* 6904 */ "G_ASSERT_ZEXT\000"
  /* 6918 */ "G_ABDU\000"
  /* 6925 */ "CF_ALU\000"
  /* 6932 */ "G_TRUNC_SSAT_U\000"
  /* 6947 */ "G_TRUNC_USAT_U\000"
  /* 6962 */ "G_FDIV\000"
  /* 6969 */ "G_STRICT_FDIV\000"
  /* 6983 */ "G_SDIV\000"
  /* 6990 */ "G_UDIV\000"
  /* 6997 */ "G_GET_FPENV\000"
  /* 7009 */ "G_RESET_FPENV\000"
  /* 7023 */ "G_SET_FPENV\000"
  /* 7035 */ "MOV\000"
  /* 7039 */ "TEX_GET_GRADIENTS_V\000"
  /* 7059 */ "TEX_SET_GRADIENTS_V\000"
  /* 7079 */ "TXD_SHADOW\000"
  /* 7090 */ "G_FPOW\000"
  /* 7097 */ "INTERP_ZW\000"
  /* 7107 */ "INTERP_PAIR_ZW\000"
  /* 7122 */ "G_VECREDUCE_FMAX\000"
  /* 7139 */ "G_ATOMICRMW_FMAX\000"
  /* 7156 */ "G_VECREDUCE_SMAX\000"
  /* 7173 */ "G_SMAX\000"
  /* 7180 */ "G_VECREDUCE_UMAX\000"
  /* 7197 */ "G_UMAX\000"
  /* 7204 */ "G_ATOMICRMW_UMAX\000"
  /* 7221 */ "G_ATOMICRMW_MAX\000"
  /* 7237 */ "G_FRAME_INDEX\000"
  /* 7251 */ "G_SBFX\000"
  /* 7258 */ "G_UBFX\000"
  /* 7265 */ "G_SMULFIX\000"
  /* 7275 */ "G_UMULFIX\000"
  /* 7285 */ "G_SDIVFIX\000"
  /* 7295 */ "G_UDIVFIX\000"
  /* 7305 */ "PRED_X\000"
  /* 7312 */ "G_MEMCPY\000"
  /* 7321 */ "CONST_COPY\000"
  /* 7332 */ "CONVERGENCECTRL_ENTRY\000"
  /* 7354 */ "INTERP_XY\000"
  /* 7364 */ "INTERP_PAIR_XY\000"
  /* 7379 */ "G_CTLZ\000"
  /* 7386 */ "G_CTTZ\000"
  /* 7393 */ "R600_RegisterLoad\000"
  /* 7411 */ "R600_RegisterStore\000"
  /* 7430 */ "R600_ExportBuf\000"
  /* 7445 */ "EG_ExportBuf\000"
  /* 7458 */ "VTX_READ_32_eg\000"
  /* 7473 */ "RAT_WRITE_CACHELESS_32_eg\000"
  /* 7499 */ "MULADD_UINT24_eg\000"
  /* 7516 */ "MULHI_UINT24_eg\000"
  /* 7532 */ "MUL_UINT24_eg\000"
  /* 7546 */ "VTX_READ_64_eg\000"
  /* 7561 */ "RAT_WRITE_CACHELESS_64_eg\000"
  /* 7587 */ "DOT4_eg\000"
  /* 7595 */ "VTX_READ_16_eg\000"
  /* 7610 */ "VTX_READ_128_eg\000"
  /* 7626 */ "RAT_WRITE_CACHELESS_128_eg\000"
  /* 7653 */ "VTX_READ_8_eg\000"
  /* 7667 */ "FMA_eg\000"
  /* 7674 */ "MULADD_eg\000"
  /* 7684 */ "LOG_CLAMPED_eg\000"
  /* 7699 */ "RECIP_CLAMPED_eg\000"
  /* 7716 */ "RECIPSQRT_CLAMPED_eg\000"
  /* 7737 */ "RAT_STORE_TYPED_eg\000"
  /* 7756 */ "CNDE_eg\000"
  /* 7764 */ "MULADD_IEEE_eg\000"
  /* 7779 */ "LOG_IEEE_eg\000"
  /* 7791 */ "RECIP_IEEE_eg\000"
  /* 7805 */ "EXP_IEEE_eg\000"
  /* 7817 */ "RECIPSQRT_IEEE_eg\000"
  /* 7835 */ "CNDGE_eg\000"
  /* 7844 */ "LSHL_eg\000"
  /* 7852 */ "SIN_eg\000"
  /* 7859 */ "ASHR_eg\000"
  /* 7867 */ "LSHR_eg\000"
  /* 7875 */ "COS_eg\000"
  /* 7882 */ "CNDGT_eg\000"
  /* 7891 */ "MUL_LIT_eg\000"
  /* 7902 */ "UINT_TO_FLT_eg\000"
  /* 7917 */ "BFE_UINT_eg\000"
  /* 7929 */ "MULHI_UINT_eg\000"
  /* 7943 */ "MULLO_UINT_eg\000"
  /* 7957 */ "FLT_TO_UINT_eg\000"
  /* 7972 */ "RECIP_UINT_eg\000"
  /* 7986 */ "MOVA_INT_eg\000"
  /* 7998 */ "BFE_INT_eg\000"
  /* 8009 */ "BFI_INT_eg\000"
  /* 8020 */ "MULHI_INT_eg\000"
  /* 8033 */ "BFM_INT_eg\000"
  /* 8044 */ "BIT_ALIGN_INT_eg\000"
  /* 8061 */ "MULLO_INT_eg\000"
  /* 8074 */ "FLT_TO_INT_eg\000"
  /* 8088 */ "CUBE_r600_real\000"
  /* 8103 */ "CUBE_eg_real\000"
  /* 8116 */ "VTX_READ_32_cm\000"
  /* 8131 */ "MULADD_INT24_cm\000"
  /* 8147 */ "MUL_INT24_cm\000"
  /* 8160 */ "VTX_READ_64_cm\000"
  /* 8175 */ "VTX_READ_16_cm\000"
  /* 8190 */ "VTX_READ_128_cm\000"
  /* 8206 */ "VTX_READ_8_cm\000"
  /* 8220 */ "RECIP_CLAMPED_cm\000"
  /* 8237 */ "RECIPSQRT_CLAMPED_cm\000"
  /* 8258 */ "RAT_STORE_TYPED_cm\000"
  /* 8277 */ "LOG_IEEE_cm\000"
  /* 8289 */ "RECIP_IEEE_cm\000"
  /* 8303 */ "EXP_IEEE_cm\000"
  /* 8315 */ "RECIPSQRT_IEEE_cm\000"
  /* 8333 */ "SIN_cm\000"
  /* 8340 */ "COS_cm\000"
  /* 8347 */ "MULHI_UINT_cm\000"
  /* 8361 */ "MULLO_UINT_cm\000"
  /* 8375 */ "MULHI_INT_cm\000"
  /* 8388 */ "MULLO_INT_cm\000"
  /* 8401 */ "CUBE_r600_pseudo\000"
  /* 8418 */ "CUBE_eg_pseudo\000"
  /* 8433 */ "R600_ExportSwz\000"
  /* 8448 */ "EG_ExportSwz\000"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const unsigned R600InstrNameIndices[] = {
    3081U, 3538U, 4635U, 3916U, 3167U, 3148U, 3176U, 3336U, 
    2641U, 2656U, 2569U, 2556U, 2683U, 5268U, 2380U, 6834U, 
    2582U, 3077U, 3157U, 1984U, 7327U, 3124U, 2130U, 6738U, 
    1797U, 1935U, 1972U, 4355U, 3324U, 6400U, 1914U, 4570U, 
    2924U, 6389U, 2196U, 4558U, 4545U, 4765U, 6083U, 6263U, 
    3256U, 3303U, 3276U, 3193U, 2309U, 4681U, 4309U, 2170U, 
    7332U, 4883U, 4516U, 2428U, 6874U, 6904U, 3739U, 1687U, 
    1349U, 3439U, 6983U, 6990U, 3504U, 3511U, 3518U, 3528U, 
    1767U, 5110U, 5065U, 5178U, 6918U, 4937U, 3245U, 4925U, 
    3234U, 2567U, 3079U, 7237U, 2390U, 2405U, 3341U, 5591U, 
    5185U, 6775U, 5202U, 4988U, 1435U, 5251U, 6411U, 5154U, 
    6807U, 2487U, 4692U, 1888U, 1409U, 1870U, 6449U, 6430U, 
    3717U, 4790U, 4809U, 1584U, 1512U, 1542U, 1569U, 1493U, 
    1523U, 2259U, 2243U, 5298U, 2834U, 2862U, 1711U, 1363U, 
    1781U, 1734U, 5122U, 5079U, 7221U, 3885U, 7204U, 3868U, 
    1654U, 1332U, 7139U, 3803U, 3633U, 3580U, 4417U, 4395U, 
    1819U, 5538U, 1964U, 2976U, 1810U, 5610U, 6753U, 1379U, 
    5346U, 6366U, 5373U, 6888U, 1427U, 5411U, 6932U, 6947U, 
    6355U, 6343U, 6728U, 2916U, 6867U, 2670U, 6897U, 3220U, 
    4876U, 4862U, 3213U, 4869U, 5137U, 3357U, 4472U, 4465U, 
    4479U, 4486U, 5601U, 4277U, 2005U, 4261U, 1956U, 4269U, 
    1997U, 4253U, 1948U, 4339U, 4331U, 3005U, 2997U, 5456U, 
    5446U, 5436U, 5426U, 5476U, 5466U, 7265U, 7275U, 5486U, 
    5499U, 7285U, 7295U, 5512U, 5525U, 1612U, 1311U, 3381U, 
    1262U, 1486U, 6962U, 3483U, 2512U, 7090U, 3103U, 4614U, 
    1087U, 596U, 2909U, 1070U, 587U, 4589U, 4621U, 2634U, 
    6859U, 1399U, 3085U, 3094U, 4447U, 4456U, 5559U, 5572U, 
    5165U, 3754U, 5285U, 2496U, 3682U, 3692U, 2063U, 2078U, 
    3569U, 3622U, 3654U, 3668U, 6997U, 7023U, 7009U, 2013U, 
    2041U, 2026U, 2879U, 2894U, 1693U, 3138U, 3837U, 7173U, 
    3861U, 7197U, 5172U, 1861U, 1851U, 4630U, 6287U, 2108U, 
    4969U, 4949U, 6315U, 6294U, 5003U, 5034U, 5020U, 5328U, 
    7386U, 2538U, 7379U, 2520U, 4537U, 4439U, 2272U, 3226U, 
    5234U, 3909U, 5241U, 3710U, 5226U, 3901U, 3702U, 1078U, 
    3029U, 3021U, 3013U, 6784U, 4916U, 6422U, 6545U, 6817U, 
    4648U, 2117U, 1456U, 2465U, 2228U, 1640U, 1318U, 3409U, 
    6969U, 3490U, 1268U, 6792U, 4598U, 4829U, 4845U, 7312U, 
    2154U, 2477U, 6215U, 4347U, 4388U, 4364U, 4376U, 1619U, 
    3388U, 1595U, 3364U, 7122U, 3786U, 3601U, 3548U, 1671U, 
    3423U, 1751U, 5095U, 5049U, 7156U, 3820U, 7180U, 3844U, 
    7251U, 7258U, 2969U, 771U, 937U, 3118U, 760U, 926U, 
    884U, 1050U, 825U, 991U, 7321U, 2456U, 738U, 904U, 
    844U, 1010U, 787U, 953U, 8418U, 8401U, 6335U, 1222U, 
    3766U, 2267U, 1806U, 1391U, 2596U, 4498U, 3778U, 2987U, 
    160U, 82U, 1394U, 752U, 918U, 867U, 1033U, 809U, 
    975U, 6224U, 4493U, 1841U, 2343U, 699U, 4661U, 711U, 
    7305U, 1095U, 1183U, 1115U, 1203U, 7393U, 7411U, 4246U, 
    3932U, 1931U, 7079U, 4506U, 1608U, 6477U, 6566U, 2298U, 
    6574U, 7859U, 388U, 6699U, 7998U, 7917U, 8009U, 8033U, 
    8044U, 3229U, 6925U, 3111U, 2449U, 4730U, 4748U, 2209U, 
    2820U, 170U, 2736U, 65U, 2725U, 34U, 3473U, 2715U, 
    22U, 2776U, 108U, 2751U, 47U, 2697U, 0U, 2706U, 
    11U, 6582U, 7756U, 267U, 6591U, 7835U, 358U, 6674U, 
    7882U, 417U, 8340U, 7875U, 408U, 578U, 8103U, 8088U, 
    7587U, 186U, 7445U, 8448U, 2787U, 121U, 8303U, 7805U, 
    324U, 2285U, 6498U, 6645U, 4919U, 723U, 1228U, 8074U, 
    553U, 7957U, 490U, 7667U, 5585U, 4716U, 666U, 7364U, 
    7107U, 1553U, 7354U, 7097U, 7903U, 442U, 6241U, 1703U, 
    6059U, 1773U, 6071U, 5989U, 2328U, 6849U, 6201U, 6716U, 
    6185U, 6532U, 6152U, 6654U, 6169U, 6508U, 6135U, 5115U, 
    6124U, 6007U, 6040U, 2364U, 1355U, 5958U, 5970U, 6020U, 
    2354U, 2851U, 6097U, 5071U, 6112U, 5217U, 7684U, 208U, 
    8277U, 7779U, 294U, 2762U, 92U, 7844U, 369U, 7867U, 
    398U, 7135U, 657U, 6720U, 6536U, 3799U, 637U, 6658U, 
    6512U, 7035U, 7986U, 3377U, 7764U, 277U, 8131U, 7499U, 
    7674U, 196U, 8375U, 1150U, 8020U, 523U, 7516U, 8347U, 
    1134U, 7929U, 458U, 8388U, 8061U, 538U, 8361U, 7943U, 
    474U, 2054U, 8147U, 7891U, 428U, 7532U, 6708U, 6667U, 
    1591U, 2813U, 151U, 2318U, 6631U, 2097U, 6601U, 6252U, 
    6684U, 2185U, 6616U, 7430U, 8433U, 5666U, 3978U, 5687U, 
    3997U, 5853U, 4149U, 5749U, 4053U, 5775U, 4077U, 5933U, 
    4223U, 5827U, 4125U, 5908U, 4200U, 5801U, 4101U, 5729U, 
    4035U, 5623U, 3939U, 5645U, 3959U, 5882U, 4176U, 5708U, 
    4016U, 4906U, 1243U, 681U, 1165U, 8258U, 7737U, 7626U, 
    7473U, 7561U, 8237U, 7716U, 244U, 8315U, 7817U, 338U, 
    8220U, 7699U, 225U, 8289U, 7791U, 308U, 7972U, 507U, 
    2148U, 2323U, 627U, 6636U, 605U, 6606U, 6487U, 646U, 
    6689U, 6521U, 616U, 6621U, 2093U, 6248U, 8333U, 7852U, 
    379U, 569U, 2181U, 6467U, 6558U, 3037U, 7039U, 4285U, 
    1727U, 5144U, 2137U, 1473U, 2941U, 3445U, 1281U, 2956U, 
    3460U, 1297U, 3057U, 7059U, 2602U, 2619U, 1403U, 7902U, 
    441U, 8190U, 7610U, 8175U, 7595U, 8116U, 7458U, 8160U, 
    7546U, 8206U, 7653U, 2799U, 135U, 6666U, 
};

static inline void InitR600MCInstrInfo(MCInstrInfo *II) {
  II->InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 662, nullptr, 0);
}


} // namespace llvm

#endif // GET_INSTRINFO_MC_DESC

#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER

namespace llvm {

struct R600GenInstrInfo : public TargetInstrInfo {
  explicit R600GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
  ~R600GenInstrInfo() override = default;
};

} // namespace llvm

namespace llvm::R600 {

constexpr unsigned SUBOP_FRAMEri_ptr = 0;
constexpr unsigned SUBOP_FRAMEri_index = 1;
constexpr unsigned SUBOP_MEMrr_ptr = 0;
constexpr unsigned SUBOP_MEMrr_index = 1;
constexpr unsigned SUBOP_MEMxi_ptr = 0;
constexpr unsigned SUBOP_MEMxi_index = 1;

} // namespace llvm::R600

#endif // GET_INSTRINFO_HEADER

#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS


#endif // GET_INSTRINFO_HELPER_DECLS

#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS


#endif // GET_INSTRINFO_HELPERS

#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR

namespace llvm {

extern const R600InstrTable R600Descs;
extern const unsigned R600InstrNameIndices[];
extern const char R600InstrNameData[];
R600GenInstrInfo::R600GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
  : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
  InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 662);
}

} // namespace llvm

#endif // GET_INSTRINFO_CTOR_DTOR

#ifdef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM

namespace llvm::R600 {

enum class OpName : uint8_t {
  dst = 0,
  src0 = 1,
  update_exec_mask_X = 2,
  update_pred_X = 3,
  write_X = 4,
  omod_X = 5,
  dst_rel_X = 6,
  clamp_X = 7,
  src0_X = 8,
  src0_neg_X = 9,
  src0_rel_X = 10,
  src0_abs_X = 11,
  src0_sel_X = 12,
  src1_X = 13,
  src1_neg_X = 14,
  src1_rel_X = 15,
  src1_abs_X = 16,
  src1_sel_X = 17,
  pred_sel_X = 18,
  update_exec_mask_Y = 19,
  update_pred_Y = 20,
  write_Y = 21,
  omod_Y = 22,
  dst_rel_Y = 23,
  clamp_Y = 24,
  src0_Y = 25,
  src0_neg_Y = 26,
  src0_rel_Y = 27,
  src0_abs_Y = 28,
  src0_sel_Y = 29,
  src1_Y = 30,
  src1_neg_Y = 31,
  src1_rel_Y = 32,
  src1_abs_Y = 33,
  src1_sel_Y = 34,
  pred_sel_Y = 35,
  update_exec_mask_Z = 36,
  update_pred_Z = 37,
  write_Z = 38,
  omod_Z = 39,
  dst_rel_Z = 40,
  clamp_Z = 41,
  src0_Z = 42,
  src0_neg_Z = 43,
  src0_rel_Z = 44,
  src0_abs_Z = 45,
  src0_sel_Z = 46,
  src1_Z = 47,
  src1_neg_Z = 48,
  src1_rel_Z = 49,
  src1_abs_Z = 50,
  src1_sel_Z = 51,
  pred_sel_Z = 52,
  update_exec_mask_W = 53,
  update_pred_W = 54,
  write_W = 55,
  omod_W = 56,
  dst_rel_W = 57,
  clamp_W = 58,
  src0_W = 59,
  src0_neg_W = 60,
  src0_rel_W = 61,
  src0_abs_W = 62,
  src0_sel_W = 63,
  src1_W = 64,
  src1_neg_W = 65,
  src1_rel_W = 66,
  src1_abs_W = 67,
  src1_sel_W = 68,
  pred_sel_W = 69,
  literal0 = 70,
  literal1 = 71,
  addr = 72,
  chan = 73,
  val = 74,
  update_exec_mask = 75,
  update_pred = 76,
  write = 77,
  omod = 78,
  dst_rel = 79,
  clamp = 80,
  src0_neg = 81,
  src0_rel = 82,
  src0_abs = 83,
  src0_sel = 84,
  src1 = 85,
  src1_neg = 86,
  src1_rel = 87,
  src1_abs = 88,
  src1_sel = 89,
  last = 90,
  pred_sel = 91,
  literal = 92,
  bank_swizzle = 93,
  src2 = 94,
  src2_neg = 95,
  src2_rel = 96,
  src2_sel = 97,
  ADDR = 98,
  KCACHE_BANK0 = 99,
  KCACHE_BANK1 = 100,
  KCACHE_MODE0 = 101,
  KCACHE_MODE1 = 102,
  KCACHE_ADDR0 = 103,
  KCACHE_ADDR1 = 104,
  COUNT = 105,
  Enabled = 106,
  NUM_OPERAND_NAMES = 107,
}; // enum class OpName

LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, OpName Name);
LLVM_READONLY OpName getOperandIdxName(uint16_t Opcode, int16_t Idx);

} // namespace llvm::R600

#endif // GET_INSTRINFO_OPERAND_ENUM

#ifdef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS

namespace llvm::R600 {

LLVM_READONLY static uint8_t getInstructionIndexForOpLookup(uint16_t Opcode) {
  static constexpr uint8_t InstructionIndex[] = {
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 1, 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 3, 4, 0, 0, 0, 0, 0, 5, 5, 5, 0,
    5, 5, 5, 6, 7, 7, 7, 5, 7, 6, 8, 8, 8, 8, 8, 8,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5,
    5, 5, 0, 0, 0, 0, 6, 6, 6, 0, 6, 6, 6, 6, 6, 6,
    6, 6, 6, 7, 6, 0, 6, 0, 0, 0, 5, 5, 6, 6, 5, 9,
    10, 9, 10, 11, 9, 12, 13, 9, 10, 9, 10, 9, 10, 9, 10, 9,
    10, 11, 11, 9, 9, 10, 11, 11, 9, 9, 10, 9, 10, 0, 6, 6,
    6, 6, 6, 0, 0, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
    5, 6, 6, 5, 7, 7, 7, 7, 7, 7, 5, 5, 5, 5, 5, 5,
    5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 7, 7, 5, 6, 5,
    0, 0, 0, 5, 5, 5, 5, 5, 5, 5, 5, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
    6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6,
    6, 6, 5, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 6, 6, 6, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 5,
  };
  return InstructionIndex[Opcode];
}
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, OpName Name) {
  assert(Name != OpName::NUM_OPERAND_NAMES);
  static constexpr int8_t OperandMap[][107] = {
    {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
    {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
    {0, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
    {0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
    {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
    {0, 7, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
    {0, 5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 6, 7, 8, 9, -1, -1, -1, -1, -1, 10, 11, 12, 13, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
    {0, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 4, 5, -1, 6, 7, 8, 9, -1, 10, 15, 16, 17, 18, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
    {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, },
    {-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 6, 7, -1, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
    {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 7, 8, -1, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
    {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, -1, -1, -1, -1, -1, 4, 5, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
    {-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 9, 10, -1, 11, 6, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
    {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 10, 11, -1, 12, 7, -1, 8, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
  };
  unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
  return OperandMap[InstrIdx][(unsigned)Name];
}
LLVM_READONLY OpName getOperandIdxName(uint16_t Opcode, int16_t Idx) {
  assert(Idx >= 0 && Idx < 71);
  static constexpr OpName OperandMap[][71] = {
    {OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
    {OpName::dst, OpName::src0, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
    {OpName::dst, OpName::update_exec_mask_X, OpName::update_pred_X, OpName::write_X, OpName::omod_X, OpName::dst_rel_X, OpName::clamp_X, OpName::src0_X, OpName::src0_neg_X, OpName::src0_rel_X, OpName::src0_abs_X, OpName::src0_sel_X, OpName::src1_X, OpName::src1_neg_X, OpName::src1_rel_X, OpName::src1_abs_X, OpName::src1_sel_X, OpName::pred_sel_X, OpName::update_exec_mask_Y, OpName::update_pred_Y, OpName::write_Y, OpName::omod_Y, OpName::dst_rel_Y, OpName::clamp_Y, OpName::src0_Y, OpName::src0_neg_Y, OpName::src0_rel_Y, OpName::src0_abs_Y, OpName::src0_sel_Y, OpName::src1_Y, OpName::src1_neg_Y, OpName::src1_rel_Y, OpName::src1_abs_Y, OpName::src1_sel_Y, OpName::pred_sel_Y, OpName::update_exec_mask_Z, OpName::update_pred_Z, OpName::write_Z, OpName::omod_Z, OpName::dst_rel_Z, OpName::clamp_Z, OpName::src0_Z, OpName::src0_neg_Z, OpName::src0_rel_Z, OpName::src0_abs_Z, OpName::src0_sel_Z, OpName::src1_Z, OpName::src1_neg_Z, OpName::src1_rel_Z, OpName::src1_abs_Z, OpName::src1_sel_Z, OpName::pred_sel_Z, OpName::update_exec_mask_W, OpName::update_pred_W, OpName::write_W, OpName::omod_W, OpName::dst_rel_W, OpName::clamp_W, OpName::src0_W, OpName::src0_neg_W, OpName::src0_rel_W, OpName::src0_abs_W, OpName::src0_sel_W, OpName::src1_W, OpName::src1_neg_W, OpName::src1_rel_W, OpName::src1_abs_W, OpName::src1_sel_W, OpName::pred_sel_W, OpName::literal0, OpName::literal1, },
    {OpName::dst, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::chan, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
    {OpName::val, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::chan, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
    {OpName::dst, OpName::update_exec_mask, OpName::update_pred, OpName::write, OpName::omod, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_abs, OpName::src0_sel, OpName::src1, OpName::src1_neg, OpName::src1_rel, OpName::src1_abs, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
    {OpName::dst, OpName::write, OpName::omod, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_abs, OpName::src0_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
    {OpName::dst, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_neg, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_neg, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
    {OpName::ADDR, OpName::KCACHE_BANK0, OpName::KCACHE_BANK1, OpName::KCACHE_MODE0, OpName::KCACHE_MODE1, OpName::KCACHE_ADDR0, OpName::KCACHE_ADDR1, OpName::COUNT, OpName::Enabled, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
    {OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
    {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
    {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
    {OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
    {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
  };
  unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
  return OperandMap[InstrIdx][(unsigned)Idx];
}

} // namespace llvm::R600

#endif // GET_INSTRINFO_NAMED_OPS

#ifdef GET_INSTRINFO_MC_HELPER_DECLS
#undef GET_INSTRINFO_MC_HELPER_DECLS

namespace llvm {

class MCInst;
class FeatureBitset;

namespace R600_MC {

void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);

} // namespace R600_MC

} // namespace llvm

#endif // GET_INSTRINFO_MC_HELPER_DECLS

#ifdef GET_INSTRINFO_MC_HELPERS
#undef GET_INSTRINFO_MC_HELPERS

namespace llvm::R600_MC {


} // namespace llvm::R600_MC

#endif // GET_INSTRINFO_MC_HELPERS

#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
    defined(GET_AVAILABLE_OPCODE_CHECKER)
#define GET_COMPUTE_FEATURES
#endif
#ifdef GET_COMPUTE_FEATURES
#undef GET_COMPUTE_FEATURES

namespace llvm::R600_MC {

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
};

inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
  FeatureBitset Features;
  return Features;
}

inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
  enum : uint8_t {
    CEFBS_None,
  };

  static constexpr FeatureBitset FeatureBitsets[] = {
    {}, // CEFBS_None
  };
  static constexpr uint8_t RequiredFeaturesRefs[] = {
    CEFBS_None, // PHI
    CEFBS_None, // INLINEASM
    CEFBS_None, // INLINEASM_BR
    CEFBS_None, // CFI_INSTRUCTION
    CEFBS_None, // EH_LABEL
    CEFBS_None, // GC_LABEL
    CEFBS_None, // ANNOTATION_LABEL
    CEFBS_None, // KILL
    CEFBS_None, // EXTRACT_SUBREG
    CEFBS_None, // INSERT_SUBREG
    CEFBS_None, // IMPLICIT_DEF
    CEFBS_None, // INIT_UNDEF
    CEFBS_None, // SUBREG_TO_REG
    CEFBS_None, // COPY_TO_REGCLASS
    CEFBS_None, // DBG_VALUE
    CEFBS_None, // DBG_VALUE_LIST
    CEFBS_None, // DBG_INSTR_REF
    CEFBS_None, // DBG_PHI
    CEFBS_None, // DBG_LABEL
    CEFBS_None, // REG_SEQUENCE
    CEFBS_None, // COPY
    CEFBS_None, // COPY_LANEMASK
    CEFBS_None, // BUNDLE
    CEFBS_None, // LIFETIME_START
    CEFBS_None, // LIFETIME_END
    CEFBS_None, // PSEUDO_PROBE
    CEFBS_None, // ARITH_FENCE
    CEFBS_None, // STACKMAP
    CEFBS_None, // FENTRY_CALL
    CEFBS_None, // PATCHPOINT
    CEFBS_None, // LOAD_STACK_GUARD
    CEFBS_None, // PREALLOCATED_SETUP
    CEFBS_None, // PREALLOCATED_ARG
    CEFBS_None, // STATEPOINT
    CEFBS_None, // LOCAL_ESCAPE
    CEFBS_None, // FAULTING_OP
    CEFBS_None, // PATCHABLE_OP
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER
    CEFBS_None, // PATCHABLE_RET
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT
    CEFBS_None, // PATCHABLE_TAIL_CALL
    CEFBS_None, // PATCHABLE_EVENT_CALL
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
    CEFBS_None, // ICALL_BRANCH_FUNNEL
    CEFBS_None, // FAKE_USE
    CEFBS_None, // MEMBARRIER
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO
    CEFBS_None, // RELOC_NONE
    CEFBS_None, // CONVERGENCECTRL_ENTRY
    CEFBS_None, // CONVERGENCECTRL_ANCHOR
    CEFBS_None, // CONVERGENCECTRL_LOOP
    CEFBS_None, // CONVERGENCECTRL_GLUE
    CEFBS_None, // G_ASSERT_SEXT
    CEFBS_None, // G_ASSERT_ZEXT
    CEFBS_None, // G_ASSERT_ALIGN
    CEFBS_None, // G_ADD
    CEFBS_None, // G_SUB
    CEFBS_None, // G_MUL
    CEFBS_None, // G_SDIV
    CEFBS_None, // G_UDIV
    CEFBS_None, // G_SREM
    CEFBS_None, // G_UREM
    CEFBS_None, // G_SDIVREM
    CEFBS_None, // G_UDIVREM
    CEFBS_None, // G_AND
    CEFBS_None, // G_OR
    CEFBS_None, // G_XOR
    CEFBS_None, // G_ABDS
    CEFBS_None, // G_ABDU
    CEFBS_None, // G_UAVGFLOOR
    CEFBS_None, // G_UAVGCEIL
    CEFBS_None, // G_SAVGFLOOR
    CEFBS_None, // G_SAVGCEIL
    CEFBS_None, // G_IMPLICIT_DEF
    CEFBS_None, // G_PHI
    CEFBS_None, // G_FRAME_INDEX
    CEFBS_None, // G_GLOBAL_VALUE
    CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
    CEFBS_None, // G_CONSTANT_POOL
    CEFBS_None, // G_EXTRACT
    CEFBS_None, // G_UNMERGE_VALUES
    CEFBS_None, // G_INSERT
    CEFBS_None, // G_MERGE_VALUES
    CEFBS_None, // G_BUILD_VECTOR
    CEFBS_None, // G_BUILD_VECTOR_TRUNC
    CEFBS_None, // G_CONCAT_VECTORS
    CEFBS_None, // G_PTRTOINT
    CEFBS_None, // G_INTTOPTR
    CEFBS_None, // G_BITCAST
    CEFBS_None, // G_FREEZE
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
    CEFBS_None, // G_INTRINSIC_TRUNC
    CEFBS_None, // G_INTRINSIC_ROUND
    CEFBS_None, // G_INTRINSIC_LRINT
    CEFBS_None, // G_INTRINSIC_LLRINT
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN
    CEFBS_None, // G_READCYCLECOUNTER
    CEFBS_None, // G_READSTEADYCOUNTER
    CEFBS_None, // G_LOAD
    CEFBS_None, // G_SEXTLOAD
    CEFBS_None, // G_ZEXTLOAD
    CEFBS_None, // G_INDEXED_LOAD
    CEFBS_None, // G_INDEXED_SEXTLOAD
    CEFBS_None, // G_INDEXED_ZEXTLOAD
    CEFBS_None, // G_STORE
    CEFBS_None, // G_INDEXED_STORE
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
    CEFBS_None, // G_ATOMIC_CMPXCHG
    CEFBS_None, // G_ATOMICRMW_XCHG
    CEFBS_None, // G_ATOMICRMW_ADD
    CEFBS_None, // G_ATOMICRMW_SUB
    CEFBS_None, // G_ATOMICRMW_AND
    CEFBS_None, // G_ATOMICRMW_NAND
    CEFBS_None, // G_ATOMICRMW_OR
    CEFBS_None, // G_ATOMICRMW_XOR
    CEFBS_None, // G_ATOMICRMW_MAX
    CEFBS_None, // G_ATOMICRMW_MIN
    CEFBS_None, // G_ATOMICRMW_UMAX
    CEFBS_None, // G_ATOMICRMW_UMIN
    CEFBS_None, // G_ATOMICRMW_FADD
    CEFBS_None, // G_ATOMICRMW_FSUB
    CEFBS_None, // G_ATOMICRMW_FMAX
    CEFBS_None, // G_ATOMICRMW_FMIN
    CEFBS_None, // G_ATOMICRMW_FMAXIMUM
    CEFBS_None, // G_ATOMICRMW_FMINIMUM
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
    CEFBS_None, // G_ATOMICRMW_USUB_COND
    CEFBS_None, // G_ATOMICRMW_USUB_SAT
    CEFBS_None, // G_FENCE
    CEFBS_None, // G_PREFETCH
    CEFBS_None, // G_BRCOND
    CEFBS_None, // G_BRINDIRECT
    CEFBS_None, // G_INVOKE_REGION_START
    CEFBS_None, // G_INTRINSIC
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
    CEFBS_None, // G_INTRINSIC_CONVERGENT
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
    CEFBS_None, // G_ANYEXT
    CEFBS_None, // G_TRUNC
    CEFBS_None, // G_TRUNC_SSAT_S
    CEFBS_None, // G_TRUNC_SSAT_U
    CEFBS_None, // G_TRUNC_USAT_U
    CEFBS_None, // G_CONSTANT
    CEFBS_None, // G_FCONSTANT
    CEFBS_None, // G_VASTART
    CEFBS_None, // G_VAARG
    CEFBS_None, // G_SEXT
    CEFBS_None, // G_SEXT_INREG
    CEFBS_None, // G_ZEXT
    CEFBS_None, // G_SHL
    CEFBS_None, // G_LSHR
    CEFBS_None, // G_ASHR
    CEFBS_None, // G_FSHL
    CEFBS_None, // G_FSHR
    CEFBS_None, // G_ROTR
    CEFBS_None, // G_ROTL
    CEFBS_None, // G_ICMP
    CEFBS_None, // G_FCMP
    CEFBS_None, // G_SCMP
    CEFBS_None, // G_UCMP
    CEFBS_None, // G_SELECT
    CEFBS_None, // G_UADDO
    CEFBS_None, // G_UADDE
    CEFBS_None, // G_USUBO
    CEFBS_None, // G_USUBE
    CEFBS_None, // G_SADDO
    CEFBS_None, // G_SADDE
    CEFBS_None, // G_SSUBO
    CEFBS_None, // G_SSUBE
    CEFBS_None, // G_UMULO
    CEFBS_None, // G_SMULO
    CEFBS_None, // G_UMULH
    CEFBS_None, // G_SMULH
    CEFBS_None, // G_UADDSAT
    CEFBS_None, // G_SADDSAT
    CEFBS_None, // G_USUBSAT
    CEFBS_None, // G_SSUBSAT
    CEFBS_None, // G_USHLSAT
    CEFBS_None, // G_SSHLSAT
    CEFBS_None, // G_SMULFIX
    CEFBS_None, // G_UMULFIX
    CEFBS_None, // G_SMULFIXSAT
    CEFBS_None, // G_UMULFIXSAT
    CEFBS_None, // G_SDIVFIX
    CEFBS_None, // G_UDIVFIX
    CEFBS_None, // G_SDIVFIXSAT
    CEFBS_None, // G_UDIVFIXSAT
    CEFBS_None, // G_FADD
    CEFBS_None, // G_FSUB
    CEFBS_None, // G_FMUL
    CEFBS_None, // G_FMA
    CEFBS_None, // G_FMAD
    CEFBS_None, // G_FDIV
    CEFBS_None, // G_FREM
    CEFBS_None, // G_FMODF
    CEFBS_None, // G_FPOW
    CEFBS_None, // G_FPOWI
    CEFBS_None, // G_FEXP
    CEFBS_None, // G_FEXP2
    CEFBS_None, // G_FEXP10
    CEFBS_None, // G_FLOG
    CEFBS_None, // G_FLOG2
    CEFBS_None, // G_FLOG10
    CEFBS_None, // G_FLDEXP
    CEFBS_None, // G_FFREXP
    CEFBS_None, // G_FNEG
    CEFBS_None, // G_FPEXT
    CEFBS_None, // G_FPTRUNC
    CEFBS_None, // G_FPTOSI
    CEFBS_None, // G_FPTOUI
    CEFBS_None, // G_SITOFP
    CEFBS_None, // G_UITOFP
    CEFBS_None, // G_FPTOSI_SAT
    CEFBS_None, // G_FPTOUI_SAT
    CEFBS_None, // G_FABS
    CEFBS_None, // G_FCOPYSIGN
    CEFBS_None, // G_IS_FPCLASS
    CEFBS_None, // G_FCANONICALIZE
    CEFBS_None, // G_FMINNUM
    CEFBS_None, // G_FMAXNUM
    CEFBS_None, // G_FMINNUM_IEEE
    CEFBS_None, // G_FMAXNUM_IEEE
    CEFBS_None, // G_FMINIMUM
    CEFBS_None, // G_FMAXIMUM
    CEFBS_None, // G_FMINIMUMNUM
    CEFBS_None, // G_FMAXIMUMNUM
    CEFBS_None, // G_GET_FPENV
    CEFBS_None, // G_SET_FPENV
    CEFBS_None, // G_RESET_FPENV
    CEFBS_None, // G_GET_FPMODE
    CEFBS_None, // G_SET_FPMODE
    CEFBS_None, // G_RESET_FPMODE
    CEFBS_None, // G_GET_ROUNDING
    CEFBS_None, // G_SET_ROUNDING
    CEFBS_None, // G_PTR_ADD
    CEFBS_None, // G_PTRMASK
    CEFBS_None, // G_SMIN
    CEFBS_None, // G_SMAX
    CEFBS_None, // G_UMIN
    CEFBS_None, // G_UMAX
    CEFBS_None, // G_ABS
    CEFBS_None, // G_LROUND
    CEFBS_None, // G_LLROUND
    CEFBS_None, // G_BR
    CEFBS_None, // G_BRJT
    CEFBS_None, // G_VSCALE
    CEFBS_None, // G_INSERT_SUBVECTOR
    CEFBS_None, // G_EXTRACT_SUBVECTOR
    CEFBS_None, // G_INSERT_VECTOR_ELT
    CEFBS_None, // G_EXTRACT_VECTOR_ELT
    CEFBS_None, // G_SHUFFLE_VECTOR
    CEFBS_None, // G_SPLAT_VECTOR
    CEFBS_None, // G_STEP_VECTOR
    CEFBS_None, // G_VECTOR_COMPRESS
    CEFBS_None, // G_CTTZ
    CEFBS_None, // G_CTTZ_ZERO_UNDEF
    CEFBS_None, // G_CTLZ
    CEFBS_None, // G_CTLZ_ZERO_UNDEF
    CEFBS_None, // G_CTPOP
    CEFBS_None, // G_BSWAP
    CEFBS_None, // G_BITREVERSE
    CEFBS_None, // G_FCEIL
    CEFBS_None, // G_FCOS
    CEFBS_None, // G_FSIN
    CEFBS_None, // G_FSINCOS
    CEFBS_None, // G_FTAN
    CEFBS_None, // G_FACOS
    CEFBS_None, // G_FASIN
    CEFBS_None, // G_FATAN
    CEFBS_None, // G_FATAN2
    CEFBS_None, // G_FCOSH
    CEFBS_None, // G_FSINH
    CEFBS_None, // G_FTANH
    CEFBS_None, // G_FSQRT
    CEFBS_None, // G_FFLOOR
    CEFBS_None, // G_FRINT
    CEFBS_None, // G_FNEARBYINT
    CEFBS_None, // G_ADDRSPACE_CAST
    CEFBS_None, // G_BLOCK_ADDR
    CEFBS_None, // G_JUMP_TABLE
    CEFBS_None, // G_DYN_STACKALLOC
    CEFBS_None, // G_STACKSAVE
    CEFBS_None, // G_STACKRESTORE
    CEFBS_None, // G_STRICT_FADD
    CEFBS_None, // G_STRICT_FSUB
    CEFBS_None, // G_STRICT_FMUL
    CEFBS_None, // G_STRICT_FDIV
    CEFBS_None, // G_STRICT_FREM
    CEFBS_None, // G_STRICT_FMA
    CEFBS_None, // G_STRICT_FSQRT
    CEFBS_None, // G_STRICT_FLDEXP
    CEFBS_None, // G_READ_REGISTER
    CEFBS_None, // G_WRITE_REGISTER
    CEFBS_None, // G_MEMCPY
    CEFBS_None, // G_MEMCPY_INLINE
    CEFBS_None, // G_MEMMOVE
    CEFBS_None, // G_MEMSET
    CEFBS_None, // G_BZERO
    CEFBS_None, // G_TRAP
    CEFBS_None, // G_DEBUGTRAP
    CEFBS_None, // G_UBSANTRAP
    CEFBS_None, // G_VECREDUCE_SEQ_FADD
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL
    CEFBS_None, // G_VECREDUCE_FADD
    CEFBS_None, // G_VECREDUCE_FMUL
    CEFBS_None, // G_VECREDUCE_FMAX
    CEFBS_None, // G_VECREDUCE_FMIN
    CEFBS_None, // G_VECREDUCE_FMAXIMUM
    CEFBS_None, // G_VECREDUCE_FMINIMUM
    CEFBS_None, // G_VECREDUCE_ADD
    CEFBS_None, // G_VECREDUCE_MUL
    CEFBS_None, // G_VECREDUCE_AND
    CEFBS_None, // G_VECREDUCE_OR
    CEFBS_None, // G_VECREDUCE_XOR
    CEFBS_None, // G_VECREDUCE_SMAX
    CEFBS_None, // G_VECREDUCE_SMIN
    CEFBS_None, // G_VECREDUCE_UMAX
    CEFBS_None, // G_VECREDUCE_UMIN
    CEFBS_None, // G_SBFX
    CEFBS_None, // G_UBFX
    CEFBS_None, // BRANCH
    CEFBS_None, // BRANCH_COND_f32
    CEFBS_None, // BRANCH_COND_i32
    CEFBS_None, // BREAK
    CEFBS_None, // BREAKC_f32
    CEFBS_None, // BREAKC_i32
    CEFBS_None, // BREAK_LOGICALNZ_f32
    CEFBS_None, // BREAK_LOGICALNZ_i32
    CEFBS_None, // BREAK_LOGICALZ_f32
    CEFBS_None, // BREAK_LOGICALZ_i32
    CEFBS_None, // CONST_COPY
    CEFBS_None, // CONTINUE
    CEFBS_None, // CONTINUEC_f32
    CEFBS_None, // CONTINUEC_i32
    CEFBS_None, // CONTINUE_LOGICALNZ_f32
    CEFBS_None, // CONTINUE_LOGICALNZ_i32
    CEFBS_None, // CONTINUE_LOGICALZ_f32
    CEFBS_None, // CONTINUE_LOGICALZ_i32
    CEFBS_None, // CUBE_eg_pseudo
    CEFBS_None, // CUBE_r600_pseudo
    CEFBS_None, // DEFAULT
    CEFBS_None, // DOT_4
    CEFBS_None, // DUMMY_CHAIN
    CEFBS_None, // ELSE
    CEFBS_None, // END
    CEFBS_None, // ENDFUNC
    CEFBS_None, // ENDIF
    CEFBS_None, // ENDLOOP
    CEFBS_None, // ENDMAIN
    CEFBS_None, // ENDSWITCH
    CEFBS_None, // FABS_R600
    CEFBS_None, // FNEG_R600
    CEFBS_None, // FUNC
    CEFBS_None, // IFC_f32
    CEFBS_None, // IFC_i32
    CEFBS_None, // IF_LOGICALNZ_f32
    CEFBS_None, // IF_LOGICALNZ_i32
    CEFBS_None, // IF_LOGICALZ_f32
    CEFBS_None, // IF_LOGICALZ_i32
    CEFBS_None, // IF_PREDICATE_SET
    CEFBS_None, // JUMP
    CEFBS_None, // JUMP_COND
    CEFBS_None, // MASK_WRITE
    CEFBS_None, // MOV_IMM_F32
    CEFBS_None, // MOV_IMM_GLOBAL_ADDR
    CEFBS_None, // MOV_IMM_I32
    CEFBS_None, // PRED_X
    CEFBS_None, // R600_EXTRACT_ELT_V2
    CEFBS_None, // R600_EXTRACT_ELT_V4
    CEFBS_None, // R600_INSERT_ELT_V2
    CEFBS_None, // R600_INSERT_ELT_V4
    CEFBS_None, // R600_RegisterLoad
    CEFBS_None, // R600_RegisterStore
    CEFBS_None, // RETDYN
    CEFBS_None, // RETURN
    CEFBS_None, // TXD
    CEFBS_None, // TXD_SHADOW
    CEFBS_None, // WHILELOOP
    CEFBS_None, // ADD
    CEFBS_None, // ADDC_UINT
    CEFBS_None, // ADD_INT
    CEFBS_None, // ALU_CLAUSE
    CEFBS_None, // AND_INT
    CEFBS_None, // ASHR_eg
    CEFBS_None, // ASHR_r600
    CEFBS_None, // BCNT_INT
    CEFBS_None, // BFE_INT_eg
    CEFBS_None, // BFE_UINT_eg
    CEFBS_None, // BFI_INT_eg
    CEFBS_None, // BFM_INT_eg
    CEFBS_None, // BIT_ALIGN_INT_eg
    CEFBS_None, // CEIL
    CEFBS_None, // CF_ALU
    CEFBS_None, // CF_ALU_BREAK
    CEFBS_None, // CF_ALU_CONTINUE
    CEFBS_None, // CF_ALU_ELSE_AFTER
    CEFBS_None, // CF_ALU_POP_AFTER
    CEFBS_None, // CF_ALU_PUSH_BEFORE
    CEFBS_None, // CF_CALL_FS_EG
    CEFBS_None, // CF_CALL_FS_R600
    CEFBS_None, // CF_CONTINUE_EG
    CEFBS_None, // CF_CONTINUE_R600
    CEFBS_None, // CF_ELSE_EG
    CEFBS_None, // CF_ELSE_R600
    CEFBS_None, // CF_END_CM
    CEFBS_None, // CF_END_EG
    CEFBS_None, // CF_END_R600
    CEFBS_None, // CF_JUMP_EG
    CEFBS_None, // CF_JUMP_R600
    CEFBS_None, // CF_PUSH_EG
    CEFBS_None, // CF_PUSH_ELSE_R600
    CEFBS_None, // CF_TC_EG
    CEFBS_None, // CF_TC_R600
    CEFBS_None, // CF_VC_EG
    CEFBS_None, // CF_VC_R600
    CEFBS_None, // CNDE_INT
    CEFBS_None, // CNDE_eg
    CEFBS_None, // CNDE_r600
    CEFBS_None, // CNDGE_INT
    CEFBS_None, // CNDGE_eg
    CEFBS_None, // CNDGE_r600
    CEFBS_None, // CNDGT_INT
    CEFBS_None, // CNDGT_eg
    CEFBS_None, // CNDGT_r600
    CEFBS_None, // COS_cm
    CEFBS_None, // COS_eg
    CEFBS_None, // COS_r600
    CEFBS_None, // COS_r700
    CEFBS_None, // CUBE_eg_real
    CEFBS_None, // CUBE_r600_real
    CEFBS_None, // DOT4_eg
    CEFBS_None, // DOT4_r600
    CEFBS_None, // EG_ExportBuf
    CEFBS_None, // EG_ExportSwz
    CEFBS_None, // END_LOOP_EG
    CEFBS_None, // END_LOOP_R600
    CEFBS_None, // EXP_IEEE_cm
    CEFBS_None, // EXP_IEEE_eg
    CEFBS_None, // EXP_IEEE_r600
    CEFBS_None, // FETCH_CLAUSE
    CEFBS_None, // FFBH_UINT
    CEFBS_None, // FFBL_INT
    CEFBS_None, // FLOOR
    CEFBS_None, // FLT16_TO_FLT32
    CEFBS_None, // FLT32_TO_FLT16
    CEFBS_None, // FLT_TO_INT_eg
    CEFBS_None, // FLT_TO_INT_r600
    CEFBS_None, // FLT_TO_UINT_eg
    CEFBS_None, // FLT_TO_UINT_r600
    CEFBS_None, // FMA_eg
    CEFBS_None, // FRACT
    CEFBS_None, // GROUP_BARRIER
    CEFBS_None, // INTERP_LOAD_P0
    CEFBS_None, // INTERP_PAIR_XY
    CEFBS_None, // INTERP_PAIR_ZW
    CEFBS_None, // INTERP_VEC_LOAD
    CEFBS_None, // INTERP_XY
    CEFBS_None, // INTERP_ZW
    CEFBS_None, // INT_TO_FLT_eg
    CEFBS_None, // INT_TO_FLT_r600
    CEFBS_None, // KILLGT
    CEFBS_None, // LDS_ADD
    CEFBS_None, // LDS_ADD_RET
    CEFBS_None, // LDS_AND
    CEFBS_None, // LDS_AND_RET
    CEFBS_None, // LDS_BYTE_READ_RET
    CEFBS_None, // LDS_BYTE_WRITE
    CEFBS_None, // LDS_CMPST
    CEFBS_None, // LDS_CMPST_RET
    CEFBS_None, // LDS_MAX_INT
    CEFBS_None, // LDS_MAX_INT_RET
    CEFBS_None, // LDS_MAX_UINT
    CEFBS_None, // LDS_MAX_UINT_RET
    CEFBS_None, // LDS_MIN_INT
    CEFBS_None, // LDS_MIN_INT_RET
    CEFBS_None, // LDS_MIN_UINT
    CEFBS_None, // LDS_MIN_UINT_RET
    CEFBS_None, // LDS_OR
    CEFBS_None, // LDS_OR_RET
    CEFBS_None, // LDS_READ_RET
    CEFBS_None, // LDS_SHORT_READ_RET
    CEFBS_None, // LDS_SHORT_WRITE
    CEFBS_None, // LDS_SUB
    CEFBS_None, // LDS_SUB_RET
    CEFBS_None, // LDS_UBYTE_READ_RET
    CEFBS_None, // LDS_USHORT_READ_RET
    CEFBS_None, // LDS_WRITE
    CEFBS_None, // LDS_WRXCHG
    CEFBS_None, // LDS_WRXCHG_RET
    CEFBS_None, // LDS_XOR
    CEFBS_None, // LDS_XOR_RET
    CEFBS_None, // LITERALS
    CEFBS_None, // LOG_CLAMPED_eg
    CEFBS_None, // LOG_CLAMPED_r600
    CEFBS_None, // LOG_IEEE_cm
    CEFBS_None, // LOG_IEEE_eg
    CEFBS_None, // LOG_IEEE_r600
    CEFBS_None, // LOOP_BREAK_EG
    CEFBS_None, // LOOP_BREAK_R600
    CEFBS_None, // LSHL_eg
    CEFBS_None, // LSHL_r600
    CEFBS_None, // LSHR_eg
    CEFBS_None, // LSHR_r600
    CEFBS_None, // MAX
    CEFBS_None, // MAX_DX10
    CEFBS_None, // MAX_INT
    CEFBS_None, // MAX_UINT
    CEFBS_None, // MIN
    CEFBS_None, // MIN_DX10
    CEFBS_None, // MIN_INT
    CEFBS_None, // MIN_UINT
    CEFBS_None, // MOV
    CEFBS_None, // MOVA_INT_eg
    CEFBS_None, // MUL
    CEFBS_None, // MULADD_IEEE_eg
    CEFBS_None, // MULADD_IEEE_r600
    CEFBS_None, // MULADD_INT24_cm
    CEFBS_None, // MULADD_UINT24_eg
    CEFBS_None, // MULADD_eg
    CEFBS_None, // MULADD_r600
    CEFBS_None, // MULHI_INT_cm
    CEFBS_None, // MULHI_INT_cm24
    CEFBS_None, // MULHI_INT_eg
    CEFBS_None, // MULHI_INT_r600
    CEFBS_None, // MULHI_UINT24_eg
    CEFBS_None, // MULHI_UINT_cm
    CEFBS_None, // MULHI_UINT_cm24
    CEFBS_None, // MULHI_UINT_eg
    CEFBS_None, // MULHI_UINT_r600
    CEFBS_None, // MULLO_INT_cm
    CEFBS_None, // MULLO_INT_eg
    CEFBS_None, // MULLO_INT_r600
    CEFBS_None, // MULLO_UINT_cm
    CEFBS_None, // MULLO_UINT_eg
    CEFBS_None, // MULLO_UINT_r600
    CEFBS_None, // MUL_IEEE
    CEFBS_None, // MUL_INT24_cm
    CEFBS_None, // MUL_LIT_eg
    CEFBS_None, // MUL_LIT_r600
    CEFBS_None, // MUL_UINT24_eg
    CEFBS_None, // NOT_INT
    CEFBS_None, // OR_INT
    CEFBS_None, // PAD
    CEFBS_None, // POP_EG
    CEFBS_None, // POP_R600
    CEFBS_None, // PRED_SETE
    CEFBS_None, // PRED_SETE_INT
    CEFBS_None, // PRED_SETGE
    CEFBS_None, // PRED_SETGE_INT
    CEFBS_None, // PRED_SETGT
    CEFBS_None, // PRED_SETGT_INT
    CEFBS_None, // PRED_SETNE
    CEFBS_None, // PRED_SETNE_INT
    CEFBS_None, // R600_ExportBuf
    CEFBS_None, // R600_ExportSwz
    CEFBS_None, // RAT_ATOMIC_ADD_NORET
    CEFBS_None, // RAT_ATOMIC_ADD_RTN
    CEFBS_None, // RAT_ATOMIC_AND_NORET
    CEFBS_None, // RAT_ATOMIC_AND_RTN
    CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_NORET
    CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_RTN
    CEFBS_None, // RAT_ATOMIC_DEC_UINT_NORET
    CEFBS_None, // RAT_ATOMIC_DEC_UINT_RTN
    CEFBS_None, // RAT_ATOMIC_INC_UINT_NORET
    CEFBS_None, // RAT_ATOMIC_INC_UINT_RTN
    CEFBS_None, // RAT_ATOMIC_MAX_INT_NORET
    CEFBS_None, // RAT_ATOMIC_MAX_INT_RTN
    CEFBS_None, // RAT_ATOMIC_MAX_UINT_NORET
    CEFBS_None, // RAT_ATOMIC_MAX_UINT_RTN
    CEFBS_None, // RAT_ATOMIC_MIN_INT_NORET
    CEFBS_None, // RAT_ATOMIC_MIN_INT_RTN
    CEFBS_None, // RAT_ATOMIC_MIN_UINT_NORET
    CEFBS_None, // RAT_ATOMIC_MIN_UINT_RTN
    CEFBS_None, // RAT_ATOMIC_OR_NORET
    CEFBS_None, // RAT_ATOMIC_OR_RTN
    CEFBS_None, // RAT_ATOMIC_RSUB_NORET
    CEFBS_None, // RAT_ATOMIC_RSUB_RTN
    CEFBS_None, // RAT_ATOMIC_SUB_NORET
    CEFBS_None, // RAT_ATOMIC_SUB_RTN
    CEFBS_None, // RAT_ATOMIC_XCHG_INT_NORET
    CEFBS_None, // RAT_ATOMIC_XCHG_INT_RTN
    CEFBS_None, // RAT_ATOMIC_XOR_NORET
    CEFBS_None, // RAT_ATOMIC_XOR_RTN
    CEFBS_None, // RAT_MSKOR
    CEFBS_None, // RAT_STORE_DWORD128
    CEFBS_None, // RAT_STORE_DWORD32
    CEFBS_None, // RAT_STORE_DWORD64
    CEFBS_None, // RAT_STORE_TYPED_cm
    CEFBS_None, // RAT_STORE_TYPED_eg
    CEFBS_None, // RAT_WRITE_CACHELESS_128_eg
    CEFBS_None, // RAT_WRITE_CACHELESS_32_eg
    CEFBS_None, // RAT_WRITE_CACHELESS_64_eg
    CEFBS_None, // RECIPSQRT_CLAMPED_cm
    CEFBS_None, // RECIPSQRT_CLAMPED_eg
    CEFBS_None, // RECIPSQRT_CLAMPED_r600
    CEFBS_None, // RECIPSQRT_IEEE_cm
    CEFBS_None, // RECIPSQRT_IEEE_eg
    CEFBS_None, // RECIPSQRT_IEEE_r600
    CEFBS_None, // RECIP_CLAMPED_cm
    CEFBS_None, // RECIP_CLAMPED_eg
    CEFBS_None, // RECIP_CLAMPED_r600
    CEFBS_None, // RECIP_IEEE_cm
    CEFBS_None, // RECIP_IEEE_eg
    CEFBS_None, // RECIP_IEEE_r600
    CEFBS_None, // RECIP_UINT_eg
    CEFBS_None, // RECIP_UINT_r600
    CEFBS_None, // RNDNE
    CEFBS_None, // SETE
    CEFBS_None, // SETE_DX10
    CEFBS_None, // SETE_INT
    CEFBS_None, // SETGE_DX10
    CEFBS_None, // SETGE_INT
    CEFBS_None, // SETGE_UINT
    CEFBS_None, // SETGT_DX10
    CEFBS_None, // SETGT_INT
    CEFBS_None, // SETGT_UINT
    CEFBS_None, // SETNE_DX10
    CEFBS_None, // SETNE_INT
    CEFBS_None, // SGE
    CEFBS_None, // SGT
    CEFBS_None, // SIN_cm
    CEFBS_None, // SIN_eg
    CEFBS_None, // SIN_r600
    CEFBS_None, // SIN_r700
    CEFBS_None, // SNE
    CEFBS_None, // SUBB_UINT
    CEFBS_None, // SUB_INT
    CEFBS_None, // TEX_GET_GRADIENTS_H
    CEFBS_None, // TEX_GET_GRADIENTS_V
    CEFBS_None, // TEX_GET_TEXTURE_RESINFO
    CEFBS_None, // TEX_LD
    CEFBS_None, // TEX_LDPTR
    CEFBS_None, // TEX_SAMPLE
    CEFBS_None, // TEX_SAMPLE_C
    CEFBS_None, // TEX_SAMPLE_C_G
    CEFBS_None, // TEX_SAMPLE_C_L
    CEFBS_None, // TEX_SAMPLE_C_LB
    CEFBS_None, // TEX_SAMPLE_G
    CEFBS_None, // TEX_SAMPLE_L
    CEFBS_None, // TEX_SAMPLE_LB
    CEFBS_None, // TEX_SET_GRADIENTS_H
    CEFBS_None, // TEX_SET_GRADIENTS_V
    CEFBS_None, // TEX_VTX_CONSTBUF
    CEFBS_None, // TEX_VTX_TEXBUF
    CEFBS_None, // TRUNC
    CEFBS_None, // UINT_TO_FLT_eg
    CEFBS_None, // UINT_TO_FLT_r600
    CEFBS_None, // VTX_READ_128_cm
    CEFBS_None, // VTX_READ_128_eg
    CEFBS_None, // VTX_READ_16_cm
    CEFBS_None, // VTX_READ_16_eg
    CEFBS_None, // VTX_READ_32_cm
    CEFBS_None, // VTX_READ_32_eg
    CEFBS_None, // VTX_READ_64_cm
    CEFBS_None, // VTX_READ_64_eg
    CEFBS_None, // VTX_READ_8_cm
    CEFBS_None, // VTX_READ_8_eg
    CEFBS_None, // WHILE_LOOP_EG
    CEFBS_None, // WHILE_LOOP_R600
    CEFBS_None, // XOR_INT
  };

  assert(Opcode < 662);
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
}


} // namespace llvm::R600_MC

#endif // GET_COMPUTE_FEATURES

#ifdef GET_AVAILABLE_OPCODE_CHECKER
#undef GET_AVAILABLE_OPCODE_CHECKER

namespace llvm::R600_MC {

bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  return !MissingFeatures.any();
}

} // namespace llvm::R600_MC

#endif // GET_AVAILABLE_OPCODE_CHECKER

#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER

#include <sstream>

namespace llvm::R600_MC {

#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
  nullptr
};

#endif // NDEBUG

void verifyInstructionPredicates(
    unsigned Opcode, const FeatureBitset &Features) {
#ifndef NDEBUG
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  if (MissingFeatures.any()) {
    std::ostringstream Msg;
    Msg << "Attempting to emit " << &R600InstrNameData[R600InstrNameIndices[Opcode]]
        << " instruction but the ";
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
      if (MissingFeatures.test(i))
        Msg << SubtargetFeatureNames[i] << " ";
    Msg << "predicate(s) are not met";
    report_fatal_error(Msg.str().c_str());
  }
#endif // NDEBUG
}

} // namespace llvm::R600_MC

#endif // ENABLE_INSTR_PREDICATE_VERIFIER

#ifdef GET_INSTRMAP_INFO
#undef GET_INSTRMAP_INFO

namespace llvm::R600 {

enum usesCustomInserter {
  usesCustomInserter_0
};

// getLDSNoRetOp
LLVM_READONLY
int getLDSNoRetOp(uint16_t Opcode) {
  using namespace R600;
  static constexpr uint16_t Table[][2] = {
    { LDS_ADD_RET, LDS_ADD },
    { LDS_AND_RET, LDS_AND },
    { LDS_MAX_INT_RET, LDS_MAX_INT },
    { LDS_MAX_UINT_RET, LDS_MAX_UINT },
    { LDS_MIN_INT_RET, LDS_MIN_INT },
    { LDS_MIN_UINT_RET, LDS_MIN_UINT },
    { LDS_OR_RET, LDS_OR },
    { LDS_SUB_RET, LDS_SUB },
    { LDS_WRXCHG_RET, LDS_WRXCHG },
    { LDS_XOR_RET, LDS_XOR },
  }; // End of Table

  unsigned mid;
  unsigned start = 0;
  unsigned end = 10;
  while (start < end) {
    mid = start + (end - start) / 2;
    if (Opcode == Table[mid][0]) 
      break;
    if (Opcode < Table[mid][0])
      end = mid;
    else
      start = mid + 1;
  }
  if (start == end)
    return -1; // Instruction doesn't exist in this table.

  return Table[mid][1];
}


} // namespace llvm::R600

#endif // GET_INSTRMAP_INFO

