/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Subtarget Enumeration Source Fragment                                      *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM

namespace llvm {


} // namespace llvm

#endif // GET_SUBTARGETINFO_ENUM

#ifdef GET_SUBTARGETINFO_MACRO


#undef GET_SUBTARGETINFO_MACRO
#endif // GET_SUBTARGETINFO_MACRO

#ifdef GET_SUBTARGETINFO_MC_DESC
#undef GET_SUBTARGETINFO_MC_DESC

namespace llvm {


#ifdef DBGFIELD
#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
#endif
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
#define DBGFIELD(x) x,
#define DBGVAL_OR_NULLPTR(x) x
#else
#define DBGFIELD(x)
#define DBGVAL_OR_NULLPTR(x) nullptr
#endif

// Functional units for "LanaiItinerary"
namespace LanaiItineraryFU {

  const InstrStage::FuncUnits ALU_FU = 1ULL << 0;
  const InstrStage::FuncUnits LDST_FU = 1ULL << 1;

} // namespace LanaiItineraryFU

extern const llvm::InstrStage LanaiStages[] = {
  { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
  { 1, LanaiItineraryFU::ALU_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
  { 1, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
  { 2, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
  { 0, 0, 0, llvm::InstrStage::Required } // End stages
};
extern const unsigned LanaiOperandCycles[] = {
  0, // No itinerary
  0 // End operand cycles
};
extern const unsigned LanaiForwardingPaths[] = {
 0, // No itinerary
 0 // End bypass tables
};

static constexpr llvm::InstrItinerary LanaiItinerary[] = {
  { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
  { 1, 1, 2, 0, 0 }, // 1 IIC_ALU_WriteALU
  { 1, 1, 2, 0, 0 }, // 2 IIC_ALU
  { 1, 2, 3, 0, 0 }, // 3 IIC_LD_WriteLD
  { 1, 3, 4, 0, 0 }, // 4 IIC_LDSW_WriteLDSW
  { 0, 0, 0, 0, 0 }, // 5 WriteLD
  { 1, 2, 3, 0, 0 }, // 6 IIC_ST_WriteST
  { 1, 3, 4, 0, 0 }, // 7 IIC_STSW_WriteSTSW
  { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
};

// ===============================================================
// Data tables for the new per-operand machine model.

// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[] = {
  { 0,  0,  0 }, // Invalid
  { 1,  1,   0}, // #1
  { 2,  1,   0} // #2
}; // LanaiWriteProcResTable

// {Cycles, WriteResourceID}
extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[] = {
  { 0,  0}, // Invalid
  { 1,  0}, // #1 WriteALU
  { 2,  0}, // #2 WriteLD_WriteLDSW_WriteST
  { 4,  0} // #3 WriteSTSW
}; // LanaiWriteLatencyTable

// {UseIdx, WriteResourceID, Cycles}
extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[] = {
  {0,  0,  0}, // Invalid
}; // LanaiReadAdvanceTable

// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
static const llvm::MCSchedClassDesc LanaiSchedModelSchedClasses[] = {
  {DBGFIELD(1)  8191, false, false, false, 0, 0,  0, 0,  0, 0},
  {DBGFIELD(/*IIC_ALU_WriteALU*/ 19)   1, false, false, false,  1, 1,  1, 1,  0, 0}, // #1
  {DBGFIELD(/*IIC_ALU*/ 36)            8191, false, false, false,  0, 0,  0, 0,  0, 0}, // #2
  {DBGFIELD(/*IIC_LD_WriteLD*/ 44)     1, false, false, false,  2, 1,  2, 1,  0, 0}, // #3
  {DBGFIELD(/*IIC_LDSW_WriteLDSW*/ 59) 1, false, false, false,  2, 1,  2, 1,  0, 0}, // #4
  {DBGFIELD(/*WriteLD*/ 78)            1, false, false, false,  2, 1,  2, 1,  0, 0}, // #5
  {DBGFIELD(/*IIC_ST_WriteST*/ 86)     1, false, false, false,  2, 1,  2, 1,  0, 0}, // #6
  {DBGFIELD(/*IIC_STSW_WriteSTSW*/ 101) 1, false, false, false,  2, 1,  3, 1,  0, 0}, // #7
}; // LanaiSchedModelSchedClasses

#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
static constexpr char LanaiSchedClassNamesStorage[] =
  "\0"
  "InvalidSchedClass\0"
  "IIC_ALU_WriteALU\0"
  "IIC_ALU\0"
  "IIC_LD_WriteLD\0"
  "IIC_LDSW_WriteLDSW\0"
  "WriteLD\0"
  "IIC_ST_WriteST\0"
  "IIC_STSW_WriteSTSW\0"
  ;
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

static constexpr llvm::StringTable
LanaiSchedClassNames = LanaiSchedClassNamesStorage;

static const llvm::MCSchedModel NoSchedModel = {
  MCSchedModel::DefaultIssueWidth,
  MCSchedModel::DefaultMicroOpBufferSize,
  MCSchedModel::DefaultLoopMicroOpBufferSize,
  MCSchedModel::DefaultLoadLatency,
  MCSchedModel::DefaultHighLatency,
  MCSchedModel::DefaultMispredictPenalty,
  false, // PostRAScheduler
  false, // CompleteModel
  false, // EnableIntervals
  0, // Processor ID
  nullptr, nullptr, 0, 0, // No instruction-level machine model.
  DBGVAL_OR_NULLPTR(&LanaiSchedClassNames), // SchedClassNames
  nullptr, // No Itinerary
  nullptr // No extra processor descriptor
};

static const unsigned LanaiSchedModelProcResourceSubUnits[] = {
  0,  // Invalid
};

// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
static const llvm::MCProcResourceDesc LanaiSchedModelProcResources[] = {
  {"InvalidUnit", 0, 0, 0, 0},
  {"ALU",             1, 0, 0, nullptr}, // #1
  {"LdSt",            1, 0, 0, nullptr}, // #2
};

static const llvm::MCSchedModel LanaiSchedModel = {
  1, // IssueWidth
  0, // MicroOpBufferSize
  0, // LoopMicroOpBufferSize
  2, // LoadLatency
  MCSchedModel::DefaultHighLatency,
  10, // MispredictPenalty
  false, // PostRAScheduler
  false, // CompleteModel
  false, // EnableIntervals
  1, // Processor ID
  LanaiSchedModelProcResources,
  LanaiSchedModelSchedClasses,
  3,
  8,
  DBGVAL_OR_NULLPTR(&LanaiSchedClassNames), // SchedClassNames
  LanaiItinerary,
  nullptr // No extra processor descriptor
};

#undef DBGFIELD

#undef DBGVAL_OR_NULLPTR

// Sorted (by key) array of values for CPU subtype.
extern const llvm::SubtargetSubTypeKV LanaiSubTypeKV[] = {
 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LanaiSchedModel },
 { "v11", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LanaiSchedModel },
};

// Sorted array of names of CPU subtypes, including aliases.
extern const llvm::StringRef LanaiNames[] = {
"generic",
"v11"};

namespace Lanai_MC {

unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
    const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
  // Don't know how to resolve this scheduling class.
  return 0;
}

} // namespace Lanai_MC
struct LanaiGenMCSubtargetInfo : public MCSubtargetInfo {
  LanaiGenMCSubtargetInfo(const Triple &TT,
    StringRef CPU, StringRef TuneCPU, StringRef FS,
    ArrayRef<StringRef> PN,
    ArrayRef<SubtargetFeatureKV> PF,
    ArrayRef<SubtargetSubTypeKV> PD,
    const MCWriteProcResEntry *WPR,
    const MCWriteLatencyEntry *WL,
    const MCReadAdvanceEntry *RA, const InstrStage *IS,
    const unsigned *OC, const unsigned *FP) :
      MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
                      WPR, WL, RA, IS, OC, FP) { }

  unsigned resolveVariantSchedClass(unsigned SchedClass,
      const MCInst *MI, const MCInstrInfo *MCII,
      unsigned CPUID) const override {
    return Lanai_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
  }
};

static inline MCSubtargetInfo *createLanaiMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
  return new LanaiGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, LanaiNames, {}, LanaiSubTypeKV, 
                      LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable, 
                      LanaiStages, LanaiOperandCycles, LanaiForwardingPaths);
}


} // namespace llvm

#endif // GET_SUBTARGETINFO_MC_DESC

#ifdef GET_SUBTARGETINFO_TARGET_DESC
#undef GET_SUBTARGETINFO_TARGET_DESC

#include "llvm/ADT/BitmaskEnum.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"

// ParseSubtargetFeatures - Parses features string setting specified
// subtarget options.
void llvm::LanaiSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
  LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
  LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
  LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
}

#endif // GET_SUBTARGETINFO_TARGET_DESC

#ifdef GET_SUBTARGETINFO_HEADER
#undef GET_SUBTARGETINFO_HEADER

namespace llvm {

class DFAPacketizer;
namespace Lanai_MC {

unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);

} // namespace Lanai_MC
struct LanaiGenSubtargetInfo : public TargetSubtargetInfo {
  explicit LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
public:
  unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
  unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
};

} // namespace llvm

#endif // GET_SUBTARGETINFO_HEADER

#ifdef GET_SUBTARGETINFO_CTOR
#undef GET_SUBTARGETINFO_CTOR

#include "llvm/CodeGen/TargetSchedule.h"

namespace llvm {

extern const llvm::StringRef LanaiNames[];
extern const llvm::SubtargetFeatureKV LanaiFeatureKV[];
extern const llvm::SubtargetSubTypeKV LanaiSubTypeKV[];
extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[];
extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[];
extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[];
extern const llvm::InstrStage LanaiStages[];
extern const unsigned LanaiOperandCycles[];
extern const unsigned LanaiForwardingPaths[];
LanaiGenSubtargetInfo::LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
  : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(LanaiNames, 2), {}, ArrayRef(LanaiSubTypeKV, 2), 
                        LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable, 
                        LanaiStages, LanaiOperandCycles, LanaiForwardingPaths) {}

unsigned LanaiGenSubtargetInfo
::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
  report_fatal_error("Expected a variant SchedClass");
} // LanaiGenSubtargetInfo::resolveSchedClass

unsigned LanaiGenSubtargetInfo
::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
  return Lanai_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
} // LanaiGenSubtargetInfo::resolveVariantSchedClass


} // namespace llvm

#endif // GET_SUBTARGETINFO_CTOR

#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS


#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS

#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS


#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS

