/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Calling Convention Implementation Fragment                                 *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#if !defined(GET_CC_REGISTER_LISTS)

bool llvm::CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
                            ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
bool llvm::CC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
                                            MVT LocVT, CCValAssign::LocInfo LocInfo,
                                            ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
bool llvm::CC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
                                    ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
bool llvm::CC_AArch64_Arm64EC_Thunk_Native(unsigned ValNo, MVT ValVT,
                                           MVT LocVT, CCValAssign::LocInfo LocInfo,
                                           ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
bool llvm::CC_AArch64_Arm64EC_VarArg(unsigned ValNo, MVT ValVT,
                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
                                     ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
bool llvm::CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT,
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
                                ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
bool llvm::CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT,
                                             MVT LocVT, CCValAssign::LocInfo LocInfo,
                                             ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
bool llvm::CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT,
                                       MVT LocVT, CCValAssign::LocInfo LocInfo,
                                       ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
bool llvm::CC_AArch64_GHC(unsigned ValNo, MVT ValVT,
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
                          ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
bool llvm::CC_AArch64_Preserve_None(unsigned ValNo, MVT ValVT,
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
                                    ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
bool llvm::CC_AArch64_Win64PCS(unsigned ValNo, MVT ValVT,
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
                               ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
bool llvm::CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT,
                                          MVT LocVT, CCValAssign::LocInfo LocInfo,
                                          ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
bool llvm::CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT,
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
                                   ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
bool llvm::RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
                               ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
bool llvm::RetCC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
                                               MVT LocVT, CCValAssign::LocInfo LocInfo,
                                               ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
bool llvm::RetCC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
                                       MVT LocVT, CCValAssign::LocInfo LocInfo,
                                       ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);


bool llvm::CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
                            ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {

  if (ArgFlags.isNest()) {
    if (MCRegister Reg = State.AllocateReg(AArch64::X15)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::iPTR) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::v2f32) {
    LocVT = MVT::v2i32;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::v2f64 ||
      LocVT == MVT::v4f32) {
    LocVT = MVT::v2i64;
    LocInfo = CCValAssign::BCvt;
  }

  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
    if (LocVT == MVT::v2i32 ||
        LocVT == MVT::v2f32 ||
        LocVT == MVT::v4i16 ||
        LocVT == MVT::v4f16 ||
        LocVT == MVT::v4bf16 ||
        LocVT == MVT::v8i8) {
      LocVT = MVT::f64;
      LocInfo = CCValAssign::BCvt;
    }
  }

  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
    if (LocVT == MVT::v2i64 ||
        LocVT == MVT::v2f64 ||
        LocVT == MVT::v4i32 ||
        LocVT == MVT::v4f32 ||
        LocVT == MVT::v8i16 ||
        LocVT == MVT::v8f16 ||
        LocVT == MVT::v8bf16 ||
        LocVT == MVT::v16i8) {
      LocVT = MVT::f128;
      LocInfo = CCValAssign::BCvt;
    }
  }

  if (ArgFlags.isInReg()) {
    if (LocVT == MVT::i64) {
      if (ArgFlags.isSRet()) {
        if (LocVT == MVT::i64) {
          static const MCPhysReg RegList1[] = {
            AArch64::X0, AArch64::X1
          };
          if (MCRegister Reg = State.AllocateReg(RegList1)) {
            State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
            return false;
          }
        }
      }
    }
  }

  if (ArgFlags.isSRet()) {
    if (LocVT == MVT::i64) {
      if (MCRegister Reg = State.AllocateReg(AArch64::X8)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (ArgFlags.isByVal()) {
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, Align(8), ArgFlags);
    return false;
  }

  if (ArgFlags.isSwiftSelf()) {
    if (LocVT == MVT::i64) {
      if (MCRegister Reg = State.AllocateReg(AArch64::X20)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (ArgFlags.isSwiftError()) {
    if (LocVT == MVT::i64) {
      if (MCRegister Reg = State.AllocateReg(AArch64::X21)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (ArgFlags.isSwiftAsync()) {
    if (LocVT == MVT::i64) {
      if (MCRegister Reg = State.AllocateReg(AArch64::X22)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (ArgFlags.isInConsecutiveRegs()) {
    if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
      return false;
  }

  if (LocVT == MVT::nxv16i8 ||
      LocVT == MVT::nxv8i16 ||
      LocVT == MVT::nxv4i32 ||
      LocVT == MVT::nxv2i64 ||
      LocVT == MVT::nxv2f16 ||
      LocVT == MVT::nxv4f16 ||
      LocVT == MVT::nxv8f16 ||
      LocVT == MVT::nxv2bf16 ||
      LocVT == MVT::nxv4bf16 ||
      LocVT == MVT::nxv8bf16 ||
      LocVT == MVT::nxv2f32 ||
      LocVT == MVT::nxv4f32 ||
      LocVT == MVT::nxv2f64) {
    static const MCPhysReg RegList2[] = {
      AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
    };
    if (MCRegister Reg = State.AllocateReg(RegList2)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::nxv16i8 ||
      LocVT == MVT::nxv8i16 ||
      LocVT == MVT::nxv4i32 ||
      LocVT == MVT::nxv2i64 ||
      LocVT == MVT::nxv2f16 ||
      LocVT == MVT::nxv4f16 ||
      LocVT == MVT::nxv8f16 ||
      LocVT == MVT::nxv2bf16 ||
      LocVT == MVT::nxv4bf16 ||
      LocVT == MVT::nxv8bf16 ||
      LocVT == MVT::nxv2f32 ||
      LocVT == MVT::nxv4f32 ||
      LocVT == MVT::nxv2f64) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::Indirect;
  }

  if (LocVT == MVT::nxv1i1 ||
      LocVT == MVT::nxv2i1 ||
      LocVT == MVT::nxv4i1 ||
      LocVT == MVT::nxv8i1 ||
      LocVT == MVT::nxv16i1 ||
      LocVT == MVT::aarch64svcount) {
    static const MCPhysReg RegList3[] = {
      AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
    };
    if (MCRegister Reg = State.AllocateReg(RegList3)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::nxv1i1 ||
      LocVT == MVT::nxv2i1 ||
      LocVT == MVT::nxv4i1 ||
      LocVT == MVT::nxv8i1 ||
      LocVT == MVT::nxv16i1 ||
      LocVT == MVT::aarch64svcount) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::Indirect;
  }

  if (LocVT == MVT::i1 ||
      LocVT == MVT::i8 ||
      LocVT == MVT::i16) {
    LocVT = MVT::i32;
    if (ArgFlags.isSExt())
      LocInfo = CCValAssign::SExt;
    else if (ArgFlags.isZExt())
      LocInfo = CCValAssign::ZExt;
    else
      LocInfo = CCValAssign::AExt;
  }

  if (LocVT == MVT::i32) {
    static const MCPhysReg RegList4[] = {
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
    };
    if (MCRegister Reg = State.AllocateReg(RegList4)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i64) {
    if (ArgFlags.isSplit()) {
      static const MCPhysReg RegList5[] = {
        AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6
      };
      static const MCPhysReg RegList6[] = {
        AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5
      };
      if (MCRegister Reg = State.AllocateReg(RegList5, RegList6)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (LocVT == MVT::i64) {
    if (ArgFlags.isSplit()) {
      static const MCPhysReg ShadowRegList7[] = {
        AArch64::X7
      };
      int64_t Offset8 = State.AllocateStack(8, Align(16), ShadowRegList7);
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i64) {
    static const MCPhysReg RegList9[] = {
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
    };
    if (MCRegister Reg = State.AllocateReg(RegList9)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f16) {
    static const MCPhysReg RegList10[] = {
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
    };
    if (MCRegister Reg = State.AllocateReg(RegList10)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::bf16) {
    static const MCPhysReg RegList11[] = {
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
    };
    if (MCRegister Reg = State.AllocateReg(RegList11)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f32) {
    static const MCPhysReg RegList12[] = {
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
    };
    if (MCRegister Reg = State.AllocateReg(RegList12)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f64) {
    static const MCPhysReg RegList13[] = {
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
    };
    if (MCRegister Reg = State.AllocateReg(RegList13)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::v1i64 ||
      LocVT == MVT::v2i32 ||
      LocVT == MVT::v4i16 ||
      LocVT == MVT::v8i8 ||
      LocVT == MVT::v1f64 ||
      LocVT == MVT::v2f32 ||
      LocVT == MVT::v4f16 ||
      LocVT == MVT::v4bf16) {
    static const MCPhysReg RegList14[] = {
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
    };
    if (MCRegister Reg = State.AllocateReg(RegList14)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f128 ||
      LocVT == MVT::v2i64 ||
      LocVT == MVT::v4i32 ||
      LocVT == MVT::v8i16 ||
      LocVT == MVT::v16i8 ||
      LocVT == MVT::v4f32 ||
      LocVT == MVT::v2f64 ||
      LocVT == MVT::v8f16 ||
      LocVT == MVT::v8bf16) {
    static const MCPhysReg RegList15[] = {
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
    };
    if (MCRegister Reg = State.AllocateReg(RegList15)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i1 ||
      LocVT == MVT::i8 ||
      LocVT == MVT::i16 ||
      LocVT == MVT::f16 ||
      LocVT == MVT::bf16) {
    int64_t Offset16 = State.AllocateStack(8, Align(8));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo));
    return false;
  }

  if (LocVT == MVT::i32 ||
      LocVT == MVT::f32) {
    int64_t Offset17 = State.AllocateStack(8, Align(8));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset17, LocVT, LocInfo));
    return false;
  }

  if (LocVT == MVT::i64 ||
      LocVT == MVT::f64 ||
      LocVT == MVT::v1f64 ||
      LocVT == MVT::v2f32 ||
      LocVT == MVT::v1i64 ||
      LocVT == MVT::v2i32 ||
      LocVT == MVT::v4i16 ||
      LocVT == MVT::v8i8 ||
      LocVT == MVT::v4f16 ||
      LocVT == MVT::v4bf16) {
    int64_t Offset18 = State.AllocateStack(8, Align(8));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo));
    return false;
  }

  if (LocVT == MVT::f128 ||
      LocVT == MVT::v2i64 ||
      LocVT == MVT::v4i32 ||
      LocVT == MVT::v8i16 ||
      LocVT == MVT::v16i8 ||
      LocVT == MVT::v4f32 ||
      LocVT == MVT::v2f64 ||
      LocVT == MVT::v8f16 ||
      LocVT == MVT::v8bf16) {
    int64_t Offset19 = State.AllocateStack(16, Align(16));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo));
    return false;
  }

  return true; // CC didn't match.
}


bool llvm::CC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
                                            MVT LocVT, CCValAssign::LocInfo LocInfo,
                                            ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {

  if (LocVT == MVT::i64) {
    static const MCPhysReg RegList1[] = {
      AArch64::X11, AArch64::X10, AArch64::X9
    };
    if (MCRegister Reg = State.AllocateReg(RegList1)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  return true; // CC didn't match.
}


bool llvm::CC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
                                    ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {

  if (ArgFlags.isInReg()) {
    if (LocVT == MVT::i64) {
      if (MCRegister Reg = State.AllocateReg(AArch64::X4)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (ArgFlags.isByVal()) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::Indirect;
  }

  if (LocVT == MVT::i1 ||
      LocVT == MVT::i8 ||
      LocVT == MVT::i16) {
    LocVT = MVT::i32;
    if (ArgFlags.isSExt())
      LocInfo = CCValAssign::SExt;
    else if (ArgFlags.isZExt())
      LocInfo = CCValAssign::ZExt;
    else
      LocInfo = CCValAssign::AExt;
  }

  if (ArgFlags.isNest()) {
    if (MCRegister Reg = State.AllocateReg(AArch64::X4)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (ArgFlags.isSwiftError()) {
    if (LocVT == MVT::i64) {
      if (MCRegister Reg = State.AllocateReg(AArch64::X19)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (ArgFlags.isSwiftSelf()) {
    if (LocVT == MVT::i64) {
      if (MCRegister Reg = State.AllocateReg(AArch64::X20)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (ArgFlags.isSwiftAsync()) {
    if (LocVT == MVT::i64) {
      if (MCRegister Reg = State.AllocateReg(AArch64::X21)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (ArgFlags.isCFGuardTarget()) {
    if (MCRegister Reg = State.AllocateReg(AArch64::X8)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::v16i8 ||
      LocVT == MVT::v8i16 ||
      LocVT == MVT::v4i32 ||
      LocVT == MVT::v2i64 ||
      LocVT == MVT::v8f16 ||
      LocVT == MVT::v4f32 ||
      LocVT == MVT::v2f64) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::Indirect;
  }

  if (LocVT == MVT::v32i8 ||
      LocVT == MVT::v16i16 ||
      LocVT == MVT::v8i32 ||
      LocVT == MVT::v4i64 ||
      LocVT == MVT::v16f16 ||
      LocVT == MVT::v8f32 ||
      LocVT == MVT::v4f64) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::Indirect;
  }

  if (LocVT == MVT::v64i8 ||
      LocVT == MVT::v32i16 ||
      LocVT == MVT::v16i32 ||
      LocVT == MVT::v32f16 ||
      LocVT == MVT::v16f32 ||
      LocVT == MVT::v8f64 ||
      LocVT == MVT::v8i64) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::Indirect;
  }

  if (LocVT == MVT::f80) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::Indirect;
  }

  if (LocVT == MVT::x86mmx) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::f16) {
    static const MCPhysReg RegList1[] = {
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3
    };
    static const MCPhysReg RegList2[] = {
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
    };
    if (MCRegister Reg = State.AllocateReg(RegList1, RegList2)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f32) {
    static const MCPhysReg RegList3[] = {
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3
    };
    static const MCPhysReg RegList4[] = {
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
    };
    if (MCRegister Reg = State.AllocateReg(RegList3, RegList4)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f64) {
    static const MCPhysReg RegList5[] = {
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3
    };
    static const MCPhysReg RegList6[] = {
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
    };
    if (MCRegister Reg = State.AllocateReg(RegList5, RegList6)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i32) {
    static const MCPhysReg RegList7[] = {
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3
    };
    static const MCPhysReg RegList8[] = {
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3
    };
    if (MCRegister Reg = State.AllocateReg(RegList7, RegList8)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i64) {
    if (MCRegister Reg = State.AllocateReg(AArch64::X9)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i64) {
    static const MCPhysReg RegList9[] = {
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
    };
    static const MCPhysReg RegList10[] = {
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3
    };
    if (MCRegister Reg = State.AllocateReg(RegList9, RegList10)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i8 ||
      LocVT == MVT::i16 ||
      LocVT == MVT::i32 ||
      LocVT == MVT::i64 ||
      LocVT == MVT::f16 ||
      LocVT == MVT::f32 ||
      LocVT == MVT::f64) {
    int64_t Offset11 = State.AllocateStack(8, Align(8));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
    return false;
  }

  return true; // CC didn't match.
}


bool llvm::CC_AArch64_Arm64EC_Thunk_Native(unsigned ValNo, MVT ValVT,
                                           MVT LocVT, CCValAssign::LocInfo LocInfo,
                                           ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {

  if (LocVT == MVT::i64) {
    if (MCRegister Reg = State.AllocateReg(AArch64::X9)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
    return false;

  return true; // CC didn't match.
}


bool llvm::CC_AArch64_Arm64EC_VarArg(unsigned ValNo, MVT ValVT,
                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
                                     ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {

  if (ArgFlags.isCFGuardTarget()) {
    if (MCRegister Reg = State.AllocateReg(AArch64::X9)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (ArgFlags.isNest()) {
    if (MCRegister Reg = State.AllocateReg(AArch64::X15)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f16 ||
      LocVT == MVT::bf16) {
    LocVT = MVT::i16;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::f32) {
    LocVT = MVT::i32;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::f64 ||
      LocVT == MVT::v1f64 ||
      LocVT == MVT::v1i64 ||
      LocVT == MVT::v2f32 ||
      LocVT == MVT::v2i32 ||
      LocVT == MVT::v4i16 ||
      LocVT == MVT::v4f16 ||
      LocVT == MVT::v4bf16 ||
      LocVT == MVT::v8i8 ||
      LocVT == MVT::iPTR) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::f128 ||
      LocVT == MVT::v2f64 ||
      LocVT == MVT::v2i64 ||
      LocVT == MVT::v4i32 ||
      LocVT == MVT::v4f32 ||
      LocVT == MVT::v8i16 ||
      LocVT == MVT::v8f16 ||
      LocVT == MVT::v8bf16 ||
      LocVT == MVT::v16i8) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::Indirect;
  }

  if (LocVT == MVT::nxv16i8 ||
      LocVT == MVT::nxv8i16 ||
      LocVT == MVT::nxv4i32 ||
      LocVT == MVT::nxv2i64 ||
      LocVT == MVT::nxv2f16 ||
      LocVT == MVT::nxv4f16 ||
      LocVT == MVT::nxv8f16 ||
      LocVT == MVT::nxv2bf16 ||
      LocVT == MVT::nxv4bf16 ||
      LocVT == MVT::nxv8bf16 ||
      LocVT == MVT::nxv2f32 ||
      LocVT == MVT::nxv4f32 ||
      LocVT == MVT::nxv2f64) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::Indirect;
  }

  if (LocVT == MVT::nxv2i1 ||
      LocVT == MVT::nxv4i1 ||
      LocVT == MVT::nxv8i1 ||
      LocVT == MVT::nxv16i1) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::Indirect;
  }

  if (ArgFlags.isInReg()) {
    if (LocVT == MVT::i64) {
      if (ArgFlags.isSRet()) {
        if (LocVT == MVT::i64) {
          static const MCPhysReg RegList1[] = {
            AArch64::X0, AArch64::X1
          };
          if (MCRegister Reg = State.AllocateReg(RegList1)) {
            State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
            return false;
          }
        }
      }
    }
  }

  if (ArgFlags.isSRet()) {
    if (LocVT == MVT::i64) {
      if (MCRegister Reg = State.AllocateReg(AArch64::X8)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (ArgFlags.isByVal()) {
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, Align(8), ArgFlags);
    return false;
  }

  if (LocVT == MVT::i1 ||
      LocVT == MVT::i8 ||
      LocVT == MVT::i16) {
    LocVT = MVT::i32;
    if (ArgFlags.isSExt())
      LocInfo = CCValAssign::SExt;
    else if (ArgFlags.isZExt())
      LocInfo = CCValAssign::ZExt;
    else
      LocInfo = CCValAssign::AExt;
  }

  if (LocVT == MVT::i32) {
    static const MCPhysReg RegList2[] = {
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3
    };
    if (MCRegister Reg = State.AllocateReg(RegList2)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i64) {
    static const MCPhysReg RegList3[] = {
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
    };
    if (MCRegister Reg = State.AllocateReg(RegList3)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i32 ||
      LocVT == MVT::i64) {
    int64_t Offset4 = State.AllocateStack(8, Align(8));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
    return false;
  }

  return true; // CC didn't match.
}


bool llvm::CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT,
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
                                ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {

  if (ArgFlags.isNest()) {
    if (MCRegister Reg = State.AllocateReg(AArch64::X15)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::iPTR) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::v2f32) {
    LocVT = MVT::v2i32;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::v2f64 ||
      LocVT == MVT::v4f32 ||
      LocVT == MVT::f128) {
    LocVT = MVT::v2i64;
    LocInfo = CCValAssign::BCvt;
  }

  if (ArgFlags.isSRet()) {
    if (LocVT == MVT::i64) {
      if (MCRegister Reg = State.AllocateReg(AArch64::X8)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (ArgFlags.isByVal()) {
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, Align(8), ArgFlags);
    return false;
  }

  if (ArgFlags.isSwiftSelf()) {
    if (LocVT == MVT::i64) {
      if (MCRegister Reg = State.AllocateReg(AArch64::X20)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (ArgFlags.isSwiftError()) {
    if (LocVT == MVT::i64) {
      if (MCRegister Reg = State.AllocateReg(AArch64::X21)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (ArgFlags.isSwiftAsync()) {
    if (LocVT == MVT::i64) {
      if (MCRegister Reg = State.AllocateReg(AArch64::X22)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (ArgFlags.isInConsecutiveRegs()) {
    if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
      return false;
  }

  if (LocVT == MVT::nxv16i8 ||
      LocVT == MVT::nxv8i16 ||
      LocVT == MVT::nxv4i32 ||
      LocVT == MVT::nxv2i64 ||
      LocVT == MVT::nxv2f16 ||
      LocVT == MVT::nxv4f16 ||
      LocVT == MVT::nxv8f16 ||
      LocVT == MVT::nxv2bf16 ||
      LocVT == MVT::nxv4bf16 ||
      LocVT == MVT::nxv8bf16 ||
      LocVT == MVT::nxv2f32 ||
      LocVT == MVT::nxv4f32 ||
      LocVT == MVT::nxv2f64) {
    static const MCPhysReg RegList1[] = {
      AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
    };
    if (MCRegister Reg = State.AllocateReg(RegList1)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::nxv16i8 ||
      LocVT == MVT::nxv8i16 ||
      LocVT == MVT::nxv4i32 ||
      LocVT == MVT::nxv2i64 ||
      LocVT == MVT::nxv2f16 ||
      LocVT == MVT::nxv4f16 ||
      LocVT == MVT::nxv8f16 ||
      LocVT == MVT::nxv2bf16 ||
      LocVT == MVT::nxv4bf16 ||
      LocVT == MVT::nxv8bf16 ||
      LocVT == MVT::nxv2f32 ||
      LocVT == MVT::nxv4f32 ||
      LocVT == MVT::nxv2f64) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::Indirect;
  }

  if (LocVT == MVT::nxv1i1 ||
      LocVT == MVT::nxv2i1 ||
      LocVT == MVT::nxv4i1 ||
      LocVT == MVT::nxv8i1 ||
      LocVT == MVT::nxv16i1 ||
      LocVT == MVT::aarch64svcount) {
    static const MCPhysReg RegList2[] = {
      AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
    };
    if (MCRegister Reg = State.AllocateReg(RegList2)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::nxv1i1 ||
      LocVT == MVT::nxv2i1 ||
      LocVT == MVT::nxv4i1 ||
      LocVT == MVT::nxv8i1 ||
      LocVT == MVT::nxv16i1 ||
      LocVT == MVT::aarch64svcount) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::Indirect;
  }

  if (LocVT == MVT::i1 ||
      LocVT == MVT::i8 ||
      LocVT == MVT::i16) {
    LocVT = MVT::i32;
    if (ArgFlags.isSExt())
      LocInfo = CCValAssign::SExt;
    else if (ArgFlags.isZExt())
      LocInfo = CCValAssign::ZExt;
    else
      LocInfo = CCValAssign::AExt;
  }

  if (LocVT == MVT::i32) {
    static const MCPhysReg RegList3[] = {
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
    };
    if (MCRegister Reg = State.AllocateReg(RegList3)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i64) {
    if (ArgFlags.isSplit()) {
      static const MCPhysReg RegList4[] = {
        AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6
      };
      if (MCRegister Reg = State.AllocateReg(RegList4)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (LocVT == MVT::i64) {
    if (ArgFlags.isSplit()) {
      static const MCPhysReg ShadowRegList5[] = {
        AArch64::X7
      };
      int64_t Offset6 = State.AllocateStack(8, Align(16), ShadowRegList5);
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i64) {
    static const MCPhysReg RegList7[] = {
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
    };
    if (MCRegister Reg = State.AllocateReg(RegList7)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f16) {
    static const MCPhysReg RegList8[] = {
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
    };
    if (MCRegister Reg = State.AllocateReg(RegList8)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::bf16) {
    static const MCPhysReg RegList9[] = {
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
    };
    if (MCRegister Reg = State.AllocateReg(RegList9)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f32) {
    static const MCPhysReg RegList10[] = {
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
    };
    if (MCRegister Reg = State.AllocateReg(RegList10)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f64) {
    static const MCPhysReg RegList11[] = {
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
    };
    if (MCRegister Reg = State.AllocateReg(RegList11)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::v1i64 ||
      LocVT == MVT::v2i32 ||
      LocVT == MVT::v4i16 ||
      LocVT == MVT::v8i8 ||
      LocVT == MVT::v1f64 ||
      LocVT == MVT::v2f32 ||
      LocVT == MVT::v4f16 ||
      LocVT == MVT::v4bf16) {
    static const MCPhysReg RegList12[] = {
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
    };
    if (MCRegister Reg = State.AllocateReg(RegList12)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::v2i64 ||
      LocVT == MVT::v4i32 ||
      LocVT == MVT::v8i16 ||
      LocVT == MVT::v16i8 ||
      LocVT == MVT::v4f32 ||
      LocVT == MVT::v2f64 ||
      LocVT == MVT::v8f16 ||
      LocVT == MVT::v8bf16) {
    static const MCPhysReg RegList13[] = {
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
    };
    if (MCRegister Reg = State.AllocateReg(RegList13)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (ValVT == MVT::i1 || ValVT == MVT::i8) {
    int64_t Offset14 = State.AllocateStack(1, Align(1));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
    return false;
  }

  if (ValVT == MVT::i16 || ValVT == MVT::f16 || ValVT == MVT::bf16) {
    int64_t Offset15 = State.AllocateStack(2, Align(2));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo));
    return false;
  }

  if (LocVT == MVT::i32 ||
      LocVT == MVT::f32) {
    int64_t Offset16 = State.AllocateStack(4, Align(4));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo));
    return false;
  }

  if (ArgFlags.isPointer()) {
    if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) {
      LocVT = MVT::i32;
      LocInfo = CCValAssign::Trunc;
    }
  }

  if (ArgFlags.isPointer()) {
    if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) {
      int64_t Offset17 = State.AllocateStack(4, Align(4));
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset17, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i64 ||
      LocVT == MVT::f64 ||
      LocVT == MVT::v1f64 ||
      LocVT == MVT::v2f32 ||
      LocVT == MVT::v1i64 ||
      LocVT == MVT::v2i32 ||
      LocVT == MVT::v4i16 ||
      LocVT == MVT::v8i8 ||
      LocVT == MVT::v4f16 ||
      LocVT == MVT::v4bf16) {
    int64_t Offset18 = State.AllocateStack(8, Align(8));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo));
    return false;
  }

  if (LocVT == MVT::v2i64 ||
      LocVT == MVT::v4i32 ||
      LocVT == MVT::v8i16 ||
      LocVT == MVT::v16i8 ||
      LocVT == MVT::v4f32 ||
      LocVT == MVT::v2f64 ||
      LocVT == MVT::v8f16 ||
      LocVT == MVT::v8bf16) {
    int64_t Offset19 = State.AllocateStack(16, Align(16));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo));
    return false;
  }

  return true; // CC didn't match.
}


bool llvm::CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT,
                                             MVT LocVT, CCValAssign::LocInfo LocInfo,
                                             ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {

  if (ArgFlags.isNest()) {
    if (MCRegister Reg = State.AllocateReg(AArch64::X15)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::v2f32) {
    LocVT = MVT::v2i32;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::v2f64 ||
      LocVT == MVT::v4f32 ||
      LocVT == MVT::f128) {
    LocVT = MVT::v2i64;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::i8 ||
      LocVT == MVT::i16) {
    LocVT = MVT::i32;
    if (ArgFlags.isSExt())
      LocInfo = CCValAssign::SExt;
    else if (ArgFlags.isZExt())
      LocInfo = CCValAssign::ZExt;
    else
      LocInfo = CCValAssign::AExt;
  }

  if (LocVT == MVT::f16 ||
      LocVT == MVT::bf16) {
    LocVT = MVT::f32;
    LocInfo = CCValAssign::FPExt;
  }

  if (ArgFlags.isPointer()) {
    if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) {
      LocVT = MVT::i32;
      LocInfo = CCValAssign::Trunc;
    }
  }

  if (LocVT == MVT::i32 ||
      LocVT == MVT::f32) {
    int64_t Offset1 = State.AllocateStack(4, Align(4));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
    return false;
  }

  if (LocVT == MVT::i64) {
    if (ArgFlags.isSplit()) {
      int64_t Offset2 = State.AllocateStack(8, Align(16));
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i64 ||
      LocVT == MVT::f64 ||
      LocVT == MVT::v1i64 ||
      LocVT == MVT::v2i32 ||
      LocVT == MVT::v4i16 ||
      LocVT == MVT::v8i8 ||
      LocVT == MVT::v1f64 ||
      LocVT == MVT::v2f32 ||
      LocVT == MVT::v4f16 ||
      LocVT == MVT::v4bf16) {
    int64_t Offset3 = State.AllocateStack(8, Align(8));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
    return false;
  }

  if (LocVT == MVT::v2i64 ||
      LocVT == MVT::v4i32 ||
      LocVT == MVT::v8i16 ||
      LocVT == MVT::v16i8 ||
      LocVT == MVT::v4f32 ||
      LocVT == MVT::v2f64 ||
      LocVT == MVT::v8f16 ||
      LocVT == MVT::v8bf16) {
    int64_t Offset4 = State.AllocateStack(16, Align(16));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
    return false;
  }

  return true; // CC didn't match.
}


bool llvm::CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT,
                                       MVT LocVT, CCValAssign::LocInfo LocInfo,
                                       ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {

  if (ArgFlags.isNest()) {
    if (MCRegister Reg = State.AllocateReg(AArch64::X15)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::iPTR) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::v2f32) {
    LocVT = MVT::v2i32;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::v2f64 ||
      LocVT == MVT::v4f32 ||
      LocVT == MVT::f128) {
    LocVT = MVT::v2i64;
    LocInfo = CCValAssign::BCvt;
  }

  if (ArgFlags.isInConsecutiveRegs()) {
    if (CC_AArch64_Custom_Stack_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
      return false;
  }

  if (LocVT == MVT::i8 ||
      LocVT == MVT::i16 ||
      LocVT == MVT::i32) {
    LocVT = MVT::i64;
    if (ArgFlags.isSExt())
      LocInfo = CCValAssign::SExt;
    else if (ArgFlags.isZExt())
      LocInfo = CCValAssign::ZExt;
    else
      LocInfo = CCValAssign::AExt;
  }

  if (LocVT == MVT::f16 ||
      LocVT == MVT::bf16 ||
      LocVT == MVT::f32) {
    LocVT = MVT::f64;
    LocInfo = CCValAssign::FPExt;
  }

  if (LocVT == MVT::i64) {
    if (ArgFlags.isSplit()) {
      int64_t Offset1 = State.AllocateStack(8, Align(16));
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i64 ||
      LocVT == MVT::f64 ||
      LocVT == MVT::v1i64 ||
      LocVT == MVT::v2i32 ||
      LocVT == MVT::v4i16 ||
      LocVT == MVT::v8i8 ||
      LocVT == MVT::v1f64 ||
      LocVT == MVT::v2f32 ||
      LocVT == MVT::v4f16 ||
      LocVT == MVT::v4bf16) {
    int64_t Offset2 = State.AllocateStack(8, Align(8));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
    return false;
  }

  if (LocVT == MVT::v2i64 ||
      LocVT == MVT::v4i32 ||
      LocVT == MVT::v8i16 ||
      LocVT == MVT::v16i8 ||
      LocVT == MVT::v4f32 ||
      LocVT == MVT::v2f64 ||
      LocVT == MVT::v8f16 ||
      LocVT == MVT::v8bf16) {
    int64_t Offset3 = State.AllocateStack(16, Align(16));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
    return false;
  }

  return true; // CC didn't match.
}


bool llvm::CC_AArch64_GHC(unsigned ValNo, MVT ValVT,
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
                          ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {

  if (ArgFlags.isNest()) {
    if (MCRegister Reg = State.AllocateReg(AArch64::X15)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::iPTR) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::v1i64 ||
      LocVT == MVT::v2i32 ||
      LocVT == MVT::v4i16 ||
      LocVT == MVT::v8i8 ||
      LocVT == MVT::v2f32) {
    LocVT = MVT::f64;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::v2i64 ||
      LocVT == MVT::v4i32 ||
      LocVT == MVT::v8i16 ||
      LocVT == MVT::v16i8 ||
      LocVT == MVT::v4f32 ||
      LocVT == MVT::f128) {
    LocVT = MVT::v2f64;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::v2f64) {
    static const MCPhysReg RegList1[] = {
      AArch64::Q4, AArch64::Q5
    };
    if (MCRegister Reg = State.AllocateReg(RegList1)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f32) {
    static const MCPhysReg RegList2[] = {
      AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11
    };
    if (MCRegister Reg = State.AllocateReg(RegList2)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f64) {
    static const MCPhysReg RegList3[] = {
      AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15
    };
    if (MCRegister Reg = State.AllocateReg(RegList3)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i8 ||
      LocVT == MVT::i16 ||
      LocVT == MVT::i32) {
    LocVT = MVT::i64;
    if (ArgFlags.isSExt())
      LocInfo = CCValAssign::SExt;
    else if (ArgFlags.isZExt())
      LocInfo = CCValAssign::ZExt;
    else
      LocInfo = CCValAssign::AExt;
  }

  if (LocVT == MVT::i64) {
    static const MCPhysReg RegList4[] = {
      AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28
    };
    if (MCRegister Reg = State.AllocateReg(RegList4)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  return true; // CC didn't match.
}


bool llvm::CC_AArch64_Preserve_None(unsigned ValNo, MVT ValVT,
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
                                    ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {

  if (State.isVarArg()) {
    if (State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetDarwin()) {
      if (!CC_AArch64_DarwinPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
        return false;
    }
  }

  if (State.isVarArg()) {
    if (State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()) {
      if (!CC_AArch64_Win64PCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
        return false;
    }
  }

  if (State.isVarArg()) {
    if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
      return false;
  }

  if (LocVT == MVT::i32) {
    static const MCPhysReg RegList1[] = {
      AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W9
    };
    if (MCRegister Reg = State.AllocateReg(RegList1)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i64) {
    static const MCPhysReg RegList2[] = {
      AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X9
    };
    if (MCRegister Reg = State.AllocateReg(RegList2)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (!State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()) {
    if (LocVT == MVT::i32) {
      if (MCRegister Reg = State.AllocateReg(AArch64::W15)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (!State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()) {
    if (LocVT == MVT::i64) {
      if (MCRegister Reg = State.AllocateReg(AArch64::X15)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
    return false;

  return true; // CC didn't match.
}


bool llvm::CC_AArch64_Win64PCS(unsigned ValNo, MVT ValVT,
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
                               ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {

  if (ArgFlags.isCFGuardTarget()) {
    if (MCRegister Reg = State.AllocateReg(AArch64::X9)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (ArgFlags.isNest()) {
    if (MCRegister Reg = State.AllocateReg(AArch64::X15)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::iPTR) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::v2f32) {
    LocVT = MVT::v2i32;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::v2f64 ||
      LocVT == MVT::v4f32) {
    LocVT = MVT::v2i64;
    LocInfo = CCValAssign::BCvt;
  }

  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
    if (LocVT == MVT::v2i32 ||
        LocVT == MVT::v2f32 ||
        LocVT == MVT::v4i16 ||
        LocVT == MVT::v4f16 ||
        LocVT == MVT::v4bf16 ||
        LocVT == MVT::v8i8) {
      LocVT = MVT::f64;
      LocInfo = CCValAssign::BCvt;
    }
  }

  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
    if (LocVT == MVT::v2i64 ||
        LocVT == MVT::v2f64 ||
        LocVT == MVT::v4i32 ||
        LocVT == MVT::v4f32 ||
        LocVT == MVT::v8i16 ||
        LocVT == MVT::v8f16 ||
        LocVT == MVT::v8bf16 ||
        LocVT == MVT::v16i8) {
      LocVT = MVT::f128;
      LocInfo = CCValAssign::BCvt;
    }
  }

  if (ArgFlags.isInReg()) {
    if (LocVT == MVT::i64) {
      if (ArgFlags.isSRet()) {
        if (LocVT == MVT::i64) {
          static const MCPhysReg RegList1[] = {
            AArch64::X0, AArch64::X1
          };
          if (MCRegister Reg = State.AllocateReg(RegList1)) {
            State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
            return false;
          }
        }
      }
    }
  }

  if (ArgFlags.isSRet()) {
    if (LocVT == MVT::i64) {
      if (MCRegister Reg = State.AllocateReg(AArch64::X8)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (ArgFlags.isByVal()) {
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, Align(8), ArgFlags);
    return false;
  }

  if (ArgFlags.isSwiftSelf()) {
    if (LocVT == MVT::i64) {
      if (MCRegister Reg = State.AllocateReg(AArch64::X20)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (ArgFlags.isSwiftError()) {
    if (LocVT == MVT::i64) {
      if (MCRegister Reg = State.AllocateReg(AArch64::X21)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (ArgFlags.isSwiftAsync()) {
    if (LocVT == MVT::i64) {
      if (MCRegister Reg = State.AllocateReg(AArch64::X22)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (ArgFlags.isInConsecutiveRegs()) {
    if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
      return false;
  }

  if (LocVT == MVT::nxv16i8 ||
      LocVT == MVT::nxv8i16 ||
      LocVT == MVT::nxv4i32 ||
      LocVT == MVT::nxv2i64 ||
      LocVT == MVT::nxv2f16 ||
      LocVT == MVT::nxv4f16 ||
      LocVT == MVT::nxv8f16 ||
      LocVT == MVT::nxv2bf16 ||
      LocVT == MVT::nxv4bf16 ||
      LocVT == MVT::nxv8bf16 ||
      LocVT == MVT::nxv2f32 ||
      LocVT == MVT::nxv4f32 ||
      LocVT == MVT::nxv2f64) {
    static const MCPhysReg RegList2[] = {
      AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
    };
    if (MCRegister Reg = State.AllocateReg(RegList2)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::nxv16i8 ||
      LocVT == MVT::nxv8i16 ||
      LocVT == MVT::nxv4i32 ||
      LocVT == MVT::nxv2i64 ||
      LocVT == MVT::nxv2f16 ||
      LocVT == MVT::nxv4f16 ||
      LocVT == MVT::nxv8f16 ||
      LocVT == MVT::nxv2bf16 ||
      LocVT == MVT::nxv4bf16 ||
      LocVT == MVT::nxv8bf16 ||
      LocVT == MVT::nxv2f32 ||
      LocVT == MVT::nxv4f32 ||
      LocVT == MVT::nxv2f64) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::Indirect;
  }

  if (LocVT == MVT::nxv1i1 ||
      LocVT == MVT::nxv2i1 ||
      LocVT == MVT::nxv4i1 ||
      LocVT == MVT::nxv8i1 ||
      LocVT == MVT::nxv16i1 ||
      LocVT == MVT::aarch64svcount) {
    static const MCPhysReg RegList3[] = {
      AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
    };
    if (MCRegister Reg = State.AllocateReg(RegList3)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::nxv1i1 ||
      LocVT == MVT::nxv2i1 ||
      LocVT == MVT::nxv4i1 ||
      LocVT == MVT::nxv8i1 ||
      LocVT == MVT::nxv16i1 ||
      LocVT == MVT::aarch64svcount) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::Indirect;
  }

  if (LocVT == MVT::i1 ||
      LocVT == MVT::i8 ||
      LocVT == MVT::i16) {
    LocVT = MVT::i32;
    if (ArgFlags.isSExt())
      LocInfo = CCValAssign::SExt;
    else if (ArgFlags.isZExt())
      LocInfo = CCValAssign::ZExt;
    else
      LocInfo = CCValAssign::AExt;
  }

  if (LocVT == MVT::i32) {
    static const MCPhysReg RegList4[] = {
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
    };
    if (MCRegister Reg = State.AllocateReg(RegList4)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i64) {
    if (ArgFlags.isSplit()) {
      static const MCPhysReg RegList5[] = {
        AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6
      };
      static const MCPhysReg RegList6[] = {
        AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5
      };
      if (MCRegister Reg = State.AllocateReg(RegList5, RegList6)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (LocVT == MVT::i64) {
    if (ArgFlags.isSplit()) {
      static const MCPhysReg ShadowRegList7[] = {
        AArch64::X7
      };
      int64_t Offset8 = State.AllocateStack(8, Align(16), ShadowRegList7);
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i64) {
    static const MCPhysReg RegList9[] = {
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
    };
    if (MCRegister Reg = State.AllocateReg(RegList9)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f16) {
    static const MCPhysReg RegList10[] = {
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
    };
    if (MCRegister Reg = State.AllocateReg(RegList10)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::bf16) {
    static const MCPhysReg RegList11[] = {
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
    };
    if (MCRegister Reg = State.AllocateReg(RegList11)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f32) {
    static const MCPhysReg RegList12[] = {
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
    };
    if (MCRegister Reg = State.AllocateReg(RegList12)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f64) {
    static const MCPhysReg RegList13[] = {
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
    };
    if (MCRegister Reg = State.AllocateReg(RegList13)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::v1i64 ||
      LocVT == MVT::v2i32 ||
      LocVT == MVT::v4i16 ||
      LocVT == MVT::v8i8 ||
      LocVT == MVT::v1f64 ||
      LocVT == MVT::v2f32 ||
      LocVT == MVT::v4f16 ||
      LocVT == MVT::v4bf16) {
    static const MCPhysReg RegList14[] = {
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
    };
    if (MCRegister Reg = State.AllocateReg(RegList14)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f128 ||
      LocVT == MVT::v2i64 ||
      LocVT == MVT::v4i32 ||
      LocVT == MVT::v8i16 ||
      LocVT == MVT::v16i8 ||
      LocVT == MVT::v4f32 ||
      LocVT == MVT::v2f64 ||
      LocVT == MVT::v8f16 ||
      LocVT == MVT::v8bf16) {
    static const MCPhysReg RegList15[] = {
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
    };
    if (MCRegister Reg = State.AllocateReg(RegList15)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i1 ||
      LocVT == MVT::i8 ||
      LocVT == MVT::i16 ||
      LocVT == MVT::f16 ||
      LocVT == MVT::bf16) {
    int64_t Offset16 = State.AllocateStack(8, Align(8));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo));
    return false;
  }

  if (LocVT == MVT::i32 ||
      LocVT == MVT::f32) {
    int64_t Offset17 = State.AllocateStack(8, Align(8));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset17, LocVT, LocInfo));
    return false;
  }

  if (LocVT == MVT::i64 ||
      LocVT == MVT::f64 ||
      LocVT == MVT::v1f64 ||
      LocVT == MVT::v2f32 ||
      LocVT == MVT::v1i64 ||
      LocVT == MVT::v2i32 ||
      LocVT == MVT::v4i16 ||
      LocVT == MVT::v8i8 ||
      LocVT == MVT::v4f16 ||
      LocVT == MVT::v4bf16) {
    int64_t Offset18 = State.AllocateStack(8, Align(8));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo));
    return false;
  }

  if (LocVT == MVT::f128 ||
      LocVT == MVT::v2i64 ||
      LocVT == MVT::v4i32 ||
      LocVT == MVT::v8i16 ||
      LocVT == MVT::v16i8 ||
      LocVT == MVT::v4f32 ||
      LocVT == MVT::v2f64 ||
      LocVT == MVT::v8f16 ||
      LocVT == MVT::v8bf16) {
    int64_t Offset19 = State.AllocateStack(16, Align(16));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo));
    return false;
  }

  return true; // CC didn't match.
}


bool llvm::CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT,
                                          MVT LocVT, CCValAssign::LocInfo LocInfo,
                                          ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {

  if (LocVT == MVT::i64) {
    if (MCRegister Reg = State.AllocateReg(AArch64::X15)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  return true; // CC didn't match.
}


bool llvm::CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT,
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
                                   ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {

  if (LocVT == MVT::f16 ||
      LocVT == MVT::bf16) {
    LocVT = MVT::i16;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::f32) {
    LocVT = MVT::i32;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::f64) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::BCvt;
  }

  if (!CC_AArch64_Win64PCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
    return false;

  return true; // CC didn't match.
}


bool llvm::RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
                               ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {

  if (LocVT == MVT::iPTR) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::v2f32) {
    LocVT = MVT::v2i32;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::v2f64 ||
      LocVT == MVT::v4f32) {
    LocVT = MVT::v2i64;
    LocInfo = CCValAssign::BCvt;
  }

  if (ArgFlags.isInConsecutiveRegs()) {
    if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
      return false;
  }

  if (ArgFlags.isSwiftError()) {
    if (LocVT == MVT::i64) {
      if (MCRegister Reg = State.AllocateReg(AArch64::X21)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
    if (LocVT == MVT::v2i32 ||
        LocVT == MVT::v2f32 ||
        LocVT == MVT::v4i16 ||
        LocVT == MVT::v4f16 ||
        LocVT == MVT::v4bf16 ||
        LocVT == MVT::v8i8) {
      LocVT = MVT::f64;
      LocInfo = CCValAssign::BCvt;
    }
  }

  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
    if (LocVT == MVT::v2i64 ||
        LocVT == MVT::v2f64 ||
        LocVT == MVT::v4i32 ||
        LocVT == MVT::v4f32 ||
        LocVT == MVT::v8i16 ||
        LocVT == MVT::v8f16 ||
        LocVT == MVT::v8bf16 ||
        LocVT == MVT::v16i8) {
      LocVT = MVT::f128;
      LocInfo = CCValAssign::BCvt;
    }
  }

  if (LocVT == MVT::i1 ||
      LocVT == MVT::i8 ||
      LocVT == MVT::i16) {
    LocVT = MVT::i32;
    if (ArgFlags.isSExt())
      LocInfo = CCValAssign::SExt;
    else if (ArgFlags.isZExt())
      LocInfo = CCValAssign::ZExt;
    else
      LocInfo = CCValAssign::AExt;
  }

  if (LocVT == MVT::i32) {
    static const MCPhysReg RegList1[] = {
      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
    };
    if (MCRegister Reg = State.AllocateReg(RegList1)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i64) {
    static const MCPhysReg RegList2[] = {
      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
    };
    if (MCRegister Reg = State.AllocateReg(RegList2)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f16) {
    static const MCPhysReg RegList3[] = {
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
    };
    if (MCRegister Reg = State.AllocateReg(RegList3)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::bf16) {
    static const MCPhysReg RegList4[] = {
      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
    };
    if (MCRegister Reg = State.AllocateReg(RegList4)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f32) {
    static const MCPhysReg RegList5[] = {
      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
    };
    if (MCRegister Reg = State.AllocateReg(RegList5)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f64) {
    static const MCPhysReg RegList6[] = {
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
    };
    if (MCRegister Reg = State.AllocateReg(RegList6)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::v1i64 ||
      LocVT == MVT::v2i32 ||
      LocVT == MVT::v4i16 ||
      LocVT == MVT::v8i8 ||
      LocVT == MVT::v1f64 ||
      LocVT == MVT::v2f32 ||
      LocVT == MVT::v4f16 ||
      LocVT == MVT::v4bf16) {
    static const MCPhysReg RegList7[] = {
      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
    };
    if (MCRegister Reg = State.AllocateReg(RegList7)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f128 ||
      LocVT == MVT::v2i64 ||
      LocVT == MVT::v4i32 ||
      LocVT == MVT::v8i16 ||
      LocVT == MVT::v16i8 ||
      LocVT == MVT::v4f32 ||
      LocVT == MVT::v2f64 ||
      LocVT == MVT::v8f16 ||
      LocVT == MVT::v8bf16) {
    static const MCPhysReg RegList8[] = {
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
    };
    if (MCRegister Reg = State.AllocateReg(RegList8)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::nxv16i8 ||
      LocVT == MVT::nxv8i16 ||
      LocVT == MVT::nxv4i32 ||
      LocVT == MVT::nxv2i64 ||
      LocVT == MVT::nxv2f16 ||
      LocVT == MVT::nxv4f16 ||
      LocVT == MVT::nxv8f16 ||
      LocVT == MVT::nxv2bf16 ||
      LocVT == MVT::nxv4bf16 ||
      LocVT == MVT::nxv8bf16 ||
      LocVT == MVT::nxv2f32 ||
      LocVT == MVT::nxv4f32 ||
      LocVT == MVT::nxv2f64) {
    static const MCPhysReg RegList9[] = {
      AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
    };
    if (MCRegister Reg = State.AllocateReg(RegList9)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::nxv1i1 ||
      LocVT == MVT::nxv2i1 ||
      LocVT == MVT::nxv4i1 ||
      LocVT == MVT::nxv8i1 ||
      LocVT == MVT::nxv16i1 ||
      LocVT == MVT::aarch64svcount) {
    static const MCPhysReg RegList10[] = {
      AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
    };
    if (MCRegister Reg = State.AllocateReg(RegList10)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  return true; // CC didn't match.
}


bool llvm::RetCC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
                                               MVT LocVT, CCValAssign::LocInfo LocInfo,
                                               ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {

  if (LocVT == MVT::i64) {
    static const MCPhysReg RegList1[] = {
      AArch64::X11, AArch64::X9
    };
    if (MCRegister Reg = State.AllocateReg(RegList1)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  return true; // CC didn't match.
}


bool llvm::RetCC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
                                       MVT LocVT, CCValAssign::LocInfo LocInfo,
                                       ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {

  if (LocVT == MVT::x86mmx) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::f16) {
    static const MCPhysReg RegList1[] = {
      AArch64::H0, AArch64::H1
    };
    if (MCRegister Reg = State.AllocateReg(RegList1)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f32) {
    static const MCPhysReg RegList2[] = {
      AArch64::S0, AArch64::S1
    };
    if (MCRegister Reg = State.AllocateReg(RegList2)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f64) {
    static const MCPhysReg RegList3[] = {
      AArch64::D0, AArch64::D1
    };
    if (MCRegister Reg = State.AllocateReg(RegList3)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f128) {
    static const MCPhysReg RegList4[] = {
      AArch64::Q0, AArch64::Q1
    };
    if (MCRegister Reg = State.AllocateReg(RegList4)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (ArgFlags.isSwiftError()) {
    if (LocVT == MVT::i64) {
      if (MCRegister Reg = State.AllocateReg(AArch64::X19)) {
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
        return false;
      }
    }
  }

  if (LocVT == MVT::i1 ||
      LocVT == MVT::i8 ||
      LocVT == MVT::i16) {
    LocVT = MVT::i32;
    if (ArgFlags.isSExt())
      LocInfo = CCValAssign::SExt;
    else if (ArgFlags.isZExt())
      LocInfo = CCValAssign::ZExt;
    else
      LocInfo = CCValAssign::AExt;
  }

  if (LocVT == MVT::i32) {
    static const MCPhysReg RegList5[] = {
      AArch64::W8, AArch64::W1, AArch64::W0
    };
    if (MCRegister Reg = State.AllocateReg(RegList5)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::i64) {
    static const MCPhysReg RegList6[] = {
      AArch64::X8, AArch64::X1, AArch64::X0
    };
    if (MCRegister Reg = State.AllocateReg(RegList6)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::v16i8 ||
      LocVT == MVT::v8i16 ||
      LocVT == MVT::v4i32 ||
      LocVT == MVT::v2i64 ||
      LocVT == MVT::v8f16 ||
      LocVT == MVT::v4f32 ||
      LocVT == MVT::v2f64) {
    static const MCPhysReg RegList7[] = {
      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3
    };
    if (MCRegister Reg = State.AllocateReg(RegList7)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  return true; // CC didn't match.
}

#else

const MCRegister CC_AArch64_AAPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X15, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
const MCRegister CC_AArch64_Arm64EC_CFGuard_Check_ArgRegs[] = { AArch64::X10, AArch64::X11, AArch64::X9 };
const MCRegister CC_AArch64_Arm64EC_Thunk_ArgRegs[] = { AArch64::X4, AArch64::X8, AArch64::X9 };
const MCRegister CC_AArch64_Arm64EC_Thunk_Native_ArgRegs[] = { AArch64::X9 };
const MCRegister CC_AArch64_Arm64EC_VarArg_ArgRegs[] = { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::X0, AArch64::X1, AArch64::X15, AArch64::X2, AArch64::X3, AArch64::X8, AArch64::X9 };
const MCRegister CC_AArch64_DarwinPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X15, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
const MCRegister CC_AArch64_DarwinPCS_ILP32_VarArg_ArgRegs[] = { AArch64::X15 };
const MCRegister CC_AArch64_DarwinPCS_VarArg_ArgRegs[] = { AArch64::X15 };
const MCRegister CC_AArch64_GHC_ArgRegs[] = { AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::Q4, AArch64::Q5, AArch64::S10, AArch64::S11, AArch64::S8, AArch64::S9, AArch64::X15, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28 };
const MCRegister CC_AArch64_Preserve_None_ArgRegs[] = { AArch64::W0, AArch64::W1, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W2, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W9, AArch64::X0, AArch64::X1, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X2, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X9 };
const MCRegister CC_AArch64_Win64PCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X15, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
const MCRegister CC_AArch64_Win64_CFGuard_Check_ArgRegs[] = { AArch64::X15 };
const MCRegister CC_AArch64_Win64_VarArg_ArgRegs[] = { 0 };
const MCRegister RetCC_AArch64_AAPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
const MCRegister RetCC_AArch64_Arm64EC_CFGuard_Check_ArgRegs[] = { AArch64::X11, AArch64::X9 };
const MCRegister RetCC_AArch64_Arm64EC_Thunk_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::H0, AArch64::H1, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::S0, AArch64::S1, AArch64::W0, AArch64::W1, AArch64::W8, AArch64::X0, AArch64::X1, AArch64::X8 };

// Registers used by Swift.
const MCRegister CC_AArch64_AAPCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 };
const MCRegister CC_AArch64_Arm64EC_Thunk_Swift_ArgRegs[] = { AArch64::X19, AArch64::X20, AArch64::X21 };
const MCRegister CC_AArch64_DarwinPCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 };
const MCRegister CC_AArch64_Win64PCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 };
const MCRegister RetCC_AArch64_AAPCS_Swift_ArgRegs[] = { AArch64::X21 };
const MCRegister RetCC_AArch64_Arm64EC_Thunk_Swift_ArgRegs[] = { AArch64::X19 };

#endif // !defined(GET_CC_REGISTER_LISTS)

