/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Machine Code Emitter                                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

uint64_t MipsMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
    SmallVectorImpl<MCFixup> &Fixups,
    const MCSubtargetInfo &STI) const {
  static const uint64_t InstBits[] = {
    UINT64_C(2080375378),	// ABSQ_S_PH
    UINT64_C(4412),	// ABSQ_S_PH_MM
    UINT64_C(2080374866),	// ABSQ_S_QB
    UINT64_C(316),	// ABSQ_S_QB_MMR2
    UINT64_C(2080375890),	// ABSQ_S_W
    UINT64_C(8508),	// ABSQ_S_W_MM
    UINT64_C(32),	// ADD
    UINT64_C(3959422976),	// ADDIUPC
    UINT64_C(2013265920),	// ADDIUPC_MM
    UINT64_C(2013265920),	// ADDIUPC_MMR6
    UINT64_C(27649),	// ADDIUR1SP_MM
    UINT64_C(27648),	// ADDIUR2_MM
    UINT64_C(19456),	// ADDIUS5_MM
    UINT64_C(19457),	// ADDIUSP_MM
    UINT64_C(805306368),	// ADDIU_MMR6
    UINT64_C(2080375320),	// ADDQH_PH
    UINT64_C(77),	// ADDQH_PH_MMR2
    UINT64_C(2080375448),	// ADDQH_R_PH
    UINT64_C(1101),	// ADDQH_R_PH_MMR2
    UINT64_C(2080375960),	// ADDQH_R_W
    UINT64_C(1165),	// ADDQH_R_W_MMR2
    UINT64_C(2080375832),	// ADDQH_W
    UINT64_C(141),	// ADDQH_W_MMR2
    UINT64_C(2080375440),	// ADDQ_PH
    UINT64_C(13),	// ADDQ_PH_MM
    UINT64_C(2080375696),	// ADDQ_S_PH
    UINT64_C(1037),	// ADDQ_S_PH_MM
    UINT64_C(2080376208),	// ADDQ_S_W
    UINT64_C(773),	// ADDQ_S_W_MM
    UINT64_C(1186988056),	// ADDR_PS64
    UINT64_C(2080375824),	// ADDSC
    UINT64_C(901),	// ADDSC_MM
    UINT64_C(2021654544),	// ADDS_A_B
    UINT64_C(2027946000),	// ADDS_A_D
    UINT64_C(2023751696),	// ADDS_A_H
    UINT64_C(2025848848),	// ADDS_A_W
    UINT64_C(2030043152),	// ADDS_S_B
    UINT64_C(2036334608),	// ADDS_S_D
    UINT64_C(2032140304),	// ADDS_S_H
    UINT64_C(2034237456),	// ADDS_S_W
    UINT64_C(2038431760),	// ADDS_U_B
    UINT64_C(2044723216),	// ADDS_U_D
    UINT64_C(2040528912),	// ADDS_U_H
    UINT64_C(2042626064),	// ADDS_U_W
    UINT64_C(1024),	// ADDU16_MM
    UINT64_C(1024),	// ADDU16_MMR6
    UINT64_C(2080374808),	// ADDUH_QB
    UINT64_C(333),	// ADDUH_QB_MMR2
    UINT64_C(2080374936),	// ADDUH_R_QB
    UINT64_C(1357),	// ADDUH_R_QB_MMR2
    UINT64_C(336),	// ADDU_MMR6
    UINT64_C(2080375312),	// ADDU_PH
    UINT64_C(269),	// ADDU_PH_MMR2
    UINT64_C(2080374800),	// ADDU_QB
    UINT64_C(205),	// ADDU_QB_MM
    UINT64_C(2080375568),	// ADDU_S_PH
    UINT64_C(1293),	// ADDU_S_PH_MMR2
    UINT64_C(2080375056),	// ADDU_S_QB
    UINT64_C(1229),	// ADDU_S_QB_MM
    UINT64_C(2013265926),	// ADDVI_B
    UINT64_C(2019557382),	// ADDVI_D
    UINT64_C(2015363078),	// ADDVI_H
    UINT64_C(2017460230),	// ADDVI_W
    UINT64_C(2013265934),	// ADDV_B
    UINT64_C(2019557390),	// ADDV_D
    UINT64_C(2015363086),	// ADDV_H
    UINT64_C(2017460238),	// ADDV_W
    UINT64_C(2080375888),	// ADDWC
    UINT64_C(965),	// ADDWC_MM
    UINT64_C(2013265936),	// ADD_A_B
    UINT64_C(2019557392),	// ADD_A_D
    UINT64_C(2015363088),	// ADD_A_H
    UINT64_C(2017460240),	// ADD_A_W
    UINT64_C(272),	// ADD_MM
    UINT64_C(272),	// ADD_MMR6
    UINT64_C(536870912),	// ADDi
    UINT64_C(268435456),	// ADDi_MM
    UINT64_C(603979776),	// ADDiu
    UINT64_C(805306368),	// ADDiu_MM
    UINT64_C(33),	// ADDu
    UINT64_C(336),	// ADDu_MM
    UINT64_C(2080375328),	// ALIGN
    UINT64_C(31),	// ALIGN_MMR6
    UINT64_C(3961454592),	// ALUIPC
    UINT64_C(2015297536),	// ALUIPC_MMR6
    UINT64_C(36),	// AND
    UINT64_C(17536),	// AND16_MM
    UINT64_C(17409),	// AND16_MMR6
    UINT64_C(36),	// AND64
    UINT64_C(11264),	// ANDI16_MM
    UINT64_C(11264),	// ANDI16_MMR6
    UINT64_C(2013265920),	// ANDI_B
    UINT64_C(3489660928),	// ANDI_MMR6
    UINT64_C(592),	// AND_MM
    UINT64_C(592),	// AND_MMR6
    UINT64_C(2013265950),	// AND_V
    UINT64_C(805306368),	// ANDi
    UINT64_C(805306368),	// ANDi64
    UINT64_C(3489660928),	// ANDi_MM
    UINT64_C(2080374833),	// APPEND
    UINT64_C(533),	// APPEND_MMR2
    UINT64_C(2046820369),	// ASUB_S_B
    UINT64_C(2053111825),	// ASUB_S_D
    UINT64_C(2048917521),	// ASUB_S_H
    UINT64_C(2051014673),	// ASUB_S_W
    UINT64_C(2055208977),	// ASUB_U_B
    UINT64_C(2061500433),	// ASUB_U_D
    UINT64_C(2057306129),	// ASUB_U_H
    UINT64_C(2059403281),	// ASUB_U_W
    UINT64_C(1006632960),	// AUI
    UINT64_C(3961389056),	// AUIPC
    UINT64_C(2015232000),	// AUIPC_MMR6
    UINT64_C(268435456),	// AUI_MMR6
    UINT64_C(2063597584),	// AVER_S_B
    UINT64_C(2069889040),	// AVER_S_D
    UINT64_C(2065694736),	// AVER_S_H
    UINT64_C(2067791888),	// AVER_S_W
    UINT64_C(2071986192),	// AVER_U_B
    UINT64_C(2078277648),	// AVER_U_D
    UINT64_C(2074083344),	// AVER_U_H
    UINT64_C(2076180496),	// AVER_U_W
    UINT64_C(2046820368),	// AVE_S_B
    UINT64_C(2053111824),	// AVE_S_D
    UINT64_C(2048917520),	// AVE_S_H
    UINT64_C(2051014672),	// AVE_S_W
    UINT64_C(2055208976),	// AVE_U_B
    UINT64_C(2061500432),	// AVE_U_D
    UINT64_C(2057306128),	// AVE_U_H
    UINT64_C(2059403280),	// AVE_U_W
    UINT64_C(4026550272),	// AddiuRxImmX16
    UINT64_C(4026533888),	// AddiuRxPcImmX16
    UINT64_C(18432),	// AddiuRxRxImm16
    UINT64_C(4026550272),	// AddiuRxRxImmX16
    UINT64_C(4026548224),	// AddiuRxRyOffMemX16
    UINT64_C(25344),	// AddiuSpImm16
    UINT64_C(4026544896),	// AddiuSpImmX16
    UINT64_C(57345),	// AdduRxRyRz16
    UINT64_C(59404),	// AndRxRxRy16
    UINT64_C(52224),	// B16_MM
    UINT64_C(1879048232),	// BADDu
    UINT64_C(68222976),	// BAL
    UINT64_C(3892314112),	// BALC
    UINT64_C(3019898880),	// BALC_MMR6
    UINT64_C(2080375857),	// BALIGN
    UINT64_C(2236),	// BALIGN_MMR2
    UINT64_C(3355443200),	// BBIT0
    UINT64_C(3623878656),	// BBIT032
    UINT64_C(3892314112),	// BBIT1
    UINT64_C(4160749568),	// BBIT132
    UINT64_C(3355443200),	// BC
    UINT64_C(52224),	// BC16_MMR6
    UINT64_C(1159725056),	// BC1EQZ
    UINT64_C(1090519040),	// BC1EQZC_MMR6
    UINT64_C(1157627904),	// BC1F
    UINT64_C(1157758976),	// BC1FL
    UINT64_C(1132462080),	// BC1F_MM
    UINT64_C(1168113664),	// BC1NEZ
    UINT64_C(1092616192),	// BC1NEZC_MMR6
    UINT64_C(1157693440),	// BC1T
    UINT64_C(1157824512),	// BC1TL
    UINT64_C(1134559232),	// BC1T_MM
    UINT64_C(1226833920),	// BC2EQZ
    UINT64_C(1094713344),	// BC2EQZC_MMR6
    UINT64_C(1235222528),	// BC2NEZ
    UINT64_C(1096810496),	// BC2NEZC_MMR6
    UINT64_C(2045771785),	// BCLRI_B
    UINT64_C(2038431753),	// BCLRI_D
    UINT64_C(2044723209),	// BCLRI_H
    UINT64_C(2042626057),	// BCLRI_W
    UINT64_C(2038431757),	// BCLR_B
    UINT64_C(2044723213),	// BCLR_D
    UINT64_C(2040528909),	// BCLR_H
    UINT64_C(2042626061),	// BCLR_W
    UINT64_C(2483027968),	// BC_MMR6
    UINT64_C(268435456),	// BEQ
    UINT64_C(268435456),	// BEQ64
    UINT64_C(536870912),	// BEQC
    UINT64_C(536870912),	// BEQC64
    UINT64_C(1946157056),	// BEQC_MMR6
    UINT64_C(1342177280),	// BEQL
    UINT64_C(35840),	// BEQZ16_MM
    UINT64_C(536870912),	// BEQZALC
    UINT64_C(1946157056),	// BEQZALC_MMR6
    UINT64_C(3623878656),	// BEQZC
    UINT64_C(35840),	// BEQZC16_MMR6
    UINT64_C(3623878656),	// BEQZC64
    UINT64_C(1088421888),	// BEQZC_MM
    UINT64_C(2147483648),	// BEQZC_MMR6
    UINT64_C(2483027968),	// BEQ_MM
    UINT64_C(1476395008),	// BGEC
    UINT64_C(1476395008),	// BGEC64
    UINT64_C(4093640704),	// BGEC_MMR6
    UINT64_C(402653184),	// BGEUC
    UINT64_C(402653184),	// BGEUC64
    UINT64_C(3221225472),	// BGEUC_MMR6
    UINT64_C(67174400),	// BGEZ
    UINT64_C(67174400),	// BGEZ64
    UINT64_C(68222976),	// BGEZAL
    UINT64_C(402653184),	// BGEZALC
    UINT64_C(3221225472),	// BGEZALC_MMR6
    UINT64_C(68354048),	// BGEZALL
    UINT64_C(1113587712),	// BGEZALS_MM
    UINT64_C(1080033280),	// BGEZAL_MM
    UINT64_C(1476395008),	// BGEZC
    UINT64_C(1476395008),	// BGEZC64
    UINT64_C(4093640704),	// BGEZC_MMR6
    UINT64_C(67305472),	// BGEZL
    UINT64_C(1077936128),	// BGEZ_MM
    UINT64_C(469762048),	// BGTZ
    UINT64_C(469762048),	// BGTZ64
    UINT64_C(469762048),	// BGTZALC
    UINT64_C(3758096384),	// BGTZALC_MMR6
    UINT64_C(1543503872),	// BGTZC
    UINT64_C(1543503872),	// BGTZC64
    UINT64_C(3556769792),	// BGTZC_MMR6
    UINT64_C(1543503872),	// BGTZL
    UINT64_C(1086324736),	// BGTZ_MM
    UINT64_C(2070937609),	// BINSLI_B
    UINT64_C(2063597577),	// BINSLI_D
    UINT64_C(2069889033),	// BINSLI_H
    UINT64_C(2067791881),	// BINSLI_W
    UINT64_C(2063597581),	// BINSL_B
    UINT64_C(2069889037),	// BINSL_D
    UINT64_C(2065694733),	// BINSL_H
    UINT64_C(2067791885),	// BINSL_W
    UINT64_C(2079326217),	// BINSRI_B
    UINT64_C(2071986185),	// BINSRI_D
    UINT64_C(2078277641),	// BINSRI_H
    UINT64_C(2076180489),	// BINSRI_W
    UINT64_C(2071986189),	// BINSR_B
    UINT64_C(2078277645),	// BINSR_D
    UINT64_C(2074083341),	// BINSR_H
    UINT64_C(2076180493),	// BINSR_W
    UINT64_C(2080376530),	// BITREV
    UINT64_C(12604),	// BITREV_MM
    UINT64_C(2080374816),	// BITSWAP
    UINT64_C(2876),	// BITSWAP_MMR6
    UINT64_C(402653184),	// BLEZ
    UINT64_C(402653184),	// BLEZ64
    UINT64_C(402653184),	// BLEZALC
    UINT64_C(3221225472),	// BLEZALC_MMR6
    UINT64_C(1476395008),	// BLEZC
    UINT64_C(1476395008),	// BLEZC64
    UINT64_C(4093640704),	// BLEZC_MMR6
    UINT64_C(1476395008),	// BLEZL
    UINT64_C(1082130432),	// BLEZ_MM
    UINT64_C(1543503872),	// BLTC
    UINT64_C(1543503872),	// BLTC64
    UINT64_C(3556769792),	// BLTC_MMR6
    UINT64_C(469762048),	// BLTUC
    UINT64_C(469762048),	// BLTUC64
    UINT64_C(3758096384),	// BLTUC_MMR6
    UINT64_C(67108864),	// BLTZ
    UINT64_C(67108864),	// BLTZ64
    UINT64_C(68157440),	// BLTZAL
    UINT64_C(469762048),	// BLTZALC
    UINT64_C(3758096384),	// BLTZALC_MMR6
    UINT64_C(68288512),	// BLTZALL
    UINT64_C(1109393408),	// BLTZALS_MM
    UINT64_C(1075838976),	// BLTZAL_MM
    UINT64_C(1543503872),	// BLTZC
    UINT64_C(1543503872),	// BLTZC64
    UINT64_C(3556769792),	// BLTZC_MMR6
    UINT64_C(67239936),	// BLTZL
    UINT64_C(1073741824),	// BLTZ_MM
    UINT64_C(2013265921),	// BMNZI_B
    UINT64_C(2021654558),	// BMNZ_V
    UINT64_C(2030043137),	// BMZI_B
    UINT64_C(2023751710),	// BMZ_V
    UINT64_C(335544320),	// BNE
    UINT64_C(335544320),	// BNE64
    UINT64_C(1610612736),	// BNEC
    UINT64_C(1610612736),	// BNEC64
    UINT64_C(2080374784),	// BNEC_MMR6
    UINT64_C(2062549001),	// BNEGI_B
    UINT64_C(2055208969),	// BNEGI_D
    UINT64_C(2061500425),	// BNEGI_H
    UINT64_C(2059403273),	// BNEGI_W
    UINT64_C(2055208973),	// BNEG_B
    UINT64_C(2061500429),	// BNEG_D
    UINT64_C(2057306125),	// BNEG_H
    UINT64_C(2059403277),	// BNEG_W
    UINT64_C(1409286144),	// BNEL
    UINT64_C(44032),	// BNEZ16_MM
    UINT64_C(1610612736),	// BNEZALC
    UINT64_C(2080374784),	// BNEZALC_MMR6
    UINT64_C(4160749568),	// BNEZC
    UINT64_C(44032),	// BNEZC16_MMR6
    UINT64_C(4160749568),	// BNEZC64
    UINT64_C(1084227584),	// BNEZC_MM
    UINT64_C(2684354560),	// BNEZC_MMR6
    UINT64_C(3019898880),	// BNE_MM
    UINT64_C(1610612736),	// BNVC
    UINT64_C(2080374784),	// BNVC_MMR6
    UINT64_C(1199570944),	// BNZ_B
    UINT64_C(1205862400),	// BNZ_D
    UINT64_C(1201668096),	// BNZ_H
    UINT64_C(1172307968),	// BNZ_V
    UINT64_C(1203765248),	// BNZ_W
    UINT64_C(536870912),	// BOVC
    UINT64_C(1946157056),	// BOVC_MMR6
    UINT64_C(68943872),	// BPOSGE32
    UINT64_C(1126170624),	// BPOSGE32C_MMR3
    UINT64_C(1130364928),	// BPOSGE32_MM
    UINT64_C(13),	// BREAK
    UINT64_C(18048),	// BREAK16_MM
    UINT64_C(17435),	// BREAK16_MMR6
    UINT64_C(7),	// BREAK_MM
    UINT64_C(7),	// BREAK_MMR6
    UINT64_C(2046820353),	// BSELI_B
    UINT64_C(2025848862),	// BSEL_V
    UINT64_C(2054160393),	// BSETI_B
    UINT64_C(2046820361),	// BSETI_D
    UINT64_C(2053111817),	// BSETI_H
    UINT64_C(2051014665),	// BSETI_W
    UINT64_C(2046820365),	// BSET_B
    UINT64_C(2053111821),	// BSET_D
    UINT64_C(2048917517),	// BSET_H
    UINT64_C(2051014669),	// BSET_W
    UINT64_C(1191182336),	// BZ_B
    UINT64_C(1197473792),	// BZ_D
    UINT64_C(1193279488),	// BZ_H
    UINT64_C(1163919360),	// BZ_V
    UINT64_C(1195376640),	// BZ_W
    UINT64_C(8192),	// BeqzRxImm16
    UINT64_C(4026540032),	// BeqzRxImmX16
    UINT64_C(4096),	// Bimm16
    UINT64_C(4026535936),	// BimmX16
    UINT64_C(10240),	// BnezRxImm16
    UINT64_C(4026542080),	// BnezRxImmX16
    UINT64_C(59397),	// Break16
    UINT64_C(24576),	// Bteqz16
    UINT64_C(4026544128),	// BteqzX16
    UINT64_C(24832),	// Btnez16
    UINT64_C(4026544384),	// BtnezX16
    UINT64_C(3154116608),	// CACHE
    UINT64_C(2080374811),	// CACHEE
    UINT64_C(1610655232),	// CACHEE_MM
    UINT64_C(536895488),	// CACHE_MM
    UINT64_C(536895488),	// CACHE_MMR6
    UINT64_C(2080374821),	// CACHE_R6
    UINT64_C(1176502282),	// CEIL_L_D64
    UINT64_C(1409307451),	// CEIL_L_D_MMR6
    UINT64_C(1174405130),	// CEIL_L_S
    UINT64_C(1409291067),	// CEIL_L_S_MMR6
    UINT64_C(1176502286),	// CEIL_W_D32
    UINT64_C(1176502286),	// CEIL_W_D64
    UINT64_C(1409309499),	// CEIL_W_D_MMR6
    UINT64_C(1409309499),	// CEIL_W_MM
    UINT64_C(1174405134),	// CEIL_W_S
    UINT64_C(1409293115),	// CEIL_W_S_MM
    UINT64_C(1409293115),	// CEIL_W_S_MMR6
    UINT64_C(2013265927),	// CEQI_B
    UINT64_C(2019557383),	// CEQI_D
    UINT64_C(2015363079),	// CEQI_H
    UINT64_C(2017460231),	// CEQI_W
    UINT64_C(2013265935),	// CEQ_B
    UINT64_C(2019557391),	// CEQ_D
    UINT64_C(2015363087),	// CEQ_H
    UINT64_C(2017460239),	// CEQ_W
    UINT64_C(1145044992),	// CFC1
    UINT64_C(1409290299),	// CFC1_MM
    UINT64_C(52540),	// CFC2_MM
    UINT64_C(2021523481),	// CFCMSA
    UINT64_C(1879048242),	// CINS
    UINT64_C(1879048243),	// CINS32
    UINT64_C(1879048242),	// CINS64_32
    UINT64_C(1879048242),	// CINS_i32
    UINT64_C(1176502299),	// CLASS_D
    UINT64_C(1409286752),	// CLASS_D_MMR6
    UINT64_C(1174405147),	// CLASS_S
    UINT64_C(1409286240),	// CLASS_S_MMR6
    UINT64_C(2046820359),	// CLEI_S_B
    UINT64_C(2053111815),	// CLEI_S_D
    UINT64_C(2048917511),	// CLEI_S_H
    UINT64_C(2051014663),	// CLEI_S_W
    UINT64_C(2055208967),	// CLEI_U_B
    UINT64_C(2061500423),	// CLEI_U_D
    UINT64_C(2057306119),	// CLEI_U_H
    UINT64_C(2059403271),	// CLEI_U_W
    UINT64_C(2046820367),	// CLE_S_B
    UINT64_C(2053111823),	// CLE_S_D
    UINT64_C(2048917519),	// CLE_S_H
    UINT64_C(2051014671),	// CLE_S_W
    UINT64_C(2055208975),	// CLE_U_B
    UINT64_C(2061500431),	// CLE_U_D
    UINT64_C(2057306127),	// CLE_U_H
    UINT64_C(2059403279),	// CLE_U_W
    UINT64_C(1879048225),	// CLO
    UINT64_C(19260),	// CLO_MM
    UINT64_C(19260),	// CLO_MMR6
    UINT64_C(81),	// CLO_R6
    UINT64_C(2030043143),	// CLTI_S_B
    UINT64_C(2036334599),	// CLTI_S_D
    UINT64_C(2032140295),	// CLTI_S_H
    UINT64_C(2034237447),	// CLTI_S_W
    UINT64_C(2038431751),	// CLTI_U_B
    UINT64_C(2044723207),	// CLTI_U_D
    UINT64_C(2040528903),	// CLTI_U_H
    UINT64_C(2042626055),	// CLTI_U_W
    UINT64_C(2030043151),	// CLT_S_B
    UINT64_C(2036334607),	// CLT_S_D
    UINT64_C(2032140303),	// CLT_S_H
    UINT64_C(2034237455),	// CLT_S_W
    UINT64_C(2038431759),	// CLT_U_B
    UINT64_C(2044723215),	// CLT_U_D
    UINT64_C(2040528911),	// CLT_U_H
    UINT64_C(2042626063),	// CLT_U_W
    UINT64_C(1879048224),	// CLZ
    UINT64_C(23356),	// CLZ_MM
    UINT64_C(80),	// CLZ_MMR6
    UINT64_C(80),	// CLZ_R6
    UINT64_C(2080376337),	// CMPGDU_EQ_QB
    UINT64_C(389),	// CMPGDU_EQ_QB_MMR2
    UINT64_C(2080376465),	// CMPGDU_LE_QB
    UINT64_C(517),	// CMPGDU_LE_QB_MMR2
    UINT64_C(2080376401),	// CMPGDU_LT_QB
    UINT64_C(453),	// CMPGDU_LT_QB_MMR2
    UINT64_C(2080375057),	// CMPGU_EQ_QB
    UINT64_C(1476395205),	// CMPGU_EQ_QB_MM
    UINT64_C(2080375185),	// CMPGU_LE_QB
    UINT64_C(1476395333),	// CMPGU_LE_QB_MM
    UINT64_C(2080375121),	// CMPGU_LT_QB
    UINT64_C(1476395269),	// CMPGU_LT_QB_MM
    UINT64_C(2080374801),	// CMPU_EQ_QB
    UINT64_C(581),	// CMPU_EQ_QB_MM
    UINT64_C(2080374929),	// CMPU_LE_QB
    UINT64_C(709),	// CMPU_LE_QB_MM
    UINT64_C(2080374865),	// CMPU_LT_QB
    UINT64_C(645),	// CMPU_LT_QB_MM
    UINT64_C(1409286165),	// CMP_AF_D_MMR6
    UINT64_C(1409286149),	// CMP_AF_S_MMR6
    UINT64_C(1184890882),	// CMP_EQ_D
    UINT64_C(1409286293),	// CMP_EQ_D_MMR6
    UINT64_C(2080375313),	// CMP_EQ_PH
    UINT64_C(5),	// CMP_EQ_PH_MM
    UINT64_C(1182793730),	// CMP_EQ_S
    UINT64_C(1409286277),	// CMP_EQ_S_MMR6
    UINT64_C(1184890880),	// CMP_F_D
    UINT64_C(1182793728),	// CMP_F_S
    UINT64_C(1184890886),	// CMP_LE_D
    UINT64_C(1409286549),	// CMP_LE_D_MMR6
    UINT64_C(2080375441),	// CMP_LE_PH
    UINT64_C(133),	// CMP_LE_PH_MM
    UINT64_C(1182793734),	// CMP_LE_S
    UINT64_C(1409286533),	// CMP_LE_S_MMR6
    UINT64_C(1184890884),	// CMP_LT_D
    UINT64_C(1409286421),	// CMP_LT_D_MMR6
    UINT64_C(2080375377),	// CMP_LT_PH
    UINT64_C(69),	// CMP_LT_PH_MM
    UINT64_C(1182793732),	// CMP_LT_S
    UINT64_C(1409286405),	// CMP_LT_S_MMR6
    UINT64_C(1184890888),	// CMP_SAF_D
    UINT64_C(1409286677),	// CMP_SAF_D_MMR6
    UINT64_C(1182793736),	// CMP_SAF_S
    UINT64_C(1409286661),	// CMP_SAF_S_MMR6
    UINT64_C(1184890890),	// CMP_SEQ_D
    UINT64_C(1409286805),	// CMP_SEQ_D_MMR6
    UINT64_C(1182793738),	// CMP_SEQ_S
    UINT64_C(1409286789),	// CMP_SEQ_S_MMR6
    UINT64_C(1184890894),	// CMP_SLE_D
    UINT64_C(1409287061),	// CMP_SLE_D_MMR6
    UINT64_C(1182793742),	// CMP_SLE_S
    UINT64_C(1409287045),	// CMP_SLE_S_MMR6
    UINT64_C(1184890892),	// CMP_SLT_D
    UINT64_C(1409286933),	// CMP_SLT_D_MMR6
    UINT64_C(1182793740),	// CMP_SLT_S
    UINT64_C(1409286917),	// CMP_SLT_S_MMR6
    UINT64_C(1184890891),	// CMP_SUEQ_D
    UINT64_C(1409286869),	// CMP_SUEQ_D_MMR6
    UINT64_C(1182793739),	// CMP_SUEQ_S
    UINT64_C(1409286853),	// CMP_SUEQ_S_MMR6
    UINT64_C(1184890895),	// CMP_SULE_D
    UINT64_C(1409287125),	// CMP_SULE_D_MMR6
    UINT64_C(1182793743),	// CMP_SULE_S
    UINT64_C(1409287109),	// CMP_SULE_S_MMR6
    UINT64_C(1184890893),	// CMP_SULT_D
    UINT64_C(1409286997),	// CMP_SULT_D_MMR6
    UINT64_C(1182793741),	// CMP_SULT_S
    UINT64_C(1409286981),	// CMP_SULT_S_MMR6
    UINT64_C(1184890889),	// CMP_SUN_D
    UINT64_C(1409286741),	// CMP_SUN_D_MMR6
    UINT64_C(1182793737),	// CMP_SUN_S
    UINT64_C(1409286725),	// CMP_SUN_S_MMR6
    UINT64_C(1184890883),	// CMP_UEQ_D
    UINT64_C(1409286357),	// CMP_UEQ_D_MMR6
    UINT64_C(1182793731),	// CMP_UEQ_S
    UINT64_C(1409286341),	// CMP_UEQ_S_MMR6
    UINT64_C(1184890887),	// CMP_ULE_D
    UINT64_C(1409286613),	// CMP_ULE_D_MMR6
    UINT64_C(1182793735),	// CMP_ULE_S
    UINT64_C(1409286597),	// CMP_ULE_S_MMR6
    UINT64_C(1184890885),	// CMP_ULT_D
    UINT64_C(1409286485),	// CMP_ULT_D_MMR6
    UINT64_C(1182793733),	// CMP_ULT_S
    UINT64_C(1409286469),	// CMP_ULT_S_MMR6
    UINT64_C(1184890881),	// CMP_UN_D
    UINT64_C(1409286229),	// CMP_UN_D_MMR6
    UINT64_C(1182793729),	// CMP_UN_S
    UINT64_C(1409286213),	// CMP_UN_S_MMR6
    UINT64_C(2021654553),	// COPY_S_B
    UINT64_C(2025324569),	// COPY_S_D
    UINT64_C(2023751705),	// COPY_S_H
    UINT64_C(2024800281),	// COPY_S_W
    UINT64_C(2025848857),	// COPY_U_B
    UINT64_C(2027946009),	// COPY_U_H
    UINT64_C(2028994585),	// COPY_U_W
    UINT64_C(2080374799),	// CRC32B
    UINT64_C(2080375055),	// CRC32CB
    UINT64_C(2080375247),	// CRC32CD
    UINT64_C(2080375119),	// CRC32CH
    UINT64_C(2080375183),	// CRC32CW
    UINT64_C(2080374991),	// CRC32D
    UINT64_C(2080374863),	// CRC32H
    UINT64_C(2080374927),	// CRC32W
    UINT64_C(1153433600),	// CTC1
    UINT64_C(1409292347),	// CTC1_MM
    UINT64_C(56636),	// CTC2_MM
    UINT64_C(2017329177),	// CTCMSA
    UINT64_C(1174405153),	// CVT_D32_S
    UINT64_C(1409291131),	// CVT_D32_S_MM
    UINT64_C(1182793761),	// CVT_D32_W
    UINT64_C(1409299323),	// CVT_D32_W_MM
    UINT64_C(1184890913),	// CVT_D64_L
    UINT64_C(1174405153),	// CVT_D64_S
    UINT64_C(1409291131),	// CVT_D64_S_MM
    UINT64_C(1182793761),	// CVT_D64_W
    UINT64_C(1409299323),	// CVT_D64_W_MM
    UINT64_C(1409307515),	// CVT_D_L_MMR6
    UINT64_C(1176502309),	// CVT_L_D64
    UINT64_C(1409302843),	// CVT_L_D64_MM
    UINT64_C(1409302843),	// CVT_L_D_MMR6
    UINT64_C(1174405157),	// CVT_L_S
    UINT64_C(1409286459),	// CVT_L_S_MM
    UINT64_C(1409286459),	// CVT_L_S_MMR6
    UINT64_C(1182793766),	// CVT_PS_PW64
    UINT64_C(1174405158),	// CVT_PS_S64
    UINT64_C(1186988068),	// CVT_PW_PS64
    UINT64_C(1176502304),	// CVT_S_D32
    UINT64_C(1409293179),	// CVT_S_D32_MM
    UINT64_C(1176502304),	// CVT_S_D64
    UINT64_C(1409293179),	// CVT_S_D64_MM
    UINT64_C(1184890912),	// CVT_S_L
    UINT64_C(1409309563),	// CVT_S_L_MMR6
    UINT64_C(1186988072),	// CVT_S_PL64
    UINT64_C(1186988064),	// CVT_S_PU64
    UINT64_C(1182793760),	// CVT_S_W
    UINT64_C(1409301371),	// CVT_S_W_MM
    UINT64_C(1409301371),	// CVT_S_W_MMR6
    UINT64_C(1176502308),	// CVT_W_D32
    UINT64_C(1409304891),	// CVT_W_D32_MM
    UINT64_C(1176502308),	// CVT_W_D64
    UINT64_C(1409304891),	// CVT_W_D64_MM
    UINT64_C(1174405156),	// CVT_W_S
    UINT64_C(1409288507),	// CVT_W_S_MM
    UINT64_C(1409288507),	// CVT_W_S_MMR6
    UINT64_C(1176502322),	// C_EQ_D32
    UINT64_C(1409287356),	// C_EQ_D32_MM
    UINT64_C(1176502322),	// C_EQ_D64
    UINT64_C(1409287356),	// C_EQ_D64_MM
    UINT64_C(1174405170),	// C_EQ_S
    UINT64_C(1409286332),	// C_EQ_S_MM
    UINT64_C(1176502320),	// C_F_D32
    UINT64_C(1409287228),	// C_F_D32_MM
    UINT64_C(1176502320),	// C_F_D64
    UINT64_C(1409287228),	// C_F_D64_MM
    UINT64_C(1174405168),	// C_F_S
    UINT64_C(1409286204),	// C_F_S_MM
    UINT64_C(1176502334),	// C_LE_D32
    UINT64_C(1409288124),	// C_LE_D32_MM
    UINT64_C(1176502334),	// C_LE_D64
    UINT64_C(1409288124),	// C_LE_D64_MM
    UINT64_C(1174405182),	// C_LE_S
    UINT64_C(1409287100),	// C_LE_S_MM
    UINT64_C(1176502332),	// C_LT_D32
    UINT64_C(1409287996),	// C_LT_D32_MM
    UINT64_C(1176502332),	// C_LT_D64
    UINT64_C(1409287996),	// C_LT_D64_MM
    UINT64_C(1174405180),	// C_LT_S
    UINT64_C(1409286972),	// C_LT_S_MM
    UINT64_C(1176502333),	// C_NGE_D32
    UINT64_C(1409288060),	// C_NGE_D32_MM
    UINT64_C(1176502333),	// C_NGE_D64
    UINT64_C(1409288060),	// C_NGE_D64_MM
    UINT64_C(1174405181),	// C_NGE_S
    UINT64_C(1409287036),	// C_NGE_S_MM
    UINT64_C(1176502329),	// C_NGLE_D32
    UINT64_C(1409287804),	// C_NGLE_D32_MM
    UINT64_C(1176502329),	// C_NGLE_D64
    UINT64_C(1409287804),	// C_NGLE_D64_MM
    UINT64_C(1174405177),	// C_NGLE_S
    UINT64_C(1409286780),	// C_NGLE_S_MM
    UINT64_C(1176502331),	// C_NGL_D32
    UINT64_C(1409287932),	// C_NGL_D32_MM
    UINT64_C(1176502331),	// C_NGL_D64
    UINT64_C(1409287932),	// C_NGL_D64_MM
    UINT64_C(1174405179),	// C_NGL_S
    UINT64_C(1409286908),	// C_NGL_S_MM
    UINT64_C(1176502335),	// C_NGT_D32
    UINT64_C(1409288188),	// C_NGT_D32_MM
    UINT64_C(1176502335),	// C_NGT_D64
    UINT64_C(1409288188),	// C_NGT_D64_MM
    UINT64_C(1174405183),	// C_NGT_S
    UINT64_C(1409287164),	// C_NGT_S_MM
    UINT64_C(1176502326),	// C_OLE_D32
    UINT64_C(1409287612),	// C_OLE_D32_MM
    UINT64_C(1176502326),	// C_OLE_D64
    UINT64_C(1409287612),	// C_OLE_D64_MM
    UINT64_C(1174405174),	// C_OLE_S
    UINT64_C(1409286588),	// C_OLE_S_MM
    UINT64_C(1176502324),	// C_OLT_D32
    UINT64_C(1409287484),	// C_OLT_D32_MM
    UINT64_C(1176502324),	// C_OLT_D64
    UINT64_C(1409287484),	// C_OLT_D64_MM
    UINT64_C(1174405172),	// C_OLT_S
    UINT64_C(1409286460),	// C_OLT_S_MM
    UINT64_C(1176502330),	// C_SEQ_D32
    UINT64_C(1409287868),	// C_SEQ_D32_MM
    UINT64_C(1176502330),	// C_SEQ_D64
    UINT64_C(1409287868),	// C_SEQ_D64_MM
    UINT64_C(1174405178),	// C_SEQ_S
    UINT64_C(1409286844),	// C_SEQ_S_MM
    UINT64_C(1176502328),	// C_SF_D32
    UINT64_C(1409287740),	// C_SF_D32_MM
    UINT64_C(1176502328),	// C_SF_D64
    UINT64_C(1409287740),	// C_SF_D64_MM
    UINT64_C(1174405176),	// C_SF_S
    UINT64_C(1409286716),	// C_SF_S_MM
    UINT64_C(1176502323),	// C_UEQ_D32
    UINT64_C(1409287420),	// C_UEQ_D32_MM
    UINT64_C(1176502323),	// C_UEQ_D64
    UINT64_C(1409287420),	// C_UEQ_D64_MM
    UINT64_C(1174405171),	// C_UEQ_S
    UINT64_C(1409286396),	// C_UEQ_S_MM
    UINT64_C(1176502327),	// C_ULE_D32
    UINT64_C(1409287676),	// C_ULE_D32_MM
    UINT64_C(1176502327),	// C_ULE_D64
    UINT64_C(1409287676),	// C_ULE_D64_MM
    UINT64_C(1174405175),	// C_ULE_S
    UINT64_C(1409286652),	// C_ULE_S_MM
    UINT64_C(1176502325),	// C_ULT_D32
    UINT64_C(1409287548),	// C_ULT_D32_MM
    UINT64_C(1176502325),	// C_ULT_D64
    UINT64_C(1409287548),	// C_ULT_D64_MM
    UINT64_C(1174405173),	// C_ULT_S
    UINT64_C(1409286524),	// C_ULT_S_MM
    UINT64_C(1176502321),	// C_UN_D32
    UINT64_C(1409287292),	// C_UN_D32_MM
    UINT64_C(1176502321),	// C_UN_D64
    UINT64_C(1409287292),	// C_UN_D64_MM
    UINT64_C(1174405169),	// C_UN_S
    UINT64_C(1409286268),	// C_UN_S_MM
    UINT64_C(59402),	// CmpRxRy16
    UINT64_C(28672),	// CmpiRxImm16
    UINT64_C(4026560512),	// CmpiRxImmX16
    UINT64_C(44),	// DADD
    UINT64_C(1610612736),	// DADDi
    UINT64_C(1677721600),	// DADDiu
    UINT64_C(45),	// DADDu
    UINT64_C(67502080),	// DAHI
    UINT64_C(2080375332),	// DALIGN
    UINT64_C(69074944),	// DATI
    UINT64_C(1946157056),	// DAUI
    UINT64_C(2080374820),	// DBITSWAP
    UINT64_C(1879048229),	// DCLO
    UINT64_C(83),	// DCLO_R6
    UINT64_C(1879048228),	// DCLZ
    UINT64_C(82),	// DCLZ_R6
    UINT64_C(158),	// DDIV
    UINT64_C(159),	// DDIVU
    UINT64_C(1107296287),	// DERET
    UINT64_C(58236),	// DERET_MM
    UINT64_C(58236),	// DERET_MMR6
    UINT64_C(2080374787),	// DEXT
    UINT64_C(2080374787),	// DEXT64_32
    UINT64_C(2080374785),	// DEXTM
    UINT64_C(2080374786),	// DEXTU
    UINT64_C(1096835072),	// DI
    UINT64_C(2080374791),	// DINS
    UINT64_C(2080374789),	// DINSM
    UINT64_C(2080374790),	// DINSU
    UINT64_C(154),	// DIV
    UINT64_C(155),	// DIVU
    UINT64_C(408),	// DIVU_MMR6
    UINT64_C(280),	// DIV_MMR6
    UINT64_C(2046820370),	// DIV_S_B
    UINT64_C(2053111826),	// DIV_S_D
    UINT64_C(2048917522),	// DIV_S_H
    UINT64_C(2051014674),	// DIV_S_W
    UINT64_C(2055208978),	// DIV_U_B
    UINT64_C(2061500434),	// DIV_U_D
    UINT64_C(2057306130),	// DIV_U_H
    UINT64_C(2059403282),	// DIV_U_W
    UINT64_C(18300),	// DI_MM
    UINT64_C(18300),	// DI_MMR6
    UINT64_C(21),	// DLSA
    UINT64_C(21),	// DLSA_R6
    UINT64_C(1075838976),	// DMFC0
    UINT64_C(1142947840),	// DMFC1
    UINT64_C(1210056704),	// DMFC2
    UINT64_C(1210056704),	// DMFC2_OCTEON
    UINT64_C(1080033536),	// DMFGC0
    UINT64_C(222),	// DMOD
    UINT64_C(223),	// DMODU
    UINT64_C(1096813505),	// DMT
    UINT64_C(1084227584),	// DMTC0
    UINT64_C(1151336448),	// DMTC1
    UINT64_C(1218445312),	// DMTC2
    UINT64_C(1218445312),	// DMTC2_OCTEON
    UINT64_C(1080034048),	// DMTGC0
    UINT64_C(220),	// DMUH
    UINT64_C(221),	// DMUHU
    UINT64_C(1879048195),	// DMUL
    UINT64_C(28),	// DMULT
    UINT64_C(29),	// DMULTu
    UINT64_C(157),	// DMULU
    UINT64_C(156),	// DMUL_R6
    UINT64_C(2019557395),	// DOTP_S_D
    UINT64_C(2015363091),	// DOTP_S_H
    UINT64_C(2017460243),	// DOTP_S_W
    UINT64_C(2027946003),	// DOTP_U_D
    UINT64_C(2023751699),	// DOTP_U_H
    UINT64_C(2025848851),	// DOTP_U_W
    UINT64_C(2036334611),	// DPADD_S_D
    UINT64_C(2032140307),	// DPADD_S_H
    UINT64_C(2034237459),	// DPADD_S_W
    UINT64_C(2044723219),	// DPADD_U_D
    UINT64_C(2040528915),	// DPADD_U_H
    UINT64_C(2042626067),	// DPADD_U_W
    UINT64_C(2080376496),	// DPAQX_SA_W_PH
    UINT64_C(12988),	// DPAQX_SA_W_PH_MMR2
    UINT64_C(2080376368),	// DPAQX_S_W_PH
    UINT64_C(8892),	// DPAQX_S_W_PH_MMR2
    UINT64_C(2080375600),	// DPAQ_SA_L_W
    UINT64_C(4796),	// DPAQ_SA_L_W_MM
    UINT64_C(2080375088),	// DPAQ_S_W_PH
    UINT64_C(700),	// DPAQ_S_W_PH_MM
    UINT64_C(2080375024),	// DPAU_H_QBL
    UINT64_C(8380),	// DPAU_H_QBL_MM
    UINT64_C(2080375280),	// DPAU_H_QBR
    UINT64_C(12476),	// DPAU_H_QBR_MM
    UINT64_C(2080375344),	// DPAX_W_PH
    UINT64_C(4284),	// DPAX_W_PH_MMR2
    UINT64_C(2080374832),	// DPA_W_PH
    UINT64_C(188),	// DPA_W_PH_MMR2
    UINT64_C(1879048237),	// DPOP
    UINT64_C(2080376560),	// DPSQX_SA_W_PH
    UINT64_C(14012),	// DPSQX_SA_W_PH_MMR2
    UINT64_C(2080376432),	// DPSQX_S_W_PH
    UINT64_C(9916),	// DPSQX_S_W_PH_MMR2
    UINT64_C(2080375664),	// DPSQ_SA_L_W
    UINT64_C(5820),	// DPSQ_SA_L_W_MM
    UINT64_C(2080375152),	// DPSQ_S_W_PH
    UINT64_C(1724),	// DPSQ_S_W_PH_MM
    UINT64_C(2053111827),	// DPSUB_S_D
    UINT64_C(2048917523),	// DPSUB_S_H
    UINT64_C(2051014675),	// DPSUB_S_W
    UINT64_C(2061500435),	// DPSUB_U_D
    UINT64_C(2057306131),	// DPSUB_U_H
    UINT64_C(2059403283),	// DPSUB_U_W
    UINT64_C(2080375536),	// DPSU_H_QBL
    UINT64_C(9404),	// DPSU_H_QBL_MM
    UINT64_C(2080375792),	// DPSU_H_QBR
    UINT64_C(13500),	// DPSU_H_QBR_MM
    UINT64_C(2080375408),	// DPSX_W_PH
    UINT64_C(5308),	// DPSX_W_PH_MMR2
    UINT64_C(2080374896),	// DPS_W_PH
    UINT64_C(1212),	// DPS_W_PH_MMR2
    UINT64_C(2097210),	// DROTR
    UINT64_C(2097214),	// DROTR32
    UINT64_C(86),	// DROTRV
    UINT64_C(2080374948),	// DSBH
    UINT64_C(30),	// DSDIV
    UINT64_C(2080375140),	// DSHD
    UINT64_C(56),	// DSLL
    UINT64_C(60),	// DSLL32
    UINT64_C(60),	// DSLL64_32
    UINT64_C(20),	// DSLLV
    UINT64_C(59),	// DSRA
    UINT64_C(63),	// DSRA32
    UINT64_C(23),	// DSRAV
    UINT64_C(58),	// DSRL
    UINT64_C(62),	// DSRL32
    UINT64_C(22),	// DSRLV
    UINT64_C(46),	// DSUB
    UINT64_C(47),	// DSUBu
    UINT64_C(31),	// DUDIV
    UINT64_C(1096810532),	// DVP
    UINT64_C(1096810497),	// DVPE
    UINT64_C(6524),	// DVP_MMR6
    UINT64_C(59418),	// DivRxRy16
    UINT64_C(59419),	// DivuRxRy16
    UINT64_C(192),	// EHB
    UINT64_C(6144),	// EHB_MM
    UINT64_C(6144),	// EHB_MMR6
    UINT64_C(1096835104),	// EI
    UINT64_C(22396),	// EI_MM
    UINT64_C(22396),	// EI_MMR6
    UINT64_C(1096813537),	// EMT
    UINT64_C(1107296280),	// ERET
    UINT64_C(1107296344),	// ERETNC
    UINT64_C(127868),	// ERETNC_MMR6
    UINT64_C(62332),	// ERET_MM
    UINT64_C(62332),	// ERET_MMR6
    UINT64_C(1096810500),	// EVP
    UINT64_C(1096810529),	// EVPE
    UINT64_C(14716),	// EVP_MMR6
    UINT64_C(2080374784),	// EXT
    UINT64_C(2080374968),	// EXTP
    UINT64_C(2080375480),	// EXTPDP
    UINT64_C(2080375544),	// EXTPDPV
    UINT64_C(14524),	// EXTPDPV_MM
    UINT64_C(13948),	// EXTPDP_MM
    UINT64_C(2080375032),	// EXTPV
    UINT64_C(10428),	// EXTPV_MM
    UINT64_C(9852),	// EXTP_MM
    UINT64_C(2080375288),	// EXTRV_RS_W
    UINT64_C(11964),	// EXTRV_RS_W_MM
    UINT64_C(2080375160),	// EXTRV_R_W
    UINT64_C(7868),	// EXTRV_R_W_MM
    UINT64_C(2080375800),	// EXTRV_S_H
    UINT64_C(16060),	// EXTRV_S_H_MM
    UINT64_C(2080374904),	// EXTRV_W
    UINT64_C(3772),	// EXTRV_W_MM
    UINT64_C(2080375224),	// EXTR_RS_W
    UINT64_C(11900),	// EXTR_RS_W_MM
    UINT64_C(2080375096),	// EXTR_R_W
    UINT64_C(7804),	// EXTR_R_W_MM
    UINT64_C(2080375736),	// EXTR_S_H
    UINT64_C(15996),	// EXTR_S_H_MM
    UINT64_C(2080374840),	// EXTR_W
    UINT64_C(3708),	// EXTR_W_MM
    UINT64_C(1879048250),	// EXTS
    UINT64_C(1879048251),	// EXTS32
    UINT64_C(44),	// EXT_MM
    UINT64_C(44),	// EXT_MMR6
    UINT64_C(1176502277),	// FABS_D32
    UINT64_C(1409295227),	// FABS_D32_MM
    UINT64_C(1176502277),	// FABS_D64
    UINT64_C(1409295227),	// FABS_D64_MM
    UINT64_C(1174405125),	// FABS_S
    UINT64_C(1409287035),	// FABS_S_MM
    UINT64_C(2015363099),	// FADD_D
    UINT64_C(1176502272),	// FADD_D32
    UINT64_C(1409286448),	// FADD_D32_MM
    UINT64_C(1176502272),	// FADD_D64
    UINT64_C(1409286448),	// FADD_D64_MM
    UINT64_C(1186988032),	// FADD_PS64
    UINT64_C(1174405120),	// FADD_S
    UINT64_C(1409286192),	// FADD_S_MM
    UINT64_C(1409286192),	// FADD_S_MMR6
    UINT64_C(2013265947),	// FADD_W
    UINT64_C(2015363098),	// FCAF_D
    UINT64_C(2013265946),	// FCAF_W
    UINT64_C(2023751706),	// FCEQ_D
    UINT64_C(2021654554),	// FCEQ_W
    UINT64_C(2065760286),	// FCLASS_D
    UINT64_C(2065694750),	// FCLASS_W
    UINT64_C(2040528922),	// FCLE_D
    UINT64_C(2038431770),	// FCLE_W
    UINT64_C(2032140314),	// FCLT_D
    UINT64_C(2030043162),	// FCLT_W
    UINT64_C(1176502320),	// FCMP_D32
    UINT64_C(1409287228),	// FCMP_D32_MM
    UINT64_C(1176502320),	// FCMP_D64
    UINT64_C(1174405168),	// FCMP_S32
    UINT64_C(1409286204),	// FCMP_S32_MM
    UINT64_C(2027946012),	// FCNE_D
    UINT64_C(2025848860),	// FCNE_W
    UINT64_C(2019557404),	// FCOR_D
    UINT64_C(2017460252),	// FCOR_W
    UINT64_C(2027946010),	// FCUEQ_D
    UINT64_C(2025848858),	// FCUEQ_W
    UINT64_C(2044723226),	// FCULE_D
    UINT64_C(2042626074),	// FCULE_W
    UINT64_C(2036334618),	// FCULT_D
    UINT64_C(2034237466),	// FCULT_W
    UINT64_C(2023751708),	// FCUNE_D
    UINT64_C(2021654556),	// FCUNE_W
    UINT64_C(2019557402),	// FCUN_D
    UINT64_C(2017460250),	// FCUN_W
    UINT64_C(2027946011),	// FDIV_D
    UINT64_C(1176502275),	// FDIV_D32
    UINT64_C(1409286640),	// FDIV_D32_MM
    UINT64_C(1176502275),	// FDIV_D64
    UINT64_C(1409286640),	// FDIV_D64_MM
    UINT64_C(1174405123),	// FDIV_S
    UINT64_C(1409286384),	// FDIV_S_MM
    UINT64_C(1409286384),	// FDIV_S_MMR6
    UINT64_C(2025848859),	// FDIV_W
    UINT64_C(2046820379),	// FEXDO_H
    UINT64_C(2048917531),	// FEXDO_W
    UINT64_C(2044723227),	// FEXP2_D
    UINT64_C(2042626075),	// FEXP2_W
    UINT64_C(2066808862),	// FEXUPL_D
    UINT64_C(2066743326),	// FEXUPL_W
    UINT64_C(2066939934),	// FEXUPR_D
    UINT64_C(2066874398),	// FEXUPR_W
    UINT64_C(2067595294),	// FFINT_S_D
    UINT64_C(2067529758),	// FFINT_S_W
    UINT64_C(2067726366),	// FFINT_U_D
    UINT64_C(2067660830),	// FFINT_U_W
    UINT64_C(2067071006),	// FFQL_D
    UINT64_C(2067005470),	// FFQL_W
    UINT64_C(2067202078),	// FFQR_D
    UINT64_C(2067136542),	// FFQR_W
    UINT64_C(2063597598),	// FILL_B
    UINT64_C(2063794206),	// FILL_D
    UINT64_C(2063663134),	// FILL_H
    UINT64_C(2063728670),	// FILL_W
    UINT64_C(2066677790),	// FLOG2_D
    UINT64_C(2066612254),	// FLOG2_W
    UINT64_C(1176502283),	// FLOOR_L_D64
    UINT64_C(1409303355),	// FLOOR_L_D_MMR6
    UINT64_C(1174405131),	// FLOOR_L_S
    UINT64_C(1409286971),	// FLOOR_L_S_MMR6
    UINT64_C(1176502287),	// FLOOR_W_D32
    UINT64_C(1176502287),	// FLOOR_W_D64
    UINT64_C(1409305403),	// FLOOR_W_D_MMR6
    UINT64_C(1409305403),	// FLOOR_W_MM
    UINT64_C(1174405135),	// FLOOR_W_S
    UINT64_C(1409289019),	// FLOOR_W_S_MM
    UINT64_C(1409289019),	// FLOOR_W_S_MMR6
    UINT64_C(2032140315),	// FMADD_D
    UINT64_C(2030043163),	// FMADD_W
    UINT64_C(2078277659),	// FMAX_A_D
    UINT64_C(2076180507),	// FMAX_A_W
    UINT64_C(2074083355),	// FMAX_D
    UINT64_C(2071986203),	// FMAX_W
    UINT64_C(2069889051),	// FMIN_A_D
    UINT64_C(2067791899),	// FMIN_A_W
    UINT64_C(2065694747),	// FMIN_D
    UINT64_C(2063597595),	// FMIN_W
    UINT64_C(1176502278),	// FMOV_D32
    UINT64_C(1409294459),	// FMOV_D32_MM
    UINT64_C(1176502278),	// FMOV_D64
    UINT64_C(1409294459),	// FMOV_D64_MM
    UINT64_C(1409294459),	// FMOV_D_MMR6
    UINT64_C(1174405126),	// FMOV_S
    UINT64_C(1409286267),	// FMOV_S_MM
    UINT64_C(1409286267),	// FMOV_S_MMR6
    UINT64_C(2036334619),	// FMSUB_D
    UINT64_C(2034237467),	// FMSUB_W
    UINT64_C(2023751707),	// FMUL_D
    UINT64_C(1176502274),	// FMUL_D32
    UINT64_C(1409286576),	// FMUL_D32_MM
    UINT64_C(1176502274),	// FMUL_D64
    UINT64_C(1409286576),	// FMUL_D64_MM
    UINT64_C(1186988034),	// FMUL_PS64
    UINT64_C(1174405122),	// FMUL_S
    UINT64_C(1409286320),	// FMUL_S_MM
    UINT64_C(1409286320),	// FMUL_S_MMR6
    UINT64_C(2021654555),	// FMUL_W
    UINT64_C(1176502279),	// FNEG_D32
    UINT64_C(1409297275),	// FNEG_D32_MM
    UINT64_C(1176502279),	// FNEG_D64
    UINT64_C(1409297275),	// FNEG_D64_MM
    UINT64_C(1174405127),	// FNEG_S
    UINT64_C(1409289083),	// FNEG_S_MM
    UINT64_C(1409289083),	// FNEG_S_MMR6
    UINT64_C(2080374792),	// FORK
    UINT64_C(2066415646),	// FRCP_D
    UINT64_C(2066350110),	// FRCP_W
    UINT64_C(2066546718),	// FRINT_D
    UINT64_C(2066481182),	// FRINT_W
    UINT64_C(2066284574),	// FRSQRT_D
    UINT64_C(2066219038),	// FRSQRT_W
    UINT64_C(2048917530),	// FSAF_D
    UINT64_C(2046820378),	// FSAF_W
    UINT64_C(2057306138),	// FSEQ_D
    UINT64_C(2055208986),	// FSEQ_W
    UINT64_C(2074083354),	// FSLE_D
    UINT64_C(2071986202),	// FSLE_W
    UINT64_C(2065694746),	// FSLT_D
    UINT64_C(2063597594),	// FSLT_W
    UINT64_C(2061500444),	// FSNE_D
    UINT64_C(2059403292),	// FSNE_W
    UINT64_C(2053111836),	// FSOR_D
    UINT64_C(2051014684),	// FSOR_W
    UINT64_C(2066153502),	// FSQRT_D
    UINT64_C(1176502276),	// FSQRT_D32
    UINT64_C(1409305147),	// FSQRT_D32_MM
    UINT64_C(1176502276),	// FSQRT_D64
    UINT64_C(1409305147),	// FSQRT_D64_MM
    UINT64_C(1174405124),	// FSQRT_S
    UINT64_C(1409288763),	// FSQRT_S_MM
    UINT64_C(2066087966),	// FSQRT_W
    UINT64_C(2019557403),	// FSUB_D
    UINT64_C(1176502273),	// FSUB_D32
    UINT64_C(1409286512),	// FSUB_D32_MM
    UINT64_C(1176502273),	// FSUB_D64
    UINT64_C(1409286512),	// FSUB_D64_MM
    UINT64_C(1186988033),	// FSUB_PS64
    UINT64_C(1174405121),	// FSUB_S
    UINT64_C(1409286256),	// FSUB_S_MM
    UINT64_C(1409286256),	// FSUB_S_MMR6
    UINT64_C(2017460251),	// FSUB_W
    UINT64_C(2061500442),	// FSUEQ_D
    UINT64_C(2059403290),	// FSUEQ_W
    UINT64_C(2078277658),	// FSULE_D
    UINT64_C(2076180506),	// FSULE_W
    UINT64_C(2069889050),	// FSULT_D
    UINT64_C(2067791898),	// FSULT_W
    UINT64_C(2057306140),	// FSUNE_D
    UINT64_C(2055208988),	// FSUNE_W
    UINT64_C(2053111834),	// FSUN_D
    UINT64_C(2051014682),	// FSUN_W
    UINT64_C(2067333150),	// FTINT_S_D
    UINT64_C(2067267614),	// FTINT_S_W
    UINT64_C(2067464222),	// FTINT_U_D
    UINT64_C(2067398686),	// FTINT_U_W
    UINT64_C(2055208987),	// FTQ_H
    UINT64_C(2057306139),	// FTQ_W
    UINT64_C(2065891358),	// FTRUNC_S_D
    UINT64_C(2065825822),	// FTRUNC_S_W
    UINT64_C(2066022430),	// FTRUNC_U_D
    UINT64_C(2065956894),	// FTRUNC_U_W
    UINT64_C(2080374845),	// GINVI
    UINT64_C(24956),	// GINVI_MMR6
    UINT64_C(2080374973),	// GINVT
    UINT64_C(29052),	// GINVT_MMR6
    UINT64_C(2053111829),	// HADD_S_D
    UINT64_C(2048917525),	// HADD_S_H
    UINT64_C(2051014677),	// HADD_S_W
    UINT64_C(2061500437),	// HADD_U_D
    UINT64_C(2057306133),	// HADD_U_H
    UINT64_C(2059403285),	// HADD_U_W
    UINT64_C(2069889045),	// HSUB_S_D
    UINT64_C(2065694741),	// HSUB_S_H
    UINT64_C(2067791893),	// HSUB_S_W
    UINT64_C(2078277653),	// HSUB_U_D
    UINT64_C(2074083349),	// HSUB_U_H
    UINT64_C(2076180501),	// HSUB_U_W
    UINT64_C(1107296296),	// HYPCALL
    UINT64_C(50044),	// HYPCALL_MM
    UINT64_C(2063597588),	// ILVEV_B
    UINT64_C(2069889044),	// ILVEV_D
    UINT64_C(2065694740),	// ILVEV_H
    UINT64_C(2067791892),	// ILVEV_W
    UINT64_C(2046820372),	// ILVL_B
    UINT64_C(2053111828),	// ILVL_D
    UINT64_C(2048917524),	// ILVL_H
    UINT64_C(2051014676),	// ILVL_W
    UINT64_C(2071986196),	// ILVOD_B
    UINT64_C(2078277652),	// ILVOD_D
    UINT64_C(2074083348),	// ILVOD_H
    UINT64_C(2076180500),	// ILVOD_W
    UINT64_C(2055208980),	// ILVR_B
    UINT64_C(2061500436),	// ILVR_D
    UINT64_C(2057306132),	// ILVR_H
    UINT64_C(2059403284),	// ILVR_W
    UINT64_C(2080374788),	// INS
    UINT64_C(2030043161),	// INSERT_B
    UINT64_C(2033713177),	// INSERT_D
    UINT64_C(2032140313),	// INSERT_H
    UINT64_C(2033188889),	// INSERT_W
    UINT64_C(2080374796),	// INSV
    UINT64_C(2034237465),	// INSVE_B
    UINT64_C(2037907481),	// INSVE_D
    UINT64_C(2036334617),	// INSVE_H
    UINT64_C(2037383193),	// INSVE_W
    UINT64_C(16700),	// INSV_MM
    UINT64_C(12),	// INS_MM
    UINT64_C(12),	// INS_MMR6
    UINT64_C(134217728),	// J
    UINT64_C(201326592),	// JAL
    UINT64_C(9),	// JALR
    UINT64_C(17856),	// JALR16_MM
    UINT64_C(9),	// JALR64
    UINT64_C(17419),	// JALRC16_MMR6
    UINT64_C(7996),	// JALRC_HB_MMR6
    UINT64_C(3900),	// JALRC_MMR6
    UINT64_C(17888),	// JALRS16_MM
    UINT64_C(20284),	// JALRS_MM
    UINT64_C(1033),	// JALR_HB
    UINT64_C(1033),	// JALR_HB64
    UINT64_C(3900),	// JALR_MM
    UINT64_C(1946157056),	// JALS_MM
    UINT64_C(1946157056),	// JALX
    UINT64_C(4026531840),	// JALX_MM
    UINT64_C(4093640704),	// JAL_MM
    UINT64_C(4160749568),	// JIALC
    UINT64_C(4160749568),	// JIALC64
    UINT64_C(2147483648),	// JIALC_MMR6
    UINT64_C(3623878656),	// JIC
    UINT64_C(3623878656),	// JIC64
    UINT64_C(2684354560),	// JIC_MMR6
    UINT64_C(8),	// JR
    UINT64_C(17792),	// JR16_MM
    UINT64_C(8),	// JR64
    UINT64_C(18176),	// JRADDIUSP
    UINT64_C(17824),	// JRC16_MM
    UINT64_C(17411),	// JRC16_MMR6
    UINT64_C(17427),	// JRCADDIUSP_MMR6
    UINT64_C(1032),	// JR_HB
    UINT64_C(1032),	// JR_HB64
    UINT64_C(1033),	// JR_HB64_R6
    UINT64_C(1033),	// JR_HB_R6
    UINT64_C(3900),	// JR_MM
    UINT64_C(3556769792),	// J_MM
    UINT64_C(402653184),	// Jal16
    UINT64_C(402653184),	// JalB16
    UINT64_C(59424),	// JrRa16
    UINT64_C(59616),	// JrcRa16
    UINT64_C(59584),	// JrcRx16
    UINT64_C(59392),	// JumpLinkReg16
    UINT64_C(2147483648),	// LB
    UINT64_C(2147483648),	// LB64
    UINT64_C(2080374828),	// LBE
    UINT64_C(1610639360),	// LBE_MM
    UINT64_C(2048),	// LBU16_MM
    UINT64_C(2080375178),	// LBUX
    UINT64_C(549),	// LBUX_MM
    UINT64_C(335544320),	// LBU_MMR6
    UINT64_C(469762048),	// LB_MM
    UINT64_C(469762048),	// LB_MMR6
    UINT64_C(2415919104),	// LBu
    UINT64_C(2415919104),	// LBu64
    UINT64_C(2080374824),	// LBuE
    UINT64_C(1610637312),	// LBuE_MM
    UINT64_C(335544320),	// LBu_MM
    UINT64_C(3690987520),	// LD
    UINT64_C(3556769792),	// LDC1
    UINT64_C(3556769792),	// LDC164
    UINT64_C(3154116608),	// LDC1_D64_MMR6
    UINT64_C(3154116608),	// LDC1_MM_D32
    UINT64_C(3154116608),	// LDC1_MM_D64
    UINT64_C(3623878656),	// LDC2
    UINT64_C(536879104),	// LDC2_MMR6
    UINT64_C(1237319680),	// LDC2_R6
    UINT64_C(3690987520),	// LDC3
    UINT64_C(2063597575),	// LDI_B
    UINT64_C(2069889031),	// LDI_D
    UINT64_C(2065694727),	// LDI_H
    UINT64_C(2067791879),	// LDI_W
    UINT64_C(1744830464),	// LDL
    UINT64_C(3960995840),	// LDPC
    UINT64_C(1811939328),	// LDR
    UINT64_C(1275068417),	// LDXC1
    UINT64_C(1275068417),	// LDXC164
    UINT64_C(2013265952),	// LD_B
    UINT64_C(2013265955),	// LD_D
    UINT64_C(2013265953),	// LD_H
    UINT64_C(2013265954),	// LD_W
    UINT64_C(603979776),	// LEA_ADDiu
    UINT64_C(1677721600),	// LEA_ADDiu64
    UINT64_C(805306368),	// LEA_ADDiu_MM
    UINT64_C(2214592512),	// LH
    UINT64_C(2214592512),	// LH64
    UINT64_C(2080374829),	// LHE
    UINT64_C(1610639872),	// LHE_MM
    UINT64_C(10240),	// LHU16_MM
    UINT64_C(2080375050),	// LHX
    UINT64_C(357),	// LHX_MM
    UINT64_C(1006632960),	// LH_MM
    UINT64_C(2483027968),	// LHu
    UINT64_C(2483027968),	// LHu64
    UINT64_C(2080374825),	// LHuE
    UINT64_C(1610637824),	// LHuE_MM
    UINT64_C(872415232),	// LHu_MM
    UINT64_C(60416),	// LI16_MM
    UINT64_C(60416),	// LI16_MMR6
    UINT64_C(3221225472),	// LL
    UINT64_C(3221225472),	// LL64
    UINT64_C(2080374838),	// LL64_R6
    UINT64_C(3489660928),	// LLD
    UINT64_C(2080374839),	// LLD_R6
    UINT64_C(2080374830),	// LLE
    UINT64_C(1610640384),	// LLE_MM
    UINT64_C(1610625024),	// LL_MM
    UINT64_C(1610625024),	// LL_MMR6
    UINT64_C(2080374838),	// LL_R6
    UINT64_C(5),	// LSA
    UINT64_C(15),	// LSA_MMR6
    UINT64_C(5),	// LSA_R6
    UINT64_C(268435456),	// LUI_MMR6
    UINT64_C(1275068421),	// LUXC1
    UINT64_C(1275068421),	// LUXC164
    UINT64_C(1409286472),	// LUXC1_MM
    UINT64_C(1006632960),	// LUi
    UINT64_C(1006632960),	// LUi64
    UINT64_C(1101004800),	// LUi_MM
    UINT64_C(2348810240),	// LW
    UINT64_C(26624),	// LW16_MM
    UINT64_C(2348810240),	// LW64
    UINT64_C(3288334336),	// LWC1
    UINT64_C(2617245696),	// LWC1_MM
    UINT64_C(3355443200),	// LWC2
    UINT64_C(536870912),	// LWC2_MMR6
    UINT64_C(1228931072),	// LWC2_R6
    UINT64_C(3422552064),	// LWC3
    UINT64_C(2348810240),	// LWDSP
    UINT64_C(4227858432),	// LWDSP_MM
    UINT64_C(2080374831),	// LWE
    UINT64_C(1610640896),	// LWE_MM
    UINT64_C(25600),	// LWGP_MM
    UINT64_C(2281701376),	// LWL
    UINT64_C(2281701376),	// LWL64
    UINT64_C(2080374809),	// LWLE
    UINT64_C(1610638336),	// LWLE_MM
    UINT64_C(1610612736),	// LWL_MM
    UINT64_C(17664),	// LWM16_MM
    UINT64_C(17410),	// LWM16_MMR6
    UINT64_C(536891392),	// LWM32_MM
    UINT64_C(3959947264),	// LWPC
    UINT64_C(2013790208),	// LWPC_MMR6
    UINT64_C(536875008),	// LWP_MM
    UINT64_C(2550136832),	// LWR
    UINT64_C(2550136832),	// LWR64
    UINT64_C(2080374810),	// LWRE
    UINT64_C(1610638848),	// LWRE_MM
    UINT64_C(1610616832),	// LWR_MM
    UINT64_C(18432),	// LWSP_MM
    UINT64_C(3960471552),	// LWUPC
    UINT64_C(1610670080),	// LWU_MM
    UINT64_C(2080374794),	// LWX
    UINT64_C(1275068416),	// LWXC1
    UINT64_C(1409286216),	// LWXC1_MM
    UINT64_C(280),	// LWXS_MM
    UINT64_C(421),	// LWX_MM
    UINT64_C(4227858432),	// LW_MM
    UINT64_C(4227858432),	// LW_MMR6
    UINT64_C(2617245696),	// LWu
    UINT64_C(4026570752),	// LbRxRyOffMemX16
    UINT64_C(4026572800),	// LbuRxRyOffMemX16
    UINT64_C(4026572800),	// LhRxRyOffMemX16
    UINT64_C(4026572800),	// LhuRxRyOffMemX16
    UINT64_C(26624),	// LiRxImm16
    UINT64_C(4026558464),	// LiRxImmAlignX16
    UINT64_C(4026558464),	// LiRxImmX16
    UINT64_C(45056),	// LwRxPcTcp16
    UINT64_C(4026576896),	// LwRxPcTcpX16
    UINT64_C(4026570752),	// LwRxRyOffMemX16
    UINT64_C(4026568704),	// LwRxSpImmX16
    UINT64_C(1879048192),	// MADD
    UINT64_C(1176502296),	// MADDF_D
    UINT64_C(1409287096),	// MADDF_D_MMR6
    UINT64_C(1174405144),	// MADDF_S
    UINT64_C(1409286584),	// MADDF_S_MMR6
    UINT64_C(2067791900),	// MADDR_Q_H
    UINT64_C(2069889052),	// MADDR_Q_W
    UINT64_C(1879048193),	// MADDU
    UINT64_C(1879048193),	// MADDU_DSP
    UINT64_C(6844),	// MADDU_DSP_MM
    UINT64_C(56124),	// MADDU_MM
    UINT64_C(2021654546),	// MADDV_B
    UINT64_C(2027946002),	// MADDV_D
    UINT64_C(2023751698),	// MADDV_H
    UINT64_C(2025848850),	// MADDV_W
    UINT64_C(1275068449),	// MADD_D32
    UINT64_C(1409286153),	// MADD_D32_MM
    UINT64_C(1275068449),	// MADD_D64
    UINT64_C(1879048192),	// MADD_DSP
    UINT64_C(2748),	// MADD_DSP_MM
    UINT64_C(52028),	// MADD_MM
    UINT64_C(2034237468),	// MADD_Q_H
    UINT64_C(2036334620),	// MADD_Q_W
    UINT64_C(1275068448),	// MADD_S
    UINT64_C(1409286145),	// MADD_S_MM
    UINT64_C(2080375856),	// MAQ_SA_W_PHL
    UINT64_C(14972),	// MAQ_SA_W_PHL_MM
    UINT64_C(2080375984),	// MAQ_SA_W_PHR
    UINT64_C(10876),	// MAQ_SA_W_PHR_MM
    UINT64_C(2080376112),	// MAQ_S_W_PHL
    UINT64_C(6780),	// MAQ_S_W_PHL_MM
    UINT64_C(2080376240),	// MAQ_S_W_PHR
    UINT64_C(2684),	// MAQ_S_W_PHR_MM
    UINT64_C(1176502303),	// MAXA_D
    UINT64_C(1409286699),	// MAXA_D_MMR6
    UINT64_C(1174405151),	// MAXA_S
    UINT64_C(1409286187),	// MAXA_S_MMR6
    UINT64_C(2030043142),	// MAXI_S_B
    UINT64_C(2036334598),	// MAXI_S_D
    UINT64_C(2032140294),	// MAXI_S_H
    UINT64_C(2034237446),	// MAXI_S_W
    UINT64_C(2038431750),	// MAXI_U_B
    UINT64_C(2044723206),	// MAXI_U_D
    UINT64_C(2040528902),	// MAXI_U_H
    UINT64_C(2042626054),	// MAXI_U_W
    UINT64_C(2063597582),	// MAX_A_B
    UINT64_C(2069889038),	// MAX_A_D
    UINT64_C(2065694734),	// MAX_A_H
    UINT64_C(2067791886),	// MAX_A_W
    UINT64_C(1176502302),	// MAX_D
    UINT64_C(1409286667),	// MAX_D_MMR6
    UINT64_C(1174405150),	// MAX_S
    UINT64_C(2030043150),	// MAX_S_B
    UINT64_C(2036334606),	// MAX_S_D
    UINT64_C(2032140302),	// MAX_S_H
    UINT64_C(1409286155),	// MAX_S_MMR6
    UINT64_C(2034237454),	// MAX_S_W
    UINT64_C(2038431758),	// MAX_U_B
    UINT64_C(2044723214),	// MAX_U_D
    UINT64_C(2040528910),	// MAX_U_H
    UINT64_C(2042626062),	// MAX_U_W
    UINT64_C(1073741824),	// MFC0
    UINT64_C(252),	// MFC0_MMR6
    UINT64_C(1140850688),	// MFC1
    UINT64_C(1140850688),	// MFC1_D64
    UINT64_C(1409294395),	// MFC1_MM
    UINT64_C(1409294395),	// MFC1_MMR6
    UINT64_C(1207959552),	// MFC2
    UINT64_C(19772),	// MFC2_MMR6
    UINT64_C(1080033280),	// MFGC0
    UINT64_C(1276),	// MFGC0_MM
    UINT64_C(244),	// MFHC0_MMR6
    UINT64_C(1147142144),	// MFHC1_D32
    UINT64_C(1409298491),	// MFHC1_D32_MM
    UINT64_C(1147142144),	// MFHC1_D64
    UINT64_C(1409298491),	// MFHC1_D64_MM
    UINT64_C(36156),	// MFHC2_MMR6
    UINT64_C(1080034304),	// MFHGC0
    UINT64_C(1268),	// MFHGC0_MM
    UINT64_C(16),	// MFHI
    UINT64_C(17920),	// MFHI16_MM
    UINT64_C(16),	// MFHI64
    UINT64_C(16),	// MFHI_DSP
    UINT64_C(124),	// MFHI_DSP_MM
    UINT64_C(3452),	// MFHI_MM
    UINT64_C(18),	// MFLO
    UINT64_C(17984),	// MFLO16_MM
    UINT64_C(18),	// MFLO64
    UINT64_C(18),	// MFLO_DSP
    UINT64_C(4220),	// MFLO_DSP_MM
    UINT64_C(7548),	// MFLO_MM
    UINT64_C(1090519040),	// MFTR
    UINT64_C(1176502301),	// MINA_D
    UINT64_C(1409286691),	// MINA_D_MMR6
    UINT64_C(1174405149),	// MINA_S
    UINT64_C(1409286179),	// MINA_S_MMR6
    UINT64_C(2046820358),	// MINI_S_B
    UINT64_C(2053111814),	// MINI_S_D
    UINT64_C(2048917510),	// MINI_S_H
    UINT64_C(2051014662),	// MINI_S_W
    UINT64_C(2055208966),	// MINI_U_B
    UINT64_C(2061500422),	// MINI_U_D
    UINT64_C(2057306118),	// MINI_U_H
    UINT64_C(2059403270),	// MINI_U_W
    UINT64_C(2071986190),	// MIN_A_B
    UINT64_C(2078277646),	// MIN_A_D
    UINT64_C(2074083342),	// MIN_A_H
    UINT64_C(2076180494),	// MIN_A_W
    UINT64_C(1176502300),	// MIN_D
    UINT64_C(1409286659),	// MIN_D_MMR6
    UINT64_C(1174405148),	// MIN_S
    UINT64_C(2046820366),	// MIN_S_B
    UINT64_C(2053111822),	// MIN_S_D
    UINT64_C(2048917518),	// MIN_S_H
    UINT64_C(1409286147),	// MIN_S_MMR6
    UINT64_C(2051014670),	// MIN_S_W
    UINT64_C(2055208974),	// MIN_U_B
    UINT64_C(2061500430),	// MIN_U_D
    UINT64_C(2057306126),	// MIN_U_H
    UINT64_C(2059403278),	// MIN_U_W
    UINT64_C(218),	// MOD
    UINT64_C(2080375952),	// MODSUB
    UINT64_C(661),	// MODSUB_MM
    UINT64_C(219),	// MODU
    UINT64_C(472),	// MODU_MMR6
    UINT64_C(344),	// MOD_MMR6
    UINT64_C(2063597586),	// MOD_S_B
    UINT64_C(2069889042),	// MOD_S_D
    UINT64_C(2065694738),	// MOD_S_H
    UINT64_C(2067791890),	// MOD_S_W
    UINT64_C(2071986194),	// MOD_U_B
    UINT64_C(2078277650),	// MOD_U_D
    UINT64_C(2074083346),	// MOD_U_H
    UINT64_C(2076180498),	// MOD_U_W
    UINT64_C(3072),	// MOVE16_MM
    UINT64_C(3072),	// MOVE16_MMR6
    UINT64_C(33792),	// MOVEP_MM
    UINT64_C(17412),	// MOVEP_MMR6
    UINT64_C(2025717785),	// MOVE_V
    UINT64_C(1176502289),	// MOVF_D32
    UINT64_C(1409286688),	// MOVF_D32_MM
    UINT64_C(1176502289),	// MOVF_D64
    UINT64_C(1),	// MOVF_I
    UINT64_C(1),	// MOVF_I64
    UINT64_C(1409286523),	// MOVF_I_MM
    UINT64_C(1174405137),	// MOVF_S
    UINT64_C(1409286176),	// MOVF_S_MM
    UINT64_C(1176502291),	// MOVN_I64_D64
    UINT64_C(11),	// MOVN_I64_I
    UINT64_C(11),	// MOVN_I64_I64
    UINT64_C(1174405139),	// MOVN_I64_S
    UINT64_C(1176502291),	// MOVN_I_D32
    UINT64_C(1409286456),	// MOVN_I_D32_MM
    UINT64_C(1176502291),	// MOVN_I_D64
    UINT64_C(11),	// MOVN_I_I
    UINT64_C(11),	// MOVN_I_I64
    UINT64_C(24),	// MOVN_I_MM
    UINT64_C(1174405139),	// MOVN_I_S
    UINT64_C(1409286200),	// MOVN_I_S_MM
    UINT64_C(1176567825),	// MOVT_D32
    UINT64_C(1409286752),	// MOVT_D32_MM
    UINT64_C(1176567825),	// MOVT_D64
    UINT64_C(65537),	// MOVT_I
    UINT64_C(65537),	// MOVT_I64
    UINT64_C(1409288571),	// MOVT_I_MM
    UINT64_C(1174470673),	// MOVT_S
    UINT64_C(1409286240),	// MOVT_S_MM
    UINT64_C(1176502290),	// MOVZ_I64_D64
    UINT64_C(10),	// MOVZ_I64_I
    UINT64_C(10),	// MOVZ_I64_I64
    UINT64_C(1174405138),	// MOVZ_I64_S
    UINT64_C(1176502290),	// MOVZ_I_D32
    UINT64_C(1409286520),	// MOVZ_I_D32_MM
    UINT64_C(1176502290),	// MOVZ_I_D64
    UINT64_C(10),	// MOVZ_I_I
    UINT64_C(10),	// MOVZ_I_I64
    UINT64_C(88),	// MOVZ_I_MM
    UINT64_C(1174405138),	// MOVZ_I_S
    UINT64_C(1409286264),	// MOVZ_I_S_MM
    UINT64_C(1879048196),	// MSUB
    UINT64_C(1176502297),	// MSUBF_D
    UINT64_C(1409287160),	// MSUBF_D_MMR6
    UINT64_C(1174405145),	// MSUBF_S
    UINT64_C(1409286648),	// MSUBF_S_MMR6
    UINT64_C(2071986204),	// MSUBR_Q_H
    UINT64_C(2074083356),	// MSUBR_Q_W
    UINT64_C(1879048197),	// MSUBU
    UINT64_C(1879048197),	// MSUBU_DSP
    UINT64_C(15036),	// MSUBU_DSP_MM
    UINT64_C(64316),	// MSUBU_MM
    UINT64_C(2030043154),	// MSUBV_B
    UINT64_C(2036334610),	// MSUBV_D
    UINT64_C(2032140306),	// MSUBV_H
    UINT64_C(2034237458),	// MSUBV_W
    UINT64_C(1275068457),	// MSUB_D32
    UINT64_C(1409286185),	// MSUB_D32_MM
    UINT64_C(1275068457),	// MSUB_D64
    UINT64_C(1879048196),	// MSUB_DSP
    UINT64_C(10940),	// MSUB_DSP_MM
    UINT64_C(60220),	// MSUB_MM
    UINT64_C(2038431772),	// MSUB_Q_H
    UINT64_C(2040528924),	// MSUB_Q_W
    UINT64_C(1275068456),	// MSUB_S
    UINT64_C(1409286177),	// MSUB_S_MM
    UINT64_C(1082130432),	// MTC0
    UINT64_C(764),	// MTC0_MMR6
    UINT64_C(1149239296),	// MTC1
    UINT64_C(1149239296),	// MTC1_D64
    UINT64_C(1409296443),	// MTC1_D64_MM
    UINT64_C(1409296443),	// MTC1_MM
    UINT64_C(1409296443),	// MTC1_MMR6
    UINT64_C(1216348160),	// MTC2
    UINT64_C(23868),	// MTC2_MMR6
    UINT64_C(1080033792),	// MTGC0
    UINT64_C(1788),	// MTGC0_MM
    UINT64_C(756),	// MTHC0_MMR6
    UINT64_C(1155530752),	// MTHC1_D32
    UINT64_C(1409300539),	// MTHC1_D32_MM
    UINT64_C(1155530752),	// MTHC1_D64
    UINT64_C(1409300539),	// MTHC1_D64_MM
    UINT64_C(40252),	// MTHC2_MMR6
    UINT64_C(1080034816),	// MTHGC0
    UINT64_C(1780),	// MTHGC0_MM
    UINT64_C(17),	// MTHI
    UINT64_C(17),	// MTHI64
    UINT64_C(17),	// MTHI_DSP
    UINT64_C(8316),	// MTHI_DSP_MM
    UINT64_C(11644),	// MTHI_MM
    UINT64_C(2080376824),	// MTHLIP
    UINT64_C(636),	// MTHLIP_MM
    UINT64_C(19),	// MTLO
    UINT64_C(19),	// MTLO64
    UINT64_C(19),	// MTLO_DSP
    UINT64_C(12412),	// MTLO_DSP_MM
    UINT64_C(15740),	// MTLO_MM
    UINT64_C(1879048200),	// MTM0
    UINT64_C(1879048204),	// MTM1
    UINT64_C(1879048205),	// MTM2
    UINT64_C(1879048201),	// MTP0
    UINT64_C(1879048202),	// MTP1
    UINT64_C(1879048203),	// MTP2
    UINT64_C(1098907648),	// MTTR
    UINT64_C(216),	// MUH
    UINT64_C(217),	// MUHU
    UINT64_C(216),	// MUHU_MMR6
    UINT64_C(88),	// MUH_MMR6
    UINT64_C(1879048194),	// MUL
    UINT64_C(2080376592),	// MULEQ_S_W_PHL
    UINT64_C(37),	// MULEQ_S_W_PHL_MM
    UINT64_C(2080376656),	// MULEQ_S_W_PHR
    UINT64_C(101),	// MULEQ_S_W_PHR_MM
    UINT64_C(2080375184),	// MULEU_S_PH_QBL
    UINT64_C(149),	// MULEU_S_PH_QBL_MM
    UINT64_C(2080375248),	// MULEU_S_PH_QBR
    UINT64_C(213),	// MULEU_S_PH_QBR_MM
    UINT64_C(2080376784),	// MULQ_RS_PH
    UINT64_C(277),	// MULQ_RS_PH_MM
    UINT64_C(2080376280),	// MULQ_RS_W
    UINT64_C(405),	// MULQ_RS_W_MMR2
    UINT64_C(2080376720),	// MULQ_S_PH
    UINT64_C(341),	// MULQ_S_PH_MMR2
    UINT64_C(2080376216),	// MULQ_S_W
    UINT64_C(469),	// MULQ_S_W_MMR2
    UINT64_C(1186988058),	// MULR_PS64
    UINT64_C(2063597596),	// MULR_Q_H
    UINT64_C(2065694748),	// MULR_Q_W
    UINT64_C(2080375216),	// MULSAQ_S_W_PH
    UINT64_C(15548),	// MULSAQ_S_W_PH_MM
    UINT64_C(2080374960),	// MULSA_W_PH
    UINT64_C(11452),	// MULSA_W_PH_MMR2
    UINT64_C(24),	// MULT
    UINT64_C(25),	// MULTU_DSP
    UINT64_C(7356),	// MULTU_DSP_MM
    UINT64_C(24),	// MULT_DSP
    UINT64_C(3260),	// MULT_DSP_MM
    UINT64_C(35644),	// MULT_MM
    UINT64_C(25),	// MULTu
    UINT64_C(39740),	// MULTu_MM
    UINT64_C(153),	// MULU
    UINT64_C(152),	// MULU_MMR6
    UINT64_C(2013265938),	// MULV_B
    UINT64_C(2019557394),	// MULV_D
    UINT64_C(2015363090),	// MULV_H
    UINT64_C(2017460242),	// MULV_W
    UINT64_C(528),	// MUL_MM
    UINT64_C(24),	// MUL_MMR6
    UINT64_C(2080375576),	// MUL_PH
    UINT64_C(45),	// MUL_PH_MMR2
    UINT64_C(2030043164),	// MUL_Q_H
    UINT64_C(2032140316),	// MUL_Q_W
    UINT64_C(152),	// MUL_R6
    UINT64_C(2080375704),	// MUL_S_PH
    UINT64_C(1069),	// MUL_S_PH_MMR2
    UINT64_C(59408),	// Mfhi16
    UINT64_C(59410),	// Mflo16
    UINT64_C(25856),	// Move32R16
    UINT64_C(26368),	// MoveR3216
    UINT64_C(68157440),	// NAL
    UINT64_C(2064121886),	// NLOC_B
    UINT64_C(2064318494),	// NLOC_D
    UINT64_C(2064187422),	// NLOC_H
    UINT64_C(2064252958),	// NLOC_W
    UINT64_C(2064384030),	// NLZC_B
    UINT64_C(2064580638),	// NLZC_D
    UINT64_C(2064449566),	// NLZC_H
    UINT64_C(2064515102),	// NLZC_W
    UINT64_C(1275068465),	// NMADD_D32
    UINT64_C(1409286154),	// NMADD_D32_MM
    UINT64_C(1275068465),	// NMADD_D64
    UINT64_C(1275068464),	// NMADD_S
    UINT64_C(1409286146),	// NMADD_S_MM
    UINT64_C(1275068473),	// NMSUB_D32
    UINT64_C(1409286186),	// NMSUB_D32_MM
    UINT64_C(1275068473),	// NMSUB_D64
    UINT64_C(1275068472),	// NMSUB_S
    UINT64_C(1409286178),	// NMSUB_S_MM
    UINT64_C(39),	// NOR
    UINT64_C(39),	// NOR64
    UINT64_C(2046820352),	// NORI_B
    UINT64_C(720),	// NOR_MM
    UINT64_C(720),	// NOR_MMR6
    UINT64_C(2017460254),	// NOR_V
    UINT64_C(17408),	// NOT16_MM
    UINT64_C(17408),	// NOT16_MMR6
    UINT64_C(59421),	// NegRxRy16
    UINT64_C(59407),	// NotRxRy16
    UINT64_C(37),	// OR
    UINT64_C(17600),	// OR16_MM
    UINT64_C(17417),	// OR16_MMR6
    UINT64_C(37),	// OR64
    UINT64_C(2030043136),	// ORI_B
    UINT64_C(1342177280),	// ORI_MMR6
    UINT64_C(656),	// OR_MM
    UINT64_C(656),	// OR_MMR6
    UINT64_C(2015363102),	// OR_V
    UINT64_C(872415232),	// ORi
    UINT64_C(872415232),	// ORi64
    UINT64_C(1342177280),	// ORi_MM
    UINT64_C(59405),	// OrRxRxRy16
    UINT64_C(2080375697),	// PACKRL_PH
    UINT64_C(429),	// PACKRL_PH_MM
    UINT64_C(320),	// PAUSE
    UINT64_C(10240),	// PAUSE_MM
    UINT64_C(10240),	// PAUSE_MMR6
    UINT64_C(2030043156),	// PCKEV_B
    UINT64_C(2036334612),	// PCKEV_D
    UINT64_C(2032140308),	// PCKEV_H
    UINT64_C(2034237460),	// PCKEV_W
    UINT64_C(2038431764),	// PCKOD_B
    UINT64_C(2044723220),	// PCKOD_D
    UINT64_C(2040528916),	// PCKOD_H
    UINT64_C(2042626068),	// PCKOD_W
    UINT64_C(2063859742),	// PCNT_B
    UINT64_C(2064056350),	// PCNT_D
    UINT64_C(2063925278),	// PCNT_H
    UINT64_C(2063990814),	// PCNT_W
    UINT64_C(2080375505),	// PICK_PH
    UINT64_C(557),	// PICK_PH_MM
    UINT64_C(2080374993),	// PICK_QB
    UINT64_C(493),	// PICK_QB_MM
    UINT64_C(1186988076),	// PLL_PS64
    UINT64_C(1186988077),	// PLU_PS64
    UINT64_C(1879048236),	// POP
    UINT64_C(2080375058),	// PRECEQU_PH_QBL
    UINT64_C(2080375186),	// PRECEQU_PH_QBLA
    UINT64_C(29500),	// PRECEQU_PH_QBLA_MM
    UINT64_C(28988),	// PRECEQU_PH_QBL_MM
    UINT64_C(2080375122),	// PRECEQU_PH_QBR
    UINT64_C(2080375250),	// PRECEQU_PH_QBRA
    UINT64_C(37692),	// PRECEQU_PH_QBRA_MM
    UINT64_C(37180),	// PRECEQU_PH_QBR_MM
    UINT64_C(2080375570),	// PRECEQ_W_PHL
    UINT64_C(20796),	// PRECEQ_W_PHL_MM
    UINT64_C(2080375634),	// PRECEQ_W_PHR
    UINT64_C(24892),	// PRECEQ_W_PHR_MM
    UINT64_C(2080376594),	// PRECEU_PH_QBL
    UINT64_C(2080376722),	// PRECEU_PH_QBLA
    UINT64_C(45884),	// PRECEU_PH_QBLA_MM
    UINT64_C(45372),	// PRECEU_PH_QBL_MM
    UINT64_C(2080376658),	// PRECEU_PH_QBR
    UINT64_C(2080376786),	// PRECEU_PH_QBRA
    UINT64_C(54076),	// PRECEU_PH_QBRA_MM
    UINT64_C(53564),	// PRECEU_PH_QBR_MM
    UINT64_C(2080375761),	// PRECRQU_S_QB_PH
    UINT64_C(365),	// PRECRQU_S_QB_PH_MM
    UINT64_C(2080376081),	// PRECRQ_PH_W
    UINT64_C(237),	// PRECRQ_PH_W_MM
    UINT64_C(2080375569),	// PRECRQ_QB_PH
    UINT64_C(173),	// PRECRQ_QB_PH_MM
    UINT64_C(2080376145),	// PRECRQ_RS_PH_W
    UINT64_C(301),	// PRECRQ_RS_PH_W_MM
    UINT64_C(2080375633),	// PRECR_QB_PH
    UINT64_C(109),	// PRECR_QB_PH_MMR2
    UINT64_C(2080376721),	// PRECR_SRA_PH_W
    UINT64_C(973),	// PRECR_SRA_PH_W_MMR2
    UINT64_C(2080376785),	// PRECR_SRA_R_PH_W
    UINT64_C(1997),	// PRECR_SRA_R_PH_W_MMR2
    UINT64_C(3422552064),	// PREF
    UINT64_C(2080374819),	// PREFE
    UINT64_C(1610654720),	// PREFE_MM
    UINT64_C(1409286560),	// PREFX_MM
    UINT64_C(1610620928),	// PREF_MM
    UINT64_C(1610620928),	// PREF_MMR6
    UINT64_C(2080374837),	// PREF_R6
    UINT64_C(2080374897),	// PREPEND
    UINT64_C(597),	// PREPEND_MMR2
    UINT64_C(1186988078),	// PUL_PS64
    UINT64_C(1186988079),	// PUU_PS64
    UINT64_C(2080376080),	// RADDU_W_QB
    UINT64_C(61756),	// RADDU_W_QB_MM
    UINT64_C(2080375992),	// RDDSP
    UINT64_C(1660),	// RDDSP_MM
    UINT64_C(2080374843),	// RDHWR
    UINT64_C(2080374843),	// RDHWR64
    UINT64_C(27452),	// RDHWR_MM
    UINT64_C(448),	// RDHWR_MMR6
    UINT64_C(57724),	// RDPGPR_MMR6
    UINT64_C(1176502293),	// RECIP_D32
    UINT64_C(1409307195),	// RECIP_D32_MM
    UINT64_C(1176502293),	// RECIP_D64
    UINT64_C(1409307195),	// RECIP_D64_MM
    UINT64_C(1174405141),	// RECIP_S
    UINT64_C(1409290811),	// RECIP_S_MM
    UINT64_C(2080375506),	// REPLV_PH
    UINT64_C(828),	// REPLV_PH_MM
    UINT64_C(2080374994),	// REPLV_QB
    UINT64_C(4924),	// REPLV_QB_MM
    UINT64_C(2080375442),	// REPL_PH
    UINT64_C(61),	// REPL_PH_MM
    UINT64_C(2080374930),	// REPL_QB
    UINT64_C(1532),	// REPL_QB_MM
    UINT64_C(1176502298),	// RINT_D
    UINT64_C(1409286688),	// RINT_D_MMR6
    UINT64_C(1174405146),	// RINT_S
    UINT64_C(1409286176),	// RINT_S_MMR6
    UINT64_C(2097154),	// ROTR
    UINT64_C(70),	// ROTRV
    UINT64_C(208),	// ROTRV_MM
    UINT64_C(192),	// ROTR_MM
    UINT64_C(1176502280),	// ROUND_L_D64
    UINT64_C(1409315643),	// ROUND_L_D_MMR6
    UINT64_C(1174405128),	// ROUND_L_S
    UINT64_C(1409299259),	// ROUND_L_S_MMR6
    UINT64_C(1176502284),	// ROUND_W_D32
    UINT64_C(1176502284),	// ROUND_W_D64
    UINT64_C(1409317691),	// ROUND_W_D_MMR6
    UINT64_C(1409317691),	// ROUND_W_MM
    UINT64_C(1174405132),	// ROUND_W_S
    UINT64_C(1409301307),	// ROUND_W_S_MM
    UINT64_C(1409301307),	// ROUND_W_S_MMR6
    UINT64_C(1176502294),	// RSQRT_D32
    UINT64_C(1409303099),	// RSQRT_D32_MM
    UINT64_C(1176502294),	// RSQRT_D64
    UINT64_C(1409303099),	// RSQRT_D64_MM
    UINT64_C(1174405142),	// RSQRT_S
    UINT64_C(1409286715),	// RSQRT_S_MM
    UINT64_C(25728),	// Restore16
    UINT64_C(25728),	// RestoreX16
    UINT64_C(1879048216),	// SAA
    UINT64_C(1879048217),	// SAAD
    UINT64_C(2020605962),	// SAT_S_B
    UINT64_C(2013265930),	// SAT_S_D
    UINT64_C(2019557386),	// SAT_S_H
    UINT64_C(2017460234),	// SAT_S_W
    UINT64_C(2028994570),	// SAT_U_B
    UINT64_C(2021654538),	// SAT_U_D
    UINT64_C(2027945994),	// SAT_U_H
    UINT64_C(2025848842),	// SAT_U_W
    UINT64_C(2684354560),	// SB
    UINT64_C(34816),	// SB16_MM
    UINT64_C(34816),	// SB16_MMR6
    UINT64_C(2684354560),	// SB64
    UINT64_C(2080374812),	// SBE
    UINT64_C(1610655744),	// SBE_MM
    UINT64_C(402653184),	// SB_MM
    UINT64_C(402653184),	// SB_MMR6
    UINT64_C(3758096384),	// SC
    UINT64_C(3758096384),	// SC64
    UINT64_C(2080374822),	// SC64_R6
    UINT64_C(4026531840),	// SCD
    UINT64_C(2080374823),	// SCD_R6
    UINT64_C(2080374814),	// SCE
    UINT64_C(1610656768),	// SCE_MM
    UINT64_C(1610657792),	// SC_MM
    UINT64_C(1610657792),	// SC_MMR6
    UINT64_C(2080374822),	// SC_R6
    UINT64_C(4227858432),	// SD
    UINT64_C(1879048255),	// SDBBP
    UINT64_C(18112),	// SDBBP16_MM
    UINT64_C(17467),	// SDBBP16_MMR6
    UINT64_C(56188),	// SDBBP_MM
    UINT64_C(56188),	// SDBBP_MMR6
    UINT64_C(14),	// SDBBP_R6
    UINT64_C(4093640704),	// SDC1
    UINT64_C(4093640704),	// SDC164
    UINT64_C(3087007744),	// SDC1_D64_MMR6
    UINT64_C(3087007744),	// SDC1_MM_D32
    UINT64_C(3087007744),	// SDC1_MM_D64
    UINT64_C(4160749568),	// SDC2
    UINT64_C(536911872),	// SDC2_MMR6
    UINT64_C(1239416832),	// SDC2_R6
    UINT64_C(4227858432),	// SDC3
    UINT64_C(26),	// SDIV
    UINT64_C(43836),	// SDIV_MM
    UINT64_C(2952790016),	// SDL
    UINT64_C(3019898880),	// SDR
    UINT64_C(1275068425),	// SDXC1
    UINT64_C(1275068425),	// SDXC164
    UINT64_C(2080375840),	// SEB
    UINT64_C(2080375840),	// SEB64
    UINT64_C(11068),	// SEB_MM
    UINT64_C(2080376352),	// SEH
    UINT64_C(2080376352),	// SEH64
    UINT64_C(15164),	// SEH_MM
    UINT64_C(53),	// SELEQZ
    UINT64_C(53),	// SELEQZ64
    UINT64_C(1176502292),	// SELEQZ_D
    UINT64_C(1409286712),	// SELEQZ_D_MMR6
    UINT64_C(320),	// SELEQZ_MMR6
    UINT64_C(1174405140),	// SELEQZ_S
    UINT64_C(1409286200),	// SELEQZ_S_MMR6
    UINT64_C(55),	// SELNEZ
    UINT64_C(55),	// SELNEZ64
    UINT64_C(1176502295),	// SELNEZ_D
    UINT64_C(1409286776),	// SELNEZ_D_MMR6
    UINT64_C(384),	// SELNEZ_MMR6
    UINT64_C(1174405143),	// SELNEZ_S
    UINT64_C(1409286264),	// SELNEZ_S_MMR6
    UINT64_C(1176502288),	// SEL_D
    UINT64_C(1409286840),	// SEL_D_MMR6
    UINT64_C(1174405136),	// SEL_S
    UINT64_C(1409286328),	// SEL_S_MMR6
    UINT64_C(1879048234),	// SEQ
    UINT64_C(1879048238),	// SEQi
    UINT64_C(2751463424),	// SH
    UINT64_C(43008),	// SH16_MM
    UINT64_C(43008),	// SH16_MMR6
    UINT64_C(2751463424),	// SH64
    UINT64_C(2080374813),	// SHE
    UINT64_C(1610656256),	// SHE_MM
    UINT64_C(2013265922),	// SHF_B
    UINT64_C(2030043138),	// SHF_H
    UINT64_C(2046820354),	// SHF_W
    UINT64_C(2080376504),	// SHILO
    UINT64_C(2080376568),	// SHILOV
    UINT64_C(4732),	// SHILOV_MM
    UINT64_C(29),	// SHILO_MM
    UINT64_C(2080375443),	// SHLLV_PH
    UINT64_C(14),	// SHLLV_PH_MM
    UINT64_C(2080374931),	// SHLLV_QB
    UINT64_C(917),	// SHLLV_QB_MM
    UINT64_C(2080375699),	// SHLLV_S_PH
    UINT64_C(1038),	// SHLLV_S_PH_MM
    UINT64_C(2080376211),	// SHLLV_S_W
    UINT64_C(981),	// SHLLV_S_W_MM
    UINT64_C(2080375315),	// SHLL_PH
    UINT64_C(949),	// SHLL_PH_MM
    UINT64_C(2080374803),	// SHLL_QB
    UINT64_C(2172),	// SHLL_QB_MM
    UINT64_C(2080375571),	// SHLL_S_PH
    UINT64_C(2997),	// SHLL_S_PH_MM
    UINT64_C(2080376083),	// SHLL_S_W
    UINT64_C(1013),	// SHLL_S_W_MM
    UINT64_C(2080375507),	// SHRAV_PH
    UINT64_C(397),	// SHRAV_PH_MM
    UINT64_C(2080375187),	// SHRAV_QB
    UINT64_C(461),	// SHRAV_QB_MMR2
    UINT64_C(2080375763),	// SHRAV_R_PH
    UINT64_C(1421),	// SHRAV_R_PH_MM
    UINT64_C(2080375251),	// SHRAV_R_QB
    UINT64_C(1485),	// SHRAV_R_QB_MMR2
    UINT64_C(2080376275),	// SHRAV_R_W
    UINT64_C(725),	// SHRAV_R_W_MM
    UINT64_C(2080375379),	// SHRA_PH
    UINT64_C(821),	// SHRA_PH_MM
    UINT64_C(2080375059),	// SHRA_QB
    UINT64_C(508),	// SHRA_QB_MMR2
    UINT64_C(2080375635),	// SHRA_R_PH
    UINT64_C(1845),	// SHRA_R_PH_MM
    UINT64_C(2080375123),	// SHRA_R_QB
    UINT64_C(4604),	// SHRA_R_QB_MMR2
    UINT64_C(2080376147),	// SHRA_R_W
    UINT64_C(757),	// SHRA_R_W_MM
    UINT64_C(2080376531),	// SHRLV_PH
    UINT64_C(789),	// SHRLV_PH_MMR2
    UINT64_C(2080374995),	// SHRLV_QB
    UINT64_C(853),	// SHRLV_QB_MM
    UINT64_C(2080376403),	// SHRL_PH
    UINT64_C(1020),	// SHRL_PH_MMR2
    UINT64_C(2080374867),	// SHRL_QB
    UINT64_C(6268),	// SHRL_QB_MM
    UINT64_C(939524096),	// SH_MM
    UINT64_C(939524096),	// SH_MMR6
    UINT64_C(68616192),	// SIGRIE
    UINT64_C(63),	// SIGRIE_MMR6
    UINT64_C(2013265945),	// SLDI_B
    UINT64_C(2016935961),	// SLDI_D
    UINT64_C(2015363097),	// SLDI_H
    UINT64_C(2016411673),	// SLDI_W
    UINT64_C(2013265940),	// SLD_B
    UINT64_C(2019557396),	// SLD_D
    UINT64_C(2015363092),	// SLD_H
    UINT64_C(2017460244),	// SLD_W
    UINT64_C(0),	// SLL
    UINT64_C(9216),	// SLL16_MM
    UINT64_C(9216),	// SLL16_MMR6
    UINT64_C(0),	// SLL64_32
    UINT64_C(0),	// SLL64_64
    UINT64_C(2020605961),	// SLLI_B
    UINT64_C(2013265929),	// SLLI_D
    UINT64_C(2019557385),	// SLLI_H
    UINT64_C(2017460233),	// SLLI_W
    UINT64_C(4),	// SLLV
    UINT64_C(16),	// SLLV_MM
    UINT64_C(2013265933),	// SLL_B
    UINT64_C(2019557389),	// SLL_D
    UINT64_C(2015363085),	// SLL_H
    UINT64_C(0),	// SLL_MM
    UINT64_C(0),	// SLL_MMR6
    UINT64_C(2017460237),	// SLL_W
    UINT64_C(42),	// SLT
    UINT64_C(42),	// SLT64
    UINT64_C(848),	// SLT_MM
    UINT64_C(671088640),	// SLTi
    UINT64_C(671088640),	// SLTi64
    UINT64_C(2415919104),	// SLTi_MM
    UINT64_C(738197504),	// SLTiu
    UINT64_C(738197504),	// SLTiu64
    UINT64_C(2952790016),	// SLTiu_MM
    UINT64_C(43),	// SLTu
    UINT64_C(43),	// SLTu64
    UINT64_C(912),	// SLTu_MM
    UINT64_C(1879048235),	// SNE
    UINT64_C(1879048239),	// SNEi
    UINT64_C(2017460249),	// SPLATI_B
    UINT64_C(2021130265),	// SPLATI_D
    UINT64_C(2019557401),	// SPLATI_H
    UINT64_C(2020605977),	// SPLATI_W
    UINT64_C(2021654548),	// SPLAT_B
    UINT64_C(2027946004),	// SPLAT_D
    UINT64_C(2023751700),	// SPLAT_H
    UINT64_C(2025848852),	// SPLAT_W
    UINT64_C(3),	// SRA
    UINT64_C(2028994569),	// SRAI_B
    UINT64_C(2021654537),	// SRAI_D
    UINT64_C(2027945993),	// SRAI_H
    UINT64_C(2025848841),	// SRAI_W
    UINT64_C(2037383178),	// SRARI_B
    UINT64_C(2030043146),	// SRARI_D
    UINT64_C(2036334602),	// SRARI_H
    UINT64_C(2034237450),	// SRARI_W
    UINT64_C(2021654549),	// SRAR_B
    UINT64_C(2027946005),	// SRAR_D
    UINT64_C(2023751701),	// SRAR_H
    UINT64_C(2025848853),	// SRAR_W
    UINT64_C(7),	// SRAV
    UINT64_C(144),	// SRAV_MM
    UINT64_C(2021654541),	// SRA_B
    UINT64_C(2027945997),	// SRA_D
    UINT64_C(2023751693),	// SRA_H
    UINT64_C(128),	// SRA_MM
    UINT64_C(2025848845),	// SRA_W
    UINT64_C(2),	// SRL
    UINT64_C(9217),	// SRL16_MM
    UINT64_C(9217),	// SRL16_MMR6
    UINT64_C(2037383177),	// SRLI_B
    UINT64_C(2030043145),	// SRLI_D
    UINT64_C(2036334601),	// SRLI_H
    UINT64_C(2034237449),	// SRLI_W
    UINT64_C(2045771786),	// SRLRI_B
    UINT64_C(2038431754),	// SRLRI_D
    UINT64_C(2044723210),	// SRLRI_H
    UINT64_C(2042626058),	// SRLRI_W
    UINT64_C(2030043157),	// SRLR_B
    UINT64_C(2036334613),	// SRLR_D
    UINT64_C(2032140309),	// SRLR_H
    UINT64_C(2034237461),	// SRLR_W
    UINT64_C(6),	// SRLV
    UINT64_C(80),	// SRLV_MM
    UINT64_C(2030043149),	// SRL_B
    UINT64_C(2036334605),	// SRL_D
    UINT64_C(2032140301),	// SRL_H
    UINT64_C(64),	// SRL_MM
    UINT64_C(2034237453),	// SRL_W
    UINT64_C(64),	// SSNOP
    UINT64_C(2048),	// SSNOP_MM
    UINT64_C(2048),	// SSNOP_MMR6
    UINT64_C(2013265956),	// ST_B
    UINT64_C(2013265959),	// ST_D
    UINT64_C(2013265957),	// ST_H
    UINT64_C(2013265958),	// ST_W
    UINT64_C(34),	// SUB
    UINT64_C(2080375384),	// SUBQH_PH
    UINT64_C(589),	// SUBQH_PH_MMR2
    UINT64_C(2080375512),	// SUBQH_R_PH
    UINT64_C(1613),	// SUBQH_R_PH_MMR2
    UINT64_C(2080376024),	// SUBQH_R_W
    UINT64_C(1677),	// SUBQH_R_W_MMR2
    UINT64_C(2080375896),	// SUBQH_W
    UINT64_C(653),	// SUBQH_W_MMR2
    UINT64_C(2080375504),	// SUBQ_PH
    UINT64_C(525),	// SUBQ_PH_MM
    UINT64_C(2080375760),	// SUBQ_S_PH
    UINT64_C(1549),	// SUBQ_S_PH_MM
    UINT64_C(2080376272),	// SUBQ_S_W
    UINT64_C(837),	// SUBQ_S_W_MM
    UINT64_C(2030043153),	// SUBSUS_U_B
    UINT64_C(2036334609),	// SUBSUS_U_D
    UINT64_C(2032140305),	// SUBSUS_U_H
    UINT64_C(2034237457),	// SUBSUS_U_W
    UINT64_C(2038431761),	// SUBSUU_S_B
    UINT64_C(2044723217),	// SUBSUU_S_D
    UINT64_C(2040528913),	// SUBSUU_S_H
    UINT64_C(2042626065),	// SUBSUU_S_W
    UINT64_C(2013265937),	// SUBS_S_B
    UINT64_C(2019557393),	// SUBS_S_D
    UINT64_C(2015363089),	// SUBS_S_H
    UINT64_C(2017460241),	// SUBS_S_W
    UINT64_C(2021654545),	// SUBS_U_B
    UINT64_C(2027946001),	// SUBS_U_D
    UINT64_C(2023751697),	// SUBS_U_H
    UINT64_C(2025848849),	// SUBS_U_W
    UINT64_C(1025),	// SUBU16_MM
    UINT64_C(1025),	// SUBU16_MMR6
    UINT64_C(2080374872),	// SUBUH_QB
    UINT64_C(845),	// SUBUH_QB_MMR2
    UINT64_C(2080375000),	// SUBUH_R_QB
    UINT64_C(1869),	// SUBUH_R_QB_MMR2
    UINT64_C(464),	// SUBU_MMR6
    UINT64_C(2080375376),	// SUBU_PH
    UINT64_C(781),	// SUBU_PH_MMR2
    UINT64_C(2080374864),	// SUBU_QB
    UINT64_C(717),	// SUBU_QB_MM
    UINT64_C(2080375632),	// SUBU_S_PH
    UINT64_C(1805),	// SUBU_S_PH_MMR2
    UINT64_C(2080375120),	// SUBU_S_QB
    UINT64_C(1741),	// SUBU_S_QB_MM
    UINT64_C(2021654534),	// SUBVI_B
    UINT64_C(2027945990),	// SUBVI_D
    UINT64_C(2023751686),	// SUBVI_H
    UINT64_C(2025848838),	// SUBVI_W
    UINT64_C(2021654542),	// SUBV_B
    UINT64_C(2027945998),	// SUBV_D
    UINT64_C(2023751694),	// SUBV_H
    UINT64_C(2025848846),	// SUBV_W
    UINT64_C(400),	// SUB_MM
    UINT64_C(400),	// SUB_MMR6
    UINT64_C(35),	// SUBu
    UINT64_C(464),	// SUBu_MM
    UINT64_C(1275068429),	// SUXC1
    UINT64_C(1275068429),	// SUXC164
    UINT64_C(1409286536),	// SUXC1_MM
    UINT64_C(2885681152),	// SW
    UINT64_C(59392),	// SW16_MM
    UINT64_C(59392),	// SW16_MMR6
    UINT64_C(2885681152),	// SW64
    UINT64_C(3825205248),	// SWC1
    UINT64_C(2550136832),	// SWC1_MM
    UINT64_C(3892314112),	// SWC2
    UINT64_C(536903680),	// SWC2_MMR6
    UINT64_C(1231028224),	// SWC2_R6
    UINT64_C(3959422976),	// SWC3
    UINT64_C(2885681152),	// SWDSP
    UINT64_C(4160749568),	// SWDSP_MM
    UINT64_C(2080374815),	// SWE
    UINT64_C(1610657280),	// SWE_MM
    UINT64_C(2818572288),	// SWL
    UINT64_C(2818572288),	// SWL64
    UINT64_C(2080374817),	// SWLE
    UINT64_C(1610653696),	// SWLE_MM
    UINT64_C(1610645504),	// SWL_MM
    UINT64_C(17728),	// SWM16_MM
    UINT64_C(17418),	// SWM16_MMR6
    UINT64_C(536924160),	// SWM32_MM
    UINT64_C(536907776),	// SWP_MM
    UINT64_C(3087007744),	// SWR
    UINT64_C(3087007744),	// SWR64
    UINT64_C(2080374818),	// SWRE
    UINT64_C(1610654208),	// SWRE_MM
    UINT64_C(1610649600),	// SWR_MM
    UINT64_C(51200),	// SWSP_MM
    UINT64_C(51200),	// SWSP_MMR6
    UINT64_C(1275068424),	// SWXC1
    UINT64_C(1409286280),	// SWXC1_MM
    UINT64_C(4160749568),	// SW_MM
    UINT64_C(4160749568),	// SW_MMR6
    UINT64_C(15),	// SYNC
    UINT64_C(69140480),	// SYNCI
    UINT64_C(1107296256),	// SYNCI_MM
    UINT64_C(1098907648),	// SYNCI_MMR6
    UINT64_C(27516),	// SYNC_MM
    UINT64_C(27516),	// SYNC_MMR6
    UINT64_C(12),	// SYSCALL
    UINT64_C(35708),	// SYSCALL_MM
    UINT64_C(25728),	// Save16
    UINT64_C(25728),	// SaveX16
    UINT64_C(4026580992),	// SbRxRyOffMemX16
    UINT64_C(59537),	// SebRx16
    UINT64_C(59569),	// SehRx16
    UINT64_C(4026583040),	// ShRxRyOffMemX16
    UINT64_C(4026544128),	// SllX16
    UINT64_C(59396),	// SllvRxRy16
    UINT64_C(59394),	// SltRxRy16
    UINT64_C(20480),	// SltiRxImm16
    UINT64_C(4026552320),	// SltiRxImmX16
    UINT64_C(22528),	// SltiuRxImm16
    UINT64_C(4026554368),	// SltiuRxImmX16
    UINT64_C(59395),	// SltuRxRy16
    UINT64_C(4026544131),	// SraX16
    UINT64_C(59399),	// SravRxRy16
    UINT64_C(4026544130),	// SrlX16
    UINT64_C(59398),	// SrlvRxRy16
    UINT64_C(57347),	// SubuRxRyRz16
    UINT64_C(4026587136),	// SwRxRyOffMemX16
    UINT64_C(4026585088),	// SwRxSpImmX16
    UINT64_C(52),	// TEQ
    UINT64_C(67895296),	// TEQI
    UINT64_C(1103101952),	// TEQI_MM
    UINT64_C(60),	// TEQ_MM
    UINT64_C(48),	// TGE
    UINT64_C(67633152),	// TGEI
    UINT64_C(67698688),	// TGEIU
    UINT64_C(1096810496),	// TGEIU_MM
    UINT64_C(1092616192),	// TGEI_MM
    UINT64_C(49),	// TGEU
    UINT64_C(1084),	// TGEU_MM
    UINT64_C(572),	// TGE_MM
    UINT64_C(1107296267),	// TLBGINV
    UINT64_C(1107296268),	// TLBGINVF
    UINT64_C(20860),	// TLBGINVF_MM
    UINT64_C(16764),	// TLBGINV_MM
    UINT64_C(1107296272),	// TLBGP
    UINT64_C(380),	// TLBGP_MM
    UINT64_C(1107296265),	// TLBGR
    UINT64_C(4476),	// TLBGR_MM
    UINT64_C(1107296266),	// TLBGWI
    UINT64_C(8572),	// TLBGWI_MM
    UINT64_C(1107296270),	// TLBGWR
    UINT64_C(12668),	// TLBGWR_MM
    UINT64_C(1107296259),	// TLBINV
    UINT64_C(1107296260),	// TLBINVF
    UINT64_C(21372),	// TLBINVF_MMR6
    UINT64_C(17276),	// TLBINV_MMR6
    UINT64_C(1107296264),	// TLBP
    UINT64_C(892),	// TLBP_MM
    UINT64_C(1107296257),	// TLBR
    UINT64_C(4988),	// TLBR_MM
    UINT64_C(1107296258),	// TLBWI
    UINT64_C(9084),	// TLBWI_MM
    UINT64_C(1107296262),	// TLBWR
    UINT64_C(13180),	// TLBWR_MM
    UINT64_C(50),	// TLT
    UINT64_C(67764224),	// TLTI
    UINT64_C(1094713344),	// TLTIU_MM
    UINT64_C(1090519040),	// TLTI_MM
    UINT64_C(51),	// TLTU
    UINT64_C(2620),	// TLTU_MM
    UINT64_C(2108),	// TLT_MM
    UINT64_C(54),	// TNE
    UINT64_C(68026368),	// TNEI
    UINT64_C(1098907648),	// TNEI_MM
    UINT64_C(3132),	// TNE_MM
    UINT64_C(1176502281),	// TRUNC_L_D64
    UINT64_C(1409311547),	// TRUNC_L_D_MMR6
    UINT64_C(1174405129),	// TRUNC_L_S
    UINT64_C(1409295163),	// TRUNC_L_S_MMR6
    UINT64_C(1176502285),	// TRUNC_W_D32
    UINT64_C(1176502285),	// TRUNC_W_D64
    UINT64_C(1409313595),	// TRUNC_W_D_MMR6
    UINT64_C(1409313595),	// TRUNC_W_MM
    UINT64_C(1174405133),	// TRUNC_W_S
    UINT64_C(1409297211),	// TRUNC_W_S_MM
    UINT64_C(1409297211),	// TRUNC_W_S_MMR6
    UINT64_C(67829760),	// TTLTIU
    UINT64_C(27),	// UDIV
    UINT64_C(47932),	// UDIV_MM
    UINT64_C(1879048209),	// V3MULU
    UINT64_C(1879048208),	// VMM0
    UINT64_C(1879048207),	// VMULU
    UINT64_C(2013265941),	// VSHF_B
    UINT64_C(2019557397),	// VSHF_D
    UINT64_C(2015363093),	// VSHF_H
    UINT64_C(2017460245),	// VSHF_W
    UINT64_C(1107296288),	// WAIT
    UINT64_C(37756),	// WAIT_MM
    UINT64_C(37756),	// WAIT_MMR6
    UINT64_C(2080376056),	// WRDSP
    UINT64_C(5756),	// WRDSP_MM
    UINT64_C(61820),	// WRPGPR_MMR6
    UINT64_C(2080374944),	// WSBH
    UINT64_C(31548),	// WSBH_MM
    UINT64_C(31548),	// WSBH_MMR6
    UINT64_C(38),	// XOR
    UINT64_C(17472),	// XOR16_MM
    UINT64_C(17416),	// XOR16_MMR6
    UINT64_C(38),	// XOR64
    UINT64_C(2063597568),	// XORI_B
    UINT64_C(1879048192),	// XORI_MMR6
    UINT64_C(784),	// XOR_MM
    UINT64_C(784),	// XOR_MMR6
    UINT64_C(2019557406),	// XOR_V
    UINT64_C(939524096),	// XORi
    UINT64_C(939524096),	// XORi64
    UINT64_C(1879048192),	// XORi_MM
    UINT64_C(59406),	// XorRxRxRy16
    UINT64_C(2080374793),	// YIELD
  };
  constexpr unsigned FirstSupportedOpcode = 780;

  const unsigned opcode = MI.getOpcode();
  if (opcode < FirstSupportedOpcode)
    reportUnsupportedInst(MI);
  unsigned TableIndex = opcode - FirstSupportedOpcode;
  uint64_t Value = InstBits[TableIndex];
  uint64_t op = 0;
  (void)op;  // suppress warning
  switch (opcode) {
    case Mips::Break16:
    case Mips::DERET:
    case Mips::DERET_MM:
    case Mips::DERET_MMR6:
    case Mips::EHB:
    case Mips::EHB_MM:
    case Mips::EHB_MMR6:
    case Mips::ERET:
    case Mips::ERETNC:
    case Mips::ERETNC_MMR6:
    case Mips::ERET_MM:
    case Mips::ERET_MMR6:
    case Mips::JrRa16:
    case Mips::JrcRa16:
    case Mips::NAL:
    case Mips::PAUSE:
    case Mips::PAUSE_MM:
    case Mips::PAUSE_MMR6:
    case Mips::Restore16:
    case Mips::RestoreX16:
    case Mips::SSNOP:
    case Mips::SSNOP_MM:
    case Mips::SSNOP_MMR6:
    case Mips::Save16:
    case Mips::SaveX16:
    case Mips::TLBGINV:
    case Mips::TLBGINVF:
    case Mips::TLBGINVF_MM:
    case Mips::TLBGINV_MM:
    case Mips::TLBGP:
    case Mips::TLBGP_MM:
    case Mips::TLBGR:
    case Mips::TLBGR_MM:
    case Mips::TLBGWI:
    case Mips::TLBGWI_MM:
    case Mips::TLBGWR:
    case Mips::TLBGWR_MM:
    case Mips::TLBINV:
    case Mips::TLBINVF:
    case Mips::TLBINVF_MMR6:
    case Mips::TLBINV_MMR6:
    case Mips::TLBP:
    case Mips::TLBP_MM:
    case Mips::TLBR:
    case Mips::TLBR_MM:
    case Mips::TLBWI:
    case Mips::TLBWI_MM:
    case Mips::TLBWR:
    case Mips::TLBWR_MM:
    case Mips::WAIT: {
      break;
    }
    case Mips::MTHLIP:
    case Mips::SHILOV: {
      // op: ac
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3) << 11;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::DPAQX_SA_W_PH:
    case Mips::DPAQX_S_W_PH:
    case Mips::DPAQ_SA_L_W:
    case Mips::DPAQ_S_W_PH:
    case Mips::DPAU_H_QBL:
    case Mips::DPAU_H_QBR:
    case Mips::DPAX_W_PH:
    case Mips::DPA_W_PH:
    case Mips::DPSQX_SA_W_PH:
    case Mips::DPSQX_S_W_PH:
    case Mips::DPSQ_SA_L_W:
    case Mips::DPSQ_S_W_PH:
    case Mips::DPSU_H_QBL:
    case Mips::DPSU_H_QBR:
    case Mips::DPSX_W_PH:
    case Mips::DPS_W_PH:
    case Mips::MADDU_DSP:
    case Mips::MADD_DSP:
    case Mips::MAQ_SA_W_PHL:
    case Mips::MAQ_SA_W_PHR:
    case Mips::MAQ_S_W_PHL:
    case Mips::MAQ_S_W_PHR:
    case Mips::MSUBU_DSP:
    case Mips::MSUB_DSP:
    case Mips::MULSAQ_S_W_PH:
    case Mips::MULSA_W_PH:
    case Mips::MULTU_DSP:
    case Mips::MULT_DSP: {
      // op: ac
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3) << 11;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::SHILO: {
      // op: ac
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3) << 11;
      // op: shift
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3f) << 20;
      break;
    }
    case Mips::CACHEE:
    case Mips::CACHE_R6:
    case Mips::PREFE:
    case Mips::PREF_R6: {
      // op: addr
      op = getMemEncoding(MI, 0, Fixups, STI);
      Value |= (op & 0x1f0000) << 5;
      Value |= (op & 0x1ff) << 7;
      // op: hint
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::SYNCI: {
      // op: addr
      op = getMemEncoding(MI, 0, Fixups, STI);
      Value |= (op & 0x1f0000) << 5;
      Value |= (op & 0xffff);
      break;
    }
    case Mips::CACHE:
    case Mips::PREF: {
      // op: addr
      op = getMemEncoding(MI, 0, Fixups, STI);
      Value |= (op & 0x1f0000) << 5;
      Value |= (op & 0xffff);
      // op: hint
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::LBE:
    case Mips::LBuE:
    case Mips::LHE:
    case Mips::LHuE:
    case Mips::LLE:
    case Mips::LWE:
    case Mips::LWLE:
    case Mips::LWRE:
    case Mips::SBE:
    case Mips::SHE:
    case Mips::SWE:
    case Mips::SWLE:
    case Mips::SWRE: {
      // op: addr
      op = getMemEncoding(MI, 1, Fixups, STI);
      Value |= (op & 0x1f0000) << 5;
      Value |= (op & 0x1ff) << 7;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::LD_B:
    case Mips::ST_B: {
      // op: addr
      op = getMemEncoding(MI, 1, Fixups, STI);
      Value |= (op & 0x3ff) << 16;
      Value |= (op & 0x1f0000) >> 5;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::SCE: {
      // op: addr
      op = getMemEncoding(MI, 2, Fixups, STI);
      Value |= (op & 0x1f0000) << 5;
      Value |= (op & 0x1ff) << 7;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::LD_H:
    case Mips::ST_H: {
      // op: addr
      op = getMemEncoding<1>(MI, 1, Fixups, STI);
      Value |= (op & 0x3ff) << 16;
      Value |= (op & 0x1f0000) >> 5;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::LD_W:
    case Mips::ST_W: {
      // op: addr
      op = getMemEncoding<2>(MI, 1, Fixups, STI);
      Value |= (op & 0x3ff) << 16;
      Value |= (op & 0x1f0000) >> 5;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::LD_D:
    case Mips::ST_D: {
      // op: addr
      op = getMemEncoding<3>(MI, 1, Fixups, STI);
      Value |= (op & 0x3ff) << 16;
      Value |= (op & 0x1f0000) >> 5;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::CACHE_MM:
    case Mips::CACHE_MMR6:
    case Mips::PREF_MM:
    case Mips::PREF_MMR6: {
      // op: addr
      op = getMemEncodingMMImm12(MI, 0, Fixups, STI);
      Value |= (op & 0x1f0000);
      Value |= (op & 0xfff);
      // op: hint
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::SYNCI_MM:
    case Mips::SYNCI_MMR6: {
      // op: addr
      op = getMemEncodingMMImm16(MI, 0, Fixups, STI);
      Value |= (op & 0x1fffff);
      break;
    }
    case Mips::LBU_MMR6:
    case Mips::LB_MMR6: {
      // op: addr
      op = getMemEncodingMMImm16(MI, 1, Fixups, STI);
      Value |= (op & 0x1fffff);
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::CACHEE_MM:
    case Mips::PREFE_MM: {
      // op: addr
      op = getMemEncodingMMImm9(MI, 0, Fixups, STI);
      Value |= (op & 0x1f0000);
      Value |= (op & 0x1ff);
      // op: hint
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::HYPCALL: {
      // op: code_
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3ff) << 11;
      break;
    }
    case Mips::HYPCALL_MM:
    case Mips::SDBBP_MM:
    case Mips::SDBBP_MMR6:
    case Mips::SYSCALL_MM:
    case Mips::WAIT_MM:
    case Mips::WAIT_MMR6: {
      // op: code_
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3ff) << 16;
      break;
    }
    case Mips::BREAK16_MMR6:
    case Mips::SDBBP16_MMR6: {
      // op: code_
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf) << 6;
      break;
    }
    case Mips::BREAK16_MM:
    case Mips::SDBBP16_MM: {
      // op: code_
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      break;
    }
    case Mips::SIGRIE_MMR6: {
      // op: code_
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xffff) << 6;
      break;
    }
    case Mips::SIGRIE: {
      // op: code_
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::SDBBP:
    case Mips::SDBBP_R6:
    case Mips::SYSCALL: {
      // op: code_
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xfffff) << 6;
      break;
    }
    case Mips::BREAK:
    case Mips::BREAK_MM:
    case Mips::BREAK_MMR6: {
      // op: code_1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3ff) << 16;
      // op: code_2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3ff) << 6;
      break;
    }
    case Mips::BC2EQZ:
    case Mips::BC2NEZ: {
      // op: ct
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: offset
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::BC1F:
    case Mips::BC1FL:
    case Mips::BC1T:
    case Mips::BC1TL: {
      // op: fcc
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 18;
      // op: offset
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::BC1F_MM:
    case Mips::BC1T_MM: {
      // op: fcc
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 18;
      // op: offset
      op = getBranchTargetOpValueMM(MI, 1, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::LUXC1_MM:
    case Mips::LWXC1_MM: {
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: base
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::MOVN_I_D32_MM:
    case Mips::MOVN_I_S_MM:
    case Mips::MOVZ_I_D32_MM:
    case Mips::MOVZ_I_S_MM: {
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::CEIL_W_MM:
    case Mips::CEIL_W_S_MM:
    case Mips::CVT_D32_S_MM:
    case Mips::CVT_D32_W_MM:
    case Mips::CVT_D64_S_MM:
    case Mips::CVT_D64_W_MM:
    case Mips::CVT_L_D64_MM:
    case Mips::CVT_L_S_MM:
    case Mips::CVT_S_D32_MM:
    case Mips::CVT_S_D64_MM:
    case Mips::CVT_S_W_MM:
    case Mips::CVT_W_D32_MM:
    case Mips::CVT_W_D64_MM:
    case Mips::CVT_W_S_MM:
    case Mips::FABS_D32_MM:
    case Mips::FABS_D64_MM:
    case Mips::FABS_S_MM:
    case Mips::FLOOR_W_MM:
    case Mips::FLOOR_W_S_MM:
    case Mips::FMOV_D32_MM:
    case Mips::FMOV_D64_MM:
    case Mips::FMOV_S_MM:
    case Mips::FNEG_D32_MM:
    case Mips::FNEG_D64_MM:
    case Mips::FNEG_S_MM:
    case Mips::FSQRT_D32_MM:
    case Mips::FSQRT_D64_MM:
    case Mips::FSQRT_S_MM:
    case Mips::RECIP_D32_MM:
    case Mips::RECIP_D64_MM:
    case Mips::RECIP_S_MM:
    case Mips::ROUND_W_MM:
    case Mips::ROUND_W_S_MM:
    case Mips::RSQRT_D32_MM:
    case Mips::RSQRT_D64_MM:
    case Mips::RSQRT_S_MM:
    case Mips::TRUNC_W_MM:
    case Mips::TRUNC_W_S_MM: {
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::MOVF_D32_MM:
    case Mips::MOVF_S_MM:
    case Mips::MOVT_D32_MM:
    case Mips::MOVT_S_MM: {
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: fcc
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 13;
      break;
    }
    case Mips::LDXC1:
    case Mips::LDXC164:
    case Mips::LUXC1:
    case Mips::LUXC164:
    case Mips::LWXC1: {
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      // op: base
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::MADD_D32:
    case Mips::MADD_D64:
    case Mips::MADD_S:
    case Mips::MSUB_D32:
    case Mips::MSUB_D64:
    case Mips::MSUB_S:
    case Mips::NMADD_D32:
    case Mips::NMADD_D64:
    case Mips::NMADD_S:
    case Mips::NMSUB_D32:
    case Mips::NMSUB_D64:
    case Mips::NMSUB_S: {
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      // op: fr
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: ft
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::CEIL_L_D64:
    case Mips::CEIL_L_S:
    case Mips::CEIL_W_D32:
    case Mips::CEIL_W_D64:
    case Mips::CEIL_W_S:
    case Mips::CVT_D32_S:
    case Mips::CVT_D32_W:
    case Mips::CVT_D64_L:
    case Mips::CVT_D64_S:
    case Mips::CVT_D64_W:
    case Mips::CVT_L_D64:
    case Mips::CVT_L_S:
    case Mips::CVT_PS_PW64:
    case Mips::CVT_PW_PS64:
    case Mips::CVT_S_D32:
    case Mips::CVT_S_D64:
    case Mips::CVT_S_L:
    case Mips::CVT_S_PL64:
    case Mips::CVT_S_PU64:
    case Mips::CVT_S_W:
    case Mips::CVT_W_D32:
    case Mips::CVT_W_D64:
    case Mips::CVT_W_S:
    case Mips::FABS_D32:
    case Mips::FABS_D64:
    case Mips::FABS_S:
    case Mips::FLOOR_L_D64:
    case Mips::FLOOR_L_S:
    case Mips::FLOOR_W_D32:
    case Mips::FLOOR_W_D64:
    case Mips::FLOOR_W_S:
    case Mips::FMOV_D32:
    case Mips::FMOV_D64:
    case Mips::FMOV_S:
    case Mips::FNEG_D32:
    case Mips::FNEG_D64:
    case Mips::FNEG_S:
    case Mips::FSQRT_D32:
    case Mips::FSQRT_D64:
    case Mips::FSQRT_S:
    case Mips::RECIP_D32:
    case Mips::RECIP_D64:
    case Mips::RECIP_S:
    case Mips::ROUND_L_D64:
    case Mips::ROUND_L_S:
    case Mips::ROUND_W_D32:
    case Mips::ROUND_W_D64:
    case Mips::ROUND_W_S:
    case Mips::RSQRT_D32:
    case Mips::RSQRT_D64:
    case Mips::RSQRT_S:
    case Mips::TRUNC_L_D64:
    case Mips::TRUNC_L_S:
    case Mips::TRUNC_W_D32:
    case Mips::TRUNC_W_D64:
    case Mips::TRUNC_W_S: {
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::MOVF_D32:
    case Mips::MOVF_D64:
    case Mips::MOVF_S:
    case Mips::MOVT_D32:
    case Mips::MOVT_D64:
    case Mips::MOVT_S: {
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: fcc
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 18;
      break;
    }
    case Mips::ADDR_PS64:
    case Mips::CMP_EQ_D:
    case Mips::CMP_EQ_S:
    case Mips::CMP_F_D:
    case Mips::CMP_F_S:
    case Mips::CMP_LE_D:
    case Mips::CMP_LE_S:
    case Mips::CMP_LT_D:
    case Mips::CMP_LT_S:
    case Mips::CMP_SAF_D:
    case Mips::CMP_SAF_S:
    case Mips::CMP_SEQ_D:
    case Mips::CMP_SEQ_S:
    case Mips::CMP_SLE_D:
    case Mips::CMP_SLE_S:
    case Mips::CMP_SLT_D:
    case Mips::CMP_SLT_S:
    case Mips::CMP_SUEQ_D:
    case Mips::CMP_SUEQ_S:
    case Mips::CMP_SULE_D:
    case Mips::CMP_SULE_S:
    case Mips::CMP_SULT_D:
    case Mips::CMP_SULT_S:
    case Mips::CMP_SUN_D:
    case Mips::CMP_SUN_S:
    case Mips::CMP_UEQ_D:
    case Mips::CMP_UEQ_S:
    case Mips::CMP_ULE_D:
    case Mips::CMP_ULE_S:
    case Mips::CMP_ULT_D:
    case Mips::CMP_ULT_S:
    case Mips::CMP_UN_D:
    case Mips::CMP_UN_S:
    case Mips::CVT_PS_S64:
    case Mips::FADD_D32:
    case Mips::FADD_D64:
    case Mips::FADD_PS64:
    case Mips::FADD_S:
    case Mips::FDIV_D32:
    case Mips::FDIV_D64:
    case Mips::FDIV_S:
    case Mips::FMUL_D32:
    case Mips::FMUL_D64:
    case Mips::FMUL_PS64:
    case Mips::FMUL_S:
    case Mips::FSUB_D32:
    case Mips::FSUB_D64:
    case Mips::FSUB_PS64:
    case Mips::FSUB_S:
    case Mips::MULR_PS64:
    case Mips::PLL_PS64:
    case Mips::PLU_PS64:
    case Mips::PUL_PS64:
    case Mips::PUU_PS64: {
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: ft
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::MOVN_I64_D64:
    case Mips::MOVN_I64_S:
    case Mips::MOVN_I_D32:
    case Mips::MOVN_I_D64:
    case Mips::MOVN_I_S:
    case Mips::MOVZ_I64_D64:
    case Mips::MOVZ_I64_S:
    case Mips::MOVZ_I_D32:
    case Mips::MOVZ_I_D64:
    case Mips::MOVZ_I_S: {
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::SUXC1_MM:
    case Mips::SWXC1_MM: {
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: base
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::SDXC1:
    case Mips::SDXC164:
    case Mips::SUXC1:
    case Mips::SUXC164:
    case Mips::SWXC1: {
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: base
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::FCMP_D32:
    case Mips::FCMP_D64:
    case Mips::FCMP_S32: {
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: ft
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: cond
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf);
      break;
    }
    case Mips::FCMP_D32_MM:
    case Mips::FCMP_S32_MM: {
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: ft
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: cond
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 6;
      break;
    }
    case Mips::CLASS_D:
    case Mips::CLASS_S:
    case Mips::RINT_D:
    case Mips::RINT_S: {
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::C_EQ_D32:
    case Mips::C_EQ_D64:
    case Mips::C_EQ_S:
    case Mips::C_F_D32:
    case Mips::C_F_D64:
    case Mips::C_F_S:
    case Mips::C_LE_D32:
    case Mips::C_LE_D64:
    case Mips::C_LE_S:
    case Mips::C_LT_D32:
    case Mips::C_LT_D64:
    case Mips::C_LT_S:
    case Mips::C_NGE_D32:
    case Mips::C_NGE_D64:
    case Mips::C_NGE_S:
    case Mips::C_NGLE_D32:
    case Mips::C_NGLE_D64:
    case Mips::C_NGLE_S:
    case Mips::C_NGL_D32:
    case Mips::C_NGL_D64:
    case Mips::C_NGL_S:
    case Mips::C_NGT_D32:
    case Mips::C_NGT_D64:
    case Mips::C_NGT_S:
    case Mips::C_OLE_D32:
    case Mips::C_OLE_D64:
    case Mips::C_OLE_S:
    case Mips::C_OLT_D32:
    case Mips::C_OLT_D64:
    case Mips::C_OLT_S:
    case Mips::C_SEQ_D32:
    case Mips::C_SEQ_D64:
    case Mips::C_SEQ_S:
    case Mips::C_SF_D32:
    case Mips::C_SF_D64:
    case Mips::C_SF_S:
    case Mips::C_UEQ_D32:
    case Mips::C_UEQ_D64:
    case Mips::C_UEQ_S:
    case Mips::C_ULE_D32:
    case Mips::C_ULE_D64:
    case Mips::C_ULE_S:
    case Mips::C_ULT_D32:
    case Mips::C_ULT_D64:
    case Mips::C_ULT_S:
    case Mips::C_UN_D32:
    case Mips::C_UN_D64:
    case Mips::C_UN_S: {
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: ft
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: fcc
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 8;
      break;
    }
    case Mips::C_EQ_D32_MM:
    case Mips::C_EQ_D64_MM:
    case Mips::C_EQ_S_MM:
    case Mips::C_F_D32_MM:
    case Mips::C_F_D64_MM:
    case Mips::C_F_S_MM:
    case Mips::C_LE_D32_MM:
    case Mips::C_LE_D64_MM:
    case Mips::C_LE_S_MM:
    case Mips::C_LT_D32_MM:
    case Mips::C_LT_D64_MM:
    case Mips::C_LT_S_MM:
    case Mips::C_NGE_D32_MM:
    case Mips::C_NGE_D64_MM:
    case Mips::C_NGE_S_MM:
    case Mips::C_NGLE_D32_MM:
    case Mips::C_NGLE_D64_MM:
    case Mips::C_NGLE_S_MM:
    case Mips::C_NGL_D32_MM:
    case Mips::C_NGL_D64_MM:
    case Mips::C_NGL_S_MM:
    case Mips::C_NGT_D32_MM:
    case Mips::C_NGT_D64_MM:
    case Mips::C_NGT_S_MM:
    case Mips::C_OLE_D32_MM:
    case Mips::C_OLE_D64_MM:
    case Mips::C_OLE_S_MM:
    case Mips::C_OLT_D32_MM:
    case Mips::C_OLT_D64_MM:
    case Mips::C_OLT_S_MM:
    case Mips::C_SEQ_D32_MM:
    case Mips::C_SEQ_D64_MM:
    case Mips::C_SEQ_S_MM:
    case Mips::C_SF_D32_MM:
    case Mips::C_SF_D64_MM:
    case Mips::C_SF_S_MM:
    case Mips::C_UEQ_D32_MM:
    case Mips::C_UEQ_D64_MM:
    case Mips::C_UEQ_S_MM:
    case Mips::C_ULE_D32_MM:
    case Mips::C_ULE_D64_MM:
    case Mips::C_ULE_S_MM:
    case Mips::C_ULT_D32_MM:
    case Mips::C_ULT_D64_MM:
    case Mips::C_ULT_S_MM:
    case Mips::C_UN_D32_MM:
    case Mips::C_UN_D64_MM:
    case Mips::C_UN_S_MM: {
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: ft
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: fcc
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 13;
      break;
    }
    case Mips::CLASS_D_MMR6:
    case Mips::CLASS_S_MMR6:
    case Mips::RINT_D_MMR6:
    case Mips::RINT_S_MMR6: {
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::BC1EQZ:
    case Mips::BC1NEZ: {
      // op: ft
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: offset
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::LDC1_D64_MMR6:
    case Mips::SDC1_D64_MMR6: {
      // op: ft
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: addr
      op = getMemEncodingMMImm16(MI, 1, Fixups, STI);
      Value |= (op & 0x1fffff);
      break;
    }
    case Mips::CEIL_L_D_MMR6:
    case Mips::CEIL_L_S_MMR6:
    case Mips::CEIL_W_D_MMR6:
    case Mips::CEIL_W_S_MMR6:
    case Mips::CVT_D_L_MMR6:
    case Mips::CVT_L_D_MMR6:
    case Mips::CVT_L_S_MMR6:
    case Mips::CVT_S_L_MMR6:
    case Mips::CVT_S_W_MMR6:
    case Mips::CVT_W_S_MMR6:
    case Mips::FLOOR_L_D_MMR6:
    case Mips::FLOOR_L_S_MMR6:
    case Mips::FLOOR_W_D_MMR6:
    case Mips::FLOOR_W_S_MMR6:
    case Mips::FMOV_D_MMR6:
    case Mips::FMOV_S_MMR6:
    case Mips::FNEG_S_MMR6:
    case Mips::ROUND_L_D_MMR6:
    case Mips::ROUND_L_S_MMR6:
    case Mips::ROUND_W_D_MMR6:
    case Mips::ROUND_W_S_MMR6:
    case Mips::TRUNC_L_D_MMR6:
    case Mips::TRUNC_L_S_MMR6:
    case Mips::TRUNC_W_D_MMR6:
    case Mips::TRUNC_W_S_MMR6: {
      // op: ft
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::FADD_S_MMR6:
    case Mips::FDIV_S_MMR6:
    case Mips::FMUL_S_MMR6:
    case Mips::FSUB_S_MMR6: {
      // op: ft
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::MAXA_D:
    case Mips::MAXA_S:
    case Mips::MAX_D:
    case Mips::MAX_S:
    case Mips::MINA_D:
    case Mips::MINA_S:
    case Mips::MIN_D:
    case Mips::MIN_S:
    case Mips::SELEQZ_D:
    case Mips::SELEQZ_S:
    case Mips::SELNEZ_D:
    case Mips::SELNEZ_S: {
      // op: ft
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::CMP_AF_D_MMR6:
    case Mips::CMP_AF_S_MMR6:
    case Mips::CMP_EQ_D_MMR6:
    case Mips::CMP_EQ_S_MMR6:
    case Mips::CMP_LE_D_MMR6:
    case Mips::CMP_LE_S_MMR6:
    case Mips::CMP_LT_D_MMR6:
    case Mips::CMP_LT_S_MMR6:
    case Mips::CMP_SAF_D_MMR6:
    case Mips::CMP_SAF_S_MMR6:
    case Mips::CMP_SEQ_D_MMR6:
    case Mips::CMP_SEQ_S_MMR6:
    case Mips::CMP_SLE_D_MMR6:
    case Mips::CMP_SLE_S_MMR6:
    case Mips::CMP_SLT_D_MMR6:
    case Mips::CMP_SLT_S_MMR6:
    case Mips::CMP_SUEQ_D_MMR6:
    case Mips::CMP_SUEQ_S_MMR6:
    case Mips::CMP_SULE_D_MMR6:
    case Mips::CMP_SULE_S_MMR6:
    case Mips::CMP_SULT_D_MMR6:
    case Mips::CMP_SULT_S_MMR6:
    case Mips::CMP_SUN_D_MMR6:
    case Mips::CMP_SUN_S_MMR6:
    case Mips::CMP_UEQ_D_MMR6:
    case Mips::CMP_UEQ_S_MMR6:
    case Mips::CMP_ULE_D_MMR6:
    case Mips::CMP_ULE_S_MMR6:
    case Mips::CMP_ULT_D_MMR6:
    case Mips::CMP_ULT_S_MMR6:
    case Mips::CMP_UN_D_MMR6:
    case Mips::CMP_UN_S_MMR6:
    case Mips::FADD_D32_MM:
    case Mips::FADD_D64_MM:
    case Mips::FADD_S_MM:
    case Mips::FDIV_D32_MM:
    case Mips::FDIV_D64_MM:
    case Mips::FDIV_S_MM:
    case Mips::FMUL_D32_MM:
    case Mips::FMUL_D64_MM:
    case Mips::FMUL_S_MM:
    case Mips::FSUB_D32_MM:
    case Mips::FSUB_D64_MM:
    case Mips::FSUB_S_MM:
    case Mips::MAXA_D_MMR6:
    case Mips::MAXA_S_MMR6:
    case Mips::MAX_D_MMR6:
    case Mips::MAX_S_MMR6:
    case Mips::MINA_D_MMR6:
    case Mips::MINA_S_MMR6:
    case Mips::MIN_D_MMR6:
    case Mips::MIN_S_MMR6:
    case Mips::SELEQZ_D_MMR6:
    case Mips::SELEQZ_S_MMR6:
    case Mips::SELNEZ_D_MMR6:
    case Mips::SELNEZ_S_MMR6: {
      // op: ft
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::MADDF_D:
    case Mips::MADDF_S:
    case Mips::MSUBF_D:
    case Mips::MSUBF_S:
    case Mips::SEL_D:
    case Mips::SEL_S: {
      // op: ft
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::MADDF_D_MMR6:
    case Mips::MADDF_S_MMR6:
    case Mips::MSUBF_D_MMR6:
    case Mips::MSUBF_S_MMR6:
    case Mips::SEL_D_MMR6:
    case Mips::SEL_S_MMR6: {
      // op: ft
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::MADD_D32_MM:
    case Mips::MADD_S_MM:
    case Mips::MSUB_D32_MM:
    case Mips::MSUB_S_MM:
    case Mips::NMADD_D32_MM:
    case Mips::NMADD_S_MM:
    case Mips::NMSUB_D32_MM:
    case Mips::NMSUB_S_MM: {
      // op: ft
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: fr
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::ADDVI_B:
    case Mips::ADDVI_D:
    case Mips::ADDVI_H:
    case Mips::ADDVI_W:
    case Mips::CEQI_B:
    case Mips::CEQI_D:
    case Mips::CEQI_H:
    case Mips::CEQI_W:
    case Mips::CLEI_S_B:
    case Mips::CLEI_S_D:
    case Mips::CLEI_S_H:
    case Mips::CLEI_S_W:
    case Mips::CLEI_U_B:
    case Mips::CLEI_U_D:
    case Mips::CLEI_U_H:
    case Mips::CLEI_U_W:
    case Mips::CLTI_S_B:
    case Mips::CLTI_S_D:
    case Mips::CLTI_S_H:
    case Mips::CLTI_S_W:
    case Mips::CLTI_U_B:
    case Mips::CLTI_U_D:
    case Mips::CLTI_U_H:
    case Mips::CLTI_U_W:
    case Mips::MAXI_S_B:
    case Mips::MAXI_S_D:
    case Mips::MAXI_S_H:
    case Mips::MAXI_S_W:
    case Mips::MAXI_U_B:
    case Mips::MAXI_U_D:
    case Mips::MAXI_U_H:
    case Mips::MAXI_U_W:
    case Mips::MINI_S_B:
    case Mips::MINI_S_D:
    case Mips::MINI_S_H:
    case Mips::MINI_S_W:
    case Mips::MINI_U_B:
    case Mips::MINI_U_D:
    case Mips::MINI_U_H:
    case Mips::MINI_U_W:
    case Mips::SUBVI_B:
    case Mips::SUBVI_D:
    case Mips::SUBVI_H:
    case Mips::SUBVI_W: {
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::ADDIUSP_MM: {
      // op: imm
      op = getSImm9AddiuspValue(MI, 0, Fixups, STI);
      Value |= (op & 0x1ff) << 1;
      break;
    }
    case Mips::JRCADDIUSP_MMR6: {
      // op: imm
      op = getUImm5Lsl2Encoding(MI, 0, Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case Mips::JRADDIUSP: {
      // op: imm
      op = getUImm5Lsl2Encoding(MI, 0, Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case Mips::Bimm16: {
      // op: imm11
      op = getBranchTargetOpValue(MI, 0, Fixups, STI);
      Value |= (op & 0x7ff);
      break;
    }
    case Mips::AddiuRxRyOffMemX16: {
      // op: imm15
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7f0) << 16;
      Value |= (op & 0x7800) << 5;
      Value |= (op & 0xf);
      // op: rx
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 8;
      // op: ry
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case Mips::BimmX16: {
      // op: imm16
      op = getBranchTargetOpValue(MI, 0, Fixups, STI);
      Value |= (op & 0x7e0) << 16;
      Value |= (op & 0xf800) << 5;
      Value |= (op & 0x1f);
      break;
    }
    case Mips::BeqzRxImmX16:
    case Mips::BnezRxImmX16: {
      // op: imm16
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
      Value |= (op & 0x7e0) << 16;
      Value |= (op & 0xf800) << 5;
      Value |= (op & 0x1f);
      // op: rx
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 8;
      break;
    }
    case Mips::AddiuSpImmX16:
    case Mips::BteqzX16:
    case Mips::BtnezX16: {
      // op: imm16
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7e0) << 16;
      Value |= (op & 0xf800) << 5;
      Value |= (op & 0x1f);
      break;
    }
    case Mips::AddiuRxImmX16:
    case Mips::AddiuRxPcImmX16:
    case Mips::CmpiRxImmX16:
    case Mips::LiRxImmAlignX16:
    case Mips::LiRxImmX16:
    case Mips::LwRxPcTcpX16:
    case Mips::SltiRxImmX16:
    case Mips::SltiuRxImmX16: {
      // op: imm16
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7e0) << 16;
      Value |= (op & 0xf800) << 5;
      Value |= (op & 0x1f);
      // op: rx
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 8;
      break;
    }
    case Mips::AddiuRxRxImmX16: {
      // op: imm16
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7e0) << 16;
      Value |= (op & 0xf800) << 5;
      Value |= (op & 0x1f);
      // op: rx
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 8;
      break;
    }
    case Mips::LbRxRyOffMemX16:
    case Mips::LbuRxRyOffMemX16:
    case Mips::LhRxRyOffMemX16:
    case Mips::LhuRxRyOffMemX16:
    case Mips::LwRxRyOffMemX16:
    case Mips::LwRxSpImmX16:
    case Mips::SbRxRyOffMemX16:
    case Mips::ShRxRyOffMemX16:
    case Mips::SwRxRyOffMemX16:
    case Mips::SwRxSpImmX16: {
      // op: imm16
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7e0) << 16;
      Value |= (op & 0xf800) << 5;
      Value |= (op & 0x1f);
      // op: rx
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 8;
      // op: ry
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case Mips::Jal16:
    case Mips::JalB16: {
      // op: imm26
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f0000) << 5;
      Value |= (op & 0x3e00000) >> 5;
      Value |= (op & 0xffff);
      break;
    }
    case Mips::AddiuSpImm16:
    case Mips::Bteqz16:
    case Mips::Btnez16: {
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xff);
      break;
    }
    case Mips::PREFX_MM: {
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: base
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: hint
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::LBUX_MM:
    case Mips::LHX_MM:
    case Mips::LWX_MM: {
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: base
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::COPY_S_D: {
      // op: n
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::SPLATI_D: {
      // op: n
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::INSVE_D: {
      // op: n
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::COPY_S_W:
    case Mips::COPY_U_W: {
      // op: n
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::SPLATI_W: {
      // op: n
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::INSVE_W: {
      // op: n
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::COPY_S_H:
    case Mips::COPY_U_H: {
      // op: n
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::SPLATI_H: {
      // op: n
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::INSVE_H: {
      // op: n
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::COPY_S_B:
    case Mips::COPY_U_B: {
      // op: n
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::SPLATI_B: {
      // op: n
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::INSVE_B: {
      // op: n
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::INSERT_D: {
      // op: n
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 16;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::SLDI_D: {
      // op: n
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::INSERT_W: {
      // op: n
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 16;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::SLDI_W: {
      // op: n
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::INSERT_H: {
      // op: n
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 16;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::SLDI_H: {
      // op: n
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::INSERT_B: {
      // op: n
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::SLDI_B: {
      // op: n
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::BALC:
    case Mips::BC: {
      // op: offset
      op = getBranchTarget26OpValue(MI, 0, Fixups, STI);
      Value |= (op & 0x3ffffff);
      break;
    }
    case Mips::BALC_MMR6:
    case Mips::BC_MMR6: {
      // op: offset
      op = getBranchTarget26OpValueMM(MI, 0, Fixups, STI);
      Value |= (op & 0x3ffffff);
      break;
    }
    case Mips::BAL:
    case Mips::BPOSGE32: {
      // op: offset
      op = getBranchTargetOpValue(MI, 0, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::BNZ_B:
    case Mips::BNZ_D:
    case Mips::BNZ_H:
    case Mips::BNZ_V:
    case Mips::BNZ_W:
    case Mips::BZ_B:
    case Mips::BZ_D:
    case Mips::BZ_H:
    case Mips::BZ_V:
    case Mips::BZ_W: {
      // op: offset
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
      Value |= (op & 0xffff);
      // op: wt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::BPOSGE32C_MMR3: {
      // op: offset
      op = getBranchTargetOpValue1SImm16(MI, 0, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::BPOSGE32_MM: {
      // op: offset
      op = getBranchTargetOpValueMM(MI, 0, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::B16_MM:
    case Mips::BC16_MMR6: {
      // op: offset
      op = getBranchTargetOpValueMMPC10(MI, 0, Fixups, STI);
      Value |= (op & 0x3ff);
      break;
    }
    case Mips::Move32R16: {
      // op: r32
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 5;
      Value |= (op & 0x18);
      // op: rz
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case Mips::MFHI:
    case Mips::MFHI64:
    case Mips::MFLO:
    case Mips::MFLO64: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::MFHI_DSP:
    case Mips::MFLO_DSP: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: ac
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3) << 21;
      break;
    }
    case Mips::LWXS_MM: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: base
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::LBUX:
    case Mips::LHX:
    case Mips::LWX: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: base
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::REPL_PH:
    case Mips::REPL_PH_MM:
    case Mips::REPL_QB: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3ff) << 16;
      break;
    }
    case Mips::RDDSP: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: mask
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3ff) << 16;
      break;
    }
    case Mips::ADDQH_PH_MMR2:
    case Mips::ADDQH_R_PH_MMR2:
    case Mips::ADDQH_R_W_MMR2:
    case Mips::ADDQH_W_MMR2:
    case Mips::ADDQ_PH_MM:
    case Mips::ADDQ_S_PH_MM:
    case Mips::ADDQ_S_W_MM:
    case Mips::ADDSC_MM:
    case Mips::ADDUH_QB_MMR2:
    case Mips::ADDUH_R_QB_MMR2:
    case Mips::ADDU_PH_MMR2:
    case Mips::ADDU_QB_MM:
    case Mips::ADDU_S_PH_MMR2:
    case Mips::ADDU_S_QB_MM:
    case Mips::ADDWC_MM:
    case Mips::CMPGDU_EQ_QB_MMR2:
    case Mips::CMPGDU_LE_QB_MMR2:
    case Mips::CMPGDU_LT_QB_MMR2:
    case Mips::MODSUB_MM:
    case Mips::MULEQ_S_W_PHL_MM:
    case Mips::MULEQ_S_W_PHR_MM:
    case Mips::MULEU_S_PH_QBL_MM:
    case Mips::MULEU_S_PH_QBR_MM:
    case Mips::MULQ_RS_PH_MM:
    case Mips::MULQ_RS_W_MMR2:
    case Mips::MULQ_S_PH_MMR2:
    case Mips::MULQ_S_W_MMR2:
    case Mips::MUL_PH_MMR2:
    case Mips::MUL_S_PH_MMR2:
    case Mips::PACKRL_PH_MM:
    case Mips::PICK_PH_MM:
    case Mips::PICK_QB_MM:
    case Mips::PRECRQU_S_QB_PH_MM:
    case Mips::PRECRQ_PH_W_MM:
    case Mips::PRECRQ_QB_PH_MM:
    case Mips::PRECRQ_RS_PH_W_MM:
    case Mips::PRECR_QB_PH_MMR2:
    case Mips::SELEQZ_MMR6:
    case Mips::SELNEZ_MMR6:
    case Mips::SUBQH_PH_MMR2:
    case Mips::SUBQH_R_PH_MMR2:
    case Mips::SUBQH_R_W_MMR2:
    case Mips::SUBQH_W_MMR2:
    case Mips::SUBQ_PH_MM:
    case Mips::SUBQ_S_PH_MM:
    case Mips::SUBQ_S_W_MM:
    case Mips::SUBUH_QB_MMR2:
    case Mips::SUBUH_R_QB_MMR2:
    case Mips::SUBU_PH_MMR2:
    case Mips::SUBU_QB_MM:
    case Mips::SUBU_S_PH_MMR2:
    case Mips::SUBU_S_QB_MM: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::LSA_MMR6: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: imm2
      op = getUImmWithOffsetEncoding<2, 1>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 9;
      break;
    }
    case Mips::CLO_R6:
    case Mips::CLZ_R6:
    case Mips::DCLO_R6:
    case Mips::DCLZ_R6:
    case Mips::DPOP:
    case Mips::JALR:
    case Mips::JALR64:
    case Mips::JALR_HB:
    case Mips::JALR_HB64:
    case Mips::POP:
    case Mips::RADDU_W_QB: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::MOVF_I:
    case Mips::MOVF_I64:
    case Mips::MOVT_I:
    case Mips::MOVT_I64: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: fcc
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 18;
      break;
    }
    case Mips::ADD:
    case Mips::ADDQH_PH:
    case Mips::ADDQH_R_PH:
    case Mips::ADDQH_R_W:
    case Mips::ADDQH_W:
    case Mips::ADDQ_PH:
    case Mips::ADDQ_S_PH:
    case Mips::ADDQ_S_W:
    case Mips::ADDSC:
    case Mips::ADDUH_QB:
    case Mips::ADDUH_R_QB:
    case Mips::ADDU_PH:
    case Mips::ADDU_QB:
    case Mips::ADDU_S_PH:
    case Mips::ADDU_S_QB:
    case Mips::ADDWC:
    case Mips::ADDu:
    case Mips::AND:
    case Mips::AND64:
    case Mips::BADDu:
    case Mips::DADD:
    case Mips::DADDu:
    case Mips::DDIV:
    case Mips::DDIVU:
    case Mips::DIV:
    case Mips::DIVU:
    case Mips::DMOD:
    case Mips::DMODU:
    case Mips::DMUH:
    case Mips::DMUHU:
    case Mips::DMUL:
    case Mips::DMULU:
    case Mips::DMUL_R6:
    case Mips::DSUB:
    case Mips::DSUBu:
    case Mips::MOD:
    case Mips::MODSUB:
    case Mips::MODU:
    case Mips::MOVN_I64_I:
    case Mips::MOVN_I64_I64:
    case Mips::MOVN_I_I:
    case Mips::MOVN_I_I64:
    case Mips::MOVZ_I64_I:
    case Mips::MOVZ_I64_I64:
    case Mips::MOVZ_I_I:
    case Mips::MOVZ_I_I64:
    case Mips::MUH:
    case Mips::MUHU:
    case Mips::MUL:
    case Mips::MULEQ_S_W_PHL:
    case Mips::MULEQ_S_W_PHR:
    case Mips::MULEU_S_PH_QBL:
    case Mips::MULEU_S_PH_QBR:
    case Mips::MULQ_RS_PH:
    case Mips::MULQ_RS_W:
    case Mips::MULQ_S_PH:
    case Mips::MULQ_S_W:
    case Mips::MULU:
    case Mips::MUL_PH:
    case Mips::MUL_R6:
    case Mips::MUL_S_PH:
    case Mips::NOR:
    case Mips::NOR64:
    case Mips::OR:
    case Mips::OR64:
    case Mips::SELEQZ:
    case Mips::SELEQZ64:
    case Mips::SELNEZ:
    case Mips::SELNEZ64:
    case Mips::SEQ:
    case Mips::SLT:
    case Mips::SLT64:
    case Mips::SLTu:
    case Mips::SLTu64:
    case Mips::SNE:
    case Mips::SUB:
    case Mips::SUBQH_PH:
    case Mips::SUBQH_R_PH:
    case Mips::SUBQH_R_W:
    case Mips::SUBQH_W:
    case Mips::SUBQ_PH:
    case Mips::SUBQ_S_PH:
    case Mips::SUBQ_S_W:
    case Mips::SUBUH_QB:
    case Mips::SUBUH_R_QB:
    case Mips::SUBU_PH:
    case Mips::SUBU_QB:
    case Mips::SUBU_S_PH:
    case Mips::SUBU_S_QB:
    case Mips::SUBu:
    case Mips::V3MULU:
    case Mips::VMM0:
    case Mips::VMULU:
    case Mips::XOR:
    case Mips::XOR64: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::ALIGN: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: bp
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 6;
      break;
    }
    case Mips::ALIGN_MMR6: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: bp
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 9;
      break;
    }
    case Mips::DALIGN: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: bp
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 6;
      break;
    }
    case Mips::DLSA_R6:
    case Mips::LSA_R6: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: imm2
      op = getUImmWithOffsetEncoding<2, 1>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 6;
      break;
    }
    case Mips::SHLLV_PH_MM:
    case Mips::SHLLV_QB_MM:
    case Mips::SHLLV_S_PH_MM:
    case Mips::SHLLV_S_W_MM:
    case Mips::SHRAV_PH_MM:
    case Mips::SHRAV_QB_MMR2:
    case Mips::SHRAV_R_PH_MM:
    case Mips::SHRAV_R_QB_MMR2:
    case Mips::SHRAV_R_W_MM:
    case Mips::SHRLV_PH_MMR2:
    case Mips::SHRLV_QB_MM: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::ABSQ_S_PH:
    case Mips::ABSQ_S_QB:
    case Mips::ABSQ_S_W:
    case Mips::BITREV:
    case Mips::BITSWAP:
    case Mips::DBITSWAP:
    case Mips::DSBH:
    case Mips::DSHD:
    case Mips::DSLL64_32:
    case Mips::PRECEQU_PH_QBL:
    case Mips::PRECEQU_PH_QBLA:
    case Mips::PRECEQU_PH_QBR:
    case Mips::PRECEQU_PH_QBRA:
    case Mips::PRECEQ_W_PHL:
    case Mips::PRECEQ_W_PHR:
    case Mips::PRECEU_PH_QBL:
    case Mips::PRECEU_PH_QBLA:
    case Mips::PRECEU_PH_QBR:
    case Mips::PRECEU_PH_QBRA:
    case Mips::REPLV_PH:
    case Mips::REPLV_QB:
    case Mips::SEB:
    case Mips::SEB64:
    case Mips::SEH:
    case Mips::SEH64:
    case Mips::SLL64_32:
    case Mips::SLL64_64:
    case Mips::WSBH: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::DROTRV:
    case Mips::DSLLV:
    case Mips::DSRAV:
    case Mips::DSRLV:
    case Mips::ROTRV:
    case Mips::SLLV:
    case Mips::SRAV:
    case Mips::SRLV: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::SHLLV_PH:
    case Mips::SHLLV_QB:
    case Mips::SHLLV_S_PH:
    case Mips::SHLLV_S_W:
    case Mips::SHLL_PH:
    case Mips::SHLL_QB:
    case Mips::SHLL_S_PH:
    case Mips::SHLL_S_W:
    case Mips::SHRAV_PH:
    case Mips::SHRAV_QB:
    case Mips::SHRAV_R_PH:
    case Mips::SHRAV_R_QB:
    case Mips::SHRAV_R_W:
    case Mips::SHRA_PH:
    case Mips::SHRA_QB:
    case Mips::SHRA_R_PH:
    case Mips::SHRA_R_QB:
    case Mips::SHRA_R_W:
    case Mips::SHRLV_PH:
    case Mips::SHRLV_QB:
    case Mips::SHRL_PH:
    case Mips::SHRL_QB: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rs_sa
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::DROTR:
    case Mips::DROTR32:
    case Mips::DSLL:
    case Mips::DSLL32:
    case Mips::DSRA:
    case Mips::DSRA32:
    case Mips::DSRL:
    case Mips::DSRL32:
    case Mips::ROTR:
    case Mips::SLL:
    case Mips::SRA:
    case Mips::SRL: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: shamt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::ROTRV_MM:
    case Mips::SLLV_MM:
    case Mips::SRAV_MM:
    case Mips::SRLV_MM: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::ADDU_MMR6:
    case Mips::ADD_MMR6:
    case Mips::AND_MMR6:
    case Mips::DIVU_MMR6:
    case Mips::DIV_MMR6:
    case Mips::MODU_MMR6:
    case Mips::MOD_MMR6:
    case Mips::MUHU_MMR6:
    case Mips::MUH_MMR6:
    case Mips::MULU_MMR6:
    case Mips::MUL_MMR6:
    case Mips::NOR_MMR6:
    case Mips::OR_MMR6:
    case Mips::SUBU_MMR6:
    case Mips::SUB_MMR6:
    case Mips::XOR_MMR6: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::MFHI_MM:
    case Mips::MFLO_MM: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::BITSWAP_MMR6: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::CLO:
    case Mips::CLZ:
    case Mips::DCLO:
    case Mips::DCLZ: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      Value |= (op & 0x1f) << 11;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::CLO_MM:
    case Mips::CLZ_MM: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::MOVF_I_MM:
    case Mips::MOVT_I_MM: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: fcc
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 13;
      break;
    }
    case Mips::SEB_MM:
    case Mips::SEH_MM:
    case Mips::WSBH_MM: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::ROTR_MM:
    case Mips::SLL_MM:
    case Mips::SLL_MMR6:
    case Mips::SRA_MM:
    case Mips::SRL_MM: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: shamt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::CFCMSA: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      // op: cs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::MFHI16_MM:
    case Mips::MFLO16_MM: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case Mips::LI16_MM:
    case Mips::LI16_MMR6: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7f);
      break;
    }
    case Mips::ADDIUR1SP_MM: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: imm
      op = getUImm6Lsl2Encoding(MI, 1, Fixups, STI);
      Value |= (op & 0x3f) << 1;
      break;
    }
    case Mips::ADDIUR2_MM: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 4;
      // op: imm
      op = getSImm3Lsa2Value(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 1;
      break;
    }
    case Mips::ANDI16_MM:
    case Mips::ANDI16_MMR6: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 4;
      // op: imm
      op = getUImm4AndValue(MI, 2, Fixups, STI);
      Value |= (op & 0xf);
      break;
    }
    case Mips::SLL16_MM:
    case Mips::SLL16_MMR6:
    case Mips::SRL16_MM:
    case Mips::SRL16_MMR6: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 4;
      // op: shamt
      op = getUImm3Mod8Encoding(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 1;
      break;
    }
    case Mips::ADDU16_MM:
    case Mips::SUBU16_MM: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 4;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 1;
      break;
    }
    case Mips::ADDIUS5_MM: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 1;
      break;
    }
    case Mips::DVP_MMR6:
    case Mips::EVP_MMR6:
    case Mips::GINVI_MMR6:
    case Mips::JR_MM:
    case Mips::MTHI_MM:
    case Mips::MTLO_MM: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::MFHI_DSP_MM:
    case Mips::MFLO_DSP_MM: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: ac
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3) << 14;
      break;
    }
    case Mips::TEQI_MM:
    case Mips::TGEIU_MM:
    case Mips::TGEI_MM:
    case Mips::TLTIU_MM:
    case Mips::TLTI_MM:
    case Mips::TNEI_MM: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: imm16
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::BEQZC_MM:
    case Mips::BGEZALS_MM:
    case Mips::BGEZAL_MM:
    case Mips::BGEZ_MM:
    case Mips::BGTZ_MM:
    case Mips::BLEZ_MM:
    case Mips::BLTZALS_MM:
    case Mips::BLTZAL_MM:
    case Mips::BLTZ_MM:
    case Mips::BNEZC_MM: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: offset
      op = getBranchTargetOpValueMM(MI, 1, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::MADDU_MM:
    case Mips::MADD_MM:
    case Mips::MSUBU_MM:
    case Mips::MSUB_MM:
    case Mips::MULT_MM:
    case Mips::MULTu_MM:
    case Mips::SDIV_MM:
    case Mips::UDIV_MM: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::TEQ_MM:
    case Mips::TGEU_MM:
    case Mips::TGE_MM:
    case Mips::TLTU_MM:
    case Mips::TLT_MM:
    case Mips::TNE_MM: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: code_
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 12;
      break;
    }
    case Mips::BEQ_MM:
    case Mips::BNE_MM: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: offset
      op = getBranchTargetOpValueMM(MI, 2, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::GINVT_MMR6: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: type
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3) << 9;
      break;
    }
    case Mips::GINVI:
    case Mips::JR:
    case Mips::JR64:
    case Mips::JR_HB:
    case Mips::JR_HB64:
    case Mips::JR_HB64_R6:
    case Mips::JR_HB_R6:
    case Mips::MTHI:
    case Mips::MTHI64:
    case Mips::MTLO:
    case Mips::MTLO64:
    case Mips::MTM0:
    case Mips::MTM1:
    case Mips::MTM2:
    case Mips::MTP0:
    case Mips::MTP1:
    case Mips::MTP2: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::ALUIPC:
    case Mips::AUIPC: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::DAHI:
    case Mips::DATI: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::LDPC: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: imm
      op = getSimm18Lsl3Encoding(MI, 1, Fixups, STI);
      Value |= (op & 0x3ffff);
      break;
    }
    case Mips::ADDIUPC:
    case Mips::LWPC:
    case Mips::LWUPC: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: imm
      op = getSimm19Lsl2Encoding(MI, 1, Fixups, STI);
      Value |= (op & 0x7ffff);
      break;
    }
    case Mips::TEQI:
    case Mips::TGEI:
    case Mips::TGEIU:
    case Mips::TLTI:
    case Mips::TNEI:
    case Mips::TTLTIU: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: imm16
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::WRDSP: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: mask
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3ff) << 11;
      break;
    }
    case Mips::BEQZC:
    case Mips::BEQZC64:
    case Mips::BNEZC:
    case Mips::BNEZC64: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: offset
      op = getBranchTarget21OpValue(MI, 1, Fixups, STI);
      Value |= (op & 0x1fffff);
      break;
    }
    case Mips::BEQZC_MMR6:
    case Mips::BNEZC_MMR6: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: offset
      op = getBranchTarget21OpValueMM(MI, 1, Fixups, STI);
      Value |= (op & 0x1fffff);
      break;
    }
    case Mips::BGEZ:
    case Mips::BGEZ64:
    case Mips::BGEZAL:
    case Mips::BGEZALL:
    case Mips::BGEZL:
    case Mips::BGTZ:
    case Mips::BGTZ64:
    case Mips::BGTZL:
    case Mips::BLEZ:
    case Mips::BLEZ64:
    case Mips::BLEZL:
    case Mips::BLTZ:
    case Mips::BLTZ64:
    case Mips::BLTZAL:
    case Mips::BLTZALL:
    case Mips::BLTZL: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: offset
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::BBIT0:
    case Mips::BBIT032:
    case Mips::BBIT1:
    case Mips::BBIT132: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: offset
      op = getBranchTargetOpValue(MI, 2, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::CMPU_EQ_QB:
    case Mips::CMPU_LE_QB:
    case Mips::CMPU_LT_QB:
    case Mips::CMP_EQ_PH:
    case Mips::CMP_LE_PH:
    case Mips::CMP_LT_PH:
    case Mips::DMULT:
    case Mips::DMULTu:
    case Mips::DSDIV:
    case Mips::DUDIV:
    case Mips::MADD:
    case Mips::MADDU:
    case Mips::MSUB:
    case Mips::MSUBU:
    case Mips::MULT:
    case Mips::MULTu:
    case Mips::SDIV:
    case Mips::UDIV: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::TEQ:
    case Mips::TGE:
    case Mips::TGEU:
    case Mips::TLT:
    case Mips::TLTU:
    case Mips::TNE: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: code_
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3ff) << 6;
      break;
    }
    case Mips::BEQ:
    case Mips::BEQ64:
    case Mips::BEQC:
    case Mips::BEQC64:
    case Mips::BEQL:
    case Mips::BGEC:
    case Mips::BGEC64:
    case Mips::BGEUC:
    case Mips::BGEUC64:
    case Mips::BLTC:
    case Mips::BLTC64:
    case Mips::BLTUC:
    case Mips::BLTUC64:
    case Mips::BNE:
    case Mips::BNE64:
    case Mips::BNEC:
    case Mips::BNEC64:
    case Mips::BNEL:
    case Mips::BNVC:
    case Mips::BOVC: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: offset
      op = getBranchTargetOpValue(MI, 2, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::FORK: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::GINVT: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: type_
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3) << 8;
      break;
    }
    case Mips::JALRC16_MMR6:
    case Mips::JRC16_MMR6: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case Mips::JALR16_MM:
    case Mips::JALRS16_MM:
    case Mips::JR16_MM:
    case Mips::JRC16_MM: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case Mips::ADDIUPC_MM: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 23;
      // op: imm
      op = getSimm23Lsl2Encoding(MI, 1, Fixups, STI);
      Value |= (op & 0x7fffff);
      break;
    }
    case Mips::BEQZ16_MM:
    case Mips::BEQZC16_MMR6:
    case Mips::BNEZ16_MM:
    case Mips::BNEZC16_MMR6: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: offset
      op = getBranchTarget7OpValueMM(MI, 1, Fixups, STI);
      Value |= (op & 0x7f);
      break;
    }
    case Mips::CTCMSA: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: cd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::FILL_B:
    case Mips::FILL_D:
    case Mips::FILL_H:
    case Mips::FILL_W: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::MTHI_DSP_MM:
    case Mips::MTHLIP_MM:
    case Mips::MTLO_DSP_MM:
    case Mips::SHILOV_MM: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: ac
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3) << 14;
      break;
    }
    case Mips::JALRS_MM:
    case Mips::JALR_MM: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::CLO_MMR6: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::AUI_MMR6: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::ADDi_MM:
    case Mips::ADDiu_MM:
    case Mips::ANDi_MM:
    case Mips::ORi_MM:
    case Mips::XORi_MM: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: imm16
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::MTHI_DSP:
    case Mips::MTLO_DSP: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: ac
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3) << 11;
      break;
    }
    case Mips::YIELD: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::CLZ_MMR6: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::AUI:
    case Mips::DAUI: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::SEQi:
    case Mips::SNEi: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: imm10
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3ff) << 6;
      break;
    }
    case Mips::ADDi:
    case Mips::ADDiu:
    case Mips::ANDi:
    case Mips::ANDi64:
    case Mips::DADDi:
    case Mips::DADDiu:
    case Mips::ORi:
    case Mips::ORi64:
    case Mips::XORi:
    case Mips::XORi64: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: imm16
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::PRECR_SRA_PH_W:
    case Mips::PRECR_SRA_R_PH_W: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: sa
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::CRC32B:
    case Mips::CRC32CB:
    case Mips::CRC32CD:
    case Mips::CRC32CH:
    case Mips::CRC32CW:
    case Mips::CRC32D:
    case Mips::CRC32H:
    case Mips::CRC32W: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::CMPGDU_EQ_QB:
    case Mips::CMPGDU_LE_QB:
    case Mips::CMPGDU_LT_QB:
    case Mips::CMPGU_EQ_QB:
    case Mips::CMPGU_LE_QB:
    case Mips::CMPGU_LT_QB:
    case Mips::PACKRL_PH:
    case Mips::PICK_PH:
    case Mips::PICK_QB:
    case Mips::PRECRQU_S_QB_PH:
    case Mips::PRECRQ_PH_W:
    case Mips::PRECRQ_QB_PH:
    case Mips::PRECRQ_RS_PH_W:
    case Mips::PRECR_QB_PH: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::DLSA:
    case Mips::LSA: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: sa
      op = getUImmWithOffsetEncoding<2, 1>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 6;
      break;
    }
    case Mips::MOVE16_MM:
    case Mips::MOVE16_MMR6: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case Mips::ADDU16_MMR6:
    case Mips::SUBU16_MMR6: {
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 4;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 1;
      break;
    }
    case Mips::DI:
    case Mips::DI_MM:
    case Mips::DI_MMR6:
    case Mips::DMT:
    case Mips::DVP:
    case Mips::DVPE:
    case Mips::EI:
    case Mips::EI_MM:
    case Mips::EI_MMR6:
    case Mips::EMT:
    case Mips::EVP:
    case Mips::EVPE: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::EXTP:
    case Mips::EXTPDP:
    case Mips::EXTPDPV:
    case Mips::EXTPV:
    case Mips::EXTRV_RS_W:
    case Mips::EXTRV_R_W:
    case Mips::EXTRV_S_H:
    case Mips::EXTRV_W:
    case Mips::EXTR_RS_W:
    case Mips::EXTR_R_W:
    case Mips::EXTR_S_H:
    case Mips::EXTR_W: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: ac
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3) << 11;
      // op: shift_rs
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::LL64_R6:
    case Mips::LLD_R6:
    case Mips::LL_R6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: addr
      op = getMemEncoding(MI, 1, Fixups, STI);
      Value |= (op & 0x1f0000) << 5;
      Value |= (op & 0x1ff) << 7;
      break;
    }
    case Mips::LB:
    case Mips::LB64:
    case Mips::LBu:
    case Mips::LBu64:
    case Mips::LD:
    case Mips::LDC1:
    case Mips::LDC164:
    case Mips::LDC2:
    case Mips::LDC3:
    case Mips::LDL:
    case Mips::LDR:
    case Mips::LEA_ADDiu:
    case Mips::LEA_ADDiu64:
    case Mips::LH:
    case Mips::LH64:
    case Mips::LHu:
    case Mips::LHu64:
    case Mips::LL:
    case Mips::LL64:
    case Mips::LLD:
    case Mips::LW:
    case Mips::LW64:
    case Mips::LWC1:
    case Mips::LWC2:
    case Mips::LWC3:
    case Mips::LWDSP:
    case Mips::LWL:
    case Mips::LWL64:
    case Mips::LWR:
    case Mips::LWR64:
    case Mips::LWu:
    case Mips::SB:
    case Mips::SB64:
    case Mips::SD:
    case Mips::SDC1:
    case Mips::SDC164:
    case Mips::SDC2:
    case Mips::SDC3:
    case Mips::SDL:
    case Mips::SDR:
    case Mips::SH:
    case Mips::SH64:
    case Mips::SW:
    case Mips::SW64:
    case Mips::SWC1:
    case Mips::SWC2:
    case Mips::SWC3:
    case Mips::SWDSP:
    case Mips::SWL:
    case Mips::SWL64:
    case Mips::SWR:
    case Mips::SWR64: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: addr
      op = getMemEncoding(MI, 1, Fixups, STI);
      Value |= (op & 0x1f0000) << 5;
      Value |= (op & 0xffff);
      break;
    }
    case Mips::LDC2_R6:
    case Mips::LWC2_R6:
    case Mips::SDC2_R6:
    case Mips::SWC2_R6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: addr
      op = getMemEncoding(MI, 1, Fixups, STI);
      Value |= (op & 0x1f0000) >> 5;
      Value |= (op & 0x7ff);
      break;
    }
    case Mips::CFC1:
    case Mips::DMFC1:
    case Mips::MFC1:
    case Mips::MFC1_D64:
    case Mips::MFHC1_D32:
    case Mips::MFHC1_D64: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::DMFC2_OCTEON:
    case Mips::DMTC2_OCTEON:
    case Mips::LUi:
    case Mips::LUi64:
    case Mips::LUi_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: imm16
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::BEQZALC:
    case Mips::BGTZALC:
    case Mips::BGTZC:
    case Mips::BGTZC64:
    case Mips::BLEZALC:
    case Mips::BLEZC:
    case Mips::BLEZC64:
    case Mips::BNEZALC: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: offset
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::BC1EQZC_MMR6:
    case Mips::BC1NEZC_MMR6:
    case Mips::BC2EQZC_MMR6:
    case Mips::BC2NEZC_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: offset
      op = getBranchTargetOpValueMM(MI, 1, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::JIALC:
    case Mips::JIALC64:
    case Mips::JIALC_MMR6:
    case Mips::JIC:
    case Mips::JIC64:
    case Mips::JIC_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: offset
      op = getJumpOffset16OpValue(MI, 1, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::RDHWR:
    case Mips::RDHWR64: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: sel
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 6;
      break;
    }
    case Mips::DMFC0:
    case Mips::DMFC2:
    case Mips::DMFGC0:
    case Mips::MFC0:
    case Mips::MFC2:
    case Mips::MFGC0:
    case Mips::MFHGC0: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: sel
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case Mips::SAA:
    case Mips::SAAD: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::SLTi:
    case Mips::SLTi64:
    case Mips::SLTiu:
    case Mips::SLTiu64: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: imm16
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::CINS:
    case Mips::CINS32:
    case Mips::CINS64_32:
    case Mips::CINS_i32:
    case Mips::EXTS:
    case Mips::EXTS32: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: pos
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      // op: lenm1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::DINS:
    case Mips::DINSM:
    case Mips::DINSU:
    case Mips::INS: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: pos
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      // op: size
      op = getSizeInsEncoding(MI, 3, Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::DEXT:
    case Mips::DEXT64_32:
    case Mips::DEXTM:
    case Mips::DEXTU:
    case Mips::EXT: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: pos
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      // op: size
      op = getUImmWithOffsetEncoding<5, 1>(MI, 3, Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::APPEND:
    case Mips::BALIGN:
    case Mips::PREPEND: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: sa
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::INSV: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      break;
    }
    case Mips::LBE_MM:
    case Mips::LBuE_MM:
    case Mips::LHE_MM:
    case Mips::LHuE_MM:
    case Mips::LLE_MM:
    case Mips::LWE_MM:
    case Mips::SBE_MM:
    case Mips::SHE_MM:
    case Mips::SWE_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: addr
      op = getMemEncoding(MI, 1, Fixups, STI);
      Value |= (op & 0x1f0000);
      Value |= (op & 0x1ff);
      break;
    }
    case Mips::LWU_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: addr
      op = getMemEncoding(MI, 1, Fixups, STI);
      Value |= (op & 0x1f0000);
      Value |= (op & 0xfff);
      break;
    }
    case Mips::LEA_ADDiu_MM:
    case Mips::LH_MM:
    case Mips::LHu_MM:
    case Mips::LWDSP_MM:
    case Mips::LW_MM:
    case Mips::LW_MMR6:
    case Mips::SB_MM:
    case Mips::SB_MMR6:
    case Mips::SH_MM:
    case Mips::SH_MMR6:
    case Mips::SWDSP_MM:
    case Mips::SW_MM:
    case Mips::SW_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: addr
      op = getMemEncoding(MI, 1, Fixups, STI);
      Value |= (op & 0x1fffff);
      break;
    }
    case Mips::LWP_MM:
    case Mips::SWP_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: addr
      op = getMemEncoding(MI, 2, Fixups, STI);
      Value |= (op & 0x1f0000);
      Value |= (op & 0xfff);
      break;
    }
    case Mips::LDC2_MMR6:
    case Mips::LWC2_MMR6:
    case Mips::SDC2_MMR6:
    case Mips::SWC2_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: addr
      op = getMemEncodingMMImm11(MI, 1, Fixups, STI);
      Value |= (op & 0x1f0000);
      Value |= (op & 0x7ff);
      break;
    }
    case Mips::LL_MM:
    case Mips::LWL_MM:
    case Mips::LWR_MM:
    case Mips::SWL_MM:
    case Mips::SWR_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: addr
      op = getMemEncodingMMImm12(MI, 1, Fixups, STI);
      Value |= (op & 0x1f0000);
      Value |= (op & 0xfff);
      break;
    }
    case Mips::LB_MM:
    case Mips::LBu_MM:
    case Mips::LDC1_MM_D32:
    case Mips::LDC1_MM_D64:
    case Mips::LWC1_MM:
    case Mips::SDC1_MM_D32:
    case Mips::SDC1_MM_D64:
    case Mips::SWC1_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: addr
      op = getMemEncodingMMImm16(MI, 1, Fixups, STI);
      Value |= (op & 0x1fffff);
      break;
    }
    case Mips::LL_MMR6:
    case Mips::LWLE_MM:
    case Mips::LWRE_MM:
    case Mips::SWLE_MM:
    case Mips::SWRE_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: addr
      op = getMemEncodingMMImm9(MI, 1, Fixups, STI);
      Value |= (op & 0x1f0000);
      Value |= (op & 0x1ff);
      break;
    }
    case Mips::CFC1_MM:
    case Mips::MFC1_MM:
    case Mips::MFC1_MMR6:
    case Mips::MFHC1_D32_MM:
    case Mips::MFHC1_D64_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::REPL_QB_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xff) << 13;
      break;
    }
    case Mips::ALUIPC_MMR6:
    case Mips::AUIPC_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::EXTPDP_MM:
    case Mips::EXTP_MM:
    case Mips::EXTR_RS_W_MM:
    case Mips::EXTR_R_W_MM:
    case Mips::EXTR_S_H_MM:
    case Mips::EXTR_W_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: ac
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3) << 14;
      break;
    }
    case Mips::ADDIUPC_MMR6:
    case Mips::LWPC_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: imm
      op = getSimm19Lsl2Encoding(MI, 1, Fixups, STI);
      Value |= (op & 0x7ffff);
      break;
    }
    case Mips::LUI_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: imm16
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::CFC2_MM:
    case Mips::MFC2_MMR6:
    case Mips::MFHC2_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: impl
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::RDDSP_MM:
    case Mips::WRDSP_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: mask
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7f) << 14;
      break;
    }
    case Mips::BGTZC_MMR6:
    case Mips::BLEZC_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: offset
      op = getBranchTargetOpValueLsl2MMR6(MI, 1, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::BEQZALC_MMR6:
    case Mips::BGTZALC_MMR6:
    case Mips::BLEZALC_MMR6:
    case Mips::BNEZALC_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: offset
      op = getBranchTargetOpValueMM(MI, 1, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::RDHWR_MM:
    case Mips::RDPGPR_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::ABSQ_S_PH_MM:
    case Mips::ABSQ_S_QB_MMR2:
    case Mips::ABSQ_S_W_MM:
    case Mips::BITREV_MM:
    case Mips::JALRC_HB_MMR6:
    case Mips::JALRC_MMR6:
    case Mips::PRECEQU_PH_QBLA_MM:
    case Mips::PRECEQU_PH_QBL_MM:
    case Mips::PRECEQU_PH_QBRA_MM:
    case Mips::PRECEQU_PH_QBR_MM:
    case Mips::PRECEQ_W_PHL_MM:
    case Mips::PRECEQ_W_PHR_MM:
    case Mips::PRECEU_PH_QBLA_MM:
    case Mips::PRECEU_PH_QBL_MM:
    case Mips::PRECEU_PH_QBRA_MM:
    case Mips::PRECEU_PH_QBR_MM:
    case Mips::RADDU_W_QB_MM:
    case Mips::REPLV_PH_MM:
    case Mips::REPLV_QB_MM:
    case Mips::WRPGPR_MMR6:
    case Mips::WSBH_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::BALIGN_MMR2: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: bp
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3) << 14;
      break;
    }
    case Mips::ADDIU_MMR6:
    case Mips::ANDI_MMR6:
    case Mips::ORI_MMR6:
    case Mips::SLTi_MM:
    case Mips::SLTiu_MM:
    case Mips::XORI_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: imm16
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::BNVC_MMR6:
    case Mips::BOVC_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: offset
      op = getBranchTargetOpValueMMR6(MI, 2, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::INS_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: pos
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      // op: size
      op = getSizeInsEncoding(MI, 3, Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::EXT_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: pos
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      // op: size
      op = getUImmWithOffsetEncoding<5, 1>(MI, 3, Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::APPEND_MMR2:
    case Mips::PRECR_SRA_PH_W_MMR2:
    case Mips::PRECR_SRA_R_PH_W_MMR2:
    case Mips::PREPEND_MMR2:
    case Mips::SHLL_S_W_MM:
    case Mips::SHRA_R_W_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: sa
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::SHLL_QB_MM:
    case Mips::SHRA_QB_MMR2:
    case Mips::SHRA_R_QB_MMR2:
    case Mips::SHRL_QB_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: sa
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 13;
      break;
    }
    case Mips::SHLL_PH_MM:
    case Mips::SHLL_S_PH_MM:
    case Mips::SHRA_PH_MM:
    case Mips::SHRA_R_PH_MM:
    case Mips::SHRL_PH_MMR2: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: sa
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 12;
      break;
    }
    case Mips::MFC0_MMR6:
    case Mips::MFGC0_MM:
    case Mips::MFHC0_MMR6:
    case Mips::MFHGC0_MM:
    case Mips::RDHWR_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: sel
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 11;
      break;
    }
    case Mips::INS_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: size
      op = getSizeInsEncoding(MI, 3, Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: pos
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::EXT_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: size
      op = getUImmWithOffsetEncoding<5, 1>(MI, 3, Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: pos
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::INSV_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::EXTPDPV_MM:
    case Mips::EXTPV_MM:
    case Mips::EXTRV_RS_W_MM:
    case Mips::EXTRV_R_W_MM:
    case Mips::EXTRV_S_H_MM:
    case Mips::EXTRV_W_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: ac
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3) << 14;
      break;
    }
    case Mips::BGEZALC:
    case Mips::BGEZC:
    case Mips::BGEZC64:
    case Mips::BLTZALC:
    case Mips::BLTZC:
    case Mips::BLTZC64: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      Value |= (op & 0x1f) << 16;
      // op: offset
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::BGEZC_MMR6:
    case Mips::BLTZC_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      Value |= (op & 0x1f) << 16;
      // op: offset
      op = getBranchTargetOpValueLsl2MMR6(MI, 1, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::BGEZALC_MMR6:
    case Mips::BLTZALC_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      Value |= (op & 0x1f) << 16;
      // op: offset
      op = getBranchTargetOpValueMM(MI, 1, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::LWSP_MM:
    case Mips::SWSP_MM:
    case Mips::SWSP_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: offset
      op = getMemEncodingMMSPImm5Lsl2(MI, 1, Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case Mips::NOT16_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 3;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case Mips::LBU16_MM:
    case Mips::SB16_MM:
    case Mips::SB16_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: addr
      op = getMemEncodingMMImm4(MI, 1, Fixups, STI);
      Value |= (op & 0x7f);
      break;
    }
    case Mips::LHU16_MM:
    case Mips::SH16_MM:
    case Mips::SH16_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: addr
      op = getMemEncodingMMImm4Lsl1(MI, 1, Fixups, STI);
      Value |= (op & 0x7f);
      break;
    }
    case Mips::LW16_MM:
    case Mips::SW16_MM:
    case Mips::SW16_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: addr
      op = getMemEncodingMMImm4Lsl2(MI, 1, Fixups, STI);
      Value |= (op & 0x7f);
      break;
    }
    case Mips::LWGP_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: offset
      op = getMemEncodingMMGPImm7Lsl2(MI, 1, Fixups, STI);
      Value |= (op & 0x7f);
      break;
    }
    case Mips::NOT16_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 4;
      break;
    }
    case Mips::SC64_R6:
    case Mips::SCD_R6:
    case Mips::SC_R6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: addr
      op = getMemEncoding(MI, 2, Fixups, STI);
      Value |= (op & 0x1f0000) << 5;
      Value |= (op & 0x1ff) << 7;
      break;
    }
    case Mips::SC:
    case Mips::SC64:
    case Mips::SCD: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: addr
      op = getMemEncoding(MI, 2, Fixups, STI);
      Value |= (op & 0x1f0000) << 5;
      Value |= (op & 0xffff);
      break;
    }
    case Mips::CTC1:
    case Mips::DMTC1:
    case Mips::MTC1:
    case Mips::MTC1_D64: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::DMTC0:
    case Mips::DMTC2:
    case Mips::DMTGC0:
    case Mips::MTC0:
    case Mips::MTC2:
    case Mips::MTGC0:
    case Mips::MTHGC0: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: sel
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case Mips::MFTR:
    case Mips::MTTR: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: u
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 5;
      // op: h
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1) << 4;
      // op: sel
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case Mips::SCE_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: addr
      op = getMemEncoding(MI, 2, Fixups, STI);
      Value |= (op & 0x1f0000);
      Value |= (op & 0x1ff);
      break;
    }
    case Mips::SC_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: addr
      op = getMemEncodingMMImm12(MI, 2, Fixups, STI);
      Value |= (op & 0x1f0000);
      Value |= (op & 0xfff);
      break;
    }
    case Mips::SC_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: addr
      op = getMemEncodingMMImm9(MI, 2, Fixups, STI);
      Value |= (op & 0x1f0000);
      Value |= (op & 0x1ff);
      break;
    }
    case Mips::CTC1_MM:
    case Mips::MTC1_D64_MM:
    case Mips::MTC1_MM:
    case Mips::MTC1_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::CTC2_MM:
    case Mips::MTC2_MMR6:
    case Mips::MTHC2_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: impl
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::CMPU_EQ_QB_MM:
    case Mips::CMPU_LE_QB_MM:
    case Mips::CMPU_LT_QB_MM:
    case Mips::CMP_EQ_PH_MM:
    case Mips::CMP_LE_PH_MM:
    case Mips::CMP_LT_PH_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::BEQC_MMR6:
    case Mips::BGEC_MMR6:
    case Mips::BGEUC_MMR6:
    case Mips::BLTC_MMR6:
    case Mips::BLTUC_MMR6:
    case Mips::BNEC_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: offset
      op = getBranchTargetOpValueLsl2MMR6(MI, 2, Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case Mips::MTC0_MMR6:
    case Mips::MTGC0_MM:
    case Mips::MTHC0_MMR6:
    case Mips::MTHGC0_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: sel
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 11;
      break;
    }
    case Mips::MTHC1_D32:
    case Mips::MTHC1_D64: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::SPLAT_B:
    case Mips::SPLAT_D:
    case Mips::SPLAT_H:
    case Mips::SPLAT_W: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::MTHC1_D32_MM:
    case Mips::MTHC1_D64_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: fs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::DPAQX_SA_W_PH_MMR2:
    case Mips::DPAQX_S_W_PH_MMR2:
    case Mips::DPAQ_SA_L_W_MM:
    case Mips::DPAQ_S_W_PH_MM:
    case Mips::DPAU_H_QBL_MM:
    case Mips::DPAU_H_QBR_MM:
    case Mips::DPAX_W_PH_MMR2:
    case Mips::DPA_W_PH_MMR2:
    case Mips::DPSQX_SA_W_PH_MMR2:
    case Mips::DPSQX_S_W_PH_MMR2:
    case Mips::DPSQ_SA_L_W_MM:
    case Mips::DPSQ_S_W_PH_MM:
    case Mips::DPSU_H_QBL_MM:
    case Mips::DPSU_H_QBR_MM:
    case Mips::DPSX_W_PH_MMR2:
    case Mips::DPS_W_PH_MMR2:
    case Mips::MADDU_DSP_MM:
    case Mips::MADD_DSP_MM:
    case Mips::MAQ_SA_W_PHL_MM:
    case Mips::MAQ_SA_W_PHR_MM:
    case Mips::MAQ_S_W_PHL_MM:
    case Mips::MAQ_S_W_PHR_MM:
    case Mips::MSUBU_DSP_MM:
    case Mips::MSUB_DSP_MM:
    case Mips::MULSAQ_S_W_PH_MM:
    case Mips::MULSA_W_PH_MMR2:
    case Mips::MULTU_DSP_MM:
    case Mips::MULT_DSP_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: ac
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3) << 14;
      break;
    }
    case Mips::ADD_MM:
    case Mips::ADDu_MM:
    case Mips::AND_MM:
    case Mips::CMPGU_EQ_QB_MM:
    case Mips::CMPGU_LE_QB_MM:
    case Mips::CMPGU_LT_QB_MM:
    case Mips::MOVN_I_MM:
    case Mips::MOVZ_I_MM:
    case Mips::MUL_MM:
    case Mips::NOR_MM:
    case Mips::OR_MM:
    case Mips::SLT_MM:
    case Mips::SLTu_MM:
    case Mips::SUB_MM:
    case Mips::SUBu_MM:
    case Mips::XOR_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      break;
    }
    case Mips::AND16_MM:
    case Mips::OR16_MM:
    case Mips::XOR16_MM: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 3;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case Mips::AND16_MMR6:
    case Mips::OR16_MMR6:
    case Mips::XOR16_MMR6: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 4;
      break;
    }
    case Mips::SLD_B:
    case Mips::SLD_D:
    case Mips::SLD_H:
    case Mips::SLD_W: {
      // op: rt
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::MOVEP_MMR6: {
      // op: rt
      op = getMovePRegSingleOpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 4;
      // op: rs
      op = getMovePRegSingleOpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x4) << 1;
      Value |= (op & 0x3);
      break;
    }
    case Mips::MOVEP_MM: {
      // op: rt
      op = getMovePRegSingleOpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 4;
      // op: rs
      op = getMovePRegSingleOpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 1;
      break;
    }
    case Mips::LWM32_MM:
    case Mips::SWM32_MM: {
      // op: rt
      op = getRegisterListOpValue(MI, 0, Fixups, STI);
      Value |= (op & 0x1f) << 21;
      // op: addr
      op = getMemEncodingMMImm12(MI, 1, Fixups, STI);
      Value |= (op & 0x1f0000);
      Value |= (op & 0xfff);
      break;
    }
    case Mips::LWM16_MM:
    case Mips::SWM16_MM: {
      // op: rt
      op = getRegisterListOpValue16(MI, 0, Fixups, STI);
      Value |= (op & 0x3) << 4;
      // op: addr
      op = getMemEncodingMMImm4sp(MI, 1, Fixups, STI);
      Value |= (op & 0xf);
      break;
    }
    case Mips::LWM16_MMR6:
    case Mips::SWM16_MMR6: {
      // op: rt
      op = getRegisterListOpValue16(MI, 0, Fixups, STI);
      Value |= (op & 0x3) << 8;
      // op: addr
      op = getMemEncodingMMImm4sp(MI, 1, Fixups, STI);
      Value |= (op & 0xf) << 4;
      break;
    }
    case Mips::JrcRx16:
    case Mips::JumpLinkReg16:
    case Mips::Mfhi16:
    case Mips::Mflo16:
    case Mips::SebRx16:
    case Mips::SehRx16: {
      // op: rx
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 8;
      break;
    }
    case Mips::BeqzRxImm16:
    case Mips::BnezRxImm16: {
      // op: rx
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 8;
      // op: imm8
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
      Value |= (op & 0xff);
      break;
    }
    case Mips::CmpiRxImm16:
    case Mips::LiRxImm16:
    case Mips::LwRxPcTcp16:
    case Mips::SltiRxImm16:
    case Mips::SltiuRxImm16: {
      // op: rx
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 8;
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xff);
      break;
    }
    case Mips::AddiuRxRxImm16: {
      // op: rx
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 8;
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xff);
      break;
    }
    case Mips::CmpRxRy16:
    case Mips::DivRxRy16:
    case Mips::DivuRxRy16:
    case Mips::NegRxRy16:
    case Mips::NotRxRy16:
    case Mips::SltRxRy16:
    case Mips::SltuRxRy16: {
      // op: rx
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 8;
      // op: ry
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case Mips::AndRxRxRy16:
    case Mips::OrRxRxRy16:
    case Mips::SllvRxRy16:
    case Mips::SravRxRy16:
    case Mips::SrlvRxRy16:
    case Mips::XorRxRxRy16: {
      // op: rx
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 8;
      // op: ry
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case Mips::AdduRxRyRz16:
    case Mips::SubuRxRyRz16: {
      // op: rx
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 8;
      // op: ry
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 5;
      // op: rz
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 2;
      break;
    }
    case Mips::MoveR3216: {
      // op: ry
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf) << 4;
      // op: r32
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf);
      break;
    }
    case Mips::LDI_B:
    case Mips::LDI_D:
    case Mips::LDI_H:
    case Mips::LDI_W: {
      // op: s10
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3ff) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::SllX16:
    case Mips::SraX16:
    case Mips::SrlX16: {
      // op: sa6
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 22;
      Value |= (op & 0x20) << 16;
      // op: rx
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 8;
      // op: ry
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case Mips::SHILO_MM: {
      // op: shift
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3f) << 16;
      // op: ac
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3) << 14;
      break;
    }
    case Mips::SYNC_MM:
    case Mips::SYNC_MMR6: {
      // op: stype
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::SYNC: {
      // op: stype
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::J:
    case Mips::JAL:
    case Mips::JALX:
    case Mips::JALX_MM: {
      // op: target
      op = getJumpTargetOpValue(MI, 0, Fixups, STI);
      Value |= (op & 0x3ffffff);
      break;
    }
    case Mips::JALS_MM:
    case Mips::JAL_MM:
    case Mips::J_MM: {
      // op: target
      op = getJumpTargetOpValueMM(MI, 0, Fixups, STI);
      Value |= (op & 0x3ffffff);
      break;
    }
    case Mips::ANDI_B:
    case Mips::NORI_B:
    case Mips::ORI_B:
    case Mips::SHF_B:
    case Mips::SHF_H:
    case Mips::SHF_W:
    case Mips::XORI_B: {
      // op: u8
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xff) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::BMNZI_B:
    case Mips::BMZI_B:
    case Mips::BSELI_B: {
      // op: u8
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xff) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::FCLASS_D:
    case Mips::FCLASS_W:
    case Mips::FEXUPL_D:
    case Mips::FEXUPL_W:
    case Mips::FEXUPR_D:
    case Mips::FEXUPR_W:
    case Mips::FFINT_S_D:
    case Mips::FFINT_S_W:
    case Mips::FFINT_U_D:
    case Mips::FFINT_U_W:
    case Mips::FFQL_D:
    case Mips::FFQL_W:
    case Mips::FFQR_D:
    case Mips::FFQR_W:
    case Mips::FLOG2_D:
    case Mips::FLOG2_W:
    case Mips::FRCP_D:
    case Mips::FRCP_W:
    case Mips::FRINT_D:
    case Mips::FRINT_W:
    case Mips::FRSQRT_D:
    case Mips::FRSQRT_W:
    case Mips::FSQRT_D:
    case Mips::FSQRT_W:
    case Mips::FTINT_S_D:
    case Mips::FTINT_S_W:
    case Mips::FTINT_U_D:
    case Mips::FTINT_U_W:
    case Mips::FTRUNC_S_D:
    case Mips::FTRUNC_S_W:
    case Mips::FTRUNC_U_D:
    case Mips::FTRUNC_U_W:
    case Mips::MOVE_V:
    case Mips::NLOC_B:
    case Mips::NLOC_D:
    case Mips::NLOC_H:
    case Mips::NLOC_W:
    case Mips::NLZC_B:
    case Mips::NLZC_D:
    case Mips::NLZC_H:
    case Mips::NLZC_W:
    case Mips::PCNT_B:
    case Mips::PCNT_D:
    case Mips::PCNT_H:
    case Mips::PCNT_W: {
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::BCLRI_W:
    case Mips::BNEGI_W:
    case Mips::BSETI_W:
    case Mips::SAT_S_W:
    case Mips::SAT_U_W:
    case Mips::SLLI_W:
    case Mips::SRAI_W:
    case Mips::SRARI_W:
    case Mips::SRLI_W:
    case Mips::SRLRI_W: {
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      // op: m
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::BCLRI_D:
    case Mips::BNEGI_D:
    case Mips::BSETI_D:
    case Mips::SAT_S_D:
    case Mips::SAT_U_D:
    case Mips::SLLI_D:
    case Mips::SRAI_D:
    case Mips::SRARI_D:
    case Mips::SRLI_D:
    case Mips::SRLRI_D: {
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      // op: m
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3f) << 16;
      break;
    }
    case Mips::BCLRI_B:
    case Mips::BNEGI_B:
    case Mips::BSETI_B:
    case Mips::SAT_S_B:
    case Mips::SAT_U_B:
    case Mips::SLLI_B:
    case Mips::SRAI_B:
    case Mips::SRARI_B:
    case Mips::SRLI_B:
    case Mips::SRLRI_B: {
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      // op: m
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 16;
      break;
    }
    case Mips::BCLRI_H:
    case Mips::BNEGI_H:
    case Mips::BSETI_H:
    case Mips::SAT_S_H:
    case Mips::SAT_U_H:
    case Mips::SLLI_H:
    case Mips::SRAI_H:
    case Mips::SRARI_H:
    case Mips::SRLI_H:
    case Mips::SRLRI_H: {
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      // op: m
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case Mips::BINSLI_W:
    case Mips::BINSRI_W: {
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      // op: m
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case Mips::BINSLI_D:
    case Mips::BINSRI_D: {
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      // op: m
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3f) << 16;
      break;
    }
    case Mips::BINSLI_B:
    case Mips::BINSRI_B: {
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      // op: m
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 16;
      break;
    }
    case Mips::BINSLI_H:
    case Mips::BINSRI_H: {
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      // op: m
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case Mips::ADDS_A_B:
    case Mips::ADDS_A_D:
    case Mips::ADDS_A_H:
    case Mips::ADDS_A_W:
    case Mips::ADDS_S_B:
    case Mips::ADDS_S_D:
    case Mips::ADDS_S_H:
    case Mips::ADDS_S_W:
    case Mips::ADDS_U_B:
    case Mips::ADDS_U_D:
    case Mips::ADDS_U_H:
    case Mips::ADDS_U_W:
    case Mips::ADDV_B:
    case Mips::ADDV_D:
    case Mips::ADDV_H:
    case Mips::ADDV_W:
    case Mips::ADD_A_B:
    case Mips::ADD_A_D:
    case Mips::ADD_A_H:
    case Mips::ADD_A_W:
    case Mips::AND_V:
    case Mips::ASUB_S_B:
    case Mips::ASUB_S_D:
    case Mips::ASUB_S_H:
    case Mips::ASUB_S_W:
    case Mips::ASUB_U_B:
    case Mips::ASUB_U_D:
    case Mips::ASUB_U_H:
    case Mips::ASUB_U_W:
    case Mips::AVER_S_B:
    case Mips::AVER_S_D:
    case Mips::AVER_S_H:
    case Mips::AVER_S_W:
    case Mips::AVER_U_B:
    case Mips::AVER_U_D:
    case Mips::AVER_U_H:
    case Mips::AVER_U_W:
    case Mips::AVE_S_B:
    case Mips::AVE_S_D:
    case Mips::AVE_S_H:
    case Mips::AVE_S_W:
    case Mips::AVE_U_B:
    case Mips::AVE_U_D:
    case Mips::AVE_U_H:
    case Mips::AVE_U_W:
    case Mips::BCLR_B:
    case Mips::BCLR_D:
    case Mips::BCLR_H:
    case Mips::BCLR_W:
    case Mips::BNEG_B:
    case Mips::BNEG_D:
    case Mips::BNEG_H:
    case Mips::BNEG_W:
    case Mips::BSET_B:
    case Mips::BSET_D:
    case Mips::BSET_H:
    case Mips::BSET_W:
    case Mips::CEQ_B:
    case Mips::CEQ_D:
    case Mips::CEQ_H:
    case Mips::CEQ_W:
    case Mips::CLE_S_B:
    case Mips::CLE_S_D:
    case Mips::CLE_S_H:
    case Mips::CLE_S_W:
    case Mips::CLE_U_B:
    case Mips::CLE_U_D:
    case Mips::CLE_U_H:
    case Mips::CLE_U_W:
    case Mips::CLT_S_B:
    case Mips::CLT_S_D:
    case Mips::CLT_S_H:
    case Mips::CLT_S_W:
    case Mips::CLT_U_B:
    case Mips::CLT_U_D:
    case Mips::CLT_U_H:
    case Mips::CLT_U_W:
    case Mips::DIV_S_B:
    case Mips::DIV_S_D:
    case Mips::DIV_S_H:
    case Mips::DIV_S_W:
    case Mips::DIV_U_B:
    case Mips::DIV_U_D:
    case Mips::DIV_U_H:
    case Mips::DIV_U_W:
    case Mips::DOTP_S_D:
    case Mips::DOTP_S_H:
    case Mips::DOTP_S_W:
    case Mips::DOTP_U_D:
    case Mips::DOTP_U_H:
    case Mips::DOTP_U_W:
    case Mips::FADD_D:
    case Mips::FADD_W:
    case Mips::FCAF_D:
    case Mips::FCAF_W:
    case Mips::FCEQ_D:
    case Mips::FCEQ_W:
    case Mips::FCLE_D:
    case Mips::FCLE_W:
    case Mips::FCLT_D:
    case Mips::FCLT_W:
    case Mips::FCNE_D:
    case Mips::FCNE_W:
    case Mips::FCOR_D:
    case Mips::FCOR_W:
    case Mips::FCUEQ_D:
    case Mips::FCUEQ_W:
    case Mips::FCULE_D:
    case Mips::FCULE_W:
    case Mips::FCULT_D:
    case Mips::FCULT_W:
    case Mips::FCUNE_D:
    case Mips::FCUNE_W:
    case Mips::FCUN_D:
    case Mips::FCUN_W:
    case Mips::FDIV_D:
    case Mips::FDIV_W:
    case Mips::FEXDO_H:
    case Mips::FEXDO_W:
    case Mips::FEXP2_D:
    case Mips::FEXP2_W:
    case Mips::FMAX_A_D:
    case Mips::FMAX_A_W:
    case Mips::FMAX_D:
    case Mips::FMAX_W:
    case Mips::FMIN_A_D:
    case Mips::FMIN_A_W:
    case Mips::FMIN_D:
    case Mips::FMIN_W:
    case Mips::FMUL_D:
    case Mips::FMUL_W:
    case Mips::FSAF_D:
    case Mips::FSAF_W:
    case Mips::FSEQ_D:
    case Mips::FSEQ_W:
    case Mips::FSLE_D:
    case Mips::FSLE_W:
    case Mips::FSLT_D:
    case Mips::FSLT_W:
    case Mips::FSNE_D:
    case Mips::FSNE_W:
    case Mips::FSOR_D:
    case Mips::FSOR_W:
    case Mips::FSUB_D:
    case Mips::FSUB_W:
    case Mips::FSUEQ_D:
    case Mips::FSUEQ_W:
    case Mips::FSULE_D:
    case Mips::FSULE_W:
    case Mips::FSULT_D:
    case Mips::FSULT_W:
    case Mips::FSUNE_D:
    case Mips::FSUNE_W:
    case Mips::FSUN_D:
    case Mips::FSUN_W:
    case Mips::FTQ_H:
    case Mips::FTQ_W:
    case Mips::HADD_S_D:
    case Mips::HADD_S_H:
    case Mips::HADD_S_W:
    case Mips::HADD_U_D:
    case Mips::HADD_U_H:
    case Mips::HADD_U_W:
    case Mips::HSUB_S_D:
    case Mips::HSUB_S_H:
    case Mips::HSUB_S_W:
    case Mips::HSUB_U_D:
    case Mips::HSUB_U_H:
    case Mips::HSUB_U_W:
    case Mips::ILVEV_B:
    case Mips::ILVEV_D:
    case Mips::ILVEV_H:
    case Mips::ILVEV_W:
    case Mips::ILVL_B:
    case Mips::ILVL_D:
    case Mips::ILVL_H:
    case Mips::ILVL_W:
    case Mips::ILVOD_B:
    case Mips::ILVOD_D:
    case Mips::ILVOD_H:
    case Mips::ILVOD_W:
    case Mips::ILVR_B:
    case Mips::ILVR_D:
    case Mips::ILVR_H:
    case Mips::ILVR_W:
    case Mips::MAX_A_B:
    case Mips::MAX_A_D:
    case Mips::MAX_A_H:
    case Mips::MAX_A_W:
    case Mips::MAX_S_B:
    case Mips::MAX_S_D:
    case Mips::MAX_S_H:
    case Mips::MAX_S_W:
    case Mips::MAX_U_B:
    case Mips::MAX_U_D:
    case Mips::MAX_U_H:
    case Mips::MAX_U_W:
    case Mips::MIN_A_B:
    case Mips::MIN_A_D:
    case Mips::MIN_A_H:
    case Mips::MIN_A_W:
    case Mips::MIN_S_B:
    case Mips::MIN_S_D:
    case Mips::MIN_S_H:
    case Mips::MIN_S_W:
    case Mips::MIN_U_B:
    case Mips::MIN_U_D:
    case Mips::MIN_U_H:
    case Mips::MIN_U_W:
    case Mips::MOD_S_B:
    case Mips::MOD_S_D:
    case Mips::MOD_S_H:
    case Mips::MOD_S_W:
    case Mips::MOD_U_B:
    case Mips::MOD_U_D:
    case Mips::MOD_U_H:
    case Mips::MOD_U_W:
    case Mips::MULR_Q_H:
    case Mips::MULR_Q_W:
    case Mips::MULV_B:
    case Mips::MULV_D:
    case Mips::MULV_H:
    case Mips::MULV_W:
    case Mips::MUL_Q_H:
    case Mips::MUL_Q_W:
    case Mips::NOR_V:
    case Mips::OR_V:
    case Mips::PCKEV_B:
    case Mips::PCKEV_D:
    case Mips::PCKEV_H:
    case Mips::PCKEV_W:
    case Mips::PCKOD_B:
    case Mips::PCKOD_D:
    case Mips::PCKOD_H:
    case Mips::PCKOD_W:
    case Mips::SLL_B:
    case Mips::SLL_D:
    case Mips::SLL_H:
    case Mips::SLL_W:
    case Mips::SRAR_B:
    case Mips::SRAR_D:
    case Mips::SRAR_H:
    case Mips::SRAR_W:
    case Mips::SRA_B:
    case Mips::SRA_D:
    case Mips::SRA_H:
    case Mips::SRA_W:
    case Mips::SRLR_B:
    case Mips::SRLR_D:
    case Mips::SRLR_H:
    case Mips::SRLR_W:
    case Mips::SRL_B:
    case Mips::SRL_D:
    case Mips::SRL_H:
    case Mips::SRL_W:
    case Mips::SUBSUS_U_B:
    case Mips::SUBSUS_U_D:
    case Mips::SUBSUS_U_H:
    case Mips::SUBSUS_U_W:
    case Mips::SUBSUU_S_B:
    case Mips::SUBSUU_S_D:
    case Mips::SUBSUU_S_H:
    case Mips::SUBSUU_S_W:
    case Mips::SUBS_S_B:
    case Mips::SUBS_S_D:
    case Mips::SUBS_S_H:
    case Mips::SUBS_S_W:
    case Mips::SUBS_U_B:
    case Mips::SUBS_U_D:
    case Mips::SUBS_U_H:
    case Mips::SUBS_U_W:
    case Mips::SUBV_B:
    case Mips::SUBV_D:
    case Mips::SUBV_H:
    case Mips::SUBV_W:
    case Mips::XOR_V: {
      // op: wt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
    case Mips::BINSL_B:
    case Mips::BINSL_D:
    case Mips::BINSL_H:
    case Mips::BINSL_W:
    case Mips::BINSR_B:
    case Mips::BINSR_D:
    case Mips::BINSR_H:
    case Mips::BINSR_W:
    case Mips::BMNZ_V:
    case Mips::BMZ_V:
    case Mips::BSEL_V:
    case Mips::DPADD_S_D:
    case Mips::DPADD_S_H:
    case Mips::DPADD_S_W:
    case Mips::DPADD_U_D:
    case Mips::DPADD_U_H:
    case Mips::DPADD_U_W:
    case Mips::DPSUB_S_D:
    case Mips::DPSUB_S_H:
    case Mips::DPSUB_S_W:
    case Mips::DPSUB_U_D:
    case Mips::DPSUB_U_H:
    case Mips::DPSUB_U_W:
    case Mips::FMADD_D:
    case Mips::FMADD_W:
    case Mips::FMSUB_D:
    case Mips::FMSUB_W:
    case Mips::MADDR_Q_H:
    case Mips::MADDR_Q_W:
    case Mips::MADDV_B:
    case Mips::MADDV_D:
    case Mips::MADDV_H:
    case Mips::MADDV_W:
    case Mips::MADD_Q_H:
    case Mips::MADD_Q_W:
    case Mips::MSUBR_Q_H:
    case Mips::MSUBR_Q_W:
    case Mips::MSUBV_B:
    case Mips::MSUBV_D:
    case Mips::MSUBV_H:
    case Mips::MSUBV_W:
    case Mips::MSUB_Q_H:
    case Mips::MSUB_Q_W:
    case Mips::VSHF_B:
    case Mips::VSHF_D:
    case Mips::VSHF_H:
    case Mips::VSHF_W: {
      // op: wt
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: ws
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 11;
      // op: wd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 6;
      break;
    }
  default:
    reportUnsupportedInst(MI);
  }
  return Value;
}

#ifdef GET_OPERAND_BIT_OFFSET
#undef GET_OPERAND_BIT_OFFSET

uint32_t MipsMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
    unsigned OpNum,
    const MCSubtargetInfo &STI) const {
  switch (MI.getOpcode()) {
    case Mips::Break16:
    case Mips::DERET:
    case Mips::DERET_MM:
    case Mips::DERET_MMR6:
    case Mips::EHB:
    case Mips::EHB_MM:
    case Mips::EHB_MMR6:
    case Mips::ERET:
    case Mips::ERETNC:
    case Mips::ERETNC_MMR6:
    case Mips::ERET_MM:
    case Mips::ERET_MMR6:
    case Mips::JrRa16:
    case Mips::JrcRa16:
    case Mips::NAL:
    case Mips::PAUSE:
    case Mips::PAUSE_MM:
    case Mips::PAUSE_MMR6:
    case Mips::Restore16:
    case Mips::RestoreX16:
    case Mips::SSNOP:
    case Mips::SSNOP_MM:
    case Mips::SSNOP_MMR6:
    case Mips::Save16:
    case Mips::SaveX16:
    case Mips::TLBGINV:
    case Mips::TLBGINVF:
    case Mips::TLBGINVF_MM:
    case Mips::TLBGINV_MM:
    case Mips::TLBGP:
    case Mips::TLBGP_MM:
    case Mips::TLBGR:
    case Mips::TLBGR_MM:
    case Mips::TLBGWI:
    case Mips::TLBGWI_MM:
    case Mips::TLBGWR:
    case Mips::TLBGWR_MM:
    case Mips::TLBINV:
    case Mips::TLBINVF:
    case Mips::TLBINVF_MMR6:
    case Mips::TLBINV_MMR6:
    case Mips::TLBP:
    case Mips::TLBP_MM:
    case Mips::TLBR:
    case Mips::TLBR_MM:
    case Mips::TLBWI:
    case Mips::TLBWI_MM:
    case Mips::TLBWR:
    case Mips::TLBWR_MM:
    case Mips::WAIT: {
      break;
    }
    case Mips::DPAQX_SA_W_PH:
    case Mips::DPAQX_S_W_PH:
    case Mips::DPAQ_SA_L_W:
    case Mips::DPAQ_S_W_PH:
    case Mips::DPAU_H_QBL:
    case Mips::DPAU_H_QBR:
    case Mips::DPAX_W_PH:
    case Mips::DPA_W_PH:
    case Mips::DPSQX_SA_W_PH:
    case Mips::DPSQX_S_W_PH:
    case Mips::DPSQ_SA_L_W:
    case Mips::DPSQ_S_W_PH:
    case Mips::DPSU_H_QBL:
    case Mips::DPSU_H_QBR:
    case Mips::DPSX_W_PH:
    case Mips::DPS_W_PH:
    case Mips::MADDU_DSP:
    case Mips::MADD_DSP:
    case Mips::MAQ_SA_W_PHL:
    case Mips::MAQ_SA_W_PHR:
    case Mips::MAQ_S_W_PHL:
    case Mips::MAQ_S_W_PHR:
    case Mips::MSUBU_DSP:
    case Mips::MSUB_DSP:
    case Mips::MULSAQ_S_W_PH:
    case Mips::MULSA_W_PH:
    case Mips::MULTU_DSP:
    case Mips::MULT_DSP: {
      switch (OpNum) {
      case 0:
        // op: ac
        return 11;
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: rt
        return 16;
      }
      break;
    }
    case Mips::MTHLIP:
    case Mips::SHILOV: {
      switch (OpNum) {
      case 0:
        // op: ac
        return 11;
      case 1:
        // op: rs
        return 21;
      }
      break;
    }
    case Mips::SHILO: {
      switch (OpNum) {
      case 0:
        // op: ac
        return 11;
      case 1:
        // op: shift
        return 20;
      }
      break;
    }
    case Mips::CACHE:
    case Mips::PREF: {
      switch (OpNum) {
      case 0:
        // op: addr
        return 0;
      case 2:
        // op: hint
        return 16;
      }
      break;
    }
    case Mips::CACHEE_MM:
    case Mips::CACHE_MM:
    case Mips::CACHE_MMR6:
    case Mips::PREFE_MM:
    case Mips::PREF_MM:
    case Mips::PREF_MMR6: {
      switch (OpNum) {
      case 0:
        // op: addr
        return 0;
      case 2:
        // op: hint
        return 21;
      }
      break;
    }
    case Mips::SYNCI:
    case Mips::SYNCI_MM:
    case Mips::SYNCI_MMR6: {
      switch (OpNum) {
      case 0:
        // op: addr
        return 0;
      }
      break;
    }
    case Mips::CACHEE:
    case Mips::CACHE_R6:
    case Mips::PREFE:
    case Mips::PREF_R6: {
      switch (OpNum) {
      case 0:
        // op: addr
        return 7;
      case 2:
        // op: hint
        return 16;
      }
      break;
    }
    case Mips::BREAK16_MM:
    case Mips::SDBBP16_MM:
    case Mips::SIGRIE: {
      switch (OpNum) {
      case 0:
        // op: code_
        return 0;
      }
      break;
    }
    case Mips::HYPCALL: {
      switch (OpNum) {
      case 0:
        // op: code_
        return 11;
      }
      break;
    }
    case Mips::HYPCALL_MM:
    case Mips::SDBBP_MM:
    case Mips::SDBBP_MMR6:
    case Mips::SYSCALL_MM:
    case Mips::WAIT_MM:
    case Mips::WAIT_MMR6: {
      switch (OpNum) {
      case 0:
        // op: code_
        return 16;
      }
      break;
    }
    case Mips::BREAK16_MMR6:
    case Mips::SDBBP:
    case Mips::SDBBP16_MMR6:
    case Mips::SDBBP_R6:
    case Mips::SIGRIE_MMR6:
    case Mips::SYSCALL: {
      switch (OpNum) {
      case 0:
        // op: code_
        return 6;
      }
      break;
    }
    case Mips::BREAK:
    case Mips::BREAK_MM:
    case Mips::BREAK_MMR6: {
      switch (OpNum) {
      case 0:
        // op: code_1
        return 16;
      case 1:
        // op: code_2
        return 6;
      }
      break;
    }
    case Mips::BC2EQZ:
    case Mips::BC2NEZ: {
      switch (OpNum) {
      case 0:
        // op: ct
        return 16;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::BC1F:
    case Mips::BC1FL:
    case Mips::BC1F_MM:
    case Mips::BC1T:
    case Mips::BC1TL:
    case Mips::BC1T_MM: {
      switch (OpNum) {
      case 0:
        // op: fcc
        return 18;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::LUXC1_MM:
    case Mips::LWXC1_MM: {
      switch (OpNum) {
      case 0:
        // op: fd
        return 11;
      case 1:
        // op: base
        return 16;
      case 2:
        // op: index
        return 21;
      }
      break;
    }
    case Mips::MOVN_I_D32_MM:
    case Mips::MOVN_I_S_MM:
    case Mips::MOVZ_I_D32_MM:
    case Mips::MOVZ_I_S_MM: {
      switch (OpNum) {
      case 0:
        // op: fd
        return 11;
      case 1:
        // op: fs
        return 16;
      case 2:
        // op: rt
        return 21;
      }
      break;
    }
    case Mips::MOVF_D32_MM:
    case Mips::MOVF_S_MM:
    case Mips::MOVT_D32_MM:
    case Mips::MOVT_S_MM: {
      switch (OpNum) {
      case 0:
        // op: fd
        return 21;
      case 1:
        // op: fs
        return 16;
      case 2:
        // op: fcc
        return 13;
      }
      break;
    }
    case Mips::CEIL_W_MM:
    case Mips::CEIL_W_S_MM:
    case Mips::CVT_D32_S_MM:
    case Mips::CVT_D32_W_MM:
    case Mips::CVT_D64_S_MM:
    case Mips::CVT_D64_W_MM:
    case Mips::CVT_L_D64_MM:
    case Mips::CVT_L_S_MM:
    case Mips::CVT_S_D32_MM:
    case Mips::CVT_S_D64_MM:
    case Mips::CVT_S_W_MM:
    case Mips::CVT_W_D32_MM:
    case Mips::CVT_W_D64_MM:
    case Mips::CVT_W_S_MM:
    case Mips::FABS_D32_MM:
    case Mips::FABS_D64_MM:
    case Mips::FABS_S_MM:
    case Mips::FLOOR_W_MM:
    case Mips::FLOOR_W_S_MM:
    case Mips::FMOV_D32_MM:
    case Mips::FMOV_D64_MM:
    case Mips::FMOV_S_MM:
    case Mips::FNEG_D32_MM:
    case Mips::FNEG_D64_MM:
    case Mips::FNEG_S_MM:
    case Mips::FSQRT_D32_MM:
    case Mips::FSQRT_D64_MM:
    case Mips::FSQRT_S_MM:
    case Mips::RECIP_D32_MM:
    case Mips::RECIP_D64_MM:
    case Mips::RECIP_S_MM:
    case Mips::ROUND_W_MM:
    case Mips::ROUND_W_S_MM:
    case Mips::RSQRT_D32_MM:
    case Mips::RSQRT_D64_MM:
    case Mips::RSQRT_S_MM:
    case Mips::TRUNC_W_MM:
    case Mips::TRUNC_W_S_MM: {
      switch (OpNum) {
      case 0:
        // op: fd
        return 21;
      case 1:
        // op: fs
        return 16;
      }
      break;
    }
    case Mips::LDXC1:
    case Mips::LDXC164:
    case Mips::LUXC1:
    case Mips::LUXC164:
    case Mips::LWXC1: {
      switch (OpNum) {
      case 0:
        // op: fd
        return 6;
      case 1:
        // op: base
        return 21;
      case 2:
        // op: index
        return 16;
      }
      break;
    }
    case Mips::MADD_D32:
    case Mips::MADD_D64:
    case Mips::MADD_S:
    case Mips::MSUB_D32:
    case Mips::MSUB_D64:
    case Mips::MSUB_S:
    case Mips::NMADD_D32:
    case Mips::NMADD_D64:
    case Mips::NMADD_S:
    case Mips::NMSUB_D32:
    case Mips::NMSUB_D64:
    case Mips::NMSUB_S: {
      switch (OpNum) {
      case 0:
        // op: fd
        return 6;
      case 1:
        // op: fr
        return 21;
      case 2:
        // op: fs
        return 11;
      case 3:
        // op: ft
        return 16;
      }
      break;
    }
    case Mips::MOVF_D32:
    case Mips::MOVF_D64:
    case Mips::MOVF_S:
    case Mips::MOVT_D32:
    case Mips::MOVT_D64:
    case Mips::MOVT_S: {
      switch (OpNum) {
      case 0:
        // op: fd
        return 6;
      case 1:
        // op: fs
        return 11;
      case 2:
        // op: fcc
        return 18;
      }
      break;
    }
    case Mips::ADDR_PS64:
    case Mips::CMP_EQ_D:
    case Mips::CMP_EQ_S:
    case Mips::CMP_F_D:
    case Mips::CMP_F_S:
    case Mips::CMP_LE_D:
    case Mips::CMP_LE_S:
    case Mips::CMP_LT_D:
    case Mips::CMP_LT_S:
    case Mips::CMP_SAF_D:
    case Mips::CMP_SAF_S:
    case Mips::CMP_SEQ_D:
    case Mips::CMP_SEQ_S:
    case Mips::CMP_SLE_D:
    case Mips::CMP_SLE_S:
    case Mips::CMP_SLT_D:
    case Mips::CMP_SLT_S:
    case Mips::CMP_SUEQ_D:
    case Mips::CMP_SUEQ_S:
    case Mips::CMP_SULE_D:
    case Mips::CMP_SULE_S:
    case Mips::CMP_SULT_D:
    case Mips::CMP_SULT_S:
    case Mips::CMP_SUN_D:
    case Mips::CMP_SUN_S:
    case Mips::CMP_UEQ_D:
    case Mips::CMP_UEQ_S:
    case Mips::CMP_ULE_D:
    case Mips::CMP_ULE_S:
    case Mips::CMP_ULT_D:
    case Mips::CMP_ULT_S:
    case Mips::CMP_UN_D:
    case Mips::CMP_UN_S:
    case Mips::CVT_PS_S64:
    case Mips::FADD_D32:
    case Mips::FADD_D64:
    case Mips::FADD_PS64:
    case Mips::FADD_S:
    case Mips::FDIV_D32:
    case Mips::FDIV_D64:
    case Mips::FDIV_S:
    case Mips::FMUL_D32:
    case Mips::FMUL_D64:
    case Mips::FMUL_PS64:
    case Mips::FMUL_S:
    case Mips::FSUB_D32:
    case Mips::FSUB_D64:
    case Mips::FSUB_PS64:
    case Mips::FSUB_S:
    case Mips::MULR_PS64:
    case Mips::PLL_PS64:
    case Mips::PLU_PS64:
    case Mips::PUL_PS64:
    case Mips::PUU_PS64: {
      switch (OpNum) {
      case 0:
        // op: fd
        return 6;
      case 1:
        // op: fs
        return 11;
      case 2:
        // op: ft
        return 16;
      }
      break;
    }
    case Mips::MOVN_I64_D64:
    case Mips::MOVN_I64_S:
    case Mips::MOVN_I_D32:
    case Mips::MOVN_I_D64:
    case Mips::MOVN_I_S:
    case Mips::MOVZ_I64_D64:
    case Mips::MOVZ_I64_S:
    case Mips::MOVZ_I_D32:
    case Mips::MOVZ_I_D64:
    case Mips::MOVZ_I_S: {
      switch (OpNum) {
      case 0:
        // op: fd
        return 6;
      case 1:
        // op: fs
        return 11;
      case 2:
        // op: rt
        return 16;
      }
      break;
    }
    case Mips::CEIL_L_D64:
    case Mips::CEIL_L_S:
    case Mips::CEIL_W_D32:
    case Mips::CEIL_W_D64:
    case Mips::CEIL_W_S:
    case Mips::CVT_D32_S:
    case Mips::CVT_D32_W:
    case Mips::CVT_D64_L:
    case Mips::CVT_D64_S:
    case Mips::CVT_D64_W:
    case Mips::CVT_L_D64:
    case Mips::CVT_L_S:
    case Mips::CVT_PS_PW64:
    case Mips::CVT_PW_PS64:
    case Mips::CVT_S_D32:
    case Mips::CVT_S_D64:
    case Mips::CVT_S_L:
    case Mips::CVT_S_PL64:
    case Mips::CVT_S_PU64:
    case Mips::CVT_S_W:
    case Mips::CVT_W_D32:
    case Mips::CVT_W_D64:
    case Mips::CVT_W_S:
    case Mips::FABS_D32:
    case Mips::FABS_D64:
    case Mips::FABS_S:
    case Mips::FLOOR_L_D64:
    case Mips::FLOOR_L_S:
    case Mips::FLOOR_W_D32:
    case Mips::FLOOR_W_D64:
    case Mips::FLOOR_W_S:
    case Mips::FMOV_D32:
    case Mips::FMOV_D64:
    case Mips::FMOV_S:
    case Mips::FNEG_D32:
    case Mips::FNEG_D64:
    case Mips::FNEG_S:
    case Mips::FSQRT_D32:
    case Mips::FSQRT_D64:
    case Mips::FSQRT_S:
    case Mips::RECIP_D32:
    case Mips::RECIP_D64:
    case Mips::RECIP_S:
    case Mips::ROUND_L_D64:
    case Mips::ROUND_L_S:
    case Mips::ROUND_W_D32:
    case Mips::ROUND_W_D64:
    case Mips::ROUND_W_S:
    case Mips::RSQRT_D32:
    case Mips::RSQRT_D64:
    case Mips::RSQRT_S:
    case Mips::TRUNC_L_D64:
    case Mips::TRUNC_L_S:
    case Mips::TRUNC_W_D32:
    case Mips::TRUNC_W_D64:
    case Mips::TRUNC_W_S: {
      switch (OpNum) {
      case 0:
        // op: fd
        return 6;
      case 1:
        // op: fs
        return 11;
      }
      break;
    }
    case Mips::SUXC1_MM:
    case Mips::SWXC1_MM: {
      switch (OpNum) {
      case 0:
        // op: fs
        return 11;
      case 1:
        // op: base
        return 16;
      case 2:
        // op: index
        return 21;
      }
      break;
    }
    case Mips::SDXC1:
    case Mips::SDXC164:
    case Mips::SUXC1:
    case Mips::SUXC164:
    case Mips::SWXC1: {
      switch (OpNum) {
      case 0:
        // op: fs
        return 11;
      case 1:
        // op: base
        return 21;
      case 2:
        // op: index
        return 16;
      }
      break;
    }
    case Mips::FCMP_D32:
    case Mips::FCMP_D64:
    case Mips::FCMP_S32: {
      switch (OpNum) {
      case 0:
        // op: fs
        return 11;
      case 1:
        // op: ft
        return 16;
      case 2:
        // op: cond
        return 0;
      }
      break;
    }
    case Mips::FCMP_D32_MM:
    case Mips::FCMP_S32_MM: {
      switch (OpNum) {
      case 0:
        // op: fs
        return 16;
      case 1:
        // op: ft
        return 21;
      case 2:
        // op: cond
        return 6;
      }
      break;
    }
    case Mips::BC1EQZ:
    case Mips::BC1NEZ: {
      switch (OpNum) {
      case 0:
        // op: ft
        return 16;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::LDC1_D64_MMR6:
    case Mips::SDC1_D64_MMR6: {
      switch (OpNum) {
      case 0:
        // op: ft
        return 21;
      case 1:
        // op: addr
        return 0;
      }
      break;
    }
    case Mips::CEIL_L_D_MMR6:
    case Mips::CEIL_L_S_MMR6:
    case Mips::CEIL_W_D_MMR6:
    case Mips::CEIL_W_S_MMR6:
    case Mips::CVT_D_L_MMR6:
    case Mips::CVT_L_D_MMR6:
    case Mips::CVT_L_S_MMR6:
    case Mips::CVT_S_L_MMR6:
    case Mips::CVT_S_W_MMR6:
    case Mips::CVT_W_S_MMR6:
    case Mips::FLOOR_L_D_MMR6:
    case Mips::FLOOR_L_S_MMR6:
    case Mips::FLOOR_W_D_MMR6:
    case Mips::FLOOR_W_S_MMR6:
    case Mips::FMOV_D_MMR6:
    case Mips::FMOV_S_MMR6:
    case Mips::FNEG_S_MMR6:
    case Mips::ROUND_L_D_MMR6:
    case Mips::ROUND_L_S_MMR6:
    case Mips::ROUND_W_D_MMR6:
    case Mips::ROUND_W_S_MMR6:
    case Mips::TRUNC_L_D_MMR6:
    case Mips::TRUNC_L_S_MMR6:
    case Mips::TRUNC_W_D_MMR6:
    case Mips::TRUNC_W_S_MMR6: {
      switch (OpNum) {
      case 0:
        // op: ft
        return 21;
      case 1:
        // op: fs
        return 16;
      }
      break;
    }
    case Mips::JRADDIUSP: {
      switch (OpNum) {
      case 0:
        // op: imm
        return 0;
      }
      break;
    }
    case Mips::ADDIUSP_MM: {
      switch (OpNum) {
      case 0:
        // op: imm
        return 1;
      }
      break;
    }
    case Mips::JRCADDIUSP_MMR6: {
      switch (OpNum) {
      case 0:
        // op: imm
        return 5;
      }
      break;
    }
    case Mips::Bimm16: {
      switch (OpNum) {
      case 0:
        // op: imm11
        return 0;
      }
      break;
    }
    case Mips::AddiuSpImmX16:
    case Mips::BimmX16:
    case Mips::BteqzX16:
    case Mips::BtnezX16: {
      switch (OpNum) {
      case 0:
        // op: imm16
        return 0;
      }
      break;
    }
    case Mips::Jal16:
    case Mips::JalB16: {
      switch (OpNum) {
      case 0:
        // op: imm26
        return 0;
      }
      break;
    }
    case Mips::AddiuSpImm16:
    case Mips::Bteqz16:
    case Mips::Btnez16: {
      switch (OpNum) {
      case 0:
        // op: imm8
        return 0;
      }
      break;
    }
    case Mips::B16_MM:
    case Mips::BAL:
    case Mips::BALC:
    case Mips::BALC_MMR6:
    case Mips::BC:
    case Mips::BC16_MMR6:
    case Mips::BC_MMR6:
    case Mips::BPOSGE32:
    case Mips::BPOSGE32C_MMR3:
    case Mips::BPOSGE32_MM: {
      switch (OpNum) {
      case 0:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::Move32R16: {
      switch (OpNum) {
      case 0:
        // op: r32
        return 3;
      case 1:
        // op: rz
        return 0;
      }
      break;
    }
    case Mips::MFHI16_MM:
    case Mips::MFLO16_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case Mips::MFHI_DSP:
    case Mips::MFLO_DSP: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: ac
        return 21;
      }
      break;
    }
    case Mips::LWXS_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: base
        return 16;
      case 2:
        // op: index
        return 21;
      }
      break;
    }
    case Mips::LBUX:
    case Mips::LHX:
    case Mips::LWX: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: base
        return 21;
      case 2:
        // op: index
        return 16;
      }
      break;
    }
    case Mips::REPL_PH:
    case Mips::REPL_PH_MM:
    case Mips::REPL_QB: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: imm
        return 16;
      }
      break;
    }
    case Mips::RDDSP: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: mask
        return 16;
      }
      break;
    }
    case Mips::LSA_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: rt
        return 21;
      case 3:
        // op: imm2
        return 9;
      }
      break;
    }
    case Mips::ADDQH_PH_MMR2:
    case Mips::ADDQH_R_PH_MMR2:
    case Mips::ADDQH_R_W_MMR2:
    case Mips::ADDQH_W_MMR2:
    case Mips::ADDQ_PH_MM:
    case Mips::ADDQ_S_PH_MM:
    case Mips::ADDQ_S_W_MM:
    case Mips::ADDSC_MM:
    case Mips::ADDUH_QB_MMR2:
    case Mips::ADDUH_R_QB_MMR2:
    case Mips::ADDU_PH_MMR2:
    case Mips::ADDU_QB_MM:
    case Mips::ADDU_S_PH_MMR2:
    case Mips::ADDU_S_QB_MM:
    case Mips::ADDWC_MM:
    case Mips::CMPGDU_EQ_QB_MMR2:
    case Mips::CMPGDU_LE_QB_MMR2:
    case Mips::CMPGDU_LT_QB_MMR2:
    case Mips::MODSUB_MM:
    case Mips::MULEQ_S_W_PHL_MM:
    case Mips::MULEQ_S_W_PHR_MM:
    case Mips::MULEU_S_PH_QBL_MM:
    case Mips::MULEU_S_PH_QBR_MM:
    case Mips::MULQ_RS_PH_MM:
    case Mips::MULQ_RS_W_MMR2:
    case Mips::MULQ_S_PH_MMR2:
    case Mips::MULQ_S_W_MMR2:
    case Mips::MUL_PH_MMR2:
    case Mips::MUL_S_PH_MMR2:
    case Mips::PACKRL_PH_MM:
    case Mips::PICK_PH_MM:
    case Mips::PICK_QB_MM:
    case Mips::PRECRQU_S_QB_PH_MM:
    case Mips::PRECRQ_PH_W_MM:
    case Mips::PRECRQ_QB_PH_MM:
    case Mips::PRECRQ_RS_PH_W_MM:
    case Mips::PRECR_QB_PH_MMR2:
    case Mips::SELEQZ_MMR6:
    case Mips::SELNEZ_MMR6:
    case Mips::SUBQH_PH_MMR2:
    case Mips::SUBQH_R_PH_MMR2:
    case Mips::SUBQH_R_W_MMR2:
    case Mips::SUBQH_W_MMR2:
    case Mips::SUBQ_PH_MM:
    case Mips::SUBQ_S_PH_MM:
    case Mips::SUBQ_S_W_MM:
    case Mips::SUBUH_QB_MMR2:
    case Mips::SUBUH_R_QB_MMR2:
    case Mips::SUBU_PH_MMR2:
    case Mips::SUBU_QB_MM:
    case Mips::SUBU_S_PH_MMR2:
    case Mips::SUBU_S_QB_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: rt
        return 21;
      }
      break;
    }
    case Mips::MOVF_I:
    case Mips::MOVF_I64:
    case Mips::MOVT_I:
    case Mips::MOVT_I64: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: fcc
        return 18;
      }
      break;
    }
    case Mips::ALIGN:
    case Mips::DALIGN: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: rt
        return 16;
      case 3:
        // op: bp
        return 6;
      }
      break;
    }
    case Mips::ALIGN_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: rt
        return 16;
      case 3:
        // op: bp
        return 9;
      }
      break;
    }
    case Mips::DLSA_R6:
    case Mips::LSA_R6: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: rt
        return 16;
      case 3:
        // op: imm2
        return 6;
      }
      break;
    }
    case Mips::ADD:
    case Mips::ADDQH_PH:
    case Mips::ADDQH_R_PH:
    case Mips::ADDQH_R_W:
    case Mips::ADDQH_W:
    case Mips::ADDQ_PH:
    case Mips::ADDQ_S_PH:
    case Mips::ADDQ_S_W:
    case Mips::ADDSC:
    case Mips::ADDUH_QB:
    case Mips::ADDUH_R_QB:
    case Mips::ADDU_PH:
    case Mips::ADDU_QB:
    case Mips::ADDU_S_PH:
    case Mips::ADDU_S_QB:
    case Mips::ADDWC:
    case Mips::ADDu:
    case Mips::AND:
    case Mips::AND64:
    case Mips::BADDu:
    case Mips::DADD:
    case Mips::DADDu:
    case Mips::DDIV:
    case Mips::DDIVU:
    case Mips::DIV:
    case Mips::DIVU:
    case Mips::DMOD:
    case Mips::DMODU:
    case Mips::DMUH:
    case Mips::DMUHU:
    case Mips::DMUL:
    case Mips::DMULU:
    case Mips::DMUL_R6:
    case Mips::DSUB:
    case Mips::DSUBu:
    case Mips::MOD:
    case Mips::MODSUB:
    case Mips::MODU:
    case Mips::MOVN_I64_I:
    case Mips::MOVN_I64_I64:
    case Mips::MOVN_I_I:
    case Mips::MOVN_I_I64:
    case Mips::MOVZ_I64_I:
    case Mips::MOVZ_I64_I64:
    case Mips::MOVZ_I_I:
    case Mips::MOVZ_I_I64:
    case Mips::MUH:
    case Mips::MUHU:
    case Mips::MUL:
    case Mips::MULEQ_S_W_PHL:
    case Mips::MULEQ_S_W_PHR:
    case Mips::MULEU_S_PH_QBL:
    case Mips::MULEU_S_PH_QBR:
    case Mips::MULQ_RS_PH:
    case Mips::MULQ_RS_W:
    case Mips::MULQ_S_PH:
    case Mips::MULQ_S_W:
    case Mips::MULU:
    case Mips::MUL_PH:
    case Mips::MUL_R6:
    case Mips::MUL_S_PH:
    case Mips::NOR:
    case Mips::NOR64:
    case Mips::OR:
    case Mips::OR64:
    case Mips::SELEQZ:
    case Mips::SELEQZ64:
    case Mips::SELNEZ:
    case Mips::SELNEZ64:
    case Mips::SEQ:
    case Mips::SLT:
    case Mips::SLT64:
    case Mips::SLTu:
    case Mips::SLTu64:
    case Mips::SNE:
    case Mips::SUB:
    case Mips::SUBQH_PH:
    case Mips::SUBQH_R_PH:
    case Mips::SUBQH_R_W:
    case Mips::SUBQH_W:
    case Mips::SUBQ_PH:
    case Mips::SUBQ_S_PH:
    case Mips::SUBQ_S_W:
    case Mips::SUBUH_QB:
    case Mips::SUBUH_R_QB:
    case Mips::SUBU_PH:
    case Mips::SUBU_QB:
    case Mips::SUBU_S_PH:
    case Mips::SUBU_S_QB:
    case Mips::SUBu:
    case Mips::V3MULU:
    case Mips::VMM0:
    case Mips::VMULU:
    case Mips::XOR:
    case Mips::XOR64: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: rt
        return 16;
      }
      break;
    }
    case Mips::CLO:
    case Mips::CLO_R6:
    case Mips::CLZ:
    case Mips::CLZ_R6:
    case Mips::DCLO:
    case Mips::DCLO_R6:
    case Mips::DCLZ:
    case Mips::DCLZ_R6:
    case Mips::DPOP:
    case Mips::JALR:
    case Mips::JALR64:
    case Mips::JALR_HB:
    case Mips::JALR_HB64:
    case Mips::POP:
    case Mips::RADDU_W_QB: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rs
        return 21;
      }
      break;
    }
    case Mips::DROTRV:
    case Mips::DSLLV:
    case Mips::DSRAV:
    case Mips::DSRLV:
    case Mips::ROTRV:
    case Mips::SLLV:
    case Mips::SRAV:
    case Mips::SRLV: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rt
        return 16;
      case 2:
        // op: rs
        return 21;
      }
      break;
    }
    case Mips::SHLLV_PH:
    case Mips::SHLLV_QB:
    case Mips::SHLLV_S_PH:
    case Mips::SHLLV_S_W:
    case Mips::SHLL_PH:
    case Mips::SHLL_QB:
    case Mips::SHLL_S_PH:
    case Mips::SHLL_S_W:
    case Mips::SHRAV_PH:
    case Mips::SHRAV_QB:
    case Mips::SHRAV_R_PH:
    case Mips::SHRAV_R_QB:
    case Mips::SHRAV_R_W:
    case Mips::SHRA_PH:
    case Mips::SHRA_QB:
    case Mips::SHRA_R_PH:
    case Mips::SHRA_R_QB:
    case Mips::SHRA_R_W:
    case Mips::SHRLV_PH:
    case Mips::SHRLV_QB:
    case Mips::SHRL_PH:
    case Mips::SHRL_QB: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rt
        return 16;
      case 2:
        // op: rs_sa
        return 21;
      }
      break;
    }
    case Mips::DROTR:
    case Mips::DROTR32:
    case Mips::DSLL:
    case Mips::DSLL32:
    case Mips::DSRA:
    case Mips::DSRA32:
    case Mips::DSRL:
    case Mips::DSRL32:
    case Mips::ROTR:
    case Mips::SLL:
    case Mips::SRA:
    case Mips::SRL: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rt
        return 16;
      case 2:
        // op: shamt
        return 6;
      }
      break;
    }
    case Mips::ABSQ_S_PH:
    case Mips::ABSQ_S_QB:
    case Mips::ABSQ_S_W:
    case Mips::BITREV:
    case Mips::BITSWAP:
    case Mips::DBITSWAP:
    case Mips::DSBH:
    case Mips::DSHD:
    case Mips::DSLL64_32:
    case Mips::PRECEQU_PH_QBL:
    case Mips::PRECEQU_PH_QBLA:
    case Mips::PRECEQU_PH_QBR:
    case Mips::PRECEQU_PH_QBRA:
    case Mips::PRECEQ_W_PHL:
    case Mips::PRECEQ_W_PHR:
    case Mips::PRECEU_PH_QBL:
    case Mips::PRECEU_PH_QBLA:
    case Mips::PRECEU_PH_QBR:
    case Mips::PRECEU_PH_QBRA:
    case Mips::REPLV_PH:
    case Mips::REPLV_QB:
    case Mips::SEB:
    case Mips::SEB64:
    case Mips::SEH:
    case Mips::SEH64:
    case Mips::SLL64_32:
    case Mips::SLL64_64:
    case Mips::WSBH: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rt
        return 16;
      }
      break;
    }
    case Mips::ROTRV_MM:
    case Mips::SLLV_MM:
    case Mips::SRAV_MM:
    case Mips::SRLV_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rt
        return 21;
      case 2:
        // op: rs
        return 16;
      }
      break;
    }
    case Mips::SHLLV_PH_MM:
    case Mips::SHLLV_QB_MM:
    case Mips::SHLLV_S_PH_MM:
    case Mips::SHLLV_S_W_MM:
    case Mips::SHRAV_PH_MM:
    case Mips::SHRAV_QB_MMR2:
    case Mips::SHRAV_R_PH_MM:
    case Mips::SHRAV_R_QB_MMR2:
    case Mips::SHRAV_R_W_MM:
    case Mips::SHRLV_PH_MMR2:
    case Mips::SHRLV_QB_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 2:
        // op: rs
        return 16;
      case 1:
        // op: rt
        return 21;
      }
      break;
    }
    case Mips::ADDU_MMR6:
    case Mips::ADD_MMR6:
    case Mips::AND_MMR6:
    case Mips::DIVU_MMR6:
    case Mips::DIV_MMR6:
    case Mips::MODU_MMR6:
    case Mips::MOD_MMR6:
    case Mips::MUHU_MMR6:
    case Mips::MUH_MMR6:
    case Mips::MULU_MMR6:
    case Mips::MUL_MMR6:
    case Mips::NOR_MMR6:
    case Mips::OR_MMR6:
    case Mips::SUBU_MMR6:
    case Mips::SUB_MMR6:
    case Mips::XOR_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 2:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      }
      break;
    }
    case Mips::MFHI:
    case Mips::MFHI64:
    case Mips::MFLO:
    case Mips::MFLO64: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      }
      break;
    }
    case Mips::BITSWAP_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 16;
      case 1:
        // op: rt
        return 21;
      }
      break;
    }
    case Mips::MFHI_MM:
    case Mips::MFLO_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 16;
      }
      break;
    }
    case Mips::MOVF_I_MM:
    case Mips::MOVT_I_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 21;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: fcc
        return 13;
      }
      break;
    }
    case Mips::CLO_MM:
    case Mips::CLZ_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 21;
      case 1:
        // op: rs
        return 16;
      }
      break;
    }
    case Mips::ROTR_MM:
    case Mips::SLL_MM:
    case Mips::SLL_MMR6:
    case Mips::SRA_MM:
    case Mips::SRL_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 21;
      case 1:
        // op: rt
        return 16;
      case 2:
        // op: shamt
        return 11;
      }
      break;
    }
    case Mips::SEB_MM:
    case Mips::SEH_MM:
    case Mips::WSBH_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 21;
      case 1:
        // op: rt
        return 16;
      }
      break;
    }
    case Mips::CFCMSA: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 6;
      case 1:
        // op: cs
        return 11;
      }
      break;
    }
    case Mips::LI16_MM:
    case Mips::LI16_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 7;
      case 1:
        // op: imm
        return 0;
      }
      break;
    }
    case Mips::ADDIUR1SP_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 7;
      case 1:
        // op: imm
        return 1;
      }
      break;
    }
    case Mips::ANDI16_MM:
    case Mips::ANDI16_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 7;
      case 1:
        // op: rs
        return 4;
      case 2:
        // op: imm
        return 0;
      }
      break;
    }
    case Mips::ADDIUR2_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 7;
      case 1:
        // op: rs
        return 4;
      case 2:
        // op: imm
        return 1;
      }
      break;
    }
    case Mips::SLL16_MM:
    case Mips::SLL16_MMR6:
    case Mips::SRL16_MM:
    case Mips::SRL16_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 7;
      case 1:
        // op: rt
        return 4;
      case 2:
        // op: shamt
        return 1;
      }
      break;
    }
    case Mips::ADDU16_MM:
    case Mips::SUBU16_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 7;
      case 2:
        // op: rt
        return 4;
      case 1:
        // op: rs
        return 1;
      }
      break;
    }
    case Mips::JALR16_MM:
    case Mips::JALRS16_MM:
    case Mips::JR16_MM:
    case Mips::JRC16_MM: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 0;
      }
      break;
    }
    case Mips::MFHI_DSP_MM:
    case Mips::MFLO_DSP_MM: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 16;
      case 1:
        // op: ac
        return 14;
      }
      break;
    }
    case Mips::TEQI_MM:
    case Mips::TGEIU_MM:
    case Mips::TGEI_MM:
    case Mips::TLTIU_MM:
    case Mips::TLTI_MM:
    case Mips::TNEI_MM: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 16;
      case 1:
        // op: imm16
        return 0;
      }
      break;
    }
    case Mips::BEQZC_MM:
    case Mips::BGEZALS_MM:
    case Mips::BGEZAL_MM:
    case Mips::BGEZ_MM:
    case Mips::BGTZ_MM:
    case Mips::BLEZ_MM:
    case Mips::BLTZALS_MM:
    case Mips::BLTZAL_MM:
    case Mips::BLTZ_MM:
    case Mips::BNEZC_MM: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 16;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::TEQ_MM:
    case Mips::TGEU_MM:
    case Mips::TGE_MM:
    case Mips::TLTU_MM:
    case Mips::TLT_MM:
    case Mips::TNE_MM: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 16;
      case 1:
        // op: rt
        return 21;
      case 2:
        // op: code_
        return 12;
      }
      break;
    }
    case Mips::BEQ_MM:
    case Mips::BNE_MM: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 16;
      case 1:
        // op: rt
        return 21;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::MADDU_MM:
    case Mips::MADD_MM:
    case Mips::MSUBU_MM:
    case Mips::MSUB_MM:
    case Mips::MULT_MM:
    case Mips::MULTu_MM:
    case Mips::SDIV_MM:
    case Mips::UDIV_MM: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 16;
      case 1:
        // op: rt
        return 21;
      }
      break;
    }
    case Mips::GINVT_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 16;
      case 1:
        // op: type
        return 9;
      }
      break;
    }
    case Mips::DVP_MMR6:
    case Mips::EVP_MMR6:
    case Mips::GINVI_MMR6:
    case Mips::JR_MM:
    case Mips::MTHI_MM:
    case Mips::MTLO_MM: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 16;
      }
      break;
    }
    case Mips::ADDIUPC:
    case Mips::ALUIPC:
    case Mips::AUIPC:
    case Mips::LDPC:
    case Mips::LWPC:
    case Mips::LWUPC: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 1:
        // op: imm
        return 0;
      }
      break;
    }
    case Mips::TEQI:
    case Mips::TGEI:
    case Mips::TGEIU:
    case Mips::TLTI:
    case Mips::TNEI:
    case Mips::TTLTIU: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 1:
        // op: imm16
        return 0;
      }
      break;
    }
    case Mips::WRDSP: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 1:
        // op: mask
        return 11;
      }
      break;
    }
    case Mips::BEQZC:
    case Mips::BEQZC64:
    case Mips::BEQZC_MMR6:
    case Mips::BGEZ:
    case Mips::BGEZ64:
    case Mips::BGEZAL:
    case Mips::BGEZALL:
    case Mips::BGEZL:
    case Mips::BGTZ:
    case Mips::BGTZ64:
    case Mips::BGTZL:
    case Mips::BLEZ:
    case Mips::BLEZ64:
    case Mips::BLEZL:
    case Mips::BLTZ:
    case Mips::BLTZ64:
    case Mips::BLTZAL:
    case Mips::BLTZALL:
    case Mips::BLTZL:
    case Mips::BNEZC:
    case Mips::BNEZC64:
    case Mips::BNEZC_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::BBIT0:
    case Mips::BBIT032:
    case Mips::BBIT1:
    case Mips::BBIT132: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 1:
        // op: p
        return 16;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::TEQ:
    case Mips::TGE:
    case Mips::TGEU:
    case Mips::TLT:
    case Mips::TLTU:
    case Mips::TNE: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 1:
        // op: rt
        return 16;
      case 2:
        // op: code_
        return 6;
      }
      break;
    }
    case Mips::BEQ:
    case Mips::BEQ64:
    case Mips::BEQC:
    case Mips::BEQC64:
    case Mips::BEQL:
    case Mips::BGEC:
    case Mips::BGEC64:
    case Mips::BGEUC:
    case Mips::BGEUC64:
    case Mips::BLTC:
    case Mips::BLTC64:
    case Mips::BLTUC:
    case Mips::BLTUC64:
    case Mips::BNE:
    case Mips::BNE64:
    case Mips::BNEC:
    case Mips::BNEC64:
    case Mips::BNEL:
    case Mips::BNVC:
    case Mips::BOVC: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 1:
        // op: rt
        return 16;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::CMPU_EQ_QB:
    case Mips::CMPU_LE_QB:
    case Mips::CMPU_LT_QB:
    case Mips::CMP_EQ_PH:
    case Mips::CMP_LE_PH:
    case Mips::CMP_LT_PH:
    case Mips::DMULT:
    case Mips::DMULTu:
    case Mips::DSDIV:
    case Mips::DUDIV:
    case Mips::MADD:
    case Mips::MADDU:
    case Mips::MSUB:
    case Mips::MSUBU:
    case Mips::MULT:
    case Mips::MULTu:
    case Mips::SDIV:
    case Mips::UDIV: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 1:
        // op: rt
        return 16;
      }
      break;
    }
    case Mips::GINVT: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 1:
        // op: type_
        return 8;
      }
      break;
    }
    case Mips::DAHI:
    case Mips::DATI: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 2:
        // op: imm
        return 0;
      }
      break;
    }
    case Mips::FORK: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 2:
        // op: rt
        return 16;
      case 1:
        // op: rd
        return 11;
      }
      break;
    }
    case Mips::GINVI:
    case Mips::JR:
    case Mips::JR64:
    case Mips::JR_HB:
    case Mips::JR_HB64:
    case Mips::JR_HB64_R6:
    case Mips::JR_HB_R6:
    case Mips::MTHI:
    case Mips::MTHI64:
    case Mips::MTLO:
    case Mips::MTLO64:
    case Mips::MTM0:
    case Mips::MTM1:
    case Mips::MTM2:
    case Mips::MTP0:
    case Mips::MTP1:
    case Mips::MTP2: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      }
      break;
    }
    case Mips::ADDIUPC_MM: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 23;
      case 1:
        // op: imm
        return 0;
      }
      break;
    }
    case Mips::JALRC16_MMR6:
    case Mips::JRC16_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 5;
      }
      break;
    }
    case Mips::BEQZ16_MM:
    case Mips::BEQZC16_MMR6:
    case Mips::BNEZ16_MM:
    case Mips::BNEZC16_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 7;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::EXTP:
    case Mips::EXTPDP:
    case Mips::EXTPDPV:
    case Mips::EXTPV:
    case Mips::EXTRV_RS_W:
    case Mips::EXTRV_R_W:
    case Mips::EXTRV_S_H:
    case Mips::EXTRV_W:
    case Mips::EXTR_RS_W:
    case Mips::EXTR_R_W:
    case Mips::EXTR_S_H:
    case Mips::EXTR_W: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: ac
        return 11;
      case 2:
        // op: shift_rs
        return 21;
      }
      break;
    }
    case Mips::LB:
    case Mips::LB64:
    case Mips::LBu:
    case Mips::LBu64:
    case Mips::LD:
    case Mips::LDC1:
    case Mips::LDC164:
    case Mips::LDC2:
    case Mips::LDC2_R6:
    case Mips::LDC3:
    case Mips::LDL:
    case Mips::LDR:
    case Mips::LEA_ADDiu:
    case Mips::LEA_ADDiu64:
    case Mips::LH:
    case Mips::LH64:
    case Mips::LHu:
    case Mips::LHu64:
    case Mips::LL:
    case Mips::LL64:
    case Mips::LLD:
    case Mips::LW:
    case Mips::LW64:
    case Mips::LWC1:
    case Mips::LWC2:
    case Mips::LWC2_R6:
    case Mips::LWC3:
    case Mips::LWDSP:
    case Mips::LWL:
    case Mips::LWL64:
    case Mips::LWR:
    case Mips::LWR64:
    case Mips::LWu:
    case Mips::SB:
    case Mips::SB64:
    case Mips::SD:
    case Mips::SDC1:
    case Mips::SDC164:
    case Mips::SDC2:
    case Mips::SDC2_R6:
    case Mips::SDC3:
    case Mips::SDL:
    case Mips::SDR:
    case Mips::SH:
    case Mips::SH64:
    case Mips::SW:
    case Mips::SW64:
    case Mips::SWC1:
    case Mips::SWC2:
    case Mips::SWC2_R6:
    case Mips::SWC3:
    case Mips::SWDSP:
    case Mips::SWL:
    case Mips::SWL64:
    case Mips::SWR:
    case Mips::SWR64: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: addr
        return 0;
      }
      break;
    }
    case Mips::LL64_R6:
    case Mips::LLD_R6:
    case Mips::LL_R6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: addr
        return 7;
      }
      break;
    }
    case Mips::CFC1:
    case Mips::DMFC1:
    case Mips::MFC1:
    case Mips::MFC1_D64:
    case Mips::MFHC1_D32:
    case Mips::MFHC1_D64: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: fs
        return 11;
      }
      break;
    }
    case Mips::DMFC2_OCTEON:
    case Mips::DMTC2_OCTEON:
    case Mips::LUi:
    case Mips::LUi64:
    case Mips::LUi_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: imm16
        return 0;
      }
      break;
    }
    case Mips::BC1EQZC_MMR6:
    case Mips::BC1NEZC_MMR6:
    case Mips::BC2EQZC_MMR6:
    case Mips::BC2NEZC_MMR6:
    case Mips::BEQZALC:
    case Mips::BGEZALC:
    case Mips::BGEZALC_MMR6:
    case Mips::BGEZC:
    case Mips::BGEZC64:
    case Mips::BGEZC_MMR6:
    case Mips::BGTZALC:
    case Mips::BGTZC:
    case Mips::BGTZC64:
    case Mips::BLEZALC:
    case Mips::BLEZC:
    case Mips::BLEZC64:
    case Mips::BLTZALC:
    case Mips::BLTZALC_MMR6:
    case Mips::BLTZC:
    case Mips::BLTZC64:
    case Mips::BLTZC_MMR6:
    case Mips::BNEZALC:
    case Mips::JIALC:
    case Mips::JIALC64:
    case Mips::JIALC_MMR6:
    case Mips::JIC:
    case Mips::JIC64:
    case Mips::JIC_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::DMFC0:
    case Mips::DMFC2:
    case Mips::DMFGC0:
    case Mips::MFC0:
    case Mips::MFC2:
    case Mips::MFGC0:
    case Mips::MFHGC0: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: rd
        return 11;
      case 2:
        // op: sel
        return 0;
      }
      break;
    }
    case Mips::RDHWR:
    case Mips::RDHWR64: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: rd
        return 11;
      case 2:
        // op: sel
        return 6;
      }
      break;
    }
    case Mips::SLTi:
    case Mips::SLTi64:
    case Mips::SLTiu:
    case Mips::SLTiu64: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: imm16
        return 0;
      }
      break;
    }
    case Mips::CINS:
    case Mips::CINS32:
    case Mips::CINS64_32:
    case Mips::CINS_i32:
    case Mips::EXTS:
    case Mips::EXTS32: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: pos
        return 6;
      case 3:
        // op: lenm1
        return 11;
      }
      break;
    }
    case Mips::DEXT:
    case Mips::DEXT64_32:
    case Mips::DEXTM:
    case Mips::DEXTU:
    case Mips::DINS:
    case Mips::DINSM:
    case Mips::DINSU:
    case Mips::EXT:
    case Mips::INS: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: pos
        return 6;
      case 3:
        // op: size
        return 11;
      }
      break;
    }
    case Mips::APPEND:
    case Mips::BALIGN:
    case Mips::PREPEND: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: sa
        return 11;
      }
      break;
    }
    case Mips::SAA:
    case Mips::SAAD: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: rs
        return 21;
      }
      break;
    }
    case Mips::INSV: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 2:
        // op: rs
        return 21;
      }
      break;
    }
    case Mips::DI:
    case Mips::DI_MM:
    case Mips::DI_MMR6:
    case Mips::DMT:
    case Mips::DVP:
    case Mips::DVPE:
    case Mips::EI:
    case Mips::EI_MM:
    case Mips::EI_MMR6:
    case Mips::EMT:
    case Mips::EVP:
    case Mips::EVPE: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      }
      break;
    }
    case Mips::LBE_MM:
    case Mips::LB_MM:
    case Mips::LBuE_MM:
    case Mips::LBu_MM:
    case Mips::LDC1_MM_D32:
    case Mips::LDC1_MM_D64:
    case Mips::LDC2_MMR6:
    case Mips::LEA_ADDiu_MM:
    case Mips::LHE_MM:
    case Mips::LH_MM:
    case Mips::LHuE_MM:
    case Mips::LHu_MM:
    case Mips::LLE_MM:
    case Mips::LL_MM:
    case Mips::LL_MMR6:
    case Mips::LWC1_MM:
    case Mips::LWC2_MMR6:
    case Mips::LWDSP_MM:
    case Mips::LWE_MM:
    case Mips::LWLE_MM:
    case Mips::LWL_MM:
    case Mips::LWM32_MM:
    case Mips::LWRE_MM:
    case Mips::LWR_MM:
    case Mips::LWU_MM:
    case Mips::LW_MM:
    case Mips::LW_MMR6:
    case Mips::SBE_MM:
    case Mips::SB_MM:
    case Mips::SB_MMR6:
    case Mips::SDC1_MM_D32:
    case Mips::SDC1_MM_D64:
    case Mips::SDC2_MMR6:
    case Mips::SHE_MM:
    case Mips::SH_MM:
    case Mips::SH_MMR6:
    case Mips::SWC1_MM:
    case Mips::SWC2_MMR6:
    case Mips::SWDSP_MM:
    case Mips::SWE_MM:
    case Mips::SWLE_MM:
    case Mips::SWL_MM:
    case Mips::SWM32_MM:
    case Mips::SWRE_MM:
    case Mips::SWR_MM:
    case Mips::SW_MM:
    case Mips::SW_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: addr
        return 0;
      }
      break;
    }
    case Mips::CFC1_MM:
    case Mips::MFC1_MM:
    case Mips::MFC1_MMR6:
    case Mips::MFHC1_D32_MM:
    case Mips::MFHC1_D64_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: fs
        return 16;
      }
      break;
    }
    case Mips::ADDIUPC_MMR6:
    case Mips::ALUIPC_MMR6:
    case Mips::AUIPC_MMR6:
    case Mips::LWPC_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: imm
        return 0;
      }
      break;
    }
    case Mips::REPL_QB_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: imm
        return 13;
      }
      break;
    }
    case Mips::LUI_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: imm16
        return 0;
      }
      break;
    }
    case Mips::CFC2_MM:
    case Mips::MFC2_MMR6:
    case Mips::MFHC2_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: impl
        return 16;
      }
      break;
    }
    case Mips::RDDSP_MM:
    case Mips::WRDSP_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: mask
        return 14;
      }
      break;
    }
    case Mips::BEQZALC_MMR6:
    case Mips::BGTZALC_MMR6:
    case Mips::BGTZC_MMR6:
    case Mips::BLEZALC_MMR6:
    case Mips::BLEZC_MMR6:
    case Mips::BNEZALC_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::RDHWR_MM:
    case Mips::RDPGPR_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rd
        return 16;
      }
      break;
    }
    case Mips::BALIGN_MMR2: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: bp
        return 14;
      }
      break;
    }
    case Mips::ADDIU_MMR6:
    case Mips::ANDI_MMR6:
    case Mips::ORI_MMR6:
    case Mips::SLTi_MM:
    case Mips::SLTiu_MM:
    case Mips::XORI_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: imm16
        return 0;
      }
      break;
    }
    case Mips::BNVC_MMR6:
    case Mips::BOVC_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::EXT_MM:
    case Mips::INS_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: pos
        return 6;
      case 3:
        // op: size
        return 11;
      }
      break;
    }
    case Mips::APPEND_MMR2:
    case Mips::PRECR_SRA_PH_W_MMR2:
    case Mips::PRECR_SRA_R_PH_W_MMR2:
    case Mips::PREPEND_MMR2:
    case Mips::SHLL_S_W_MM:
    case Mips::SHRA_R_W_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: sa
        return 11;
      }
      break;
    }
    case Mips::SHLL_PH_MM:
    case Mips::SHLL_S_PH_MM:
    case Mips::SHRA_PH_MM:
    case Mips::SHRA_R_PH_MM:
    case Mips::SHRL_PH_MMR2: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: sa
        return 12;
      }
      break;
    }
    case Mips::SHLL_QB_MM:
    case Mips::SHRA_QB_MMR2:
    case Mips::SHRA_R_QB_MMR2:
    case Mips::SHRL_QB_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: sa
        return 13;
      }
      break;
    }
    case Mips::MFC0_MMR6:
    case Mips::MFGC0_MM:
    case Mips::MFHC0_MMR6:
    case Mips::MFHGC0_MM:
    case Mips::RDHWR_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: sel
        return 11;
      }
      break;
    }
    case Mips::EXT_MMR6:
    case Mips::INS_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 3:
        // op: size
        return 11;
      case 2:
        // op: pos
        return 6;
      }
      break;
    }
    case Mips::ABSQ_S_PH_MM:
    case Mips::ABSQ_S_QB_MMR2:
    case Mips::ABSQ_S_W_MM:
    case Mips::BITREV_MM:
    case Mips::JALRC_HB_MMR6:
    case Mips::JALRC_MMR6:
    case Mips::PRECEQU_PH_QBLA_MM:
    case Mips::PRECEQU_PH_QBL_MM:
    case Mips::PRECEQU_PH_QBRA_MM:
    case Mips::PRECEQU_PH_QBR_MM:
    case Mips::PRECEQ_W_PHL_MM:
    case Mips::PRECEQ_W_PHR_MM:
    case Mips::PRECEU_PH_QBLA_MM:
    case Mips::PRECEU_PH_QBL_MM:
    case Mips::PRECEU_PH_QBRA_MM:
    case Mips::PRECEU_PH_QBR_MM:
    case Mips::RADDU_W_QB_MM:
    case Mips::REPLV_PH_MM:
    case Mips::REPLV_QB_MM:
    case Mips::WRPGPR_MMR6:
    case Mips::WSBH_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      }
      break;
    }
    case Mips::LWP_MM:
    case Mips::SWP_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 2:
        // op: addr
        return 0;
      }
      break;
    }
    case Mips::EXTPDP_MM:
    case Mips::EXTP_MM:
    case Mips::EXTR_RS_W_MM:
    case Mips::EXTR_R_W_MM:
    case Mips::EXTR_S_H_MM:
    case Mips::EXTR_W_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 2:
        // op: imm
        return 16;
      case 1:
        // op: ac
        return 14;
      }
      break;
    }
    case Mips::EXTPDPV_MM:
    case Mips::EXTPV_MM:
    case Mips::EXTRV_RS_W_MM:
    case Mips::EXTRV_R_W_MM:
    case Mips::EXTRV_S_H_MM:
    case Mips::EXTRV_W_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 2:
        // op: rs
        return 16;
      case 1:
        // op: ac
        return 14;
      }
      break;
    }
    case Mips::INSV_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 2:
        // op: rs
        return 16;
      }
      break;
    }
    case Mips::NOT16_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 3;
      case 1:
        // op: rs
        return 0;
      }
      break;
    }
    case Mips::LWM16_MM:
    case Mips::SWM16_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 4;
      case 1:
        // op: addr
        return 0;
      }
      break;
    }
    case Mips::LWSP_MM:
    case Mips::SWSP_MM:
    case Mips::SWSP_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 5;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::LBU16_MM:
    case Mips::LHU16_MM:
    case Mips::LW16_MM:
    case Mips::SB16_MM:
    case Mips::SB16_MMR6:
    case Mips::SH16_MM:
    case Mips::SH16_MMR6:
    case Mips::SW16_MM:
    case Mips::SW16_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 7;
      case 1:
        // op: addr
        return 0;
      }
      break;
    }
    case Mips::LWGP_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 7;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::NOT16_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 7;
      case 1:
        // op: rs
        return 4;
      }
      break;
    }
    case Mips::LWM16_MMR6:
    case Mips::SWM16_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 8;
      case 1:
        // op: addr
        return 4;
      }
      break;
    }
    case Mips::BeqzRxImm16:
    case Mips::BnezRxImm16:
    case Mips::CmpiRxImm16:
    case Mips::LiRxImm16:
    case Mips::LwRxPcTcp16:
    case Mips::SltiRxImm16:
    case Mips::SltiuRxImm16: {
      switch (OpNum) {
      case 0:
        // op: rx
        return 8;
      case 1:
        // op: imm8
        return 0;
      }
      break;
    }
    case Mips::CmpRxRy16:
    case Mips::DivRxRy16:
    case Mips::DivuRxRy16:
    case Mips::NegRxRy16:
    case Mips::NotRxRy16:
    case Mips::SltRxRy16:
    case Mips::SltuRxRy16: {
      switch (OpNum) {
      case 0:
        // op: rx
        return 8;
      case 1:
        // op: ry
        return 5;
      }
      break;
    }
    case Mips::AddiuRxRxImm16: {
      switch (OpNum) {
      case 0:
        // op: rx
        return 8;
      case 2:
        // op: imm8
        return 0;
      }
      break;
    }
    case Mips::JrcRx16:
    case Mips::JumpLinkReg16:
    case Mips::Mfhi16:
    case Mips::Mflo16:
    case Mips::SebRx16:
    case Mips::SehRx16: {
      switch (OpNum) {
      case 0:
        // op: rx
        return 8;
      }
      break;
    }
    case Mips::MoveR3216: {
      switch (OpNum) {
      case 0:
        // op: ry
        return 4;
      case 1:
        // op: r32
        return 0;
      }
      break;
    }
    case Mips::SYNC_MM:
    case Mips::SYNC_MMR6: {
      switch (OpNum) {
      case 0:
        // op: stype
        return 16;
      }
      break;
    }
    case Mips::SYNC: {
      switch (OpNum) {
      case 0:
        // op: stype
        return 6;
      }
      break;
    }
    case Mips::J:
    case Mips::JAL:
    case Mips::JALS_MM:
    case Mips::JALX:
    case Mips::JALX_MM:
    case Mips::JAL_MM:
    case Mips::J_MM: {
      switch (OpNum) {
      case 0:
        // op: target
        return 0;
      }
      break;
    }
    case Mips::LBU_MMR6:
    case Mips::LB_MMR6: {
      switch (OpNum) {
      case 1:
        // op: addr
        return 0;
      case 0:
        // op: rt
        return 21;
      }
      break;
    }
    case Mips::LD_B:
    case Mips::LD_D:
    case Mips::LD_H:
    case Mips::LD_W:
    case Mips::ST_B:
    case Mips::ST_D:
    case Mips::ST_H:
    case Mips::ST_W: {
      switch (OpNum) {
      case 1:
        // op: addr
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::LBE:
    case Mips::LBuE:
    case Mips::LHE:
    case Mips::LHuE:
    case Mips::LLE:
    case Mips::LWE:
    case Mips::LWLE:
    case Mips::LWRE:
    case Mips::SBE:
    case Mips::SHE:
    case Mips::SWE:
    case Mips::SWLE:
    case Mips::SWRE: {
      switch (OpNum) {
      case 1:
        // op: addr
        return 7;
      case 0:
        // op: rt
        return 16;
      }
      break;
    }
    case Mips::CLASS_D:
    case Mips::CLASS_S:
    case Mips::RINT_D:
    case Mips::RINT_S: {
      switch (OpNum) {
      case 1:
        // op: fs
        return 11;
      case 0:
        // op: fd
        return 6;
      }
      break;
    }
    case Mips::C_EQ_D32:
    case Mips::C_EQ_D64:
    case Mips::C_EQ_S:
    case Mips::C_F_D32:
    case Mips::C_F_D64:
    case Mips::C_F_S:
    case Mips::C_LE_D32:
    case Mips::C_LE_D64:
    case Mips::C_LE_S:
    case Mips::C_LT_D32:
    case Mips::C_LT_D64:
    case Mips::C_LT_S:
    case Mips::C_NGE_D32:
    case Mips::C_NGE_D64:
    case Mips::C_NGE_S:
    case Mips::C_NGLE_D32:
    case Mips::C_NGLE_D64:
    case Mips::C_NGLE_S:
    case Mips::C_NGL_D32:
    case Mips::C_NGL_D64:
    case Mips::C_NGL_S:
    case Mips::C_NGT_D32:
    case Mips::C_NGT_D64:
    case Mips::C_NGT_S:
    case Mips::C_OLE_D32:
    case Mips::C_OLE_D64:
    case Mips::C_OLE_S:
    case Mips::C_OLT_D32:
    case Mips::C_OLT_D64:
    case Mips::C_OLT_S:
    case Mips::C_SEQ_D32:
    case Mips::C_SEQ_D64:
    case Mips::C_SEQ_S:
    case Mips::C_SF_D32:
    case Mips::C_SF_D64:
    case Mips::C_SF_S:
    case Mips::C_UEQ_D32:
    case Mips::C_UEQ_D64:
    case Mips::C_UEQ_S:
    case Mips::C_ULE_D32:
    case Mips::C_ULE_D64:
    case Mips::C_ULE_S:
    case Mips::C_ULT_D32:
    case Mips::C_ULT_D64:
    case Mips::C_ULT_S:
    case Mips::C_UN_D32:
    case Mips::C_UN_D64:
    case Mips::C_UN_S: {
      switch (OpNum) {
      case 1:
        // op: fs
        return 11;
      case 2:
        // op: ft
        return 16;
      case 0:
        // op: fcc
        return 8;
      }
      break;
    }
    case Mips::C_EQ_D32_MM:
    case Mips::C_EQ_D64_MM:
    case Mips::C_EQ_S_MM:
    case Mips::C_F_D32_MM:
    case Mips::C_F_D64_MM:
    case Mips::C_F_S_MM:
    case Mips::C_LE_D32_MM:
    case Mips::C_LE_D64_MM:
    case Mips::C_LE_S_MM:
    case Mips::C_LT_D32_MM:
    case Mips::C_LT_D64_MM:
    case Mips::C_LT_S_MM:
    case Mips::C_NGE_D32_MM:
    case Mips::C_NGE_D64_MM:
    case Mips::C_NGE_S_MM:
    case Mips::C_NGLE_D32_MM:
    case Mips::C_NGLE_D64_MM:
    case Mips::C_NGLE_S_MM:
    case Mips::C_NGL_D32_MM:
    case Mips::C_NGL_D64_MM:
    case Mips::C_NGL_S_MM:
    case Mips::C_NGT_D32_MM:
    case Mips::C_NGT_D64_MM:
    case Mips::C_NGT_S_MM:
    case Mips::C_OLE_D32_MM:
    case Mips::C_OLE_D64_MM:
    case Mips::C_OLE_S_MM:
    case Mips::C_OLT_D32_MM:
    case Mips::C_OLT_D64_MM:
    case Mips::C_OLT_S_MM:
    case Mips::C_SEQ_D32_MM:
    case Mips::C_SEQ_D64_MM:
    case Mips::C_SEQ_S_MM:
    case Mips::C_SF_D32_MM:
    case Mips::C_SF_D64_MM:
    case Mips::C_SF_S_MM:
    case Mips::C_UEQ_D32_MM:
    case Mips::C_UEQ_D64_MM:
    case Mips::C_UEQ_S_MM:
    case Mips::C_ULE_D32_MM:
    case Mips::C_ULE_D64_MM:
    case Mips::C_ULE_S_MM:
    case Mips::C_ULT_D32_MM:
    case Mips::C_ULT_D64_MM:
    case Mips::C_ULT_S_MM:
    case Mips::C_UN_D32_MM:
    case Mips::C_UN_D64_MM:
    case Mips::C_UN_S_MM: {
      switch (OpNum) {
      case 1:
        // op: fs
        return 16;
      case 2:
        // op: ft
        return 21;
      case 0:
        // op: fcc
        return 13;
      }
      break;
    }
    case Mips::CLASS_D_MMR6:
    case Mips::CLASS_S_MMR6:
    case Mips::RINT_D_MMR6:
    case Mips::RINT_S_MMR6: {
      switch (OpNum) {
      case 1:
        // op: fs
        return 21;
      case 0:
        // op: fd
        return 16;
      }
      break;
    }
    case Mips::FADD_S_MMR6:
    case Mips::FDIV_S_MMR6:
    case Mips::FMUL_S_MMR6:
    case Mips::FSUB_S_MMR6: {
      switch (OpNum) {
      case 1:
        // op: ft
        return 21;
      case 2:
        // op: fs
        return 16;
      case 0:
        // op: fd
        return 11;
      }
      break;
    }
    case Mips::AddiuRxImmX16:
    case Mips::AddiuRxPcImmX16:
    case Mips::BeqzRxImmX16:
    case Mips::BnezRxImmX16:
    case Mips::CmpiRxImmX16:
    case Mips::LiRxImmAlignX16:
    case Mips::LiRxImmX16:
    case Mips::LwRxPcTcpX16:
    case Mips::SltiRxImmX16:
    case Mips::SltiuRxImmX16: {
      switch (OpNum) {
      case 1:
        // op: imm16
        return 0;
      case 0:
        // op: rx
        return 8;
      }
      break;
    }
    case Mips::PREFX_MM: {
      switch (OpNum) {
      case 1:
        // op: index
        return 21;
      case 0:
        // op: base
        return 16;
      case 2:
        // op: hint
        return 11;
      }
      break;
    }
    case Mips::BNZ_B:
    case Mips::BNZ_D:
    case Mips::BNZ_H:
    case Mips::BNZ_V:
    case Mips::BNZ_W:
    case Mips::BZ_B:
    case Mips::BZ_D:
    case Mips::BZ_H:
    case Mips::BZ_V:
    case Mips::BZ_W: {
      switch (OpNum) {
      case 1:
        // op: offset
        return 0;
      case 0:
        // op: wt
        return 16;
      }
      break;
    }
    case Mips::ADDIUS5_MM: {
      switch (OpNum) {
      case 1:
        // op: rd
        return 5;
      case 2:
        // op: imm
        return 1;
      }
      break;
    }
    case Mips::MOVE16_MM:
    case Mips::MOVE16_MMR6: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 0;
      case 0:
        // op: rd
        return 5;
      }
      break;
    }
    case Mips::CTCMSA: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 11;
      case 0:
        // op: cd
        return 6;
      }
      break;
    }
    case Mips::FILL_B:
    case Mips::FILL_D:
    case Mips::FILL_H:
    case Mips::FILL_W: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::MTHI_DSP_MM:
    case Mips::MTHLIP_MM:
    case Mips::MTLO_DSP_MM:
    case Mips::SHILOV_MM: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 16;
      case 0:
        // op: ac
        return 14;
      }
      break;
    }
    case Mips::JALRS_MM:
    case Mips::JALR_MM: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 16;
      case 0:
        // op: rd
        return 21;
      }
      break;
    }
    case Mips::AUI_MMR6: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 16;
      case 0:
        // op: rt
        return 21;
      case 2:
        // op: imm
        return 0;
      }
      break;
    }
    case Mips::ADDi_MM:
    case Mips::ADDiu_MM:
    case Mips::ANDi_MM:
    case Mips::ORi_MM:
    case Mips::XORi_MM: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 16;
      case 0:
        // op: rt
        return 21;
      case 2:
        // op: imm16
        return 0;
      }
      break;
    }
    case Mips::CLO_MMR6: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 16;
      case 0:
        // op: rt
        return 21;
      }
      break;
    }
    case Mips::MTHI_DSP:
    case Mips::MTLO_DSP: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 21;
      case 0:
        // op: ac
        return 11;
      }
      break;
    }
    case Mips::YIELD: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 21;
      case 0:
        // op: rd
        return 11;
      }
      break;
    }
    case Mips::CLZ_MMR6: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 21;
      case 0:
        // op: rt
        return 11;
      }
      break;
    }
    case Mips::AUI:
    case Mips::DAUI: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 21;
      case 0:
        // op: rt
        return 16;
      case 2:
        // op: imm
        return 0;
      }
      break;
    }
    case Mips::SEQi:
    case Mips::SNEi: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 21;
      case 0:
        // op: rt
        return 16;
      case 2:
        // op: imm10
        return 6;
      }
      break;
    }
    case Mips::ADDi:
    case Mips::ADDiu:
    case Mips::ANDi:
    case Mips::ANDi64:
    case Mips::DADDi:
    case Mips::DADDiu:
    case Mips::ORi:
    case Mips::ORi64:
    case Mips::XORi:
    case Mips::XORi64: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 21;
      case 0:
        // op: rt
        return 16;
      case 2:
        // op: imm16
        return 0;
      }
      break;
    }
    case Mips::PRECR_SRA_PH_W:
    case Mips::PRECR_SRA_R_PH_W: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 21;
      case 0:
        // op: rt
        return 16;
      case 2:
        // op: sa
        return 11;
      }
      break;
    }
    case Mips::DLSA:
    case Mips::LSA: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: rt
        return 16;
      case 0:
        // op: rd
        return 11;
      case 3:
        // op: sa
        return 6;
      }
      break;
    }
    case Mips::CMPGDU_EQ_QB:
    case Mips::CMPGDU_LE_QB:
    case Mips::CMPGDU_LT_QB:
    case Mips::CMPGU_EQ_QB:
    case Mips::CMPGU_LE_QB:
    case Mips::CMPGU_LT_QB:
    case Mips::PACKRL_PH:
    case Mips::PICK_PH:
    case Mips::PICK_QB:
    case Mips::PRECRQU_S_QB_PH:
    case Mips::PRECRQ_PH_W:
    case Mips::PRECRQ_QB_PH:
    case Mips::PRECRQ_RS_PH_W:
    case Mips::PRECR_QB_PH: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: rt
        return 16;
      case 0:
        // op: rd
        return 11;
      }
      break;
    }
    case Mips::CRC32B:
    case Mips::CRC32CB:
    case Mips::CRC32CD:
    case Mips::CRC32CH:
    case Mips::CRC32CW:
    case Mips::CRC32D:
    case Mips::CRC32H:
    case Mips::CRC32W: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: rt
        return 16;
      }
      break;
    }
    case Mips::ADDU16_MMR6:
    case Mips::SUBU16_MMR6: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 7;
      case 2:
        // op: rt
        return 4;
      case 0:
        // op: rd
        return 1;
      }
      break;
    }
    case Mips::CTC1:
    case Mips::DMTC1:
    case Mips::MTC1:
    case Mips::MTC1_D64: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 16;
      case 0:
        // op: fs
        return 11;
      }
      break;
    }
    case Mips::DMTC0:
    case Mips::DMTC2:
    case Mips::DMTGC0:
    case Mips::MTC0:
    case Mips::MTC2:
    case Mips::MTGC0:
    case Mips::MTHGC0: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 16;
      case 0:
        // op: rd
        return 11;
      case 2:
        // op: sel
        return 0;
      }
      break;
    }
    case Mips::MFTR:
    case Mips::MTTR: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 16;
      case 0:
        // op: rd
        return 11;
      case 2:
        // op: u
        return 5;
      case 4:
        // op: h
        return 4;
      case 3:
        // op: sel
        return 0;
      }
      break;
    }
    case Mips::SC:
    case Mips::SC64:
    case Mips::SCD: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 16;
      case 2:
        // op: addr
        return 0;
      }
      break;
    }
    case Mips::SC64_R6:
    case Mips::SCD_R6:
    case Mips::SC_R6: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 16;
      case 2:
        // op: addr
        return 7;
      }
      break;
    }
    case Mips::CTC1_MM:
    case Mips::MTC1_D64_MM:
    case Mips::MTC1_MM:
    case Mips::MTC1_MMR6: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 21;
      case 0:
        // op: fs
        return 16;
      }
      break;
    }
    case Mips::CTC2_MM:
    case Mips::MTC2_MMR6:
    case Mips::MTHC2_MMR6: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 21;
      case 0:
        // op: impl
        return 16;
      }
      break;
    }
    case Mips::BEQC_MMR6:
    case Mips::BGEC_MMR6:
    case Mips::BGEUC_MMR6:
    case Mips::BLTC_MMR6:
    case Mips::BLTUC_MMR6:
    case Mips::BNEC_MMR6: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 21;
      case 0:
        // op: rs
        return 16;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::MTC0_MMR6:
    case Mips::MTGC0_MM:
    case Mips::MTHC0_MMR6:
    case Mips::MTHGC0_MM: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 21;
      case 0:
        // op: rs
        return 16;
      case 2:
        // op: sel
        return 11;
      }
      break;
    }
    case Mips::CMPU_EQ_QB_MM:
    case Mips::CMPU_LE_QB_MM:
    case Mips::CMPU_LT_QB_MM:
    case Mips::CMP_EQ_PH_MM:
    case Mips::CMP_LE_PH_MM:
    case Mips::CMP_LT_PH_MM: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 21;
      case 0:
        // op: rs
        return 16;
      }
      break;
    }
    case Mips::SCE_MM:
    case Mips::SC_MM:
    case Mips::SC_MMR6: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 21;
      case 2:
        // op: addr
        return 0;
      }
      break;
    }
    case Mips::AdduRxRyRz16:
    case Mips::SubuRxRyRz16: {
      switch (OpNum) {
      case 1:
        // op: rx
        return 8;
      case 2:
        // op: ry
        return 5;
      case 0:
        // op: rz
        return 2;
      }
      break;
    }
    case Mips::AndRxRxRy16:
    case Mips::OrRxRxRy16:
    case Mips::SllvRxRy16:
    case Mips::SravRxRy16:
    case Mips::SrlvRxRy16:
    case Mips::XorRxRxRy16: {
      switch (OpNum) {
      case 1:
        // op: rx
        return 8;
      case 2:
        // op: ry
        return 5;
      }
      break;
    }
    case Mips::LDI_B:
    case Mips::LDI_D:
    case Mips::LDI_H:
    case Mips::LDI_W: {
      switch (OpNum) {
      case 1:
        // op: s10
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::SHILO_MM: {
      switch (OpNum) {
      case 1:
        // op: shift
        return 16;
      case 0:
        // op: ac
        return 14;
      }
      break;
    }
    case Mips::BCLRI_B:
    case Mips::BCLRI_D:
    case Mips::BCLRI_H:
    case Mips::BCLRI_W:
    case Mips::BNEGI_B:
    case Mips::BNEGI_D:
    case Mips::BNEGI_H:
    case Mips::BNEGI_W:
    case Mips::BSETI_B:
    case Mips::BSETI_D:
    case Mips::BSETI_H:
    case Mips::BSETI_W:
    case Mips::SAT_S_B:
    case Mips::SAT_S_D:
    case Mips::SAT_S_H:
    case Mips::SAT_S_W:
    case Mips::SAT_U_B:
    case Mips::SAT_U_D:
    case Mips::SAT_U_H:
    case Mips::SAT_U_W:
    case Mips::SLLI_B:
    case Mips::SLLI_D:
    case Mips::SLLI_H:
    case Mips::SLLI_W:
    case Mips::SRAI_B:
    case Mips::SRAI_D:
    case Mips::SRAI_H:
    case Mips::SRAI_W:
    case Mips::SRARI_B:
    case Mips::SRARI_D:
    case Mips::SRARI_H:
    case Mips::SRARI_W:
    case Mips::SRLI_B:
    case Mips::SRLI_D:
    case Mips::SRLI_H:
    case Mips::SRLI_W:
    case Mips::SRLRI_B:
    case Mips::SRLRI_D:
    case Mips::SRLRI_H:
    case Mips::SRLRI_W: {
      switch (OpNum) {
      case 1:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      case 2:
        // op: m
        return 16;
      }
      break;
    }
    case Mips::FCLASS_D:
    case Mips::FCLASS_W:
    case Mips::FEXUPL_D:
    case Mips::FEXUPL_W:
    case Mips::FEXUPR_D:
    case Mips::FEXUPR_W:
    case Mips::FFINT_S_D:
    case Mips::FFINT_S_W:
    case Mips::FFINT_U_D:
    case Mips::FFINT_U_W:
    case Mips::FFQL_D:
    case Mips::FFQL_W:
    case Mips::FFQR_D:
    case Mips::FFQR_W:
    case Mips::FLOG2_D:
    case Mips::FLOG2_W:
    case Mips::FRCP_D:
    case Mips::FRCP_W:
    case Mips::FRINT_D:
    case Mips::FRINT_W:
    case Mips::FRSQRT_D:
    case Mips::FRSQRT_W:
    case Mips::FSQRT_D:
    case Mips::FSQRT_W:
    case Mips::FTINT_S_D:
    case Mips::FTINT_S_W:
    case Mips::FTINT_U_D:
    case Mips::FTINT_U_W:
    case Mips::FTRUNC_S_D:
    case Mips::FTRUNC_S_W:
    case Mips::FTRUNC_U_D:
    case Mips::FTRUNC_U_W:
    case Mips::MOVE_V:
    case Mips::NLOC_B:
    case Mips::NLOC_D:
    case Mips::NLOC_H:
    case Mips::NLOC_W:
    case Mips::NLZC_B:
    case Mips::NLZC_D:
    case Mips::NLZC_H:
    case Mips::NLZC_W:
    case Mips::PCNT_B:
    case Mips::PCNT_D:
    case Mips::PCNT_H:
    case Mips::PCNT_W: {
      switch (OpNum) {
      case 1:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::SCE: {
      switch (OpNum) {
      case 2:
        // op: addr
        return 7;
      case 1:
        // op: rt
        return 16;
      }
      break;
    }
    case Mips::MAXA_D:
    case Mips::MAXA_S:
    case Mips::MAX_D:
    case Mips::MAX_S:
    case Mips::MINA_D:
    case Mips::MINA_S:
    case Mips::MIN_D:
    case Mips::MIN_S:
    case Mips::SELEQZ_D:
    case Mips::SELEQZ_S:
    case Mips::SELNEZ_D:
    case Mips::SELNEZ_S: {
      switch (OpNum) {
      case 2:
        // op: ft
        return 16;
      case 1:
        // op: fs
        return 11;
      case 0:
        // op: fd
        return 6;
      }
      break;
    }
    case Mips::CMP_AF_D_MMR6:
    case Mips::CMP_AF_S_MMR6:
    case Mips::CMP_EQ_D_MMR6:
    case Mips::CMP_EQ_S_MMR6:
    case Mips::CMP_LE_D_MMR6:
    case Mips::CMP_LE_S_MMR6:
    case Mips::CMP_LT_D_MMR6:
    case Mips::CMP_LT_S_MMR6:
    case Mips::CMP_SAF_D_MMR6:
    case Mips::CMP_SAF_S_MMR6:
    case Mips::CMP_SEQ_D_MMR6:
    case Mips::CMP_SEQ_S_MMR6:
    case Mips::CMP_SLE_D_MMR6:
    case Mips::CMP_SLE_S_MMR6:
    case Mips::CMP_SLT_D_MMR6:
    case Mips::CMP_SLT_S_MMR6:
    case Mips::CMP_SUEQ_D_MMR6:
    case Mips::CMP_SUEQ_S_MMR6:
    case Mips::CMP_SULE_D_MMR6:
    case Mips::CMP_SULE_S_MMR6:
    case Mips::CMP_SULT_D_MMR6:
    case Mips::CMP_SULT_S_MMR6:
    case Mips::CMP_SUN_D_MMR6:
    case Mips::CMP_SUN_S_MMR6:
    case Mips::CMP_UEQ_D_MMR6:
    case Mips::CMP_UEQ_S_MMR6:
    case Mips::CMP_ULE_D_MMR6:
    case Mips::CMP_ULE_S_MMR6:
    case Mips::CMP_ULT_D_MMR6:
    case Mips::CMP_ULT_S_MMR6:
    case Mips::CMP_UN_D_MMR6:
    case Mips::CMP_UN_S_MMR6:
    case Mips::FADD_D32_MM:
    case Mips::FADD_D64_MM:
    case Mips::FADD_S_MM:
    case Mips::FDIV_D32_MM:
    case Mips::FDIV_D64_MM:
    case Mips::FDIV_S_MM:
    case Mips::FMUL_D32_MM:
    case Mips::FMUL_D64_MM:
    case Mips::FMUL_S_MM:
    case Mips::FSUB_D32_MM:
    case Mips::FSUB_D64_MM:
    case Mips::FSUB_S_MM:
    case Mips::MAXA_D_MMR6:
    case Mips::MAXA_S_MMR6:
    case Mips::MAX_D_MMR6:
    case Mips::MAX_S_MMR6:
    case Mips::MINA_D_MMR6:
    case Mips::MINA_S_MMR6:
    case Mips::MIN_D_MMR6:
    case Mips::MIN_S_MMR6:
    case Mips::SELEQZ_D_MMR6:
    case Mips::SELEQZ_S_MMR6:
    case Mips::SELNEZ_D_MMR6:
    case Mips::SELNEZ_S_MMR6: {
      switch (OpNum) {
      case 2:
        // op: ft
        return 21;
      case 1:
        // op: fs
        return 16;
      case 0:
        // op: fd
        return 11;
      }
      break;
    }
    case Mips::ADDVI_B:
    case Mips::ADDVI_D:
    case Mips::ADDVI_H:
    case Mips::ADDVI_W:
    case Mips::CEQI_B:
    case Mips::CEQI_D:
    case Mips::CEQI_H:
    case Mips::CEQI_W:
    case Mips::CLEI_S_B:
    case Mips::CLEI_S_D:
    case Mips::CLEI_S_H:
    case Mips::CLEI_S_W:
    case Mips::CLEI_U_B:
    case Mips::CLEI_U_D:
    case Mips::CLEI_U_H:
    case Mips::CLEI_U_W:
    case Mips::CLTI_S_B:
    case Mips::CLTI_S_D:
    case Mips::CLTI_S_H:
    case Mips::CLTI_S_W:
    case Mips::CLTI_U_B:
    case Mips::CLTI_U_D:
    case Mips::CLTI_U_H:
    case Mips::CLTI_U_W:
    case Mips::MAXI_S_B:
    case Mips::MAXI_S_D:
    case Mips::MAXI_S_H:
    case Mips::MAXI_S_W:
    case Mips::MAXI_U_B:
    case Mips::MAXI_U_D:
    case Mips::MAXI_U_H:
    case Mips::MAXI_U_W:
    case Mips::MINI_S_B:
    case Mips::MINI_S_D:
    case Mips::MINI_S_H:
    case Mips::MINI_S_W:
    case Mips::MINI_U_B:
    case Mips::MINI_U_D:
    case Mips::MINI_U_H:
    case Mips::MINI_U_W:
    case Mips::SUBVI_B:
    case Mips::SUBVI_D:
    case Mips::SUBVI_H:
    case Mips::SUBVI_W: {
      switch (OpNum) {
      case 2:
        // op: imm
        return 16;
      case 1:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::AddiuRxRyOffMemX16: {
      switch (OpNum) {
      case 2:
        // op: imm15
        return 0;
      case 1:
        // op: rx
        return 8;
      case 0:
        // op: ry
        return 5;
      }
      break;
    }
    case Mips::AddiuRxRxImmX16: {
      switch (OpNum) {
      case 2:
        // op: imm16
        return 0;
      case 0:
        // op: rx
        return 8;
      }
      break;
    }
    case Mips::LbRxRyOffMemX16:
    case Mips::LbuRxRyOffMemX16:
    case Mips::LhRxRyOffMemX16:
    case Mips::LhuRxRyOffMemX16:
    case Mips::LwRxRyOffMemX16:
    case Mips::LwRxSpImmX16:
    case Mips::SbRxRyOffMemX16:
    case Mips::ShRxRyOffMemX16:
    case Mips::SwRxRyOffMemX16:
    case Mips::SwRxSpImmX16: {
      switch (OpNum) {
      case 2:
        // op: imm16
        return 0;
      case 1:
        // op: rx
        return 8;
      case 0:
        // op: ry
        return 5;
      }
      break;
    }
    case Mips::LBUX_MM:
    case Mips::LHX_MM:
    case Mips::LWX_MM: {
      switch (OpNum) {
      case 2:
        // op: index
        return 21;
      case 1:
        // op: base
        return 16;
      case 0:
        // op: rd
        return 11;
      }
      break;
    }
    case Mips::COPY_S_B:
    case Mips::COPY_S_D:
    case Mips::COPY_S_H:
    case Mips::COPY_S_W:
    case Mips::COPY_U_B:
    case Mips::COPY_U_H:
    case Mips::COPY_U_W: {
      switch (OpNum) {
      case 2:
        // op: n
        return 16;
      case 1:
        // op: ws
        return 11;
      case 0:
        // op: rd
        return 6;
      }
      break;
    }
    case Mips::SPLATI_B:
    case Mips::SPLATI_D:
    case Mips::SPLATI_H:
    case Mips::SPLATI_W: {
      switch (OpNum) {
      case 2:
        // op: n
        return 16;
      case 1:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::INSVE_B:
    case Mips::INSVE_D:
    case Mips::INSVE_H:
    case Mips::INSVE_W: {
      switch (OpNum) {
      case 2:
        // op: n
        return 16;
      case 3:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::MTHC1_D32:
    case Mips::MTHC1_D64: {
      switch (OpNum) {
      case 2:
        // op: rt
        return 16;
      case 0:
        // op: fs
        return 11;
      }
      break;
    }
    case Mips::SPLAT_B:
    case Mips::SPLAT_D:
    case Mips::SPLAT_H:
    case Mips::SPLAT_W: {
      switch (OpNum) {
      case 2:
        // op: rt
        return 16;
      case 1:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::MTHC1_D32_MM:
    case Mips::MTHC1_D64_MM: {
      switch (OpNum) {
      case 2:
        // op: rt
        return 21;
      case 0:
        // op: fs
        return 16;
      }
      break;
    }
    case Mips::DPAQX_SA_W_PH_MMR2:
    case Mips::DPAQX_S_W_PH_MMR2:
    case Mips::DPAQ_SA_L_W_MM:
    case Mips::DPAQ_S_W_PH_MM:
    case Mips::DPAU_H_QBL_MM:
    case Mips::DPAU_H_QBR_MM:
    case Mips::DPAX_W_PH_MMR2:
    case Mips::DPA_W_PH_MMR2:
    case Mips::DPSQX_SA_W_PH_MMR2:
    case Mips::DPSQX_S_W_PH_MMR2:
    case Mips::DPSQ_SA_L_W_MM:
    case Mips::DPSQ_S_W_PH_MM:
    case Mips::DPSU_H_QBL_MM:
    case Mips::DPSU_H_QBR_MM:
    case Mips::DPSX_W_PH_MMR2:
    case Mips::DPS_W_PH_MMR2:
    case Mips::MADDU_DSP_MM:
    case Mips::MADD_DSP_MM:
    case Mips::MAQ_SA_W_PHL_MM:
    case Mips::MAQ_SA_W_PHR_MM:
    case Mips::MAQ_S_W_PHL_MM:
    case Mips::MAQ_S_W_PHR_MM:
    case Mips::MSUBU_DSP_MM:
    case Mips::MSUB_DSP_MM:
    case Mips::MULSAQ_S_W_PH_MM:
    case Mips::MULSA_W_PH_MMR2:
    case Mips::MULTU_DSP_MM:
    case Mips::MULT_DSP_MM: {
      switch (OpNum) {
      case 2:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 0:
        // op: ac
        return 14;
      }
      break;
    }
    case Mips::ADD_MM:
    case Mips::ADDu_MM:
    case Mips::AND_MM:
    case Mips::CMPGU_EQ_QB_MM:
    case Mips::CMPGU_LE_QB_MM:
    case Mips::CMPGU_LT_QB_MM:
    case Mips::MOVN_I_MM:
    case Mips::MOVZ_I_MM:
    case Mips::MUL_MM:
    case Mips::NOR_MM:
    case Mips::OR_MM:
    case Mips::SLT_MM:
    case Mips::SLTu_MM:
    case Mips::SUB_MM:
    case Mips::SUBu_MM:
    case Mips::XOR_MM: {
      switch (OpNum) {
      case 2:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 0:
        // op: rd
        return 11;
      }
      break;
    }
    case Mips::AND16_MM:
    case Mips::OR16_MM:
    case Mips::XOR16_MM: {
      switch (OpNum) {
      case 2:
        // op: rt
        return 3;
      case 1:
        // op: rs
        return 0;
      }
      break;
    }
    case Mips::AND16_MMR6:
    case Mips::OR16_MMR6:
    case Mips::XOR16_MMR6: {
      switch (OpNum) {
      case 2:
        // op: rt
        return 7;
      case 1:
        // op: rs
        return 4;
      }
      break;
    }
    case Mips::SllX16:
    case Mips::SraX16:
    case Mips::SrlX16: {
      switch (OpNum) {
      case 2:
        // op: sa6
        return 21;
      case 0:
        // op: rx
        return 8;
      case 1:
        // op: ry
        return 5;
      }
      break;
    }
    case Mips::ANDI_B:
    case Mips::NORI_B:
    case Mips::ORI_B:
    case Mips::SHF_B:
    case Mips::SHF_H:
    case Mips::SHF_W:
    case Mips::XORI_B: {
      switch (OpNum) {
      case 2:
        // op: u8
        return 16;
      case 1:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::BINSLI_B:
    case Mips::BINSLI_D:
    case Mips::BINSLI_H:
    case Mips::BINSLI_W:
    case Mips::BINSRI_B:
    case Mips::BINSRI_D:
    case Mips::BINSRI_H:
    case Mips::BINSRI_W: {
      switch (OpNum) {
      case 2:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      case 3:
        // op: m
        return 16;
      }
      break;
    }
    case Mips::ADDS_A_B:
    case Mips::ADDS_A_D:
    case Mips::ADDS_A_H:
    case Mips::ADDS_A_W:
    case Mips::ADDS_S_B:
    case Mips::ADDS_S_D:
    case Mips::ADDS_S_H:
    case Mips::ADDS_S_W:
    case Mips::ADDS_U_B:
    case Mips::ADDS_U_D:
    case Mips::ADDS_U_H:
    case Mips::ADDS_U_W:
    case Mips::ADDV_B:
    case Mips::ADDV_D:
    case Mips::ADDV_H:
    case Mips::ADDV_W:
    case Mips::ADD_A_B:
    case Mips::ADD_A_D:
    case Mips::ADD_A_H:
    case Mips::ADD_A_W:
    case Mips::AND_V:
    case Mips::ASUB_S_B:
    case Mips::ASUB_S_D:
    case Mips::ASUB_S_H:
    case Mips::ASUB_S_W:
    case Mips::ASUB_U_B:
    case Mips::ASUB_U_D:
    case Mips::ASUB_U_H:
    case Mips::ASUB_U_W:
    case Mips::AVER_S_B:
    case Mips::AVER_S_D:
    case Mips::AVER_S_H:
    case Mips::AVER_S_W:
    case Mips::AVER_U_B:
    case Mips::AVER_U_D:
    case Mips::AVER_U_H:
    case Mips::AVER_U_W:
    case Mips::AVE_S_B:
    case Mips::AVE_S_D:
    case Mips::AVE_S_H:
    case Mips::AVE_S_W:
    case Mips::AVE_U_B:
    case Mips::AVE_U_D:
    case Mips::AVE_U_H:
    case Mips::AVE_U_W:
    case Mips::BCLR_B:
    case Mips::BCLR_D:
    case Mips::BCLR_H:
    case Mips::BCLR_W:
    case Mips::BNEG_B:
    case Mips::BNEG_D:
    case Mips::BNEG_H:
    case Mips::BNEG_W:
    case Mips::BSET_B:
    case Mips::BSET_D:
    case Mips::BSET_H:
    case Mips::BSET_W:
    case Mips::CEQ_B:
    case Mips::CEQ_D:
    case Mips::CEQ_H:
    case Mips::CEQ_W:
    case Mips::CLE_S_B:
    case Mips::CLE_S_D:
    case Mips::CLE_S_H:
    case Mips::CLE_S_W:
    case Mips::CLE_U_B:
    case Mips::CLE_U_D:
    case Mips::CLE_U_H:
    case Mips::CLE_U_W:
    case Mips::CLT_S_B:
    case Mips::CLT_S_D:
    case Mips::CLT_S_H:
    case Mips::CLT_S_W:
    case Mips::CLT_U_B:
    case Mips::CLT_U_D:
    case Mips::CLT_U_H:
    case Mips::CLT_U_W:
    case Mips::DIV_S_B:
    case Mips::DIV_S_D:
    case Mips::DIV_S_H:
    case Mips::DIV_S_W:
    case Mips::DIV_U_B:
    case Mips::DIV_U_D:
    case Mips::DIV_U_H:
    case Mips::DIV_U_W:
    case Mips::DOTP_S_D:
    case Mips::DOTP_S_H:
    case Mips::DOTP_S_W:
    case Mips::DOTP_U_D:
    case Mips::DOTP_U_H:
    case Mips::DOTP_U_W:
    case Mips::FADD_D:
    case Mips::FADD_W:
    case Mips::FCAF_D:
    case Mips::FCAF_W:
    case Mips::FCEQ_D:
    case Mips::FCEQ_W:
    case Mips::FCLE_D:
    case Mips::FCLE_W:
    case Mips::FCLT_D:
    case Mips::FCLT_W:
    case Mips::FCNE_D:
    case Mips::FCNE_W:
    case Mips::FCOR_D:
    case Mips::FCOR_W:
    case Mips::FCUEQ_D:
    case Mips::FCUEQ_W:
    case Mips::FCULE_D:
    case Mips::FCULE_W:
    case Mips::FCULT_D:
    case Mips::FCULT_W:
    case Mips::FCUNE_D:
    case Mips::FCUNE_W:
    case Mips::FCUN_D:
    case Mips::FCUN_W:
    case Mips::FDIV_D:
    case Mips::FDIV_W:
    case Mips::FEXDO_H:
    case Mips::FEXDO_W:
    case Mips::FEXP2_D:
    case Mips::FEXP2_W:
    case Mips::FMAX_A_D:
    case Mips::FMAX_A_W:
    case Mips::FMAX_D:
    case Mips::FMAX_W:
    case Mips::FMIN_A_D:
    case Mips::FMIN_A_W:
    case Mips::FMIN_D:
    case Mips::FMIN_W:
    case Mips::FMUL_D:
    case Mips::FMUL_W:
    case Mips::FSAF_D:
    case Mips::FSAF_W:
    case Mips::FSEQ_D:
    case Mips::FSEQ_W:
    case Mips::FSLE_D:
    case Mips::FSLE_W:
    case Mips::FSLT_D:
    case Mips::FSLT_W:
    case Mips::FSNE_D:
    case Mips::FSNE_W:
    case Mips::FSOR_D:
    case Mips::FSOR_W:
    case Mips::FSUB_D:
    case Mips::FSUB_W:
    case Mips::FSUEQ_D:
    case Mips::FSUEQ_W:
    case Mips::FSULE_D:
    case Mips::FSULE_W:
    case Mips::FSULT_D:
    case Mips::FSULT_W:
    case Mips::FSUNE_D:
    case Mips::FSUNE_W:
    case Mips::FSUN_D:
    case Mips::FSUN_W:
    case Mips::FTQ_H:
    case Mips::FTQ_W:
    case Mips::HADD_S_D:
    case Mips::HADD_S_H:
    case Mips::HADD_S_W:
    case Mips::HADD_U_D:
    case Mips::HADD_U_H:
    case Mips::HADD_U_W:
    case Mips::HSUB_S_D:
    case Mips::HSUB_S_H:
    case Mips::HSUB_S_W:
    case Mips::HSUB_U_D:
    case Mips::HSUB_U_H:
    case Mips::HSUB_U_W:
    case Mips::ILVEV_B:
    case Mips::ILVEV_D:
    case Mips::ILVEV_H:
    case Mips::ILVEV_W:
    case Mips::ILVL_B:
    case Mips::ILVL_D:
    case Mips::ILVL_H:
    case Mips::ILVL_W:
    case Mips::ILVOD_B:
    case Mips::ILVOD_D:
    case Mips::ILVOD_H:
    case Mips::ILVOD_W:
    case Mips::ILVR_B:
    case Mips::ILVR_D:
    case Mips::ILVR_H:
    case Mips::ILVR_W:
    case Mips::MAX_A_B:
    case Mips::MAX_A_D:
    case Mips::MAX_A_H:
    case Mips::MAX_A_W:
    case Mips::MAX_S_B:
    case Mips::MAX_S_D:
    case Mips::MAX_S_H:
    case Mips::MAX_S_W:
    case Mips::MAX_U_B:
    case Mips::MAX_U_D:
    case Mips::MAX_U_H:
    case Mips::MAX_U_W:
    case Mips::MIN_A_B:
    case Mips::MIN_A_D:
    case Mips::MIN_A_H:
    case Mips::MIN_A_W:
    case Mips::MIN_S_B:
    case Mips::MIN_S_D:
    case Mips::MIN_S_H:
    case Mips::MIN_S_W:
    case Mips::MIN_U_B:
    case Mips::MIN_U_D:
    case Mips::MIN_U_H:
    case Mips::MIN_U_W:
    case Mips::MOD_S_B:
    case Mips::MOD_S_D:
    case Mips::MOD_S_H:
    case Mips::MOD_S_W:
    case Mips::MOD_U_B:
    case Mips::MOD_U_D:
    case Mips::MOD_U_H:
    case Mips::MOD_U_W:
    case Mips::MULR_Q_H:
    case Mips::MULR_Q_W:
    case Mips::MULV_B:
    case Mips::MULV_D:
    case Mips::MULV_H:
    case Mips::MULV_W:
    case Mips::MUL_Q_H:
    case Mips::MUL_Q_W:
    case Mips::NOR_V:
    case Mips::OR_V:
    case Mips::PCKEV_B:
    case Mips::PCKEV_D:
    case Mips::PCKEV_H:
    case Mips::PCKEV_W:
    case Mips::PCKOD_B:
    case Mips::PCKOD_D:
    case Mips::PCKOD_H:
    case Mips::PCKOD_W:
    case Mips::SLL_B:
    case Mips::SLL_D:
    case Mips::SLL_H:
    case Mips::SLL_W:
    case Mips::SRAR_B:
    case Mips::SRAR_D:
    case Mips::SRAR_H:
    case Mips::SRAR_W:
    case Mips::SRA_B:
    case Mips::SRA_D:
    case Mips::SRA_H:
    case Mips::SRA_W:
    case Mips::SRLR_B:
    case Mips::SRLR_D:
    case Mips::SRLR_H:
    case Mips::SRLR_W:
    case Mips::SRL_B:
    case Mips::SRL_D:
    case Mips::SRL_H:
    case Mips::SRL_W:
    case Mips::SUBSUS_U_B:
    case Mips::SUBSUS_U_D:
    case Mips::SUBSUS_U_H:
    case Mips::SUBSUS_U_W:
    case Mips::SUBSUU_S_B:
    case Mips::SUBSUU_S_D:
    case Mips::SUBSUU_S_H:
    case Mips::SUBSUU_S_W:
    case Mips::SUBS_S_B:
    case Mips::SUBS_S_D:
    case Mips::SUBS_S_H:
    case Mips::SUBS_S_W:
    case Mips::SUBS_U_B:
    case Mips::SUBS_U_D:
    case Mips::SUBS_U_H:
    case Mips::SUBS_U_W:
    case Mips::SUBV_B:
    case Mips::SUBV_D:
    case Mips::SUBV_H:
    case Mips::SUBV_W:
    case Mips::XOR_V: {
      switch (OpNum) {
      case 2:
        // op: wt
        return 16;
      case 1:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::MADDF_D:
    case Mips::MADDF_S:
    case Mips::MSUBF_D:
    case Mips::MSUBF_S:
    case Mips::SEL_D:
    case Mips::SEL_S: {
      switch (OpNum) {
      case 3:
        // op: ft
        return 16;
      case 2:
        // op: fs
        return 11;
      case 0:
        // op: fd
        return 6;
      }
      break;
    }
    case Mips::MADD_D32_MM:
    case Mips::MADD_S_MM:
    case Mips::MSUB_D32_MM:
    case Mips::MSUB_S_MM:
    case Mips::NMADD_D32_MM:
    case Mips::NMADD_S_MM:
    case Mips::NMSUB_D32_MM:
    case Mips::NMSUB_S_MM: {
      switch (OpNum) {
      case 3:
        // op: ft
        return 21;
      case 2:
        // op: fs
        return 16;
      case 0:
        // op: fd
        return 11;
      case 1:
        // op: fr
        return 6;
      }
      break;
    }
    case Mips::MADDF_D_MMR6:
    case Mips::MADDF_S_MMR6:
    case Mips::MSUBF_D_MMR6:
    case Mips::MSUBF_S_MMR6:
    case Mips::SEL_D_MMR6:
    case Mips::SEL_S_MMR6: {
      switch (OpNum) {
      case 3:
        // op: ft
        return 21;
      case 2:
        // op: fs
        return 16;
      case 0:
        // op: fd
        return 11;
      }
      break;
    }
    case Mips::INSERT_B:
    case Mips::INSERT_D:
    case Mips::INSERT_H:
    case Mips::INSERT_W: {
      switch (OpNum) {
      case 3:
        // op: n
        return 16;
      case 2:
        // op: rs
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::SLDI_B:
    case Mips::SLDI_D:
    case Mips::SLDI_H:
    case Mips::SLDI_W: {
      switch (OpNum) {
      case 3:
        // op: n
        return 16;
      case 2:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::SLD_B:
    case Mips::SLD_D:
    case Mips::SLD_H:
    case Mips::SLD_W: {
      switch (OpNum) {
      case 3:
        // op: rt
        return 16;
      case 2:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::MOVEP_MMR6: {
      switch (OpNum) {
      case 3:
        // op: rt
        return 4;
      case 2:
        // op: rs
        return 0;
      }
      break;
    }
    case Mips::MOVEP_MM: {
      switch (OpNum) {
      case 3:
        // op: rt
        return 4;
      case 2:
        // op: rs
        return 1;
      }
      break;
    }
    case Mips::BMNZI_B:
    case Mips::BMZI_B:
    case Mips::BSELI_B: {
      switch (OpNum) {
      case 3:
        // op: u8
        return 16;
      case 2:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::BINSL_B:
    case Mips::BINSL_D:
    case Mips::BINSL_H:
    case Mips::BINSL_W:
    case Mips::BINSR_B:
    case Mips::BINSR_D:
    case Mips::BINSR_H:
    case Mips::BINSR_W:
    case Mips::BMNZ_V:
    case Mips::BMZ_V:
    case Mips::BSEL_V:
    case Mips::DPADD_S_D:
    case Mips::DPADD_S_H:
    case Mips::DPADD_S_W:
    case Mips::DPADD_U_D:
    case Mips::DPADD_U_H:
    case Mips::DPADD_U_W:
    case Mips::DPSUB_S_D:
    case Mips::DPSUB_S_H:
    case Mips::DPSUB_S_W:
    case Mips::DPSUB_U_D:
    case Mips::DPSUB_U_H:
    case Mips::DPSUB_U_W:
    case Mips::FMADD_D:
    case Mips::FMADD_W:
    case Mips::FMSUB_D:
    case Mips::FMSUB_W:
    case Mips::MADDR_Q_H:
    case Mips::MADDR_Q_W:
    case Mips::MADDV_B:
    case Mips::MADDV_D:
    case Mips::MADDV_H:
    case Mips::MADDV_W:
    case Mips::MADD_Q_H:
    case Mips::MADD_Q_W:
    case Mips::MSUBR_Q_H:
    case Mips::MSUBR_Q_W:
    case Mips::MSUBV_B:
    case Mips::MSUBV_D:
    case Mips::MSUBV_H:
    case Mips::MSUBV_W:
    case Mips::MSUB_Q_H:
    case Mips::MSUB_Q_W:
    case Mips::VSHF_B:
    case Mips::VSHF_D:
    case Mips::VSHF_H:
    case Mips::VSHF_W: {
      switch (OpNum) {
      case 3:
        // op: wt
        return 16;
      case 2:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
  default:
    reportUnsupportedInst(MI);
  }
  reportUnsupportedOperand(MI, OpNum);
}

#endif // GET_OPERAND_BIT_OFFSET

