/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|*  * AVR Disassembler                                                        *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/DataTypes.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/LEB128.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/TargetParser/SubtargetFeature.h"
#include <assert.h>

namespace {

// InsnBitWidth is essentially a type trait used by the decoder emitter to query
// the supported bitwidth for a given type. But default, the value is 0, making
// it an invalid type for use as `InsnType` when instantiating the decoder.
// Individual targets are expected to provide specializations for these based
// on their usage.
template <typename T> constexpr uint32_t InsnBitWidth = 0;

static const uint8_t DecoderTable16[865] = {
  OPC_SwitchField, 14, 2,                    //   0: switch Inst[15:14] {
  0, 168, 1,                                 //   3: case 0x0: {
  OPC_SwitchField, 12, 2,                    //   6:  switch Inst[13:12] {
  0, 99,                                     //   9:  case 0x0: {
  OPC_SwitchField, 10, 2,                    //  11:   switch Inst[11:10] {
  0, 76,                                     //  14:   case 0x0: {
  OPC_SwitchField, 8, 2,                     //  16:    switch Inst[9:8] {
  0, 8,                                      //  19:    case 0x0: {
  OPC_CheckField, 0, 8, 0,                   //  21:     check Inst[7:0] == 0x0
  OPC_Decode, 225, 3, 0,                     //  25:     decode to NOP using decoder 0
                                             //  25:    }
  1, 6,                                      //  29:    case 0x1: {
  OPC_CheckPredicate, 0,                     //  31:     check predicate 0
  OPC_Decode, 220, 3, 1,                     //  33:     decode to MOVWRdRr using decoder 1
                                             //  33:    }
  2, 6,                                      //  37:    case 0x2: {
  OPC_CheckPredicate, 1,                     //  39:     check predicate 1
  OPC_Decode, 222, 3, 2,                     //  41:     decode to MULSRdRr using decoder 2
                                             //  41:    }
  3, 0,                                      //  45:    case 0x3: {
  OPC_SwitchField, 3, 1,                     //  47:     switch Inst[3] {
  0, 19,                                     //  50:     case 0x0: {
  OPC_SwitchField, 7, 1,                     //  52:      switch Inst[7] {
  0, 6,                                      //  55:      case 0x0: {
  OPC_CheckPredicate, 1,                     //  57:       check predicate 1
  OPC_Decode, 223, 3, 3,                     //  59:       decode to MULSURdRr using decoder 3
                                             //  59:      }
  1, 0,                                      //  63:      case 0x1: {
  OPC_CheckPredicate, 1,                     //  65:       check predicate 1
  OPC_Decode, 198, 3, 3,                     //  67:       decode to FMULS using decoder 3
                                             //  67:      }
                                             //  67:      } // switch Inst[7]
                                             //  67:     }
  1, 0,                                      //  71:     case 0x1: {
  OPC_SwitchField, 7, 1,                     //  73:      switch Inst[7] {
  0, 6,                                      //  76:      case 0x0: {
  OPC_CheckPredicate, 1,                     //  78:       check predicate 1
  OPC_Decode, 197, 3, 3,                     //  80:       decode to FMUL using decoder 3
                                             //  80:      }
  1, 0,                                      //  84:      case 0x1: {
  OPC_CheckPredicate, 1,                     //  86:       check predicate 1
  OPC_Decode, 199, 3, 3,                     //  88:       decode to FMULSU using decoder 3
                                             //  88:      }
                                             //  88:      } // switch Inst[7]
                                             //  88:     }
                                             //  88:     } // switch Inst[3]
                                             //  88:    }
                                             //  88:    } // switch Inst[9:8]
                                             //  88:   }
  1, 4,                                      //  92:   case 0x1: {
  OPC_Decode, 185, 3, 4,                     //  94:    decode to CPCRdRr using decoder 4
                                             //  94:   }
  2, 4,                                      //  98:   case 0x2: {
  OPC_Decode, 237, 3, 5,                     // 100:    decode to SBCRdRr using decoder 5
                                             // 100:   }
  3, 0,                                      // 104:   case 0x3: {
  OPC_Decode, 162, 3, 5,                     // 106:    decode to ADDRdRr using decoder 5
                                             // 106:   }
                                             // 106:   } // switch Inst[11:10]
                                             // 106:  }
  1, 27,                                     // 110:  case 0x1: {
  OPC_SwitchField, 10, 2,                    // 112:   switch Inst[11:10] {
  0, 4,                                      // 115:   case 0x0: {
  OPC_Decode, 188, 3, 4,                     // 117:    decode to CPSE using decoder 4
                                             // 117:   }
  1, 4,                                      // 121:   case 0x1: {
  OPC_Decode, 187, 3, 4,                     // 123:    decode to CPRdRr using decoder 4
                                             // 123:   }
  2, 4,                                      // 127:   case 0x2: {
  OPC_Decode, 254, 3, 5,                     // 129:    decode to SUBRdRr using decoder 5
                                             // 129:   }
  3, 0,                                      // 133:   case 0x3: {
  OPC_Decode, 161, 3, 5,                     // 135:    decode to ADCRdRr using decoder 5
                                             // 135:   }
                                             // 135:   } // switch Inst[11:10]
                                             // 135:  }
  2, 27,                                     // 139:  case 0x2: {
  OPC_SwitchField, 10, 2,                    // 141:   switch Inst[11:10] {
  0, 4,                                      // 144:   case 0x0: {
  OPC_Decode, 165, 3, 5,                     // 146:    decode to ANDRdRr using decoder 5
                                             // 146:   }
  1, 4,                                      // 150:   case 0x1: {
  OPC_Decode, 196, 3, 5,                     // 152:    decode to EORRdRr using decoder 5
                                             // 152:   }
  2, 4,                                      // 156:   case 0x2: {
  OPC_Decode, 227, 3, 5,                     // 158:    decode to ORRdRr using decoder 5
                                             // 158:   }
  3, 0,                                      // 162:   case 0x3: {
  OPC_Decode, 219, 3, 4,                     // 164:    decode to MOVRdRr using decoder 4
                                             // 164:   }
                                             // 164:   } // switch Inst[11:10]
                                             // 164:  }
  3, 0,                                      // 168:  case 0x3: {
  OPC_Decode, 186, 3, 6,                     // 170:   decode to CPIRdK using decoder 6
                                             // 170:  }
                                             // 170:  } // switch Inst[13:12]
                                             // 170: }
  1, 27,                                     // 174: case 0x1: {
  OPC_SwitchField, 12, 2,                    // 176:  switch Inst[13:12] {
  0, 4,                                      // 179:  case 0x0: {
  OPC_Decode, 236, 3, 7,                     // 181:   decode to SBCIRdK using decoder 7
                                             // 181:  }
  1, 4,                                      // 185:  case 0x1: {
  OPC_Decode, 253, 3, 7,                     // 187:   decode to SUBIRdK using decoder 7
                                             // 187:  }
  2, 4,                                      // 191:  case 0x2: {
  OPC_Decode, 226, 3, 7,                     // 193:   decode to ORIRdK using decoder 7
                                             // 193:  }
  3, 0,                                      // 197:  case 0x3: {
  OPC_Decode, 164, 3, 7,                     // 199:   decode to ANDIRdK using decoder 7
                                             // 199:  }
                                             // 199:  } // switch Inst[13:12]
                                             // 199: }
  2, 255, 3,                                 // 203: case 0x2: {
  OPC_SwitchField, 12, 1,                    // 206:  switch Inst[12] {
  0, 125,                                    // 209:  case 0x0: {
  OPC_SwitchField, 9, 1,                     // 211:   switch Inst[9] {
  0, 59,                                     // 214:   case 0x0: {
  OPC_Scope, 51,                             // 216:    try {
  OPC_SwitchField, 0, 2,                     // 218:     switch Inst[1:0] {
  0, 14,                                     // 221:     case 0x0: {
  OPC_CheckPredicate, 2,                     // 223:      check predicate 2
  OPC_CheckField, 13, 1, 0,                  // 225:      check Inst[13] == 0x0
  OPC_CheckField, 10, 2, 0,                  // 229:      check Inst[11:10] == 0x0
  OPC_Decode, 210, 3, 8,                     // 233:      decode to LDRdPtr using decoder 8
                                             // 233:     }
  1, 14,                                     // 237:     case 0x1: {
  OPC_CheckPredicate, 2,                     // 239:      check predicate 2
  OPC_CheckField, 13, 1, 0,                  // 241:      check Inst[13] == 0x0
  OPC_CheckField, 10, 2, 0,                  // 245:      check Inst[11:10] == 0x0
  OPC_Decode, 212, 3, 8,                     // 249:      decode to LDRdPtrPi using decoder 8
                                             // 249:     }
  2, 0,                                      // 253:     case 0x2: {
  OPC_CheckPredicate, 2,                     // 255:      check predicate 2
  OPC_CheckField, 13, 1, 0,                  // 257:      check Inst[13] == 0x0
  OPC_CheckField, 10, 2, 0,                  // 261:      check Inst[11:10] == 0x0
  OPC_Decode, 211, 3, 8,                     // 265:      decode to LDRdPtrPd using decoder 8
                                             // 265:     }
                                             // 265:     } // switch Inst[1:0]
                                             // 265:    } else try {
  OPC_CheckPredicate, 3,                     // 269:     check predicate 3
  OPC_Decode, 208, 3, 9,                     // 271:     decode to LDDRdPtrQ using decoder 9
                                             // 271:    }
                                             // 271:   }
  1, 0,                                      // 275:   case 0x1: {
  OPC_Scope, 51,                             // 277:    try {
  OPC_SwitchField, 0, 2,                     // 279:     switch Inst[1:0] {
  0, 14,                                     // 282:     case 0x0: {
  OPC_CheckPredicate, 2,                     // 284:      check predicate 2
  OPC_CheckField, 13, 1, 0,                  // 286:      check Inst[13] == 0x0
  OPC_CheckField, 10, 2, 0,                  // 290:      check Inst[11:10] == 0x0
  OPC_Decode, 250, 3, 8,                     // 294:      decode to STPtrRr using decoder 8
                                             // 294:     }
  1, 14,                                     // 298:     case 0x1: {
  OPC_CheckPredicate, 2,                     // 300:      check predicate 2
  OPC_CheckField, 13, 1, 0,                  // 302:      check Inst[13] == 0x0
  OPC_CheckField, 10, 2, 0,                  // 306:      check Inst[11:10] == 0x0
  OPC_Decode, 249, 3, 8,                     // 310:      decode to STPtrPiRr using decoder 8
                                             // 310:     }
  2, 0,                                      // 314:     case 0x2: {
  OPC_CheckPredicate, 2,                     // 316:      check predicate 2
  OPC_CheckField, 13, 1, 0,                  // 318:      check Inst[13] == 0x0
  OPC_CheckField, 10, 2, 0,                  // 322:      check Inst[11:10] == 0x0
  OPC_Decode, 248, 3, 8,                     // 326:      decode to STPtrPdRr using decoder 8
                                             // 326:     }
                                             // 326:     } // switch Inst[1:0]
                                             // 326:    } else try {
  OPC_CheckPredicate, 3,                     // 330:     check predicate 3
  OPC_Decode, 247, 3, 10,                    // 332:     decode to STDPtrQRr using decoder 10
                                             // 332:    }
                                             // 332:   }
                                             // 332:   } // switch Inst[9]
                                             // 332:  }
  1, 0,                                      // 336:  case 0x1: {
  OPC_SwitchField, 11, 1,                    // 338:   switch Inst[11] {
  0, 192, 2,                                 // 341:   case 0x0: {
  OPC_SwitchField, 13, 1,                    // 344:    switch Inst[13] {
  0, 180, 2,                                 // 347:    case 0x0: {
  OPC_SwitchField, 9, 2,                     // 350:     switch Inst[10:9] {
  0, 43,                                     // 353:     case 0x0: {
  OPC_SwitchField, 0, 4,                     // 355:      switch Inst[3:0] {
  4, 6,                                      // 358:      case 0x4: {
  OPC_CheckPredicate, 4,                     // 360:       check predicate 4
  OPC_Decode, 216, 3, 11,                    // 362:       decode to LPMRdZ using decoder 11
                                             // 362:      }
  5, 6,                                      // 366:      case 0x5: {
  OPC_CheckPredicate, 4,                     // 368:       check predicate 4
  OPC_Decode, 217, 3, 11,                    // 370:       decode to LPMRdZPi using decoder 11
                                             // 370:      }
  6, 6,                                      // 374:      case 0x6: {
  OPC_CheckPredicate, 5,                     // 376:       check predicate 5
  OPC_Decode, 194, 3, 11,                    // 378:       decode to ELPMRdZ using decoder 11
                                             // 378:      }
  7, 6,                                      // 382:      case 0x7: {
  OPC_CheckPredicate, 5,                     // 384:       check predicate 5
  OPC_Decode, 195, 3, 11,                    // 386:       decode to ELPMRdZPi using decoder 11
                                             // 386:      }
  15, 0,                                     // 390:      case 0xf: {
  OPC_CheckPredicate, 2,                     // 392:       check predicate 2
  OPC_Decode, 229, 3, 12,                    // 394:       decode to POPRd using decoder 12
                                             // 394:      }
                                             // 394:      } // switch Inst[3:0]
                                             // 394:     }
  1, 43,                                     // 398:     case 0x1: {
  OPC_SwitchField, 0, 4,                     // 400:      switch Inst[3:0] {
  4, 6,                                      // 403:      case 0x4: {
  OPC_CheckPredicate, 6,                     // 405:       check predicate 6
  OPC_Decode, 129, 4, 11,                    // 407:       decode to XCHZRd using decoder 11
                                             // 407:      }
  5, 6,                                      // 411:      case 0x5: {
  OPC_CheckPredicate, 6,                     // 413:       check predicate 6
  OPC_Decode, 206, 3, 11,                    // 415:       decode to LASZRd using decoder 11
                                             // 415:      }
  6, 6,                                      // 419:      case 0x6: {
  OPC_CheckPredicate, 6,                     // 421:       check predicate 6
  OPC_Decode, 205, 3, 11,                    // 423:       decode to LACZRd using decoder 11
                                             // 423:      }
  7, 6,                                      // 427:      case 0x7: {
  OPC_CheckPredicate, 6,                     // 429:       check predicate 6
  OPC_Decode, 207, 3, 11,                    // 431:       decode to LATZRd using decoder 11
                                             // 431:      }
  15, 0,                                     // 435:      case 0xf: {
  OPC_CheckPredicate, 2,                     // 437:       check predicate 2
  OPC_Decode, 230, 3, 12,                    // 439:       decode to PUSHRr using decoder 12
                                             // 439:      }
                                             // 439:      } // switch Inst[3:0]
                                             // 439:     }
  2, 191, 1,                                 // 443:     case 0x2: {
  OPC_SwitchField, 0, 4,                     // 446:      switch Inst[3:0] {
  0, 4,                                      // 449:      case 0x0: {
  OPC_Decode, 184, 3, 13,                    // 451:       decode to COMRd using decoder 13
                                             // 451:      }
  1, 4,                                      // 455:      case 0x1: {
  OPC_Decode, 224, 3, 13,                    // 457:       decode to NEGRd using decoder 13
                                             // 457:      }
  2, 4,                                      // 461:      case 0x2: {
  OPC_Decode, 255, 3, 13,                    // 463:       decode to SWAPRd using decoder 13
                                             // 463:      }
  3, 4,                                      // 467:      case 0x3: {
  OPC_Decode, 202, 3, 13,                    // 469:       decode to INCRd using decoder 13
                                             // 469:      }
  5, 4,                                      // 473:      case 0x5: {
  OPC_Decode, 166, 3, 13,                    // 475:       decode to ASRRd using decoder 13
                                             // 475:      }
  6, 4,                                      // 479:      case 0x6: {
  OPC_Decode, 218, 3, 13,                    // 481:       decode to LSRRd using decoder 13
                                             // 481:      }
  7, 4,                                      // 485:      case 0x7: {
  OPC_Decode, 235, 3, 13,                    // 487:       decode to RORRd using decoder 13
                                             // 487:      }
  8, 89,                                     // 491:      case 0x8: {
  OPC_SwitchField, 7, 2,                     // 493:       switch Inst[8:7] {
  0, 4,                                      // 496:       case 0x0: {
  OPC_Decode, 180, 3, 14,                    // 498:        decode to BSETs using decoder 14
                                             // 498:       }
  1, 4,                                      // 502:       case 0x1: {
  OPC_Decode, 167, 3, 14,                    // 504:        decode to BCLRs using decoder 14
                                             // 504:       }
  2, 15,                                     // 508:       case 0x2: {
  OPC_SwitchField, 4, 3,                     // 510:        switch Inst[6:4] {
  0, 4,                                      // 513:        case 0x0: {
  OPC_Decode, 232, 3, 0,                     // 515:         decode to RET using decoder 0
                                             // 515:        }
  1, 0,                                      // 519:        case 0x1: {
  OPC_Decode, 233, 3, 0,                     // 521:         decode to RETI using decoder 0
                                             // 521:        }
                                             // 521:        } // switch Inst[6:4]
                                             // 521:       }
  3, 0,                                      // 525:       case 0x3: {
  OPC_SwitchField, 4, 3,                     // 527:        switch Inst[6:4] {
  0, 4,                                      // 530:        case 0x0: {
  OPC_Decode, 244, 3, 0,                     // 532:         decode to SLEEP using decoder 0
                                             // 532:        }
  1, 6,                                      // 536:        case 0x1: {
  OPC_CheckPredicate, 7,                     // 538:         check predicate 7
  OPC_Decode, 171, 3, 0,                     // 540:         decode to BREAK using decoder 0
                                             // 540:        }
  2, 4,                                      // 544:        case 0x2: {
  OPC_Decode, 128, 4, 0,                     // 546:         decode to WDR using decoder 0
                                             // 546:        }
  4, 6,                                      // 550:        case 0x4: {
  OPC_CheckPredicate, 8,                     // 552:         check predicate 8
  OPC_Decode, 215, 3, 0,                     // 554:         decode to LPM using decoder 0
                                             // 554:        }
  5, 6,                                      // 558:        case 0x5: {
  OPC_CheckPredicate, 9,                     // 560:         check predicate 9
  OPC_Decode, 193, 3, 0,                     // 562:         decode to ELPM using decoder 0
                                             // 562:        }
  6, 6,                                      // 566:        case 0x6: {
  OPC_CheckPredicate, 10,                    // 568:         check predicate 10
  OPC_Decode, 245, 3, 0,                     // 570:         decode to SPM using decoder 0
                                             // 570:        }
  7, 0,                                      // 574:        case 0x7: {
  OPC_CheckPredicate, 11,                    // 576:         check predicate 11
  OPC_Decode, 246, 3, 15,                    // 578:         decode to SPMZPi using decoder 15
                                             // 578:        }
                                             // 578:        } // switch Inst[6:4]
                                             // 578:       }
                                             // 578:       } // switch Inst[8:7]
                                             // 578:      }
  9, 35,                                     // 582:      case 0x9: {
  OPC_SwitchField, 4, 5,                     // 584:       switch Inst[8:4] {
  0, 6,                                      // 587:       case 0x0: {
  OPC_CheckPredicate, 12,                    // 589:        check predicate 12
  OPC_Decode, 201, 3, 0,                     // 591:        decode to IJMP using decoder 0
                                             // 591:       }
  1, 6,                                      // 595:       case 0x1: {
  OPC_CheckPredicate, 13,                    // 597:        check predicate 13
  OPC_Decode, 192, 3, 0,                     // 599:        decode to EIJMP using decoder 0
                                             // 599:       }
  16, 6,                                     // 603:       case 0x10: {
  OPC_CheckPredicate, 12,                    // 605:        check predicate 12
  OPC_Decode, 200, 3, 0,                     // 607:        decode to ICALL using decoder 0
                                             // 607:       }
  17, 0,                                     // 611:       case 0x11: {
  OPC_CheckPredicate, 13,                    // 613:        check predicate 13
  OPC_Decode, 191, 3, 0,                     // 615:        decode to EICALL using decoder 0
                                             // 615:       }
                                             // 615:       } // switch Inst[8:4]
                                             // 615:      }
  10, 4,                                     // 619:      case 0xa: {
  OPC_Decode, 189, 3, 13,                    // 621:       decode to DECRd using decoder 13
                                             // 621:      }
  11, 0,                                     // 625:      case 0xb: {
  OPC_CheckPredicate, 14,                    // 627:       check predicate 14
  OPC_CheckField, 8, 1, 0,                   // 629:       check Inst[8] == 0x0
  OPC_Decode, 190, 3, 16,                    // 633:       decode to DESK using decoder 16
                                             // 633:      }
                                             // 633:      } // switch Inst[3:0]
                                             // 633:     }
  3, 0,                                      // 637:     case 0x3: {
  OPC_SwitchField, 8, 1,                     // 639:      switch Inst[8] {
  0, 6,                                      // 642:      case 0x0: {
  OPC_CheckPredicate, 15,                    // 644:       check predicate 15
  OPC_Decode, 163, 3, 17,                    // 646:       decode to ADIWRdK using decoder 17
                                             // 646:      }
  1, 0,                                      // 650:      case 0x1: {
  OPC_CheckPredicate, 15,                    // 652:       check predicate 15
  OPC_Decode, 241, 3, 17,                    // 654:       decode to SBIWRdK using decoder 17
                                             // 654:      }
                                             // 654:      } // switch Inst[8]
                                             // 654:     }
                                             // 654:     } // switch Inst[10:9]
                                             // 654:    }
  1, 0,                                      // 658:    case 0x1: {
  OPC_Decode, 203, 3, 18,                    // 660:     decode to INRdA using decoder 18
                                             // 660:    }
                                             // 660:    } // switch Inst[13]
                                             // 660:   }
  1, 0,                                      // 664:   case 0x1: {
  OPC_SwitchField, 13, 1,                    // 666:    switch Inst[13] {
  0, 40,                                     // 669:    case 0x0: {
  OPC_SwitchField, 10, 1,                    // 671:     switch Inst[10] {
  0, 27,                                     // 674:     case 0x0: {
  OPC_SwitchField, 8, 2,                     // 676:      switch Inst[9:8] {
  0, 4,                                      // 679:      case 0x0: {
  OPC_Decode, 183, 3, 19,                    // 681:       decode to CBIAb using decoder 19
                                             // 681:      }
  1, 4,                                      // 685:      case 0x1: {
  OPC_Decode, 239, 3, 19,                    // 687:       decode to SBICAb using decoder 19
                                             // 687:      }
  2, 4,                                      // 691:      case 0x2: {
  OPC_Decode, 238, 3, 19,                    // 693:       decode to SBIAb using decoder 19
                                             // 693:      }
  3, 0,                                      // 697:      case 0x3: {
  OPC_Decode, 240, 3, 19,                    // 699:       decode to SBISAb using decoder 19
                                             // 699:      }
                                             // 699:      } // switch Inst[9:8]
                                             // 699:     }
  1, 0,                                      // 703:     case 0x1: {
  OPC_CheckPredicate, 1,                     // 705:      check predicate 1
  OPC_Decode, 221, 3, 4,                     // 707:      decode to MULRdRr using decoder 4
                                             // 707:     }
                                             // 707:     } // switch Inst[10]
                                             // 707:    }
  1, 0,                                      // 711:    case 0x1: {
  OPC_Decode, 228, 3, 20,                    // 713:     decode to OUTARr using decoder 20
                                             // 713:    }
                                             // 713:    } // switch Inst[13]
                                             // 713:   }
                                             // 713:   } // switch Inst[11]
                                             // 713:  }
                                             // 713:  } // switch Inst[12]
                                             // 713: }
  3, 0,                                      // 717: case 0x3: {
  OPC_SwitchField, 12, 2,                    // 719:  switch Inst[13:12] {
  0, 4,                                      // 722:  case 0x0: {
  OPC_Decode, 234, 3, 21,                    // 724:   decode to RJMPk using decoder 21
                                             // 724:  }
  1, 4,                                      // 728:  case 0x1: {
  OPC_Decode, 231, 3, 21,                    // 730:   decode to RCALLk using decoder 21
                                             // 730:  }
  2, 4,                                      // 734:  case 0x2: {
  OPC_Decode, 209, 3, 6,                     // 736:   decode to LDIRdK using decoder 6
                                             // 736:  }
  3, 0,                                      // 740:  case 0x3: {
  OPC_SwitchField, 10, 2,                    // 742:   switch Inst[11:10] {
  0, 33,                                     // 745:   case 0x0: {
  OPC_Scope, 27,                             // 747:    try {
  OPC_SwitchField, 0, 3,                     // 749:     switch Inst[2:0] {
  0, 4,                                      // 752:     case 0x0: {
  OPC_Decode, 174, 3, 22,                    // 754:      decode to BRLOk using decoder 22
                                             // 754:     }
  1, 4,                                      // 758:     case 0x1: {
  OPC_Decode, 172, 3, 22,                    // 760:      decode to BREQk using decoder 22
                                             // 760:     }
  2, 4,                                      // 764:     case 0x2: {
  OPC_Decode, 176, 3, 22,                    // 766:      decode to BRMIk using decoder 22
                                             // 766:     }
  4, 0,                                      // 770:     case 0x4: {
  OPC_Decode, 175, 3, 22,                    // 772:      decode to BRLTk using decoder 22
                                             // 772:     }
                                             // 772:     } // switch Inst[2:0]
                                             // 772:    } else try {
  OPC_Decode, 170, 3, 23,                    // 776:     decode to BRBSsk using decoder 23
                                             // 776:    }
                                             // 776:   }
  1, 33,                                     // 780:   case 0x1: {
  OPC_Scope, 27,                             // 782:    try {
  OPC_SwitchField, 0, 3,                     // 784:     switch Inst[2:0] {
  0, 4,                                      // 787:     case 0x0: {
  OPC_Decode, 179, 3, 22,                    // 789:      decode to BRSHk using decoder 22
                                             // 789:     }
  1, 4,                                      // 793:     case 0x1: {
  OPC_Decode, 177, 3, 22,                    // 795:      decode to BRNEk using decoder 22
                                             // 795:     }
  2, 4,                                      // 799:     case 0x2: {
  OPC_Decode, 178, 3, 22,                    // 801:      decode to BRPLk using decoder 22
                                             // 801:     }
  4, 0,                                      // 805:     case 0x4: {
  OPC_Decode, 173, 3, 22,                    // 807:      decode to BRGEk using decoder 22
                                             // 807:     }
                                             // 807:     } // switch Inst[2:0]
                                             // 807:    } else try {
  OPC_Decode, 169, 3, 23,                    // 811:     decode to BRBCsk using decoder 23
                                             // 811:    }
                                             // 811:   }
  2, 23,                                     // 815:   case 0x2: {
  OPC_SwitchField, 9, 1,                     // 817:    switch Inst[9] {
  0, 8,                                      // 820:    case 0x0: {
  OPC_CheckField, 3, 1, 0,                   // 822:     check Inst[3] == 0x0
  OPC_Decode, 168, 3, 24,                    // 826:     decode to BLD using decoder 24
                                             // 826:    }
  1, 0,                                      // 830:    case 0x1: {
  OPC_CheckField, 3, 1, 0,                   // 832:     check Inst[3] == 0x0
  OPC_Decode, 181, 3, 25,                    // 836:     decode to BST using decoder 25
                                             // 836:    }
                                             // 836:    } // switch Inst[9]
                                             // 836:   }
  3, 0,                                      // 840:   case 0x3: {
  OPC_SwitchField, 9, 1,                     // 842:    switch Inst[9] {
  0, 8,                                      // 845:    case 0x0: {
  OPC_CheckField, 3, 1, 0,                   // 847:     check Inst[3] == 0x0
  OPC_Decode, 242, 3, 25,                    // 851:     decode to SBRCRrB using decoder 25
                                             // 851:    }
  1, 0,                                      // 855:    case 0x1: {
  OPC_CheckField, 3, 1, 0,                   // 857:     check Inst[3] == 0x0
  OPC_Decode, 243, 3, 25,                    // 861:     decode to SBRSRrB using decoder 25
                                             // 861:    }
                                             // 861:    } // switch Inst[9]
                                             // 861:   }
                                             // 861:   } // switch Inst[11:10]
                                             // 861:  }
                                             // 861:  } // switch Inst[13:12]
                                             // 861: }
                                             // 861: } // switch Inst[15:14]
};
static const uint8_t DecoderTableAVRTiny16[19] = {
  OPC_SwitchField, 11, 5,                    //  0: switch Inst[15:11] {
  20, 6,                                     //  3: case 0x14: {
  OPC_CheckPredicate, 16,                    //  5:  check predicate 16
  OPC_Decode, 214, 3, 26,                    //  7:  decode to LDSRdKTiny using decoder 26
                                             //  7: }
  21, 0,                                     // 11: case 0x15: {
  OPC_CheckPredicate, 16,                    // 13:  check predicate 16
  OPC_Decode, 252, 3, 27,                    // 15:  decode to STSKRrTiny using decoder 27
                                             // 15: }
                                             // 15: } // switch Inst[15:11]
};
static const uint8_t DecoderTable32[56] = {
  OPC_SwitchField, 17, 3,                    //  0: switch Inst[19:17] {
  0, 27,                                     //  3: case 0x0: {
  OPC_SwitchField, 25, 7,                    //  5:  switch Inst[31:25] {
  72, 10,                                    //  8:  case 0x48: {
  OPC_CheckPredicate, 3,                     // 10:   check predicate 3
  OPC_CheckField, 16, 1, 0,                  // 12:   check Inst[16] == 0x0
  OPC_Decode, 213, 3, 28,                    // 16:   decode to LDSRdK using decoder 28
                                             // 16:  }
  73, 0,                                     // 20:  case 0x49: {
  OPC_CheckPredicate, 3,                     // 22:   check predicate 3
  OPC_CheckField, 16, 1, 0,                  // 24:   check Inst[16] == 0x0
  OPC_Decode, 251, 3, 29,                    // 28:   decode to STSKRr using decoder 29
                                             // 28:  }
                                             // 28:  } // switch Inst[31:25]
                                             // 28: }
  6, 10,                                     // 32: case 0x6: {
  OPC_CheckPredicate, 17,                    // 34:  check predicate 17
  OPC_CheckField, 25, 7, 74,                 // 36:  check Inst[31:25] == 0x4a
  OPC_Decode, 204, 3, 30,                    // 40:  decode to JMPk using decoder 30
                                             // 40: }
  7, 0,                                      // 44: case 0x7: {
  OPC_CheckPredicate, 17,                    // 46:  check predicate 17
  OPC_CheckField, 25, 7, 74,                 // 48:  check Inst[31:25] == 0x4a
  OPC_Decode, 182, 3, 30,                    // 52:  decode to CALLk using decoder 30
                                             // 52: }
                                             // 52: } // switch Inst[19:17]
};
// Handling 31 cases.
template <typename InsnType>
static DecodeStatus decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) {
  DecodeComplete = true;
  using TmpType = std::conditional_t<std::is_integral<InsnType>::value, InsnType, uint64_t>;
  TmpType tmp;
  switch (Idx) {
  default: llvm_unreachable("Invalid decoder index!");
  case 0:
    return S;
  case 1:
    tmp = fieldFromInstruction(insn, 4, 4);
    if (!Check(S, DecodeDREGSRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 4);
    if (!Check(S, DecodeDREGSRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 2:
    tmp = fieldFromInstruction(insn, 4, 4);
    if (!Check(S, DecodeLD8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 4);
    if (!Check(S, DecodeLD8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 3:
    tmp = fieldFromInstruction(insn, 4, 3);
    if (!Check(S, DecodeLD8loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 3);
    if (!Check(S, DecodeLD8loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 4:
    tmp = fieldFromInstruction(insn, 4, 5);
    if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 4);
    tmp |= fieldFromInstruction(insn, 9, 1) << 4;
    if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 5:
    tmp = fieldFromInstruction(insn, 4, 5);
    if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 4, 5);
    if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 4);
    tmp |= fieldFromInstruction(insn, 9, 1) << 4;
    if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 6:
    tmp = fieldFromInstruction(insn, 4, 4);
    if (!Check(S, DecodeLD8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 4);
    tmp |= fieldFromInstruction(insn, 8, 4) << 4;
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 7:
    tmp = fieldFromInstruction(insn, 4, 4);
    if (!Check(S, DecodeLD8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 4, 4);
    if (!Check(S, DecodeLD8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 4);
    tmp |= fieldFromInstruction(insn, 8, 4) << 4;
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 8:
    if (!Check(S, decodeLoadStore(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 9:
    tmp = fieldFromInstruction(insn, 4, 5);
    if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 3);
    tmp |= fieldFromInstruction(insn, 3, 1) << 6;
    tmp |= fieldFromInstruction(insn, 10, 2) << 3;
    tmp |= fieldFromInstruction(insn, 13, 1) << 5;
    if (!Check(S, decodeMemri(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 10:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 3);
    tmp |= fieldFromInstruction(insn, 3, 1) << 6;
    tmp |= fieldFromInstruction(insn, 10, 2) << 3;
    tmp |= fieldFromInstruction(insn, 13, 1) << 5;
    if (!Check(S, decodeMemri(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 4, 5);
    if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 11:
    tmp = fieldFromInstruction(insn, 4, 5);
    if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    if (!Check(S, DecodeZREGRegisterClass(MI, Decoder)))
      return MCDisassembler::Fail;
    return S;
  case 12:
    tmp = fieldFromInstruction(insn, 4, 5);
    if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 13:
    tmp = fieldFromInstruction(insn, 4, 5);
    if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 4, 5);
    if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 14:
    tmp = fieldFromInstruction(insn, 4, 3);
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 15:
    if (!Check(S, DecodeZREGRegisterClass(MI, Decoder)))
      return MCDisassembler::Fail;
    return S;
  case 16:
    tmp = fieldFromInstruction(insn, 4, 4);
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 17:
    tmp = fieldFromInstruction(insn, 4, 2);
    if (!Check(S, DecodeIWREGSRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 4, 2);
    if (!Check(S, DecodeIWREGSRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 4);
    tmp |= fieldFromInstruction(insn, 6, 2) << 4;
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 18:
    tmp = fieldFromInstruction(insn, 4, 5);
    if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 4);
    tmp |= fieldFromInstruction(insn, 9, 2) << 4;
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 19:
    tmp = fieldFromInstruction(insn, 3, 5);
    MI.addOperand(MCOperand::createImm(tmp));
    tmp = fieldFromInstruction(insn, 0, 3);
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 20:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 4);
    tmp |= fieldFromInstruction(insn, 9, 2) << 4;
    MI.addOperand(MCOperand::createImm(tmp));
    tmp = fieldFromInstruction(insn, 4, 5);
    if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 21:
    tmp = fieldFromInstruction(insn, 0, 12);
    if (!Check(S, decodeRelCondBrTarget13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 22:
    tmp = fieldFromInstruction(insn, 3, 7);
    if (!Check(S, decodeRelCondBrTarget7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 23:
    tmp = fieldFromInstruction(insn, 0, 3);
    MI.addOperand(MCOperand::createImm(tmp));
    tmp = fieldFromInstruction(insn, 3, 7);
    if (!Check(S, decodeRelCondBrTarget7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 24:
    tmp = fieldFromInstruction(insn, 4, 5);
    if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 4, 5);
    if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 3);
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 25:
    tmp = fieldFromInstruction(insn, 4, 5);
    if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 3);
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 26:
    tmp = fieldFromInstruction(insn, 4, 4);
    if (!Check(S, DecodeLD8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 4);
    tmp |= fieldFromInstruction(insn, 8, 3) << 4;
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 27:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 4);
    tmp |= fieldFromInstruction(insn, 8, 3) << 4;
    MI.addOperand(MCOperand::createImm(tmp));
    tmp = fieldFromInstruction(insn, 4, 4);
    if (!Check(S, DecodeLD8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 28:
    tmp = fieldFromInstruction(insn, 20, 5);
    if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 29:
    tmp = fieldFromInstruction(insn, 0, 16);
    MI.addOperand(MCOperand::createImm(tmp));
    tmp = fieldFromInstruction(insn, 20, 5);
    if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 30:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 17);
    tmp |= fieldFromInstruction(insn, 20, 5) << 17;
    if (!Check(S, decodeCallTarget(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  }
}
static bool checkDecoderPredicate(unsigned Idx, const FeatureBitset &FB) {
  switch (Idx) {
  default: llvm_unreachable("Invalid index!");
  case 0:
    return FB[AVR::FeatureMOVW];
  case 1:
    return FB[AVR::FeatureMultiplication];
  case 2:
    return FB[AVR::FeatureSRAM];
  case 3:
    return FB[AVR::FeatureSRAM] && !FB[AVR::FeatureTinyEncoding];
  case 4:
    return FB[AVR::FeatureLPMX];
  case 5:
    return FB[AVR::FeatureELPMX];
  case 6:
    return FB[AVR::FeatureRMW];
  case 7:
    return FB[AVR::FeatureBREAK];
  case 8:
    return FB[AVR::FeatureLPM];
  case 9:
    return FB[AVR::FeatureELPM];
  case 10:
    return FB[AVR::FeatureSPM];
  case 11:
    return FB[AVR::FeatureSPMX];
  case 12:
    return FB[AVR::FeatureIJMPCALL];
  case 13:
    return FB[AVR::FeatureEIJMPCALL];
  case 14:
    return FB[AVR::FeatureDES];
  case 15:
    return FB[AVR::FeatureADDSUBIW];
  case 16:
    return FB[AVR::FeatureSRAM] && FB[AVR::FeatureTinyEncoding];
  case 17:
    return FB[AVR::FeatureJMPCALL];
  }
}


template <typename InsnType>
static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
                                      InsnType insn, uint64_t Address,
                                      const MCDisassembler *DisAsm,
                                      const MCSubtargetInfo &STI) {
  const FeatureBitset &Bits = STI.getFeatureBits();
  const uint8_t *Ptr = DecodeTable;

  SmallVector<const uint8_t *, 8> ScopeStack;
  DecodeStatus S = MCDisassembler::Success;
  while (true) {
    ptrdiff_t Loc = Ptr - DecodeTable;
    const uint8_t DecoderOp = *Ptr++;
    switch (DecoderOp) {
    default:
      errs() << Loc << ": Unexpected decode table opcode: "
             << (int)DecoderOp << '\n';
      return MCDisassembler::Fail;
    case OPC_Scope: {
      unsigned NumToSkip = decodeULEB128AndIncUnsafe(Ptr);
      const uint8_t *SkipTo = Ptr + NumToSkip;
      ScopeStack.push_back(SkipTo);
      LLVM_DEBUG(dbgs() << Loc << ": OPC_Scope(" << SkipTo - DecodeTable
                        << ")\n");
      continue;
    }
    case OPC_SwitchField: {
      // Decode the start value.
      unsigned Start = decodeULEB128AndIncUnsafe(Ptr);
      unsigned Len = *Ptr++;
      uint64_t FieldValue = fieldFromInstruction(insn, Start, Len);
      uint64_t CaseValue;
      unsigned CaseSize;
      while (true) {
        CaseValue = decodeULEB128AndIncUnsafe(Ptr);
        CaseSize = decodeULEB128AndIncUnsafe(Ptr);
        if (FieldValue == CaseValue || !CaseSize)
          break;
        Ptr += CaseSize;
      }
      if (FieldValue == CaseValue) {
        LLVM_DEBUG(dbgs() << Loc << ": OPC_SwitchField(" << Start << ", " << Len
                          << "): " << FieldValue << '\n');
        continue;
      }
      break;
    }
    case OPC_CheckField: {
      // Decode the start value.
      unsigned Start = decodeULEB128AndIncUnsafe(Ptr);
      unsigned Len = *Ptr;
      uint64_t FieldValue = fieldFromInstruction(insn, Start, Len);
      // Decode the field value.
      unsigned PtrLen = 0;
      uint64_t ExpectedValue = decodeULEB128(++Ptr, &PtrLen);
      Ptr += PtrLen;
      bool Failed = ExpectedValue != FieldValue;

      LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckField(" << Start << ", " << Len
                        << ", " << ExpectedValue << "): FieldValue = "
                        << FieldValue << ", ExpectedValue = " << ExpectedValue
                        << ": " << (Failed ? "FAIL, " : "PASS\n"););
      if (!Failed)
        continue;
      break;
    }
    case OPC_CheckPredicate: {
      // Decode the Predicate Index value.
      unsigned PIdx = decodeULEB128AndIncUnsafe(Ptr);
      // Check the predicate.
      bool Failed = !checkDecoderPredicate(PIdx, Bits);

      LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckPredicate(" << PIdx << "): "
                        << (Failed ? "FAIL, " : "PASS\n"););
      if (!Failed)
        continue;
      break;
    }
    case OPC_Decode: {
      // Decode the Opcode value.
      unsigned Opc = decodeULEB128AndIncUnsafe(Ptr);
      unsigned DecodeIdx = decodeULEB128AndIncUnsafe(Ptr);

      MI.clear();
      MI.setOpcode(Opc);
      bool DecodeComplete;
      S = decodeToMCInst(DecodeIdx, S, insn, MI, Address, DisAsm,
                         DecodeComplete);
      LLVM_DEBUG(dbgs() << Loc << ": OPC_Decode: opcode " << Opc
                        << ", using decoder " << DecodeIdx << ": "
                        << (S ? "PASS, " : "FAIL, "));

      if (DecodeComplete) {
        LLVM_DEBUG(dbgs() << "decoding complete\n");
        return S;
      }
      assert(S == MCDisassembler::Fail);
      // Reset decode status. This also drops a SoftFail status that could be
      // set before the decode attempt.
      S = MCDisassembler::Success;
      break;
    }
    }
    if (ScopeStack.empty()) {
      LLVM_DEBUG(dbgs() << "returning Fail\n");
      return MCDisassembler::Fail;
    }
    Ptr = ScopeStack.pop_back_val();
    LLVM_DEBUG(dbgs() << "continuing at " << Ptr - DecodeTable << '\n');
  }
  llvm_unreachable("bogosity detected in disassembler state machine!");
}


} // namespace
