/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|*  * Lanai Disassembler                                                      *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/DataTypes.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/LEB128.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/TargetParser/SubtargetFeature.h"
#include <assert.h>

namespace {

// InsnBitWidth is essentially a type trait used by the decoder emitter to query
// the supported bitwidth for a given type. But default, the value is 0, making
// it an invalid type for use as `InsnType` when instantiating the decoder.
// Individual targets are expected to provide specializations for these based
// on their usage.
template <typename T> constexpr uint32_t InsnBitWidth = 0;

static const uint8_t DecoderTableLanai32[743] = {
  OPC_SwitchField, 28, 4,                    //   0: switch Inst[31:28] {
  0, 92,                                     //   3: case 0x0: {
  OPC_SwitchField, 16, 2,                    //   5:  switch Inst[17:16] {
  0, 69,                                     //   8:  case 0x0: {
  OPC_Scope, 63,                             //  10:   try {
  OPC_SwitchField, 0, 16,                    //  12:    switch Inst[15:0] {
  1, 8,                                      //  15:    case 0x1: {
  OPC_CheckField, 18, 10, 0,                 //  17:     check Inst[27:18] == 0x0
  OPC_Decode, 242, 2, 0,                     //  21:     decode to NOP using decoder 0
                                             //  21:    }
  2, 8,                                      //  25:    case 0x2: {
  OPC_CheckField, 18, 10, 0,                 //  27:     check Inst[27:18] == 0x0
  OPC_Decode, 236, 2, 0,                     //  31:     decode to LOG0 using decoder 0
                                             //  31:    }
  3, 8,                                      //  35:    case 0x3: {
  OPC_CheckField, 18, 10, 0,                 //  37:     check Inst[27:18] == 0x0
  OPC_Decode, 237, 2, 0,                     //  41:     decode to LOG1 using decoder 0
                                             //  41:    }
  4, 8,                                      //  45:    case 0x4: {
  OPC_CheckField, 18, 10, 0,                 //  47:     check Inst[27:18] == 0x0
  OPC_Decode, 238, 2, 0,                     //  51:     decode to LOG2 using decoder 0
                                             //  51:    }
  5, 8,                                      //  55:    case 0x5: {
  OPC_CheckField, 18, 10, 0,                 //  57:     check Inst[27:18] == 0x0
  OPC_Decode, 239, 2, 0,                     //  61:     decode to LOG3 using decoder 0
                                             //  61:    }
  6, 0,                                      //  65:    case 0x6: {
  OPC_CheckField, 18, 10, 0,                 //  67:     check Inst[27:18] == 0x0
  OPC_Decode, 240, 2, 0,                     //  71:     decode to LOG4 using decoder 0
                                             //  71:    }
                                             //  71:    } // switch Inst[15:0]
                                             //  71:   } else try {
  OPC_Decode, 209, 2, 1,                     //  75:    decode to ADD_I_LO using decoder 1
                                             //  75:   }
                                             //  75:  }
  1, 4,                                      //  79:  case 0x1: {
  OPC_Decode, 208, 2, 1,                     //  81:   decode to ADD_I_HI using decoder 1
                                             //  81:  }
  2, 4,                                      //  85:  case 0x2: {
  OPC_Decode, 206, 2, 1,                     //  87:   decode to ADD_F_I_LO using decoder 1
                                             //  87:  }
  3, 0,                                      //  91:  case 0x3: {
  OPC_Decode, 205, 2, 1,                     //  93:   decode to ADD_F_I_HI using decoder 1
                                             //  93:  }
                                             //  93:  } // switch Inst[17:16]
                                             //  93: }
  1, 27,                                     //  97: case 0x1: {
  OPC_SwitchField, 16, 2,                    //  99:  switch Inst[17:16] {
  0, 4,                                      // 102:  case 0x0: {
  OPC_Decode, 203, 2, 1,                     // 104:   decode to ADDC_I_LO using decoder 1
                                             // 104:  }
  1, 4,                                      // 108:  case 0x1: {
  OPC_Decode, 202, 2, 1,                     // 110:   decode to ADDC_I_HI using decoder 1
                                             // 110:  }
  2, 4,                                      // 114:  case 0x2: {
  OPC_Decode, 200, 2, 1,                     // 116:   decode to ADDC_F_I_LO using decoder 1
                                             // 116:  }
  3, 0,                                      // 120:  case 0x3: {
  OPC_Decode, 199, 2, 1,                     // 122:   decode to ADDC_F_I_HI using decoder 1
                                             // 122:  }
                                             // 122:  } // switch Inst[17:16]
                                             // 122: }
  2, 27,                                     // 126: case 0x2: {
  OPC_SwitchField, 16, 2,                    // 128:  switch Inst[17:16] {
  0, 4,                                      // 131:  case 0x0: {
  OPC_Decode, 154, 3, 1,                     // 133:   decode to SUB_I_LO using decoder 1
                                             // 133:  }
  1, 4,                                      // 137:  case 0x1: {
  OPC_Decode, 153, 3, 1,                     // 139:   decode to SUB_I_HI using decoder 1
                                             // 139:  }
  2, 4,                                      // 143:  case 0x2: {
  OPC_Decode, 151, 3, 1,                     // 145:   decode to SUB_F_I_LO using decoder 1
                                             // 145:  }
  3, 0,                                      // 149:  case 0x3: {
  OPC_Decode, 150, 3, 1,                     // 151:   decode to SUB_F_I_HI using decoder 1
                                             // 151:  }
                                             // 151:  } // switch Inst[17:16]
                                             // 151: }
  3, 27,                                     // 155: case 0x3: {
  OPC_SwitchField, 16, 2,                    // 157:  switch Inst[17:16] {
  0, 4,                                      // 160:  case 0x0: {
  OPC_Decode, 148, 3, 1,                     // 162:   decode to SUBB_I_LO using decoder 1
                                             // 162:  }
  1, 4,                                      // 166:  case 0x1: {
  OPC_Decode, 147, 3, 1,                     // 168:   decode to SUBB_I_HI using decoder 1
                                             // 168:  }
  2, 4,                                      // 172:  case 0x2: {
  OPC_Decode, 145, 3, 1,                     // 174:   decode to SUBB_F_I_LO using decoder 1
                                             // 174:  }
  3, 0,                                      // 178:  case 0x3: {
  OPC_Decode, 144, 3, 1,                     // 180:   decode to SUBB_F_I_HI using decoder 1
                                             // 180:  }
                                             // 180:  } // switch Inst[17:16]
                                             // 180: }
  4, 27,                                     // 184: case 0x4: {
  OPC_SwitchField, 16, 2,                    // 186:  switch Inst[17:16] {
  0, 4,                                      // 189:  case 0x0: {
  OPC_Decode, 215, 2, 1,                     // 191:   decode to AND_I_LO using decoder 1
                                             // 191:  }
  1, 4,                                      // 195:  case 0x1: {
  OPC_Decode, 214, 2, 1,                     // 197:   decode to AND_I_HI using decoder 1
                                             // 197:  }
  2, 4,                                      // 201:  case 0x2: {
  OPC_Decode, 212, 2, 1,                     // 203:   decode to AND_F_I_LO using decoder 1
                                             // 203:  }
  3, 0,                                      // 207:  case 0x3: {
  OPC_Decode, 211, 2, 1,                     // 209:   decode to AND_F_I_HI using decoder 1
                                             // 209:  }
                                             // 209:  } // switch Inst[17:16]
                                             // 209: }
  5, 27,                                     // 213: case 0x5: {
  OPC_SwitchField, 16, 2,                    // 215:  switch Inst[17:16] {
  0, 4,                                      // 218:  case 0x0: {
  OPC_Decode, 247, 2, 1,                     // 220:   decode to OR_I_LO using decoder 1
                                             // 220:  }
  1, 4,                                      // 224:  case 0x1: {
  OPC_Decode, 246, 2, 1,                     // 226:   decode to OR_I_HI using decoder 1
                                             // 226:  }
  2, 4,                                      // 230:  case 0x2: {
  OPC_Decode, 244, 2, 1,                     // 232:   decode to OR_F_I_LO using decoder 1
                                             // 232:  }
  3, 0,                                      // 236:  case 0x3: {
  OPC_Decode, 243, 2, 1,                     // 238:   decode to OR_F_I_HI using decoder 1
                                             // 238:  }
                                             // 238:  } // switch Inst[17:16]
                                             // 238: }
  6, 27,                                     // 242: case 0x6: {
  OPC_SwitchField, 16, 2,                    // 244:  switch Inst[17:16] {
  0, 4,                                      // 247:  case 0x0: {
  OPC_Decode, 163, 3, 1,                     // 249:   decode to XOR_I_LO using decoder 1
                                             // 249:  }
  1, 4,                                      // 253:  case 0x1: {
  OPC_Decode, 162, 3, 1,                     // 255:   decode to XOR_I_HI using decoder 1
                                             // 255:  }
  2, 4,                                      // 259:  case 0x2: {
  OPC_Decode, 160, 3, 1,                     // 261:   decode to XOR_F_I_LO using decoder 1
                                             // 261:  }
  3, 0,                                      // 265:  case 0x3: {
  OPC_Decode, 159, 3, 1,                     // 267:   decode to XOR_F_I_HI using decoder 1
                                             // 267:  }
                                             // 267:  } // switch Inst[17:16]
                                             // 267: }
  7, 27,                                     // 271: case 0x7: {
  OPC_SwitchField, 16, 2,                    // 273:  switch Inst[17:16] {
  0, 4,                                      // 276:  case 0x0: {
  OPC_Decode, 134, 3, 2,                     // 278:   decode to SL_I using decoder 2
                                             // 278:  }
  1, 4,                                      // 282:  case 0x1: {
  OPC_Decode, 252, 2, 2,                     // 284:   decode to SA_I using decoder 2
                                             // 284:  }
  2, 4,                                      // 288:  case 0x2: {
  OPC_Decode, 133, 3, 2,                     // 290:   decode to SL_F_I using decoder 2
                                             // 290:  }
  3, 0,                                      // 294:  case 0x3: {
  OPC_Decode, 251, 2, 2,                     // 296:   decode to SA_F_I using decoder 2
                                             // 296:  }
                                             // 296:  } // switch Inst[17:16]
                                             // 296: }
  8, 17,                                     // 300: case 0x8: {
  OPC_Scope, 11,                             // 302:  try {
  OPC_CheckField, 0, 28, 252, 255, 219, 8,   // 304:   check Inst[27:0] == 0x116fffc
  OPC_Decode, 250, 2, 0,                     // 311:   decode to RET using decoder 0
                                             // 311:  } else try {
  OPC_Decode, 232, 2, 3,                     // 315:   decode to LDW_RI using decoder 3
                                             // 315:  }
                                             // 315: }
  9, 4,                                      // 319: case 0x9: {
  OPC_Decode, 156, 3, 3,                     // 321:  decode to SW_RI using decoder 3
                                             // 321: }
  10, 39,                                    // 325: case 0xa: {
  OPC_SwitchField, 0, 3,                     // 327:  switch Inst[2:0] {
  0, 4,                                      // 330:  case 0x0: {
  OPC_Decode, 229, 2, 4,                     // 332:   decode to LDHs_RR using decoder 4
                                             // 332:  }
  1, 4,                                      // 336:  case 0x1: {
  OPC_Decode, 231, 2, 4,                     // 338:   decode to LDHz_RR using decoder 4
                                             // 338:  }
  2, 4,                                      // 342:  case 0x2: {
  OPC_Decode, 233, 2, 4,                     // 344:   decode to LDW_RR using decoder 4
                                             // 344:  }
  3, 4,                                      // 348:  case 0x3: {
  OPC_Decode, 234, 2, 4,                     // 350:   decode to LDWz_RR using decoder 4
                                             // 350:  }
  4, 4,                                      // 354:  case 0x4: {
  OPC_Decode, 225, 2, 4,                     // 356:   decode to LDBs_RR using decoder 4
                                             // 356:  }
  5, 0,                                      // 360:  case 0x5: {
  OPC_Decode, 227, 2, 4,                     // 362:   decode to LDBz_RR using decoder 4
                                             // 362:  }
                                             // 362:  } // switch Inst[2:0]
                                             // 362: }
  11, 21,                                    // 366: case 0xb: {
  OPC_SwitchField, 0, 3,                     // 368:  switch Inst[2:0] {
  0, 4,                                      // 371:  case 0x0: {
  OPC_Decode, 143, 3, 4,                     // 373:   decode to STH_RR using decoder 4
                                             // 373:  }
  2, 4,                                      // 377:  case 0x2: {
  OPC_Decode, 157, 3, 4,                     // 379:   decode to SW_RR using decoder 4
                                             // 379:  }
  4, 0,                                      // 383:  case 0x4: {
  OPC_Decode, 141, 3, 4,                     // 385:   decode to STB_RR using decoder 4
                                             // 385:  }
                                             // 385:  } // switch Inst[2:0]
                                             // 385: }
  12, 214, 1,                                // 389: case 0xc: {
  OPC_SwitchField, 3, 8,                     // 392:  switch Inst[10:3] {
  0, 15,                                     // 395:  case 0x0: {
  OPC_SwitchField, 17, 1,                    // 397:   switch Inst[17] {
  0, 4,                                      // 400:   case 0x0: {
  OPC_Decode, 210, 2, 5,                     // 402:    decode to ADD_R using decoder 5
                                             // 402:   }
  1, 0,                                      // 406:   case 0x1: {
  OPC_Decode, 207, 2, 5,                     // 408:    decode to ADD_F_R using decoder 5
                                             // 408:   }
                                             // 408:   } // switch Inst[17]
                                             // 408:  }
  32, 15,                                    // 412:  case 0x20: {
  OPC_SwitchField, 17, 1,                    // 414:   switch Inst[17] {
  0, 4,                                      // 417:   case 0x0: {
  OPC_Decode, 204, 2, 5,                     // 419:    decode to ADDC_R using decoder 5
                                             // 419:   }
  1, 0,                                      // 423:   case 0x1: {
  OPC_Decode, 201, 2, 5,                     // 425:    decode to ADDC_F_R using decoder 5
                                             // 425:   }
                                             // 425:   } // switch Inst[17]
                                             // 425:  }
  64, 15,                                    // 429:  case 0x40: {
  OPC_SwitchField, 17, 1,                    // 431:   switch Inst[17] {
  0, 4,                                      // 434:   case 0x0: {
  OPC_Decode, 155, 3, 5,                     // 436:    decode to SUB_R using decoder 5
                                             // 436:   }
  1, 0,                                      // 440:   case 0x1: {
  OPC_Decode, 152, 3, 5,                     // 442:    decode to SUB_F_R using decoder 5
                                             // 442:   }
                                             // 442:   } // switch Inst[17]
                                             // 442:  }
  96, 15,                                    // 446:  case 0x60: {
  OPC_SwitchField, 17, 1,                    // 448:   switch Inst[17] {
  0, 4,                                      // 451:   case 0x0: {
  OPC_Decode, 149, 3, 5,                     // 453:    decode to SUBB_R using decoder 5
                                             // 453:   }
  1, 0,                                      // 457:   case 0x1: {
  OPC_Decode, 146, 3, 5,                     // 459:    decode to SUBB_F_R using decoder 5
                                             // 459:   }
                                             // 459:   } // switch Inst[17]
                                             // 459:  }
  128, 1, 15,                                // 463:  case 0x80: {
  OPC_SwitchField, 17, 1,                    // 466:   switch Inst[17] {
  0, 4,                                      // 469:   case 0x0: {
  OPC_Decode, 216, 2, 5,                     // 471:    decode to AND_R using decoder 5
                                             // 471:   }
  1, 0,                                      // 475:   case 0x1: {
  OPC_Decode, 213, 2, 5,                     // 477:    decode to AND_F_R using decoder 5
                                             // 477:   }
                                             // 477:   } // switch Inst[17]
                                             // 477:  }
  160, 1, 57,                                // 481:  case 0xa0: {
  OPC_SwitchField, 17, 1,                    // 484:   switch Inst[17] {
  0, 46,                                     // 487:   case 0x0: {
  OPC_Scope, 16,                             // 489:    try {
  OPC_CheckField, 0, 3, 0,                   // 491:     check Inst[2:0] == 0x0
  OPC_CheckField, 18, 10, 64,                // 495:     check Inst[27:18] == 0x40
  OPC_CheckField, 16, 1, 0,                  // 499:     check Inst[16] == 0x0
  OPC_Decode, 222, 2, 6,                     // 503:     decode to JR using decoder 6
  OPC_Scope, 12,                             // 507:    } else try {
  OPC_CheckField, 11, 5, 0,                  // 509:     check Inst[15:11] == 0x0
  OPC_CheckField, 23, 5, 2,                  // 513:     check Inst[27:23] == 0x2
  OPC_Decode, 218, 2, 7,                     // 517:     decode to BRIND_CC using decoder 7
  OPC_Scope, 8,                              // 521:    } else try {
  OPC_CheckField, 23, 5, 2,                  // 523:     check Inst[27:23] == 0x2
  OPC_Decode, 219, 2, 8,                     // 527:     decode to BRIND_CCA using decoder 8
                                             // 527:    } else try {
  OPC_Decode, 248, 2, 5,                     // 531:     decode to OR_R using decoder 5
                                             // 531:    }
                                             // 531:   }
  1, 0,                                      // 535:   case 0x1: {
  OPC_Decode, 245, 2, 5,                     // 537:    decode to OR_F_R using decoder 5
                                             // 537:   }
                                             // 537:   } // switch Inst[17]
                                             // 537:  }
  192, 1, 15,                                // 541:  case 0xc0: {
  OPC_SwitchField, 17, 1,                    // 544:   switch Inst[17] {
  0, 4,                                      // 547:   case 0x0: {
  OPC_Decode, 164, 3, 5,                     // 549:    decode to XOR_R using decoder 5
                                             // 549:   }
  1, 0,                                      // 553:   case 0x1: {
  OPC_Decode, 161, 3, 5,                     // 555:    decode to XOR_F_R using decoder 5
                                             // 555:   }
                                             // 555:   } // switch Inst[17]
                                             // 555:  }
  224, 1, 8,                                 // 559:  case 0xe0: {
  OPC_CheckField, 17, 1, 0,                  // 562:   check Inst[17] == 0x0
  OPC_Decode, 254, 2, 9,                     // 566:   decode to SELECT using decoder 9
                                             // 566:  }
  240, 1, 15,                                // 570:  case 0xf0: {
  OPC_SwitchField, 17, 1,                    // 573:   switch Inst[17] {
  0, 4,                                      // 576:   case 0x0: {
  OPC_Decode, 131, 3, 5,                     // 578:    decode to SHL_R using decoder 5
                                             // 578:   }
  1, 0,                                      // 582:   case 0x1: {
  OPC_Decode, 130, 3, 5,                     // 584:    decode to SHL_F_R using decoder 5
                                             // 584:   }
                                             // 584:   } // switch Inst[17]
                                             // 584:  }
  248, 1, 0,                                 // 588:  case 0xf8: {
  OPC_SwitchField, 17, 1,                    // 591:   switch Inst[17] {
  0, 4,                                      // 594:   case 0x0: {
  OPC_Decode, 136, 3, 5,                     // 596:    decode to SRA_R using decoder 5
                                             // 596:   }
  1, 0,                                      // 600:   case 0x1: {
  OPC_Decode, 135, 3, 5,                     // 602:    decode to SRA_F_R using decoder 5
                                             // 602:   }
                                             // 602:   } // switch Inst[17]
                                             // 602:  }
                                             // 602:  } // switch Inst[10:3]
                                             // 602: }
  13, 21,                                    // 606: case 0xd: {
  OPC_SwitchField, 0, 18,                    // 608:  switch Inst[17:0] {
  1, 4,                                      // 611:  case 0x1: {
  OPC_Decode, 249, 2, 10,                    // 613:   decode to POPC using decoder 10
                                             // 613:  }
  2, 4,                                      // 617:  case 0x2: {
  OPC_Decode, 235, 2, 10,                    // 619:   decode to LEADZ using decoder 10
                                             // 619:  }
  3, 0,                                      // 623:  case 0x3: {
  OPC_Decode, 158, 3, 10,                    // 625:   decode to TRAILZ using decoder 10
                                             // 625:  }
                                             // 625:  } // switch Inst[17:0]
                                             // 625: }
  14, 48,                                    // 629: case 0xe: {
  OPC_SwitchField, 1, 1,                     // 631:  switch Inst[1] {
  0, 18,                                     // 634:  case 0x0: {
  OPC_Scope, 12,                             // 636:   try {
  OPC_CheckField, 0, 1, 0,                   // 638:    check Inst[0] == 0x0
  OPC_CheckField, 25, 3, 0,                  // 642:    check Inst[27:25] == 0x0
  OPC_Decode, 221, 2, 11,                    // 646:    decode to BT using decoder 11
                                             // 646:   } else try {
  OPC_Decode, 217, 2, 12,                    // 650:    decode to BRCC using decoder 12
                                             // 650:   }
                                             // 650:  }
  1, 0,                                      // 654:  case 0x1: {
  OPC_SwitchField, 23, 2,                    // 656:   switch Inst[24:23] {
  0, 8,                                      // 659:   case 0x0: {
  OPC_CheckField, 2, 16, 0,                  // 661:    check Inst[17:2] == 0x0
  OPC_Decode, 253, 2, 13,                    // 665:    decode to SCC using decoder 13
                                             // 665:   }
  2, 0,                                      // 669:   case 0x2: {
  OPC_CheckField, 16, 7, 0,                  // 671:    check Inst[22:16] == 0x0
  OPC_Decode, 220, 2, 14,                    // 675:    decode to BRR using decoder 14
                                             // 675:   }
                                             // 675:   } // switch Inst[24:23]
                                             // 675:  }
                                             // 675:  } // switch Inst[1]
                                             // 675: }
  15, 0,                                     // 679: case 0xf: {
  OPC_SwitchField, 16, 2,                    // 681:  switch Inst[17:16] {
  0, 4,                                      // 684:  case 0x0: {
  OPC_Decode, 223, 2, 15,                    // 686:   decode to LDADDR using decoder 15
                                             // 686:  }
  1, 4,                                      // 690:  case 0x1: {
  OPC_Decode, 139, 3, 15,                    // 692:   decode to STADDR using decoder 15
                                             // 692:  }
  2, 4,                                      // 696:  case 0x2: {
  OPC_Decode, 132, 3, 15,                    // 698:   decode to SLI using decoder 15
                                             // 698:  }
  3, 0,                                      // 702:  case 0x3: {
  OPC_SwitchField, 12, 4,                    // 704:   switch Inst[15:12] {
  0, 4,                                      // 707:   case 0x0: {
  OPC_Decode, 228, 2, 16,                    // 709:    decode to LDHs_RI using decoder 16
                                             // 709:   }
  1, 4,                                      // 713:   case 0x1: {
  OPC_Decode, 230, 2, 16,                    // 715:    decode to LDHz_RI using decoder 16
                                             // 715:   }
  2, 4,                                      // 719:   case 0x2: {
  OPC_Decode, 142, 3, 16,                    // 721:    decode to STH_RI using decoder 16
                                             // 721:   }
  4, 4,                                      // 725:   case 0x4: {
  OPC_Decode, 224, 2, 16,                    // 727:    decode to LDBs_RI using decoder 16
                                             // 727:   }
  5, 4,                                      // 731:   case 0x5: {
  OPC_Decode, 226, 2, 16,                    // 733:    decode to LDBz_RI using decoder 16
                                             // 733:   }
  6, 0,                                      // 737:   case 0x6: {
  OPC_Decode, 140, 3, 16,                    // 739:    decode to STB_RI using decoder 16
                                             // 739:   }
                                             // 739:   } // switch Inst[15:12]
                                             // 739:  }
                                             // 739:  } // switch Inst[17:16]
                                             // 739: }
                                             // 739: } // switch Inst[31:28]
};
// Handling 17 cases.
template <typename InsnType>
static DecodeStatus decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) {
  DecodeComplete = true;
  using TmpType = std::conditional_t<std::is_integral<InsnType>::value, InsnType, uint64_t>;
  TmpType tmp;
  switch (Idx) {
  default: llvm_unreachable("Invalid decoder index!");
  case 0:
    return S;
  case 1:
    tmp = fieldFromInstruction(insn, 23, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 18, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 2:
    tmp = fieldFromInstruction(insn, 23, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 18, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    if (!Check(S, decodeShiftImm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 3:
    tmp = fieldFromInstruction(insn, 23, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 23);
    if (!Check(S, decodeRiMemoryValue(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 4:
    tmp = fieldFromInstruction(insn, 23, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 3, 8);
    tmp |= fieldFromInstruction(insn, 11, 5) << 10;
    tmp |= fieldFromInstruction(insn, 16, 2) << 8;
    tmp |= fieldFromInstruction(insn, 18, 5) << 15;
    if (!Check(S, decodeRrMemoryValue(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 5:
    tmp = fieldFromInstruction(insn, 23, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 18, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 3) << 1;
    tmp |= fieldFromInstruction(insn, 16, 1);
    if (!Check(S, decodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 6:
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 7:
    tmp = fieldFromInstruction(insn, 18, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 3) << 1;
    tmp |= fieldFromInstruction(insn, 16, 1);
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 8:
    tmp = fieldFromInstruction(insn, 18, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 3) << 1;
    tmp |= fieldFromInstruction(insn, 16, 1);
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 9:
    tmp = fieldFromInstruction(insn, 23, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 18, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 3) << 1;
    tmp |= fieldFromInstruction(insn, 16, 1);
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 10:
    tmp = fieldFromInstruction(insn, 23, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 18, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 11:
    tmp = fieldFromInstruction(insn, 2, 23) << 2;
    if (!Check(S, decodeBranch(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 12:
    tmp = fieldFromInstruction(insn, 2, 23) << 2;
    if (!Check(S, decodeBranch(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1);
    tmp |= fieldFromInstruction(insn, 25, 3) << 1;
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 13:
    tmp = fieldFromInstruction(insn, 18, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1);
    tmp |= fieldFromInstruction(insn, 25, 3) << 1;
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 14:
    tmp = fieldFromInstruction(insn, 2, 14) << 2;
    MI.addOperand(MCOperand::createImm(tmp));
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1);
    tmp |= fieldFromInstruction(insn, 25, 3) << 1;
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 15:
    tmp = fieldFromInstruction(insn, 23, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 18, 5) << 16;
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 16:
    tmp = fieldFromInstruction(insn, 23, 5);
    if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 12);
    tmp |= fieldFromInstruction(insn, 18, 5) << 12;
    if (!Check(S, decodeSplsValue(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  }
}

template <typename InsnType>
static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
                                      InsnType insn, uint64_t Address,
                                      const MCDisassembler *DisAsm,
                                      const MCSubtargetInfo &STI) {
  const uint8_t *Ptr = DecodeTable;

  SmallVector<const uint8_t *, 8> ScopeStack;
  DecodeStatus S = MCDisassembler::Success;
  while (true) {
    ptrdiff_t Loc = Ptr - DecodeTable;
    const uint8_t DecoderOp = *Ptr++;
    switch (DecoderOp) {
    default:
      errs() << Loc << ": Unexpected decode table opcode: "
             << (int)DecoderOp << '\n';
      return MCDisassembler::Fail;
    case OPC_Scope: {
      unsigned NumToSkip = decodeULEB128AndIncUnsafe(Ptr);
      const uint8_t *SkipTo = Ptr + NumToSkip;
      ScopeStack.push_back(SkipTo);
      LLVM_DEBUG(dbgs() << Loc << ": OPC_Scope(" << SkipTo - DecodeTable
                        << ")\n");
      continue;
    }
    case OPC_SwitchField: {
      // Decode the start value.
      unsigned Start = decodeULEB128AndIncUnsafe(Ptr);
      unsigned Len = *Ptr++;
      uint64_t FieldValue = fieldFromInstruction(insn, Start, Len);
      uint64_t CaseValue;
      unsigned CaseSize;
      while (true) {
        CaseValue = decodeULEB128AndIncUnsafe(Ptr);
        CaseSize = decodeULEB128AndIncUnsafe(Ptr);
        if (FieldValue == CaseValue || !CaseSize)
          break;
        Ptr += CaseSize;
      }
      if (FieldValue == CaseValue) {
        LLVM_DEBUG(dbgs() << Loc << ": OPC_SwitchField(" << Start << ", " << Len
                          << "): " << FieldValue << '\n');
        continue;
      }
      break;
    }
    case OPC_CheckField: {
      // Decode the start value.
      unsigned Start = decodeULEB128AndIncUnsafe(Ptr);
      unsigned Len = *Ptr;
      uint64_t FieldValue = fieldFromInstruction(insn, Start, Len);
      // Decode the field value.
      unsigned PtrLen = 0;
      uint64_t ExpectedValue = decodeULEB128(++Ptr, &PtrLen);
      Ptr += PtrLen;
      bool Failed = ExpectedValue != FieldValue;

      LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckField(" << Start << ", " << Len
                        << ", " << ExpectedValue << "): FieldValue = "
                        << FieldValue << ", ExpectedValue = " << ExpectedValue
                        << ": " << (Failed ? "FAIL, " : "PASS\n"););
      if (!Failed)
        continue;
      break;
    }
    case OPC_Decode: {
      // Decode the Opcode value.
      unsigned Opc = decodeULEB128AndIncUnsafe(Ptr);
      unsigned DecodeIdx = decodeULEB128AndIncUnsafe(Ptr);

      MI.clear();
      MI.setOpcode(Opc);
      bool DecodeComplete;
      S = decodeToMCInst(DecodeIdx, S, insn, MI, Address, DisAsm,
                         DecodeComplete);
      LLVM_DEBUG(dbgs() << Loc << ": OPC_Decode: opcode " << Opc
                        << ", using decoder " << DecodeIdx << ": "
                        << (S ? "PASS, " : "FAIL, "));

      if (DecodeComplete) {
        LLVM_DEBUG(dbgs() << "decoding complete\n");
        return S;
      }
      assert(S == MCDisassembler::Fail);
      // Reset decode status. This also drops a SoftFail status that could be
      // set before the decode attempt.
      S = MCDisassembler::Success;
      break;
    }
    }
    if (ScopeStack.empty()) {
      LLVM_DEBUG(dbgs() << "returning Fail\n");
      return MCDisassembler::Fail;
    }
    Ptr = ScopeStack.pop_back_val();
    LLVM_DEBUG(dbgs() << "continuing at " << Ptr - DecodeTable << '\n');
  }
  llvm_unreachable("bogosity detected in disassembler state machine!");
}


} // namespace
