/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Instruction Enum Values and Descriptors                             *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM

namespace llvm::AVR {

  enum {
    PHI                                   = 0, // Target.td:1200
    INLINEASM                             = 1, // Target.td:1206
    INLINEASM_BR                          = 2, // Target.td:1212
    CFI_INSTRUCTION                       = 3, // Target.td:1221
    EH_LABEL                              = 4, // Target.td:1230
    GC_LABEL                              = 5, // Target.td:1239
    ANNOTATION_LABEL                      = 6, // Target.td:1248
    KILL                                  = 7, // Target.td:1256
    EXTRACT_SUBREG                        = 8, // Target.td:1263
    INSERT_SUBREG                         = 9, // Target.td:1269
    IMPLICIT_DEF                          = 10, // Target.td:1276
    INIT_UNDEF                            = 11, // Target.td:1285
    SUBREG_TO_REG                         = 12, // Target.td:1292
    COPY_TO_REGCLASS                      = 13, // Target.td:1298
    DBG_VALUE                             = 14, // Target.td:1305
    DBG_VALUE_LIST                        = 15, // Target.td:1312
    DBG_INSTR_REF                         = 16, // Target.td:1319
    DBG_PHI                               = 17, // Target.td:1326
    DBG_LABEL                             = 18, // Target.td:1333
    REG_SEQUENCE                          = 19, // Target.td:1340
    COPY                                  = 20, // Target.td:1347
    COPY_LANEMASK                         = 21, // Target.td:1355
    BUNDLE                                = 22, // Target.td:1362
    LIFETIME_START                        = 23, // Target.td:1368
    LIFETIME_END                          = 24, // Target.td:1375
    PSEUDO_PROBE                          = 25, // Target.td:1382
    ARITH_FENCE                           = 26, // Target.td:1389
    STACKMAP                              = 27, // Target.td:1398
    FENTRY_CALL                           = 28, // Target.td:1533
    PATCHPOINT                            = 29, // Target.td:1406
    LOAD_STACK_GUARD                      = 30, // Target.td:1424
    PREALLOCATED_SETUP                    = 31, // Target.td:1432
    PREALLOCATED_ARG                      = 32, // Target.td:1438
    STATEPOINT                            = 33, // Target.td:1415
    LOCAL_ESCAPE                          = 34, // Target.td:1444
    FAULTING_OP                           = 35, // Target.td:1453
    PATCHABLE_OP                          = 36, // Target.td:1473
    PATCHABLE_FUNCTION_ENTER              = 37, // Target.td:1481
    PATCHABLE_RET                         = 38, // Target.td:1488
    PATCHABLE_FUNCTION_EXIT               = 39, // Target.td:1497
    PATCHABLE_TAIL_CALL                   = 40, // Target.td:1505
    PATCHABLE_EVENT_CALL                  = 41, // Target.td:1513
    PATCHABLE_TYPED_EVENT_CALL            = 42, // Target.td:1523
    ICALL_BRANCH_FUNNEL                   = 43, // Target.td:1543
    FAKE_USE                              = 44, // Target.td:1463
    MEMBARRIER                            = 45, // Target.td:1549
    JUMP_TABLE_DEBUG_INFO                 = 46, // Target.td:1557
    RELOC_NONE                            = 47, // Target.td:1565
    CONVERGENCECTRL_ENTRY                 = 48, // Target.td:1576
    CONVERGENCECTRL_ANCHOR                = 49, // Target.td:1572
    CONVERGENCECTRL_LOOP                  = 50, // Target.td:1580
    CONVERGENCECTRL_GLUE                  = 51, // Target.td:1584
    G_ASSERT_SEXT                         = 52, // GenericOpcodes.td:1859
    G_ASSERT_ZEXT                         = 53, // GenericOpcodes.td:1851
    G_ASSERT_ALIGN                        = 54, // GenericOpcodes.td:1866
    G_ADD                                 = 55, // GenericOpcodes.td:294
    G_SUB                                 = 56, // GenericOpcodes.td:302
    G_MUL                                 = 57, // GenericOpcodes.td:310
    G_SDIV                                = 58, // GenericOpcodes.td:318
    G_UDIV                                = 59, // GenericOpcodes.td:326
    G_SREM                                = 60, // GenericOpcodes.td:334
    G_UREM                                = 61, // GenericOpcodes.td:342
    G_SDIVREM                             = 62, // GenericOpcodes.td:350
    G_UDIVREM                             = 63, // GenericOpcodes.td:358
    G_AND                                 = 64, // GenericOpcodes.td:366
    G_OR                                  = 65, // GenericOpcodes.td:374
    G_XOR                                 = 66, // GenericOpcodes.td:382
    G_ABDS                                = 67, // GenericOpcodes.td:411
    G_ABDU                                = 68, // GenericOpcodes.td:419
    G_UAVGFLOOR                           = 69, // GenericOpcodes.td:427
    G_UAVGCEIL                            = 70, // GenericOpcodes.td:434
    G_SAVGFLOOR                           = 71, // GenericOpcodes.td:441
    G_SAVGCEIL                            = 72, // GenericOpcodes.td:448
    G_IMPLICIT_DEF                        = 73, // GenericOpcodes.td:110
    G_PHI                                 = 74, // GenericOpcodes.td:116
    G_FRAME_INDEX                         = 75, // GenericOpcodes.td:122
    G_GLOBAL_VALUE                        = 76, // GenericOpcodes.td:128
    G_PTRAUTH_GLOBAL_VALUE                = 77, // GenericOpcodes.td:134
    G_CONSTANT_POOL                       = 78, // GenericOpcodes.td:140
    G_EXTRACT                             = 79, // GenericOpcodes.td:1466
    G_UNMERGE_VALUES                      = 80, // GenericOpcodes.td:1478
    G_INSERT                              = 81, // GenericOpcodes.td:1486
    G_MERGE_VALUES                        = 82, // GenericOpcodes.td:1496
    G_BUILD_VECTOR                        = 83, // GenericOpcodes.td:1515
    G_BUILD_VECTOR_TRUNC                  = 84, // GenericOpcodes.td:1524
    G_CONCAT_VECTORS                      = 85, // GenericOpcodes.td:1531
    G_PTRTOINT                            = 86, // GenericOpcodes.td:152
    G_INTTOPTR                            = 87, // GenericOpcodes.td:146
    G_BITCAST                             = 88, // GenericOpcodes.td:158
    G_FREEZE                              = 89, // GenericOpcodes.td:271
    G_CONSTANT_FOLD_BARRIER               = 90, // GenericOpcodes.td:1873
    G_INTRINSIC_FPTRUNC_ROUND             = 91, // GenericOpcodes.td:1257
    G_INTRINSIC_TRUNC                     = 92, // GenericOpcodes.td:1263
    G_INTRINSIC_ROUND                     = 93, // GenericOpcodes.td:1269
    G_INTRINSIC_LRINT                     = 94, // GenericOpcodes.td:1275
    G_INTRINSIC_LLRINT                    = 95, // GenericOpcodes.td:1281
    G_INTRINSIC_ROUNDEVEN                 = 96, // GenericOpcodes.td:1287
    G_READCYCLECOUNTER                    = 97, // GenericOpcodes.td:1293
    G_READSTEADYCOUNTER                   = 98, // GenericOpcodes.td:1299
    G_LOAD                                = 99, // GenericOpcodes.td:1326
    G_SEXTLOAD                            = 100, // GenericOpcodes.td:1334
    G_ZEXTLOAD                            = 101, // GenericOpcodes.td:1342
    G_INDEXED_LOAD                        = 102, // GenericOpcodes.td:1352
    G_INDEXED_SEXTLOAD                    = 103, // GenericOpcodes.td:1360
    G_INDEXED_ZEXTLOAD                    = 104, // GenericOpcodes.td:1368
    G_STORE                               = 105, // GenericOpcodes.td:1376
    G_INDEXED_STORE                       = 106, // GenericOpcodes.td:1384
    G_ATOMIC_CMPXCHG_WITH_SUCCESS         = 107, // GenericOpcodes.td:1394
    G_ATOMIC_CMPXCHG                      = 108, // GenericOpcodes.td:1404
    G_ATOMICRMW_XCHG                      = 109, // GenericOpcodes.td:1422
    G_ATOMICRMW_ADD                       = 110, // GenericOpcodes.td:1423
    G_ATOMICRMW_SUB                       = 111, // GenericOpcodes.td:1424
    G_ATOMICRMW_AND                       = 112, // GenericOpcodes.td:1425
    G_ATOMICRMW_NAND                      = 113, // GenericOpcodes.td:1426
    G_ATOMICRMW_OR                        = 114, // GenericOpcodes.td:1427
    G_ATOMICRMW_XOR                       = 115, // GenericOpcodes.td:1428
    G_ATOMICRMW_MAX                       = 116, // GenericOpcodes.td:1429
    G_ATOMICRMW_MIN                       = 117, // GenericOpcodes.td:1430
    G_ATOMICRMW_UMAX                      = 118, // GenericOpcodes.td:1431
    G_ATOMICRMW_UMIN                      = 119, // GenericOpcodes.td:1432
    G_ATOMICRMW_FADD                      = 120, // GenericOpcodes.td:1433
    G_ATOMICRMW_FSUB                      = 121, // GenericOpcodes.td:1434
    G_ATOMICRMW_FMAX                      = 122, // GenericOpcodes.td:1435
    G_ATOMICRMW_FMIN                      = 123, // GenericOpcodes.td:1436
    G_ATOMICRMW_FMAXIMUM                  = 124, // GenericOpcodes.td:1437
    G_ATOMICRMW_FMINIMUM                  = 125, // GenericOpcodes.td:1438
    G_ATOMICRMW_UINC_WRAP                 = 126, // GenericOpcodes.td:1439
    G_ATOMICRMW_UDEC_WRAP                 = 127, // GenericOpcodes.td:1440
    G_ATOMICRMW_USUB_COND                 = 128, // GenericOpcodes.td:1441
    G_ATOMICRMW_USUB_SAT                  = 129, // GenericOpcodes.td:1442
    G_FENCE                               = 130, // GenericOpcodes.td:1444
    G_PREFETCH                            = 131, // GenericOpcodes.td:1451
    G_BRCOND                              = 132, // GenericOpcodes.td:1586
    G_BRINDIRECT                          = 133, // GenericOpcodes.td:1595
    G_INVOKE_REGION_START                 = 134, // GenericOpcodes.td:1618
    G_INTRINSIC                           = 135, // GenericOpcodes.td:1538
    G_INTRINSIC_W_SIDE_EFFECTS            = 136, // GenericOpcodes.td:1545
    G_INTRINSIC_CONVERGENT                = 137, // GenericOpcodes.td:1554
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1562
    G_ANYEXT                              = 139, // GenericOpcodes.td:44
    G_TRUNC                               = 140, // GenericOpcodes.td:83
    G_TRUNC_SSAT_S                        = 141, // GenericOpcodes.td:90
    G_TRUNC_SSAT_U                        = 142, // GenericOpcodes.td:97
    G_TRUNC_USAT_U                        = 143, // GenericOpcodes.td:104
    G_CONSTANT                            = 144, // GenericOpcodes.td:165
    G_FCONSTANT                           = 145, // GenericOpcodes.td:172
    G_VASTART                             = 146, // GenericOpcodes.td:178
    G_VAARG                               = 147, // GenericOpcodes.td:185
    G_SEXT                                = 148, // GenericOpcodes.td:52
    G_SEXT_INREG                          = 149, // GenericOpcodes.td:66
    G_ZEXT                                = 150, // GenericOpcodes.td:74
    G_SHL                                 = 151, // GenericOpcodes.td:390
    G_LSHR                                = 152, // GenericOpcodes.td:397
    G_ASHR                                = 153, // GenericOpcodes.td:404
    G_FSHL                                = 154, // GenericOpcodes.td:456
    G_FSHR                                = 155, // GenericOpcodes.td:464
    G_ROTR                                = 156, // GenericOpcodes.td:471
    G_ROTL                                = 157, // GenericOpcodes.td:478
    G_ICMP                                = 158, // GenericOpcodes.td:485
    G_FCMP                                = 159, // GenericOpcodes.td:492
    G_SCMP                                = 160, // GenericOpcodes.td:499
    G_UCMP                                = 161, // GenericOpcodes.td:506
    G_SELECT                              = 162, // GenericOpcodes.td:513
    G_UADDO                               = 163, // GenericOpcodes.td:578
    G_UADDE                               = 164, // GenericOpcodes.td:586
    G_USUBO                               = 165, // GenericOpcodes.td:608
    G_USUBE                               = 166, // GenericOpcodes.td:614
    G_SADDO                               = 167, // GenericOpcodes.td:593
    G_SADDE                               = 168, // GenericOpcodes.td:601
    G_SSUBO                               = 169, // GenericOpcodes.td:621
    G_SSUBE                               = 170, // GenericOpcodes.td:628
    G_UMULO                               = 171, // GenericOpcodes.td:635
    G_SMULO                               = 172, // GenericOpcodes.td:643
    G_UMULH                               = 173, // GenericOpcodes.td:652
    G_SMULH                               = 174, // GenericOpcodes.td:661
    G_UADDSAT                             = 175, // GenericOpcodes.td:673
    G_SADDSAT                             = 176, // GenericOpcodes.td:681
    G_USUBSAT                             = 177, // GenericOpcodes.td:689
    G_SSUBSAT                             = 178, // GenericOpcodes.td:697
    G_USHLSAT                             = 179, // GenericOpcodes.td:705
    G_SSHLSAT                             = 180, // GenericOpcodes.td:713
    G_SMULFIX                             = 181, // GenericOpcodes.td:725
    G_UMULFIX                             = 182, // GenericOpcodes.td:732
    G_SMULFIXSAT                          = 183, // GenericOpcodes.td:742
    G_UMULFIXSAT                          = 184, // GenericOpcodes.td:749
    G_SDIVFIX                             = 185, // GenericOpcodes.td:760
    G_UDIVFIX                             = 186, // GenericOpcodes.td:767
    G_SDIVFIXSAT                          = 187, // GenericOpcodes.td:777
    G_UDIVFIXSAT                          = 188, // GenericOpcodes.td:784
    G_FADD                                = 189, // GenericOpcodes.td:957
    G_FSUB                                = 190, // GenericOpcodes.td:965
    G_FMUL                                = 191, // GenericOpcodes.td:973
    G_FMA                                 = 192, // GenericOpcodes.td:982
    G_FMAD                                = 193, // GenericOpcodes.td:991
    G_FDIV                                = 194, // GenericOpcodes.td:999
    G_FREM                                = 195, // GenericOpcodes.td:1006
    G_FMODF                               = 196, // GenericOpcodes.td:1013
    G_FPOW                                = 197, // GenericOpcodes.td:1020
    G_FPOWI                               = 198, // GenericOpcodes.td:1027
    G_FEXP                                = 199, // GenericOpcodes.td:1034
    G_FEXP2                               = 200, // GenericOpcodes.td:1041
    G_FEXP10                              = 201, // GenericOpcodes.td:1048
    G_FLOG                                = 202, // GenericOpcodes.td:1055
    G_FLOG2                               = 203, // GenericOpcodes.td:1062
    G_FLOG10                              = 204, // GenericOpcodes.td:1069
    G_FLDEXP                              = 205, // GenericOpcodes.td:1076
    G_FFREXP                              = 206, // GenericOpcodes.td:1083
    G_FNEG                                = 207, // GenericOpcodes.td:795
    G_FPEXT                               = 208, // GenericOpcodes.td:801
    G_FPTRUNC                             = 209, // GenericOpcodes.td:807
    G_FPTOSI                              = 210, // GenericOpcodes.td:813
    G_FPTOUI                              = 211, // GenericOpcodes.td:819
    G_SITOFP                              = 212, // GenericOpcodes.td:825
    G_UITOFP                              = 213, // GenericOpcodes.td:831
    G_FPTOSI_SAT                          = 214, // GenericOpcodes.td:837
    G_FPTOUI_SAT                          = 215, // GenericOpcodes.td:843
    G_FABS                                = 216, // GenericOpcodes.td:849
    G_FCOPYSIGN                           = 217, // GenericOpcodes.td:855
    G_IS_FPCLASS                          = 218, // GenericOpcodes.td:868
    G_FCANONICALIZE                       = 219, // GenericOpcodes.td:861
    G_FMINNUM                             = 220, // GenericOpcodes.td:881
    G_FMAXNUM                             = 221, // GenericOpcodes.td:888
    G_FMINNUM_IEEE                        = 222, // GenericOpcodes.td:906
    G_FMAXNUM_IEEE                        = 223, // GenericOpcodes.td:913
    G_FMINIMUM                            = 224, // GenericOpcodes.td:923
    G_FMAXIMUM                            = 225, // GenericOpcodes.td:930
    G_FMINIMUMNUM                         = 226, // GenericOpcodes.td:938
    G_FMAXIMUMNUM                         = 227, // GenericOpcodes.td:945
    G_GET_FPENV                           = 228, // GenericOpcodes.td:1213
    G_SET_FPENV                           = 229, // GenericOpcodes.td:1220
    G_RESET_FPENV                         = 230, // GenericOpcodes.td:1227
    G_GET_FPMODE                          = 231, // GenericOpcodes.td:1234
    G_SET_FPMODE                          = 232, // GenericOpcodes.td:1241
    G_RESET_FPMODE                        = 233, // GenericOpcodes.td:1248
    G_GET_ROUNDING                        = 234, // GenericOpcodes.td:1305
    G_SET_ROUNDING                        = 235, // GenericOpcodes.td:1311
    G_PTR_ADD                             = 236, // GenericOpcodes.td:520
    G_PTRMASK                             = 237, // GenericOpcodes.td:528
    G_SMIN                                = 238, // GenericOpcodes.td:535
    G_SMAX                                = 239, // GenericOpcodes.td:543
    G_UMIN                                = 240, // GenericOpcodes.td:551
    G_UMAX                                = 241, // GenericOpcodes.td:559
    G_ABS                                 = 242, // GenericOpcodes.td:567
    G_LROUND                              = 243, // GenericOpcodes.td:277
    G_LLROUND                             = 244, // GenericOpcodes.td:283
    G_BR                                  = 245, // GenericOpcodes.td:1576
    G_BRJT                                = 246, // GenericOpcodes.td:1606
    G_VSCALE                              = 247, // GenericOpcodes.td:1506
    G_INSERT_SUBVECTOR                    = 248, // GenericOpcodes.td:1650
    G_EXTRACT_SUBVECTOR                   = 249, // GenericOpcodes.td:1657
    G_INSERT_VECTOR_ELT                   = 250, // GenericOpcodes.td:1664
    G_EXTRACT_VECTOR_ELT                  = 251, // GenericOpcodes.td:1671
    G_SHUFFLE_VECTOR                      = 252, // GenericOpcodes.td:1681
    G_SPLAT_VECTOR                        = 253, // GenericOpcodes.td:1688
    G_STEP_VECTOR                         = 254, // GenericOpcodes.td:1695
    G_VECTOR_COMPRESS                     = 255, // GenericOpcodes.td:1702
    G_CTTZ                                = 256, // GenericOpcodes.td:205
    G_CTTZ_ZERO_UNDEF                     = 257, // GenericOpcodes.td:211
    G_CTLZ                                = 258, // GenericOpcodes.td:193
    G_CTLZ_ZERO_UNDEF                     = 259, // GenericOpcodes.td:199
    G_CTPOP                               = 260, // GenericOpcodes.td:217
    G_BSWAP                               = 261, // GenericOpcodes.td:223
    G_BITREVERSE                          = 262, // GenericOpcodes.td:229
    G_FCEIL                               = 263, // GenericOpcodes.td:1090
    G_FCOS                                = 264, // GenericOpcodes.td:1097
    G_FSIN                                = 265, // GenericOpcodes.td:1104
    G_FSINCOS                             = 266, // GenericOpcodes.td:1111
    G_FTAN                                = 267, // GenericOpcodes.td:1118
    G_FACOS                               = 268, // GenericOpcodes.td:1125
    G_FASIN                               = 269, // GenericOpcodes.td:1132
    G_FATAN                               = 270, // GenericOpcodes.td:1139
    G_FATAN2                              = 271, // GenericOpcodes.td:1146
    G_FCOSH                               = 272, // GenericOpcodes.td:1153
    G_FSINH                               = 273, // GenericOpcodes.td:1160
    G_FTANH                               = 274, // GenericOpcodes.td:1167
    G_FSQRT                               = 275, // GenericOpcodes.td:1177
    G_FFLOOR                              = 276, // GenericOpcodes.td:1184
    G_FRINT                               = 277, // GenericOpcodes.td:1191
    G_FNEARBYINT                          = 278, // GenericOpcodes.td:1198
    G_ADDRSPACE_CAST                      = 279, // GenericOpcodes.td:235
    G_BLOCK_ADDR                          = 280, // GenericOpcodes.td:241
    G_JUMP_TABLE                          = 281, // GenericOpcodes.td:247
    G_DYN_STACKALLOC                      = 282, // GenericOpcodes.td:253
    G_STACKSAVE                           = 283, // GenericOpcodes.td:259
    G_STACKRESTORE                        = 284, // GenericOpcodes.td:265
    G_STRICT_FADD                         = 285, // GenericOpcodes.td:1752
    G_STRICT_FSUB                         = 286, // GenericOpcodes.td:1753
    G_STRICT_FMUL                         = 287, // GenericOpcodes.td:1754
    G_STRICT_FDIV                         = 288, // GenericOpcodes.td:1755
    G_STRICT_FREM                         = 289, // GenericOpcodes.td:1756
    G_STRICT_FMA                          = 290, // GenericOpcodes.td:1757
    G_STRICT_FSQRT                        = 291, // GenericOpcodes.td:1758
    G_STRICT_FLDEXP                       = 292, // GenericOpcodes.td:1759
    G_READ_REGISTER                       = 293, // GenericOpcodes.td:1625
    G_WRITE_REGISTER                      = 294, // GenericOpcodes.td:1635
    G_MEMCPY                              = 295, // GenericOpcodes.td:1765
    G_MEMCPY_INLINE                       = 296, // GenericOpcodes.td:1773
    G_MEMMOVE                             = 297, // GenericOpcodes.td:1781
    G_MEMSET                              = 298, // GenericOpcodes.td:1789
    G_BZERO                               = 299, // GenericOpcodes.td:1796
    G_TRAP                                = 300, // GenericOpcodes.td:1806
    G_DEBUGTRAP                           = 301, // GenericOpcodes.td:1813
    G_UBSANTRAP                           = 302, // GenericOpcodes.td:1819
    G_VECREDUCE_SEQ_FADD                  = 303, // GenericOpcodes.td:1718
    G_VECREDUCE_SEQ_FMUL                  = 304, // GenericOpcodes.td:1724
    G_VECREDUCE_FADD                      = 305, // GenericOpcodes.td:1730
    G_VECREDUCE_FMUL                      = 306, // GenericOpcodes.td:1731
    G_VECREDUCE_FMAX                      = 307, // GenericOpcodes.td:1733
    G_VECREDUCE_FMIN                      = 308, // GenericOpcodes.td:1734
    G_VECREDUCE_FMAXIMUM                  = 309, // GenericOpcodes.td:1735
    G_VECREDUCE_FMINIMUM                  = 310, // GenericOpcodes.td:1736
    G_VECREDUCE_ADD                       = 311, // GenericOpcodes.td:1738
    G_VECREDUCE_MUL                       = 312, // GenericOpcodes.td:1739
    G_VECREDUCE_AND                       = 313, // GenericOpcodes.td:1740
    G_VECREDUCE_OR                        = 314, // GenericOpcodes.td:1741
    G_VECREDUCE_XOR                       = 315, // GenericOpcodes.td:1742
    G_VECREDUCE_SMAX                      = 316, // GenericOpcodes.td:1743
    G_VECREDUCE_SMIN                      = 317, // GenericOpcodes.td:1744
    G_VECREDUCE_UMAX                      = 318, // GenericOpcodes.td:1745
    G_VECREDUCE_UMIN                      = 319, // GenericOpcodes.td:1746
    G_SBFX                                = 320, // GenericOpcodes.td:1831
    G_UBFX                                = 321, // GenericOpcodes.td:1839
    ADCWRdRr                              = 322, // AVRInstrInfo.td:397
    ADDWRdRr                              = 323, // AVRInstrInfo.td:378
    ADJCALLSTACKDOWN                      = 324, // AVRInstrInfo.td:346
    ADJCALLSTACKUP                        = 325, // AVRInstrInfo.td:356
    ANDIWRdK                              = 326, // AVRInstrInfo.td:583
    ANDWRdRr                              = 327, // AVRInstrInfo.td:543
    ASRBNRd                               = 328, // AVRInstrInfo.td:1357
    ASRWLoRd                              = 329, // AVRInstrInfo.td:1364
    ASRWNRd                               = 330, // AVRInstrInfo.td:1353
    ASRWRd                                = 331, // AVRInstrInfo.td:1361
    Asr16                                 = 332, // AVRInstrInfo.td:1625
    Asr32                                 = 333, // AVRInstrInfo.td:1629
    Asr8                                  = 334, // AVRInstrInfo.td:1621
    AtomicFence                           = 335, // AVRInstrInfo.td:1044
    AtomicLoad16                          = 336, // AVRInstrInfo.td:1022
    AtomicLoad8                           = 337, // AVRInstrInfo.td:1021
    AtomicLoadAdd16                       = 338, // AVRInstrInfo.td:1032
    AtomicLoadAdd8                        = 339, // AVRInstrInfo.td:1031
    AtomicLoadAnd16                       = 340, // AVRInstrInfo.td:1036
    AtomicLoadAnd8                        = 341, // AVRInstrInfo.td:1035
    AtomicLoadOr16                        = 342, // AVRInstrInfo.td:1038
    AtomicLoadOr8                         = 343, // AVRInstrInfo.td:1037
    AtomicLoadSub16                       = 344, // AVRInstrInfo.td:1034
    AtomicLoadSub8                        = 345, // AVRInstrInfo.td:1033
    AtomicLoadXor16                       = 346, // AVRInstrInfo.td:1040
    AtomicLoadXor8                        = 347, // AVRInstrInfo.td:1039
    AtomicStore16                         = 348, // AVRInstrInfo.td:1025
    AtomicStore8                          = 349, // AVRInstrInfo.td:1024
    COMWRd                                = 350, // AVRInstrInfo.td:613
    CPCWRdRr                              = 351, // AVRInstrInfo.td:736
    CPWRdRr                               = 352, // AVRInstrInfo.td:721
    CopyZero                              = 353, // AVRInstrInfo.td:1637
    ELPMBRdZ                              = 354, // AVRInstrInfo.td:1221
    ELPMBRdZPi                            = 355, // AVRInstrInfo.td:1233
    ELPMWRdZ                              = 356, // AVRInstrInfo.td:1226
    ELPMWRdZPi                            = 357, // AVRInstrInfo.td:1237
    EORWRdRr                              = 358, // AVRInstrInfo.td:569
    FRMIDX                                = 359, // AVRInstrInfo.td:1530
    INWRdA                                = 360, // AVRInstrInfo.td:1261
    LDDWRdPtrQ                            = 361, // AVRInstrInfo.td:970
    LDDWRdYQ                              = 362, // AVRInstrInfo.td:991
    LDIWRdK                               = 363, // AVRInstrInfo.td:874
    LDSWRdK                               = 364, // AVRInstrInfo.td:894
    LDWRdPtr                              = 365, // AVRInstrInfo.td:917
    LDWRdPtrPd                            = 366, // AVRInstrInfo.td:947
    LDWRdPtrPi                            = 367, // AVRInstrInfo.td:934
    LPMBRdZ                               = 368, // AVRInstrInfo.td:1179
    LPMWRdZ                               = 369, // AVRInstrInfo.td:1183
    LPMWRdZPi                             = 370, // AVRInstrInfo.td:1198
    LSLBNRd                               = 371, // AVRInstrInfo.td:1329
    LSLWHiRd                              = 372, // AVRInstrInfo.td:1322
    LSLWNRd                               = 373, // AVRInstrInfo.td:1325
    LSLWRd                                = 374, // AVRInstrInfo.td:1319
    LSRBNRd                               = 375, // AVRInstrInfo.td:1346
    LSRWLoRd                              = 376, // AVRInstrInfo.td:1339
    LSRWNRd                               = 377, // AVRInstrInfo.td:1342
    LSRWRd                                = 378, // AVRInstrInfo.td:1336
    Lsl16                                 = 379, // AVRInstrInfo.td:1581
    Lsl32                                 = 380, // AVRInstrInfo.td:1585
    Lsl8                                  = 381, // AVRInstrInfo.td:1577
    Lsr16                                 = 382, // AVRInstrInfo.td:1595
    Lsr32                                 = 383, // AVRInstrInfo.td:1599
    Lsr8                                  = 384, // AVRInstrInfo.td:1591
    NEGWRd                                = 385, // AVRInstrInfo.td:625
    ORIWRdK                               = 386, // AVRInstrInfo.td:596
    ORWRdRr                               = 387, // AVRInstrInfo.td:556
    OUTWARr                               = 388, // AVRInstrInfo.td:1270
    POPWRd                                = 389, // AVRInstrInfo.td:1291
    PUSHWRr                               = 390, // AVRInstrInfo.td:1282
    ROLBRdR1                              = 391, // AVRInstrInfo.td:1368
    ROLBRdR17                             = 392, // AVRInstrInfo.td:1373
    ROLWRd                                = 393, // AVRInstrInfo.td:1382
    RORBRd                                = 394, // AVRInstrInfo.td:1377
    RORWRd                                = 395, // AVRInstrInfo.td:1388
    Rol16                                 = 396, // AVRInstrInfo.td:1609
    Rol8                                  = 397, // AVRInstrInfo.td:1605
    Ror16                                 = 398, // AVRInstrInfo.td:1617
    Ror8                                  = 399, // AVRInstrInfo.td:1613
    SBCIWRdK                              = 400, // AVRInstrInfo.td:469
    SBCWRdRr                              = 401, // AVRInstrInfo.td:458
    SEXT                                  = 402, // AVRInstrInfo.td:1522
    SPREAD                                = 403, // AVRInstrInfo.td:1558
    SPWRITE                               = 404, // AVRInstrInfo.td:1561
    STDSPQRr                              = 405, // AVRInstrInfo.td:1545
    STDWPtrQRr                            = 406, // AVRInstrInfo.td:1167
    STDWSPQRr                             = 407, // AVRInstrInfo.td:1552
    STSWKRr                               = 408, // AVRInstrInfo.td:1065
    STWPtrPdRr                            = 409, // AVRInstrInfo.td:1137
    STWPtrPiRr                            = 410, // AVRInstrInfo.td:1112
    STWPtrRr                              = 411, // AVRInstrInfo.td:1088
    SUBIWRdK                              = 412, // AVRInstrInfo.td:438
    SUBWRdRr                              = 413, // AVRInstrInfo.td:425
    Select16                              = 414, // AVRInstrInfo.td:1571
    Select8                               = 415, // AVRInstrInfo.td:1565
    ZEXT                                  = 416, // AVRInstrInfo.td:1525
    ADCRdRr                               = 417, // AVRInstrInfo.td:385
    ADDRdRr                               = 418, // AVRInstrInfo.td:368
    ADIWRdK                               = 419, // AVRInstrInfo.td:403
    ANDIRdK                               = 420, // AVRInstrInfo.td:574
    ANDRdRr                               = 421, // AVRInstrInfo.td:534
    ASRRd                                 = 422, // AVRInstrInfo.td:1350
    BCLRs                                 = 423, // AVRInstrInfo.td:1446
    BLD                                   = 424, // AVRInstrInfo.td:1419
    BRBCsk                                = 425, // AVRInstrInfo.td:775
    BRBSsk                                = 426, // AVRInstrInfo.td:770
    BREAK                                 = 427, // AVRInstrInfo.td:1490
    BREQk                                 = 428, // AVRInstrInfo.td:826
    BRGEk                                 = 429, // AVRInstrInfo.td:844
    BRLOk                                 = 430, // AVRInstrInfo.td:835
    BRLTk                                 = 431, // AVRInstrInfo.td:847
    BRMIk                                 = 432, // AVRInstrInfo.td:838
    BRNEk                                 = 433, // AVRInstrInfo.td:829
    BRPLk                                 = 434, // AVRInstrInfo.td:841
    BRSHk                                 = 435, // AVRInstrInfo.td:832
    BSETs                                 = 436, // AVRInstrInfo.td:1445
    BST                                   = 437, // AVRInstrInfo.td:1416
    CALLk                                 = 438, // AVRInstrInfo.td:688
    CBIAb                                 = 439, // AVRInstrInfo.td:1408
    COMRd                                 = 440, // AVRInstrInfo.td:605
    CPCRdRr                               = 441, // AVRInstrInfo.td:726
    CPIRdK                                = 442, // AVRInstrInfo.td:742
    CPRdRr                                = 443, // AVRInstrInfo.td:712
    CPSE                                  = 444, // AVRInstrInfo.td:709
    DECRd                                 = 445, // AVRInstrInfo.td:483
    DESK                                  = 446, // AVRInstrInfo.td:525
    EICALL                                = 447, // AVRInstrInfo.td:678
    EIJMP                                 = 448, // AVRInstrInfo.td:652
    ELPM                                  = 449, // AVRInstrInfo.td:1207
    ELPMRdZ                               = 450, // AVRInstrInfo.td:1210
    ELPMRdZPi                             = 451, // AVRInstrInfo.td:1215
    EORRdRr                               = 452, // AVRInstrInfo.td:560
    FMUL                                  = 453, // AVRInstrInfo.td:509
    FMULS                                 = 454, // AVRInstrInfo.td:513
    FMULSU                                = 455, // AVRInstrInfo.td:517
    ICALL                                 = 456, // AVRInstrInfo.td:672
    IJMP                                  = 457, // AVRInstrInfo.td:648
    INCRd                                 = 458, // AVRInstrInfo.td:479
    INRdA                                 = 459, // AVRInstrInfo.td:1258
    JMPk                                  = 460, // AVRInstrInfo.td:655
    LACZRd                                = 461, // AVRInstrInfo.td:1304
    LASZRd                                = 462, // AVRInstrInfo.td:1301
    LATZRd                                = 463, // AVRInstrInfo.td:1307
    LDDRdPtrQ                             = 464, // AVRInstrInfo.td:954
    LDIRdK                                = 465, // AVRInstrInfo.td:866
    LDRdPtr                               = 466, // AVRInstrInfo.td:902
    LDRdPtrPd                             = 467, // AVRInstrInfo.td:938
    LDRdPtrPi                             = 468, // AVRInstrInfo.td:926
    LDSRdK                                = 469, // AVRInstrInfo.td:880
    LDSRdKTiny                            = 470, // AVRInstrInfo.td:885
    LPM                                   = 471, // AVRInstrInfo.td:1174
    LPMRdZ                                = 472, // AVRInstrInfo.td:1187
    LPMRdZPi                              = 473, // AVRInstrInfo.td:1194
    LSRRd                                 = 474, // AVRInstrInfo.td:1333
    MOVRdRr                               = 475, // AVRInstrInfo.td:856
    MOVWRdRr                              = 476, // AVRInstrInfo.td:859
    MULRdRr                               = 477, // AVRInstrInfo.td:496
    MULSRdRr                              = 478, // AVRInstrInfo.td:500
    MULSURdRr                             = 479, // AVRInstrInfo.td:505
    NEGRd                                 = 480, // AVRInstrInfo.td:616
    NOP                                   = 481, // AVRInstrInfo.td:1499
    ORIRdK                                = 482, // AVRInstrInfo.td:587
    ORRdRr                                = 483, // AVRInstrInfo.td:547
    OUTARr                                = 484, // AVRInstrInfo.td:1267
    POPRd                                 = 485, // AVRInstrInfo.td:1288
    PUSHRr                                = 486, // AVRInstrInfo.td:1278
    RCALLk                                = 487, // AVRInstrInfo.td:666
    RET                                   = 488, // AVRInstrInfo.td:697
    RETI                                  = 489, // AVRInstrInfo.td:699
    RJMPk                                 = 490, // AVRInstrInfo.td:645
    RORRd                                 = 491, // AVRInstrInfo.td:1385
    SBCIRdK                               = 492, // AVRInstrInfo.td:462
    SBCRdRr                               = 493, // AVRInstrInfo.td:449
    SBIAb                                 = 494, // AVRInstrInfo.td:1403
    SBICAb                                = 495, // AVRInstrInfo.td:759
    SBISAb                                = 496, // AVRInstrInfo.td:762
    SBIWRdK                               = 497, // AVRInstrInfo.td:442
    SBRCRrB                               = 498, // AVRInstrInfo.td:753
    SBRSRrB                               = 499, // AVRInstrInfo.td:756
    SLEEP                                 = 500, // AVRInstrInfo.td:1506
    SPM                                   = 501, // AVRInstrInfo.td:1246
    SPMZPi                                = 502, // AVRInstrInfo.td:1250
    STDPtrQRr                             = 503, // AVRInstrInfo.td:1150
    STPtrPdRr                             = 504, // AVRInstrInfo.td:1123
    STPtrPiRr                             = 505, // AVRInstrInfo.td:1098
    STPtrRr                               = 506, // AVRInstrInfo.td:1073
    STSKRr                                = 507, // AVRInstrInfo.td:1049
    STSKRrTiny                            = 508, // AVRInstrInfo.td:1054
    SUBIRdK                               = 509, // AVRInstrInfo.td:429
    SUBRdRr                               = 510, // AVRInstrInfo.td:415
    SWAPRd                                = 511, // AVRInstrInfo.td:1396
    WDR                                   = 512, // AVRInstrInfo.td:1513
    XCHZRd                                = 513, // AVRInstrInfo.td:1298
    INSTRUCTION_LIST_END = 514
  };

} // namespace llvm::AVR

#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM

namespace llvm::AVR::Sched {

  enum {
    NoInstrModel	= 0,
    SCHED_LIST_END = 1
  };

} // namespace llvm::AVR::Sched

#endif // GET_INSTRINFO_SCHED_ENUM

#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

namespace llvm {

struct AVRInstrTable {
  MCInstrDesc Insts[514];
  static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
  MCPhysReg ImplicitOps[41];
  char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
  MCOperandInfo OperandInfo[316];
};
} // namespace llvm

#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC

namespace llvm {

static_assert((sizeof AVRInstrTable::ImplicitOps + sizeof AVRInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
static constexpr unsigned AVROpInfoBase = (sizeof AVRInstrTable::ImplicitOps + sizeof AVRInstrTable::Padding) / sizeof(MCOperandInfo);

extern const AVRInstrTable AVRDescs = {
  {
    { 513,	2,	1,	2,	0,	0,	0,	AVROpInfoBase + 226,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // XCHZRd
    { 512,	0,	0,	2,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // WDR
    { 511,	2,	1,	2,	0,	0,	0,	AVROpInfoBase + 241,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SWAPRd
    { 510,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 272,	2,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SUBRdRr
    { 509,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 278,	2,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SUBIRdK
    { 508,	2,	0,	2,	0,	0,	0,	AVROpInfoBase + 314,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STSKRrTiny
    { 507,	2,	0,	4,	0,	0,	0,	AVROpInfoBase + 304,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STSKRr
    { 506,	2,	0,	2,	0,	0,	0,	AVROpInfoBase + 192,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STPtrRr
    { 505,	4,	1,	2,	0,	0,	0,	AVROpInfoBase + 310,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STPtrPiRr
    { 504,	4,	1,	2,	0,	0,	0,	AVROpInfoBase + 310,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STPtrPdRr
    { 503,	3,	0,	2,	0,	0,	0,	AVROpInfoBase + 307,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STDPtrQRr
    { 502,	1,	0,	2,	0,	2,	1,	AVROpInfoBase + 306,	38,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SPMZPi
    { 501,	0,	0,	2,	0,	1,	0,	AVROpInfoBase + 1,	9,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SPM
    { 500,	0,	0,	2,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SLEEP
    { 499,	2,	0,	2,	0,	0,	0,	AVROpInfoBase + 286,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SBRSRrB
    { 498,	2,	0,	2,	0,	0,	0,	AVROpInfoBase + 286,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SBRCRrB
    { 497,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 275,	2,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SBIWRdK
    { 496,	2,	0,	2,	0,	0,	0,	AVROpInfoBase + 36,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SBISAb
    { 495,	2,	0,	2,	0,	0,	0,	AVROpInfoBase + 36,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SBICAb
    { 494,	2,	0,	2,	0,	0,	0,	AVROpInfoBase + 36,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SBIAb
    { 493,	3,	1,	2,	0,	1,	1,	AVROpInfoBase + 272,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SBCRdRr
    { 492,	3,	1,	2,	0,	1,	1,	AVROpInfoBase + 278,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SBCIRdK
    { 491,	2,	1,	2,	0,	1,	1,	AVROpInfoBase + 241,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // RORRd
    { 490,	1,	0,	2,	0,	0,	0,	AVROpInfoBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // RJMPk
    { 489,	0,	0,	2,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // RETI
    { 488,	0,	0,	2,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // RET
    { 487,	1,	0,	2,	0,	1,	0,	AVROpInfoBase + 0,	16,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // RCALLk
    { 486,	1,	0,	2,	0,	1,	1,	AVROpInfoBase + 196,	10,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // PUSHRr
    { 485,	1,	1,	2,	0,	1,	1,	AVROpInfoBase + 196,	10,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // POPRd
    { 484,	2,	0,	2,	0,	0,	0,	AVROpInfoBase + 304,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // OUTARr
    { 483,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 272,	2,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ORRdRr
    { 482,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 278,	2,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ORIRdK
    { 481,	0,	0,	2,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // NOP
    { 480,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 241,	2,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // NEGRd
    { 479,	2,	0,	2,	0,	0,	3,	AVROpInfoBase + 292,	35,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // MULSURdRr
    { 478,	2,	0,	2,	0,	0,	3,	AVROpInfoBase + 302,	35,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // MULSRdRr
    { 477,	2,	0,	2,	0,	0,	3,	AVROpInfoBase + 288,	35,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // MULRdRr
    { 476,	2,	1,	2,	0,	0,	0,	AVROpInfoBase + 194,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // MOVWRdRr
    { 475,	2,	1,	2,	0,	0,	0,	AVROpInfoBase + 288,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // MOVRdRr
    { 474,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 241,	2,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LSRRd
    { 473,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 226,	9,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LPMRdZPi
    { 472,	2,	1,	2,	0,	0,	0,	AVROpInfoBase + 226,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LPMRdZ
    { 471,	0,	0,	2,	0,	1,	1,	AVROpInfoBase + 1,	33,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LPM
    { 470,	2,	1,	2,	0,	0,	0,	AVROpInfoBase + 290,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDSRdKTiny
    { 469,	2,	1,	4,	0,	0,	0,	AVROpInfoBase + 294,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDSRdK
    { 468,	3,	2,	2,	0,	0,	0,	AVROpInfoBase + 299,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDRdPtrPi
    { 467,	3,	2,	2,	0,	0,	0,	AVROpInfoBase + 299,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDRdPtrPd
    { 466,	2,	1,	2,	0,	0,	0,	AVROpInfoBase + 182,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDRdPtr
    { 465,	2,	1,	2,	0,	0,	0,	AVROpInfoBase + 290,	0,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDIRdK
    { 464,	3,	1,	2,	0,	0,	0,	AVROpInfoBase + 296,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDDRdPtrQ
    { 463,	2,	1,	2,	0,	0,	0,	AVROpInfoBase + 226,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LATZRd
    { 462,	2,	1,	2,	0,	0,	0,	AVROpInfoBase + 226,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LASZRd
    { 461,	2,	1,	2,	0,	0,	0,	AVROpInfoBase + 226,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LACZRd
    { 460,	1,	0,	4,	0,	0,	0,	AVROpInfoBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // JMPk
    { 459,	2,	1,	2,	0,	0,	0,	AVROpInfoBase + 294,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // INRdA
    { 458,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 241,	2,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // INCRd
    { 457,	0,	0,	2,	0,	1,	0,	AVROpInfoBase + 1,	9,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // IJMP
    { 456,	0,	0,	2,	0,	2,	0,	AVROpInfoBase + 1,	6,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ICALL
    { 455,	2,	0,	2,	0,	0,	3,	AVROpInfoBase + 292,	35,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // FMULSU
    { 454,	2,	0,	2,	0,	0,	3,	AVROpInfoBase + 292,	35,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // FMULS
    { 453,	2,	0,	2,	0,	0,	3,	AVROpInfoBase + 292,	35,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // FMUL
    { 452,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 272,	2,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // EORRdRr
    { 451,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 226,	9,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ELPMRdZPi
    { 450,	2,	1,	2,	0,	0,	0,	AVROpInfoBase + 226,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ELPMRdZ
    { 449,	0,	0,	2,	0,	1,	1,	AVROpInfoBase + 1,	33,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ELPM
    { 448,	0,	0,	2,	0,	1,	0,	AVROpInfoBase + 1,	9,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // EIJMP
    { 447,	0,	0,	2,	0,	2,	0,	AVROpInfoBase + 1,	6,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // EICALL
    { 446,	1,	0,	2,	0,	0,	16,	AVROpInfoBase + 1,	17,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // DESK
    { 445,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 241,	2,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // DECRd
    { 444,	2,	0,	2,	0,	0,	1,	AVROpInfoBase + 288,	2,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // CPSE
    { 443,	2,	0,	2,	0,	0,	1,	AVROpInfoBase + 288,	2,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // CPRdRr
    { 442,	2,	0,	2,	0,	0,	1,	AVROpInfoBase + 290,	2,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // CPIRdK
    { 441,	2,	0,	2,	0,	1,	1,	AVROpInfoBase + 288,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // CPCRdRr
    { 440,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 241,	2,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // COMRd
    { 439,	2,	0,	2,	0,	0,	0,	AVROpInfoBase + 36,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // CBIAb
    { 438,	1,	0,	4,	0,	1,	0,	AVROpInfoBase + 0,	16,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // CALLk
    { 437,	2,	0,	2,	0,	0,	1,	AVROpInfoBase + 286,	2,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BST
    { 436,	1,	0,	2,	0,	0,	1,	AVROpInfoBase + 1,	2,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BSETs
    { 435,	1,	0,	2,	0,	1,	0,	AVROpInfoBase + 0,	2,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BRSHk
    { 434,	1,	0,	2,	0,	1,	0,	AVROpInfoBase + 0,	2,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BRPLk
    { 433,	1,	0,	2,	0,	1,	0,	AVROpInfoBase + 0,	2,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BRNEk
    { 432,	1,	0,	2,	0,	1,	0,	AVROpInfoBase + 0,	2,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BRMIk
    { 431,	1,	0,	2,	0,	1,	0,	AVROpInfoBase + 0,	2,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BRLTk
    { 430,	1,	0,	2,	0,	1,	0,	AVROpInfoBase + 0,	2,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BRLOk
    { 429,	1,	0,	2,	0,	1,	0,	AVROpInfoBase + 0,	2,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BRGEk
    { 428,	1,	0,	2,	0,	1,	0,	AVROpInfoBase + 0,	2,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BREQk
    { 427,	0,	0,	2,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BREAK
    { 426,	2,	0,	2,	0,	1,	0,	AVROpInfoBase + 284,	2,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BRBSsk
    { 425,	2,	0,	2,	0,	1,	0,	AVROpInfoBase + 284,	2,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BRBCsk
    { 424,	3,	1,	2,	0,	1,	0,	AVROpInfoBase + 281,	2,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BLD
    { 423,	1,	0,	2,	0,	0,	1,	AVROpInfoBase + 1,	2,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BCLRs
    { 422,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 241,	2,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ASRRd
    { 421,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 272,	2,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ANDRdRr
    { 420,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 278,	2,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ANDIRdK
    { 419,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 275,	2,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADIWRdK
    { 418,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 272,	2,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADDRdRr
    { 417,	3,	1,	2,	0,	1,	1,	AVROpInfoBase + 272,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADCRdRr
    { 416,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 243,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ZEXT
    { 415,	4,	1,	2,	0,	1,	0,	AVROpInfoBase + 268,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Select8
    { 414,	4,	1,	2,	0,	1,	0,	AVROpInfoBase + 264,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Select16
    { 413,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 155,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SUBWRdRr
    { 412,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 158,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SUBIWRdK
    { 411,	2,	0,	2,	0,	0,	0,	AVROpInfoBase + 190,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STWPtrRr
    { 410,	4,	1,	2,	0,	0,	0,	AVROpInfoBase + 260,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STWPtrPiRr
    { 409,	4,	1,	2,	0,	0,	0,	AVROpInfoBase + 260,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STWPtrPdRr
    { 408,	2,	0,	2,	0,	0,	0,	AVROpInfoBase + 258,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STSWKRr
    { 407,	3,	0,	2,	0,	1,	1,	AVROpInfoBase + 255,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STDWSPQRr
    { 406,	3,	0,	2,	0,	0,	0,	AVROpInfoBase + 252,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STDWPtrQRr
    { 405,	3,	0,	2,	0,	1,	1,	AVROpInfoBase + 249,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STDSPQRr
    { 404,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 247,	16,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SPWRITE
    { 403,	2,	1,	2,	0,	1,	0,	AVROpInfoBase + 245,	16,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SPREAD
    { 402,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 243,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SEXT
    { 401,	3,	1,	2,	0,	1,	1,	AVROpInfoBase + 155,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SBCWRdRr
    { 400,	3,	1,	2,	0,	1,	1,	AVROpInfoBase + 158,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SBCIWRdK
    { 399,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 177,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Ror8
    { 398,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 169,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Ror16
    { 397,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 177,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Rol8
    { 396,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 169,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Rol16
    { 395,	2,	1,	2,	0,	1,	1,	AVROpInfoBase + 164,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // RORWRd
    { 394,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 241,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // RORBRd
    { 393,	2,	1,	2,	0,	1,	1,	AVROpInfoBase + 164,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ROLWRd
    { 392,	2,	1,	2,	0,	1,	1,	AVROpInfoBase + 241,	14,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ROLBRdR17
    { 391,	2,	1,	2,	0,	1,	1,	AVROpInfoBase + 241,	12,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ROLBRdR1
    { 390,	1,	0,	2,	0,	1,	1,	AVROpInfoBase + 240,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // PUSHWRr
    { 389,	1,	1,	2,	0,	1,	1,	AVROpInfoBase + 240,	10,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // POPWRd
    { 388,	2,	0,	2,	0,	0,	0,	AVROpInfoBase + 238,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // OUTWARr
    { 387,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 155,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ORWRdRr
    { 386,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 158,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ORIWRdK
    { 385,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 235,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // NEGWRd
    { 384,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 177,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Lsr8
    { 383,	5,	2,	2,	0,	0,	1,	AVROpInfoBase + 172,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Lsr32
    { 382,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 169,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Lsr16
    { 381,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 177,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Lsl8
    { 380,	5,	2,	2,	0,	0,	1,	AVROpInfoBase + 172,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Lsl32
    { 379,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 169,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Lsl16
    { 378,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 164,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LSRWRd
    { 377,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 232,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LSRWNRd
    { 376,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 164,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LSRWLoRd
    { 375,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 161,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LSRBNRd
    { 374,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 164,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LSLWRd
    { 373,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 232,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LSLWNRd
    { 372,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 164,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LSLWHiRd
    { 371,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 161,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LSLBNRd
    { 370,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 230,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LPMWRdZPi
    { 369,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 228,	8,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LPMWRdZ
    { 368,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 226,	8,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LPMBRdZ
    { 367,	3,	2,	2,	0,	0,	0,	AVROpInfoBase + 223,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDWRdPtrPi
    { 366,	3,	2,	2,	0,	0,	0,	AVROpInfoBase + 223,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDWRdPtrPd
    { 365,	2,	1,	2,	0,	0,	0,	AVROpInfoBase + 221,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDWRdPtr
    { 364,	2,	1,	2,	0,	0,	0,	AVROpInfoBase + 219,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDSWRdK
    { 363,	2,	1,	2,	0,	0,	0,	AVROpInfoBase + 217,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDIWRdK
    { 362,	3,	1,	2,	0,	0,	0,	AVROpInfoBase + 214,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDDWRdYQ
    { 361,	3,	1,	2,	0,	0,	0,	AVROpInfoBase + 211,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDDWRdPtrQ
    { 360,	2,	1,	2,	0,	0,	0,	AVROpInfoBase + 209,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // INWRdA
    { 359,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 206,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // FRMIDX
    { 358,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 155,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // EORWRdRr
    { 357,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 203,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ELPMWRdZPi
    { 356,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 200,	8,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ELPMWRdZ
    { 355,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 197,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ELPMBRdZPi
    { 354,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 197,	8,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ELPMBRdZ
    { 353,	1,	1,	2,	0,	0,	0,	AVROpInfoBase + 196,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // CopyZero
    { 352,	2,	0,	2,	0,	0,	1,	AVROpInfoBase + 194,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // CPWRdRr
    { 351,	2,	0,	2,	0,	1,	1,	AVROpInfoBase + 194,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // CPCWRdRr
    { 350,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 164,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // COMWRd
    { 349,	2,	0,	2,	0,	0,	0,	AVROpInfoBase + 192,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AtomicStore8
    { 348,	2,	0,	2,	0,	0,	0,	AVROpInfoBase + 190,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AtomicStore16
    { 347,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 187,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AtomicLoadXor8
    { 346,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 184,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AtomicLoadXor16
    { 345,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 187,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AtomicLoadSub8
    { 344,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 184,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AtomicLoadSub16
    { 343,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 187,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AtomicLoadOr8
    { 342,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 184,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AtomicLoadOr16
    { 341,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 187,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AtomicLoadAnd8
    { 340,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 184,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AtomicLoadAnd16
    { 339,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 187,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AtomicLoadAdd8
    { 338,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 184,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AtomicLoadAdd16
    { 337,	2,	1,	2,	0,	0,	0,	AVROpInfoBase + 182,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AtomicLoad8
    { 336,	2,	1,	2,	0,	0,	0,	AVROpInfoBase + 180,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AtomicLoad16
    { 335,	0,	0,	2,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AtomicFence
    { 334,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 177,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Asr8
    { 333,	5,	2,	2,	0,	0,	1,	AVROpInfoBase + 172,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Asr32
    { 332,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 169,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Asr16
    { 331,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 164,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ASRWRd
    { 330,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 166,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ASRWNRd
    { 329,	2,	1,	2,	0,	0,	1,	AVROpInfoBase + 164,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ASRWLoRd
    { 328,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 161,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ASRBNRd
    { 327,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 155,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ANDWRdRr
    { 326,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 158,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ANDIWRdK
    { 325,	2,	0,	2,	0,	1,	1,	AVROpInfoBase + 24,	6,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADJCALLSTACKUP
    { 324,	2,	0,	2,	0,	1,	2,	AVROpInfoBase + 24,	3,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADJCALLSTACKDOWN
    { 323,	3,	1,	2,	0,	0,	1,	AVROpInfoBase + 155,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADDWRdRr
    { 322,	3,	1,	2,	0,	1,	1,	AVROpInfoBase + 155,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADCWRdRr
    { 321,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 151,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UBFX
    { 320,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 151,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SBFX
    { 319,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_UMIN
    { 318,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_UMAX
    { 317,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_SMIN
    { 316,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_SMAX
    { 315,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_XOR
    { 314,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_OR
    { 313,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_AND
    { 312,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_MUL
    { 311,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_ADD
    { 310,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_FMINIMUM
    { 309,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_FMAXIMUM
    { 308,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_FMIN
    { 307,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_FMAX
    { 306,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_FMUL
    { 305,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_FADD
    { 304,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 134,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_SEQ_FMUL
    { 303,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 134,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_SEQ_FADD
    { 302,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UBSANTRAP
    { 301,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_DEBUGTRAP
    { 300,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_TRAP
    { 299,	3,	0,	0,	0,	0,	0,	AVROpInfoBase + 61,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BZERO
    { 298,	4,	0,	0,	0,	0,	0,	AVROpInfoBase + 147,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_MEMSET
    { 297,	4,	0,	0,	0,	0,	0,	AVROpInfoBase + 147,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_MEMMOVE
    { 296,	3,	0,	0,	0,	0,	0,	AVROpInfoBase + 134,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_MEMCPY_INLINE
    { 295,	4,	0,	0,	0,	0,	0,	AVROpInfoBase + 147,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_MEMCPY
    { 294,	2,	0,	0,	0,	0,	0,	AVROpInfoBase + 145,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // G_WRITE_REGISTER
    { 293,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // G_READ_REGISTER
    { 292,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STRICT_FLDEXP
    { 291,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STRICT_FSQRT
    { 290,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 49,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STRICT_FMA
    { 289,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STRICT_FREM
    { 288,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STRICT_FDIV
    { 287,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STRICT_FMUL
    { 286,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STRICT_FSUB
    { 285,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STRICT_FADD
    { 284,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STACKRESTORE
    { 283,	1,	1,	0,	0,	0,	0,	AVROpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STACKSAVE
    { 282,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 72,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_DYN_STACKALLOC
    { 281,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_JUMP_TABLE
    { 280,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BLOCK_ADDR
    { 279,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ADDRSPACE_CAST
    { 278,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FNEARBYINT
    { 277,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FRINT
    { 276,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FFLOOR
    { 275,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FSQRT
    { 274,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FTANH
    { 273,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FSINH
    { 272,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FCOSH
    { 271,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FATAN2
    { 270,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FATAN
    { 269,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FASIN
    { 268,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FACOS
    { 267,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FTAN
    { 266,	3,	2,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FSINCOS
    { 265,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FSIN
    { 264,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FCOS
    { 263,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FCEIL
    { 262,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BITREVERSE
    { 261,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BSWAP
    { 260,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_CTPOP
    { 259,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_CTLZ_ZERO_UNDEF
    { 258,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_CTLZ
    { 257,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_CTTZ_ZERO_UNDEF
    { 256,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_CTTZ
    { 255,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 141,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECTOR_COMPRESS
    { 254,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STEP_VECTOR
    { 253,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SPLAT_VECTOR
    { 252,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 137,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SHUFFLE_VECTOR
    { 251,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 134,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_EXTRACT_VECTOR_ELT
    { 250,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 130,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INSERT_VECTOR_ELT
    { 249,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 61,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_EXTRACT_SUBVECTOR
    { 248,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 66,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INSERT_SUBVECTOR
    { 247,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VSCALE
    { 246,	3,	0,	0,	0,	0,	0,	AVROpInfoBase + 127,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BRJT
    { 245,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BR
    { 244,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_LLROUND
    { 243,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_LROUND
    { 242,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ABS
    { 241,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UMAX
    { 240,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UMIN
    { 239,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SMAX
    { 238,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SMIN
    { 237,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_PTRMASK
    { 236,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_PTR_ADD
    { 235,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SET_ROUNDING
    { 234,	1,	1,	0,	0,	0,	0,	AVROpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_GET_ROUNDING
    { 233,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_RESET_FPMODE
    { 232,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SET_FPMODE
    { 231,	1,	1,	0,	0,	0,	0,	AVROpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_GET_FPMODE
    { 230,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_RESET_FPENV
    { 229,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SET_FPENV
    { 228,	1,	1,	0,	0,	0,	0,	AVROpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_GET_FPENV
    { 227,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMAXIMUMNUM
    { 226,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMINIMUMNUM
    { 225,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMAXIMUM
    { 224,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMINIMUM
    { 223,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMAXNUM_IEEE
    { 222,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMINNUM_IEEE
    { 221,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMAXNUM
    { 220,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMINNUM
    { 219,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FCANONICALIZE
    { 218,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 101,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_IS_FPCLASS
    { 217,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FCOPYSIGN
    { 216,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FABS
    { 215,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FPTOUI_SAT
    { 214,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FPTOSI_SAT
    { 213,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UITOFP
    { 212,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SITOFP
    { 211,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FPTOUI
    { 210,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FPTOSI
    { 209,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FPTRUNC
    { 208,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FPEXT
    { 207,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FNEG
    { 206,	3,	2,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FFREXP
    { 205,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FLDEXP
    { 204,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FLOG10
    { 203,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FLOG2
    { 202,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FLOG
    { 201,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FEXP10
    { 200,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FEXP2
    { 199,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FEXP
    { 198,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FPOWI
    { 197,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FPOW
    { 196,	3,	2,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMODF
    { 195,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FREM
    { 194,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FDIV
    { 193,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 49,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMAD
    { 192,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 49,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMA
    { 191,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMUL
    { 190,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FSUB
    { 189,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FADD
    { 188,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UDIVFIXSAT
    { 187,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SDIVFIXSAT
    { 186,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UDIVFIX
    { 185,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SDIVFIX
    { 184,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UMULFIXSAT
    { 183,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SMULFIXSAT
    { 182,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UMULFIX
    { 181,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SMULFIX
    { 180,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SSHLSAT
    { 179,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_USHLSAT
    { 178,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SSUBSAT
    { 177,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_USUBSAT
    { 176,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SADDSAT
    { 175,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UADDSAT
    { 174,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SMULH
    { 173,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UMULH
    { 172,	4,	2,	0,	0,	0,	0,	AVROpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SMULO
    { 171,	4,	2,	0,	0,	0,	0,	AVROpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UMULO
    { 170,	5,	2,	0,	0,	0,	0,	AVROpInfoBase + 118,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SSUBE
    { 169,	4,	2,	0,	0,	0,	0,	AVROpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SSUBO
    { 168,	5,	2,	0,	0,	0,	0,	AVROpInfoBase + 118,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SADDE
    { 167,	4,	2,	0,	0,	0,	0,	AVROpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SADDO
    { 166,	5,	2,	0,	0,	0,	0,	AVROpInfoBase + 118,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_USUBE
    { 165,	4,	2,	0,	0,	0,	0,	AVROpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_USUBO
    { 164,	5,	2,	0,	0,	0,	0,	AVROpInfoBase + 118,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UADDE
    { 163,	4,	2,	0,	0,	0,	0,	AVROpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UADDO
    { 162,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SELECT
    { 161,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 115,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UCMP
    { 160,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 115,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SCMP
    { 159,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 111,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FCMP
    { 158,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 111,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ICMP
    { 157,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ROTL
    { 156,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ROTR
    { 155,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 107,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FSHR
    { 154,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 107,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FSHL
    { 153,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ASHR
    { 152,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_LSHR
    { 151,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SHL
    { 150,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ZEXT
    { 149,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 43,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SEXT_INREG
    { 148,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SEXT
    { 147,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 101,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VAARG
    { 146,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VASTART
    { 145,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FCONSTANT
    { 144,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_CONSTANT
    { 143,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_TRUNC_USAT_U
    { 142,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_TRUNC_SSAT_U
    { 141,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_TRUNC_SSAT_S
    { 140,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_TRUNC
    { 139,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ANYEXT
    { 138,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
    { 137,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // G_INTRINSIC_CONVERGENT
    { 136,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INTRINSIC_W_SIDE_EFFECTS
    { 135,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INTRINSIC
    { 134,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INVOKE_REGION_START
    { 133,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BRINDIRECT
    { 132,	2,	0,	0,	0,	0,	0,	AVROpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BRCOND
    { 131,	4,	0,	0,	0,	0,	0,	AVROpInfoBase + 97,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_PREFETCH
    { 130,	2,	0,	0,	0,	0,	0,	AVROpInfoBase + 24,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FENCE
    { 129,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_USUB_SAT
    { 128,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_USUB_COND
    { 127,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_UDEC_WRAP
    { 126,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_UINC_WRAP
    { 125,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_FMINIMUM
    { 124,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_FMAXIMUM
    { 123,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_FMIN
    { 122,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_FMAX
    { 121,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_FSUB
    { 120,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_FADD
    { 119,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_UMIN
    { 118,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_UMAX
    { 117,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_MIN
    { 116,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_MAX
    { 115,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_XOR
    { 114,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_OR
    { 113,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_NAND
    { 112,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_AND
    { 111,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_SUB
    { 110,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_ADD
    { 109,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_XCHG
    { 108,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMIC_CMPXCHG
    { 107,	5,	2,	0,	0,	0,	0,	AVROpInfoBase + 85,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMIC_CMPXCHG_WITH_SUCCESS
    { 106,	5,	1,	0,	0,	0,	0,	AVROpInfoBase + 80,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INDEXED_STORE
    { 105,	2,	0,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STORE
    { 104,	5,	2,	0,	0,	0,	0,	AVROpInfoBase + 75,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INDEXED_ZEXTLOAD
    { 103,	5,	2,	0,	0,	0,	0,	AVROpInfoBase + 75,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INDEXED_SEXTLOAD
    { 102,	5,	2,	0,	0,	0,	0,	AVROpInfoBase + 75,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INDEXED_LOAD
    { 101,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ZEXTLOAD
    { 100,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SEXTLOAD
    { 99,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_LOAD
    { 98,	1,	1,	0,	0,	0,	0,	AVROpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_READSTEADYCOUNTER
    { 97,	1,	1,	0,	0,	0,	0,	AVROpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_READCYCLECOUNTER
    { 96,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INTRINSIC_ROUNDEVEN
    { 95,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INTRINSIC_LLRINT
    { 94,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INTRINSIC_LRINT
    { 93,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INTRINSIC_ROUND
    { 92,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INTRINSIC_TRUNC
    { 91,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 72,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INTRINSIC_FPTRUNC_ROUND
    { 90,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_CONSTANT_FOLD_BARRIER
    { 89,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FREEZE
    { 88,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BITCAST
    { 87,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INTTOPTR
    { 86,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_PTRTOINT
    { 85,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_CONCAT_VECTORS
    { 84,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BUILD_VECTOR_TRUNC
    { 83,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BUILD_VECTOR
    { 82,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_MERGE_VALUES
    { 81,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 66,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INSERT
    { 80,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UNMERGE_VALUES
    { 79,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 61,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_EXTRACT
    { 78,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_CONSTANT_POOL
    { 77,	5,	1,	0,	0,	0,	0,	AVROpInfoBase + 56,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_PTRAUTH_GLOBAL_VALUE
    { 76,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_GLOBAL_VALUE
    { 75,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FRAME_INDEX
    { 74,	1,	1,	0,	0,	0,	0,	AVROpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_PHI
    { 73,	1,	1,	0,	0,	0,	0,	AVROpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_IMPLICIT_DEF
    { 72,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SAVGCEIL
    { 71,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SAVGFLOOR
    { 70,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UAVGCEIL
    { 69,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UAVGFLOOR
    { 68,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ABDU
    { 67,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ABDS
    { 66,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_XOR
    { 65,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_OR
    { 64,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_AND
    { 63,	4,	2,	0,	0,	0,	0,	AVROpInfoBase + 49,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UDIVREM
    { 62,	4,	2,	0,	0,	0,	0,	AVROpInfoBase + 49,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SDIVREM
    { 61,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UREM
    { 60,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SREM
    { 59,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UDIV
    { 58,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SDIV
    { 57,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_MUL
    { 56,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SUB
    { 55,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ADD
    { 54,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 43,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ASSERT_ALIGN
    { 53,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 43,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ASSERT_ZEXT
    { 52,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 43,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ASSERT_SEXT
    { 51,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // CONVERGENCECTRL_GLUE
    { 50,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 13,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // CONVERGENCECTRL_LOOP
    { 49,	1,	1,	0,	0,	0,	0,	AVROpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // CONVERGENCECTRL_ANCHOR
    { 48,	1,	1,	0,	0,	0,	0,	AVROpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // CONVERGENCECTRL_ENTRY
    { 47,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // RELOC_NONE
    { 46,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // JUMP_TABLE_DEBUG_INFO
    { 45,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // MEMBARRIER
    { 44,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // FAKE_USE
    { 43,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ICALL_BRANCH_FUNNEL
    { 42,	3,	0,	0,	0,	0,	0,	AVROpInfoBase + 40,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // anonymous_14916
    { 41,	2,	0,	0,	0,	0,	0,	AVROpInfoBase + 38,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // anonymous_14915
    { 40,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // PATCHABLE_TAIL_CALL
    { 39,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // PATCHABLE_FUNCTION_EXIT
    { 38,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // PATCHABLE_RET
    { 37,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // PATCHABLE_FUNCTION_ENTER
    { 36,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // PATCHABLE_OP
    { 35,	1,	1,	0,	0,	0,	0,	AVROpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // FAULTING_OP
    { 34,	2,	0,	0,	0,	0,	0,	AVROpInfoBase + 36,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LOCAL_ESCAPE
    { 33,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STATEPOINT
    { 32,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 33,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // anonymous_14914
    { 31,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // PREALLOCATED_SETUP
    { 30,	1,	1,	0,	0,	0,	0,	AVROpInfoBase + 32,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // anonymous_14196
    { 29,	6,	1,	0,	0,	0,	0,	AVROpInfoBase + 26,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // PATCHPOINT
    { 28,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // FENTRY_CALL
    { 27,	2,	0,	0,	0,	0,	0,	AVROpInfoBase + 24,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STACKMAP
    { 26,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 22,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ARITH_FENCE
    { 25,	4,	0,	0,	0,	0,	0,	AVROpInfoBase + 18,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // PSEUDO_PROBE
    { 24,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LIFETIME_END
    { 23,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LIFETIME_START
    { 22,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BUNDLE
    { 21,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 15,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // COPY_LANEMASK
    { 20,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 13,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // COPY
    { 19,	2,	1,	0,	0,	0,	0,	AVROpInfoBase + 13,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // REG_SEQUENCE
    { 18,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // DBG_LABEL
    { 17,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // DBG_PHI
    { 16,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // DBG_INSTR_REF
    { 15,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // DBG_VALUE_LIST
    { 14,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // DBG_VALUE
    { 13,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 2,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // COPY_TO_REGCLASS
    { 12,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 9,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SUBREG_TO_REG
    { 11,	1,	1,	0,	0,	0,	0,	AVROpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // INIT_UNDEF
    { 10,	1,	1,	0,	0,	0,	0,	AVROpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // IMPLICIT_DEF
    { 9,	4,	1,	0,	0,	0,	0,	AVROpInfoBase + 5,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // INSERT_SUBREG
    { 8,	3,	1,	0,	0,	0,	0,	AVROpInfoBase + 2,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // EXTRACT_SUBREG
    { 7,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // KILL
    { 6,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ANNOTATION_LABEL
    { 5,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // GC_LABEL
    { 4,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // EH_LABEL
    { 3,	1,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // CFI_INSTRUCTION
    { 2,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // INLINEASM_BR
    { 1,	0,	0,	0,	0,	0,	0,	AVROpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // INLINEASM
    { 0,	1,	1,	0,	0,	0,	0,	AVROpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // PHI
  }, {
    /* 0 */
    /* 0 */ AVR::SREG, AVR::SREG,
    /* 2 */ AVR::SREG,
    /* 3 */ AVR::SP, AVR::SP, AVR::SREG,
    /* 6 */ AVR::SP, AVR::R31R30,
    /* 8 */ AVR::R0,
    /* 9 */ AVR::R31R30,
    /* 10 */ AVR::SP, AVR::SP,
    /* 12 */ AVR::R1, AVR::SREG,
    /* 14 */ AVR::R17, AVR::SREG,
    /* 16 */ AVR::SP,
    /* 17 */ AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R1, AVR::R0,
    /* 33 */ AVR::R31R30, AVR::R0,
    /* 35 */ AVR::R1, AVR::R0, AVR::SREG,
    /* 38 */ AVR::R1, AVR::R0, AVR::R31R30,
  }, {
    0
  }, {
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 1 */
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 15 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 18 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
    /* 24 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 26 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 32 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 33 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 38 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 40 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 54 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 70 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 75 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 80 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 85 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 118 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 141 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 145 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 151 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 155 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 158 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 161 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 164 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 166 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 169 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 172 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 177 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 180 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 182 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 184 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 187 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 190 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 192 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 194 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 196 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 197 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 200 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 203 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 206 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 209 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 211 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 214 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 217 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 219 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 221 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 223 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) },
    /* 226 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 228 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 230 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 232 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 235 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 238 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 240 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 241 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 243 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 245 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 247 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 249 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8NOZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 252 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 255 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSNOZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 258 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 260 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 264 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 268 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 272 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 275 */ { AVR::IWREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::IWREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 278 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 281 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 284 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 286 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 288 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 290 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 292 */ { AVR::LD8loRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8loRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 294 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 296 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 299 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) },
    /* 302 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 304 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 306 */ { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 307 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 310 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 314 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
  }
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char AVRInstrNameData[] = {
  /* 0 */ "G_FLOG10\000"
  /* 9 */ "G_FEXP10\000"
  /* 18 */ "ROLBRdR1\000"
  /* 27 */ "Lsl32\000"
  /* 33 */ "Asr32\000"
  /* 39 */ "Lsr32\000"
  /* 45 */ "G_FLOG2\000"
  /* 53 */ "G_FATAN2\000"
  /* 62 */ "G_FEXP2\000"
  /* 70 */ "AtomicLoadSub16\000"
  /* 86 */ "AtomicLoad16\000"
  /* 99 */ "AtomicLoadAdd16\000"
  /* 115 */ "AtomicLoadAnd16\000"
  /* 131 */ "AtomicStore16\000"
  /* 145 */ "Rol16\000"
  /* 151 */ "Lsl16\000"
  /* 157 */ "AtomicLoadOr16\000"
  /* 172 */ "Ror16\000"
  /* 178 */ "AtomicLoadXor16\000"
  /* 194 */ "Asr16\000"
  /* 200 */ "Lsr16\000"
  /* 206 */ "Select16\000"
  /* 215 */ "ROLBRdR17\000"
  /* 225 */ "AtomicLoadSub8\000"
  /* 240 */ "AtomicLoad8\000"
  /* 252 */ "AtomicLoadAdd8\000"
  /* 267 */ "AtomicLoadAnd8\000"
  /* 282 */ "AtomicStore8\000"
  /* 295 */ "Rol8\000"
  /* 300 */ "Lsl8\000"
  /* 305 */ "AtomicLoadOr8\000"
  /* 319 */ "Ror8\000"
  /* 324 */ "AtomicLoadXor8\000"
  /* 339 */ "Asr8\000"
  /* 344 */ "Lsr8\000"
  /* 349 */ "Select8\000"
  /* 357 */ "G_FMA\000"
  /* 363 */ "G_STRICT_FMA\000"
  /* 376 */ "INRdA\000"
  /* 382 */ "INWRdA\000"
  /* 389 */ "G_FSUB\000"
  /* 396 */ "G_STRICT_FSUB\000"
  /* 410 */ "G_ATOMICRMW_FSUB\000"
  /* 427 */ "G_SUB\000"
  /* 433 */ "G_ATOMICRMW_SUB\000"
  /* 449 */ "SBRCRrB\000"
  /* 457 */ "SBRSRrB\000"
  /* 465 */ "G_INTRINSIC\000"
  /* 477 */ "G_FPTRUNC\000"
  /* 487 */ "G_INTRINSIC_TRUNC\000"
  /* 505 */ "G_TRUNC\000"
  /* 513 */ "G_BUILD_VECTOR_TRUNC\000"
  /* 534 */ "G_DYN_STACKALLOC\000"
  /* 551 */ "SPREAD\000"
  /* 558 */ "G_FMAD\000"
  /* 565 */ "G_INDEXED_SEXTLOAD\000"
  /* 584 */ "G_SEXTLOAD\000"
  /* 595 */ "G_INDEXED_ZEXTLOAD\000"
  /* 614 */ "G_ZEXTLOAD\000"
  /* 625 */ "G_INDEXED_LOAD\000"
  /* 640 */ "G_LOAD\000"
  /* 647 */ "G_VECREDUCE_FADD\000"
  /* 664 */ "G_FADD\000"
  /* 671 */ "G_VECREDUCE_SEQ_FADD\000"
  /* 692 */ "G_STRICT_FADD\000"
  /* 706 */ "G_ATOMICRMW_FADD\000"
  /* 723 */ "G_VECREDUCE_ADD\000"
  /* 739 */ "G_ADD\000"
  /* 745 */ "G_PTR_ADD\000"
  /* 755 */ "G_ATOMICRMW_ADD\000"
  /* 771 */ "BLD\000"
  /* 775 */ "G_ATOMICRMW_NAND\000"
  /* 792 */ "G_VECREDUCE_AND\000"
  /* 808 */ "G_AND\000"
  /* 814 */ "G_ATOMICRMW_AND\000"
  /* 830 */ "LIFETIME_END\000"
  /* 843 */ "G_BRCOND\000"
  /* 852 */ "G_ATOMICRMW_USUB_COND\000"
  /* 874 */ "G_LLROUND\000"
  /* 884 */ "G_LROUND\000"
  /* 893 */ "G_INTRINSIC_ROUND\000"
  /* 911 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
  /* 937 */ "LOAD_STACK_GUARD\000"
  /* 954 */ "PSEUDO_PROBE\000"
  /* 967 */ "G_SSUBE\000"
  /* 975 */ "G_USUBE\000"
  /* 983 */ "G_FENCE\000"
  /* 991 */ "ARITH_FENCE\000"
  /* 1003 */ "REG_SEQUENCE\000"
  /* 1016 */ "G_SADDE\000"
  /* 1024 */ "G_UADDE\000"
  /* 1032 */ "G_GET_FPMODE\000"
  /* 1045 */ "G_RESET_FPMODE\000"
  /* 1060 */ "G_SET_FPMODE\000"
  /* 1073 */ "G_FMINNUM_IEEE\000"
  /* 1088 */ "G_FMAXNUM_IEEE\000"
  /* 1103 */ "G_VSCALE\000"
  /* 1112 */ "G_JUMP_TABLE\000"
  /* 1125 */ "BUNDLE\000"
  /* 1132 */ "G_MEMCPY_INLINE\000"
  /* 1148 */ "RELOC_NONE\000"
  /* 1159 */ "LOCAL_ESCAPE\000"
  /* 1172 */ "G_STACKRESTORE\000"
  /* 1187 */ "G_INDEXED_STORE\000"
  /* 1203 */ "G_STORE\000"
  /* 1211 */ "CPSE\000"
  /* 1216 */ "G_BITREVERSE\000"
  /* 1229 */ "FAKE_USE\000"
  /* 1238 */ "SPWRITE\000"
  /* 1246 */ "DBG_VALUE\000"
  /* 1256 */ "G_GLOBAL_VALUE\000"
  /* 1271 */ "G_PTRAUTH_GLOBAL_VALUE\000"
  /* 1294 */ "CONVERGENCECTRL_GLUE\000"
  /* 1315 */ "G_STACKSAVE\000"
  /* 1327 */ "G_MEMMOVE\000"
  /* 1337 */ "G_FREEZE\000"
  /* 1346 */ "G_FCANONICALIZE\000"
  /* 1362 */ "G_FMODF\000"
  /* 1370 */ "G_CTLZ_ZERO_UNDEF\000"
  /* 1388 */ "G_CTTZ_ZERO_UNDEF\000"
  /* 1406 */ "INIT_UNDEF\000"
  /* 1417 */ "G_IMPLICIT_DEF\000"
  /* 1432 */ "DBG_INSTR_REF\000"
  /* 1446 */ "G_FNEG\000"
  /* 1453 */ "EXTRACT_SUBREG\000"
  /* 1468 */ "INSERT_SUBREG\000"
  /* 1482 */ "G_SEXT_INREG\000"
  /* 1495 */ "SUBREG_TO_REG\000"
  /* 1509 */ "G_ATOMIC_CMPXCHG\000"
  /* 1526 */ "G_ATOMICRMW_XCHG\000"
  /* 1543 */ "G_GET_ROUNDING\000"
  /* 1558 */ "G_SET_ROUNDING\000"
  /* 1573 */ "G_FLOG\000"
  /* 1580 */ "G_VAARG\000"
  /* 1588 */ "PREALLOCATED_ARG\000"
  /* 1605 */ "G_PREFETCH\000"
  /* 1616 */ "G_SMULH\000"
  /* 1624 */ "G_UMULH\000"
  /* 1632 */ "G_FTANH\000"
  /* 1640 */ "G_FSINH\000"
  /* 1648 */ "G_FCOSH\000"
  /* 1656 */ "DBG_PHI\000"
  /* 1664 */ "G_FPTOSI\000"
  /* 1673 */ "RETI\000"
  /* 1678 */ "G_FPTOUI\000"
  /* 1687 */ "G_FPOWI\000"
  /* 1695 */ "BREAK\000"
  /* 1701 */ "COPY_LANEMASK\000"
  /* 1715 */ "G_PTRMASK\000"
  /* 1725 */ "DESK\000"
  /* 1730 */ "SUBIRdK\000"
  /* 1738 */ "SBCIRdK\000"
  /* 1746 */ "LDIRdK\000"
  /* 1753 */ "ANDIRdK\000"
  /* 1761 */ "CPIRdK\000"
  /* 1768 */ "ORIRdK\000"
  /* 1775 */ "LDSRdK\000"
  /* 1782 */ "SBIWRdK\000"
  /* 1790 */ "SUBIWRdK\000"
  /* 1799 */ "SBCIWRdK\000"
  /* 1808 */ "ADIWRdK\000"
  /* 1816 */ "LDIWRdK\000"
  /* 1824 */ "ANDIWRdK\000"
  /* 1833 */ "ORIWRdK\000"
  /* 1841 */ "LDSWRdK\000"
  /* 1849 */ "GC_LABEL\000"
  /* 1858 */ "DBG_LABEL\000"
  /* 1868 */ "EH_LABEL\000"
  /* 1877 */ "ANNOTATION_LABEL\000"
  /* 1894 */ "ICALL_BRANCH_FUNNEL\000"
  /* 1914 */ "G_FSHL\000"
  /* 1921 */ "G_SHL\000"
  /* 1927 */ "G_FCEIL\000"
  /* 1935 */ "G_SAVGCEIL\000"
  /* 1946 */ "G_UAVGCEIL\000"
  /* 1957 */ "EICALL\000"
  /* 1964 */ "PATCHABLE_TAIL_CALL\000"
  /* 1984 */ "PATCHABLE_TYPED_EVENT_CALL\000"
  /* 2011 */ "PATCHABLE_EVENT_CALL\000"
  /* 2032 */ "FENTRY_CALL\000"
  /* 2044 */ "KILL\000"
  /* 2049 */ "G_CONSTANT_POOL\000"
  /* 2065 */ "G_ROTL\000"
  /* 2072 */ "G_VECREDUCE_FMUL\000"
  /* 2089 */ "G_FMUL\000"
  /* 2096 */ "G_VECREDUCE_SEQ_FMUL\000"
  /* 2117 */ "G_STRICT_FMUL\000"
  /* 2131 */ "G_VECREDUCE_MUL\000"
  /* 2147 */ "G_MUL\000"
  /* 2153 */ "G_FREM\000"
  /* 2160 */ "G_STRICT_FREM\000"
  /* 2174 */ "G_SREM\000"
  /* 2181 */ "G_UREM\000"
  /* 2188 */ "G_SDIVREM\000"
  /* 2198 */ "G_UDIVREM\000"
  /* 2208 */ "ELPM\000"
  /* 2213 */ "SPM\000"
  /* 2217 */ "INLINEASM\000"
  /* 2227 */ "G_VECREDUCE_FMINIMUM\000"
  /* 2248 */ "G_FMINIMUM\000"
  /* 2259 */ "G_ATOMICRMW_FMINIMUM\000"
  /* 2280 */ "G_VECREDUCE_FMAXIMUM\000"
  /* 2301 */ "G_FMAXIMUM\000"
  /* 2312 */ "G_ATOMICRMW_FMAXIMUM\000"
  /* 2333 */ "G_FMINIMUMNUM\000"
  /* 2347 */ "G_FMAXIMUMNUM\000"
  /* 2361 */ "G_FMINNUM\000"
  /* 2371 */ "G_FMAXNUM\000"
  /* 2381 */ "G_FATAN\000"
  /* 2389 */ "G_FTAN\000"
  /* 2396 */ "G_INTRINSIC_ROUNDEVEN\000"
  /* 2418 */ "G_ASSERT_ALIGN\000"
  /* 2433 */ "G_FCOPYSIGN\000"
  /* 2445 */ "G_VECREDUCE_FMIN\000"
  /* 2462 */ "G_ATOMICRMW_FMIN\000"
  /* 2479 */ "G_VECREDUCE_SMIN\000"
  /* 2496 */ "G_SMIN\000"
  /* 2503 */ "G_VECREDUCE_UMIN\000"
  /* 2520 */ "G_UMIN\000"
  /* 2527 */ "G_ATOMICRMW_UMIN\000"
  /* 2544 */ "G_ATOMICRMW_MIN\000"
  /* 2560 */ "G_FASIN\000"
  /* 2568 */ "G_FSIN\000"
  /* 2575 */ "CFI_INSTRUCTION\000"
  /* 2591 */ "ADJCALLSTACKDOWN\000"
  /* 2608 */ "G_SSUBO\000"
  /* 2616 */ "G_USUBO\000"
  /* 2624 */ "G_SADDO\000"
  /* 2632 */ "G_UADDO\000"
  /* 2640 */ "JUMP_TABLE_DEBUG_INFO\000"
  /* 2662 */ "G_SMULO\000"
  /* 2670 */ "G_UMULO\000"
  /* 2678 */ "G_BZERO\000"
  /* 2686 */ "STACKMAP\000"
  /* 2695 */ "G_DEBUGTRAP\000"
  /* 2707 */ "G_UBSANTRAP\000"
  /* 2719 */ "G_TRAP\000"
  /* 2726 */ "G_ATOMICRMW_UDEC_WRAP\000"
  /* 2748 */ "G_ATOMICRMW_UINC_WRAP\000"
  /* 2770 */ "G_BSWAP\000"
  /* 2778 */ "SLEEP\000"
  /* 2784 */ "G_SITOFP\000"
  /* 2793 */ "G_UITOFP\000"
  /* 2802 */ "G_FCMP\000"
  /* 2809 */ "G_ICMP\000"
  /* 2816 */ "G_SCMP\000"
  /* 2823 */ "G_UCMP\000"
  /* 2830 */ "EIJMP\000"
  /* 2836 */ "NOP\000"
  /* 2840 */ "CONVERGENCECTRL_LOOP\000"
  /* 2861 */ "G_CTPOP\000"
  /* 2869 */ "PATCHABLE_OP\000"
  /* 2882 */ "FAULTING_OP\000"
  /* 2894 */ "ADJCALLSTACKUP\000"
  /* 2909 */ "PREALLOCATED_SETUP\000"
  /* 2928 */ "G_FLDEXP\000"
  /* 2937 */ "G_STRICT_FLDEXP\000"
  /* 2953 */ "G_FEXP\000"
  /* 2960 */ "G_FFREXP\000"
  /* 2969 */ "LDDWRdYQ\000"
  /* 2978 */ "LDDRdPtrQ\000"
  /* 2988 */ "LDDWRdPtrQ\000"
  /* 2999 */ "G_BR\000"
  /* 3004 */ "INLINEASM_BR\000"
  /* 3017 */ "G_BLOCK_ADDR\000"
  /* 3030 */ "WDR\000"
  /* 3034 */ "MEMBARRIER\000"
  /* 3045 */ "G_CONSTANT_FOLD_BARRIER\000"
  /* 3069 */ "PATCHABLE_FUNCTION_ENTER\000"
  /* 3094 */ "G_READCYCLECOUNTER\000"
  /* 3113 */ "G_READSTEADYCOUNTER\000"
  /* 3133 */ "G_READ_REGISTER\000"
  /* 3149 */ "G_WRITE_REGISTER\000"
  /* 3166 */ "G_ASHR\000"
  /* 3173 */ "G_FSHR\000"
  /* 3180 */ "G_LSHR\000"
  /* 3187 */ "CONVERGENCECTRL_ANCHOR\000"
  /* 3210 */ "G_FFLOOR\000"
  /* 3219 */ "G_SAVGFLOOR\000"
  /* 3231 */ "G_UAVGFLOOR\000"
  /* 3243 */ "G_EXTRACT_SUBVECTOR\000"
  /* 3263 */ "G_INSERT_SUBVECTOR\000"
  /* 3282 */ "G_BUILD_VECTOR\000"
  /* 3297 */ "G_SHUFFLE_VECTOR\000"
  /* 3314 */ "G_STEP_VECTOR\000"
  /* 3328 */ "G_SPLAT_VECTOR\000"
  /* 3343 */ "G_VECREDUCE_XOR\000"
  /* 3359 */ "G_XOR\000"
  /* 3365 */ "G_ATOMICRMW_XOR\000"
  /* 3381 */ "G_VECREDUCE_OR\000"
  /* 3396 */ "G_OR\000"
  /* 3401 */ "G_ATOMICRMW_OR\000"
  /* 3416 */ "G_ROTR\000"
  /* 3423 */ "G_INTTOPTR\000"
  /* 3434 */ "G_FABS\000"
  /* 3441 */ "G_ABS\000"
  /* 3447 */ "G_ABDS\000"
  /* 3454 */ "G_UNMERGE_VALUES\000"
  /* 3471 */ "G_MERGE_VALUES\000"
  /* 3486 */ "FMULS\000"
  /* 3492 */ "G_FACOS\000"
  /* 3500 */ "G_FCOS\000"
  /* 3507 */ "G_FSINCOS\000"
  /* 3517 */ "G_CONCAT_VECTORS\000"
  /* 3534 */ "COPY_TO_REGCLASS\000"
  /* 3551 */ "G_IS_FPCLASS\000"
  /* 3564 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
  /* 3594 */ "G_VECTOR_COMPRESS\000"
  /* 3612 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
  /* 3639 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
  /* 3677 */ "G_TRUNC_SSAT_S\000"
  /* 3692 */ "G_SSUBSAT\000"
  /* 3702 */ "G_USUBSAT\000"
  /* 3712 */ "G_SADDSAT\000"
  /* 3722 */ "G_UADDSAT\000"
  /* 3732 */ "G_SSHLSAT\000"
  /* 3742 */ "G_USHLSAT\000"
  /* 3752 */ "G_SMULFIXSAT\000"
  /* 3765 */ "G_UMULFIXSAT\000"
  /* 3778 */ "G_SDIVFIXSAT\000"
  /* 3791 */ "G_UDIVFIXSAT\000"
  /* 3804 */ "G_ATOMICRMW_USUB_SAT\000"
  /* 3825 */ "G_FPTOSI_SAT\000"
  /* 3838 */ "G_FPTOUI_SAT\000"
  /* 3851 */ "G_EXTRACT\000"
  /* 3861 */ "G_SELECT\000"
  /* 3870 */ "G_BRINDIRECT\000"
  /* 3883 */ "PATCHABLE_RET\000"
  /* 3897 */ "G_MEMSET\000"
  /* 3906 */ "PATCHABLE_FUNCTION_EXIT\000"
  /* 3930 */ "G_BRJT\000"
  /* 3937 */ "G_EXTRACT_VECTOR_ELT\000"
  /* 3958 */ "G_INSERT_VECTOR_ELT\000"
  /* 3978 */ "G_FCONSTANT\000"
  /* 3990 */ "G_CONSTANT\000"
  /* 4001 */ "G_INTRINSIC_CONVERGENT\000"
  /* 4024 */ "STATEPOINT\000"
  /* 4035 */ "PATCHPOINT\000"
  /* 4046 */ "G_PTRTOINT\000"
  /* 4057 */ "G_FRINT\000"
  /* 4065 */ "G_INTRINSIC_LLRINT\000"
  /* 4084 */ "G_INTRINSIC_LRINT\000"
  /* 4102 */ "G_FNEARBYINT\000"
  /* 4115 */ "G_VASTART\000"
  /* 4125 */ "LIFETIME_START\000"
  /* 4140 */ "G_INVOKE_REGION_START\000"
  /* 4162 */ "G_INSERT\000"
  /* 4171 */ "G_FSQRT\000"
  /* 4179 */ "G_STRICT_FSQRT\000"
  /* 4194 */ "G_BITCAST\000"
  /* 4204 */ "G_ADDRSPACE_CAST\000"
  /* 4221 */ "BST\000"
  /* 4225 */ "DBG_VALUE_LIST\000"
  /* 4240 */ "G_FPEXT\000"
  /* 4248 */ "G_SEXT\000"
  /* 4255 */ "G_ASSERT_SEXT\000"
  /* 4269 */ "G_ANYEXT\000"
  /* 4278 */ "G_ZEXT\000"
  /* 4285 */ "G_ASSERT_ZEXT\000"
  /* 4299 */ "G_ABDU\000"
  /* 4306 */ "FMULSU\000"
  /* 4313 */ "G_TRUNC_SSAT_U\000"
  /* 4328 */ "G_TRUNC_USAT_U\000"
  /* 4343 */ "G_FDIV\000"
  /* 4350 */ "G_STRICT_FDIV\000"
  /* 4364 */ "G_SDIV\000"
  /* 4371 */ "G_UDIV\000"
  /* 4378 */ "G_GET_FPENV\000"
  /* 4390 */ "G_RESET_FPENV\000"
  /* 4404 */ "G_SET_FPENV\000"
  /* 4416 */ "G_FPOW\000"
  /* 4423 */ "G_VECREDUCE_FMAX\000"
  /* 4440 */ "G_ATOMICRMW_FMAX\000"
  /* 4457 */ "G_VECREDUCE_SMAX\000"
  /* 4474 */ "G_SMAX\000"
  /* 4481 */ "G_VECREDUCE_UMAX\000"
  /* 4498 */ "G_UMAX\000"
  /* 4505 */ "G_ATOMICRMW_UMAX\000"
  /* 4522 */ "G_ATOMICRMW_MAX\000"
  /* 4538 */ "FRMIDX\000"
  /* 4545 */ "G_FRAME_INDEX\000"
  /* 4559 */ "G_SBFX\000"
  /* 4566 */ "G_UBFX\000"
  /* 4573 */ "G_SMULFIX\000"
  /* 4583 */ "G_UMULFIX\000"
  /* 4593 */ "G_SDIVFIX\000"
  /* 4603 */ "G_UDIVFIX\000"
  /* 4613 */ "G_MEMCPY\000"
  /* 4622 */ "COPY\000"
  /* 4627 */ "CONVERGENCECTRL_ENTRY\000"
  /* 4649 */ "G_CTLZ\000"
  /* 4656 */ "G_CTTZ\000"
  /* 4663 */ "ELPMBRdZ\000"
  /* 4672 */ "ELPMRdZ\000"
  /* 4680 */ "ELPMWRdZ\000"
  /* 4689 */ "SBICAb\000"
  /* 4696 */ "CBIAb\000"
  /* 4702 */ "SBIAb\000"
  /* 4708 */ "SBISAb\000"
  /* 4715 */ "LDRdPtrPd\000"
  /* 4725 */ "LDWRdPtrPd\000"
  /* 4736 */ "RORBRd\000"
  /* 4743 */ "DECRd\000"
  /* 4749 */ "INCRd\000"
  /* 4755 */ "NEGRd\000"
  /* 4761 */ "COMRd\000"
  /* 4767 */ "LSLBNRd\000"
  /* 4775 */ "ASRBNRd\000"
  /* 4783 */ "LSRBNRd\000"
  /* 4791 */ "LSLWNRd\000"
  /* 4799 */ "ASRWNRd\000"
  /* 4807 */ "LSRWNRd\000"
  /* 4815 */ "SWAPRd\000"
  /* 4822 */ "POPRd\000"
  /* 4828 */ "RORRd\000"
  /* 4834 */ "ASRRd\000"
  /* 4840 */ "LSRRd\000"
  /* 4846 */ "NEGWRd\000"
  /* 4853 */ "ROLWRd\000"
  /* 4860 */ "LSLWRd\000"
  /* 4867 */ "COMWRd\000"
  /* 4874 */ "POPWRd\000"
  /* 4881 */ "RORWRd\000"
  /* 4888 */ "ASRWRd\000"
  /* 4895 */ "LSRWRd\000"
  /* 4902 */ "LACZRd\000"
  /* 4909 */ "XCHZRd\000"
  /* 4916 */ "LASZRd\000"
  /* 4923 */ "LATZRd\000"
  /* 4930 */ "LSLWHiRd\000"
  /* 4939 */ "ASRWLoRd\000"
  /* 4948 */ "LSRWLoRd\000"
  /* 4957 */ "AtomicFence\000"
  /* 4969 */ "SPMZPi\000"
  /* 4976 */ "ELPMBRdZPi\000"
  /* 4987 */ "ELPMRdZPi\000"
  /* 4997 */ "ELPMWRdZPi\000"
  /* 5008 */ "LDRdPtrPi\000"
  /* 5018 */ "LDWRdPtrPi\000"
  /* 5029 */ "BRGEk\000"
  /* 5035 */ "BRNEk\000"
  /* 5041 */ "BRSHk\000"
  /* 5047 */ "BRMIk\000"
  /* 5053 */ "RCALLk\000"
  /* 5060 */ "BRPLk\000"
  /* 5066 */ "BRLOk\000"
  /* 5072 */ "RJMPk\000"
  /* 5078 */ "BREQk\000"
  /* 5084 */ "BRLTk\000"
  /* 5090 */ "BRBCsk\000"
  /* 5097 */ "BRBSsk\000"
  /* 5104 */ "CopyZero\000"
  /* 5113 */ "OUTARr\000"
  /* 5120 */ "OUTWARr\000"
  /* 5128 */ "PUSHRr\000"
  /* 5135 */ "STSKRr\000"
  /* 5142 */ "STSWKRr\000"
  /* 5150 */ "STDSPQRr\000"
  /* 5159 */ "STDWSPQRr\000"
  /* 5169 */ "STDPtrQRr\000"
  /* 5179 */ "STDWPtrQRr\000"
  /* 5190 */ "PUSHWRr\000"
  /* 5198 */ "STPtrPdRr\000"
  /* 5208 */ "STWPtrPdRr\000"
  /* 5219 */ "SUBRdRr\000"
  /* 5227 */ "SBCRdRr\000"
  /* 5235 */ "ADCRdRr\000"
  /* 5243 */ "CPCRdRr\000"
  /* 5251 */ "ADDRdRr\000"
  /* 5259 */ "ANDRdRr\000"
  /* 5267 */ "MULRdRr\000"
  /* 5275 */ "CPRdRr\000"
  /* 5282 */ "EORRdRr\000"
  /* 5290 */ "MULSRdRr\000"
  /* 5299 */ "MULSURdRr\000"
  /* 5309 */ "MOVRdRr\000"
  /* 5317 */ "SUBWRdRr\000"
  /* 5326 */ "SBCWRdRr\000"
  /* 5335 */ "ADCWRdRr\000"
  /* 5344 */ "CPCWRdRr\000"
  /* 5353 */ "ADDWRdRr\000"
  /* 5362 */ "ANDWRdRr\000"
  /* 5371 */ "CPWRdRr\000"
  /* 5379 */ "EORWRdRr\000"
  /* 5388 */ "MOVWRdRr\000"
  /* 5397 */ "STPtrPiRr\000"
  /* 5407 */ "STWPtrPiRr\000"
  /* 5418 */ "STPtrRr\000"
  /* 5426 */ "STWPtrRr\000"
  /* 5435 */ "LDRdPtr\000"
  /* 5443 */ "LDWRdPtr\000"
  /* 5452 */ "BCLRs\000"
  /* 5458 */ "BSETs\000"
  /* 5464 */ "LDSRdKTiny\000"
  /* 5475 */ "STSKRrTiny\000"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const unsigned AVRInstrNameIndices[] = {
    1660U, 2217U, 3004U, 2575U, 1868U, 1849U, 1877U, 2044U, 
    1453U, 1468U, 1419U, 1406U, 1495U, 3534U, 1246U, 4225U, 
    1432U, 1656U, 1858U, 1003U, 4622U, 1701U, 1125U, 4125U, 
    830U, 954U, 991U, 2686U, 2032U, 4035U, 937U, 2909U, 
    1588U, 4024U, 1159U, 2882U, 2869U, 3069U, 3883U, 3906U, 
    1964U, 2011U, 1984U, 1894U, 1229U, 3034U, 2640U, 1148U, 
    4627U, 3187U, 2840U, 1294U, 4255U, 4285U, 2418U, 739U, 
    427U, 2147U, 4364U, 4371U, 2174U, 2181U, 2188U, 2198U, 
    808U, 3396U, 3359U, 3447U, 4299U, 3231U, 1946U, 3219U, 
    1935U, 1417U, 1658U, 4545U, 1256U, 1271U, 2049U, 3851U, 
    3454U, 4162U, 3471U, 3282U, 513U, 3517U, 4046U, 3423U, 
    4194U, 1337U, 3045U, 911U, 487U, 893U, 4084U, 4065U, 
    2396U, 3094U, 3113U, 640U, 584U, 614U, 625U, 565U, 
    595U, 1203U, 1187U, 3564U, 1509U, 1526U, 755U, 433U, 
    814U, 775U, 3401U, 3365U, 4522U, 2544U, 4505U, 2527U, 
    706U, 410U, 4440U, 2462U, 2312U, 2259U, 2748U, 2726U, 
    852U, 3804U, 983U, 1605U, 843U, 3870U, 4140U, 465U, 
    3612U, 4001U, 3639U, 4269U, 505U, 3677U, 4313U, 4328U, 
    3990U, 3978U, 4115U, 1580U, 4248U, 1482U, 4278U, 1921U, 
    3180U, 3166U, 1914U, 3173U, 3416U, 2065U, 2809U, 2802U, 
    2816U, 2823U, 3861U, 2632U, 1024U, 2616U, 975U, 2624U, 
    1016U, 2608U, 967U, 2670U, 2662U, 1624U, 1616U, 3722U, 
    3712U, 3702U, 3692U, 3742U, 3732U, 4573U, 4583U, 3752U, 
    3765U, 4593U, 4603U, 3778U, 3791U, 664U, 389U, 2089U, 
    357U, 558U, 4343U, 2153U, 1362U, 4416U, 1687U, 2953U, 
    62U, 9U, 1573U, 45U, 0U, 2928U, 2960U, 1446U, 
    4240U, 477U, 1664U, 1678U, 2784U, 2793U, 3825U, 3838U, 
    3434U, 2433U, 3551U, 1346U, 2361U, 2371U, 1073U, 1088U, 
    2248U, 2301U, 2333U, 2347U, 4378U, 4404U, 4390U, 1032U, 
    1060U, 1045U, 1543U, 1558U, 745U, 1715U, 2496U, 4474U, 
    2520U, 4498U, 3441U, 884U, 874U, 2999U, 3930U, 1103U, 
    3263U, 3243U, 3958U, 3937U, 3297U, 3328U, 3314U, 3594U, 
    4656U, 1388U, 4649U, 1370U, 2861U, 2770U, 1216U, 1927U, 
    3500U, 2568U, 3507U, 2389U, 3492U, 2560U, 2381U, 53U, 
    1648U, 1640U, 1632U, 4171U, 3210U, 4057U, 4102U, 4204U, 
    3017U, 1112U, 534U, 1315U, 1172U, 692U, 396U, 2117U, 
    4350U, 2160U, 363U, 4179U, 2937U, 3133U, 3149U, 4613U, 
    1132U, 1327U, 3897U, 2678U, 2719U, 2695U, 2707U, 671U, 
    2096U, 647U, 2072U, 4423U, 2445U, 2280U, 2227U, 723U, 
    2131U, 792U, 3381U, 3343U, 4457U, 2479U, 4481U, 2503U, 
    4559U, 4566U, 5335U, 5353U, 2591U, 2894U, 1824U, 5362U, 
    4775U, 4939U, 4799U, 4888U, 194U, 33U, 339U, 4957U, 
    86U, 240U, 99U, 252U, 115U, 267U, 157U, 305U, 
    70U, 225U, 178U, 324U, 131U, 282U, 4867U, 5344U, 
    5371U, 5104U, 4663U, 4976U, 4680U, 4997U, 5379U, 4538U, 
    382U, 2988U, 2969U, 1816U, 1841U, 5443U, 4725U, 5018U, 
    4664U, 4681U, 4998U, 4767U, 4930U, 4791U, 4860U, 4783U, 
    4948U, 4807U, 4895U, 151U, 27U, 300U, 200U, 39U, 
    344U, 4846U, 1833U, 5380U, 5120U, 4874U, 5190U, 18U, 
    215U, 4853U, 4736U, 4881U, 145U, 295U, 172U, 319U, 
    1799U, 5326U, 4250U, 551U, 1238U, 5150U, 5179U, 5159U, 
    5142U, 5208U, 5407U, 5426U, 1790U, 5317U, 206U, 349U, 
    4280U, 5235U, 5251U, 1808U, 1753U, 5259U, 4834U, 5452U, 
    771U, 5090U, 5097U, 1695U, 5078U, 5029U, 5066U, 5084U, 
    5047U, 5035U, 5060U, 5041U, 5458U, 4221U, 5054U, 4696U, 
    4761U, 5243U, 1761U, 5275U, 1211U, 4743U, 1725U, 1957U, 
    2830U, 2208U, 4672U, 4987U, 5282U, 2084U, 3486U, 4306U, 
    1958U, 2831U, 4749U, 376U, 5073U, 4902U, 4916U, 4923U, 
    2978U, 1746U, 5435U, 4715U, 5008U, 1775U, 5464U, 2209U, 
    4673U, 4988U, 4840U, 5309U, 5388U, 5267U, 5290U, 5299U, 
    4755U, 2836U, 1768U, 5283U, 5113U, 4822U, 5128U, 5053U, 
    3893U, 1673U, 5072U, 4828U, 1738U, 5227U, 4702U, 4689U, 
    4708U, 1782U, 449U, 457U, 2778U, 2213U, 4969U, 5169U, 
    5198U, 5397U, 5418U, 5135U, 5475U, 1730U, 5219U, 4815U, 
    3030U, 4909U, 
};

static inline void InitAVRMCInstrInfo(MCInstrInfo *II) {
  II->InitMCInstrInfo(AVRDescs.Insts, AVRInstrNameIndices, AVRInstrNameData, nullptr, nullptr, 514, nullptr, 0);
}


} // namespace llvm

#endif // GET_INSTRINFO_MC_DESC

#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER

namespace llvm {

struct AVRGenInstrInfo : public TargetInstrInfo {
  explicit AVRGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
  ~AVRGenInstrInfo() override = default;
};

} // namespace llvm

namespace llvm::AVR {


} // namespace llvm::AVR

#endif // GET_INSTRINFO_HEADER

#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS


#endif // GET_INSTRINFO_HELPER_DECLS

#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS


#endif // GET_INSTRINFO_HELPERS

#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR

namespace llvm {

extern const AVRInstrTable AVRDescs;
extern const unsigned AVRInstrNameIndices[];
extern const char AVRInstrNameData[];
AVRGenInstrInfo::AVRGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
  : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
  InitMCInstrInfo(AVRDescs.Insts, AVRInstrNameIndices, AVRInstrNameData, nullptr, nullptr, 514);
}

} // namespace llvm

#endif // GET_INSTRINFO_CTOR_DTOR

#ifdef GET_INSTRINFO_MC_HELPER_DECLS
#undef GET_INSTRINFO_MC_HELPER_DECLS

namespace llvm {

class MCInst;
class FeatureBitset;

namespace AVR_MC {

void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);

} // namespace AVR_MC

} // namespace llvm

#endif // GET_INSTRINFO_MC_HELPER_DECLS

#ifdef GET_INSTRINFO_MC_HELPERS
#undef GET_INSTRINFO_MC_HELPERS

namespace llvm::AVR_MC {


} // namespace llvm::AVR_MC

#endif // GET_INSTRINFO_MC_HELPERS

#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
    defined(GET_AVAILABLE_OPCODE_CHECKER)
#define GET_COMPUTE_FEATURES
#endif
#ifdef GET_COMPUTE_FEATURES
#undef GET_COMPUTE_FEATURES

namespace llvm::AVR_MC {

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
  Feature_HasSRAMBit = 14,
  Feature_HasJMPCALLBit = 7,
  Feature_HasIJMPCALLBit = 6,
  Feature_HasEIJMPCALLBit = 3,
  Feature_HasADDSUBIWBit = 0,
  Feature_HasSmallStackBit = 15,
  Feature_HasMOVWBit = 10,
  Feature_HasLPMBit = 8,
  Feature_HasLPMXBit = 9,
  Feature_HasELPMBit = 4,
  Feature_HasELPMXBit = 5,
  Feature_HasSPMBit = 12,
  Feature_HasSPMXBit = 13,
  Feature_HasDESBit = 2,
  Feature_SupportsRMWBit = 18,
  Feature_SupportsMultiplicationBit = 17,
  Feature_HasBREAKBit = 1,
  Feature_HasTinyEncodingBit = 16,
  Feature_HasNonTinyEncodingBit = 11,
};

inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
  FeatureBitset Features;
  if (FB[AVR::FeatureSRAM])
    Features.set(Feature_HasSRAMBit);
  if (FB[AVR::FeatureJMPCALL])
    Features.set(Feature_HasJMPCALLBit);
  if (FB[AVR::FeatureIJMPCALL])
    Features.set(Feature_HasIJMPCALLBit);
  if (FB[AVR::FeatureEIJMPCALL])
    Features.set(Feature_HasEIJMPCALLBit);
  if (FB[AVR::FeatureADDSUBIW])
    Features.set(Feature_HasADDSUBIWBit);
  if (FB[AVR::FeatureSmallStack])
    Features.set(Feature_HasSmallStackBit);
  if (FB[AVR::FeatureMOVW])
    Features.set(Feature_HasMOVWBit);
  if (FB[AVR::FeatureLPM])
    Features.set(Feature_HasLPMBit);
  if (FB[AVR::FeatureLPMX])
    Features.set(Feature_HasLPMXBit);
  if (FB[AVR::FeatureELPM])
    Features.set(Feature_HasELPMBit);
  if (FB[AVR::FeatureELPMX])
    Features.set(Feature_HasELPMXBit);
  if (FB[AVR::FeatureSPM])
    Features.set(Feature_HasSPMBit);
  if (FB[AVR::FeatureSPMX])
    Features.set(Feature_HasSPMXBit);
  if (FB[AVR::FeatureDES])
    Features.set(Feature_HasDESBit);
  if (FB[AVR::FeatureRMW])
    Features.set(Feature_SupportsRMWBit);
  if (FB[AVR::FeatureMultiplication])
    Features.set(Feature_SupportsMultiplicationBit);
  if (FB[AVR::FeatureBREAK])
    Features.set(Feature_HasBREAKBit);
  if (FB[AVR::FeatureTinyEncoding])
    Features.set(Feature_HasTinyEncodingBit);
  if (!FB[AVR::FeatureTinyEncoding])
    Features.set(Feature_HasNonTinyEncodingBit);
  return Features;
}

inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
  enum : uint8_t {
    CEFBS_None,
    CEFBS_HasADDSUBIW,
    CEFBS_HasBREAK,
    CEFBS_HasDES,
    CEFBS_HasEIJMPCALL,
    CEFBS_HasELPM,
    CEFBS_HasELPMX,
    CEFBS_HasIJMPCALL,
    CEFBS_HasJMPCALL,
    CEFBS_HasLPM,
    CEFBS_HasLPMX,
    CEFBS_HasMOVW,
    CEFBS_HasNonTinyEncoding,
    CEFBS_HasSPM,
    CEFBS_HasSPMX,
    CEFBS_HasSRAM,
    CEFBS_HasTinyEncoding,
    CEFBS_SupportsMultiplication,
    CEFBS_SupportsRMW,
    CEFBS_HasSRAM_HasNonTinyEncoding,
    CEFBS_HasSRAM_HasTinyEncoding,
  };

  static constexpr FeatureBitset FeatureBitsets[] = {
    {}, // CEFBS_None
    {Feature_HasADDSUBIWBit, },
    {Feature_HasBREAKBit, },
    {Feature_HasDESBit, },
    {Feature_HasEIJMPCALLBit, },
    {Feature_HasELPMBit, },
    {Feature_HasELPMXBit, },
    {Feature_HasIJMPCALLBit, },
    {Feature_HasJMPCALLBit, },
    {Feature_HasLPMBit, },
    {Feature_HasLPMXBit, },
    {Feature_HasMOVWBit, },
    {Feature_HasNonTinyEncodingBit, },
    {Feature_HasSPMBit, },
    {Feature_HasSPMXBit, },
    {Feature_HasSRAMBit, },
    {Feature_HasTinyEncodingBit, },
    {Feature_SupportsMultiplicationBit, },
    {Feature_SupportsRMWBit, },
    {Feature_HasSRAMBit, Feature_HasNonTinyEncodingBit, },
    {Feature_HasSRAMBit, Feature_HasTinyEncodingBit, },
  };
  static constexpr uint8_t RequiredFeaturesRefs[] = {
    CEFBS_None, // PHI
    CEFBS_None, // INLINEASM
    CEFBS_None, // INLINEASM_BR
    CEFBS_None, // CFI_INSTRUCTION
    CEFBS_None, // EH_LABEL
    CEFBS_None, // GC_LABEL
    CEFBS_None, // ANNOTATION_LABEL
    CEFBS_None, // KILL
    CEFBS_None, // EXTRACT_SUBREG
    CEFBS_None, // INSERT_SUBREG
    CEFBS_None, // IMPLICIT_DEF
    CEFBS_None, // INIT_UNDEF
    CEFBS_None, // SUBREG_TO_REG
    CEFBS_None, // COPY_TO_REGCLASS
    CEFBS_None, // DBG_VALUE
    CEFBS_None, // DBG_VALUE_LIST
    CEFBS_None, // DBG_INSTR_REF
    CEFBS_None, // DBG_PHI
    CEFBS_None, // DBG_LABEL
    CEFBS_None, // REG_SEQUENCE
    CEFBS_None, // COPY
    CEFBS_None, // COPY_LANEMASK
    CEFBS_None, // BUNDLE
    CEFBS_None, // LIFETIME_START
    CEFBS_None, // LIFETIME_END
    CEFBS_None, // PSEUDO_PROBE
    CEFBS_None, // ARITH_FENCE
    CEFBS_None, // STACKMAP
    CEFBS_None, // FENTRY_CALL
    CEFBS_None, // PATCHPOINT
    CEFBS_None, // LOAD_STACK_GUARD
    CEFBS_None, // PREALLOCATED_SETUP
    CEFBS_None, // PREALLOCATED_ARG
    CEFBS_None, // STATEPOINT
    CEFBS_None, // LOCAL_ESCAPE
    CEFBS_None, // FAULTING_OP
    CEFBS_None, // PATCHABLE_OP
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER
    CEFBS_None, // PATCHABLE_RET
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT
    CEFBS_None, // PATCHABLE_TAIL_CALL
    CEFBS_None, // PATCHABLE_EVENT_CALL
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
    CEFBS_None, // ICALL_BRANCH_FUNNEL
    CEFBS_None, // FAKE_USE
    CEFBS_None, // MEMBARRIER
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO
    CEFBS_None, // RELOC_NONE
    CEFBS_None, // CONVERGENCECTRL_ENTRY
    CEFBS_None, // CONVERGENCECTRL_ANCHOR
    CEFBS_None, // CONVERGENCECTRL_LOOP
    CEFBS_None, // CONVERGENCECTRL_GLUE
    CEFBS_None, // G_ASSERT_SEXT
    CEFBS_None, // G_ASSERT_ZEXT
    CEFBS_None, // G_ASSERT_ALIGN
    CEFBS_None, // G_ADD
    CEFBS_None, // G_SUB
    CEFBS_None, // G_MUL
    CEFBS_None, // G_SDIV
    CEFBS_None, // G_UDIV
    CEFBS_None, // G_SREM
    CEFBS_None, // G_UREM
    CEFBS_None, // G_SDIVREM
    CEFBS_None, // G_UDIVREM
    CEFBS_None, // G_AND
    CEFBS_None, // G_OR
    CEFBS_None, // G_XOR
    CEFBS_None, // G_ABDS
    CEFBS_None, // G_ABDU
    CEFBS_None, // G_UAVGFLOOR
    CEFBS_None, // G_UAVGCEIL
    CEFBS_None, // G_SAVGFLOOR
    CEFBS_None, // G_SAVGCEIL
    CEFBS_None, // G_IMPLICIT_DEF
    CEFBS_None, // G_PHI
    CEFBS_None, // G_FRAME_INDEX
    CEFBS_None, // G_GLOBAL_VALUE
    CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
    CEFBS_None, // G_CONSTANT_POOL
    CEFBS_None, // G_EXTRACT
    CEFBS_None, // G_UNMERGE_VALUES
    CEFBS_None, // G_INSERT
    CEFBS_None, // G_MERGE_VALUES
    CEFBS_None, // G_BUILD_VECTOR
    CEFBS_None, // G_BUILD_VECTOR_TRUNC
    CEFBS_None, // G_CONCAT_VECTORS
    CEFBS_None, // G_PTRTOINT
    CEFBS_None, // G_INTTOPTR
    CEFBS_None, // G_BITCAST
    CEFBS_None, // G_FREEZE
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
    CEFBS_None, // G_INTRINSIC_TRUNC
    CEFBS_None, // G_INTRINSIC_ROUND
    CEFBS_None, // G_INTRINSIC_LRINT
    CEFBS_None, // G_INTRINSIC_LLRINT
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN
    CEFBS_None, // G_READCYCLECOUNTER
    CEFBS_None, // G_READSTEADYCOUNTER
    CEFBS_None, // G_LOAD
    CEFBS_None, // G_SEXTLOAD
    CEFBS_None, // G_ZEXTLOAD
    CEFBS_None, // G_INDEXED_LOAD
    CEFBS_None, // G_INDEXED_SEXTLOAD
    CEFBS_None, // G_INDEXED_ZEXTLOAD
    CEFBS_None, // G_STORE
    CEFBS_None, // G_INDEXED_STORE
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
    CEFBS_None, // G_ATOMIC_CMPXCHG
    CEFBS_None, // G_ATOMICRMW_XCHG
    CEFBS_None, // G_ATOMICRMW_ADD
    CEFBS_None, // G_ATOMICRMW_SUB
    CEFBS_None, // G_ATOMICRMW_AND
    CEFBS_None, // G_ATOMICRMW_NAND
    CEFBS_None, // G_ATOMICRMW_OR
    CEFBS_None, // G_ATOMICRMW_XOR
    CEFBS_None, // G_ATOMICRMW_MAX
    CEFBS_None, // G_ATOMICRMW_MIN
    CEFBS_None, // G_ATOMICRMW_UMAX
    CEFBS_None, // G_ATOMICRMW_UMIN
    CEFBS_None, // G_ATOMICRMW_FADD
    CEFBS_None, // G_ATOMICRMW_FSUB
    CEFBS_None, // G_ATOMICRMW_FMAX
    CEFBS_None, // G_ATOMICRMW_FMIN
    CEFBS_None, // G_ATOMICRMW_FMAXIMUM
    CEFBS_None, // G_ATOMICRMW_FMINIMUM
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
    CEFBS_None, // G_ATOMICRMW_USUB_COND
    CEFBS_None, // G_ATOMICRMW_USUB_SAT
    CEFBS_None, // G_FENCE
    CEFBS_None, // G_PREFETCH
    CEFBS_None, // G_BRCOND
    CEFBS_None, // G_BRINDIRECT
    CEFBS_None, // G_INVOKE_REGION_START
    CEFBS_None, // G_INTRINSIC
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
    CEFBS_None, // G_INTRINSIC_CONVERGENT
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
    CEFBS_None, // G_ANYEXT
    CEFBS_None, // G_TRUNC
    CEFBS_None, // G_TRUNC_SSAT_S
    CEFBS_None, // G_TRUNC_SSAT_U
    CEFBS_None, // G_TRUNC_USAT_U
    CEFBS_None, // G_CONSTANT
    CEFBS_None, // G_FCONSTANT
    CEFBS_None, // G_VASTART
    CEFBS_None, // G_VAARG
    CEFBS_None, // G_SEXT
    CEFBS_None, // G_SEXT_INREG
    CEFBS_None, // G_ZEXT
    CEFBS_None, // G_SHL
    CEFBS_None, // G_LSHR
    CEFBS_None, // G_ASHR
    CEFBS_None, // G_FSHL
    CEFBS_None, // G_FSHR
    CEFBS_None, // G_ROTR
    CEFBS_None, // G_ROTL
    CEFBS_None, // G_ICMP
    CEFBS_None, // G_FCMP
    CEFBS_None, // G_SCMP
    CEFBS_None, // G_UCMP
    CEFBS_None, // G_SELECT
    CEFBS_None, // G_UADDO
    CEFBS_None, // G_UADDE
    CEFBS_None, // G_USUBO
    CEFBS_None, // G_USUBE
    CEFBS_None, // G_SADDO
    CEFBS_None, // G_SADDE
    CEFBS_None, // G_SSUBO
    CEFBS_None, // G_SSUBE
    CEFBS_None, // G_UMULO
    CEFBS_None, // G_SMULO
    CEFBS_None, // G_UMULH
    CEFBS_None, // G_SMULH
    CEFBS_None, // G_UADDSAT
    CEFBS_None, // G_SADDSAT
    CEFBS_None, // G_USUBSAT
    CEFBS_None, // G_SSUBSAT
    CEFBS_None, // G_USHLSAT
    CEFBS_None, // G_SSHLSAT
    CEFBS_None, // G_SMULFIX
    CEFBS_None, // G_UMULFIX
    CEFBS_None, // G_SMULFIXSAT
    CEFBS_None, // G_UMULFIXSAT
    CEFBS_None, // G_SDIVFIX
    CEFBS_None, // G_UDIVFIX
    CEFBS_None, // G_SDIVFIXSAT
    CEFBS_None, // G_UDIVFIXSAT
    CEFBS_None, // G_FADD
    CEFBS_None, // G_FSUB
    CEFBS_None, // G_FMUL
    CEFBS_None, // G_FMA
    CEFBS_None, // G_FMAD
    CEFBS_None, // G_FDIV
    CEFBS_None, // G_FREM
    CEFBS_None, // G_FMODF
    CEFBS_None, // G_FPOW
    CEFBS_None, // G_FPOWI
    CEFBS_None, // G_FEXP
    CEFBS_None, // G_FEXP2
    CEFBS_None, // G_FEXP10
    CEFBS_None, // G_FLOG
    CEFBS_None, // G_FLOG2
    CEFBS_None, // G_FLOG10
    CEFBS_None, // G_FLDEXP
    CEFBS_None, // G_FFREXP
    CEFBS_None, // G_FNEG
    CEFBS_None, // G_FPEXT
    CEFBS_None, // G_FPTRUNC
    CEFBS_None, // G_FPTOSI
    CEFBS_None, // G_FPTOUI
    CEFBS_None, // G_SITOFP
    CEFBS_None, // G_UITOFP
    CEFBS_None, // G_FPTOSI_SAT
    CEFBS_None, // G_FPTOUI_SAT
    CEFBS_None, // G_FABS
    CEFBS_None, // G_FCOPYSIGN
    CEFBS_None, // G_IS_FPCLASS
    CEFBS_None, // G_FCANONICALIZE
    CEFBS_None, // G_FMINNUM
    CEFBS_None, // G_FMAXNUM
    CEFBS_None, // G_FMINNUM_IEEE
    CEFBS_None, // G_FMAXNUM_IEEE
    CEFBS_None, // G_FMINIMUM
    CEFBS_None, // G_FMAXIMUM
    CEFBS_None, // G_FMINIMUMNUM
    CEFBS_None, // G_FMAXIMUMNUM
    CEFBS_None, // G_GET_FPENV
    CEFBS_None, // G_SET_FPENV
    CEFBS_None, // G_RESET_FPENV
    CEFBS_None, // G_GET_FPMODE
    CEFBS_None, // G_SET_FPMODE
    CEFBS_None, // G_RESET_FPMODE
    CEFBS_None, // G_GET_ROUNDING
    CEFBS_None, // G_SET_ROUNDING
    CEFBS_None, // G_PTR_ADD
    CEFBS_None, // G_PTRMASK
    CEFBS_None, // G_SMIN
    CEFBS_None, // G_SMAX
    CEFBS_None, // G_UMIN
    CEFBS_None, // G_UMAX
    CEFBS_None, // G_ABS
    CEFBS_None, // G_LROUND
    CEFBS_None, // G_LLROUND
    CEFBS_None, // G_BR
    CEFBS_None, // G_BRJT
    CEFBS_None, // G_VSCALE
    CEFBS_None, // G_INSERT_SUBVECTOR
    CEFBS_None, // G_EXTRACT_SUBVECTOR
    CEFBS_None, // G_INSERT_VECTOR_ELT
    CEFBS_None, // G_EXTRACT_VECTOR_ELT
    CEFBS_None, // G_SHUFFLE_VECTOR
    CEFBS_None, // G_SPLAT_VECTOR
    CEFBS_None, // G_STEP_VECTOR
    CEFBS_None, // G_VECTOR_COMPRESS
    CEFBS_None, // G_CTTZ
    CEFBS_None, // G_CTTZ_ZERO_UNDEF
    CEFBS_None, // G_CTLZ
    CEFBS_None, // G_CTLZ_ZERO_UNDEF
    CEFBS_None, // G_CTPOP
    CEFBS_None, // G_BSWAP
    CEFBS_None, // G_BITREVERSE
    CEFBS_None, // G_FCEIL
    CEFBS_None, // G_FCOS
    CEFBS_None, // G_FSIN
    CEFBS_None, // G_FSINCOS
    CEFBS_None, // G_FTAN
    CEFBS_None, // G_FACOS
    CEFBS_None, // G_FASIN
    CEFBS_None, // G_FATAN
    CEFBS_None, // G_FATAN2
    CEFBS_None, // G_FCOSH
    CEFBS_None, // G_FSINH
    CEFBS_None, // G_FTANH
    CEFBS_None, // G_FSQRT
    CEFBS_None, // G_FFLOOR
    CEFBS_None, // G_FRINT
    CEFBS_None, // G_FNEARBYINT
    CEFBS_None, // G_ADDRSPACE_CAST
    CEFBS_None, // G_BLOCK_ADDR
    CEFBS_None, // G_JUMP_TABLE
    CEFBS_None, // G_DYN_STACKALLOC
    CEFBS_None, // G_STACKSAVE
    CEFBS_None, // G_STACKRESTORE
    CEFBS_None, // G_STRICT_FADD
    CEFBS_None, // G_STRICT_FSUB
    CEFBS_None, // G_STRICT_FMUL
    CEFBS_None, // G_STRICT_FDIV
    CEFBS_None, // G_STRICT_FREM
    CEFBS_None, // G_STRICT_FMA
    CEFBS_None, // G_STRICT_FSQRT
    CEFBS_None, // G_STRICT_FLDEXP
    CEFBS_None, // G_READ_REGISTER
    CEFBS_None, // G_WRITE_REGISTER
    CEFBS_None, // G_MEMCPY
    CEFBS_None, // G_MEMCPY_INLINE
    CEFBS_None, // G_MEMMOVE
    CEFBS_None, // G_MEMSET
    CEFBS_None, // G_BZERO
    CEFBS_None, // G_TRAP
    CEFBS_None, // G_DEBUGTRAP
    CEFBS_None, // G_UBSANTRAP
    CEFBS_None, // G_VECREDUCE_SEQ_FADD
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL
    CEFBS_None, // G_VECREDUCE_FADD
    CEFBS_None, // G_VECREDUCE_FMUL
    CEFBS_None, // G_VECREDUCE_FMAX
    CEFBS_None, // G_VECREDUCE_FMIN
    CEFBS_None, // G_VECREDUCE_FMAXIMUM
    CEFBS_None, // G_VECREDUCE_FMINIMUM
    CEFBS_None, // G_VECREDUCE_ADD
    CEFBS_None, // G_VECREDUCE_MUL
    CEFBS_None, // G_VECREDUCE_AND
    CEFBS_None, // G_VECREDUCE_OR
    CEFBS_None, // G_VECREDUCE_XOR
    CEFBS_None, // G_VECREDUCE_SMAX
    CEFBS_None, // G_VECREDUCE_SMIN
    CEFBS_None, // G_VECREDUCE_UMAX
    CEFBS_None, // G_VECREDUCE_UMIN
    CEFBS_None, // G_SBFX
    CEFBS_None, // G_UBFX
    CEFBS_None, // ADCWRdRr
    CEFBS_None, // ADDWRdRr
    CEFBS_None, // ADJCALLSTACKDOWN
    CEFBS_None, // ADJCALLSTACKUP
    CEFBS_None, // ANDIWRdK
    CEFBS_None, // ANDWRdRr
    CEFBS_None, // ASRBNRd
    CEFBS_None, // ASRWLoRd
    CEFBS_None, // ASRWNRd
    CEFBS_None, // ASRWRd
    CEFBS_None, // Asr16
    CEFBS_None, // Asr32
    CEFBS_None, // Asr8
    CEFBS_None, // AtomicFence
    CEFBS_None, // AtomicLoad16
    CEFBS_None, // AtomicLoad8
    CEFBS_None, // AtomicLoadAdd16
    CEFBS_None, // AtomicLoadAdd8
    CEFBS_None, // AtomicLoadAnd16
    CEFBS_None, // AtomicLoadAnd8
    CEFBS_None, // AtomicLoadOr16
    CEFBS_None, // AtomicLoadOr8
    CEFBS_None, // AtomicLoadSub16
    CEFBS_None, // AtomicLoadSub8
    CEFBS_None, // AtomicLoadXor16
    CEFBS_None, // AtomicLoadXor8
    CEFBS_None, // AtomicStore16
    CEFBS_None, // AtomicStore8
    CEFBS_None, // COMWRd
    CEFBS_None, // CPCWRdRr
    CEFBS_None, // CPWRdRr
    CEFBS_None, // CopyZero
    CEFBS_HasELPM, // ELPMBRdZ
    CEFBS_HasELPMX, // ELPMBRdZPi
    CEFBS_HasELPM, // ELPMWRdZ
    CEFBS_HasELPMX, // ELPMWRdZPi
    CEFBS_None, // EORWRdRr
    CEFBS_None, // FRMIDX
    CEFBS_None, // INWRdA
    CEFBS_HasSRAM, // LDDWRdPtrQ
    CEFBS_HasSRAM, // LDDWRdYQ
    CEFBS_None, // LDIWRdK
    CEFBS_HasSRAM_HasNonTinyEncoding, // LDSWRdK
    CEFBS_HasSRAM, // LDWRdPtr
    CEFBS_HasSRAM, // LDWRdPtrPd
    CEFBS_HasSRAM, // LDWRdPtrPi
    CEFBS_HasLPM, // LPMBRdZ
    CEFBS_HasLPM, // LPMWRdZ
    CEFBS_HasLPMX, // LPMWRdZPi
    CEFBS_None, // LSLBNRd
    CEFBS_None, // LSLWHiRd
    CEFBS_None, // LSLWNRd
    CEFBS_None, // LSLWRd
    CEFBS_None, // LSRBNRd
    CEFBS_None, // LSRWLoRd
    CEFBS_None, // LSRWNRd
    CEFBS_None, // LSRWRd
    CEFBS_None, // Lsl16
    CEFBS_None, // Lsl32
    CEFBS_None, // Lsl8
    CEFBS_None, // Lsr16
    CEFBS_None, // Lsr32
    CEFBS_None, // Lsr8
    CEFBS_None, // NEGWRd
    CEFBS_None, // ORIWRdK
    CEFBS_None, // ORWRdRr
    CEFBS_None, // OUTWARr
    CEFBS_HasSRAM, // POPWRd
    CEFBS_HasSRAM, // PUSHWRr
    CEFBS_HasNonTinyEncoding, // ROLBRdR1
    CEFBS_HasTinyEncoding, // ROLBRdR17
    CEFBS_None, // ROLWRd
    CEFBS_None, // RORBRd
    CEFBS_None, // RORWRd
    CEFBS_None, // Rol16
    CEFBS_None, // Rol8
    CEFBS_None, // Ror16
    CEFBS_None, // Ror8
    CEFBS_None, // SBCIWRdK
    CEFBS_None, // SBCWRdRr
    CEFBS_None, // SEXT
    CEFBS_None, // SPREAD
    CEFBS_None, // SPWRITE
    CEFBS_None, // STDSPQRr
    CEFBS_HasSRAM, // STDWPtrQRr
    CEFBS_None, // STDWSPQRr
    CEFBS_HasSRAM_HasNonTinyEncoding, // STSWKRr
    CEFBS_HasSRAM, // STWPtrPdRr
    CEFBS_HasSRAM, // STWPtrPiRr
    CEFBS_HasSRAM, // STWPtrRr
    CEFBS_None, // SUBIWRdK
    CEFBS_None, // SUBWRdRr
    CEFBS_None, // Select16
    CEFBS_None, // Select8
    CEFBS_None, // ZEXT
    CEFBS_None, // ADCRdRr
    CEFBS_None, // ADDRdRr
    CEFBS_HasADDSUBIW, // ADIWRdK
    CEFBS_None, // ANDIRdK
    CEFBS_None, // ANDRdRr
    CEFBS_None, // ASRRd
    CEFBS_None, // BCLRs
    CEFBS_None, // BLD
    CEFBS_None, // BRBCsk
    CEFBS_None, // BRBSsk
    CEFBS_HasBREAK, // BREAK
    CEFBS_None, // BREQk
    CEFBS_None, // BRGEk
    CEFBS_None, // BRLOk
    CEFBS_None, // BRLTk
    CEFBS_None, // BRMIk
    CEFBS_None, // BRNEk
    CEFBS_None, // BRPLk
    CEFBS_None, // BRSHk
    CEFBS_None, // BSETs
    CEFBS_None, // BST
    CEFBS_HasJMPCALL, // CALLk
    CEFBS_None, // CBIAb
    CEFBS_None, // COMRd
    CEFBS_None, // CPCRdRr
    CEFBS_None, // CPIRdK
    CEFBS_None, // CPRdRr
    CEFBS_None, // CPSE
    CEFBS_None, // DECRd
    CEFBS_HasDES, // DESK
    CEFBS_HasEIJMPCALL, // EICALL
    CEFBS_HasEIJMPCALL, // EIJMP
    CEFBS_HasELPM, // ELPM
    CEFBS_HasELPMX, // ELPMRdZ
    CEFBS_HasELPMX, // ELPMRdZPi
    CEFBS_None, // EORRdRr
    CEFBS_SupportsMultiplication, // FMUL
    CEFBS_SupportsMultiplication, // FMULS
    CEFBS_SupportsMultiplication, // FMULSU
    CEFBS_HasIJMPCALL, // ICALL
    CEFBS_HasIJMPCALL, // IJMP
    CEFBS_None, // INCRd
    CEFBS_None, // INRdA
    CEFBS_HasJMPCALL, // JMPk
    CEFBS_SupportsRMW, // LACZRd
    CEFBS_SupportsRMW, // LASZRd
    CEFBS_SupportsRMW, // LATZRd
    CEFBS_HasSRAM_HasNonTinyEncoding, // LDDRdPtrQ
    CEFBS_None, // LDIRdK
    CEFBS_HasSRAM, // LDRdPtr
    CEFBS_HasSRAM, // LDRdPtrPd
    CEFBS_HasSRAM, // LDRdPtrPi
    CEFBS_HasSRAM_HasNonTinyEncoding, // LDSRdK
    CEFBS_HasSRAM_HasTinyEncoding, // LDSRdKTiny
    CEFBS_HasLPM, // LPM
    CEFBS_HasLPMX, // LPMRdZ
    CEFBS_HasLPMX, // LPMRdZPi
    CEFBS_None, // LSRRd
    CEFBS_None, // MOVRdRr
    CEFBS_HasMOVW, // MOVWRdRr
    CEFBS_SupportsMultiplication, // MULRdRr
    CEFBS_SupportsMultiplication, // MULSRdRr
    CEFBS_SupportsMultiplication, // MULSURdRr
    CEFBS_None, // NEGRd
    CEFBS_None, // NOP
    CEFBS_None, // ORIRdK
    CEFBS_None, // ORRdRr
    CEFBS_None, // OUTARr
    CEFBS_HasSRAM, // POPRd
    CEFBS_HasSRAM, // PUSHRr
    CEFBS_None, // RCALLk
    CEFBS_None, // RET
    CEFBS_None, // RETI
    CEFBS_None, // RJMPk
    CEFBS_None, // RORRd
    CEFBS_None, // SBCIRdK
    CEFBS_None, // SBCRdRr
    CEFBS_None, // SBIAb
    CEFBS_None, // SBICAb
    CEFBS_None, // SBISAb
    CEFBS_HasADDSUBIW, // SBIWRdK
    CEFBS_None, // SBRCRrB
    CEFBS_None, // SBRSRrB
    CEFBS_None, // SLEEP
    CEFBS_HasSPM, // SPM
    CEFBS_HasSPMX, // SPMZPi
    CEFBS_HasSRAM_HasNonTinyEncoding, // STDPtrQRr
    CEFBS_HasSRAM, // STPtrPdRr
    CEFBS_HasSRAM, // STPtrPiRr
    CEFBS_HasSRAM, // STPtrRr
    CEFBS_HasSRAM_HasNonTinyEncoding, // STSKRr
    CEFBS_HasSRAM_HasTinyEncoding, // STSKRrTiny
    CEFBS_None, // SUBIRdK
    CEFBS_None, // SUBRdRr
    CEFBS_None, // SWAPRd
    CEFBS_None, // WDR
    CEFBS_SupportsRMW, // XCHZRd
  };

  assert(Opcode < 514);
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
}


} // namespace llvm::AVR_MC

#endif // GET_COMPUTE_FEATURES

#ifdef GET_AVAILABLE_OPCODE_CHECKER
#undef GET_AVAILABLE_OPCODE_CHECKER

namespace llvm::AVR_MC {

bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  return !MissingFeatures.any();
}

} // namespace llvm::AVR_MC

#endif // GET_AVAILABLE_OPCODE_CHECKER

#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER

#include <sstream>

namespace llvm::AVR_MC {

#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
  "Feature_HasADDSUBIW",
  "Feature_HasBREAK",
  "Feature_HasDES",
  "Feature_HasEIJMPCALL",
  "Feature_HasELPM",
  "Feature_HasELPMX",
  "Feature_HasIJMPCALL",
  "Feature_HasJMPCALL",
  "Feature_HasLPM",
  "Feature_HasLPMX",
  "Feature_HasMOVW",
  "Feature_HasNonTinyEncoding",
  "Feature_HasSPM",
  "Feature_HasSPMX",
  "Feature_HasSRAM",
  "Feature_HasSmallStack",
  "Feature_HasTinyEncoding",
  "Feature_SupportsMultiplication",
  "Feature_SupportsRMW",
  nullptr
};

#endif // NDEBUG

void verifyInstructionPredicates(
    unsigned Opcode, const FeatureBitset &Features) {
#ifndef NDEBUG
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  if (MissingFeatures.any()) {
    std::ostringstream Msg;
    Msg << "Attempting to emit " << &AVRInstrNameData[AVRInstrNameIndices[Opcode]]
        << " instruction but the ";
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
      if (MissingFeatures.test(i))
        Msg << SubtargetFeatureNames[i] << " ";
    Msg << "predicate(s) are not met";
    report_fatal_error(Msg.str().c_str());
  }
#endif // NDEBUG
}

} // namespace llvm::AVR_MC

#endif // ENABLE_INSTR_PREDICATE_VERIFIER

