/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Register Information Header Fragment                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#include "llvm/CodeGen/TargetRegisterInfo.h"

namespace llvm {

class HexagonFrameLowering;

struct HexagonGenRegisterInfo : public TargetRegisterInfo {
  explicit HexagonGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
      unsigned PC = 0, unsigned HwMode = 0);
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
  unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const override;
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
  const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
  unsigned getRegUnitWeight(MCRegUnit RegUnit) const override;
  unsigned getNumRegPressureSets() const override;
  const char *getRegPressureSetName(unsigned Idx) const override;
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
  const int *getRegUnitPressureSets(MCRegUnit RegUnit) const override;
  ArrayRef<const char *> getRegMaskNames() const override;
  ArrayRef<const uint32_t *> getRegMasks() const override;
  bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
  bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
  bool isFixedRegister(const MachineFunction &, MCRegister) const override;
  bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
  bool isConstantPhysReg(MCRegister PhysReg) const override final;
  /// Devirtualized TargetFrameLowering.
  static const HexagonFrameLowering *getFrameLowering(
      const MachineFunction &MF);
};

namespace Hexagon { // Register classes
  extern const TargetRegisterClass UsrBitsRegClass;
  extern const TargetRegisterClass SysRegsRegClass;
  extern const TargetRegisterClass GuestRegsRegClass;
  extern const TargetRegisterClass IntRegsRegClass;
  extern const TargetRegisterClass CtrRegsRegClass;
  extern const TargetRegisterClass GeneralSubRegsRegClass;
  extern const TargetRegisterClass V62RegsRegClass;
  extern const TargetRegisterClass IntRegsLow8RegClass;
  extern const TargetRegisterClass CtrRegs_and_V62RegsRegClass;
  extern const TargetRegisterClass PredRegsRegClass;
  extern const TargetRegisterClass V62Regs_with_isub_hiRegClass;
  extern const TargetRegisterClass ModRegsRegClass;
  extern const TargetRegisterClass CtrRegs_with_subreg_overflowRegClass;
  extern const TargetRegisterClass V65RegsRegClass;
  extern const TargetRegisterClass SysRegs64RegClass;
  extern const TargetRegisterClass DoubleRegsRegClass;
  extern const TargetRegisterClass GuestRegs64RegClass;
  extern const TargetRegisterClass VectRegRevRegClass;
  extern const TargetRegisterClass CtrRegs64RegClass;
  extern const TargetRegisterClass GeneralDoubleLow8RegsRegClass;
  extern const TargetRegisterClass DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass;
  extern const TargetRegisterClass CtrRegs64_and_V62RegsRegClass;
  extern const TargetRegisterClass CtrRegs64_with_isub_hi_in_ModRegsRegClass;
  extern const TargetRegisterClass HvxQRRegClass;
  extern const TargetRegisterClass HvxVRRegClass;
  extern const TargetRegisterClass HvxVR_and_V65RegsRegClass;
  extern const TargetRegisterClass HvxWRRegClass;
  extern const TargetRegisterClass HvxWR_and_VectRegRevRegClass;
  extern const TargetRegisterClass HvxVQRRegClass;
} // end namespace Hexagon

} // end namespace llvm

