/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Machine Code Emitter                                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

void AMDGPUMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
    SmallVectorImpl<MCFixup> &Fixups,
    APInt &Inst,
    APInt &Scratch,
    const MCSubtargetInfo &STI) const {
  static const uint64_t InstBits[] = {
    UINT64_C(3771252736), UINT64_C(0),	// BUFFER_ATOMIC_ADD_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3771236352), UINT64_C(0),	// BUFFER_ATOMIC_ADD_ADDR64_gfx6_gfx7
    UINT64_C(3771232256), UINT64_C(0),	// BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx10
    UINT64_C(54043199300452352), UINT64_C(0),	// BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx11
    UINT64_C(3771232256), UINT64_C(0),	// BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3775426560), UINT64_C(0),	// BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx90a
    UINT64_C(3775426560), UINT64_C(0),	// BUFFER_ATOMIC_ADD_BOTHEN_RTN_vi
    UINT64_C(3771215872), UINT64_C(0),	// BUFFER_ATOMIC_ADD_BOTHEN_gfx10
    UINT64_C(54043199300435968), UINT64_C(0),	// BUFFER_ATOMIC_ADD_BOTHEN_gfx11
    UINT64_C(3771215872), UINT64_C(0),	// BUFFER_ATOMIC_ADD_BOTHEN_gfx6_gfx7
    UINT64_C(3775410176), UINT64_C(0),	// BUFFER_ATOMIC_ADD_BOTHEN_gfx90a
    UINT64_C(3775410176), UINT64_C(0),	// BUFFER_ATOMIC_ADD_BOTHEN_vi
    UINT64_C(54043199309103104), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_BOTHEN_RTN_gfx11
    UINT64_C(3778310144), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_BOTHEN_RTN_gfx90a
    UINT64_C(3778310144), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_BOTHEN_RTN_gfx940
    UINT64_C(3778310144), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_BOTHEN_RTN_vi
    UINT64_C(54043199309086720), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_BOTHEN_gfx11
    UINT64_C(3778293760), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_BOTHEN_gfx90a
    UINT64_C(3778293760), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_BOTHEN_gfx940
    UINT64_C(3778293760), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_BOTHEN_vi
    UINT64_C(36028800799621120), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_IDXEN_RTN_gfx11
    UINT64_C(3778306048), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_IDXEN_RTN_gfx90a
    UINT64_C(3778306048), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_IDXEN_RTN_gfx940
    UINT64_C(3778306048), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_IDXEN_RTN_vi
    UINT64_C(36028800799604736), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_IDXEN_gfx11
    UINT64_C(3778289664), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_IDXEN_gfx90a
    UINT64_C(3778289664), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_IDXEN_gfx940
    UINT64_C(3778289664), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_IDXEN_vi
    UINT64_C(18014402290139136), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_OFFEN_RTN_gfx11
    UINT64_C(3778301952), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_OFFEN_RTN_gfx90a
    UINT64_C(3778301952), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_OFFEN_RTN_gfx940
    UINT64_C(3778301952), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_OFFEN_RTN_vi
    UINT64_C(18014402290122752), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_OFFEN_gfx11
    UINT64_C(3778285568), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_OFFEN_gfx90a
    UINT64_C(3778285568), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_OFFEN_gfx940
    UINT64_C(3778285568), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_OFFEN_vi
    UINT64_C(3780657152), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_OFFSET_RTN_gfx11
    UINT64_C(3778297856), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_OFFSET_RTN_gfx90a
    UINT64_C(3778297856), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_OFFSET_RTN_gfx940
    UINT64_C(3778297856), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_OFFSET_RTN_vi
    UINT64_C(3780640768), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_OFFSET_gfx11
    UINT64_C(3778281472), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_OFFSET_gfx90a
    UINT64_C(3778281472), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_OFFSET_gfx940
    UINT64_C(3778281472), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_OFFSET_vi
    UINT64_C(13875590455218241536), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658199277568), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590871040), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571907072), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790853632), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771889664), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163483136), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144519168), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363465728), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344501760), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818736095232), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021717131264), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399936077824), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602917113856), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308707328), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFSET_gfx12
    UINT64_C(3289743360), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3778834432), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_BOTHEN_RTN_gfx90a
    UINT64_C(3778834432), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_BOTHEN_RTN_gfx940
    UINT64_C(3778834432), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_BOTHEN_RTN_vi
    UINT64_C(3778818048), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_BOTHEN_gfx90a
    UINT64_C(3778818048), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_BOTHEN_gfx940
    UINT64_C(3778818048), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_BOTHEN_vi
    UINT64_C(3778830336), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_IDXEN_RTN_gfx90a
    UINT64_C(3778830336), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_IDXEN_RTN_gfx940
    UINT64_C(3778830336), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_IDXEN_RTN_vi
    UINT64_C(3778813952), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_IDXEN_gfx90a
    UINT64_C(3778813952), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_IDXEN_gfx940
    UINT64_C(3778813952), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_IDXEN_vi
    UINT64_C(3778826240), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_OFFEN_RTN_gfx90a
    UINT64_C(3778826240), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_OFFEN_RTN_gfx940
    UINT64_C(3778826240), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_OFFEN_RTN_vi
    UINT64_C(3778809856), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_OFFEN_gfx90a
    UINT64_C(3778809856), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_OFFEN_gfx940
    UINT64_C(3778809856), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_OFFEN_vi
    UINT64_C(3778822144), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_OFFSET_RTN_gfx90a
    UINT64_C(3778822144), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_OFFSET_RTN_gfx940
    UINT64_C(3778822144), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_OFFSET_RTN_vi
    UINT64_C(3778805760), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_OFFSET_gfx90a
    UINT64_C(3778805760), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_OFFSET_gfx940
    UINT64_C(3778805760), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_OFFSET_vi
    UINT64_C(13875590455218225152), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658199261184), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590854656), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571890688), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790837248), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771873280), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163466752), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144502784), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363449344), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344485376), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818736078848), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021717114880), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399936061440), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602917097472), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308690944), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFSET_gfx12
    UINT64_C(3289726976), UINT64_C(0),	// BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3771228160), UINT64_C(0),	// BUFFER_ATOMIC_ADD_IDXEN_RTN_gfx10
    UINT64_C(36028800790970368), UINT64_C(0),	// BUFFER_ATOMIC_ADD_IDXEN_RTN_gfx11
    UINT64_C(3771228160), UINT64_C(0),	// BUFFER_ATOMIC_ADD_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3775422464), UINT64_C(0),	// BUFFER_ATOMIC_ADD_IDXEN_RTN_gfx90a
    UINT64_C(3775422464), UINT64_C(0),	// BUFFER_ATOMIC_ADD_IDXEN_RTN_vi
    UINT64_C(3771211776), UINT64_C(0),	// BUFFER_ATOMIC_ADD_IDXEN_gfx10
    UINT64_C(36028800790953984), UINT64_C(0),	// BUFFER_ATOMIC_ADD_IDXEN_gfx11
    UINT64_C(3771211776), UINT64_C(0),	// BUFFER_ATOMIC_ADD_IDXEN_gfx6_gfx7
    UINT64_C(3775406080), UINT64_C(0),	// BUFFER_ATOMIC_ADD_IDXEN_gfx90a
    UINT64_C(3775406080), UINT64_C(0),	// BUFFER_ATOMIC_ADD_IDXEN_vi
    UINT64_C(3771224064), UINT64_C(0),	// BUFFER_ATOMIC_ADD_OFFEN_RTN_gfx10
    UINT64_C(18014402281488384), UINT64_C(0),	// BUFFER_ATOMIC_ADD_OFFEN_RTN_gfx11
    UINT64_C(3771224064), UINT64_C(0),	// BUFFER_ATOMIC_ADD_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3775418368), UINT64_C(0),	// BUFFER_ATOMIC_ADD_OFFEN_RTN_gfx90a
    UINT64_C(3775418368), UINT64_C(0),	// BUFFER_ATOMIC_ADD_OFFEN_RTN_vi
    UINT64_C(3771207680), UINT64_C(0),	// BUFFER_ATOMIC_ADD_OFFEN_gfx10
    UINT64_C(18014402281472000), UINT64_C(0),	// BUFFER_ATOMIC_ADD_OFFEN_gfx11
    UINT64_C(3771207680), UINT64_C(0),	// BUFFER_ATOMIC_ADD_OFFEN_gfx6_gfx7
    UINT64_C(3775401984), UINT64_C(0),	// BUFFER_ATOMIC_ADD_OFFEN_gfx90a
    UINT64_C(3775401984), UINT64_C(0),	// BUFFER_ATOMIC_ADD_OFFEN_vi
    UINT64_C(3771219968), UINT64_C(0),	// BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx10
    UINT64_C(3772006400), UINT64_C(0),	// BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx11
    UINT64_C(3771219968), UINT64_C(0),	// BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3775414272), UINT64_C(0),	// BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx90a
    UINT64_C(3775414272), UINT64_C(0),	// BUFFER_ATOMIC_ADD_OFFSET_RTN_vi
    UINT64_C(3771203584), UINT64_C(0),	// BUFFER_ATOMIC_ADD_OFFSET_gfx10
    UINT64_C(3771990016), UINT64_C(0),	// BUFFER_ATOMIC_ADD_OFFSET_gfx11
    UINT64_C(3771203584), UINT64_C(0),	// BUFFER_ATOMIC_ADD_OFFSET_gfx6_gfx7
    UINT64_C(3775397888), UINT64_C(0),	// BUFFER_ATOMIC_ADD_OFFSET_gfx90a
    UINT64_C(3775397888), UINT64_C(0),	// BUFFER_ATOMIC_ADD_OFFSET_vi
    UINT64_C(13875590455217700864), UINT64_C(0),	// BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658198736896), UINT64_C(0),	// BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590330368), UINT64_C(0),	// BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571366400), UINT64_C(0),	// BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790312960), UINT64_C(0),	// BUFFER_ATOMIC_ADD_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771348992), UINT64_C(0),	// BUFFER_ATOMIC_ADD_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837162942464), UINT64_C(0),	// BUFFER_ATOMIC_ADD_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143978496), UINT64_C(0),	// BUFFER_ATOMIC_ADD_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418362925056), UINT64_C(0),	// BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621343961088), UINT64_C(0),	// BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735554560), UINT64_C(0),	// BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716590592), UINT64_C(0),	// BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935537152), UINT64_C(0),	// BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916573184), UINT64_C(0),	// BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308166656), UINT64_C(0),	// BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_gfx12
    UINT64_C(3289202688), UINT64_C(0),	// BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3779641344), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3779624960), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_ADDR64_gfx6_gfx7
    UINT64_C(3779620864), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx10
    UINT64_C(54043199304122368), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx11
    UINT64_C(3779620864), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3783815168), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx90a
    UINT64_C(3783815168), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_vi
    UINT64_C(3779604480), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_BOTHEN_gfx10
    UINT64_C(54043199304105984), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_BOTHEN_gfx11
    UINT64_C(3779604480), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_BOTHEN_gfx6_gfx7
    UINT64_C(3783798784), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_BOTHEN_gfx90a
    UINT64_C(3783798784), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_BOTHEN_vi
    UINT64_C(3779616768), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_gfx10
    UINT64_C(36028800794640384), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_gfx11
    UINT64_C(3779616768), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3783811072), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_gfx90a
    UINT64_C(3783811072), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_vi
    UINT64_C(3779600384), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_IDXEN_gfx10
    UINT64_C(36028800794624000), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_IDXEN_gfx11
    UINT64_C(3779600384), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_IDXEN_gfx6_gfx7
    UINT64_C(3783794688), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_IDXEN_gfx90a
    UINT64_C(3783794688), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_IDXEN_vi
    UINT64_C(3779612672), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_gfx10
    UINT64_C(18014402285158400), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_gfx11
    UINT64_C(3779612672), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3783806976), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_gfx90a
    UINT64_C(3783806976), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_vi
    UINT64_C(3779596288), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_OFFEN_gfx10
    UINT64_C(18014402285142016), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_OFFEN_gfx11
    UINT64_C(3779596288), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_OFFEN_gfx6_gfx7
    UINT64_C(3783790592), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_OFFEN_gfx90a
    UINT64_C(3783790592), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_OFFEN_vi
    UINT64_C(3779608576), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_gfx10
    UINT64_C(3775676416), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_gfx11
    UINT64_C(3779608576), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3783802880), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_gfx90a
    UINT64_C(3783802880), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_vi
    UINT64_C(3779592192), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_OFFSET_gfx10
    UINT64_C(3775660032), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_OFFSET_gfx11
    UINT64_C(3779592192), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_OFFSET_gfx6_gfx7
    UINT64_C(3783786496), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_OFFSET_gfx90a
    UINT64_C(3783786496), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_OFFSET_vi
    UINT64_C(13875590455217930240), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658198966272), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590559744), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571595776), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790542336), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771578368), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163171840), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144207872), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363154432), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344190464), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735783936), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716819968), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935766528), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916802560), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308396032), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_gfx12
    UINT64_C(3289432064), UINT64_C(0),	// BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3773087744), UINT64_C(0),	// BUFFER_ATOMIC_AND_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3773071360), UINT64_C(0),	// BUFFER_ATOMIC_AND_ADDR64_gfx6_gfx7
    UINT64_C(3773067264), UINT64_C(0),	// BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx10
    UINT64_C(54043199302287360), UINT64_C(0),	// BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx11
    UINT64_C(3773067264), UINT64_C(0),	// BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3776999424), UINT64_C(0),	// BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx90a
    UINT64_C(3776999424), UINT64_C(0),	// BUFFER_ATOMIC_AND_BOTHEN_RTN_vi
    UINT64_C(3773050880), UINT64_C(0),	// BUFFER_ATOMIC_AND_BOTHEN_gfx10
    UINT64_C(54043199302270976), UINT64_C(0),	// BUFFER_ATOMIC_AND_BOTHEN_gfx11
    UINT64_C(3773050880), UINT64_C(0),	// BUFFER_ATOMIC_AND_BOTHEN_gfx6_gfx7
    UINT64_C(3776983040), UINT64_C(0),	// BUFFER_ATOMIC_AND_BOTHEN_gfx90a
    UINT64_C(3776983040), UINT64_C(0),	// BUFFER_ATOMIC_AND_BOTHEN_vi
    UINT64_C(3773063168), UINT64_C(0),	// BUFFER_ATOMIC_AND_IDXEN_RTN_gfx10
    UINT64_C(36028800792805376), UINT64_C(0),	// BUFFER_ATOMIC_AND_IDXEN_RTN_gfx11
    UINT64_C(3773063168), UINT64_C(0),	// BUFFER_ATOMIC_AND_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3776995328), UINT64_C(0),	// BUFFER_ATOMIC_AND_IDXEN_RTN_gfx90a
    UINT64_C(3776995328), UINT64_C(0),	// BUFFER_ATOMIC_AND_IDXEN_RTN_vi
    UINT64_C(3773046784), UINT64_C(0),	// BUFFER_ATOMIC_AND_IDXEN_gfx10
    UINT64_C(36028800792788992), UINT64_C(0),	// BUFFER_ATOMIC_AND_IDXEN_gfx11
    UINT64_C(3773046784), UINT64_C(0),	// BUFFER_ATOMIC_AND_IDXEN_gfx6_gfx7
    UINT64_C(3776978944), UINT64_C(0),	// BUFFER_ATOMIC_AND_IDXEN_gfx90a
    UINT64_C(3776978944), UINT64_C(0),	// BUFFER_ATOMIC_AND_IDXEN_vi
    UINT64_C(3773059072), UINT64_C(0),	// BUFFER_ATOMIC_AND_OFFEN_RTN_gfx10
    UINT64_C(18014402283323392), UINT64_C(0),	// BUFFER_ATOMIC_AND_OFFEN_RTN_gfx11
    UINT64_C(3773059072), UINT64_C(0),	// BUFFER_ATOMIC_AND_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3776991232), UINT64_C(0),	// BUFFER_ATOMIC_AND_OFFEN_RTN_gfx90a
    UINT64_C(3776991232), UINT64_C(0),	// BUFFER_ATOMIC_AND_OFFEN_RTN_vi
    UINT64_C(3773042688), UINT64_C(0),	// BUFFER_ATOMIC_AND_OFFEN_gfx10
    UINT64_C(18014402283307008), UINT64_C(0),	// BUFFER_ATOMIC_AND_OFFEN_gfx11
    UINT64_C(3773042688), UINT64_C(0),	// BUFFER_ATOMIC_AND_OFFEN_gfx6_gfx7
    UINT64_C(3776974848), UINT64_C(0),	// BUFFER_ATOMIC_AND_OFFEN_gfx90a
    UINT64_C(3776974848), UINT64_C(0),	// BUFFER_ATOMIC_AND_OFFEN_vi
    UINT64_C(3773054976), UINT64_C(0),	// BUFFER_ATOMIC_AND_OFFSET_RTN_gfx10
    UINT64_C(3773841408), UINT64_C(0),	// BUFFER_ATOMIC_AND_OFFSET_RTN_gfx11
    UINT64_C(3773054976), UINT64_C(0),	// BUFFER_ATOMIC_AND_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3776987136), UINT64_C(0),	// BUFFER_ATOMIC_AND_OFFSET_RTN_gfx90a
    UINT64_C(3776987136), UINT64_C(0),	// BUFFER_ATOMIC_AND_OFFSET_RTN_vi
    UINT64_C(3773038592), UINT64_C(0),	// BUFFER_ATOMIC_AND_OFFSET_gfx10
    UINT64_C(3773825024), UINT64_C(0),	// BUFFER_ATOMIC_AND_OFFSET_gfx11
    UINT64_C(3773038592), UINT64_C(0),	// BUFFER_ATOMIC_AND_OFFSET_gfx6_gfx7
    UINT64_C(3776970752), UINT64_C(0),	// BUFFER_ATOMIC_AND_OFFSET_gfx90a
    UINT64_C(3776970752), UINT64_C(0),	// BUFFER_ATOMIC_AND_OFFSET_vi
    UINT64_C(13875590455217815552), UINT64_C(0),	// BUFFER_ATOMIC_AND_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658198851584), UINT64_C(0),	// BUFFER_ATOMIC_AND_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590445056), UINT64_C(0),	// BUFFER_ATOMIC_AND_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571481088), UINT64_C(0),	// BUFFER_ATOMIC_AND_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790427648), UINT64_C(0),	// BUFFER_ATOMIC_AND_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771463680), UINT64_C(0),	// BUFFER_ATOMIC_AND_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163057152), UINT64_C(0),	// BUFFER_ATOMIC_AND_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144093184), UINT64_C(0),	// BUFFER_ATOMIC_AND_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363039744), UINT64_C(0),	// BUFFER_ATOMIC_AND_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344075776), UINT64_C(0),	// BUFFER_ATOMIC_AND_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735669248), UINT64_C(0),	// BUFFER_ATOMIC_AND_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716705280), UINT64_C(0),	// BUFFER_ATOMIC_AND_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935651840), UINT64_C(0),	// BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916687872), UINT64_C(0),	// BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308281344), UINT64_C(0),	// BUFFER_ATOMIC_AND_VBUFFER_OFFSET_gfx12
    UINT64_C(3289317376), UINT64_C(0),	// BUFFER_ATOMIC_AND_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3781476352), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3781459968), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_ADDR64_gfx6_gfx7
    UINT64_C(3781455872), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx10
    UINT64_C(54043199305695232), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx11
    UINT64_C(3781455872), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3785388032), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx90a
    UINT64_C(3785388032), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_vi
    UINT64_C(3781439488), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_BOTHEN_gfx10
    UINT64_C(54043199305678848), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_BOTHEN_gfx11
    UINT64_C(3781439488), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_BOTHEN_gfx6_gfx7
    UINT64_C(3785371648), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_BOTHEN_gfx90a
    UINT64_C(3785371648), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_BOTHEN_vi
    UINT64_C(3781451776), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_IDXEN_RTN_gfx10
    UINT64_C(36028800796213248), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_IDXEN_RTN_gfx11
    UINT64_C(3781451776), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3785383936), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_IDXEN_RTN_gfx90a
    UINT64_C(3785383936), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_IDXEN_RTN_vi
    UINT64_C(3781435392), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_IDXEN_gfx10
    UINT64_C(36028800796196864), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_IDXEN_gfx11
    UINT64_C(3781435392), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_IDXEN_gfx6_gfx7
    UINT64_C(3785367552), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_IDXEN_gfx90a
    UINT64_C(3785367552), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_IDXEN_vi
    UINT64_C(3781447680), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_OFFEN_RTN_gfx10
    UINT64_C(18014402286731264), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_OFFEN_RTN_gfx11
    UINT64_C(3781447680), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3785379840), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_OFFEN_RTN_gfx90a
    UINT64_C(3785379840), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_OFFEN_RTN_vi
    UINT64_C(3781431296), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_OFFEN_gfx10
    UINT64_C(18014402286714880), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_OFFEN_gfx11
    UINT64_C(3781431296), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_OFFEN_gfx6_gfx7
    UINT64_C(3785363456), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_OFFEN_gfx90a
    UINT64_C(3785363456), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_OFFEN_vi
    UINT64_C(3781443584), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_OFFSET_RTN_gfx10
    UINT64_C(3777249280), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_OFFSET_RTN_gfx11
    UINT64_C(3781443584), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3785375744), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_OFFSET_RTN_gfx90a
    UINT64_C(3785375744), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_OFFSET_RTN_vi
    UINT64_C(3781427200), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_OFFSET_gfx10
    UINT64_C(3777232896), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_OFFSET_gfx11
    UINT64_C(3781427200), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_OFFSET_gfx6_gfx7
    UINT64_C(3785359360), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_OFFSET_gfx90a
    UINT64_C(3785359360), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_OFFSET_vi
    UINT64_C(13875590455218028544), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658199064576), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590658048), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571694080), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790640640), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771676672), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163270144), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144306176), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363252736), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344288768), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735882240), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716918272), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935864832), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916900864), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308494336), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_gfx12
    UINT64_C(3289530368), UINT64_C(0),	// BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3770990592), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3770974208), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_ADDR64_gfx6_gfx7
    UINT64_C(3770970112), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx10
    UINT64_C(54043199300190208), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx11
    UINT64_C(3770970112), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3775164416), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx90a
    UINT64_C(3775164416), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_vi
    UINT64_C(3770953728), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_BOTHEN_gfx10
    UINT64_C(54043199300173824), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_BOTHEN_gfx11
    UINT64_C(3770953728), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_BOTHEN_gfx6_gfx7
    UINT64_C(3775148032), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_BOTHEN_gfx90a
    UINT64_C(3775148032), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_BOTHEN_vi
    UINT64_C(3770966016), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_gfx10
    UINT64_C(36028800790708224), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_gfx11
    UINT64_C(3770966016), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3775160320), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_gfx90a
    UINT64_C(3775160320), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_vi
    UINT64_C(3770949632), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_IDXEN_gfx10
    UINT64_C(36028800790691840), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_IDXEN_gfx11
    UINT64_C(3770949632), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_IDXEN_gfx6_gfx7
    UINT64_C(3775143936), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_IDXEN_gfx90a
    UINT64_C(3775143936), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_IDXEN_vi
    UINT64_C(3770961920), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_gfx10
    UINT64_C(18014402281226240), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_gfx11
    UINT64_C(3770961920), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3775156224), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_gfx90a
    UINT64_C(3775156224), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_vi
    UINT64_C(3770945536), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_OFFEN_gfx10
    UINT64_C(18014402281209856), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_OFFEN_gfx11
    UINT64_C(3770945536), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_OFFEN_gfx6_gfx7
    UINT64_C(3775139840), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_OFFEN_gfx90a
    UINT64_C(3775139840), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_OFFEN_vi
    UINT64_C(3770957824), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_gfx10
    UINT64_C(3771744256), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_gfx11
    UINT64_C(3770957824), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3775152128), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_gfx90a
    UINT64_C(3775152128), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_vi
    UINT64_C(3770941440), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_OFFSET_gfx10
    UINT64_C(3771727872), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_OFFSET_gfx11
    UINT64_C(3770941440), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_OFFSET_gfx6_gfx7
    UINT64_C(3775135744), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_OFFSET_gfx90a
    UINT64_C(3775135744), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_OFFSET_vi
    UINT64_C(13875590455217684480), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658198720512), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590313984), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571350016), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790296576), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771332608), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837162926080), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143962112), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418362908672), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621343944704), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735538176), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716574208), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935520768), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916556800), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308150272), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET_gfx12
    UINT64_C(3289186304), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3779379200), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3779362816), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_gfx6_gfx7
    UINT64_C(3779358720), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_gfx10
    UINT64_C(54043199303860224), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_gfx11
    UINT64_C(3779358720), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3783553024), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_gfx90a
    UINT64_C(3783553024), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_vi
    UINT64_C(3779342336), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_gfx10
    UINT64_C(54043199303843840), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_gfx11
    UINT64_C(3779342336), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_gfx6_gfx7
    UINT64_C(3783536640), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_gfx90a
    UINT64_C(3783536640), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_vi
    UINT64_C(3779354624), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_gfx10
    UINT64_C(36028800794378240), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_gfx11
    UINT64_C(3779354624), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3783548928), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_gfx90a
    UINT64_C(3783548928), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_vi
    UINT64_C(3779338240), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_gfx10
    UINT64_C(36028800794361856), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_gfx11
    UINT64_C(3779338240), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_gfx6_gfx7
    UINT64_C(3783532544), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_gfx90a
    UINT64_C(3783532544), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_vi
    UINT64_C(3779350528), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_gfx10
    UINT64_C(18014402284896256), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_gfx11
    UINT64_C(3779350528), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3783544832), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_gfx90a
    UINT64_C(3783544832), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_vi
    UINT64_C(3779334144), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_gfx10
    UINT64_C(18014402284879872), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_gfx11
    UINT64_C(3779334144), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_gfx6_gfx7
    UINT64_C(3783528448), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_gfx90a
    UINT64_C(3783528448), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_vi
    UINT64_C(3779346432), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_gfx10
    UINT64_C(3775414272), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_gfx11
    UINT64_C(3779346432), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3783540736), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_gfx90a
    UINT64_C(3783540736), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_vi
    UINT64_C(3779330048), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_gfx10
    UINT64_C(3775397888), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_gfx11
    UINT64_C(3779330048), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_gfx6_gfx7
    UINT64_C(3783524352), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_gfx90a
    UINT64_C(3783524352), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_vi
    UINT64_C(13875590455217913856), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658198949888), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590543360), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571579392), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790525952), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771561984), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163155456), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144191488), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363138048), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344174080), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735767552), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716803584), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935750144), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916786176), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308379648), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET_gfx12
    UINT64_C(3289415680), UINT64_C(0),	// BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13875590455218143232), UINT64_C(0),	// BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658199179264), UINT64_C(0),	// BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590772736), UINT64_C(0),	// BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571808768), UINT64_C(0),	// BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790755328), UINT64_C(0),	// BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771791360), UINT64_C(0),	// BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163384832), UINT64_C(0),	// BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144420864), UINT64_C(0),	// BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363367424), UINT64_C(0),	// BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344403456), UINT64_C(0),	// BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735996928), UINT64_C(0),	// BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021717032960), UINT64_C(0),	// BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935979520), UINT64_C(0),	// BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602917015552), UINT64_C(0),	// BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308609024), UINT64_C(0),	// BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFSET_gfx12
    UINT64_C(3289645056), UINT64_C(0),	// BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3771756544), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_BOTHEN_RTN_gfx10
    UINT64_C(54043199300976640), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_BOTHEN_RTN_gfx11
    UINT64_C(3771740160), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_BOTHEN_gfx10
    UINT64_C(54043199300960256), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_BOTHEN_gfx11
    UINT64_C(3771752448), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_IDXEN_RTN_gfx10
    UINT64_C(36028800791494656), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_IDXEN_RTN_gfx11
    UINT64_C(3771736064), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_IDXEN_gfx10
    UINT64_C(36028800791478272), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_IDXEN_gfx11
    UINT64_C(3771748352), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_OFFEN_RTN_gfx10
    UINT64_C(18014402282012672), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_OFFEN_RTN_gfx11
    UINT64_C(3771731968), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_OFFEN_gfx10
    UINT64_C(18014402281996288), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_OFFEN_gfx11
    UINT64_C(3771744256), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_OFFSET_RTN_gfx10
    UINT64_C(3772530688), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_OFFSET_RTN_gfx11
    UINT64_C(3771727872), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_OFFSET_gfx10
    UINT64_C(3772514304), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_OFFSET_gfx11
    UINT64_C(13875590455217733632), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658198769664), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590363136), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571399168), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790345728), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771381760), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837162975232), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144011264), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418362957824), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621343993856), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735587328), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716623360), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935569920), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916605952), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308199424), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_VBUFFER_OFFSET_gfx12
    UINT64_C(3289235456), UINT64_C(0),	// BUFFER_ATOMIC_CSUB_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3774136320), UINT64_C(0),	// BUFFER_ATOMIC_DEC_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3774119936), UINT64_C(0),	// BUFFER_ATOMIC_DEC_ADDR64_gfx6_gfx7
    UINT64_C(3774115840), UINT64_C(0),	// BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx10
    UINT64_C(54043199303335936), UINT64_C(0),	// BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx11
    UINT64_C(3774115840), UINT64_C(0),	// BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3778048000), UINT64_C(0),	// BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx90a
    UINT64_C(3778048000), UINT64_C(0),	// BUFFER_ATOMIC_DEC_BOTHEN_RTN_vi
    UINT64_C(3774099456), UINT64_C(0),	// BUFFER_ATOMIC_DEC_BOTHEN_gfx10
    UINT64_C(54043199303319552), UINT64_C(0),	// BUFFER_ATOMIC_DEC_BOTHEN_gfx11
    UINT64_C(3774099456), UINT64_C(0),	// BUFFER_ATOMIC_DEC_BOTHEN_gfx6_gfx7
    UINT64_C(3778031616), UINT64_C(0),	// BUFFER_ATOMIC_DEC_BOTHEN_gfx90a
    UINT64_C(3778031616), UINT64_C(0),	// BUFFER_ATOMIC_DEC_BOTHEN_vi
    UINT64_C(3774111744), UINT64_C(0),	// BUFFER_ATOMIC_DEC_IDXEN_RTN_gfx10
    UINT64_C(36028800793853952), UINT64_C(0),	// BUFFER_ATOMIC_DEC_IDXEN_RTN_gfx11
    UINT64_C(3774111744), UINT64_C(0),	// BUFFER_ATOMIC_DEC_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3778043904), UINT64_C(0),	// BUFFER_ATOMIC_DEC_IDXEN_RTN_gfx90a
    UINT64_C(3778043904), UINT64_C(0),	// BUFFER_ATOMIC_DEC_IDXEN_RTN_vi
    UINT64_C(3774095360), UINT64_C(0),	// BUFFER_ATOMIC_DEC_IDXEN_gfx10
    UINT64_C(36028800793837568), UINT64_C(0),	// BUFFER_ATOMIC_DEC_IDXEN_gfx11
    UINT64_C(3774095360), UINT64_C(0),	// BUFFER_ATOMIC_DEC_IDXEN_gfx6_gfx7
    UINT64_C(3778027520), UINT64_C(0),	// BUFFER_ATOMIC_DEC_IDXEN_gfx90a
    UINT64_C(3778027520), UINT64_C(0),	// BUFFER_ATOMIC_DEC_IDXEN_vi
    UINT64_C(3774107648), UINT64_C(0),	// BUFFER_ATOMIC_DEC_OFFEN_RTN_gfx10
    UINT64_C(18014402284371968), UINT64_C(0),	// BUFFER_ATOMIC_DEC_OFFEN_RTN_gfx11
    UINT64_C(3774107648), UINT64_C(0),	// BUFFER_ATOMIC_DEC_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3778039808), UINT64_C(0),	// BUFFER_ATOMIC_DEC_OFFEN_RTN_gfx90a
    UINT64_C(3778039808), UINT64_C(0),	// BUFFER_ATOMIC_DEC_OFFEN_RTN_vi
    UINT64_C(3774091264), UINT64_C(0),	// BUFFER_ATOMIC_DEC_OFFEN_gfx10
    UINT64_C(18014402284355584), UINT64_C(0),	// BUFFER_ATOMIC_DEC_OFFEN_gfx11
    UINT64_C(3774091264), UINT64_C(0),	// BUFFER_ATOMIC_DEC_OFFEN_gfx6_gfx7
    UINT64_C(3778023424), UINT64_C(0),	// BUFFER_ATOMIC_DEC_OFFEN_gfx90a
    UINT64_C(3778023424), UINT64_C(0),	// BUFFER_ATOMIC_DEC_OFFEN_vi
    UINT64_C(3774103552), UINT64_C(0),	// BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx10
    UINT64_C(3774889984), UINT64_C(0),	// BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx11
    UINT64_C(3774103552), UINT64_C(0),	// BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3778035712), UINT64_C(0),	// BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx90a
    UINT64_C(3778035712), UINT64_C(0),	// BUFFER_ATOMIC_DEC_OFFSET_RTN_vi
    UINT64_C(3774087168), UINT64_C(0),	// BUFFER_ATOMIC_DEC_OFFSET_gfx10
    UINT64_C(3774873600), UINT64_C(0),	// BUFFER_ATOMIC_DEC_OFFSET_gfx11
    UINT64_C(3774087168), UINT64_C(0),	// BUFFER_ATOMIC_DEC_OFFSET_gfx6_gfx7
    UINT64_C(3778019328), UINT64_C(0),	// BUFFER_ATOMIC_DEC_OFFSET_gfx90a
    UINT64_C(3778019328), UINT64_C(0),	// BUFFER_ATOMIC_DEC_OFFSET_vi
    UINT64_C(13875590455217881088), UINT64_C(0),	// BUFFER_ATOMIC_DEC_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658198917120), UINT64_C(0),	// BUFFER_ATOMIC_DEC_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590510592), UINT64_C(0),	// BUFFER_ATOMIC_DEC_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571546624), UINT64_C(0),	// BUFFER_ATOMIC_DEC_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790493184), UINT64_C(0),	// BUFFER_ATOMIC_DEC_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771529216), UINT64_C(0),	// BUFFER_ATOMIC_DEC_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163122688), UINT64_C(0),	// BUFFER_ATOMIC_DEC_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144158720), UINT64_C(0),	// BUFFER_ATOMIC_DEC_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363105280), UINT64_C(0),	// BUFFER_ATOMIC_DEC_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344141312), UINT64_C(0),	// BUFFER_ATOMIC_DEC_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735734784), UINT64_C(0),	// BUFFER_ATOMIC_DEC_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716770816), UINT64_C(0),	// BUFFER_ATOMIC_DEC_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935717376), UINT64_C(0),	// BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916753408), UINT64_C(0),	// BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308346880), UINT64_C(0),	// BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_gfx12
    UINT64_C(3289382912), UINT64_C(0),	// BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3782524928), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3782508544), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_ADDR64_gfx6_gfx7
    UINT64_C(3782504448), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx10
    UINT64_C(54043199306743808), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx11
    UINT64_C(3782504448), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3786436608), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx90a
    UINT64_C(3786436608), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_vi
    UINT64_C(3782488064), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_BOTHEN_gfx10
    UINT64_C(54043199306727424), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_BOTHEN_gfx11
    UINT64_C(3782488064), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_BOTHEN_gfx6_gfx7
    UINT64_C(3786420224), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_BOTHEN_gfx90a
    UINT64_C(3786420224), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_BOTHEN_vi
    UINT64_C(3782500352), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_gfx10
    UINT64_C(36028800797261824), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_gfx11
    UINT64_C(3782500352), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3786432512), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_gfx90a
    UINT64_C(3786432512), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_vi
    UINT64_C(3782483968), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_IDXEN_gfx10
    UINT64_C(36028800797245440), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_IDXEN_gfx11
    UINT64_C(3782483968), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_IDXEN_gfx6_gfx7
    UINT64_C(3786416128), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_IDXEN_gfx90a
    UINT64_C(3786416128), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_IDXEN_vi
    UINT64_C(3782496256), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_gfx10
    UINT64_C(18014402287779840), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_gfx11
    UINT64_C(3782496256), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3786428416), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_gfx90a
    UINT64_C(3786428416), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_vi
    UINT64_C(3782479872), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_OFFEN_gfx10
    UINT64_C(18014402287763456), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_OFFEN_gfx11
    UINT64_C(3782479872), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_OFFEN_gfx6_gfx7
    UINT64_C(3786412032), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_OFFEN_gfx90a
    UINT64_C(3786412032), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_OFFEN_vi
    UINT64_C(3782492160), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_gfx10
    UINT64_C(3778297856), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_gfx11
    UINT64_C(3782492160), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3786424320), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_gfx90a
    UINT64_C(3786424320), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_vi
    UINT64_C(3782475776), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_OFFSET_gfx10
    UINT64_C(3778281472), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_OFFSET_gfx11
    UINT64_C(3782475776), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_OFFSET_gfx6_gfx7
    UINT64_C(3786407936), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_OFFSET_gfx90a
    UINT64_C(3786407936), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_OFFSET_vi
    UINT64_C(13875590455218094080), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658199130112), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590723584), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571759616), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790706176), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771742208), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163335680), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144371712), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363318272), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344354304), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735947776), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716983808), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935930368), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916966400), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308559872), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_gfx12
    UINT64_C(3289595904), UINT64_C(0),	// BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3774398464), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3774382080), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_ADDR64_gfx6_gfx7
    UINT64_C(3774377984), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN_gfx10
    UINT64_C(54043199307530240), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN_gfx11
    UINT64_C(3774377984), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3774361600), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_BOTHEN_gfx10
    UINT64_C(54043199307513856), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_BOTHEN_gfx11
    UINT64_C(3774361600), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_BOTHEN_gfx6_gfx7
    UINT64_C(3774373888), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_IDXEN_RTN_gfx10
    UINT64_C(36028800798048256), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_IDXEN_RTN_gfx11
    UINT64_C(3774373888), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3774357504), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_IDXEN_gfx10
    UINT64_C(36028800798031872), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_IDXEN_gfx11
    UINT64_C(3774357504), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_IDXEN_gfx6_gfx7
    UINT64_C(3774369792), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_OFFEN_RTN_gfx10
    UINT64_C(18014402288566272), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_OFFEN_RTN_gfx11
    UINT64_C(3774369792), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3774353408), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_OFFEN_gfx10
    UINT64_C(18014402288549888), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_OFFEN_gfx11
    UINT64_C(3774353408), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_OFFEN_gfx6_gfx7
    UINT64_C(3774365696), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_OFFSET_RTN_gfx10
    UINT64_C(3779084288), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_OFFSET_RTN_gfx11
    UINT64_C(3774365696), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3774349312), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_OFFSET_gfx10
    UINT64_C(3779067904), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_OFFSET_gfx11
    UINT64_C(3774349312), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_OFFSET_gfx6_gfx7
    UINT64_C(3782787072), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_X2_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3782770688), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_X2_ADDR64_gfx6_gfx7
    UINT64_C(3782766592), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_RTN_gfx10
    UINT64_C(3782766592), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3782750208), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_gfx10
    UINT64_C(3782750208), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_gfx6_gfx7
    UINT64_C(3782762496), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_RTN_gfx10
    UINT64_C(3782762496), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3782746112), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_gfx10
    UINT64_C(3782746112), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_gfx6_gfx7
    UINT64_C(3782758400), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_RTN_gfx10
    UINT64_C(3782758400), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3782742016), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_gfx10
    UINT64_C(3782742016), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_gfx6_gfx7
    UINT64_C(3782754304), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_RTN_gfx10
    UINT64_C(3782754304), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3782737920), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_gfx10
    UINT64_C(3782737920), UINT64_C(0),	// BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_gfx6_gfx7
    UINT64_C(3774922752), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3774906368), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_ADDR64_gfx6_gfx7
    UINT64_C(3774902272), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_BOTHEN_RTN_gfx10
    UINT64_C(54043199308054528), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_BOTHEN_RTN_gfx11
    UINT64_C(3774902272), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3774885888), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_BOTHEN_gfx10
    UINT64_C(54043199308038144), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_BOTHEN_gfx11
    UINT64_C(3774885888), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_BOTHEN_gfx6_gfx7
    UINT64_C(3774898176), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_IDXEN_RTN_gfx10
    UINT64_C(36028800798572544), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_IDXEN_RTN_gfx11
    UINT64_C(3774898176), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3774881792), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_IDXEN_gfx10
    UINT64_C(36028800798556160), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_IDXEN_gfx11
    UINT64_C(3774881792), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_IDXEN_gfx6_gfx7
    UINT64_C(3774894080), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_OFFEN_RTN_gfx10
    UINT64_C(18014402289090560), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_OFFEN_RTN_gfx11
    UINT64_C(3774894080), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3774877696), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_OFFEN_gfx10
    UINT64_C(18014402289074176), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_OFFEN_gfx11
    UINT64_C(3774877696), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_OFFEN_gfx6_gfx7
    UINT64_C(3774889984), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_OFFSET_RTN_gfx10
    UINT64_C(3779608576), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_OFFSET_RTN_gfx11
    UINT64_C(3774889984), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3774873600), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_OFFSET_gfx10
    UINT64_C(3779592192), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_OFFSET_gfx11
    UINT64_C(3774873600), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_OFFSET_gfx6_gfx7
    UINT64_C(13875590455218176000), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658199212032), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590805504), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571841536), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790788096), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771824128), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163417600), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144453632), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363400192), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344436224), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818736029696), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021717065728), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399936012288), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602917048320), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308641792), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_gfx12
    UINT64_C(3289677824), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3783311360), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_X2_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3783294976), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_X2_ADDR64_gfx6_gfx7
    UINT64_C(3783290880), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_X2_BOTHEN_RTN_gfx10
    UINT64_C(3783290880), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_X2_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3783274496), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_X2_BOTHEN_gfx10
    UINT64_C(3783274496), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_X2_BOTHEN_gfx6_gfx7
    UINT64_C(3783286784), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_X2_IDXEN_RTN_gfx10
    UINT64_C(3783286784), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_X2_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3783270400), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_X2_IDXEN_gfx10
    UINT64_C(3783270400), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_X2_IDXEN_gfx6_gfx7
    UINT64_C(3783282688), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_X2_OFFEN_RTN_gfx10
    UINT64_C(3783282688), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_X2_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3783266304), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_X2_OFFEN_gfx10
    UINT64_C(3783266304), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_X2_OFFEN_gfx6_gfx7
    UINT64_C(3783278592), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_X2_OFFSET_RTN_gfx10
    UINT64_C(3783278592), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_X2_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3783262208), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_X2_OFFSET_gfx10
    UINT64_C(3783262208), UINT64_C(0),	// BUFFER_ATOMIC_FMAX_X2_OFFSET_gfx6_gfx7
    UINT64_C(3774660608), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3774644224), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_ADDR64_gfx6_gfx7
    UINT64_C(3774640128), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_BOTHEN_RTN_gfx10
    UINT64_C(54043199307792384), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_BOTHEN_RTN_gfx11
    UINT64_C(3774640128), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3774623744), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_BOTHEN_gfx10
    UINT64_C(54043199307776000), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_BOTHEN_gfx11
    UINT64_C(3774623744), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_BOTHEN_gfx6_gfx7
    UINT64_C(3774636032), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_IDXEN_RTN_gfx10
    UINT64_C(36028800798310400), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_IDXEN_RTN_gfx11
    UINT64_C(3774636032), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3774619648), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_IDXEN_gfx10
    UINT64_C(36028800798294016), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_IDXEN_gfx11
    UINT64_C(3774619648), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_IDXEN_gfx6_gfx7
    UINT64_C(3774631936), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_OFFEN_RTN_gfx10
    UINT64_C(18014402288828416), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_OFFEN_RTN_gfx11
    UINT64_C(3774631936), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3774615552), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_OFFEN_gfx10
    UINT64_C(18014402288812032), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_OFFEN_gfx11
    UINT64_C(3774615552), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_OFFEN_gfx6_gfx7
    UINT64_C(3774627840), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_OFFSET_RTN_gfx10
    UINT64_C(3779346432), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_OFFSET_RTN_gfx11
    UINT64_C(3774627840), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3774611456), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_OFFSET_gfx10
    UINT64_C(3779330048), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_OFFSET_gfx11
    UINT64_C(3774611456), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_OFFSET_gfx6_gfx7
    UINT64_C(13875590455218159616), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658199195648), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590789120), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571825152), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790771712), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771807744), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163401216), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144437248), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363383808), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344419840), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818736013312), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021717049344), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935995904), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602917031936), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308625408), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_gfx12
    UINT64_C(3289661440), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3783049216), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_X2_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3783032832), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_X2_ADDR64_gfx6_gfx7
    UINT64_C(3783028736), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_X2_BOTHEN_RTN_gfx10
    UINT64_C(3783028736), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_X2_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3783012352), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_X2_BOTHEN_gfx10
    UINT64_C(3783012352), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_X2_BOTHEN_gfx6_gfx7
    UINT64_C(3783024640), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_X2_IDXEN_RTN_gfx10
    UINT64_C(3783024640), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_X2_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3783008256), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_X2_IDXEN_gfx10
    UINT64_C(3783008256), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_X2_IDXEN_gfx6_gfx7
    UINT64_C(3783020544), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_X2_OFFEN_RTN_gfx10
    UINT64_C(3783020544), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_X2_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3783004160), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_X2_OFFEN_gfx10
    UINT64_C(3783004160), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_X2_OFFEN_gfx6_gfx7
    UINT64_C(3783016448), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_X2_OFFSET_RTN_gfx10
    UINT64_C(3783016448), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_X2_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3783000064), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_X2_OFFSET_gfx10
    UINT64_C(3783000064), UINT64_C(0),	// BUFFER_ATOMIC_FMIN_X2_OFFSET_gfx6_gfx7
    UINT64_C(3773874176), UINT64_C(0),	// BUFFER_ATOMIC_INC_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3773857792), UINT64_C(0),	// BUFFER_ATOMIC_INC_ADDR64_gfx6_gfx7
    UINT64_C(3773853696), UINT64_C(0),	// BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx10
    UINT64_C(54043199303073792), UINT64_C(0),	// BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx11
    UINT64_C(3773853696), UINT64_C(0),	// BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3777785856), UINT64_C(0),	// BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx90a
    UINT64_C(3777785856), UINT64_C(0),	// BUFFER_ATOMIC_INC_BOTHEN_RTN_vi
    UINT64_C(3773837312), UINT64_C(0),	// BUFFER_ATOMIC_INC_BOTHEN_gfx10
    UINT64_C(54043199303057408), UINT64_C(0),	// BUFFER_ATOMIC_INC_BOTHEN_gfx11
    UINT64_C(3773837312), UINT64_C(0),	// BUFFER_ATOMIC_INC_BOTHEN_gfx6_gfx7
    UINT64_C(3777769472), UINT64_C(0),	// BUFFER_ATOMIC_INC_BOTHEN_gfx90a
    UINT64_C(3777769472), UINT64_C(0),	// BUFFER_ATOMIC_INC_BOTHEN_vi
    UINT64_C(3773849600), UINT64_C(0),	// BUFFER_ATOMIC_INC_IDXEN_RTN_gfx10
    UINT64_C(36028800793591808), UINT64_C(0),	// BUFFER_ATOMIC_INC_IDXEN_RTN_gfx11
    UINT64_C(3773849600), UINT64_C(0),	// BUFFER_ATOMIC_INC_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3777781760), UINT64_C(0),	// BUFFER_ATOMIC_INC_IDXEN_RTN_gfx90a
    UINT64_C(3777781760), UINT64_C(0),	// BUFFER_ATOMIC_INC_IDXEN_RTN_vi
    UINT64_C(3773833216), UINT64_C(0),	// BUFFER_ATOMIC_INC_IDXEN_gfx10
    UINT64_C(36028800793575424), UINT64_C(0),	// BUFFER_ATOMIC_INC_IDXEN_gfx11
    UINT64_C(3773833216), UINT64_C(0),	// BUFFER_ATOMIC_INC_IDXEN_gfx6_gfx7
    UINT64_C(3777765376), UINT64_C(0),	// BUFFER_ATOMIC_INC_IDXEN_gfx90a
    UINT64_C(3777765376), UINT64_C(0),	// BUFFER_ATOMIC_INC_IDXEN_vi
    UINT64_C(3773845504), UINT64_C(0),	// BUFFER_ATOMIC_INC_OFFEN_RTN_gfx10
    UINT64_C(18014402284109824), UINT64_C(0),	// BUFFER_ATOMIC_INC_OFFEN_RTN_gfx11
    UINT64_C(3773845504), UINT64_C(0),	// BUFFER_ATOMIC_INC_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3777777664), UINT64_C(0),	// BUFFER_ATOMIC_INC_OFFEN_RTN_gfx90a
    UINT64_C(3777777664), UINT64_C(0),	// BUFFER_ATOMIC_INC_OFFEN_RTN_vi
    UINT64_C(3773829120), UINT64_C(0),	// BUFFER_ATOMIC_INC_OFFEN_gfx10
    UINT64_C(18014402284093440), UINT64_C(0),	// BUFFER_ATOMIC_INC_OFFEN_gfx11
    UINT64_C(3773829120), UINT64_C(0),	// BUFFER_ATOMIC_INC_OFFEN_gfx6_gfx7
    UINT64_C(3777761280), UINT64_C(0),	// BUFFER_ATOMIC_INC_OFFEN_gfx90a
    UINT64_C(3777761280), UINT64_C(0),	// BUFFER_ATOMIC_INC_OFFEN_vi
    UINT64_C(3773841408), UINT64_C(0),	// BUFFER_ATOMIC_INC_OFFSET_RTN_gfx10
    UINT64_C(3774627840), UINT64_C(0),	// BUFFER_ATOMIC_INC_OFFSET_RTN_gfx11
    UINT64_C(3773841408), UINT64_C(0),	// BUFFER_ATOMIC_INC_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3777773568), UINT64_C(0),	// BUFFER_ATOMIC_INC_OFFSET_RTN_gfx90a
    UINT64_C(3777773568), UINT64_C(0),	// BUFFER_ATOMIC_INC_OFFSET_RTN_vi
    UINT64_C(3773825024), UINT64_C(0),	// BUFFER_ATOMIC_INC_OFFSET_gfx10
    UINT64_C(3774611456), UINT64_C(0),	// BUFFER_ATOMIC_INC_OFFSET_gfx11
    UINT64_C(3773825024), UINT64_C(0),	// BUFFER_ATOMIC_INC_OFFSET_gfx6_gfx7
    UINT64_C(3777757184), UINT64_C(0),	// BUFFER_ATOMIC_INC_OFFSET_gfx90a
    UINT64_C(3777757184), UINT64_C(0),	// BUFFER_ATOMIC_INC_OFFSET_vi
    UINT64_C(13875590455217864704), UINT64_C(0),	// BUFFER_ATOMIC_INC_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658198900736), UINT64_C(0),	// BUFFER_ATOMIC_INC_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590494208), UINT64_C(0),	// BUFFER_ATOMIC_INC_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571530240), UINT64_C(0),	// BUFFER_ATOMIC_INC_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790476800), UINT64_C(0),	// BUFFER_ATOMIC_INC_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771512832), UINT64_C(0),	// BUFFER_ATOMIC_INC_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163106304), UINT64_C(0),	// BUFFER_ATOMIC_INC_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144142336), UINT64_C(0),	// BUFFER_ATOMIC_INC_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363088896), UINT64_C(0),	// BUFFER_ATOMIC_INC_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344124928), UINT64_C(0),	// BUFFER_ATOMIC_INC_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735718400), UINT64_C(0),	// BUFFER_ATOMIC_INC_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716754432), UINT64_C(0),	// BUFFER_ATOMIC_INC_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935700992), UINT64_C(0),	// BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916737024), UINT64_C(0),	// BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308330496), UINT64_C(0),	// BUFFER_ATOMIC_INC_VBUFFER_OFFSET_gfx12
    UINT64_C(3289366528), UINT64_C(0),	// BUFFER_ATOMIC_INC_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3782262784), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3782246400), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_ADDR64_gfx6_gfx7
    UINT64_C(3782242304), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx10
    UINT64_C(54043199306481664), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx11
    UINT64_C(3782242304), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3786174464), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx90a
    UINT64_C(3786174464), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_vi
    UINT64_C(3782225920), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_BOTHEN_gfx10
    UINT64_C(54043199306465280), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_BOTHEN_gfx11
    UINT64_C(3782225920), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_BOTHEN_gfx6_gfx7
    UINT64_C(3786158080), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_BOTHEN_gfx90a
    UINT64_C(3786158080), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_BOTHEN_vi
    UINT64_C(3782238208), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_IDXEN_RTN_gfx10
    UINT64_C(36028800796999680), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_IDXEN_RTN_gfx11
    UINT64_C(3782238208), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3786170368), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_IDXEN_RTN_gfx90a
    UINT64_C(3786170368), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_IDXEN_RTN_vi
    UINT64_C(3782221824), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_IDXEN_gfx10
    UINT64_C(36028800796983296), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_IDXEN_gfx11
    UINT64_C(3782221824), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_IDXEN_gfx6_gfx7
    UINT64_C(3786153984), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_IDXEN_gfx90a
    UINT64_C(3786153984), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_IDXEN_vi
    UINT64_C(3782234112), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_OFFEN_RTN_gfx10
    UINT64_C(18014402287517696), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_OFFEN_RTN_gfx11
    UINT64_C(3782234112), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3786166272), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_OFFEN_RTN_gfx90a
    UINT64_C(3786166272), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_OFFEN_RTN_vi
    UINT64_C(3782217728), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_OFFEN_gfx10
    UINT64_C(18014402287501312), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_OFFEN_gfx11
    UINT64_C(3782217728), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_OFFEN_gfx6_gfx7
    UINT64_C(3786149888), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_OFFEN_gfx90a
    UINT64_C(3786149888), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_OFFEN_vi
    UINT64_C(3782230016), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_OFFSET_RTN_gfx10
    UINT64_C(3778035712), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_OFFSET_RTN_gfx11
    UINT64_C(3782230016), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3786162176), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_OFFSET_RTN_gfx90a
    UINT64_C(3786162176), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_OFFSET_RTN_vi
    UINT64_C(3782213632), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_OFFSET_gfx10
    UINT64_C(3778019328), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_OFFSET_gfx11
    UINT64_C(3782213632), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_OFFSET_gfx6_gfx7
    UINT64_C(3786145792), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_OFFSET_gfx90a
    UINT64_C(3786145792), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_OFFSET_vi
    UINT64_C(13875590455218077696), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658199113728), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590707200), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571743232), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790689792), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771725824), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163319296), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144355328), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363301888), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344337920), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735931392), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716967424), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935913984), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916950016), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308543488), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_gfx12
    UINT64_C(3289579520), UINT64_C(0),	// BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3779358720), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_BOTHEN_RTN_gfx90a
    UINT64_C(3779358720), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_BOTHEN_RTN_gfx940
    UINT64_C(3779358720), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_BOTHEN_RTN_vi
    UINT64_C(3779342336), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_BOTHEN_gfx90a
    UINT64_C(3779342336), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_BOTHEN_gfx940
    UINT64_C(3779342336), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_BOTHEN_vi
    UINT64_C(3779354624), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_IDXEN_RTN_gfx90a
    UINT64_C(3779354624), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_IDXEN_RTN_gfx940
    UINT64_C(3779354624), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_IDXEN_RTN_vi
    UINT64_C(3779338240), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_IDXEN_gfx90a
    UINT64_C(3779338240), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_IDXEN_gfx940
    UINT64_C(3779338240), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_IDXEN_vi
    UINT64_C(3779350528), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_OFFEN_RTN_gfx90a
    UINT64_C(3779350528), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_OFFEN_RTN_gfx940
    UINT64_C(3779350528), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_OFFEN_RTN_vi
    UINT64_C(3779334144), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_OFFEN_gfx90a
    UINT64_C(3779334144), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_OFFEN_gfx940
    UINT64_C(3779334144), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_OFFEN_vi
    UINT64_C(3779346432), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_OFFSET_RTN_gfx90a
    UINT64_C(3779346432), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_OFFSET_RTN_gfx940
    UINT64_C(3779346432), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_OFFSET_RTN_vi
    UINT64_C(3779330048), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_OFFSET_gfx90a
    UINT64_C(3779330048), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_OFFSET_gfx940
    UINT64_C(3779330048), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_OFFSET_vi
    UINT64_C(13875590455218339840), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658199375872), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590969344), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058572005376), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790951936), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771987968), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163581440), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144617472), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363564032), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344600064), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818736193536), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021717229568), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399936176128), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602917212160), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308805632), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_gfx12
    UINT64_C(3289841664), UINT64_C(0),	// BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3779096576), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_BOTHEN_RTN_gfx90a
    UINT64_C(3779096576), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_BOTHEN_RTN_gfx940
    UINT64_C(3779096576), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_BOTHEN_RTN_vi
    UINT64_C(3779080192), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_BOTHEN_gfx90a
    UINT64_C(3779080192), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_BOTHEN_gfx940
    UINT64_C(3779080192), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_BOTHEN_vi
    UINT64_C(3779092480), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_IDXEN_RTN_gfx90a
    UINT64_C(3779092480), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_IDXEN_RTN_gfx940
    UINT64_C(3779092480), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_IDXEN_RTN_vi
    UINT64_C(3779076096), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_IDXEN_gfx90a
    UINT64_C(3779076096), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_IDXEN_gfx940
    UINT64_C(3779076096), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_IDXEN_vi
    UINT64_C(3779088384), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_OFFEN_RTN_gfx90a
    UINT64_C(3779088384), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_OFFEN_RTN_gfx940
    UINT64_C(3779088384), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_OFFEN_RTN_vi
    UINT64_C(3779072000), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_OFFEN_gfx90a
    UINT64_C(3779072000), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_OFFEN_gfx940
    UINT64_C(3779072000), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_OFFEN_vi
    UINT64_C(3779084288), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_OFFSET_RTN_gfx90a
    UINT64_C(3779084288), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_OFFSET_RTN_gfx940
    UINT64_C(3779084288), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_OFFSET_RTN_vi
    UINT64_C(3779067904), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_OFFSET_gfx90a
    UINT64_C(3779067904), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_OFFSET_gfx940
    UINT64_C(3779067904), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_OFFSET_vi
    UINT64_C(13875590455218323456), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658199359488), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590952960), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571988992), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790935552), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771971584), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163565056), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144601088), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363547648), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344583680), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818736177152), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021717213184), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399936159744), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602917195776), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308789248), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_gfx12
    UINT64_C(3289825280), UINT64_C(0),	// BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3773349888), UINT64_C(0),	// BUFFER_ATOMIC_OR_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3773333504), UINT64_C(0),	// BUFFER_ATOMIC_OR_ADDR64_gfx6_gfx7
    UINT64_C(3773329408), UINT64_C(0),	// BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx10
    UINT64_C(54043199302549504), UINT64_C(0),	// BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx11
    UINT64_C(3773329408), UINT64_C(0),	// BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3777261568), UINT64_C(0),	// BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx90a
    UINT64_C(3777261568), UINT64_C(0),	// BUFFER_ATOMIC_OR_BOTHEN_RTN_vi
    UINT64_C(3773313024), UINT64_C(0),	// BUFFER_ATOMIC_OR_BOTHEN_gfx10
    UINT64_C(54043199302533120), UINT64_C(0),	// BUFFER_ATOMIC_OR_BOTHEN_gfx11
    UINT64_C(3773313024), UINT64_C(0),	// BUFFER_ATOMIC_OR_BOTHEN_gfx6_gfx7
    UINT64_C(3777245184), UINT64_C(0),	// BUFFER_ATOMIC_OR_BOTHEN_gfx90a
    UINT64_C(3777245184), UINT64_C(0),	// BUFFER_ATOMIC_OR_BOTHEN_vi
    UINT64_C(3773325312), UINT64_C(0),	// BUFFER_ATOMIC_OR_IDXEN_RTN_gfx10
    UINT64_C(36028800793067520), UINT64_C(0),	// BUFFER_ATOMIC_OR_IDXEN_RTN_gfx11
    UINT64_C(3773325312), UINT64_C(0),	// BUFFER_ATOMIC_OR_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3777257472), UINT64_C(0),	// BUFFER_ATOMIC_OR_IDXEN_RTN_gfx90a
    UINT64_C(3777257472), UINT64_C(0),	// BUFFER_ATOMIC_OR_IDXEN_RTN_vi
    UINT64_C(3773308928), UINT64_C(0),	// BUFFER_ATOMIC_OR_IDXEN_gfx10
    UINT64_C(36028800793051136), UINT64_C(0),	// BUFFER_ATOMIC_OR_IDXEN_gfx11
    UINT64_C(3773308928), UINT64_C(0),	// BUFFER_ATOMIC_OR_IDXEN_gfx6_gfx7
    UINT64_C(3777241088), UINT64_C(0),	// BUFFER_ATOMIC_OR_IDXEN_gfx90a
    UINT64_C(3777241088), UINT64_C(0),	// BUFFER_ATOMIC_OR_IDXEN_vi
    UINT64_C(3773321216), UINT64_C(0),	// BUFFER_ATOMIC_OR_OFFEN_RTN_gfx10
    UINT64_C(18014402283585536), UINT64_C(0),	// BUFFER_ATOMIC_OR_OFFEN_RTN_gfx11
    UINT64_C(3773321216), UINT64_C(0),	// BUFFER_ATOMIC_OR_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3777253376), UINT64_C(0),	// BUFFER_ATOMIC_OR_OFFEN_RTN_gfx90a
    UINT64_C(3777253376), UINT64_C(0),	// BUFFER_ATOMIC_OR_OFFEN_RTN_vi
    UINT64_C(3773304832), UINT64_C(0),	// BUFFER_ATOMIC_OR_OFFEN_gfx10
    UINT64_C(18014402283569152), UINT64_C(0),	// BUFFER_ATOMIC_OR_OFFEN_gfx11
    UINT64_C(3773304832), UINT64_C(0),	// BUFFER_ATOMIC_OR_OFFEN_gfx6_gfx7
    UINT64_C(3777236992), UINT64_C(0),	// BUFFER_ATOMIC_OR_OFFEN_gfx90a
    UINT64_C(3777236992), UINT64_C(0),	// BUFFER_ATOMIC_OR_OFFEN_vi
    UINT64_C(3773317120), UINT64_C(0),	// BUFFER_ATOMIC_OR_OFFSET_RTN_gfx10
    UINT64_C(3774103552), UINT64_C(0),	// BUFFER_ATOMIC_OR_OFFSET_RTN_gfx11
    UINT64_C(3773317120), UINT64_C(0),	// BUFFER_ATOMIC_OR_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3777249280), UINT64_C(0),	// BUFFER_ATOMIC_OR_OFFSET_RTN_gfx90a
    UINT64_C(3777249280), UINT64_C(0),	// BUFFER_ATOMIC_OR_OFFSET_RTN_vi
    UINT64_C(3773300736), UINT64_C(0),	// BUFFER_ATOMIC_OR_OFFSET_gfx10
    UINT64_C(3774087168), UINT64_C(0),	// BUFFER_ATOMIC_OR_OFFSET_gfx11
    UINT64_C(3773300736), UINT64_C(0),	// BUFFER_ATOMIC_OR_OFFSET_gfx6_gfx7
    UINT64_C(3777232896), UINT64_C(0),	// BUFFER_ATOMIC_OR_OFFSET_gfx90a
    UINT64_C(3777232896), UINT64_C(0),	// BUFFER_ATOMIC_OR_OFFSET_vi
    UINT64_C(13875590455217831936), UINT64_C(0),	// BUFFER_ATOMIC_OR_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658198867968), UINT64_C(0),	// BUFFER_ATOMIC_OR_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590461440), UINT64_C(0),	// BUFFER_ATOMIC_OR_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571497472), UINT64_C(0),	// BUFFER_ATOMIC_OR_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790444032), UINT64_C(0),	// BUFFER_ATOMIC_OR_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771480064), UINT64_C(0),	// BUFFER_ATOMIC_OR_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163073536), UINT64_C(0),	// BUFFER_ATOMIC_OR_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144109568), UINT64_C(0),	// BUFFER_ATOMIC_OR_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363056128), UINT64_C(0),	// BUFFER_ATOMIC_OR_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344092160), UINT64_C(0),	// BUFFER_ATOMIC_OR_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735685632), UINT64_C(0),	// BUFFER_ATOMIC_OR_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716721664), UINT64_C(0),	// BUFFER_ATOMIC_OR_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935668224), UINT64_C(0),	// BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916704256), UINT64_C(0),	// BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308297728), UINT64_C(0),	// BUFFER_ATOMIC_OR_VBUFFER_OFFSET_gfx12
    UINT64_C(3289333760), UINT64_C(0),	// BUFFER_ATOMIC_OR_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3781738496), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3781722112), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_ADDR64_gfx6_gfx7
    UINT64_C(3781718016), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx10
    UINT64_C(54043199305957376), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx11
    UINT64_C(3781718016), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3785650176), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx90a
    UINT64_C(3785650176), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_vi
    UINT64_C(3781701632), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_BOTHEN_gfx10
    UINT64_C(54043199305940992), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_BOTHEN_gfx11
    UINT64_C(3781701632), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_BOTHEN_gfx6_gfx7
    UINT64_C(3785633792), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_BOTHEN_gfx90a
    UINT64_C(3785633792), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_BOTHEN_vi
    UINT64_C(3781713920), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_IDXEN_RTN_gfx10
    UINT64_C(36028800796475392), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_IDXEN_RTN_gfx11
    UINT64_C(3781713920), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3785646080), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_IDXEN_RTN_gfx90a
    UINT64_C(3785646080), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_IDXEN_RTN_vi
    UINT64_C(3781697536), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_IDXEN_gfx10
    UINT64_C(36028800796459008), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_IDXEN_gfx11
    UINT64_C(3781697536), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_IDXEN_gfx6_gfx7
    UINT64_C(3785629696), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_IDXEN_gfx90a
    UINT64_C(3785629696), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_IDXEN_vi
    UINT64_C(3781709824), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_OFFEN_RTN_gfx10
    UINT64_C(18014402286993408), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_OFFEN_RTN_gfx11
    UINT64_C(3781709824), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3785641984), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_OFFEN_RTN_gfx90a
    UINT64_C(3785641984), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_OFFEN_RTN_vi
    UINT64_C(3781693440), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_OFFEN_gfx10
    UINT64_C(18014402286977024), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_OFFEN_gfx11
    UINT64_C(3781693440), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_OFFEN_gfx6_gfx7
    UINT64_C(3785625600), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_OFFEN_gfx90a
    UINT64_C(3785625600), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_OFFEN_vi
    UINT64_C(3781705728), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_OFFSET_RTN_gfx10
    UINT64_C(3777511424), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_OFFSET_RTN_gfx11
    UINT64_C(3781705728), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3785637888), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_OFFSET_RTN_gfx90a
    UINT64_C(3785637888), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_OFFSET_RTN_vi
    UINT64_C(3781689344), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_OFFSET_gfx10
    UINT64_C(3777495040), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_OFFSET_gfx11
    UINT64_C(3781689344), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_OFFSET_gfx6_gfx7
    UINT64_C(3785621504), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_OFFSET_gfx90a
    UINT64_C(3785621504), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_OFFSET_vi
    UINT64_C(13875590455218044928), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658199080960), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590674432), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571710464), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790657024), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771693056), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163286528), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144322560), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363269120), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344305152), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735898624), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716934656), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935881216), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916917248), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308510720), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_gfx12
    UINT64_C(3289546752), UINT64_C(0),	// BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3779620864), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN_RTN_gfx90a
    UINT64_C(3779620864), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN_RTN_gfx940
    UINT64_C(3779620864), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN_RTN_vi
    UINT64_C(3779604480), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN_gfx90a
    UINT64_C(3779604480), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN_gfx940
    UINT64_C(3779604480), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN_vi
    UINT64_C(3779616768), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_IDXEN_RTN_gfx90a
    UINT64_C(3779616768), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_IDXEN_RTN_gfx940
    UINT64_C(3779616768), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_IDXEN_RTN_vi
    UINT64_C(3779600384), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_IDXEN_gfx90a
    UINT64_C(3779600384), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_IDXEN_gfx940
    UINT64_C(3779600384), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_IDXEN_vi
    UINT64_C(3779612672), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_OFFEN_RTN_gfx90a
    UINT64_C(3779612672), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_OFFEN_RTN_gfx940
    UINT64_C(3779612672), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_OFFEN_RTN_vi
    UINT64_C(3779596288), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_OFFEN_gfx90a
    UINT64_C(3779596288), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_OFFEN_gfx940
    UINT64_C(3779596288), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_OFFEN_vi
    UINT64_C(3779608576), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_OFFSET_RTN_gfx90a
    UINT64_C(3779608576), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_OFFSET_RTN_gfx940
    UINT64_C(3779608576), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_OFFSET_RTN_vi
    UINT64_C(3779592192), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_OFFSET_gfx90a
    UINT64_C(3779592192), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_OFFSET_gfx940
    UINT64_C(3779592192), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_OFFSET_vi
    UINT64_C(13875590455218307072), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658199343104), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590936576), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571972608), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790919168), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771955200), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163548672), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144584704), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363531264), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344567296), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818736160768), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021717196800), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399936143360), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602917179392), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308772864), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFSET_gfx12
    UINT64_C(3289808896), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3778572288), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_RTN_gfx90a
    UINT64_C(3778572288), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_RTN_gfx940
    UINT64_C(3778572288), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_RTN_vi
    UINT64_C(3778555904), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_gfx90a
    UINT64_C(3778555904), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_gfx940
    UINT64_C(3778555904), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_vi
    UINT64_C(3778568192), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_IDXEN_RTN_gfx90a
    UINT64_C(3778568192), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_IDXEN_RTN_gfx940
    UINT64_C(3778568192), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_IDXEN_RTN_vi
    UINT64_C(3778551808), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_IDXEN_gfx90a
    UINT64_C(3778551808), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_IDXEN_gfx940
    UINT64_C(3778551808), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_IDXEN_vi
    UINT64_C(3778564096), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_OFFEN_RTN_gfx90a
    UINT64_C(3778564096), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_OFFEN_RTN_gfx940
    UINT64_C(3778564096), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_OFFEN_RTN_vi
    UINT64_C(3778547712), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_OFFEN_gfx90a
    UINT64_C(3778547712), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_OFFEN_gfx940
    UINT64_C(3778547712), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_OFFEN_vi
    UINT64_C(3778560000), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_OFFSET_RTN_gfx90a
    UINT64_C(3778560000), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_OFFSET_RTN_gfx940
    UINT64_C(3778560000), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_OFFSET_RTN_vi
    UINT64_C(3778543616), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_OFFSET_gfx90a
    UINT64_C(3778543616), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_OFFSET_gfx940
    UINT64_C(3778543616), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_OFFSET_vi
    UINT64_C(13875590455218290688), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658199326720), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590920192), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571956224), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790902784), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771938816), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163532288), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144568320), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363514880), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344550912), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818736144384), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021717180416), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399936126976), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602917163008), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308756480), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFSET_gfx12
    UINT64_C(3289792512), UINT64_C(0),	// BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3772563456), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3772547072), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_ADDR64_gfx6_gfx7
    UINT64_C(3772542976), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx10
    UINT64_C(54043199301763072), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx11
    UINT64_C(3772542976), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3776475136), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx90a
    UINT64_C(3776475136), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_BOTHEN_RTN_vi
    UINT64_C(3772526592), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_BOTHEN_gfx10
    UINT64_C(54043199301746688), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_BOTHEN_gfx11
    UINT64_C(3772526592), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_BOTHEN_gfx6_gfx7
    UINT64_C(3776458752), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_BOTHEN_gfx90a
    UINT64_C(3776458752), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_BOTHEN_vi
    UINT64_C(3772538880), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_IDXEN_RTN_gfx10
    UINT64_C(36028800792281088), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_IDXEN_RTN_gfx11
    UINT64_C(3772538880), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3776471040), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_IDXEN_RTN_gfx90a
    UINT64_C(3776471040), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_IDXEN_RTN_vi
    UINT64_C(3772522496), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_IDXEN_gfx10
    UINT64_C(36028800792264704), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_IDXEN_gfx11
    UINT64_C(3772522496), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_IDXEN_gfx6_gfx7
    UINT64_C(3776454656), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_IDXEN_gfx90a
    UINT64_C(3776454656), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_IDXEN_vi
    UINT64_C(3772534784), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_OFFEN_RTN_gfx10
    UINT64_C(18014402282799104), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_OFFEN_RTN_gfx11
    UINT64_C(3772534784), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3776466944), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_OFFEN_RTN_gfx90a
    UINT64_C(3776466944), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_OFFEN_RTN_vi
    UINT64_C(3772518400), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_OFFEN_gfx10
    UINT64_C(18014402282782720), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_OFFEN_gfx11
    UINT64_C(3772518400), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_OFFEN_gfx6_gfx7
    UINT64_C(3776450560), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_OFFEN_gfx90a
    UINT64_C(3776450560), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_OFFEN_vi
    UINT64_C(3772530688), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx10
    UINT64_C(3773317120), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx11
    UINT64_C(3772530688), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3776462848), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx90a
    UINT64_C(3776462848), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_OFFSET_RTN_vi
    UINT64_C(3772514304), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_OFFSET_gfx10
    UINT64_C(3773300736), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_OFFSET_gfx11
    UINT64_C(3772514304), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_OFFSET_gfx6_gfx7
    UINT64_C(3776446464), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_OFFSET_gfx90a
    UINT64_C(3776446464), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_OFFSET_vi
    UINT64_C(13875590455217782784), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658198818816), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590412288), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571448320), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790394880), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771430912), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163024384), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144060416), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363006976), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344043008), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735636480), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716672512), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935619072), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916655104), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308248576), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_gfx12
    UINT64_C(3289284608), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3780952064), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3780935680), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_ADDR64_gfx6_gfx7
    UINT64_C(3780931584), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx10
    UINT64_C(54043199305170944), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx11
    UINT64_C(3780931584), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3784863744), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx90a
    UINT64_C(3784863744), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_vi
    UINT64_C(3780915200), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_BOTHEN_gfx10
    UINT64_C(54043199305154560), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_BOTHEN_gfx11
    UINT64_C(3780915200), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_BOTHEN_gfx6_gfx7
    UINT64_C(3784847360), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_BOTHEN_gfx90a
    UINT64_C(3784847360), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_BOTHEN_vi
    UINT64_C(3780927488), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_gfx10
    UINT64_C(36028800795688960), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_gfx11
    UINT64_C(3780927488), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3784859648), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_gfx90a
    UINT64_C(3784859648), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_vi
    UINT64_C(3780911104), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_IDXEN_gfx10
    UINT64_C(36028800795672576), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_IDXEN_gfx11
    UINT64_C(3780911104), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_IDXEN_gfx6_gfx7
    UINT64_C(3784843264), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_IDXEN_gfx90a
    UINT64_C(3784843264), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_IDXEN_vi
    UINT64_C(3780923392), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_gfx10
    UINT64_C(18014402286206976), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_gfx11
    UINT64_C(3780923392), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3784855552), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_gfx90a
    UINT64_C(3784855552), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_vi
    UINT64_C(3780907008), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_OFFEN_gfx10
    UINT64_C(18014402286190592), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_OFFEN_gfx11
    UINT64_C(3780907008), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_OFFEN_gfx6_gfx7
    UINT64_C(3784839168), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_OFFEN_gfx90a
    UINT64_C(3784839168), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_OFFEN_vi
    UINT64_C(3780919296), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_gfx10
    UINT64_C(3776724992), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_gfx11
    UINT64_C(3780919296), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3784851456), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_gfx90a
    UINT64_C(3784851456), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_vi
    UINT64_C(3780902912), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_OFFSET_gfx10
    UINT64_C(3776708608), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_OFFSET_gfx11
    UINT64_C(3780902912), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_OFFSET_gfx6_gfx7
    UINT64_C(3784835072), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_OFFSET_gfx90a
    UINT64_C(3784835072), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_OFFSET_vi
    UINT64_C(13875590455217995776), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658199031808), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590625280), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571661312), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790607872), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771643904), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163237376), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144273408), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363219968), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344256000), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735849472), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716885504), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935832064), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916868096), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308461568), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_gfx12
    UINT64_C(3289497600), UINT64_C(0),	// BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3772039168), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3772022784), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_ADDR64_gfx6_gfx7
    UINT64_C(3772018688), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx10
    UINT64_C(54043199301238784), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx11
    UINT64_C(3772018688), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3775950848), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx90a
    UINT64_C(3775950848), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_BOTHEN_RTN_vi
    UINT64_C(3772002304), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_BOTHEN_gfx10
    UINT64_C(54043199301222400), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_BOTHEN_gfx11
    UINT64_C(3772002304), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_BOTHEN_gfx6_gfx7
    UINT64_C(3775934464), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_BOTHEN_gfx90a
    UINT64_C(3775934464), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_BOTHEN_vi
    UINT64_C(3772014592), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_IDXEN_RTN_gfx10
    UINT64_C(36028800791756800), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_IDXEN_RTN_gfx11
    UINT64_C(3772014592), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3775946752), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_IDXEN_RTN_gfx90a
    UINT64_C(3775946752), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_IDXEN_RTN_vi
    UINT64_C(3771998208), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_IDXEN_gfx10
    UINT64_C(36028800791740416), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_IDXEN_gfx11
    UINT64_C(3771998208), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_IDXEN_gfx6_gfx7
    UINT64_C(3775930368), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_IDXEN_gfx90a
    UINT64_C(3775930368), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_IDXEN_vi
    UINT64_C(3772010496), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_OFFEN_RTN_gfx10
    UINT64_C(18014402282274816), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_OFFEN_RTN_gfx11
    UINT64_C(3772010496), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3775942656), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_OFFEN_RTN_gfx90a
    UINT64_C(3775942656), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_OFFEN_RTN_vi
    UINT64_C(3771994112), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_OFFEN_gfx10
    UINT64_C(18014402282258432), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_OFFEN_gfx11
    UINT64_C(3771994112), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_OFFEN_gfx6_gfx7
    UINT64_C(3775926272), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_OFFEN_gfx90a
    UINT64_C(3775926272), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_OFFEN_vi
    UINT64_C(3772006400), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx10
    UINT64_C(3772792832), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx11
    UINT64_C(3772006400), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3775938560), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx90a
    UINT64_C(3775938560), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_OFFSET_RTN_vi
    UINT64_C(3771990016), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_OFFSET_gfx10
    UINT64_C(3772776448), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_OFFSET_gfx11
    UINT64_C(3771990016), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_OFFSET_gfx6_gfx7
    UINT64_C(3775922176), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_OFFSET_gfx90a
    UINT64_C(3775922176), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_OFFSET_vi
    UINT64_C(13875590455217750016), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658198786048), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590379520), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571415552), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790362112), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771398144), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837162991616), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144027648), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418362974208), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344010240), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735603712), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716639744), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935586304), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916622336), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308215808), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_gfx12
    UINT64_C(3289251840), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3780427776), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3780411392), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_ADDR64_gfx6_gfx7
    UINT64_C(3780407296), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx10
    UINT64_C(54043199304646656), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx11
    UINT64_C(3780407296), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3784339456), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx90a
    UINT64_C(3784339456), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_vi
    UINT64_C(3780390912), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_BOTHEN_gfx10
    UINT64_C(54043199304630272), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_BOTHEN_gfx11
    UINT64_C(3780390912), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_BOTHEN_gfx6_gfx7
    UINT64_C(3784323072), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_BOTHEN_gfx90a
    UINT64_C(3784323072), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_BOTHEN_vi
    UINT64_C(3780403200), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_gfx10
    UINT64_C(36028800795164672), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_gfx11
    UINT64_C(3780403200), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3784335360), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_gfx90a
    UINT64_C(3784335360), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_vi
    UINT64_C(3780386816), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_IDXEN_gfx10
    UINT64_C(36028800795148288), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_IDXEN_gfx11
    UINT64_C(3780386816), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_IDXEN_gfx6_gfx7
    UINT64_C(3784318976), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_IDXEN_gfx90a
    UINT64_C(3784318976), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_IDXEN_vi
    UINT64_C(3780399104), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_gfx10
    UINT64_C(18014402285682688), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_gfx11
    UINT64_C(3780399104), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3784331264), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_gfx90a
    UINT64_C(3784331264), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_vi
    UINT64_C(3780382720), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_OFFEN_gfx10
    UINT64_C(18014402285666304), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_OFFEN_gfx11
    UINT64_C(3780382720), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_OFFEN_gfx6_gfx7
    UINT64_C(3784314880), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_OFFEN_gfx90a
    UINT64_C(3784314880), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_OFFEN_vi
    UINT64_C(3780395008), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_gfx10
    UINT64_C(3776200704), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_gfx11
    UINT64_C(3780395008), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3784327168), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_gfx90a
    UINT64_C(3784327168), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_vi
    UINT64_C(3780378624), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_OFFSET_gfx10
    UINT64_C(3776184320), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_OFFSET_gfx11
    UINT64_C(3780378624), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_OFFSET_gfx6_gfx7
    UINT64_C(3784310784), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_OFFSET_gfx90a
    UINT64_C(3784310784), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_OFFSET_vi
    UINT64_C(13875590455217963008), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658198999040), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590592512), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571628544), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790575104), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771611136), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163204608), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144240640), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363187200), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344223232), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735816704), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716852736), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935799296), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916835328), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308428800), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_gfx12
    UINT64_C(3289464832), UINT64_C(0),	// BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3771514880), UINT64_C(0),	// BUFFER_ATOMIC_SUB_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3771498496), UINT64_C(0),	// BUFFER_ATOMIC_SUB_ADDR64_gfx6_gfx7
    UINT64_C(3771494400), UINT64_C(0),	// BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx10
    UINT64_C(54043199300714496), UINT64_C(0),	// BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx11
    UINT64_C(3771494400), UINT64_C(0),	// BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3775688704), UINT64_C(0),	// BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx90a
    UINT64_C(3775688704), UINT64_C(0),	// BUFFER_ATOMIC_SUB_BOTHEN_RTN_vi
    UINT64_C(3771478016), UINT64_C(0),	// BUFFER_ATOMIC_SUB_BOTHEN_gfx10
    UINT64_C(54043199300698112), UINT64_C(0),	// BUFFER_ATOMIC_SUB_BOTHEN_gfx11
    UINT64_C(3771478016), UINT64_C(0),	// BUFFER_ATOMIC_SUB_BOTHEN_gfx6_gfx7
    UINT64_C(3775672320), UINT64_C(0),	// BUFFER_ATOMIC_SUB_BOTHEN_gfx90a
    UINT64_C(3775672320), UINT64_C(0),	// BUFFER_ATOMIC_SUB_BOTHEN_vi
    UINT64_C(3771490304), UINT64_C(0),	// BUFFER_ATOMIC_SUB_IDXEN_RTN_gfx10
    UINT64_C(36028800791232512), UINT64_C(0),	// BUFFER_ATOMIC_SUB_IDXEN_RTN_gfx11
    UINT64_C(3771490304), UINT64_C(0),	// BUFFER_ATOMIC_SUB_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3775684608), UINT64_C(0),	// BUFFER_ATOMIC_SUB_IDXEN_RTN_gfx90a
    UINT64_C(3775684608), UINT64_C(0),	// BUFFER_ATOMIC_SUB_IDXEN_RTN_vi
    UINT64_C(3771473920), UINT64_C(0),	// BUFFER_ATOMIC_SUB_IDXEN_gfx10
    UINT64_C(36028800791216128), UINT64_C(0),	// BUFFER_ATOMIC_SUB_IDXEN_gfx11
    UINT64_C(3771473920), UINT64_C(0),	// BUFFER_ATOMIC_SUB_IDXEN_gfx6_gfx7
    UINT64_C(3775668224), UINT64_C(0),	// BUFFER_ATOMIC_SUB_IDXEN_gfx90a
    UINT64_C(3775668224), UINT64_C(0),	// BUFFER_ATOMIC_SUB_IDXEN_vi
    UINT64_C(3771486208), UINT64_C(0),	// BUFFER_ATOMIC_SUB_OFFEN_RTN_gfx10
    UINT64_C(18014402281750528), UINT64_C(0),	// BUFFER_ATOMIC_SUB_OFFEN_RTN_gfx11
    UINT64_C(3771486208), UINT64_C(0),	// BUFFER_ATOMIC_SUB_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3775680512), UINT64_C(0),	// BUFFER_ATOMIC_SUB_OFFEN_RTN_gfx90a
    UINT64_C(3775680512), UINT64_C(0),	// BUFFER_ATOMIC_SUB_OFFEN_RTN_vi
    UINT64_C(3771469824), UINT64_C(0),	// BUFFER_ATOMIC_SUB_OFFEN_gfx10
    UINT64_C(18014402281734144), UINT64_C(0),	// BUFFER_ATOMIC_SUB_OFFEN_gfx11
    UINT64_C(3771469824), UINT64_C(0),	// BUFFER_ATOMIC_SUB_OFFEN_gfx6_gfx7
    UINT64_C(3775664128), UINT64_C(0),	// BUFFER_ATOMIC_SUB_OFFEN_gfx90a
    UINT64_C(3775664128), UINT64_C(0),	// BUFFER_ATOMIC_SUB_OFFEN_vi
    UINT64_C(3771482112), UINT64_C(0),	// BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx10
    UINT64_C(3772268544), UINT64_C(0),	// BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx11
    UINT64_C(3771482112), UINT64_C(0),	// BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3775676416), UINT64_C(0),	// BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx90a
    UINT64_C(3775676416), UINT64_C(0),	// BUFFER_ATOMIC_SUB_OFFSET_RTN_vi
    UINT64_C(3771465728), UINT64_C(0),	// BUFFER_ATOMIC_SUB_OFFSET_gfx10
    UINT64_C(3772252160), UINT64_C(0),	// BUFFER_ATOMIC_SUB_OFFSET_gfx11
    UINT64_C(3771465728), UINT64_C(0),	// BUFFER_ATOMIC_SUB_OFFSET_gfx6_gfx7
    UINT64_C(3775660032), UINT64_C(0),	// BUFFER_ATOMIC_SUB_OFFSET_gfx90a
    UINT64_C(3775660032), UINT64_C(0),	// BUFFER_ATOMIC_SUB_OFFSET_vi
    UINT64_C(13875590455217717248), UINT64_C(0),	// BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658198753280), UINT64_C(0),	// BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590346752), UINT64_C(0),	// BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571382784), UINT64_C(0),	// BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790329344), UINT64_C(0),	// BUFFER_ATOMIC_SUB_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771365376), UINT64_C(0),	// BUFFER_ATOMIC_SUB_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837162958848), UINT64_C(0),	// BUFFER_ATOMIC_SUB_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143994880), UINT64_C(0),	// BUFFER_ATOMIC_SUB_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418362941440), UINT64_C(0),	// BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621343977472), UINT64_C(0),	// BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735570944), UINT64_C(0),	// BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716606976), UINT64_C(0),	// BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935553536), UINT64_C(0),	// BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916589568), UINT64_C(0),	// BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308183040), UINT64_C(0),	// BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_gfx12
    UINT64_C(3289219072), UINT64_C(0),	// BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3779903488), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3779887104), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_ADDR64_gfx6_gfx7
    UINT64_C(3779883008), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx10
    UINT64_C(54043199304384512), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx11
    UINT64_C(3779883008), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3784077312), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx90a
    UINT64_C(3784077312), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_vi
    UINT64_C(3779866624), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_BOTHEN_gfx10
    UINT64_C(54043199304368128), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_BOTHEN_gfx11
    UINT64_C(3779866624), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_BOTHEN_gfx6_gfx7
    UINT64_C(3784060928), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_BOTHEN_gfx90a
    UINT64_C(3784060928), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_BOTHEN_vi
    UINT64_C(3779878912), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_gfx10
    UINT64_C(36028800794902528), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_gfx11
    UINT64_C(3779878912), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3784073216), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_gfx90a
    UINT64_C(3784073216), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_vi
    UINT64_C(3779862528), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_IDXEN_gfx10
    UINT64_C(36028800794886144), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_IDXEN_gfx11
    UINT64_C(3779862528), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_IDXEN_gfx6_gfx7
    UINT64_C(3784056832), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_IDXEN_gfx90a
    UINT64_C(3784056832), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_IDXEN_vi
    UINT64_C(3779874816), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_gfx10
    UINT64_C(18014402285420544), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_gfx11
    UINT64_C(3779874816), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3784069120), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_gfx90a
    UINT64_C(3784069120), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_vi
    UINT64_C(3779858432), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_OFFEN_gfx10
    UINT64_C(18014402285404160), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_OFFEN_gfx11
    UINT64_C(3779858432), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_OFFEN_gfx6_gfx7
    UINT64_C(3784052736), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_OFFEN_gfx90a
    UINT64_C(3784052736), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_OFFEN_vi
    UINT64_C(3779870720), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_gfx10
    UINT64_C(3775938560), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_gfx11
    UINT64_C(3779870720), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3784065024), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_gfx90a
    UINT64_C(3784065024), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_vi
    UINT64_C(3779854336), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_OFFSET_gfx10
    UINT64_C(3775922176), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_OFFSET_gfx11
    UINT64_C(3779854336), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_OFFSET_gfx6_gfx7
    UINT64_C(3784048640), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_OFFSET_gfx90a
    UINT64_C(3784048640), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_OFFSET_vi
    UINT64_C(13875590455217946624), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658198982656), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590576128), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571612160), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790558720), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771594752), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163188224), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144224256), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363170816), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344206848), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735800320), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716836352), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935782912), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916818944), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308412416), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_gfx12
    UINT64_C(3289448448), UINT64_C(0),	// BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3770728448), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3770712064), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_ADDR64_gfx6_gfx7
    UINT64_C(3770707968), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx10
    UINT64_C(54043199299928064), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx11
    UINT64_C(3770707968), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3774902272), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx90a
    UINT64_C(3774902272), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_BOTHEN_RTN_vi
    UINT64_C(3770691584), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_BOTHEN_gfx10
    UINT64_C(54043199299911680), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_BOTHEN_gfx11
    UINT64_C(3770691584), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_BOTHEN_gfx6_gfx7
    UINT64_C(3774885888), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_BOTHEN_gfx90a
    UINT64_C(3774885888), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_BOTHEN_vi
    UINT64_C(3770703872), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_IDXEN_RTN_gfx10
    UINT64_C(36028800790446080), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_IDXEN_RTN_gfx11
    UINT64_C(3770703872), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3774898176), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_IDXEN_RTN_gfx90a
    UINT64_C(3774898176), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_IDXEN_RTN_vi
    UINT64_C(3770687488), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_IDXEN_gfx10
    UINT64_C(36028800790429696), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_IDXEN_gfx11
    UINT64_C(3770687488), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_IDXEN_gfx6_gfx7
    UINT64_C(3774881792), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_IDXEN_gfx90a
    UINT64_C(3774881792), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_IDXEN_vi
    UINT64_C(3770699776), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_OFFEN_RTN_gfx10
    UINT64_C(18014402280964096), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_OFFEN_RTN_gfx11
    UINT64_C(3770699776), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3774894080), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_OFFEN_RTN_gfx90a
    UINT64_C(3774894080), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_OFFEN_RTN_vi
    UINT64_C(3770683392), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_OFFEN_gfx10
    UINT64_C(18014402280947712), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_OFFEN_gfx11
    UINT64_C(3770683392), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_OFFEN_gfx6_gfx7
    UINT64_C(3774877696), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_OFFEN_gfx90a
    UINT64_C(3774877696), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_OFFEN_vi
    UINT64_C(3770695680), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx10
    UINT64_C(3771482112), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx11
    UINT64_C(3770695680), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3774889984), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx90a
    UINT64_C(3774889984), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_OFFSET_RTN_vi
    UINT64_C(3770679296), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_OFFSET_gfx10
    UINT64_C(3771465728), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_OFFSET_gfx11
    UINT64_C(3770679296), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_OFFSET_gfx6_gfx7
    UINT64_C(3774873600), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_OFFSET_gfx90a
    UINT64_C(3774873600), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_OFFSET_vi
    UINT64_C(13875590455217668096), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658198704128), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590297600), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571333632), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790280192), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771316224), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837162909696), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143945728), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418362892288), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621343928320), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735521792), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716557824), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935504384), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916540416), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308133888), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_gfx12
    UINT64_C(3289169920), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3779117056), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3779100672), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_ADDR64_gfx6_gfx7
    UINT64_C(3779096576), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx10
    UINT64_C(54043199303598080), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx11
    UINT64_C(3779096576), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3783290880), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx90a
    UINT64_C(3783290880), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_vi
    UINT64_C(3779080192), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_BOTHEN_gfx10
    UINT64_C(54043199303581696), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_BOTHEN_gfx11
    UINT64_C(3779080192), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_BOTHEN_gfx6_gfx7
    UINT64_C(3783274496), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_BOTHEN_gfx90a
    UINT64_C(3783274496), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_BOTHEN_vi
    UINT64_C(3779092480), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_gfx10
    UINT64_C(36028800794116096), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_gfx11
    UINT64_C(3779092480), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3783286784), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_gfx90a
    UINT64_C(3783286784), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_vi
    UINT64_C(3779076096), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_IDXEN_gfx10
    UINT64_C(36028800794099712), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_IDXEN_gfx11
    UINT64_C(3779076096), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_IDXEN_gfx6_gfx7
    UINT64_C(3783270400), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_IDXEN_gfx90a
    UINT64_C(3783270400), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_IDXEN_vi
    UINT64_C(3779088384), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_gfx10
    UINT64_C(18014402284634112), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_gfx11
    UINT64_C(3779088384), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3783282688), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_gfx90a
    UINT64_C(3783282688), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_vi
    UINT64_C(3779072000), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_OFFEN_gfx10
    UINT64_C(18014402284617728), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_OFFEN_gfx11
    UINT64_C(3779072000), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_OFFEN_gfx6_gfx7
    UINT64_C(3783266304), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_OFFEN_gfx90a
    UINT64_C(3783266304), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_OFFEN_vi
    UINT64_C(3779084288), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_gfx10
    UINT64_C(3775152128), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_gfx11
    UINT64_C(3779084288), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3783278592), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_gfx90a
    UINT64_C(3783278592), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_vi
    UINT64_C(3779067904), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_OFFSET_gfx10
    UINT64_C(3775135744), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_OFFSET_gfx11
    UINT64_C(3779067904), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_OFFSET_gfx6_gfx7
    UINT64_C(3783262208), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_OFFSET_gfx90a
    UINT64_C(3783262208), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_OFFSET_vi
    UINT64_C(13875590455217897472), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658198933504), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590526976), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571563008), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790509568), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771545600), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163139072), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144175104), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363121664), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344157696), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735751168), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716787200), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935733760), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916769792), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308363264), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_gfx12
    UINT64_C(3289399296), UINT64_C(0),	// BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3772825600), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3772809216), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_ADDR64_gfx6_gfx7
    UINT64_C(3772805120), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx10
    UINT64_C(54043199302025216), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx11
    UINT64_C(3772805120), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3776737280), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx90a
    UINT64_C(3776737280), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_BOTHEN_RTN_vi
    UINT64_C(3772788736), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_BOTHEN_gfx10
    UINT64_C(54043199302008832), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_BOTHEN_gfx11
    UINT64_C(3772788736), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_BOTHEN_gfx6_gfx7
    UINT64_C(3776720896), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_BOTHEN_gfx90a
    UINT64_C(3776720896), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_BOTHEN_vi
    UINT64_C(3772801024), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_IDXEN_RTN_gfx10
    UINT64_C(36028800792543232), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_IDXEN_RTN_gfx11
    UINT64_C(3772801024), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3776733184), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_IDXEN_RTN_gfx90a
    UINT64_C(3776733184), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_IDXEN_RTN_vi
    UINT64_C(3772784640), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_IDXEN_gfx10
    UINT64_C(36028800792526848), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_IDXEN_gfx11
    UINT64_C(3772784640), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_IDXEN_gfx6_gfx7
    UINT64_C(3776716800), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_IDXEN_gfx90a
    UINT64_C(3776716800), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_IDXEN_vi
    UINT64_C(3772796928), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_OFFEN_RTN_gfx10
    UINT64_C(18014402283061248), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_OFFEN_RTN_gfx11
    UINT64_C(3772796928), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3776729088), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_OFFEN_RTN_gfx90a
    UINT64_C(3776729088), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_OFFEN_RTN_vi
    UINT64_C(3772780544), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_OFFEN_gfx10
    UINT64_C(18014402283044864), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_OFFEN_gfx11
    UINT64_C(3772780544), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_OFFEN_gfx6_gfx7
    UINT64_C(3776712704), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_OFFEN_gfx90a
    UINT64_C(3776712704), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_OFFEN_vi
    UINT64_C(3772792832), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx10
    UINT64_C(3773579264), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx11
    UINT64_C(3772792832), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3776724992), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx90a
    UINT64_C(3776724992), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_OFFSET_RTN_vi
    UINT64_C(3772776448), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_OFFSET_gfx10
    UINT64_C(3773562880), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_OFFSET_gfx11
    UINT64_C(3772776448), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_OFFSET_gfx6_gfx7
    UINT64_C(3776708608), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_OFFSET_gfx90a
    UINT64_C(3776708608), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_OFFSET_vi
    UINT64_C(13875590455217799168), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658198835200), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590428672), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571464704), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790411264), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771447296), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163040768), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144076800), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363023360), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344059392), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735652864), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716688896), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935635456), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916671488), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308264960), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_gfx12
    UINT64_C(3289300992), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3781214208), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3781197824), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_ADDR64_gfx6_gfx7
    UINT64_C(3781193728), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx10
    UINT64_C(54043199305433088), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx11
    UINT64_C(3781193728), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3785125888), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx90a
    UINT64_C(3785125888), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_vi
    UINT64_C(3781177344), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_BOTHEN_gfx10
    UINT64_C(54043199305416704), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_BOTHEN_gfx11
    UINT64_C(3781177344), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_BOTHEN_gfx6_gfx7
    UINT64_C(3785109504), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_BOTHEN_gfx90a
    UINT64_C(3785109504), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_BOTHEN_vi
    UINT64_C(3781189632), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_gfx10
    UINT64_C(36028800795951104), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_gfx11
    UINT64_C(3781189632), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3785121792), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_gfx90a
    UINT64_C(3785121792), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_vi
    UINT64_C(3781173248), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_IDXEN_gfx10
    UINT64_C(36028800795934720), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_IDXEN_gfx11
    UINT64_C(3781173248), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_IDXEN_gfx6_gfx7
    UINT64_C(3785105408), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_IDXEN_gfx90a
    UINT64_C(3785105408), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_IDXEN_vi
    UINT64_C(3781185536), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_gfx10
    UINT64_C(18014402286469120), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_gfx11
    UINT64_C(3781185536), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3785117696), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_gfx90a
    UINT64_C(3785117696), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_vi
    UINT64_C(3781169152), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_OFFEN_gfx10
    UINT64_C(18014402286452736), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_OFFEN_gfx11
    UINT64_C(3781169152), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_OFFEN_gfx6_gfx7
    UINT64_C(3785101312), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_OFFEN_gfx90a
    UINT64_C(3785101312), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_OFFEN_vi
    UINT64_C(3781181440), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_gfx10
    UINT64_C(3776987136), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_gfx11
    UINT64_C(3781181440), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3785113600), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_gfx90a
    UINT64_C(3785113600), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_vi
    UINT64_C(3781165056), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_OFFSET_gfx10
    UINT64_C(3776970752), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_OFFSET_gfx11
    UINT64_C(3781165056), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_OFFSET_gfx6_gfx7
    UINT64_C(3785097216), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_OFFSET_gfx90a
    UINT64_C(3785097216), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_OFFSET_vi
    UINT64_C(13875590455218012160), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658199048192), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590641664), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571677696), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790624256), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771660288), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163253760), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144289792), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363236352), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344272384), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735865856), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716901888), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935848448), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916884480), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308477952), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_gfx12
    UINT64_C(3289513984), UINT64_C(0),	// BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3772301312), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3772284928), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_ADDR64_gfx6_gfx7
    UINT64_C(3772280832), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx10
    UINT64_C(54043199301500928), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx11
    UINT64_C(3772280832), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3776212992), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx90a
    UINT64_C(3776212992), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_BOTHEN_RTN_vi
    UINT64_C(3772264448), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_BOTHEN_gfx10
    UINT64_C(54043199301484544), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_BOTHEN_gfx11
    UINT64_C(3772264448), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_BOTHEN_gfx6_gfx7
    UINT64_C(3776196608), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_BOTHEN_gfx90a
    UINT64_C(3776196608), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_BOTHEN_vi
    UINT64_C(3772276736), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_IDXEN_RTN_gfx10
    UINT64_C(36028800792018944), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_IDXEN_RTN_gfx11
    UINT64_C(3772276736), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3776208896), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_IDXEN_RTN_gfx90a
    UINT64_C(3776208896), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_IDXEN_RTN_vi
    UINT64_C(3772260352), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_IDXEN_gfx10
    UINT64_C(36028800792002560), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_IDXEN_gfx11
    UINT64_C(3772260352), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_IDXEN_gfx6_gfx7
    UINT64_C(3776192512), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_IDXEN_gfx90a
    UINT64_C(3776192512), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_IDXEN_vi
    UINT64_C(3772272640), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_OFFEN_RTN_gfx10
    UINT64_C(18014402282536960), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_OFFEN_RTN_gfx11
    UINT64_C(3772272640), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3776204800), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_OFFEN_RTN_gfx90a
    UINT64_C(3776204800), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_OFFEN_RTN_vi
    UINT64_C(3772256256), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_OFFEN_gfx10
    UINT64_C(18014402282520576), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_OFFEN_gfx11
    UINT64_C(3772256256), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_OFFEN_gfx6_gfx7
    UINT64_C(3776188416), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_OFFEN_gfx90a
    UINT64_C(3776188416), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_OFFEN_vi
    UINT64_C(3772268544), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx10
    UINT64_C(3773054976), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx11
    UINT64_C(3772268544), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3776200704), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx90a
    UINT64_C(3776200704), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_OFFSET_RTN_vi
    UINT64_C(3772252160), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_OFFSET_gfx10
    UINT64_C(3773038592), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_OFFSET_gfx11
    UINT64_C(3772252160), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_OFFSET_gfx6_gfx7
    UINT64_C(3776184320), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_OFFSET_gfx90a
    UINT64_C(3776184320), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_OFFSET_vi
    UINT64_C(13875590455217766400), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658198802432), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590395904), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571431936), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790378496), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771414528), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163008000), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144044032), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418362990592), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344026624), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735620096), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716656128), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935602688), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916638720), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308232192), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_gfx12
    UINT64_C(3289268224), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3780689920), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3780673536), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_ADDR64_gfx6_gfx7
    UINT64_C(3780669440), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx10
    UINT64_C(54043199304908800), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx11
    UINT64_C(3780669440), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3784601600), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx90a
    UINT64_C(3784601600), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_vi
    UINT64_C(3780653056), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_BOTHEN_gfx10
    UINT64_C(54043199304892416), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_BOTHEN_gfx11
    UINT64_C(3780653056), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_BOTHEN_gfx6_gfx7
    UINT64_C(3784585216), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_BOTHEN_gfx90a
    UINT64_C(3784585216), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_BOTHEN_vi
    UINT64_C(3780665344), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_gfx10
    UINT64_C(36028800795426816), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_gfx11
    UINT64_C(3780665344), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3784597504), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_gfx90a
    UINT64_C(3784597504), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_vi
    UINT64_C(3780648960), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_IDXEN_gfx10
    UINT64_C(36028800795410432), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_IDXEN_gfx11
    UINT64_C(3780648960), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_IDXEN_gfx6_gfx7
    UINT64_C(3784581120), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_IDXEN_gfx90a
    UINT64_C(3784581120), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_IDXEN_vi
    UINT64_C(3780661248), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_gfx10
    UINT64_C(18014402285944832), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_gfx11
    UINT64_C(3780661248), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3784593408), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_gfx90a
    UINT64_C(3784593408), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_vi
    UINT64_C(3780644864), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_OFFEN_gfx10
    UINT64_C(18014402285928448), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_OFFEN_gfx11
    UINT64_C(3780644864), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_OFFEN_gfx6_gfx7
    UINT64_C(3784577024), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_OFFEN_gfx90a
    UINT64_C(3784577024), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_OFFEN_vi
    UINT64_C(3780657152), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_gfx10
    UINT64_C(3776462848), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_gfx11
    UINT64_C(3780657152), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3784589312), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_gfx90a
    UINT64_C(3784589312), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_vi
    UINT64_C(3780640768), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_OFFSET_gfx10
    UINT64_C(3776446464), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_OFFSET_gfx11
    UINT64_C(3780640768), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_OFFSET_gfx6_gfx7
    UINT64_C(3784572928), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_OFFSET_gfx90a
    UINT64_C(3784572928), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_OFFSET_vi
    UINT64_C(13875590455217979392), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658199015424), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590608896), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571644928), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790591488), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771627520), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163220992), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144257024), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363203584), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344239616), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735833088), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716869120), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935815680), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916851712), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308445184), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_gfx12
    UINT64_C(3289481216), UINT64_C(0),	// BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3773612032), UINT64_C(0),	// BUFFER_ATOMIC_XOR_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3773595648), UINT64_C(0),	// BUFFER_ATOMIC_XOR_ADDR64_gfx6_gfx7
    UINT64_C(3773591552), UINT64_C(0),	// BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx10
    UINT64_C(54043199302811648), UINT64_C(0),	// BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx11
    UINT64_C(3773591552), UINT64_C(0),	// BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3777523712), UINT64_C(0),	// BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx90a
    UINT64_C(3777523712), UINT64_C(0),	// BUFFER_ATOMIC_XOR_BOTHEN_RTN_vi
    UINT64_C(3773575168), UINT64_C(0),	// BUFFER_ATOMIC_XOR_BOTHEN_gfx10
    UINT64_C(54043199302795264), UINT64_C(0),	// BUFFER_ATOMIC_XOR_BOTHEN_gfx11
    UINT64_C(3773575168), UINT64_C(0),	// BUFFER_ATOMIC_XOR_BOTHEN_gfx6_gfx7
    UINT64_C(3777507328), UINT64_C(0),	// BUFFER_ATOMIC_XOR_BOTHEN_gfx90a
    UINT64_C(3777507328), UINT64_C(0),	// BUFFER_ATOMIC_XOR_BOTHEN_vi
    UINT64_C(3773587456), UINT64_C(0),	// BUFFER_ATOMIC_XOR_IDXEN_RTN_gfx10
    UINT64_C(36028800793329664), UINT64_C(0),	// BUFFER_ATOMIC_XOR_IDXEN_RTN_gfx11
    UINT64_C(3773587456), UINT64_C(0),	// BUFFER_ATOMIC_XOR_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3777519616), UINT64_C(0),	// BUFFER_ATOMIC_XOR_IDXEN_RTN_gfx90a
    UINT64_C(3777519616), UINT64_C(0),	// BUFFER_ATOMIC_XOR_IDXEN_RTN_vi
    UINT64_C(3773571072), UINT64_C(0),	// BUFFER_ATOMIC_XOR_IDXEN_gfx10
    UINT64_C(36028800793313280), UINT64_C(0),	// BUFFER_ATOMIC_XOR_IDXEN_gfx11
    UINT64_C(3773571072), UINT64_C(0),	// BUFFER_ATOMIC_XOR_IDXEN_gfx6_gfx7
    UINT64_C(3777503232), UINT64_C(0),	// BUFFER_ATOMIC_XOR_IDXEN_gfx90a
    UINT64_C(3777503232), UINT64_C(0),	// BUFFER_ATOMIC_XOR_IDXEN_vi
    UINT64_C(3773583360), UINT64_C(0),	// BUFFER_ATOMIC_XOR_OFFEN_RTN_gfx10
    UINT64_C(18014402283847680), UINT64_C(0),	// BUFFER_ATOMIC_XOR_OFFEN_RTN_gfx11
    UINT64_C(3773583360), UINT64_C(0),	// BUFFER_ATOMIC_XOR_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3777515520), UINT64_C(0),	// BUFFER_ATOMIC_XOR_OFFEN_RTN_gfx90a
    UINT64_C(3777515520), UINT64_C(0),	// BUFFER_ATOMIC_XOR_OFFEN_RTN_vi
    UINT64_C(3773566976), UINT64_C(0),	// BUFFER_ATOMIC_XOR_OFFEN_gfx10
    UINT64_C(18014402283831296), UINT64_C(0),	// BUFFER_ATOMIC_XOR_OFFEN_gfx11
    UINT64_C(3773566976), UINT64_C(0),	// BUFFER_ATOMIC_XOR_OFFEN_gfx6_gfx7
    UINT64_C(3777499136), UINT64_C(0),	// BUFFER_ATOMIC_XOR_OFFEN_gfx90a
    UINT64_C(3777499136), UINT64_C(0),	// BUFFER_ATOMIC_XOR_OFFEN_vi
    UINT64_C(3773579264), UINT64_C(0),	// BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx10
    UINT64_C(3774365696), UINT64_C(0),	// BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx11
    UINT64_C(3773579264), UINT64_C(0),	// BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3777511424), UINT64_C(0),	// BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx90a
    UINT64_C(3777511424), UINT64_C(0),	// BUFFER_ATOMIC_XOR_OFFSET_RTN_vi
    UINT64_C(3773562880), UINT64_C(0),	// BUFFER_ATOMIC_XOR_OFFSET_gfx10
    UINT64_C(3774349312), UINT64_C(0),	// BUFFER_ATOMIC_XOR_OFFSET_gfx11
    UINT64_C(3773562880), UINT64_C(0),	// BUFFER_ATOMIC_XOR_OFFSET_gfx6_gfx7
    UINT64_C(3777495040), UINT64_C(0),	// BUFFER_ATOMIC_XOR_OFFSET_gfx90a
    UINT64_C(3777495040), UINT64_C(0),	// BUFFER_ATOMIC_XOR_OFFSET_vi
    UINT64_C(13875590455217848320), UINT64_C(0),	// BUFFER_ATOMIC_XOR_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658198884352), UINT64_C(0),	// BUFFER_ATOMIC_XOR_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590477824), UINT64_C(0),	// BUFFER_ATOMIC_XOR_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571513856), UINT64_C(0),	// BUFFER_ATOMIC_XOR_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790460416), UINT64_C(0),	// BUFFER_ATOMIC_XOR_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771496448), UINT64_C(0),	// BUFFER_ATOMIC_XOR_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163089920), UINT64_C(0),	// BUFFER_ATOMIC_XOR_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144125952), UINT64_C(0),	// BUFFER_ATOMIC_XOR_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363072512), UINT64_C(0),	// BUFFER_ATOMIC_XOR_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344108544), UINT64_C(0),	// BUFFER_ATOMIC_XOR_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735702016), UINT64_C(0),	// BUFFER_ATOMIC_XOR_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716738048), UINT64_C(0),	// BUFFER_ATOMIC_XOR_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935684608), UINT64_C(0),	// BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916720640), UINT64_C(0),	// BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308314112), UINT64_C(0),	// BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_gfx12
    UINT64_C(3289350144), UINT64_C(0),	// BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3782000640), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_ADDR64_RTN_gfx6_gfx7
    UINT64_C(3781984256), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_ADDR64_gfx6_gfx7
    UINT64_C(3781980160), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx10
    UINT64_C(54043199306219520), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx11
    UINT64_C(3781980160), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx6_gfx7
    UINT64_C(3785912320), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx90a
    UINT64_C(3785912320), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_vi
    UINT64_C(3781963776), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_BOTHEN_gfx10
    UINT64_C(54043199306203136), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_BOTHEN_gfx11
    UINT64_C(3781963776), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_BOTHEN_gfx6_gfx7
    UINT64_C(3785895936), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_BOTHEN_gfx90a
    UINT64_C(3785895936), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_BOTHEN_vi
    UINT64_C(3781976064), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_gfx10
    UINT64_C(36028800796737536), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_gfx11
    UINT64_C(3781976064), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_gfx6_gfx7
    UINT64_C(3785908224), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_gfx90a
    UINT64_C(3785908224), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_vi
    UINT64_C(3781959680), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_IDXEN_gfx10
    UINT64_C(36028800796721152), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_IDXEN_gfx11
    UINT64_C(3781959680), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_IDXEN_gfx6_gfx7
    UINT64_C(3785891840), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_IDXEN_gfx90a
    UINT64_C(3785891840), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_IDXEN_vi
    UINT64_C(3781971968), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_gfx10
    UINT64_C(18014402287255552), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_gfx11
    UINT64_C(3781971968), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_gfx6_gfx7
    UINT64_C(3785904128), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_gfx90a
    UINT64_C(3785904128), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_vi
    UINT64_C(3781955584), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_OFFEN_gfx10
    UINT64_C(18014402287239168), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_OFFEN_gfx11
    UINT64_C(3781955584), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_OFFEN_gfx6_gfx7
    UINT64_C(3785887744), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_OFFEN_gfx90a
    UINT64_C(3785887744), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_OFFEN_vi
    UINT64_C(3781967872), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_gfx10
    UINT64_C(3777773568), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_gfx11
    UINT64_C(3781967872), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_gfx6_gfx7
    UINT64_C(3785900032), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_gfx90a
    UINT64_C(3785900032), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_vi
    UINT64_C(3781951488), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_OFFSET_gfx10
    UINT64_C(3777757184), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_OFFSET_gfx11
    UINT64_C(3781951488), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_OFFSET_gfx6_gfx7
    UINT64_C(3785883648), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_OFFSET_gfx90a
    UINT64_C(3785883648), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_OFFSET_vi
    UINT64_C(13875590455218061312), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_VBUFFER_BOTHEN_RTN_gfx12
    UINT64_C(13839561658199097344), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_VBUFFER_BOTHEN_RTN_gfx12_format
    UINT64_C(13871086855590690816), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571726848), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9263904436790673408), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_VBUFFER_IDXEN_RTN_gfx12
    UINT64_C(9227875639771709440), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_VBUFFER_IDXEN_RTN_gfx12_format
    UINT64_C(9259400837163302912), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040144338944), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4652218418363285504), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFEN_RTN_gfx12
    UINT64_C(4616189621344321536), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFEN_RTN_gfx12_format
    UINT64_C(4647714818735915008), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716951040), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFEN_gfx12_format
    UINT64_C(40532399935897600), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN_gfx12
    UINT64_C(4503602916933632), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN_gfx12_format
    UINT64_C(36028800308527104), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_gfx12
    UINT64_C(3289563136), UINT64_C(0),	// BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3787718656), UINT64_C(0),	// BUFFER_GL0_INV_gfx10
    UINT64_C(3769368576), UINT64_C(0),	// BUFFER_GL0_INV_gfx11
    UINT64_C(3787980800), UINT64_C(0),	// BUFFER_GL1_INV_gfx10
    UINT64_C(3769630720), UINT64_C(0),	// BUFFER_GL1_INV_gfx11
    UINT64_C(3768844288), UINT64_C(0),	// BUFFER_INVL2_gfx90a
    UINT64_C(3768844288), UINT64_C(0),	// BUFFER_INV_gfx940
    UINT64_C(3761537024), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_ADDR64_gfx6_gfx7
    UINT64_C(3761516544), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_BOTHEN_gfx10
    UINT64_C(54043199292047360), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_BOTHEN_gfx11
    UINT64_C(3761516544), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_BOTHEN_gfx6_gfx7
    UINT64_C(3763613696), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_BOTHEN_gfx90a
    UINT64_C(3763613696), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_BOTHEN_vi
    UINT64_C(3761512448), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_IDXEN_gfx10
    UINT64_C(36028800782565376), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_IDXEN_gfx11
    UINT64_C(3761512448), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_IDXEN_gfx6_gfx7
    UINT64_C(3763609600), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_IDXEN_gfx90a
    UINT64_C(3763609600), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_IDXEN_vi
    UINT64_C(3761508352), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_OFFEN_gfx10
    UINT64_C(18014402273083392), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_OFFEN_gfx11
    UINT64_C(3761508352), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_OFFEN_gfx6_gfx7
    UINT64_C(3763605504), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_OFFEN_gfx90a
    UINT64_C(3763605504), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_OFFEN_vi
    UINT64_C(3761504256), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_OFFSET_gfx10
    UINT64_C(3763601408), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_OFFSET_gfx11
    UINT64_C(3761504256), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_OFFSET_gfx6_gfx7
    UINT64_C(3763601408), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_OFFSET_gfx90a
    UINT64_C(3763601408), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_OFFSET_vi
    UINT64_C(36028800780500992), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800780480512), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_BOTHEN_gfx10
    UINT64_C(63050398546788352), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_BOTHEN_gfx11
    UINT64_C(36028800780480512), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800782577664), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_BOTHEN_vi
    UINT64_C(36028800780476416), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_IDXEN_gfx10
    UINT64_C(45036000037306368), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_IDXEN_gfx11
    UINT64_C(36028800780476416), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800782573568), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_IDXEN_vi
    UINT64_C(36028800780472320), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_OFFEN_gfx10
    UINT64_C(27021601527824384), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_OFFEN_gfx11
    UINT64_C(36028800780472320), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800782569472), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_OFFEN_vi
    UINT64_C(36028800780468224), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_OFFSET_gfx10
    UINT64_C(9007203018342400), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_OFFSET_gfx11
    UINT64_C(36028800780468224), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800782565376), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_OFFSET_vi
    UINT64_C(13871086855594000384), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575036416), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166612480), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147648512), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739224576), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720260608), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311836672), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292872704), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589806080), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570842112), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162418176), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143454208), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818735030272), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716066304), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307642368), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET_gfx12
    UINT64_C(3288678400), UINT64_C(0),	// BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3762061312), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_ADDR64_gfx6_gfx7
    UINT64_C(3762040832), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_BOTHEN_gfx10
    UINT64_C(54043199292309504), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_BOTHEN_gfx11
    UINT64_C(3762040832), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_BOTHEN_gfx6_gfx7
    UINT64_C(3763875840), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_BOTHEN_gfx90a
    UINT64_C(3763875840), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_BOTHEN_vi
    UINT64_C(3762036736), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_IDXEN_gfx10
    UINT64_C(36028800782827520), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_IDXEN_gfx11
    UINT64_C(3762036736), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_IDXEN_gfx6_gfx7
    UINT64_C(3763871744), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_IDXEN_gfx90a
    UINT64_C(3763871744), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_IDXEN_vi
    UINT64_C(3763941376), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_LDS_BOTHEN_gfx90a
    UINT64_C(3763941376), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_LDS_BOTHEN_vi
    UINT64_C(3763937280), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_LDS_IDXEN_gfx90a
    UINT64_C(3763937280), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_LDS_IDXEN_vi
    UINT64_C(3763933184), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_LDS_OFFEN_gfx90a
    UINT64_C(3763933184), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_LDS_OFFEN_vi
    UINT64_C(3763929088), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_LDS_OFFSET_gfx90a
    UINT64_C(3763929088), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_LDS_OFFSET_vi
    UINT64_C(3762032640), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_OFFEN_gfx10
    UINT64_C(18014402273345536), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_OFFEN_gfx11
    UINT64_C(3762032640), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_OFFEN_gfx6_gfx7
    UINT64_C(3763867648), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_OFFEN_gfx90a
    UINT64_C(3763867648), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_OFFEN_vi
    UINT64_C(3762028544), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_OFFSET_gfx10
    UINT64_C(3763863552), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_OFFSET_gfx11
    UINT64_C(3762028544), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_OFFSET_gfx6_gfx7
    UINT64_C(3763863552), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_OFFSET_gfx90a
    UINT64_C(3763863552), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_OFFSET_vi
    UINT64_C(36028800781025280), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800781004800), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_BOTHEN_gfx10
    UINT64_C(63050398547050496), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_BOTHEN_gfx11
    UINT64_C(36028800781004800), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800782839808), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_BOTHEN_vi
    UINT64_C(36028800781000704), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_IDXEN_gfx10
    UINT64_C(45036000037568512), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_IDXEN_gfx11
    UINT64_C(36028800781000704), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800782835712), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_IDXEN_vi
    UINT64_C(36028800780996608), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_OFFEN_gfx10
    UINT64_C(27021601528086528), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_OFFEN_gfx11
    UINT64_C(36028800780996608), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800782831616), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_OFFEN_vi
    UINT64_C(36028800780992512), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_OFFSET_gfx10
    UINT64_C(9007203018604544), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_OFFSET_gfx11
    UINT64_C(36028800780992512), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800782827520), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_OFFSET_vi
    UINT64_C(13871086855594016768), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575052800), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166628864), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147664896), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739240960), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720276992), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311853056), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292889088), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589822464), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570858496), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162434560), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143470592), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818735046656), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716082688), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307658752), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET_gfx12
    UINT64_C(3288694784), UINT64_C(0),	// BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3761799168), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_ADDR64_gfx6_gfx7
    UINT64_C(3761778688), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_BOTHEN_gfx10
    UINT64_C(54043199292571648), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_BOTHEN_gfx11
    UINT64_C(3761778688), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_BOTHEN_gfx6_gfx7
    UINT64_C(3764137984), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_BOTHEN_gfx90a
    UINT64_C(3764137984), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_BOTHEN_vi
    UINT64_C(3761774592), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_IDXEN_gfx10
    UINT64_C(36028800783089664), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_IDXEN_gfx11
    UINT64_C(3761774592), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_IDXEN_gfx6_gfx7
    UINT64_C(3764133888), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_IDXEN_gfx90a
    UINT64_C(3764133888), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_IDXEN_vi
    UINT64_C(3764203520), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_LDS_BOTHEN_gfx90a
    UINT64_C(3764203520), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_LDS_BOTHEN_vi
    UINT64_C(3764199424), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_LDS_IDXEN_gfx90a
    UINT64_C(3764199424), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_LDS_IDXEN_vi
    UINT64_C(3764195328), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_LDS_OFFEN_gfx90a
    UINT64_C(3764195328), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_LDS_OFFEN_vi
    UINT64_C(3764191232), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_LDS_OFFSET_gfx90a
    UINT64_C(3764191232), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_LDS_OFFSET_vi
    UINT64_C(3761770496), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_OFFEN_gfx10
    UINT64_C(18014402273607680), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_OFFEN_gfx11
    UINT64_C(3761770496), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_OFFEN_gfx6_gfx7
    UINT64_C(3764129792), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_OFFEN_gfx90a
    UINT64_C(3764129792), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_OFFEN_vi
    UINT64_C(3761766400), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_OFFSET_gfx10
    UINT64_C(3764125696), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_OFFSET_gfx11
    UINT64_C(3761766400), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_OFFSET_gfx6_gfx7
    UINT64_C(3764125696), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_OFFSET_gfx90a
    UINT64_C(3764125696), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_OFFSET_vi
    UINT64_C(36028800780763136), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800780742656), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_BOTHEN_gfx10
    UINT64_C(63050398547312640), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_BOTHEN_gfx11
    UINT64_C(36028800780742656), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800783101952), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_BOTHEN_vi
    UINT64_C(36028800780738560), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_IDXEN_gfx10
    UINT64_C(45036000037830656), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_IDXEN_gfx11
    UINT64_C(36028800780738560), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800783097856), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_IDXEN_vi
    UINT64_C(36028800780734464), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_OFFEN_gfx10
    UINT64_C(27021601528348672), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_OFFEN_gfx11
    UINT64_C(36028800780734464), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800783093760), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_OFFEN_vi
    UINT64_C(36028800780730368), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_OFFSET_gfx10
    UINT64_C(9007203018866688), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_OFFSET_gfx11
    UINT64_C(36028800780730368), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800783089664), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_OFFSET_vi
    UINT64_C(13871086855594033152), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575069184), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166645248), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147681280), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739257344), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720293376), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311869440), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292905472), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589838848), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570874880), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162450944), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143486976), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818735063040), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716099072), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307675136), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET_gfx12
    UINT64_C(3288711168), UINT64_C(0),	// BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3761274880), UINT64_C(0),	// BUFFER_LOAD_DWORD_ADDR64_gfx6_gfx7
    UINT64_C(3761254400), UINT64_C(0),	// BUFFER_LOAD_DWORD_BOTHEN_gfx10
    UINT64_C(54043199291785216), UINT64_C(0),	// BUFFER_LOAD_DWORD_BOTHEN_gfx11
    UINT64_C(3761254400), UINT64_C(0),	// BUFFER_LOAD_DWORD_BOTHEN_gfx6_gfx7
    UINT64_C(3763351552), UINT64_C(0),	// BUFFER_LOAD_DWORD_BOTHEN_gfx90a
    UINT64_C(3763351552), UINT64_C(0),	// BUFFER_LOAD_DWORD_BOTHEN_vi
    UINT64_C(3761250304), UINT64_C(0),	// BUFFER_LOAD_DWORD_IDXEN_gfx10
    UINT64_C(36028800782303232), UINT64_C(0),	// BUFFER_LOAD_DWORD_IDXEN_gfx11
    UINT64_C(3761250304), UINT64_C(0),	// BUFFER_LOAD_DWORD_IDXEN_gfx6_gfx7
    UINT64_C(3763347456), UINT64_C(0),	// BUFFER_LOAD_DWORD_IDXEN_gfx90a
    UINT64_C(3763347456), UINT64_C(0),	// BUFFER_LOAD_DWORD_IDXEN_vi
    UINT64_C(3761340416), UINT64_C(0),	// BUFFER_LOAD_DWORD_LDS_ADDR64_gfx6_gfx7
    UINT64_C(3761319936), UINT64_C(0),	// BUFFER_LOAD_DWORD_LDS_BOTHEN_gfx10
    UINT64_C(3761319936), UINT64_C(0),	// BUFFER_LOAD_DWORD_LDS_BOTHEN_gfx6_gfx7
    UINT64_C(3763417088), UINT64_C(0),	// BUFFER_LOAD_DWORD_LDS_BOTHEN_gfx90a
    UINT64_C(3763417088), UINT64_C(0),	// BUFFER_LOAD_DWORD_LDS_BOTHEN_vi
    UINT64_C(3761315840), UINT64_C(0),	// BUFFER_LOAD_DWORD_LDS_IDXEN_gfx10
    UINT64_C(3761315840), UINT64_C(0),	// BUFFER_LOAD_DWORD_LDS_IDXEN_gfx6_gfx7
    UINT64_C(3763412992), UINT64_C(0),	// BUFFER_LOAD_DWORD_LDS_IDXEN_gfx90a
    UINT64_C(3763412992), UINT64_C(0),	// BUFFER_LOAD_DWORD_LDS_IDXEN_vi
    UINT64_C(3761311744), UINT64_C(0),	// BUFFER_LOAD_DWORD_LDS_OFFEN_gfx10
    UINT64_C(3761311744), UINT64_C(0),	// BUFFER_LOAD_DWORD_LDS_OFFEN_gfx6_gfx7
    UINT64_C(3763408896), UINT64_C(0),	// BUFFER_LOAD_DWORD_LDS_OFFEN_gfx90a
    UINT64_C(3763408896), UINT64_C(0),	// BUFFER_LOAD_DWORD_LDS_OFFEN_vi
    UINT64_C(3761307648), UINT64_C(0),	// BUFFER_LOAD_DWORD_LDS_OFFSET_gfx10
    UINT64_C(3761307648), UINT64_C(0),	// BUFFER_LOAD_DWORD_LDS_OFFSET_gfx6_gfx7
    UINT64_C(3763404800), UINT64_C(0),	// BUFFER_LOAD_DWORD_LDS_OFFSET_gfx90a
    UINT64_C(3763404800), UINT64_C(0),	// BUFFER_LOAD_DWORD_LDS_OFFSET_vi
    UINT64_C(3761246208), UINT64_C(0),	// BUFFER_LOAD_DWORD_OFFEN_gfx10
    UINT64_C(18014402272821248), UINT64_C(0),	// BUFFER_LOAD_DWORD_OFFEN_gfx11
    UINT64_C(3761246208), UINT64_C(0),	// BUFFER_LOAD_DWORD_OFFEN_gfx6_gfx7
    UINT64_C(3763343360), UINT64_C(0),	// BUFFER_LOAD_DWORD_OFFEN_gfx90a
    UINT64_C(3763343360), UINT64_C(0),	// BUFFER_LOAD_DWORD_OFFEN_vi
    UINT64_C(3761242112), UINT64_C(0),	// BUFFER_LOAD_DWORD_OFFSET_gfx10
    UINT64_C(3763339264), UINT64_C(0),	// BUFFER_LOAD_DWORD_OFFSET_gfx11
    UINT64_C(3761242112), UINT64_C(0),	// BUFFER_LOAD_DWORD_OFFSET_gfx6_gfx7
    UINT64_C(3763339264), UINT64_C(0),	// BUFFER_LOAD_DWORD_OFFSET_gfx90a
    UINT64_C(3763339264), UINT64_C(0),	// BUFFER_LOAD_DWORD_OFFSET_vi
    UINT64_C(36028800780238848), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800780218368), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_BOTHEN_gfx10
    UINT64_C(63050398546526208), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_BOTHEN_gfx11
    UINT64_C(36028800780218368), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800782315520), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_BOTHEN_vi
    UINT64_C(36028800780214272), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_IDXEN_gfx10
    UINT64_C(45036000037044224), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_IDXEN_gfx11
    UINT64_C(36028800780214272), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800782311424), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_IDXEN_vi
    UINT64_C(36028800780210176), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_OFFEN_gfx10
    UINT64_C(27021601527562240), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_OFFEN_gfx11
    UINT64_C(36028800780210176), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800782307328), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_OFFEN_vi
    UINT64_C(36028800780206080), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_OFFSET_gfx10
    UINT64_C(9007203018080256), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_OFFSET_gfx11
    UINT64_C(36028800780206080), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800782303232), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_OFFSET_vi
    UINT64_C(13871086855593984000), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575020032), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166596096), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147632128), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739208192), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720244224), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311820288), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292856320), UINT64_C(0),	// BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589789696), UINT64_C(0),	// BUFFER_LOAD_DWORD_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570825728), UINT64_C(0),	// BUFFER_LOAD_DWORD_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162401792), UINT64_C(0),	// BUFFER_LOAD_DWORD_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143437824), UINT64_C(0),	// BUFFER_LOAD_DWORD_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818735013888), UINT64_C(0),	// BUFFER_LOAD_DWORD_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716049920), UINT64_C(0),	// BUFFER_LOAD_DWORD_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307625984), UINT64_C(0),	// BUFFER_LOAD_DWORD_VBUFFER_OFFSET_gfx12
    UINT64_C(3288662016), UINT64_C(0),	// BUFFER_LOAD_DWORD_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3768070144), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_gfx10
    UINT64_C(54043199296503808), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_gfx11
    UINT64_C(3768070144), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_gfx90a
    UINT64_C(3768070144), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_vi
    UINT64_C(3768066048), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_gfx10
    UINT64_C(36028800787021824), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_gfx11
    UINT64_C(3768066048), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_gfx90a
    UINT64_C(3768066048), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_vi
    UINT64_C(3768061952), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_gfx10
    UINT64_C(18014402277539840), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_gfx11
    UINT64_C(3768061952), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_gfx90a
    UINT64_C(3768061952), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_vi
    UINT64_C(3768057856), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_gfx10
    UINT64_C(3768057856), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_gfx11
    UINT64_C(3768057856), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_gfx90a
    UINT64_C(3768057856), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_vi
    UINT64_C(36028800787034112), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_TFE_BOTHEN_gfx10
    UINT64_C(63050398551244800), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_TFE_BOTHEN_gfx11
    UINT64_C(36028800787034112), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_TFE_BOTHEN_vi
    UINT64_C(36028800787030016), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_TFE_IDXEN_gfx10
    UINT64_C(45036000041762816), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_TFE_IDXEN_gfx11
    UINT64_C(36028800787030016), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_TFE_IDXEN_vi
    UINT64_C(36028800787025920), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_TFE_OFFEN_gfx10
    UINT64_C(27021601532280832), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_TFE_OFFEN_gfx11
    UINT64_C(36028800787025920), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_TFE_OFFEN_vi
    UINT64_C(36028800787021824), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_TFE_OFFSET_gfx10
    UINT64_C(9007203022798848), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_TFE_OFFSET_gfx11
    UINT64_C(36028800787021824), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_TFE_OFFSET_vi
    UINT64_C(13871086855594278912), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575314944), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166891008), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147927040), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739503104), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720539136), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800312115200), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3293151232), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855590084608), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571120640), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162696704), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143732736), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818735308800), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716344832), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307920896), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_OFFSET_gfx12
    UINT64_C(3288956928), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3792449536), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx10
    UINT64_C(54043199289425920), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx11
    UINT64_C(3760992256), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx90a
    UINT64_C(3760992256), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_vi
    UINT64_C(3792445440), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx10
    UINT64_C(36028800779943936), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx11
    UINT64_C(3760988160), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx90a
    UINT64_C(3760988160), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_vi
    UINT64_C(3792441344), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx10
    UINT64_C(18014402270461952), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx11
    UINT64_C(3760984064), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx90a
    UINT64_C(3760984064), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_vi
    UINT64_C(3792437248), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx10
    UINT64_C(3760979968), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx11
    UINT64_C(3760979968), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx90a
    UINT64_C(3760979968), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_vi
    UINT64_C(36028800811413504), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_TFE_BOTHEN_gfx10
    UINT64_C(63050398544166912), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_TFE_BOTHEN_gfx11
    UINT64_C(36028800779956224), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_TFE_BOTHEN_vi
    UINT64_C(36028800811409408), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_TFE_IDXEN_gfx10
    UINT64_C(45036000034684928), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_TFE_IDXEN_gfx11
    UINT64_C(36028800779952128), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_TFE_IDXEN_vi
    UINT64_C(36028800811405312), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_TFE_OFFEN_gfx10
    UINT64_C(27021601525202944), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_TFE_OFFEN_gfx11
    UINT64_C(36028800779948032), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_TFE_OFFEN_vi
    UINT64_C(36028800811401216), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_TFE_OFFSET_gfx10
    UINT64_C(9007203015720960), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_TFE_OFFSET_gfx11
    UINT64_C(36028800779943936), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_TFE_OFFSET_vi
    UINT64_C(13871086855593836544), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058574872576), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166448640), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147484672), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739060736), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720096768), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311672832), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292708864), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589642240), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570678272), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162254336), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143290368), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818734866432), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021715902464), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307478528), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET_gfx12
    UINT64_C(3288514560), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3760992256), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80
    UINT64_C(3760988160), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80
    UINT64_C(3760984064), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80
    UINT64_C(3760979968), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80
    UINT64_C(36028800779956224), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_TFE_BOTHEN_gfx80
    UINT64_C(36028800779952128), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_TFE_IDXEN_gfx80
    UINT64_C(36028800779948032), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_TFE_OFFEN_gfx80
    UINT64_C(36028800779943936), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_TFE_OFFSET_gfx80
    UINT64_C(3792187392), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx10
    UINT64_C(54043199289163776), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx11
    UINT64_C(3760730112), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx90a
    UINT64_C(3760730112), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_vi
    UINT64_C(3792183296), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx10
    UINT64_C(36028800779681792), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx11
    UINT64_C(3760726016), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx90a
    UINT64_C(3760726016), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_vi
    UINT64_C(3792179200), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx10
    UINT64_C(18014402270199808), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx11
    UINT64_C(3760721920), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx90a
    UINT64_C(3760721920), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_vi
    UINT64_C(3792175104), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx10
    UINT64_C(3760717824), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx11
    UINT64_C(3760717824), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx90a
    UINT64_C(3760717824), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_vi
    UINT64_C(36028800811151360), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_TFE_BOTHEN_gfx10
    UINT64_C(63050398543904768), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_TFE_BOTHEN_gfx11
    UINT64_C(36028800779694080), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_TFE_BOTHEN_vi
    UINT64_C(36028800811147264), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_TFE_IDXEN_gfx10
    UINT64_C(45036000034422784), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_TFE_IDXEN_gfx11
    UINT64_C(36028800779689984), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_TFE_IDXEN_vi
    UINT64_C(36028800811143168), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_TFE_OFFEN_gfx10
    UINT64_C(27021601524940800), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_TFE_OFFEN_gfx11
    UINT64_C(36028800779685888), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_TFE_OFFEN_vi
    UINT64_C(36028800811139072), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_TFE_OFFSET_gfx10
    UINT64_C(9007203015458816), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_TFE_OFFSET_gfx11
    UINT64_C(36028800779681792), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_TFE_OFFSET_vi
    UINT64_C(13871086855593820160), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058574856192), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166432256), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147468288), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739044352), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720080384), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311656448), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292692480), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589625856), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570661888), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162237952), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143273984), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818734850048), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021715886080), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307462144), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET_gfx12
    UINT64_C(3288498176), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3760730112), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80
    UINT64_C(3760726016), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80
    UINT64_C(3760721920), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80
    UINT64_C(3760717824), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80
    UINT64_C(36028800779694080), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_TFE_BOTHEN_gfx80
    UINT64_C(36028800779689984), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_TFE_IDXEN_gfx80
    UINT64_C(36028800779685888), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_TFE_OFFEN_gfx80
    UINT64_C(36028800779681792), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_TFE_OFFSET_gfx80
    UINT64_C(3791925248), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx10
    UINT64_C(54043199288901632), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx11
    UINT64_C(3760467968), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx90a
    UINT64_C(3760467968), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_vi
    UINT64_C(3791921152), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx10
    UINT64_C(36028800779419648), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx11
    UINT64_C(3760463872), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx90a
    UINT64_C(3760463872), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_IDXEN_vi
    UINT64_C(3791917056), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx10
    UINT64_C(18014402269937664), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx11
    UINT64_C(3760459776), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx90a
    UINT64_C(3760459776), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_OFFEN_vi
    UINT64_C(3791912960), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx10
    UINT64_C(3760455680), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx11
    UINT64_C(3760455680), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx90a
    UINT64_C(3760455680), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_OFFSET_vi
    UINT64_C(36028800810889216), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_TFE_BOTHEN_gfx10
    UINT64_C(63050398543642624), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_TFE_BOTHEN_gfx11
    UINT64_C(36028800779431936), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_TFE_BOTHEN_vi
    UINT64_C(36028800810885120), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_TFE_IDXEN_gfx10
    UINT64_C(45036000034160640), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_TFE_IDXEN_gfx11
    UINT64_C(36028800779427840), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_TFE_IDXEN_vi
    UINT64_C(36028800810881024), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_TFE_OFFEN_gfx10
    UINT64_C(27021601524678656), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_TFE_OFFEN_gfx11
    UINT64_C(36028800779423744), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_TFE_OFFEN_vi
    UINT64_C(36028800810876928), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_TFE_OFFSET_gfx10
    UINT64_C(9007203015196672), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_TFE_OFFSET_gfx11
    UINT64_C(36028800779419648), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_TFE_OFFSET_vi
    UINT64_C(13871086855593803776), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058574839808), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166415872), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147451904), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739027968), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720064000), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311640064), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292676096), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589609472), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570645504), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162221568), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143257600), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818734833664), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021715869696), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307445760), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET_gfx12
    UINT64_C(3288481792), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3760467968), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_gfx80
    UINT64_C(3760463872), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_gfx80
    UINT64_C(3760459776), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_gfx80
    UINT64_C(3760455680), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_gfx80
    UINT64_C(36028800779431936), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_gfx80_TFE_BOTHEN_gfx80
    UINT64_C(36028800779427840), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_gfx80_TFE_IDXEN_gfx80
    UINT64_C(36028800779423744), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_gfx80_TFE_OFFEN_gfx80
    UINT64_C(36028800779419648), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_XY_gfx80_TFE_OFFSET_gfx80
    UINT64_C(3791663104), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx10
    UINT64_C(54043199288639488), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx11
    UINT64_C(3760205824), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx90a
    UINT64_C(3760205824), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_BOTHEN_vi
    UINT64_C(3791659008), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx10
    UINT64_C(36028800779157504), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx11
    UINT64_C(3760201728), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx90a
    UINT64_C(3760201728), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_IDXEN_vi
    UINT64_C(3791654912), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx10
    UINT64_C(18014402269675520), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx11
    UINT64_C(3760197632), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx90a
    UINT64_C(3760197632), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_OFFEN_vi
    UINT64_C(3791650816), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx10
    UINT64_C(3760193536), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx11
    UINT64_C(3760193536), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx90a
    UINT64_C(3760193536), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_OFFSET_vi
    UINT64_C(36028800810627072), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_TFE_BOTHEN_gfx10
    UINT64_C(63050398543380480), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_TFE_BOTHEN_gfx11
    UINT64_C(36028800779169792), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_TFE_BOTHEN_vi
    UINT64_C(36028800810622976), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_TFE_IDXEN_gfx10
    UINT64_C(45036000033898496), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_TFE_IDXEN_gfx11
    UINT64_C(36028800779165696), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_TFE_IDXEN_vi
    UINT64_C(36028800810618880), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_TFE_OFFEN_gfx10
    UINT64_C(27021601524416512), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_TFE_OFFEN_gfx11
    UINT64_C(36028800779161600), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_TFE_OFFEN_vi
    UINT64_C(36028800810614784), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_TFE_OFFSET_gfx10
    UINT64_C(9007203014934528), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_TFE_OFFSET_gfx11
    UINT64_C(36028800779157504), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_TFE_OFFSET_vi
    UINT64_C(13871086855593787392), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058574823424), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166399488), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147435520), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739011584), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720047616), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311623680), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292659712), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589593088), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570629120), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162205184), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143241216), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818734817280), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021715853312), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307429376), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET_gfx12
    UINT64_C(3288465408), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3760205824), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_gfx80
    UINT64_C(3760201728), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_gfx80
    UINT64_C(3760197632), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_gfx80
    UINT64_C(3760193536), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_gfx80
    UINT64_C(36028800779169792), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_gfx80_TFE_BOTHEN_gfx80
    UINT64_C(36028800779165696), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_gfx80_TFE_IDXEN_gfx80
    UINT64_C(36028800779161600), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_gfx80_TFE_OFFEN_gfx80
    UINT64_C(36028800779157504), UINT64_C(0),	// BUFFER_LOAD_FORMAT_D16_X_gfx80_TFE_OFFSET_gfx80
    UINT64_C(3758915584), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_ADDR64_gfx6_gfx7
    UINT64_C(3758895104), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx10
    UINT64_C(54043199287328768), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx11
    UINT64_C(3758895104), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx6_gfx7
    UINT64_C(3758895104), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx90a
    UINT64_C(3758895104), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi
    UINT64_C(3758891008), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx10
    UINT64_C(36028800777846784), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx11
    UINT64_C(3758891008), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx6_gfx7
    UINT64_C(3758891008), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx90a
    UINT64_C(3758891008), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_IDXEN_vi
    UINT64_C(3758886912), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx10
    UINT64_C(18014402268364800), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx11
    UINT64_C(3758886912), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx6_gfx7
    UINT64_C(3758886912), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx90a
    UINT64_C(3758886912), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_OFFEN_vi
    UINT64_C(3758882816), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx10
    UINT64_C(3758882816), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx11
    UINT64_C(3758882816), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx6_gfx7
    UINT64_C(3758882816), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx90a
    UINT64_C(3758882816), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_OFFSET_vi
    UINT64_C(36028800777879552), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800777859072), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_BOTHEN_gfx10
    UINT64_C(63050398542069760), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_BOTHEN_gfx11
    UINT64_C(36028800777859072), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800777859072), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_BOTHEN_vi
    UINT64_C(36028800777854976), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN_gfx10
    UINT64_C(45036000032587776), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN_gfx11
    UINT64_C(36028800777854976), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800777854976), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN_vi
    UINT64_C(36028800777850880), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_OFFEN_gfx10
    UINT64_C(27021601523105792), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_OFFEN_gfx11
    UINT64_C(36028800777850880), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800777850880), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_OFFEN_vi
    UINT64_C(36028800777846784), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_OFFSET_gfx10
    UINT64_C(9007203013623808), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_OFFSET_gfx11
    UINT64_C(36028800777846784), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800777846784), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_OFFSET_vi
    UINT64_C(13871086855593705472), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058574741504), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166317568), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147353600), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818738929664), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021719965696), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311541760), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292577792), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589511168), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570547200), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162123264), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143159296), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818734735360), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021715771392), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307347456), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET_gfx12
    UINT64_C(3288383488), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3758653440), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_ADDR64_gfx6_gfx7
    UINT64_C(3758632960), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx10
    UINT64_C(54043199287066624), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx11
    UINT64_C(3758632960), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx6_gfx7
    UINT64_C(3758632960), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx90a
    UINT64_C(3758632960), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi
    UINT64_C(3758628864), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx10
    UINT64_C(36028800777584640), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx11
    UINT64_C(3758628864), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx6_gfx7
    UINT64_C(3758628864), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx90a
    UINT64_C(3758628864), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_IDXEN_vi
    UINT64_C(3758624768), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx10
    UINT64_C(18014402268102656), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx11
    UINT64_C(3758624768), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx6_gfx7
    UINT64_C(3758624768), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx90a
    UINT64_C(3758624768), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_OFFEN_vi
    UINT64_C(3758620672), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx10
    UINT64_C(3758620672), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx11
    UINT64_C(3758620672), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx6_gfx7
    UINT64_C(3758620672), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx90a
    UINT64_C(3758620672), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_OFFSET_vi
    UINT64_C(36028800777617408), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800777596928), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_BOTHEN_gfx10
    UINT64_C(63050398541807616), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_BOTHEN_gfx11
    UINT64_C(36028800777596928), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800777596928), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_BOTHEN_vi
    UINT64_C(36028800777592832), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN_gfx10
    UINT64_C(45036000032325632), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN_gfx11
    UINT64_C(36028800777592832), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800777592832), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN_vi
    UINT64_C(36028800777588736), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_OFFEN_gfx10
    UINT64_C(27021601522843648), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_OFFEN_gfx11
    UINT64_C(36028800777588736), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800777588736), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_OFFEN_vi
    UINT64_C(36028800777584640), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_OFFSET_gfx10
    UINT64_C(9007203013361664), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_OFFSET_gfx11
    UINT64_C(36028800777584640), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800777584640), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_OFFSET_vi
    UINT64_C(13871086855593689088), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058574725120), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166301184), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147337216), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818738913280), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021719949312), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311525376), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292561408), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589494784), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570530816), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162106880), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143142912), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818734718976), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021715755008), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307331072), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET_gfx12
    UINT64_C(3288367104), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3758391296), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_ADDR64_gfx6_gfx7
    UINT64_C(3758370816), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx10
    UINT64_C(54043199286804480), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx11
    UINT64_C(3758370816), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx6_gfx7
    UINT64_C(3758370816), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx90a
    UINT64_C(3758370816), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_BOTHEN_vi
    UINT64_C(3758366720), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_IDXEN_gfx10
    UINT64_C(36028800777322496), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_IDXEN_gfx11
    UINT64_C(3758366720), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_IDXEN_gfx6_gfx7
    UINT64_C(3758366720), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_IDXEN_gfx90a
    UINT64_C(3758366720), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_IDXEN_vi
    UINT64_C(3758362624), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_OFFEN_gfx10
    UINT64_C(18014402267840512), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_OFFEN_gfx11
    UINT64_C(3758362624), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_OFFEN_gfx6_gfx7
    UINT64_C(3758362624), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_OFFEN_gfx90a
    UINT64_C(3758362624), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_OFFEN_vi
    UINT64_C(3758358528), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_OFFSET_gfx10
    UINT64_C(3758358528), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_OFFSET_gfx11
    UINT64_C(3758358528), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_OFFSET_gfx6_gfx7
    UINT64_C(3758358528), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_OFFSET_gfx90a
    UINT64_C(3758358528), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_OFFSET_vi
    UINT64_C(36028800777355264), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800777334784), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_BOTHEN_gfx10
    UINT64_C(63050398541545472), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_BOTHEN_gfx11
    UINT64_C(36028800777334784), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800777334784), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_BOTHEN_vi
    UINT64_C(36028800777330688), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_IDXEN_gfx10
    UINT64_C(45036000032063488), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_IDXEN_gfx11
    UINT64_C(36028800777330688), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800777330688), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_IDXEN_vi
    UINT64_C(36028800777326592), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_OFFEN_gfx10
    UINT64_C(27021601522581504), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_OFFEN_gfx11
    UINT64_C(36028800777326592), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800777326592), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_OFFEN_vi
    UINT64_C(36028800777322496), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_OFFSET_gfx10
    UINT64_C(9007203013099520), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_OFFSET_gfx11
    UINT64_C(36028800777322496), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800777322496), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_OFFSET_vi
    UINT64_C(13871086855593672704), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058574708736), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166284800), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147320832), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818738896896), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021719932928), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311508992), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292545024), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589478400), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570514432), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162090496), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143126528), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818734702592), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021715738624), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307314688), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET_gfx12
    UINT64_C(3288350720), UINT64_C(0),	// BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3758129152), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_ADDR64_gfx6_gfx7
    UINT64_C(3758108672), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_BOTHEN_gfx10
    UINT64_C(54043199286542336), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_BOTHEN_gfx11
    UINT64_C(3758108672), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_BOTHEN_gfx6_gfx7
    UINT64_C(3758108672), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_BOTHEN_gfx90a
    UINT64_C(3758108672), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_BOTHEN_vi
    UINT64_C(3758104576), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_IDXEN_gfx10
    UINT64_C(36028800777060352), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_IDXEN_gfx11
    UINT64_C(3758104576), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_IDXEN_gfx6_gfx7
    UINT64_C(3758104576), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_IDXEN_gfx90a
    UINT64_C(3758104576), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_IDXEN_vi
    UINT64_C(3758194688), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_LDS_ADDR64_gfx6_gfx7
    UINT64_C(3758174208), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_gfx10
    UINT64_C(3758174208), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_gfx6_gfx7
    UINT64_C(3758174208), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_gfx90a
    UINT64_C(3758174208), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_vi
    UINT64_C(3758170112), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_LDS_IDXEN_gfx10
    UINT64_C(3758170112), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_LDS_IDXEN_gfx6_gfx7
    UINT64_C(3758170112), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_LDS_IDXEN_gfx90a
    UINT64_C(3758170112), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_LDS_IDXEN_vi
    UINT64_C(3758166016), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_LDS_OFFEN_gfx10
    UINT64_C(3758166016), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_LDS_OFFEN_gfx6_gfx7
    UINT64_C(3758166016), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_LDS_OFFEN_gfx90a
    UINT64_C(3758166016), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_LDS_OFFEN_vi
    UINT64_C(3758161920), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_LDS_OFFSET_gfx10
    UINT64_C(3758161920), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_LDS_OFFSET_gfx6_gfx7
    UINT64_C(3758161920), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_LDS_OFFSET_gfx90a
    UINT64_C(3758161920), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_LDS_OFFSET_vi
    UINT64_C(3758100480), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_OFFEN_gfx10
    UINT64_C(18014402267578368), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_OFFEN_gfx11
    UINT64_C(3758100480), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_OFFEN_gfx6_gfx7
    UINT64_C(3758100480), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_OFFEN_gfx90a
    UINT64_C(3758100480), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_OFFEN_vi
    UINT64_C(3758096384), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_OFFSET_gfx10
    UINT64_C(3758096384), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_OFFSET_gfx11
    UINT64_C(3758096384), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_OFFSET_gfx6_gfx7
    UINT64_C(3758096384), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_OFFSET_gfx90a
    UINT64_C(3758096384), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_OFFSET_vi
    UINT64_C(36028800777093120), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800777072640), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_BOTHEN_gfx10
    UINT64_C(63050398541283328), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_BOTHEN_gfx11
    UINT64_C(36028800777072640), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800777072640), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_BOTHEN_vi
    UINT64_C(36028800777068544), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_IDXEN_gfx10
    UINT64_C(45036000031801344), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_IDXEN_gfx11
    UINT64_C(36028800777068544), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800777068544), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_IDXEN_vi
    UINT64_C(36028800777064448), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_OFFEN_gfx10
    UINT64_C(27021601522319360), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_OFFEN_gfx11
    UINT64_C(36028800777064448), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800777064448), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_OFFEN_vi
    UINT64_C(36028800777060352), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_OFFSET_gfx10
    UINT64_C(9007203012837376), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_OFFSET_gfx11
    UINT64_C(36028800777060352), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800777060352), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_OFFSET_vi
    UINT64_C(13871086855593656320), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058574692352), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166268416), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147304448), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818738880512), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021719916544), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311492608), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292528640), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589462016), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570498048), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162074112), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143110144), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818734686208), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021715722240), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307298304), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET_gfx12
    UINT64_C(3288334336), UINT64_C(0),	// BUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3760488448), UINT64_C(0),	// BUFFER_LOAD_SBYTE_ADDR64_gfx6_gfx7
    UINT64_C(3760467968), UINT64_C(0),	// BUFFER_LOAD_SBYTE_BOTHEN_gfx10
    UINT64_C(54043199290998784), UINT64_C(0),	// BUFFER_LOAD_SBYTE_BOTHEN_gfx11
    UINT64_C(3760467968), UINT64_C(0),	// BUFFER_LOAD_SBYTE_BOTHEN_gfx6_gfx7
    UINT64_C(3762565120), UINT64_C(0),	// BUFFER_LOAD_SBYTE_BOTHEN_gfx90a
    UINT64_C(3762565120), UINT64_C(0),	// BUFFER_LOAD_SBYTE_BOTHEN_vi
    UINT64_C(3767021568), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_BOTHEN_gfx10
    UINT64_C(54043199294668800), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_BOTHEN_gfx11
    UINT64_C(3767021568), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_BOTHEN_gfx90a
    UINT64_C(3767021568), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_BOTHEN_vi
    UINT64_C(3767283712), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_gfx10
    UINT64_C(54043199295455232), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_gfx11
    UINT64_C(3767283712), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_gfx90a
    UINT64_C(3767283712), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_vi
    UINT64_C(3767279616), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_IDXEN_gfx10
    UINT64_C(36028800785973248), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_IDXEN_gfx11
    UINT64_C(3767279616), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_IDXEN_gfx90a
    UINT64_C(3767279616), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_IDXEN_vi
    UINT64_C(3767275520), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_OFFEN_gfx10
    UINT64_C(18014402276491264), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_OFFEN_gfx11
    UINT64_C(3767275520), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_OFFEN_gfx90a
    UINT64_C(3767275520), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_OFFEN_vi
    UINT64_C(3767271424), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_OFFSET_gfx10
    UINT64_C(3767009280), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_OFFSET_gfx11
    UINT64_C(3767271424), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_OFFSET_gfx90a
    UINT64_C(3767271424), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_OFFSET_vi
    UINT64_C(36028800786247680), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_TFE_BOTHEN_gfx10
    UINT64_C(63050398550196224), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_TFE_BOTHEN_gfx11
    UINT64_C(36028800786247680), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_TFE_BOTHEN_vi
    UINT64_C(36028800786243584), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_TFE_IDXEN_gfx10
    UINT64_C(45036000040714240), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_TFE_IDXEN_gfx11
    UINT64_C(36028800786243584), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_TFE_IDXEN_vi
    UINT64_C(36028800786239488), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_TFE_OFFEN_gfx10
    UINT64_C(27021601531232256), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_TFE_OFFEN_gfx11
    UINT64_C(36028800786239488), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_TFE_OFFEN_vi
    UINT64_C(36028800786235392), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_TFE_OFFSET_gfx10
    UINT64_C(9007203021750272), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_TFE_OFFSET_gfx11
    UINT64_C(36028800786235392), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_TFE_OFFSET_vi
    UINT64_C(13871086855594213376), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575249408), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166825472), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147861504), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739437568), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720473600), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800312049664), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3293085696), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855590019072), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571055104), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162631168), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143667200), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818735243264), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716279296), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307855360), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_OFFSET_gfx12
    UINT64_C(3288891392), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3767017472), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_IDXEN_gfx10
    UINT64_C(36028800785186816), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_IDXEN_gfx11
    UINT64_C(3767017472), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_IDXEN_gfx90a
    UINT64_C(3767017472), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_IDXEN_vi
    UINT64_C(3767013376), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_OFFEN_gfx10
    UINT64_C(18014402275704832), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_OFFEN_gfx11
    UINT64_C(3767013376), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_OFFEN_gfx90a
    UINT64_C(3767013376), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_OFFEN_vi
    UINT64_C(3767009280), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_OFFSET_gfx10
    UINT64_C(3766222848), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_OFFSET_gfx11
    UINT64_C(3767009280), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_OFFSET_gfx90a
    UINT64_C(3767009280), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_OFFSET_vi
    UINT64_C(36028800785985536), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_TFE_BOTHEN_gfx10
    UINT64_C(63050398549409792), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_TFE_BOTHEN_gfx11
    UINT64_C(36028800785985536), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_TFE_BOTHEN_vi
    UINT64_C(36028800785981440), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_TFE_IDXEN_gfx10
    UINT64_C(45036000039927808), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_TFE_IDXEN_gfx11
    UINT64_C(36028800785981440), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_TFE_IDXEN_vi
    UINT64_C(36028800785977344), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_TFE_OFFEN_gfx10
    UINT64_C(27021601530445824), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_TFE_OFFEN_gfx11
    UINT64_C(36028800785977344), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_TFE_OFFEN_vi
    UINT64_C(36028800785973248), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_TFE_OFFSET_gfx10
    UINT64_C(9007203020963840), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_TFE_OFFSET_gfx11
    UINT64_C(36028800785973248), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_TFE_OFFSET_vi
    UINT64_C(13871086855594164224), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575200256), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166776320), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147812352), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739388416), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720424448), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800312000512), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3293036544), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589969920), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571005952), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162582016), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143618048), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818735194112), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716230144), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307806208), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_VBUFFER_OFFSET_gfx12
    UINT64_C(3288842240), UINT64_C(0),	// BUFFER_LOAD_SBYTE_D16_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3760463872), UINT64_C(0),	// BUFFER_LOAD_SBYTE_IDXEN_gfx10
    UINT64_C(36028800781516800), UINT64_C(0),	// BUFFER_LOAD_SBYTE_IDXEN_gfx11
    UINT64_C(3760463872), UINT64_C(0),	// BUFFER_LOAD_SBYTE_IDXEN_gfx6_gfx7
    UINT64_C(3762561024), UINT64_C(0),	// BUFFER_LOAD_SBYTE_IDXEN_gfx90a
    UINT64_C(3762561024), UINT64_C(0),	// BUFFER_LOAD_SBYTE_IDXEN_vi
    UINT64_C(3760553984), UINT64_C(0),	// BUFFER_LOAD_SBYTE_LDS_ADDR64_gfx6_gfx7
    UINT64_C(3760533504), UINT64_C(0),	// BUFFER_LOAD_SBYTE_LDS_BOTHEN_gfx10
    UINT64_C(3760533504), UINT64_C(0),	// BUFFER_LOAD_SBYTE_LDS_BOTHEN_gfx6_gfx7
    UINT64_C(3762630656), UINT64_C(0),	// BUFFER_LOAD_SBYTE_LDS_BOTHEN_gfx90a
    UINT64_C(3762630656), UINT64_C(0),	// BUFFER_LOAD_SBYTE_LDS_BOTHEN_vi
    UINT64_C(3760529408), UINT64_C(0),	// BUFFER_LOAD_SBYTE_LDS_IDXEN_gfx10
    UINT64_C(3760529408), UINT64_C(0),	// BUFFER_LOAD_SBYTE_LDS_IDXEN_gfx6_gfx7
    UINT64_C(3762626560), UINT64_C(0),	// BUFFER_LOAD_SBYTE_LDS_IDXEN_gfx90a
    UINT64_C(3762626560), UINT64_C(0),	// BUFFER_LOAD_SBYTE_LDS_IDXEN_vi
    UINT64_C(3760525312), UINT64_C(0),	// BUFFER_LOAD_SBYTE_LDS_OFFEN_gfx10
    UINT64_C(3760525312), UINT64_C(0),	// BUFFER_LOAD_SBYTE_LDS_OFFEN_gfx6_gfx7
    UINT64_C(3762622464), UINT64_C(0),	// BUFFER_LOAD_SBYTE_LDS_OFFEN_gfx90a
    UINT64_C(3762622464), UINT64_C(0),	// BUFFER_LOAD_SBYTE_LDS_OFFEN_vi
    UINT64_C(3760521216), UINT64_C(0),	// BUFFER_LOAD_SBYTE_LDS_OFFSET_gfx10
    UINT64_C(3760521216), UINT64_C(0),	// BUFFER_LOAD_SBYTE_LDS_OFFSET_gfx6_gfx7
    UINT64_C(3762618368), UINT64_C(0),	// BUFFER_LOAD_SBYTE_LDS_OFFSET_gfx90a
    UINT64_C(3762618368), UINT64_C(0),	// BUFFER_LOAD_SBYTE_LDS_OFFSET_vi
    UINT64_C(3760459776), UINT64_C(0),	// BUFFER_LOAD_SBYTE_OFFEN_gfx10
    UINT64_C(18014402272034816), UINT64_C(0),	// BUFFER_LOAD_SBYTE_OFFEN_gfx11
    UINT64_C(3760459776), UINT64_C(0),	// BUFFER_LOAD_SBYTE_OFFEN_gfx6_gfx7
    UINT64_C(3762556928), UINT64_C(0),	// BUFFER_LOAD_SBYTE_OFFEN_gfx90a
    UINT64_C(3762556928), UINT64_C(0),	// BUFFER_LOAD_SBYTE_OFFEN_vi
    UINT64_C(3760455680), UINT64_C(0),	// BUFFER_LOAD_SBYTE_OFFSET_gfx10
    UINT64_C(3762552832), UINT64_C(0),	// BUFFER_LOAD_SBYTE_OFFSET_gfx11
    UINT64_C(3760455680), UINT64_C(0),	// BUFFER_LOAD_SBYTE_OFFSET_gfx6_gfx7
    UINT64_C(3762552832), UINT64_C(0),	// BUFFER_LOAD_SBYTE_OFFSET_gfx90a
    UINT64_C(3762552832), UINT64_C(0),	// BUFFER_LOAD_SBYTE_OFFSET_vi
    UINT64_C(36028800779452416), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800779431936), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_BOTHEN_gfx10
    UINT64_C(63050398545739776), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_BOTHEN_gfx11
    UINT64_C(36028800779431936), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800781529088), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_BOTHEN_vi
    UINT64_C(36028800779427840), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_IDXEN_gfx10
    UINT64_C(45036000036257792), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_IDXEN_gfx11
    UINT64_C(36028800779427840), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800781524992), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_IDXEN_vi
    UINT64_C(36028800779423744), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_OFFEN_gfx10
    UINT64_C(27021601526775808), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_OFFEN_gfx11
    UINT64_C(36028800779423744), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800781520896), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_OFFEN_vi
    UINT64_C(36028800779419648), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_OFFSET_gfx10
    UINT64_C(9007203017293824), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_OFFSET_gfx11
    UINT64_C(36028800779419648), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800781516800), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_OFFSET_vi
    UINT64_C(13871086855593934848), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058574970880), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166546944), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147582976), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739159040), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720195072), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311771136), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292807168), UINT64_C(0),	// BUFFER_LOAD_SBYTE_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589740544), UINT64_C(0),	// BUFFER_LOAD_SBYTE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570776576), UINT64_C(0),	// BUFFER_LOAD_SBYTE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162352640), UINT64_C(0),	// BUFFER_LOAD_SBYTE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143388672), UINT64_C(0),	// BUFFER_LOAD_SBYTE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818734964736), UINT64_C(0),	// BUFFER_LOAD_SBYTE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716000768), UINT64_C(0),	// BUFFER_LOAD_SBYTE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307576832), UINT64_C(0),	// BUFFER_LOAD_SBYTE_VBUFFER_OFFSET_gfx12
    UINT64_C(3288612864), UINT64_C(0),	// BUFFER_LOAD_SBYTE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3767545856), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_BOTHEN_gfx10
    UINT64_C(54043199294930944), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_BOTHEN_gfx11
    UINT64_C(3767545856), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_BOTHEN_gfx90a
    UINT64_C(3767545856), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_BOTHEN_vi
    UINT64_C(3767808000), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_BOTHEN_gfx10
    UINT64_C(54043199295717376), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_BOTHEN_gfx11
    UINT64_C(3767808000), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_BOTHEN_gfx90a
    UINT64_C(3767808000), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_BOTHEN_vi
    UINT64_C(3767803904), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_IDXEN_gfx10
    UINT64_C(36028800786235392), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_IDXEN_gfx11
    UINT64_C(3767803904), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_IDXEN_gfx90a
    UINT64_C(3767803904), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_IDXEN_vi
    UINT64_C(3767799808), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_OFFEN_gfx10
    UINT64_C(18014402276753408), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_OFFEN_gfx11
    UINT64_C(3767799808), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_OFFEN_gfx90a
    UINT64_C(3767799808), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_OFFEN_vi
    UINT64_C(3767795712), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_OFFSET_gfx10
    UINT64_C(3767271424), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_OFFSET_gfx11
    UINT64_C(3767795712), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_OFFSET_gfx90a
    UINT64_C(3767795712), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_OFFSET_vi
    UINT64_C(36028800786771968), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_TFE_BOTHEN_gfx10
    UINT64_C(63050398550458368), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_TFE_BOTHEN_gfx11
    UINT64_C(36028800786771968), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_TFE_BOTHEN_vi
    UINT64_C(36028800786767872), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_TFE_IDXEN_gfx10
    UINT64_C(45036000040976384), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_TFE_IDXEN_gfx11
    UINT64_C(36028800786767872), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_TFE_IDXEN_vi
    UINT64_C(36028800786763776), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_TFE_OFFEN_gfx10
    UINT64_C(27021601531494400), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_TFE_OFFEN_gfx11
    UINT64_C(36028800786763776), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_TFE_OFFEN_vi
    UINT64_C(36028800786759680), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_TFE_OFFSET_gfx10
    UINT64_C(9007203022012416), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_TFE_OFFSET_gfx11
    UINT64_C(36028800786759680), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_TFE_OFFSET_vi
    UINT64_C(13871086855594229760), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575265792), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166841856), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147877888), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739453952), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720489984), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800312066048), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3293102080), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855590035456), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571071488), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162647552), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143683584), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818735259648), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716295680), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307871744), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_VBUFFER_OFFSET_gfx12
    UINT64_C(3288907776), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_HI_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3767541760), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_IDXEN_gfx10
    UINT64_C(36028800785448960), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_IDXEN_gfx11
    UINT64_C(3767541760), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_IDXEN_gfx90a
    UINT64_C(3767541760), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_IDXEN_vi
    UINT64_C(3767537664), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_OFFEN_gfx10
    UINT64_C(18014402275966976), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_OFFEN_gfx11
    UINT64_C(3767537664), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_OFFEN_gfx90a
    UINT64_C(3767537664), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_OFFEN_vi
    UINT64_C(3767533568), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_OFFSET_gfx10
    UINT64_C(3766484992), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_OFFSET_gfx11
    UINT64_C(3767533568), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_OFFSET_gfx90a
    UINT64_C(3767533568), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_OFFSET_vi
    UINT64_C(36028800786509824), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_TFE_BOTHEN_gfx10
    UINT64_C(63050398549671936), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_TFE_BOTHEN_gfx11
    UINT64_C(36028800786509824), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_TFE_BOTHEN_vi
    UINT64_C(36028800786505728), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_TFE_IDXEN_gfx10
    UINT64_C(45036000040189952), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_TFE_IDXEN_gfx11
    UINT64_C(36028800786505728), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_TFE_IDXEN_vi
    UINT64_C(36028800786501632), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_TFE_OFFEN_gfx10
    UINT64_C(27021601530707968), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_TFE_OFFEN_gfx11
    UINT64_C(36028800786501632), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_TFE_OFFEN_vi
    UINT64_C(36028800786497536), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_TFE_OFFSET_gfx10
    UINT64_C(9007203021225984), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_TFE_OFFSET_gfx11
    UINT64_C(36028800786497536), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_TFE_OFFSET_vi
    UINT64_C(13871086855594180608), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575216640), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166792704), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147828736), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739404800), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720440832), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800312016896), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3293052928), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589986304), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571022336), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162598400), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143634432), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818735210496), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716246528), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307822592), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_VBUFFER_OFFSET_gfx12
    UINT64_C(3288858624), UINT64_C(0),	// BUFFER_LOAD_SHORT_D16_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3761012736), UINT64_C(0),	// BUFFER_LOAD_SSHORT_ADDR64_gfx6_gfx7
    UINT64_C(3760992256), UINT64_C(0),	// BUFFER_LOAD_SSHORT_BOTHEN_gfx10
    UINT64_C(54043199291523072), UINT64_C(0),	// BUFFER_LOAD_SSHORT_BOTHEN_gfx11
    UINT64_C(3760992256), UINT64_C(0),	// BUFFER_LOAD_SSHORT_BOTHEN_gfx6_gfx7
    UINT64_C(3763089408), UINT64_C(0),	// BUFFER_LOAD_SSHORT_BOTHEN_gfx90a
    UINT64_C(3763089408), UINT64_C(0),	// BUFFER_LOAD_SSHORT_BOTHEN_vi
    UINT64_C(3760988160), UINT64_C(0),	// BUFFER_LOAD_SSHORT_IDXEN_gfx10
    UINT64_C(36028800782041088), UINT64_C(0),	// BUFFER_LOAD_SSHORT_IDXEN_gfx11
    UINT64_C(3760988160), UINT64_C(0),	// BUFFER_LOAD_SSHORT_IDXEN_gfx6_gfx7
    UINT64_C(3763085312), UINT64_C(0),	// BUFFER_LOAD_SSHORT_IDXEN_gfx90a
    UINT64_C(3763085312), UINT64_C(0),	// BUFFER_LOAD_SSHORT_IDXEN_vi
    UINT64_C(3761078272), UINT64_C(0),	// BUFFER_LOAD_SSHORT_LDS_ADDR64_gfx6_gfx7
    UINT64_C(3761057792), UINT64_C(0),	// BUFFER_LOAD_SSHORT_LDS_BOTHEN_gfx10
    UINT64_C(3761057792), UINT64_C(0),	// BUFFER_LOAD_SSHORT_LDS_BOTHEN_gfx6_gfx7
    UINT64_C(3763154944), UINT64_C(0),	// BUFFER_LOAD_SSHORT_LDS_BOTHEN_gfx90a
    UINT64_C(3763154944), UINT64_C(0),	// BUFFER_LOAD_SSHORT_LDS_BOTHEN_vi
    UINT64_C(3761053696), UINT64_C(0),	// BUFFER_LOAD_SSHORT_LDS_IDXEN_gfx10
    UINT64_C(3761053696), UINT64_C(0),	// BUFFER_LOAD_SSHORT_LDS_IDXEN_gfx6_gfx7
    UINT64_C(3763150848), UINT64_C(0),	// BUFFER_LOAD_SSHORT_LDS_IDXEN_gfx90a
    UINT64_C(3763150848), UINT64_C(0),	// BUFFER_LOAD_SSHORT_LDS_IDXEN_vi
    UINT64_C(3761049600), UINT64_C(0),	// BUFFER_LOAD_SSHORT_LDS_OFFEN_gfx10
    UINT64_C(3761049600), UINT64_C(0),	// BUFFER_LOAD_SSHORT_LDS_OFFEN_gfx6_gfx7
    UINT64_C(3763146752), UINT64_C(0),	// BUFFER_LOAD_SSHORT_LDS_OFFEN_gfx90a
    UINT64_C(3763146752), UINT64_C(0),	// BUFFER_LOAD_SSHORT_LDS_OFFEN_vi
    UINT64_C(3761045504), UINT64_C(0),	// BUFFER_LOAD_SSHORT_LDS_OFFSET_gfx10
    UINT64_C(3761045504), UINT64_C(0),	// BUFFER_LOAD_SSHORT_LDS_OFFSET_gfx6_gfx7
    UINT64_C(3763142656), UINT64_C(0),	// BUFFER_LOAD_SSHORT_LDS_OFFSET_gfx90a
    UINT64_C(3763142656), UINT64_C(0),	// BUFFER_LOAD_SSHORT_LDS_OFFSET_vi
    UINT64_C(3760984064), UINT64_C(0),	// BUFFER_LOAD_SSHORT_OFFEN_gfx10
    UINT64_C(18014402272559104), UINT64_C(0),	// BUFFER_LOAD_SSHORT_OFFEN_gfx11
    UINT64_C(3760984064), UINT64_C(0),	// BUFFER_LOAD_SSHORT_OFFEN_gfx6_gfx7
    UINT64_C(3763081216), UINT64_C(0),	// BUFFER_LOAD_SSHORT_OFFEN_gfx90a
    UINT64_C(3763081216), UINT64_C(0),	// BUFFER_LOAD_SSHORT_OFFEN_vi
    UINT64_C(3760979968), UINT64_C(0),	// BUFFER_LOAD_SSHORT_OFFSET_gfx10
    UINT64_C(3763077120), UINT64_C(0),	// BUFFER_LOAD_SSHORT_OFFSET_gfx11
    UINT64_C(3760979968), UINT64_C(0),	// BUFFER_LOAD_SSHORT_OFFSET_gfx6_gfx7
    UINT64_C(3763077120), UINT64_C(0),	// BUFFER_LOAD_SSHORT_OFFSET_gfx90a
    UINT64_C(3763077120), UINT64_C(0),	// BUFFER_LOAD_SSHORT_OFFSET_vi
    UINT64_C(36028800779976704), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800779956224), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_BOTHEN_gfx10
    UINT64_C(63050398546264064), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_BOTHEN_gfx11
    UINT64_C(36028800779956224), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800782053376), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_BOTHEN_vi
    UINT64_C(36028800779952128), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_IDXEN_gfx10
    UINT64_C(45036000036782080), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_IDXEN_gfx11
    UINT64_C(36028800779952128), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800782049280), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_IDXEN_vi
    UINT64_C(36028800779948032), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_OFFEN_gfx10
    UINT64_C(27021601527300096), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_OFFEN_gfx11
    UINT64_C(36028800779948032), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800782045184), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_OFFEN_vi
    UINT64_C(36028800779943936), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_OFFSET_gfx10
    UINT64_C(9007203017818112), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_OFFSET_gfx11
    UINT64_C(36028800779943936), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800782041088), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_OFFSET_vi
    UINT64_C(13871086855593967616), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575003648), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166579712), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147615744), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739191808), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720227840), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311803904), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292839936), UINT64_C(0),	// BUFFER_LOAD_SSHORT_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589773312), UINT64_C(0),	// BUFFER_LOAD_SSHORT_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570809344), UINT64_C(0),	// BUFFER_LOAD_SSHORT_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162385408), UINT64_C(0),	// BUFFER_LOAD_SSHORT_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143421440), UINT64_C(0),	// BUFFER_LOAD_SSHORT_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818734997504), UINT64_C(0),	// BUFFER_LOAD_SSHORT_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716033536), UINT64_C(0),	// BUFFER_LOAD_SSHORT_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307609600), UINT64_C(0),	// BUFFER_LOAD_SSHORT_VBUFFER_OFFSET_gfx12
    UINT64_C(3288645632), UINT64_C(0),	// BUFFER_LOAD_SSHORT_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3760226304), UINT64_C(0),	// BUFFER_LOAD_UBYTE_ADDR64_gfx6_gfx7
    UINT64_C(3760205824), UINT64_C(0),	// BUFFER_LOAD_UBYTE_BOTHEN_gfx10
    UINT64_C(54043199290736640), UINT64_C(0),	// BUFFER_LOAD_UBYTE_BOTHEN_gfx11
    UINT64_C(3760205824), UINT64_C(0),	// BUFFER_LOAD_UBYTE_BOTHEN_gfx6_gfx7
    UINT64_C(3762302976), UINT64_C(0),	// BUFFER_LOAD_UBYTE_BOTHEN_gfx90a
    UINT64_C(3762302976), UINT64_C(0),	// BUFFER_LOAD_UBYTE_BOTHEN_vi
    UINT64_C(3766497280), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_BOTHEN_gfx10
    UINT64_C(54043199294406656), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_BOTHEN_gfx11
    UINT64_C(3766497280), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_BOTHEN_gfx90a
    UINT64_C(3766497280), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_BOTHEN_vi
    UINT64_C(3766759424), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_gfx10
    UINT64_C(54043199295193088), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_gfx11
    UINT64_C(3766759424), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_gfx90a
    UINT64_C(3766759424), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_vi
    UINT64_C(3766755328), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_IDXEN_gfx10
    UINT64_C(36028800785711104), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_IDXEN_gfx11
    UINT64_C(3766755328), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_IDXEN_gfx90a
    UINT64_C(3766755328), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_IDXEN_vi
    UINT64_C(3766751232), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_OFFEN_gfx10
    UINT64_C(18014402276229120), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_OFFEN_gfx11
    UINT64_C(3766751232), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_OFFEN_gfx90a
    UINT64_C(3766751232), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_OFFEN_vi
    UINT64_C(3766747136), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_OFFSET_gfx10
    UINT64_C(3766747136), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_OFFSET_gfx11
    UINT64_C(3766747136), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_OFFSET_gfx90a
    UINT64_C(3766747136), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_OFFSET_vi
    UINT64_C(36028800785723392), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_TFE_BOTHEN_gfx10
    UINT64_C(63050398549934080), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_TFE_BOTHEN_gfx11
    UINT64_C(36028800785723392), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_TFE_BOTHEN_vi
    UINT64_C(36028800785719296), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_TFE_IDXEN_gfx10
    UINT64_C(45036000040452096), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_TFE_IDXEN_gfx11
    UINT64_C(36028800785719296), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_TFE_IDXEN_vi
    UINT64_C(36028800785715200), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_TFE_OFFEN_gfx10
    UINT64_C(27021601530970112), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_TFE_OFFEN_gfx11
    UINT64_C(36028800785715200), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_TFE_OFFEN_vi
    UINT64_C(36028800785711104), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_TFE_OFFSET_gfx10
    UINT64_C(9007203021488128), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_TFE_OFFSET_gfx11
    UINT64_C(36028800785711104), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_TFE_OFFSET_vi
    UINT64_C(13871086855594196992), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575233024), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166809088), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147845120), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739421184), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720457216), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800312033280), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3293069312), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855590002688), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571038720), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162614784), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143650816), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818735226880), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716262912), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307838976), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_OFFSET_gfx12
    UINT64_C(3288875008), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3766493184), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_IDXEN_gfx10
    UINT64_C(36028800784924672), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_IDXEN_gfx11
    UINT64_C(3766493184), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_IDXEN_gfx90a
    UINT64_C(3766493184), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_IDXEN_vi
    UINT64_C(3766489088), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_OFFEN_gfx10
    UINT64_C(18014402275442688), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_OFFEN_gfx11
    UINT64_C(3766489088), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_OFFEN_gfx90a
    UINT64_C(3766489088), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_OFFEN_vi
    UINT64_C(3766484992), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_OFFSET_gfx10
    UINT64_C(3765960704), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_OFFSET_gfx11
    UINT64_C(3766484992), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_OFFSET_gfx90a
    UINT64_C(3766484992), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_OFFSET_vi
    UINT64_C(36028800785461248), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_TFE_BOTHEN_gfx10
    UINT64_C(63050398549147648), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_TFE_BOTHEN_gfx11
    UINT64_C(36028800785461248), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_TFE_BOTHEN_vi
    UINT64_C(36028800785457152), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_TFE_IDXEN_gfx10
    UINT64_C(45036000039665664), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_TFE_IDXEN_gfx11
    UINT64_C(36028800785457152), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_TFE_IDXEN_vi
    UINT64_C(36028800785453056), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_TFE_OFFEN_gfx10
    UINT64_C(27021601530183680), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_TFE_OFFEN_gfx11
    UINT64_C(36028800785453056), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_TFE_OFFEN_vi
    UINT64_C(36028800785448960), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_TFE_OFFSET_gfx10
    UINT64_C(9007203020701696), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_TFE_OFFSET_gfx11
    UINT64_C(36028800785448960), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_TFE_OFFSET_vi
    UINT64_C(13871086855594147840), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575183872), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166759936), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147795968), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739372032), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720408064), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311984128), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3293020160), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589953536), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570989568), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162565632), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143601664), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818735177728), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716213760), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307789824), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_VBUFFER_OFFSET_gfx12
    UINT64_C(3288825856), UINT64_C(0),	// BUFFER_LOAD_UBYTE_D16_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3760201728), UINT64_C(0),	// BUFFER_LOAD_UBYTE_IDXEN_gfx10
    UINT64_C(36028800781254656), UINT64_C(0),	// BUFFER_LOAD_UBYTE_IDXEN_gfx11
    UINT64_C(3760201728), UINT64_C(0),	// BUFFER_LOAD_UBYTE_IDXEN_gfx6_gfx7
    UINT64_C(3762298880), UINT64_C(0),	// BUFFER_LOAD_UBYTE_IDXEN_gfx90a
    UINT64_C(3762298880), UINT64_C(0),	// BUFFER_LOAD_UBYTE_IDXEN_vi
    UINT64_C(3760291840), UINT64_C(0),	// BUFFER_LOAD_UBYTE_LDS_ADDR64_gfx6_gfx7
    UINT64_C(3760271360), UINT64_C(0),	// BUFFER_LOAD_UBYTE_LDS_BOTHEN_gfx10
    UINT64_C(3760271360), UINT64_C(0),	// BUFFER_LOAD_UBYTE_LDS_BOTHEN_gfx6_gfx7
    UINT64_C(3762368512), UINT64_C(0),	// BUFFER_LOAD_UBYTE_LDS_BOTHEN_gfx90a
    UINT64_C(3762368512), UINT64_C(0),	// BUFFER_LOAD_UBYTE_LDS_BOTHEN_vi
    UINT64_C(3760267264), UINT64_C(0),	// BUFFER_LOAD_UBYTE_LDS_IDXEN_gfx10
    UINT64_C(3760267264), UINT64_C(0),	// BUFFER_LOAD_UBYTE_LDS_IDXEN_gfx6_gfx7
    UINT64_C(3762364416), UINT64_C(0),	// BUFFER_LOAD_UBYTE_LDS_IDXEN_gfx90a
    UINT64_C(3762364416), UINT64_C(0),	// BUFFER_LOAD_UBYTE_LDS_IDXEN_vi
    UINT64_C(3760263168), UINT64_C(0),	// BUFFER_LOAD_UBYTE_LDS_OFFEN_gfx10
    UINT64_C(3760263168), UINT64_C(0),	// BUFFER_LOAD_UBYTE_LDS_OFFEN_gfx6_gfx7
    UINT64_C(3762360320), UINT64_C(0),	// BUFFER_LOAD_UBYTE_LDS_OFFEN_gfx90a
    UINT64_C(3762360320), UINT64_C(0),	// BUFFER_LOAD_UBYTE_LDS_OFFEN_vi
    UINT64_C(3760259072), UINT64_C(0),	// BUFFER_LOAD_UBYTE_LDS_OFFSET_gfx10
    UINT64_C(3760259072), UINT64_C(0),	// BUFFER_LOAD_UBYTE_LDS_OFFSET_gfx6_gfx7
    UINT64_C(3762356224), UINT64_C(0),	// BUFFER_LOAD_UBYTE_LDS_OFFSET_gfx90a
    UINT64_C(3762356224), UINT64_C(0),	// BUFFER_LOAD_UBYTE_LDS_OFFSET_vi
    UINT64_C(3760197632), UINT64_C(0),	// BUFFER_LOAD_UBYTE_OFFEN_gfx10
    UINT64_C(18014402271772672), UINT64_C(0),	// BUFFER_LOAD_UBYTE_OFFEN_gfx11
    UINT64_C(3760197632), UINT64_C(0),	// BUFFER_LOAD_UBYTE_OFFEN_gfx6_gfx7
    UINT64_C(3762294784), UINT64_C(0),	// BUFFER_LOAD_UBYTE_OFFEN_gfx90a
    UINT64_C(3762294784), UINT64_C(0),	// BUFFER_LOAD_UBYTE_OFFEN_vi
    UINT64_C(3760193536), UINT64_C(0),	// BUFFER_LOAD_UBYTE_OFFSET_gfx10
    UINT64_C(3762290688), UINT64_C(0),	// BUFFER_LOAD_UBYTE_OFFSET_gfx11
    UINT64_C(3760193536), UINT64_C(0),	// BUFFER_LOAD_UBYTE_OFFSET_gfx6_gfx7
    UINT64_C(3762290688), UINT64_C(0),	// BUFFER_LOAD_UBYTE_OFFSET_gfx90a
    UINT64_C(3762290688), UINT64_C(0),	// BUFFER_LOAD_UBYTE_OFFSET_vi
    UINT64_C(36028800779190272), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800779169792), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_BOTHEN_gfx10
    UINT64_C(63050398545477632), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_BOTHEN_gfx11
    UINT64_C(36028800779169792), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800781266944), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_BOTHEN_vi
    UINT64_C(36028800779165696), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_IDXEN_gfx10
    UINT64_C(45036000035995648), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_IDXEN_gfx11
    UINT64_C(36028800779165696), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800781262848), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_IDXEN_vi
    UINT64_C(36028800779161600), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_OFFEN_gfx10
    UINT64_C(27021601526513664), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_OFFEN_gfx11
    UINT64_C(36028800779161600), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800781258752), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_OFFEN_vi
    UINT64_C(36028800779157504), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_OFFSET_gfx10
    UINT64_C(9007203017031680), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_OFFSET_gfx11
    UINT64_C(36028800779157504), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800781254656), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_OFFSET_vi
    UINT64_C(13871086855593918464), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058574954496), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166530560), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147566592), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739142656), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720178688), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311754752), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292790784), UINT64_C(0),	// BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589724160), UINT64_C(0),	// BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570760192), UINT64_C(0),	// BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162336256), UINT64_C(0),	// BUFFER_LOAD_UBYTE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143372288), UINT64_C(0),	// BUFFER_LOAD_UBYTE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818734948352), UINT64_C(0),	// BUFFER_LOAD_UBYTE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021715984384), UINT64_C(0),	// BUFFER_LOAD_UBYTE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307560448), UINT64_C(0),	// BUFFER_LOAD_UBYTE_VBUFFER_OFFSET_gfx12
    UINT64_C(3288596480), UINT64_C(0),	// BUFFER_LOAD_UBYTE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3760750592), UINT64_C(0),	// BUFFER_LOAD_USHORT_ADDR64_gfx6_gfx7
    UINT64_C(3760730112), UINT64_C(0),	// BUFFER_LOAD_USHORT_BOTHEN_gfx10
    UINT64_C(54043199291260928), UINT64_C(0),	// BUFFER_LOAD_USHORT_BOTHEN_gfx11
    UINT64_C(3760730112), UINT64_C(0),	// BUFFER_LOAD_USHORT_BOTHEN_gfx6_gfx7
    UINT64_C(3762827264), UINT64_C(0),	// BUFFER_LOAD_USHORT_BOTHEN_gfx90a
    UINT64_C(3762827264), UINT64_C(0),	// BUFFER_LOAD_USHORT_BOTHEN_vi
    UINT64_C(3760726016), UINT64_C(0),	// BUFFER_LOAD_USHORT_IDXEN_gfx10
    UINT64_C(36028800781778944), UINT64_C(0),	// BUFFER_LOAD_USHORT_IDXEN_gfx11
    UINT64_C(3760726016), UINT64_C(0),	// BUFFER_LOAD_USHORT_IDXEN_gfx6_gfx7
    UINT64_C(3762823168), UINT64_C(0),	// BUFFER_LOAD_USHORT_IDXEN_gfx90a
    UINT64_C(3762823168), UINT64_C(0),	// BUFFER_LOAD_USHORT_IDXEN_vi
    UINT64_C(3760816128), UINT64_C(0),	// BUFFER_LOAD_USHORT_LDS_ADDR64_gfx6_gfx7
    UINT64_C(3760795648), UINT64_C(0),	// BUFFER_LOAD_USHORT_LDS_BOTHEN_gfx10
    UINT64_C(3760795648), UINT64_C(0),	// BUFFER_LOAD_USHORT_LDS_BOTHEN_gfx6_gfx7
    UINT64_C(3762892800), UINT64_C(0),	// BUFFER_LOAD_USHORT_LDS_BOTHEN_gfx90a
    UINT64_C(3762892800), UINT64_C(0),	// BUFFER_LOAD_USHORT_LDS_BOTHEN_vi
    UINT64_C(3760791552), UINT64_C(0),	// BUFFER_LOAD_USHORT_LDS_IDXEN_gfx10
    UINT64_C(3760791552), UINT64_C(0),	// BUFFER_LOAD_USHORT_LDS_IDXEN_gfx6_gfx7
    UINT64_C(3762888704), UINT64_C(0),	// BUFFER_LOAD_USHORT_LDS_IDXEN_gfx90a
    UINT64_C(3762888704), UINT64_C(0),	// BUFFER_LOAD_USHORT_LDS_IDXEN_vi
    UINT64_C(3760787456), UINT64_C(0),	// BUFFER_LOAD_USHORT_LDS_OFFEN_gfx10
    UINT64_C(3760787456), UINT64_C(0),	// BUFFER_LOAD_USHORT_LDS_OFFEN_gfx6_gfx7
    UINT64_C(3762884608), UINT64_C(0),	// BUFFER_LOAD_USHORT_LDS_OFFEN_gfx90a
    UINT64_C(3762884608), UINT64_C(0),	// BUFFER_LOAD_USHORT_LDS_OFFEN_vi
    UINT64_C(3760783360), UINT64_C(0),	// BUFFER_LOAD_USHORT_LDS_OFFSET_gfx10
    UINT64_C(3760783360), UINT64_C(0),	// BUFFER_LOAD_USHORT_LDS_OFFSET_gfx6_gfx7
    UINT64_C(3762880512), UINT64_C(0),	// BUFFER_LOAD_USHORT_LDS_OFFSET_gfx90a
    UINT64_C(3762880512), UINT64_C(0),	// BUFFER_LOAD_USHORT_LDS_OFFSET_vi
    UINT64_C(3760721920), UINT64_C(0),	// BUFFER_LOAD_USHORT_OFFEN_gfx10
    UINT64_C(18014402272296960), UINT64_C(0),	// BUFFER_LOAD_USHORT_OFFEN_gfx11
    UINT64_C(3760721920), UINT64_C(0),	// BUFFER_LOAD_USHORT_OFFEN_gfx6_gfx7
    UINT64_C(3762819072), UINT64_C(0),	// BUFFER_LOAD_USHORT_OFFEN_gfx90a
    UINT64_C(3762819072), UINT64_C(0),	// BUFFER_LOAD_USHORT_OFFEN_vi
    UINT64_C(3760717824), UINT64_C(0),	// BUFFER_LOAD_USHORT_OFFSET_gfx10
    UINT64_C(3762814976), UINT64_C(0),	// BUFFER_LOAD_USHORT_OFFSET_gfx11
    UINT64_C(3760717824), UINT64_C(0),	// BUFFER_LOAD_USHORT_OFFSET_gfx6_gfx7
    UINT64_C(3762814976), UINT64_C(0),	// BUFFER_LOAD_USHORT_OFFSET_gfx90a
    UINT64_C(3762814976), UINT64_C(0),	// BUFFER_LOAD_USHORT_OFFSET_vi
    UINT64_C(36028800779714560), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800779694080), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_BOTHEN_gfx10
    UINT64_C(63050398546001920), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_BOTHEN_gfx11
    UINT64_C(36028800779694080), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800781791232), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_BOTHEN_vi
    UINT64_C(36028800779689984), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_IDXEN_gfx10
    UINT64_C(45036000036519936), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_IDXEN_gfx11
    UINT64_C(36028800779689984), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800781787136), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_IDXEN_vi
    UINT64_C(36028800779685888), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_OFFEN_gfx10
    UINT64_C(27021601527037952), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_OFFEN_gfx11
    UINT64_C(36028800779685888), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800781783040), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_OFFEN_vi
    UINT64_C(36028800779681792), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_OFFSET_gfx10
    UINT64_C(9007203017555968), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_OFFSET_gfx11
    UINT64_C(36028800779681792), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800781778944), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_OFFSET_vi
    UINT64_C(13871086855593951232), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058574987264), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166563328), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147599360), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739175424), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720211456), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311787520), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292823552), UINT64_C(0),	// BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589756928), UINT64_C(0),	// BUFFER_LOAD_USHORT_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570792960), UINT64_C(0),	// BUFFER_LOAD_USHORT_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162369024), UINT64_C(0),	// BUFFER_LOAD_USHORT_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143405056), UINT64_C(0),	// BUFFER_LOAD_USHORT_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818734981120), UINT64_C(0),	// BUFFER_LOAD_USHORT_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716017152), UINT64_C(0),	// BUFFER_LOAD_USHORT_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307593216), UINT64_C(0),	// BUFFER_LOAD_USHORT_VBUFFER_OFFSET_gfx12
    UINT64_C(3288629248), UINT64_C(0),	// BUFFER_LOAD_USHORT_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3764420608), UINT64_C(0),	// BUFFER_STORE_BYTE_ADDR64_gfx6_gfx7
    UINT64_C(3764400128), UINT64_C(0),	// BUFFER_STORE_BYTE_BOTHEN_gfx10
    UINT64_C(54043199292833792), UINT64_C(0),	// BUFFER_STORE_BYTE_BOTHEN_gfx11
    UINT64_C(3764400128), UINT64_C(0),	// BUFFER_STORE_BYTE_BOTHEN_gfx6_gfx7
    UINT64_C(3764400128), UINT64_C(0),	// BUFFER_STORE_BYTE_BOTHEN_gfx90a
    UINT64_C(3764400128), UINT64_C(0),	// BUFFER_STORE_BYTE_BOTHEN_vi
    UINT64_C(3764662272), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_BOTHEN_gfx10
    UINT64_C(54043199295979520), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_BOTHEN_gfx11
    UINT64_C(3764662272), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_BOTHEN_gfx90a
    UINT64_C(3764662272), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_BOTHEN_vi
    UINT64_C(3764658176), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_IDXEN_gfx10
    UINT64_C(36028800786497536), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_IDXEN_gfx11
    UINT64_C(3764658176), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_IDXEN_gfx90a
    UINT64_C(3764658176), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_IDXEN_vi
    UINT64_C(3764654080), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_OFFEN_gfx10
    UINT64_C(18014402277015552), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_OFFEN_gfx11
    UINT64_C(3764654080), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_OFFEN_gfx90a
    UINT64_C(3764654080), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_OFFEN_vi
    UINT64_C(3764649984), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_OFFSET_gfx10
    UINT64_C(3767533568), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_OFFSET_gfx11
    UINT64_C(3764649984), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_OFFSET_gfx90a
    UINT64_C(3764649984), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_OFFSET_vi
    UINT64_C(36028800783626240), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_TFE_BOTHEN_gfx10
    UINT64_C(63050398550720512), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_TFE_BOTHEN_gfx11
    UINT64_C(36028800783626240), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_TFE_BOTHEN_vi
    UINT64_C(36028800783622144), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_TFE_IDXEN_gfx10
    UINT64_C(45036000041238528), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_TFE_IDXEN_gfx11
    UINT64_C(36028800783622144), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_TFE_IDXEN_vi
    UINT64_C(36028800783618048), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_TFE_OFFEN_gfx10
    UINT64_C(27021601531756544), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_TFE_OFFEN_gfx11
    UINT64_C(36028800783618048), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_TFE_OFFEN_vi
    UINT64_C(36028800783613952), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_TFE_OFFSET_gfx10
    UINT64_C(9007203022274560), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_TFE_OFFSET_gfx11
    UINT64_C(36028800783613952), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_TFE_OFFSET_vi
    UINT64_C(13871086855594246144), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575282176), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166858240), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147894272), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739470336), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720506368), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800312082432), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3293118464), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855590051840), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571087872), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162663936), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143699968), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818735276032), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716312064), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307888128), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFSET_gfx12
    UINT64_C(3288924160), UINT64_C(0),	// BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3764396032), UINT64_C(0),	// BUFFER_STORE_BYTE_IDXEN_gfx10
    UINT64_C(36028800783351808), UINT64_C(0),	// BUFFER_STORE_BYTE_IDXEN_gfx11
    UINT64_C(3764396032), UINT64_C(0),	// BUFFER_STORE_BYTE_IDXEN_gfx6_gfx7
    UINT64_C(3764396032), UINT64_C(0),	// BUFFER_STORE_BYTE_IDXEN_gfx90a
    UINT64_C(3764396032), UINT64_C(0),	// BUFFER_STORE_BYTE_IDXEN_vi
    UINT64_C(3764391936), UINT64_C(0),	// BUFFER_STORE_BYTE_OFFEN_gfx10
    UINT64_C(18014402273869824), UINT64_C(0),	// BUFFER_STORE_BYTE_OFFEN_gfx11
    UINT64_C(3764391936), UINT64_C(0),	// BUFFER_STORE_BYTE_OFFEN_gfx6_gfx7
    UINT64_C(3764391936), UINT64_C(0),	// BUFFER_STORE_BYTE_OFFEN_gfx90a
    UINT64_C(3764391936), UINT64_C(0),	// BUFFER_STORE_BYTE_OFFEN_vi
    UINT64_C(3764387840), UINT64_C(0),	// BUFFER_STORE_BYTE_OFFSET_gfx10
    UINT64_C(3764387840), UINT64_C(0),	// BUFFER_STORE_BYTE_OFFSET_gfx11
    UINT64_C(3764387840), UINT64_C(0),	// BUFFER_STORE_BYTE_OFFSET_gfx6_gfx7
    UINT64_C(3764387840), UINT64_C(0),	// BUFFER_STORE_BYTE_OFFSET_gfx90a
    UINT64_C(3764387840), UINT64_C(0),	// BUFFER_STORE_BYTE_OFFSET_vi
    UINT64_C(36028800783384576), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800783364096), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_BOTHEN_gfx10
    UINT64_C(63050398547574784), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_BOTHEN_gfx11
    UINT64_C(36028800783364096), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800783364096), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_BOTHEN_vi
    UINT64_C(36028800783360000), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_IDXEN_gfx10
    UINT64_C(45036000038092800), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_IDXEN_gfx11
    UINT64_C(36028800783360000), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800783360000), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_IDXEN_vi
    UINT64_C(36028800783355904), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_OFFEN_gfx10
    UINT64_C(27021601528610816), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_OFFEN_gfx11
    UINT64_C(36028800783355904), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800783355904), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_OFFEN_vi
    UINT64_C(36028800783351808), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_OFFSET_gfx10
    UINT64_C(9007203019128832), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_OFFSET_gfx11
    UINT64_C(36028800783351808), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800783351808), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_OFFSET_vi
    UINT64_C(13871086855594049536), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575085568), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166661632), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147697664), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739273728), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720309760), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311885824), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292921856), UINT64_C(0),	// BUFFER_STORE_BYTE_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589855232), UINT64_C(0),	// BUFFER_STORE_BYTE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570891264), UINT64_C(0),	// BUFFER_STORE_BYTE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162467328), UINT64_C(0),	// BUFFER_STORE_BYTE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143503360), UINT64_C(0),	// BUFFER_STORE_BYTE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818735079424), UINT64_C(0),	// BUFFER_STORE_BYTE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716115456), UINT64_C(0),	// BUFFER_STORE_BYTE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307691520), UINT64_C(0),	// BUFFER_STORE_BYTE_VBUFFER_OFFSET_gfx12
    UINT64_C(3288727552), UINT64_C(0),	// BUFFER_STORE_BYTE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3765731328), UINT64_C(0),	// BUFFER_STORE_DWORDX2_ADDR64_gfx6_gfx7
    UINT64_C(3765710848), UINT64_C(0),	// BUFFER_STORE_DWORDX2_BOTHEN_gfx10
    UINT64_C(54043199293620224), UINT64_C(0),	// BUFFER_STORE_DWORDX2_BOTHEN_gfx11
    UINT64_C(3765710848), UINT64_C(0),	// BUFFER_STORE_DWORDX2_BOTHEN_gfx6_gfx7
    UINT64_C(3765710848), UINT64_C(0),	// BUFFER_STORE_DWORDX2_BOTHEN_gfx90a
    UINT64_C(3765710848), UINT64_C(0),	// BUFFER_STORE_DWORDX2_BOTHEN_vi
    UINT64_C(3765706752), UINT64_C(0),	// BUFFER_STORE_DWORDX2_IDXEN_gfx10
    UINT64_C(36028800784138240), UINT64_C(0),	// BUFFER_STORE_DWORDX2_IDXEN_gfx11
    UINT64_C(3765706752), UINT64_C(0),	// BUFFER_STORE_DWORDX2_IDXEN_gfx6_gfx7
    UINT64_C(3765706752), UINT64_C(0),	// BUFFER_STORE_DWORDX2_IDXEN_gfx90a
    UINT64_C(3765706752), UINT64_C(0),	// BUFFER_STORE_DWORDX2_IDXEN_vi
    UINT64_C(3765702656), UINT64_C(0),	// BUFFER_STORE_DWORDX2_OFFEN_gfx10
    UINT64_C(18014402274656256), UINT64_C(0),	// BUFFER_STORE_DWORDX2_OFFEN_gfx11
    UINT64_C(3765702656), UINT64_C(0),	// BUFFER_STORE_DWORDX2_OFFEN_gfx6_gfx7
    UINT64_C(3765702656), UINT64_C(0),	// BUFFER_STORE_DWORDX2_OFFEN_gfx90a
    UINT64_C(3765702656), UINT64_C(0),	// BUFFER_STORE_DWORDX2_OFFEN_vi
    UINT64_C(3765698560), UINT64_C(0),	// BUFFER_STORE_DWORDX2_OFFSET_gfx10
    UINT64_C(3765174272), UINT64_C(0),	// BUFFER_STORE_DWORDX2_OFFSET_gfx11
    UINT64_C(3765698560), UINT64_C(0),	// BUFFER_STORE_DWORDX2_OFFSET_gfx6_gfx7
    UINT64_C(3765698560), UINT64_C(0),	// BUFFER_STORE_DWORDX2_OFFSET_gfx90a
    UINT64_C(3765698560), UINT64_C(0),	// BUFFER_STORE_DWORDX2_OFFSET_vi
    UINT64_C(36028800784695296), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800784674816), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_BOTHEN_gfx10
    UINT64_C(63050398548361216), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_BOTHEN_gfx11
    UINT64_C(36028800784674816), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800784674816), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_BOTHEN_vi
    UINT64_C(36028800784670720), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_IDXEN_gfx10
    UINT64_C(45036000038879232), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_IDXEN_gfx11
    UINT64_C(36028800784670720), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800784670720), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_IDXEN_vi
    UINT64_C(36028800784666624), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_OFFEN_gfx10
    UINT64_C(27021601529397248), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_OFFEN_gfx11
    UINT64_C(36028800784666624), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800784666624), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_OFFEN_vi
    UINT64_C(36028800784662528), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_OFFSET_gfx10
    UINT64_C(9007203019915264), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_OFFSET_gfx11
    UINT64_C(36028800784662528), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800784662528), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_OFFSET_vi
    UINT64_C(13871086855594098688), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575134720), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166710784), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147746816), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739322880), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720358912), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311934976), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292971008), UINT64_C(0),	// BUFFER_STORE_DWORDX2_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589904384), UINT64_C(0),	// BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570940416), UINT64_C(0),	// BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162516480), UINT64_C(0),	// BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143552512), UINT64_C(0),	// BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818735128576), UINT64_C(0),	// BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716164608), UINT64_C(0),	// BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307740672), UINT64_C(0),	// BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_gfx12
    UINT64_C(3288776704), UINT64_C(0),	// BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3766255616), UINT64_C(0),	// BUFFER_STORE_DWORDX3_ADDR64_gfx6_gfx7
    UINT64_C(3766235136), UINT64_C(0),	// BUFFER_STORE_DWORDX3_BOTHEN_gfx10
    UINT64_C(54043199293882368), UINT64_C(0),	// BUFFER_STORE_DWORDX3_BOTHEN_gfx11
    UINT64_C(3766235136), UINT64_C(0),	// BUFFER_STORE_DWORDX3_BOTHEN_gfx6_gfx7
    UINT64_C(3765972992), UINT64_C(0),	// BUFFER_STORE_DWORDX3_BOTHEN_gfx90a
    UINT64_C(3765972992), UINT64_C(0),	// BUFFER_STORE_DWORDX3_BOTHEN_vi
    UINT64_C(3766231040), UINT64_C(0),	// BUFFER_STORE_DWORDX3_IDXEN_gfx10
    UINT64_C(36028800784400384), UINT64_C(0),	// BUFFER_STORE_DWORDX3_IDXEN_gfx11
    UINT64_C(3766231040), UINT64_C(0),	// BUFFER_STORE_DWORDX3_IDXEN_gfx6_gfx7
    UINT64_C(3765968896), UINT64_C(0),	// BUFFER_STORE_DWORDX3_IDXEN_gfx90a
    UINT64_C(3765968896), UINT64_C(0),	// BUFFER_STORE_DWORDX3_IDXEN_vi
    UINT64_C(3766226944), UINT64_C(0),	// BUFFER_STORE_DWORDX3_OFFEN_gfx10
    UINT64_C(18014402274918400), UINT64_C(0),	// BUFFER_STORE_DWORDX3_OFFEN_gfx11
    UINT64_C(3766226944), UINT64_C(0),	// BUFFER_STORE_DWORDX3_OFFEN_gfx6_gfx7
    UINT64_C(3765964800), UINT64_C(0),	// BUFFER_STORE_DWORDX3_OFFEN_gfx90a
    UINT64_C(3765964800), UINT64_C(0),	// BUFFER_STORE_DWORDX3_OFFEN_vi
    UINT64_C(3766222848), UINT64_C(0),	// BUFFER_STORE_DWORDX3_OFFSET_gfx10
    UINT64_C(3765436416), UINT64_C(0),	// BUFFER_STORE_DWORDX3_OFFSET_gfx11
    UINT64_C(3766222848), UINT64_C(0),	// BUFFER_STORE_DWORDX3_OFFSET_gfx6_gfx7
    UINT64_C(3765960704), UINT64_C(0),	// BUFFER_STORE_DWORDX3_OFFSET_gfx90a
    UINT64_C(3765960704), UINT64_C(0),	// BUFFER_STORE_DWORDX3_OFFSET_vi
    UINT64_C(36028800785219584), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800785199104), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_BOTHEN_gfx10
    UINT64_C(63050398548623360), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_BOTHEN_gfx11
    UINT64_C(36028800785199104), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800784936960), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_BOTHEN_vi
    UINT64_C(36028800785195008), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_IDXEN_gfx10
    UINT64_C(45036000039141376), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_IDXEN_gfx11
    UINT64_C(36028800785195008), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800784932864), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_IDXEN_vi
    UINT64_C(36028800785190912), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_OFFEN_gfx10
    UINT64_C(27021601529659392), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_OFFEN_gfx11
    UINT64_C(36028800785190912), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800784928768), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_OFFEN_vi
    UINT64_C(36028800785186816), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_OFFSET_gfx10
    UINT64_C(9007203020177408), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_OFFSET_gfx11
    UINT64_C(36028800785186816), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800784924672), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_OFFSET_vi
    UINT64_C(13871086855594115072), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575151104), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166727168), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147763200), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739339264), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720375296), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311951360), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292987392), UINT64_C(0),	// BUFFER_STORE_DWORDX3_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589920768), UINT64_C(0),	// BUFFER_STORE_DWORDX3_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570956800), UINT64_C(0),	// BUFFER_STORE_DWORDX3_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162532864), UINT64_C(0),	// BUFFER_STORE_DWORDX3_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143568896), UINT64_C(0),	// BUFFER_STORE_DWORDX3_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818735144960), UINT64_C(0),	// BUFFER_STORE_DWORDX3_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716180992), UINT64_C(0),	// BUFFER_STORE_DWORDX3_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307757056), UINT64_C(0),	// BUFFER_STORE_DWORDX3_VBUFFER_OFFSET_gfx12
    UINT64_C(3288793088), UINT64_C(0),	// BUFFER_STORE_DWORDX3_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3765993472), UINT64_C(0),	// BUFFER_STORE_DWORDX4_ADDR64_gfx6_gfx7
    UINT64_C(3765972992), UINT64_C(0),	// BUFFER_STORE_DWORDX4_BOTHEN_gfx10
    UINT64_C(54043199294144512), UINT64_C(0),	// BUFFER_STORE_DWORDX4_BOTHEN_gfx11
    UINT64_C(3765972992), UINT64_C(0),	// BUFFER_STORE_DWORDX4_BOTHEN_gfx6_gfx7
    UINT64_C(3766235136), UINT64_C(0),	// BUFFER_STORE_DWORDX4_BOTHEN_gfx90a
    UINT64_C(3766235136), UINT64_C(0),	// BUFFER_STORE_DWORDX4_BOTHEN_vi
    UINT64_C(3765968896), UINT64_C(0),	// BUFFER_STORE_DWORDX4_IDXEN_gfx10
    UINT64_C(36028800784662528), UINT64_C(0),	// BUFFER_STORE_DWORDX4_IDXEN_gfx11
    UINT64_C(3765968896), UINT64_C(0),	// BUFFER_STORE_DWORDX4_IDXEN_gfx6_gfx7
    UINT64_C(3766231040), UINT64_C(0),	// BUFFER_STORE_DWORDX4_IDXEN_gfx90a
    UINT64_C(3766231040), UINT64_C(0),	// BUFFER_STORE_DWORDX4_IDXEN_vi
    UINT64_C(3765964800), UINT64_C(0),	// BUFFER_STORE_DWORDX4_OFFEN_gfx10
    UINT64_C(18014402275180544), UINT64_C(0),	// BUFFER_STORE_DWORDX4_OFFEN_gfx11
    UINT64_C(3765964800), UINT64_C(0),	// BUFFER_STORE_DWORDX4_OFFEN_gfx6_gfx7
    UINT64_C(3766226944), UINT64_C(0),	// BUFFER_STORE_DWORDX4_OFFEN_gfx90a
    UINT64_C(3766226944), UINT64_C(0),	// BUFFER_STORE_DWORDX4_OFFEN_vi
    UINT64_C(3765960704), UINT64_C(0),	// BUFFER_STORE_DWORDX4_OFFSET_gfx10
    UINT64_C(3765698560), UINT64_C(0),	// BUFFER_STORE_DWORDX4_OFFSET_gfx11
    UINT64_C(3765960704), UINT64_C(0),	// BUFFER_STORE_DWORDX4_OFFSET_gfx6_gfx7
    UINT64_C(3766222848), UINT64_C(0),	// BUFFER_STORE_DWORDX4_OFFSET_gfx90a
    UINT64_C(3766222848), UINT64_C(0),	// BUFFER_STORE_DWORDX4_OFFSET_vi
    UINT64_C(36028800784957440), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800784936960), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_BOTHEN_gfx10
    UINT64_C(63050398548885504), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_BOTHEN_gfx11
    UINT64_C(36028800784936960), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800785199104), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_BOTHEN_vi
    UINT64_C(36028800784932864), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_IDXEN_gfx10
    UINT64_C(45036000039403520), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_IDXEN_gfx11
    UINT64_C(36028800784932864), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800785195008), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_IDXEN_vi
    UINT64_C(36028800784928768), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_OFFEN_gfx10
    UINT64_C(27021601529921536), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_OFFEN_gfx11
    UINT64_C(36028800784928768), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800785190912), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_OFFEN_vi
    UINT64_C(36028800784924672), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_OFFSET_gfx10
    UINT64_C(9007203020439552), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_OFFSET_gfx11
    UINT64_C(36028800784924672), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800785186816), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_OFFSET_vi
    UINT64_C(13871086855594131456), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575167488), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166743552), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147779584), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739355648), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720391680), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311967744), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3293003776), UINT64_C(0),	// BUFFER_STORE_DWORDX4_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589937152), UINT64_C(0),	// BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570973184), UINT64_C(0),	// BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162549248), UINT64_C(0),	// BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143585280), UINT64_C(0),	// BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818735161344), UINT64_C(0),	// BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716197376), UINT64_C(0),	// BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307773440), UINT64_C(0),	// BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_gfx12
    UINT64_C(3288809472), UINT64_C(0),	// BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3765469184), UINT64_C(0),	// BUFFER_STORE_DWORD_ADDR64_gfx6_gfx7
    UINT64_C(3765448704), UINT64_C(0),	// BUFFER_STORE_DWORD_BOTHEN_gfx10
    UINT64_C(54043199293358080), UINT64_C(0),	// BUFFER_STORE_DWORD_BOTHEN_gfx11
    UINT64_C(3765448704), UINT64_C(0),	// BUFFER_STORE_DWORD_BOTHEN_gfx6_gfx7
    UINT64_C(3765448704), UINT64_C(0),	// BUFFER_STORE_DWORD_BOTHEN_gfx90a
    UINT64_C(3765448704), UINT64_C(0),	// BUFFER_STORE_DWORD_BOTHEN_vi
    UINT64_C(3765444608), UINT64_C(0),	// BUFFER_STORE_DWORD_IDXEN_gfx10
    UINT64_C(36028800783876096), UINT64_C(0),	// BUFFER_STORE_DWORD_IDXEN_gfx11
    UINT64_C(3765444608), UINT64_C(0),	// BUFFER_STORE_DWORD_IDXEN_gfx6_gfx7
    UINT64_C(3765444608), UINT64_C(0),	// BUFFER_STORE_DWORD_IDXEN_gfx90a
    UINT64_C(3765444608), UINT64_C(0),	// BUFFER_STORE_DWORD_IDXEN_vi
    UINT64_C(3765440512), UINT64_C(0),	// BUFFER_STORE_DWORD_OFFEN_gfx10
    UINT64_C(18014402274394112), UINT64_C(0),	// BUFFER_STORE_DWORD_OFFEN_gfx11
    UINT64_C(3765440512), UINT64_C(0),	// BUFFER_STORE_DWORD_OFFEN_gfx6_gfx7
    UINT64_C(3765440512), UINT64_C(0),	// BUFFER_STORE_DWORD_OFFEN_gfx90a
    UINT64_C(3765440512), UINT64_C(0),	// BUFFER_STORE_DWORD_OFFEN_vi
    UINT64_C(3765436416), UINT64_C(0),	// BUFFER_STORE_DWORD_OFFSET_gfx10
    UINT64_C(3764912128), UINT64_C(0),	// BUFFER_STORE_DWORD_OFFSET_gfx11
    UINT64_C(3765436416), UINT64_C(0),	// BUFFER_STORE_DWORD_OFFSET_gfx6_gfx7
    UINT64_C(3765436416), UINT64_C(0),	// BUFFER_STORE_DWORD_OFFSET_gfx90a
    UINT64_C(3765436416), UINT64_C(0),	// BUFFER_STORE_DWORD_OFFSET_vi
    UINT64_C(36028800784433152), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800784412672), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_BOTHEN_gfx10
    UINT64_C(63050398548099072), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_BOTHEN_gfx11
    UINT64_C(36028800784412672), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800784412672), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_BOTHEN_vi
    UINT64_C(36028800784408576), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_IDXEN_gfx10
    UINT64_C(45036000038617088), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_IDXEN_gfx11
    UINT64_C(36028800784408576), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800784408576), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_IDXEN_vi
    UINT64_C(36028800784404480), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_OFFEN_gfx10
    UINT64_C(27021601529135104), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_OFFEN_gfx11
    UINT64_C(36028800784404480), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800784404480), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_OFFEN_vi
    UINT64_C(36028800784400384), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_OFFSET_gfx10
    UINT64_C(9007203019653120), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_OFFSET_gfx11
    UINT64_C(36028800784400384), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800784400384), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_OFFSET_vi
    UINT64_C(13871086855594082304), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575118336), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166694400), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147730432), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739306496), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720342528), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311918592), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292954624), UINT64_C(0),	// BUFFER_STORE_DWORD_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589888000), UINT64_C(0),	// BUFFER_STORE_DWORD_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570924032), UINT64_C(0),	// BUFFER_STORE_DWORD_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162500096), UINT64_C(0),	// BUFFER_STORE_DWORD_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143536128), UINT64_C(0),	// BUFFER_STORE_DWORD_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818735112192), UINT64_C(0),	// BUFFER_STORE_DWORD_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716148224), UINT64_C(0),	// BUFFER_STORE_DWORD_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307724288), UINT64_C(0),	// BUFFER_STORE_DWORD_VBUFFER_OFFSET_gfx12
    UINT64_C(3288760320), UINT64_C(0),	// BUFFER_STORE_DWORD_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3768332288), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_gfx10
    UINT64_C(54043199296765952), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_gfx11
    UINT64_C(3768332288), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_gfx90a
    UINT64_C(3768332288), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_vi
    UINT64_C(3768328192), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_gfx10
    UINT64_C(36028800787283968), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_gfx11
    UINT64_C(3768328192), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_gfx90a
    UINT64_C(3768328192), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_vi
    UINT64_C(3768324096), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_gfx10
    UINT64_C(18014402277801984), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_gfx11
    UINT64_C(3768324096), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_gfx90a
    UINT64_C(3768324096), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_vi
    UINT64_C(3768320000), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_gfx10
    UINT64_C(3768320000), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_gfx11
    UINT64_C(3768320000), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_gfx90a
    UINT64_C(3768320000), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_vi
    UINT64_C(36028800787296256), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_TFE_BOTHEN_gfx10
    UINT64_C(63050398551506944), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_TFE_BOTHEN_gfx11
    UINT64_C(36028800787296256), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_TFE_BOTHEN_vi
    UINT64_C(36028800787292160), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_TFE_IDXEN_gfx10
    UINT64_C(45036000042024960), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_TFE_IDXEN_gfx11
    UINT64_C(36028800787292160), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_TFE_IDXEN_vi
    UINT64_C(36028800787288064), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_TFE_OFFEN_gfx10
    UINT64_C(27021601532542976), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_TFE_OFFEN_gfx11
    UINT64_C(36028800787288064), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_TFE_OFFEN_vi
    UINT64_C(36028800787283968), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_TFE_OFFSET_gfx10
    UINT64_C(9007203023060992), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_TFE_OFFSET_gfx11
    UINT64_C(36028800787283968), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_TFE_OFFSET_vi
    UINT64_C(13871086855594295296), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575331328), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166907392), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147943424), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739519488), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720555520), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800312131584), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3293167616), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855590100992), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571137024), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162713088), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143749120), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818735325184), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716361216), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307937280), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_OFFSET_gfx12
    UINT64_C(3288973312), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3793498112), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx10
    UINT64_C(54043199290474496), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx11
    UINT64_C(3762040832), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx90a
    UINT64_C(3762040832), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_vi
    UINT64_C(3793494016), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx10
    UINT64_C(36028800780992512), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx11
    UINT64_C(3762036736), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx90a
    UINT64_C(3762036736), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_vi
    UINT64_C(3793489920), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx10
    UINT64_C(18014402271510528), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx11
    UINT64_C(3762032640), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx90a
    UINT64_C(3762032640), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_vi
    UINT64_C(3793485824), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx10
    UINT64_C(3762028544), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx11
    UINT64_C(3762028544), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx90a
    UINT64_C(3762028544), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_vi
    UINT64_C(36028800812462080), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_TFE_BOTHEN_gfx10
    UINT64_C(63050398545215488), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_TFE_BOTHEN_gfx11
    UINT64_C(36028800781004800), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_TFE_BOTHEN_vi
    UINT64_C(36028800812457984), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_TFE_IDXEN_gfx10
    UINT64_C(45036000035733504), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_TFE_IDXEN_gfx11
    UINT64_C(36028800781000704), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_TFE_IDXEN_vi
    UINT64_C(36028800812453888), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_TFE_OFFEN_gfx10
    UINT64_C(27021601526251520), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_TFE_OFFEN_gfx11
    UINT64_C(36028800780996608), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_TFE_OFFEN_vi
    UINT64_C(36028800812449792), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_TFE_OFFSET_gfx10
    UINT64_C(9007203016769536), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_TFE_OFFSET_gfx11
    UINT64_C(36028800780992512), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_TFE_OFFSET_vi
    UINT64_C(13871086855593902080), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058574938112), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166514176), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147550208), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739126272), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720162304), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311738368), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292774400), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589707776), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570743808), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162319872), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143355904), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818734931968), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021715968000), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307544064), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_gfx12
    UINT64_C(3288580096), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3762040832), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80
    UINT64_C(3762036736), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80
    UINT64_C(3762032640), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80
    UINT64_C(3762028544), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80
    UINT64_C(36028800781004800), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_gfx80_TFE_BOTHEN_gfx80
    UINT64_C(36028800781000704), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_gfx80_TFE_IDXEN_gfx80
    UINT64_C(36028800780996608), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_gfx80_TFE_OFFEN_gfx80
    UINT64_C(36028800780992512), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZW_gfx80_TFE_OFFSET_gfx80
    UINT64_C(3793235968), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx10
    UINT64_C(54043199290212352), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx11
    UINT64_C(3761778688), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx90a
    UINT64_C(3761778688), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_vi
    UINT64_C(3793231872), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx10
    UINT64_C(36028800780730368), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx11
    UINT64_C(3761774592), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx90a
    UINT64_C(3761774592), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_vi
    UINT64_C(3793227776), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx10
    UINT64_C(18014402271248384), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx11
    UINT64_C(3761770496), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx90a
    UINT64_C(3761770496), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_vi
    UINT64_C(3793223680), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx10
    UINT64_C(3761766400), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx11
    UINT64_C(3761766400), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx90a
    UINT64_C(3761766400), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_vi
    UINT64_C(36028800812199936), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_TFE_BOTHEN_gfx10
    UINT64_C(63050398544953344), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_TFE_BOTHEN_gfx11
    UINT64_C(36028800780742656), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_TFE_BOTHEN_vi
    UINT64_C(36028800812195840), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_TFE_IDXEN_gfx10
    UINT64_C(45036000035471360), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_TFE_IDXEN_gfx11
    UINT64_C(36028800780738560), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_TFE_IDXEN_vi
    UINT64_C(36028800812191744), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_TFE_OFFEN_gfx10
    UINT64_C(27021601525989376), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_TFE_OFFEN_gfx11
    UINT64_C(36028800780734464), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_TFE_OFFEN_vi
    UINT64_C(36028800812187648), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_TFE_OFFSET_gfx10
    UINT64_C(9007203016507392), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_TFE_OFFSET_gfx11
    UINT64_C(36028800780730368), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_TFE_OFFSET_vi
    UINT64_C(13871086855593885696), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058574921728), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166497792), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147533824), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739109888), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720145920), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311721984), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292758016), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589691392), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570727424), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162303488), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143339520), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818734915584), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021715951616), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307527680), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_OFFSET_gfx12
    UINT64_C(3288563712), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3761778688), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80
    UINT64_C(3761774592), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80
    UINT64_C(3761770496), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80
    UINT64_C(3761766400), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80
    UINT64_C(36028800780742656), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_gfx80_TFE_BOTHEN_gfx80
    UINT64_C(36028800780738560), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_gfx80_TFE_IDXEN_gfx80
    UINT64_C(36028800780734464), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_gfx80_TFE_OFFEN_gfx80
    UINT64_C(36028800780730368), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XYZ_gfx80_TFE_OFFSET_gfx80
    UINT64_C(3792973824), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx10
    UINT64_C(54043199289950208), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx11
    UINT64_C(3761516544), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx90a
    UINT64_C(3761516544), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_BOTHEN_vi
    UINT64_C(3792969728), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx10
    UINT64_C(36028800780468224), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx11
    UINT64_C(3761512448), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx90a
    UINT64_C(3761512448), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_IDXEN_vi
    UINT64_C(3792965632), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx10
    UINT64_C(18014402270986240), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx11
    UINT64_C(3761508352), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx90a
    UINT64_C(3761508352), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_OFFEN_vi
    UINT64_C(3792961536), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx10
    UINT64_C(3761504256), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx11
    UINT64_C(3761504256), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx90a
    UINT64_C(3761504256), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_OFFSET_vi
    UINT64_C(36028800811937792), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_TFE_BOTHEN_gfx10
    UINT64_C(63050398544691200), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_TFE_BOTHEN_gfx11
    UINT64_C(36028800780480512), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_TFE_BOTHEN_vi
    UINT64_C(36028800811933696), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_TFE_IDXEN_gfx10
    UINT64_C(45036000035209216), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_TFE_IDXEN_gfx11
    UINT64_C(36028800780476416), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_TFE_IDXEN_vi
    UINT64_C(36028800811929600), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_TFE_OFFEN_gfx10
    UINT64_C(27021601525727232), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_TFE_OFFEN_gfx11
    UINT64_C(36028800780472320), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_TFE_OFFEN_vi
    UINT64_C(36028800811925504), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_TFE_OFFSET_gfx10
    UINT64_C(9007203016245248), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_TFE_OFFSET_gfx11
    UINT64_C(36028800780468224), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_TFE_OFFSET_vi
    UINT64_C(13871086855593869312), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058574905344), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166481408), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147517440), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739093504), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720129536), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311705600), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292741632), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589675008), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570711040), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162287104), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143323136), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818734899200), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021715935232), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307511296), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_gfx12
    UINT64_C(3288547328), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3761516544), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_gfx80
    UINT64_C(3761512448), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_gfx80
    UINT64_C(3761508352), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_gfx80
    UINT64_C(3761504256), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_gfx80
    UINT64_C(36028800780480512), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_gfx80_TFE_BOTHEN_gfx80
    UINT64_C(36028800780476416), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_gfx80_TFE_IDXEN_gfx80
    UINT64_C(36028800780472320), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_gfx80_TFE_OFFEN_gfx80
    UINT64_C(36028800780468224), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_XY_gfx80_TFE_OFFSET_gfx80
    UINT64_C(3792711680), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx10
    UINT64_C(54043199289688064), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx11
    UINT64_C(3761254400), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx90a
    UINT64_C(3761254400), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_BOTHEN_vi
    UINT64_C(3792707584), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_IDXEN_gfx10
    UINT64_C(36028800780206080), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_IDXEN_gfx11
    UINT64_C(3761250304), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_IDXEN_gfx90a
    UINT64_C(3761250304), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_IDXEN_vi
    UINT64_C(3792703488), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_OFFEN_gfx10
    UINT64_C(18014402270724096), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_OFFEN_gfx11
    UINT64_C(3761246208), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_OFFEN_gfx90a
    UINT64_C(3761246208), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_OFFEN_vi
    UINT64_C(3792699392), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_OFFSET_gfx10
    UINT64_C(3761242112), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_OFFSET_gfx11
    UINT64_C(3761242112), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_OFFSET_gfx90a
    UINT64_C(3761242112), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_OFFSET_vi
    UINT64_C(36028800811675648), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_TFE_BOTHEN_gfx10
    UINT64_C(63050398544429056), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_TFE_BOTHEN_gfx11
    UINT64_C(36028800780218368), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_TFE_BOTHEN_vi
    UINT64_C(36028800811671552), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_TFE_IDXEN_gfx10
    UINT64_C(45036000034947072), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_TFE_IDXEN_gfx11
    UINT64_C(36028800780214272), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_TFE_IDXEN_vi
    UINT64_C(36028800811667456), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_TFE_OFFEN_gfx10
    UINT64_C(27021601525465088), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_TFE_OFFEN_gfx11
    UINT64_C(36028800780210176), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_TFE_OFFEN_vi
    UINT64_C(36028800811663360), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_TFE_OFFSET_gfx10
    UINT64_C(9007203015983104), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_TFE_OFFSET_gfx11
    UINT64_C(36028800780206080), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_TFE_OFFSET_vi
    UINT64_C(13871086855593852928), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058574888960), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166465024), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147501056), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739077120), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720113152), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311689216), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292725248), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589658624), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570694656), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162270720), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143306752), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818734882816), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021715918848), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307494912), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_gfx12
    UINT64_C(3288530944), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3761254400), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_gfx80
    UINT64_C(3761250304), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_gfx80
    UINT64_C(3761246208), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_gfx80
    UINT64_C(3761242112), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_gfx80
    UINT64_C(36028800780218368), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_gfx80_TFE_BOTHEN_gfx80
    UINT64_C(36028800780214272), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_gfx80_TFE_IDXEN_gfx80
    UINT64_C(36028800780210176), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_gfx80_TFE_OFFEN_gfx80
    UINT64_C(36028800780206080), UINT64_C(0),	// BUFFER_STORE_FORMAT_D16_X_gfx80_TFE_OFFSET_gfx80
    UINT64_C(3759964160), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_ADDR64_gfx6_gfx7
    UINT64_C(3759943680), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx10
    UINT64_C(54043199288377344), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx11
    UINT64_C(3759943680), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx6_gfx7
    UINT64_C(3759943680), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx90a
    UINT64_C(3759943680), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_BOTHEN_vi
    UINT64_C(3759939584), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx10
    UINT64_C(36028800778895360), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx11
    UINT64_C(3759939584), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx6_gfx7
    UINT64_C(3759939584), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx90a
    UINT64_C(3759939584), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_IDXEN_vi
    UINT64_C(3759935488), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx10
    UINT64_C(18014402269413376), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx11
    UINT64_C(3759935488), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx6_gfx7
    UINT64_C(3759935488), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx90a
    UINT64_C(3759935488), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_OFFEN_vi
    UINT64_C(3759931392), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx10
    UINT64_C(3759931392), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx11
    UINT64_C(3759931392), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx6_gfx7
    UINT64_C(3759931392), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx90a
    UINT64_C(3759931392), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_OFFSET_vi
    UINT64_C(36028800778928128), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800778907648), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_BOTHEN_gfx10
    UINT64_C(63050398543118336), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_BOTHEN_gfx11
    UINT64_C(36028800778907648), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800778907648), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_BOTHEN_vi
    UINT64_C(36028800778903552), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_IDXEN_gfx10
    UINT64_C(45036000033636352), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_IDXEN_gfx11
    UINT64_C(36028800778903552), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800778903552), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_IDXEN_vi
    UINT64_C(36028800778899456), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_OFFEN_gfx10
    UINT64_C(27021601524154368), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_OFFEN_gfx11
    UINT64_C(36028800778899456), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800778899456), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_OFFEN_vi
    UINT64_C(36028800778895360), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_OFFSET_gfx10
    UINT64_C(9007203014672384), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_OFFSET_gfx11
    UINT64_C(36028800778895360), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800778895360), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_OFFSET_vi
    UINT64_C(13871086855593771008), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058574807040), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166383104), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147419136), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818738995200), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720031232), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311607296), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292643328), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589576704), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570612736), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162188800), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143224832), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818734800896), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021715836928), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307412992), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_gfx12
    UINT64_C(3288449024), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3759702016), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_ADDR64_gfx6_gfx7
    UINT64_C(3759681536), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx10
    UINT64_C(54043199288115200), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx11
    UINT64_C(3759681536), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx6_gfx7
    UINT64_C(3759681536), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx90a
    UINT64_C(3759681536), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_BOTHEN_vi
    UINT64_C(3759677440), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx10
    UINT64_C(36028800778633216), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx11
    UINT64_C(3759677440), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx6_gfx7
    UINT64_C(3759677440), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx90a
    UINT64_C(3759677440), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_IDXEN_vi
    UINT64_C(3759673344), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx10
    UINT64_C(18014402269151232), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx11
    UINT64_C(3759673344), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx6_gfx7
    UINT64_C(3759673344), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx90a
    UINT64_C(3759673344), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_OFFEN_vi
    UINT64_C(3759669248), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx10
    UINT64_C(3759669248), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx11
    UINT64_C(3759669248), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx6_gfx7
    UINT64_C(3759669248), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx90a
    UINT64_C(3759669248), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_OFFSET_vi
    UINT64_C(36028800778665984), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800778645504), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_BOTHEN_gfx10
    UINT64_C(63050398542856192), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_BOTHEN_gfx11
    UINT64_C(36028800778645504), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800778645504), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_BOTHEN_vi
    UINT64_C(36028800778641408), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_IDXEN_gfx10
    UINT64_C(45036000033374208), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_IDXEN_gfx11
    UINT64_C(36028800778641408), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800778641408), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_IDXEN_vi
    UINT64_C(36028800778637312), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_OFFEN_gfx10
    UINT64_C(27021601523892224), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_OFFEN_gfx11
    UINT64_C(36028800778637312), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800778637312), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_OFFEN_vi
    UINT64_C(36028800778633216), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_OFFSET_gfx10
    UINT64_C(9007203014410240), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_OFFSET_gfx11
    UINT64_C(36028800778633216), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800778633216), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_OFFSET_vi
    UINT64_C(13871086855593754624), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058574790656), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166366720), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147402752), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818738978816), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720014848), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311590912), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292626944), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589560320), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570596352), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162172416), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143208448), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818734784512), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021715820544), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307396608), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_gfx12
    UINT64_C(3288432640), UINT64_C(0),	// BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3759439872), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_ADDR64_gfx6_gfx7
    UINT64_C(3759419392), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_BOTHEN_gfx10
    UINT64_C(54043199287853056), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_BOTHEN_gfx11
    UINT64_C(3759419392), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_BOTHEN_gfx6_gfx7
    UINT64_C(3759419392), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_BOTHEN_gfx90a
    UINT64_C(3759419392), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_BOTHEN_vi
    UINT64_C(3759415296), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_IDXEN_gfx10
    UINT64_C(36028800778371072), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_IDXEN_gfx11
    UINT64_C(3759415296), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_IDXEN_gfx6_gfx7
    UINT64_C(3759415296), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_IDXEN_gfx90a
    UINT64_C(3759415296), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_IDXEN_vi
    UINT64_C(3759411200), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_OFFEN_gfx10
    UINT64_C(18014402268889088), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_OFFEN_gfx11
    UINT64_C(3759411200), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_OFFEN_gfx6_gfx7
    UINT64_C(3759411200), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_OFFEN_gfx90a
    UINT64_C(3759411200), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_OFFEN_vi
    UINT64_C(3759407104), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_OFFSET_gfx10
    UINT64_C(3759407104), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_OFFSET_gfx11
    UINT64_C(3759407104), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_OFFSET_gfx6_gfx7
    UINT64_C(3759407104), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_OFFSET_gfx90a
    UINT64_C(3759407104), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_OFFSET_vi
    UINT64_C(36028800778403840), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800778383360), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_BOTHEN_gfx10
    UINT64_C(63050398542594048), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_BOTHEN_gfx11
    UINT64_C(36028800778383360), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800778383360), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_BOTHEN_vi
    UINT64_C(36028800778379264), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_IDXEN_gfx10
    UINT64_C(45036000033112064), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_IDXEN_gfx11
    UINT64_C(36028800778379264), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800778379264), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_IDXEN_vi
    UINT64_C(36028800778375168), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_OFFEN_gfx10
    UINT64_C(27021601523630080), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_OFFEN_gfx11
    UINT64_C(36028800778375168), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800778375168), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_OFFEN_vi
    UINT64_C(36028800778371072), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_OFFSET_gfx10
    UINT64_C(9007203014148096), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_OFFSET_gfx11
    UINT64_C(36028800778371072), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800778371072), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_OFFSET_vi
    UINT64_C(13871086855593738240), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058574774272), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166350336), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147386368), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818738962432), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021719998464), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311574528), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292610560), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589543936), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570579968), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162156032), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143192064), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818734768128), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021715804160), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307380224), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_gfx12
    UINT64_C(3288416256), UINT64_C(0),	// BUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3759177728), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_ADDR64_gfx6_gfx7
    UINT64_C(3759157248), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_BOTHEN_gfx10
    UINT64_C(54043199287590912), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_BOTHEN_gfx11
    UINT64_C(3759157248), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_BOTHEN_gfx6_gfx7
    UINT64_C(3759157248), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_BOTHEN_gfx90a
    UINT64_C(3759157248), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_BOTHEN_vi
    UINT64_C(3759153152), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_IDXEN_gfx10
    UINT64_C(36028800778108928), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_IDXEN_gfx11
    UINT64_C(3759153152), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_IDXEN_gfx6_gfx7
    UINT64_C(3759153152), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_IDXEN_gfx90a
    UINT64_C(3759153152), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_IDXEN_vi
    UINT64_C(3759149056), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_OFFEN_gfx10
    UINT64_C(18014402268626944), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_OFFEN_gfx11
    UINT64_C(3759149056), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_OFFEN_gfx6_gfx7
    UINT64_C(3759149056), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_OFFEN_gfx90a
    UINT64_C(3759149056), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_OFFEN_vi
    UINT64_C(3759144960), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_OFFSET_gfx10
    UINT64_C(3759144960), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_OFFSET_gfx11
    UINT64_C(3759144960), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_OFFSET_gfx6_gfx7
    UINT64_C(3759144960), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_OFFSET_gfx90a
    UINT64_C(3759144960), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_OFFSET_vi
    UINT64_C(36028800778141696), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800778121216), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_BOTHEN_gfx10
    UINT64_C(63050398542331904), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_BOTHEN_gfx11
    UINT64_C(36028800778121216), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800778121216), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_BOTHEN_vi
    UINT64_C(36028800778117120), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_IDXEN_gfx10
    UINT64_C(45036000032849920), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_IDXEN_gfx11
    UINT64_C(36028800778117120), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800778117120), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_IDXEN_vi
    UINT64_C(36028800778113024), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_OFFEN_gfx10
    UINT64_C(27021601523367936), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_OFFEN_gfx11
    UINT64_C(36028800778113024), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800778113024), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_OFFEN_vi
    UINT64_C(36028800778108928), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_OFFSET_gfx10
    UINT64_C(9007203013885952), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_OFFSET_gfx11
    UINT64_C(36028800778108928), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800778108928), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_OFFSET_vi
    UINT64_C(13871086855593721856), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058574757888), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166333952), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147369984), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818738946048), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021719982080), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311558144), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292594176), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589527552), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570563584), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162139648), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143175680), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818734751744), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021715787776), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307363840), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_gfx12
    UINT64_C(3288399872), UINT64_C(0),	// BUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3774152704), UINT64_C(0),	// BUFFER_STORE_LDS_DWORD_gfx90a
    UINT64_C(3774152704), UINT64_C(0),	// BUFFER_STORE_LDS_DWORD_vi
    UINT64_C(3764944896), UINT64_C(0),	// BUFFER_STORE_SHORT_ADDR64_gfx6_gfx7
    UINT64_C(3764924416), UINT64_C(0),	// BUFFER_STORE_SHORT_BOTHEN_gfx10
    UINT64_C(54043199293095936), UINT64_C(0),	// BUFFER_STORE_SHORT_BOTHEN_gfx11
    UINT64_C(3764924416), UINT64_C(0),	// BUFFER_STORE_SHORT_BOTHEN_gfx6_gfx7
    UINT64_C(3764924416), UINT64_C(0),	// BUFFER_STORE_SHORT_BOTHEN_gfx90a
    UINT64_C(3764924416), UINT64_C(0),	// BUFFER_STORE_SHORT_BOTHEN_vi
    UINT64_C(3765186560), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_BOTHEN_gfx10
    UINT64_C(54043199296241664), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_BOTHEN_gfx11
    UINT64_C(3765186560), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_BOTHEN_gfx90a
    UINT64_C(3765186560), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_BOTHEN_vi
    UINT64_C(3765182464), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_IDXEN_gfx10
    UINT64_C(36028800786759680), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_IDXEN_gfx11
    UINT64_C(3765182464), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_IDXEN_gfx90a
    UINT64_C(3765182464), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_IDXEN_vi
    UINT64_C(3765178368), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_OFFEN_gfx10
    UINT64_C(18014402277277696), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_OFFEN_gfx11
    UINT64_C(3765178368), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_OFFEN_gfx90a
    UINT64_C(3765178368), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_OFFEN_vi
    UINT64_C(3765174272), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_OFFSET_gfx10
    UINT64_C(3767795712), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_OFFSET_gfx11
    UINT64_C(3765174272), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_OFFSET_gfx90a
    UINT64_C(3765174272), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_OFFSET_vi
    UINT64_C(36028800784150528), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_TFE_BOTHEN_gfx10
    UINT64_C(63050398550982656), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_TFE_BOTHEN_gfx11
    UINT64_C(36028800784150528), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_TFE_BOTHEN_vi
    UINT64_C(36028800784146432), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_TFE_IDXEN_gfx10
    UINT64_C(45036000041500672), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_TFE_IDXEN_gfx11
    UINT64_C(36028800784146432), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_TFE_IDXEN_vi
    UINT64_C(36028800784142336), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_TFE_OFFEN_gfx10
    UINT64_C(27021601532018688), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_TFE_OFFEN_gfx11
    UINT64_C(36028800784142336), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_TFE_OFFEN_vi
    UINT64_C(36028800784138240), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_TFE_OFFSET_gfx10
    UINT64_C(9007203022536704), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_TFE_OFFSET_gfx11
    UINT64_C(36028800784138240), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_TFE_OFFSET_vi
    UINT64_C(13871086855594262528), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575298560), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166874624), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147910656), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739486720), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720522752), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800312098816), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3293134848), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855590068224), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058571104256), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162680320), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143716352), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818735292416), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716328448), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307904512), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFSET_gfx12
    UINT64_C(3288940544), UINT64_C(0),	// BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3764920320), UINT64_C(0),	// BUFFER_STORE_SHORT_IDXEN_gfx10
    UINT64_C(36028800783613952), UINT64_C(0),	// BUFFER_STORE_SHORT_IDXEN_gfx11
    UINT64_C(3764920320), UINT64_C(0),	// BUFFER_STORE_SHORT_IDXEN_gfx6_gfx7
    UINT64_C(3764920320), UINT64_C(0),	// BUFFER_STORE_SHORT_IDXEN_gfx90a
    UINT64_C(3764920320), UINT64_C(0),	// BUFFER_STORE_SHORT_IDXEN_vi
    UINT64_C(3764916224), UINT64_C(0),	// BUFFER_STORE_SHORT_OFFEN_gfx10
    UINT64_C(18014402274131968), UINT64_C(0),	// BUFFER_STORE_SHORT_OFFEN_gfx11
    UINT64_C(3764916224), UINT64_C(0),	// BUFFER_STORE_SHORT_OFFEN_gfx6_gfx7
    UINT64_C(3764916224), UINT64_C(0),	// BUFFER_STORE_SHORT_OFFEN_gfx90a
    UINT64_C(3764916224), UINT64_C(0),	// BUFFER_STORE_SHORT_OFFEN_vi
    UINT64_C(3764912128), UINT64_C(0),	// BUFFER_STORE_SHORT_OFFSET_gfx10
    UINT64_C(3764649984), UINT64_C(0),	// BUFFER_STORE_SHORT_OFFSET_gfx11
    UINT64_C(3764912128), UINT64_C(0),	// BUFFER_STORE_SHORT_OFFSET_gfx6_gfx7
    UINT64_C(3764912128), UINT64_C(0),	// BUFFER_STORE_SHORT_OFFSET_gfx90a
    UINT64_C(3764912128), UINT64_C(0),	// BUFFER_STORE_SHORT_OFFSET_vi
    UINT64_C(36028800783908864), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_ADDR64_gfx6_gfx7
    UINT64_C(36028800783888384), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_BOTHEN_gfx10
    UINT64_C(63050398547836928), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_BOTHEN_gfx11
    UINT64_C(36028800783888384), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_BOTHEN_gfx6_gfx7
    UINT64_C(36028800783888384), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_BOTHEN_vi
    UINT64_C(36028800783884288), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_IDXEN_gfx10
    UINT64_C(45036000038354944), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_IDXEN_gfx11
    UINT64_C(36028800783884288), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_IDXEN_gfx6_gfx7
    UINT64_C(36028800783884288), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_IDXEN_vi
    UINT64_C(36028800783880192), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_OFFEN_gfx10
    UINT64_C(27021601528872960), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_OFFEN_gfx11
    UINT64_C(36028800783880192), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_OFFEN_gfx6_gfx7
    UINT64_C(36028800783880192), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_OFFEN_vi
    UINT64_C(36028800783876096), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_OFFSET_gfx10
    UINT64_C(9007203019390976), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_OFFSET_gfx11
    UINT64_C(36028800783876096), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_OFFSET_gfx6_gfx7
    UINT64_C(36028800783876096), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_OFFSET_vi
    UINT64_C(13871086855594065920), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058575101952), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837166678016), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040147714048), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818739290112), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021720326144), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800311902208), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_VBUFFER_OFFSET_gfx12
    UINT64_C(3292938240), UINT64_C(0),	// BUFFER_STORE_SHORT_TFE_VBUFFER_OFFSET_gfx12_format
    UINT64_C(13871086855589871616), UINT64_C(0),	// BUFFER_STORE_SHORT_VBUFFER_BOTHEN_gfx12
    UINT64_C(13835058058570907648), UINT64_C(0),	// BUFFER_STORE_SHORT_VBUFFER_BOTHEN_gfx12_format
    UINT64_C(9259400837162483712), UINT64_C(0),	// BUFFER_STORE_SHORT_VBUFFER_IDXEN_gfx12
    UINT64_C(9223372040143519744), UINT64_C(0),	// BUFFER_STORE_SHORT_VBUFFER_IDXEN_gfx12_format
    UINT64_C(4647714818735095808), UINT64_C(0),	// BUFFER_STORE_SHORT_VBUFFER_OFFEN_gfx12
    UINT64_C(4611686021716131840), UINT64_C(0),	// BUFFER_STORE_SHORT_VBUFFER_OFFEN_gfx12_format
    UINT64_C(36028800307707904), UINT64_C(0),	// BUFFER_STORE_SHORT_VBUFFER_OFFSET_gfx12
    UINT64_C(3288743936), UINT64_C(0),	// BUFFER_STORE_SHORT_VBUFFER_OFFSET_gfx12_format
    UINT64_C(3787456512), UINT64_C(0),	// BUFFER_WBINVL1_SC_gfx6
    UINT64_C(3787456512), UINT64_C(0),	// BUFFER_WBINVL1_VOL_gfx7
    UINT64_C(3774611456), UINT64_C(0),	// BUFFER_WBINVL1_VOL_vi
    UINT64_C(3787718656), UINT64_C(0),	// BUFFER_WBINVL1_gfx6_gfx7
    UINT64_C(3774349312), UINT64_C(0),	// BUFFER_WBINVL1_vi
    UINT64_C(3768582144), UINT64_C(0),	// BUFFER_WBL2_gfx90a
    UINT64_C(3768582144), UINT64_C(0),	// BUFFER_WBL2_gfx940
    UINT64_C(3994763264), UINT64_C(0),	// CLUSTER_LOAD_ASYNC_TO_LDS_B128_SADDR_gfx1250
    UINT64_C(3994763388), UINT64_C(0),	// CLUSTER_LOAD_ASYNC_TO_LDS_B128_gfx1250
    UINT64_C(3994730496), UINT64_C(0),	// CLUSTER_LOAD_ASYNC_TO_LDS_B32_SADDR_gfx1250
    UINT64_C(3994730620), UINT64_C(0),	// CLUSTER_LOAD_ASYNC_TO_LDS_B32_gfx1250
    UINT64_C(3994746880), UINT64_C(0),	// CLUSTER_LOAD_ASYNC_TO_LDS_B64_SADDR_gfx1250
    UINT64_C(3994747004), UINT64_C(0),	// CLUSTER_LOAD_ASYNC_TO_LDS_B64_gfx1250
    UINT64_C(3994714112), UINT64_C(0),	// CLUSTER_LOAD_ASYNC_TO_LDS_B8_SADDR_gfx1250
    UINT64_C(3994714236), UINT64_C(0),	// CLUSTER_LOAD_ASYNC_TO_LDS_B8_gfx1250
    UINT64_C(3994697728), UINT64_C(0),	// CLUSTER_LOAD_B128_SADDR_gfx1250
    UINT64_C(3994697852), UINT64_C(0),	// CLUSTER_LOAD_B128_gfx1250
    UINT64_C(3994664960), UINT64_C(0),	// CLUSTER_LOAD_B32_SADDR_gfx1250
    UINT64_C(3994665084), UINT64_C(0),	// CLUSTER_LOAD_B32_gfx1250
    UINT64_C(3994681344), UINT64_C(0),	// CLUSTER_LOAD_B64_SADDR_gfx1250
    UINT64_C(3994681468), UINT64_C(0),	// CLUSTER_LOAD_B64_gfx1250
    UINT64_C(3629383680), UINT64_C(0),	// DS_ADD_F32_gfx10
    UINT64_C(3629383680), UINT64_C(0),	// DS_ADD_F32_gfx11
    UINT64_C(3629383680), UINT64_C(0),	// DS_ADD_F32_gfx12
    UINT64_C(3626631168), UINT64_C(0),	// DS_ADD_F32_vi
    UINT64_C(3626631168), UINT64_C(0),	// DS_ADD_F32_vi_gfx9
    UINT64_C(3645898752), UINT64_C(0),	// DS_ADD_F64_gfx12
    UINT64_C(3635937280), UINT64_C(0),	// DS_ADD_F64_vi
    UINT64_C(3655991296), UINT64_C(0),	// DS_ADD_GS_REG_RTN_gfx11
    UINT64_C(3646160896), UINT64_C(0),	// DS_ADD_RTN_F32_gfx10
    UINT64_C(3655598080), UINT64_C(0),	// DS_ADD_RTN_F32_gfx11
    UINT64_C(3655598080), UINT64_C(0),	// DS_ADD_RTN_F32_gfx12
    UINT64_C(3630825472), UINT64_C(0),	// DS_ADD_RTN_F32_vi
    UINT64_C(3664379904), UINT64_C(0),	// DS_ADD_RTN_F32_vi_agpr
    UINT64_C(3630825472), UINT64_C(0),	// DS_ADD_RTN_F32_vi_gfx9
    UINT64_C(3654287360), UINT64_C(0),	// DS_ADD_RTN_F64_gfx12
    UINT64_C(3640131584), UINT64_C(0),	// DS_ADD_RTN_F64_vi
    UINT64_C(3673686016), UINT64_C(0),	// DS_ADD_RTN_F64_vi_agpr
    UINT64_C(3632267264), UINT64_C(0),	// DS_ADD_RTN_U32_gfx10
    UINT64_C(3632267264), UINT64_C(0),	// DS_ADD_RTN_U32_gfx11
    UINT64_C(3632267264), UINT64_C(0),	// DS_ADD_RTN_U32_gfx12
    UINT64_C(3632267264), UINT64_C(0),	// DS_ADD_RTN_U32_gfx6_gfx7
    UINT64_C(3628072960), UINT64_C(0),	// DS_ADD_RTN_U32_vi
    UINT64_C(3661627392), UINT64_C(0),	// DS_ADD_RTN_U32_vi_agpr
    UINT64_C(3628072960), UINT64_C(0),	// DS_ADD_RTN_U32_vi_gfx9
    UINT64_C(3649044480), UINT64_C(0),	// DS_ADD_RTN_U64_gfx10
    UINT64_C(3649044480), UINT64_C(0),	// DS_ADD_RTN_U64_gfx11
    UINT64_C(3649044480), UINT64_C(0),	// DS_ADD_RTN_U64_gfx12
    UINT64_C(3649044480), UINT64_C(0),	// DS_ADD_RTN_U64_gfx6_gfx7
    UINT64_C(3636461568), UINT64_C(0),	// DS_ADD_RTN_U64_vi
    UINT64_C(3670016000), UINT64_C(0),	// DS_ADD_RTN_U64_vi_agpr
    UINT64_C(3636461568), UINT64_C(0),	// DS_ADD_RTN_U64_vi_gfx9
    UINT64_C(3662938112), UINT64_C(0),	// DS_ADD_SRC2_F32_gfx10
    UINT64_C(3643408384), UINT64_C(0),	// DS_ADD_SRC2_F32_vi
    UINT64_C(3657433088), UINT64_C(0),	// DS_ADD_SRC2_U32_gfx10
    UINT64_C(3657433088), UINT64_C(0),	// DS_ADD_SRC2_U32_gfx6_gfx7
    UINT64_C(3640655872), UINT64_C(0),	// DS_ADD_SRC2_U32_vi
    UINT64_C(3674210304), UINT64_C(0),	// DS_ADD_SRC2_U64_gfx10
    UINT64_C(3674210304), UINT64_C(0),	// DS_ADD_SRC2_U64_gfx6_gfx7
    UINT64_C(3649044480), UINT64_C(0),	// DS_ADD_SRC2_U64_vi
    UINT64_C(3623878656), UINT64_C(0),	// DS_ADD_U32_gfx10
    UINT64_C(3623878656), UINT64_C(0),	// DS_ADD_U32_gfx11
    UINT64_C(3623878656), UINT64_C(0),	// DS_ADD_U32_gfx12
    UINT64_C(3623878656), UINT64_C(0),	// DS_ADD_U32_gfx6_gfx7
    UINT64_C(3623878656), UINT64_C(0),	// DS_ADD_U32_vi
    UINT64_C(3623878656), UINT64_C(0),	// DS_ADD_U32_vi_gfx9
    UINT64_C(3640655872), UINT64_C(0),	// DS_ADD_U64_gfx10
    UINT64_C(3640655872), UINT64_C(0),	// DS_ADD_U64_gfx11
    UINT64_C(3640655872), UINT64_C(0),	// DS_ADD_U64_gfx12
    UINT64_C(3640655872), UINT64_C(0),	// DS_ADD_U64_gfx6_gfx7
    UINT64_C(3632267264), UINT64_C(0),	// DS_ADD_U64_vi
    UINT64_C(3632267264), UINT64_C(0),	// DS_ADD_U64_vi_gfx9
    UINT64_C(3626237952), UINT64_C(0),	// DS_AND_B32_gfx10
    UINT64_C(3626237952), UINT64_C(0),	// DS_AND_B32_gfx11
    UINT64_C(3626237952), UINT64_C(0),	// DS_AND_B32_gfx12
    UINT64_C(3626237952), UINT64_C(0),	// DS_AND_B32_gfx6_gfx7
    UINT64_C(3625058304), UINT64_C(0),	// DS_AND_B32_vi
    UINT64_C(3625058304), UINT64_C(0),	// DS_AND_B32_vi_gfx9
    UINT64_C(3643015168), UINT64_C(0),	// DS_AND_B64_gfx10
    UINT64_C(3643015168), UINT64_C(0),	// DS_AND_B64_gfx11
    UINT64_C(3643015168), UINT64_C(0),	// DS_AND_B64_gfx12
    UINT64_C(3643015168), UINT64_C(0),	// DS_AND_B64_gfx6_gfx7
    UINT64_C(3633446912), UINT64_C(0),	// DS_AND_B64_vi
    UINT64_C(3633446912), UINT64_C(0),	// DS_AND_B64_vi_gfx9
    UINT64_C(3634626560), UINT64_C(0),	// DS_AND_RTN_B32_gfx10
    UINT64_C(3634626560), UINT64_C(0),	// DS_AND_RTN_B32_gfx11
    UINT64_C(3634626560), UINT64_C(0),	// DS_AND_RTN_B32_gfx12
    UINT64_C(3634626560), UINT64_C(0),	// DS_AND_RTN_B32_gfx6_gfx7
    UINT64_C(3629252608), UINT64_C(0),	// DS_AND_RTN_B32_vi
    UINT64_C(3662807040), UINT64_C(0),	// DS_AND_RTN_B32_vi_agpr
    UINT64_C(3629252608), UINT64_C(0),	// DS_AND_RTN_B32_vi_gfx9
    UINT64_C(3651403776), UINT64_C(0),	// DS_AND_RTN_B64_gfx10
    UINT64_C(3651403776), UINT64_C(0),	// DS_AND_RTN_B64_gfx11
    UINT64_C(3651403776), UINT64_C(0),	// DS_AND_RTN_B64_gfx12
    UINT64_C(3651403776), UINT64_C(0),	// DS_AND_RTN_B64_gfx6_gfx7
    UINT64_C(3637641216), UINT64_C(0),	// DS_AND_RTN_B64_vi
    UINT64_C(3671195648), UINT64_C(0),	// DS_AND_RTN_B64_vi_agpr
    UINT64_C(3637641216), UINT64_C(0),	// DS_AND_RTN_B64_vi_gfx9
    UINT64_C(3659792384), UINT64_C(0),	// DS_AND_SRC2_B32_gfx10
    UINT64_C(3659792384), UINT64_C(0),	// DS_AND_SRC2_B32_gfx6_gfx7
    UINT64_C(3641835520), UINT64_C(0),	// DS_AND_SRC2_B32_vi
    UINT64_C(3676569600), UINT64_C(0),	// DS_AND_SRC2_B64_gfx10
    UINT64_C(3676569600), UINT64_C(0),	// DS_AND_SRC2_B64_gfx6_gfx7
    UINT64_C(3650224128), UINT64_C(0),	// DS_AND_SRC2_B64_vi
    UINT64_C(3640131584), UINT64_C(0),	// DS_APPEND_gfx10
    UINT64_C(3640131584), UINT64_C(0),	// DS_APPEND_gfx11
    UINT64_C(3640131584), UINT64_C(0),	// DS_APPEND_gfx12
    UINT64_C(3640131584), UINT64_C(0),	// DS_APPEND_gfx6_gfx7
    UINT64_C(3648782336), UINT64_C(0),	// DS_APPEND_vi
    UINT64_C(3646423040), UINT64_C(0),	// DS_ATOMIC_ASYNC_BARRIER_ARRIVE_B64_gfx12
    UINT64_C(3654549504), UINT64_C(0),	// DS_ATOMIC_BARRIER_ARRIVE_RTN_B64_gfx12
    UINT64_C(3670802432), UINT64_C(0),	// DS_BPERMUTE_B32_gfx10
    UINT64_C(3670802432), UINT64_C(0),	// DS_BPERMUTE_B32_gfx11
    UINT64_C(3670802432), UINT64_C(0),	// DS_BPERMUTE_B32_gfx12
    UINT64_C(3632136192), UINT64_C(0),	// DS_BPERMUTE_B32_vi
    UINT64_C(3665690624), UINT64_C(0),	// DS_BPERMUTE_B32_vi_agpr
    UINT64_C(3677618176), UINT64_C(0),	// DS_BPERMUTE_FI_B32_gfx12
    UINT64_C(3682861056), UINT64_C(0),	// DS_BVH_STACK_PUSH8_POP1_RTN_B32_gfx12
    UINT64_C(3683123200), UINT64_C(0),	// DS_BVH_STACK_PUSH8_POP2_RTN_B64_gfx12
    UINT64_C(3669229568), UINT64_C(0),	// DS_BVH_STACK_RTN_B32_gfx11
    UINT64_C(3682598912), UINT64_C(0),	// DS_BVH_STACK_RTN_B32_gfx12
    UINT64_C(3628072960), UINT64_C(0),	// DS_CMPSTORE_B32_gfx11
    UINT64_C(3628072960), UINT64_C(0),	// DS_CMPSTORE_B32_gfx12
    UINT64_C(3644850176), UINT64_C(0),	// DS_CMPSTORE_B64_gfx11
    UINT64_C(3644850176), UINT64_C(0),	// DS_CMPSTORE_B64_gfx12
    UINT64_C(3628335104), UINT64_C(0),	// DS_CMPSTORE_F32_gfx11
    UINT64_C(3645112320), UINT64_C(0),	// DS_CMPSTORE_F64_gfx11
    UINT64_C(3636461568), UINT64_C(0),	// DS_CMPSTORE_RTN_B32_gfx11
    UINT64_C(3636461568), UINT64_C(0),	// DS_CMPSTORE_RTN_B32_gfx12
    UINT64_C(3653238784), UINT64_C(0),	// DS_CMPSTORE_RTN_B64_gfx11
    UINT64_C(3653238784), UINT64_C(0),	// DS_CMPSTORE_RTN_B64_gfx12
    UINT64_C(3636723712), UINT64_C(0),	// DS_CMPSTORE_RTN_F32_gfx11
    UINT64_C(3653500928), UINT64_C(0),	// DS_CMPSTORE_RTN_F64_gfx11
    UINT64_C(3628072960), UINT64_C(0),	// DS_CMPST_B32_gfx10
    UINT64_C(3628072960), UINT64_C(0),	// DS_CMPST_B32_gfx6_gfx7
    UINT64_C(3625975808), UINT64_C(0),	// DS_CMPST_B32_vi
    UINT64_C(3659530240), UINT64_C(0),	// DS_CMPST_B32_vi_agpr
    UINT64_C(3625975808), UINT64_C(0),	// DS_CMPST_B32_vi_gfx9
    UINT64_C(3644850176), UINT64_C(0),	// DS_CMPST_B64_gfx10
    UINT64_C(3644850176), UINT64_C(0),	// DS_CMPST_B64_gfx6_gfx7
    UINT64_C(3634364416), UINT64_C(0),	// DS_CMPST_B64_vi
    UINT64_C(3667918848), UINT64_C(0),	// DS_CMPST_B64_vi_agpr
    UINT64_C(3634364416), UINT64_C(0),	// DS_CMPST_B64_vi_gfx9
    UINT64_C(3628335104), UINT64_C(0),	// DS_CMPST_F32_gfx10
    UINT64_C(3628335104), UINT64_C(0),	// DS_CMPST_F32_gfx6_gfx7
    UINT64_C(3626106880), UINT64_C(0),	// DS_CMPST_F32_vi
    UINT64_C(3659661312), UINT64_C(0),	// DS_CMPST_F32_vi_agpr
    UINT64_C(3626106880), UINT64_C(0),	// DS_CMPST_F32_vi_gfx9
    UINT64_C(3645112320), UINT64_C(0),	// DS_CMPST_F64_gfx10
    UINT64_C(3645112320), UINT64_C(0),	// DS_CMPST_F64_gfx6_gfx7
    UINT64_C(3634495488), UINT64_C(0),	// DS_CMPST_F64_vi
    UINT64_C(3668049920), UINT64_C(0),	// DS_CMPST_F64_vi_agpr
    UINT64_C(3634495488), UINT64_C(0),	// DS_CMPST_F64_vi_gfx9
    UINT64_C(3636461568), UINT64_C(0),	// DS_CMPST_RTN_B32_gfx10
    UINT64_C(3636461568), UINT64_C(0),	// DS_CMPST_RTN_B32_gfx6_gfx7
    UINT64_C(3630170112), UINT64_C(0),	// DS_CMPST_RTN_B32_vi
    UINT64_C(3663724544), UINT64_C(0),	// DS_CMPST_RTN_B32_vi_agpr
    UINT64_C(3630170112), UINT64_C(0),	// DS_CMPST_RTN_B32_vi_gfx9
    UINT64_C(3653238784), UINT64_C(0),	// DS_CMPST_RTN_B64_gfx10
    UINT64_C(3653238784), UINT64_C(0),	// DS_CMPST_RTN_B64_gfx6_gfx7
    UINT64_C(3638558720), UINT64_C(0),	// DS_CMPST_RTN_B64_vi
    UINT64_C(3672113152), UINT64_C(0),	// DS_CMPST_RTN_B64_vi_agpr
    UINT64_C(3638558720), UINT64_C(0),	// DS_CMPST_RTN_B64_vi_gfx9
    UINT64_C(3636723712), UINT64_C(0),	// DS_CMPST_RTN_F32_gfx10
    UINT64_C(3636723712), UINT64_C(0),	// DS_CMPST_RTN_F32_gfx6_gfx7
    UINT64_C(3630301184), UINT64_C(0),	// DS_CMPST_RTN_F32_vi
    UINT64_C(3663855616), UINT64_C(0),	// DS_CMPST_RTN_F32_vi_agpr
    UINT64_C(3630301184), UINT64_C(0),	// DS_CMPST_RTN_F32_vi_gfx9
    UINT64_C(3653500928), UINT64_C(0),	// DS_CMPST_RTN_F64_gfx10
    UINT64_C(3653500928), UINT64_C(0),	// DS_CMPST_RTN_F64_gfx6_gfx7
    UINT64_C(3638689792), UINT64_C(0),	// DS_CMPST_RTN_F64_vi
    UINT64_C(3672244224), UINT64_C(0),	// DS_CMPST_RTN_F64_vi_agpr
    UINT64_C(3638689792), UINT64_C(0),	// DS_CMPST_RTN_F64_vi_gfx9
    UINT64_C(3656908800), UINT64_C(0),	// DS_CONDXCHG32_RTN_B64_gfx10
    UINT64_C(3656908800), UINT64_C(0),	// DS_CONDXCHG32_RTN_B64_gfx11
    UINT64_C(3656908800), UINT64_C(0),	// DS_CONDXCHG32_RTN_B64_gfx12
    UINT64_C(3656908800), UINT64_C(0),	// DS_CONDXCHG32_RTN_B64_gfx7
    UINT64_C(3640393728), UINT64_C(0),	// DS_CONDXCHG32_RTN_B64_vi
    UINT64_C(3673948160), UINT64_C(0),	// DS_CONDXCHG32_RTN_B64_vi_agpr
    UINT64_C(3640393728), UINT64_C(0),	// DS_CONDXCHG32_RTN_B64_vi_gfx9
    UINT64_C(3667918848), UINT64_C(0),	// DS_COND_SUB_RTN_U32_gfx12
    UINT64_C(3663724544), UINT64_C(0),	// DS_COND_SUB_U32_gfx12
    UINT64_C(3639869440), UINT64_C(0),	// DS_CONSUME_gfx10
    UINT64_C(3639869440), UINT64_C(0),	// DS_CONSUME_gfx11
    UINT64_C(3639869440), UINT64_C(0),	// DS_CONSUME_gfx12
    UINT64_C(3639869440), UINT64_C(0),	// DS_CONSUME_gfx6_gfx7
    UINT64_C(3648651264), UINT64_C(0),	// DS_CONSUME_vi
    UINT64_C(3633315840), UINT64_C(0),	// DS_DEC_RTN_U32_gfx10
    UINT64_C(3633315840), UINT64_C(0),	// DS_DEC_RTN_U32_gfx11
    UINT64_C(3633315840), UINT64_C(0),	// DS_DEC_RTN_U32_gfx12
    UINT64_C(3633315840), UINT64_C(0),	// DS_DEC_RTN_U32_gfx6_gfx7
    UINT64_C(3628597248), UINT64_C(0),	// DS_DEC_RTN_U32_vi
    UINT64_C(3662151680), UINT64_C(0),	// DS_DEC_RTN_U32_vi_agpr
    UINT64_C(3628597248), UINT64_C(0),	// DS_DEC_RTN_U32_vi_gfx9
    UINT64_C(3650093056), UINT64_C(0),	// DS_DEC_RTN_U64_gfx10
    UINT64_C(3650093056), UINT64_C(0),	// DS_DEC_RTN_U64_gfx11
    UINT64_C(3650093056), UINT64_C(0),	// DS_DEC_RTN_U64_gfx12
    UINT64_C(3650093056), UINT64_C(0),	// DS_DEC_RTN_U64_gfx6_gfx7
    UINT64_C(3636985856), UINT64_C(0),	// DS_DEC_RTN_U64_vi
    UINT64_C(3670540288), UINT64_C(0),	// DS_DEC_RTN_U64_vi_agpr
    UINT64_C(3636985856), UINT64_C(0),	// DS_DEC_RTN_U64_vi_gfx9
    UINT64_C(3658481664), UINT64_C(0),	// DS_DEC_SRC2_U32_gfx10
    UINT64_C(3658481664), UINT64_C(0),	// DS_DEC_SRC2_U32_gfx6_gfx7
    UINT64_C(3641180160), UINT64_C(0),	// DS_DEC_SRC2_U32_vi
    UINT64_C(3675258880), UINT64_C(0),	// DS_DEC_SRC2_U64_gfx10
    UINT64_C(3675258880), UINT64_C(0),	// DS_DEC_SRC2_U64_gfx6_gfx7
    UINT64_C(3649568768), UINT64_C(0),	// DS_DEC_SRC2_U64_vi
    UINT64_C(3624927232), UINT64_C(0),	// DS_DEC_U32_gfx10
    UINT64_C(3624927232), UINT64_C(0),	// DS_DEC_U32_gfx11
    UINT64_C(3624927232), UINT64_C(0),	// DS_DEC_U32_gfx12
    UINT64_C(3624927232), UINT64_C(0),	// DS_DEC_U32_gfx6_gfx7
    UINT64_C(3624402944), UINT64_C(0),	// DS_DEC_U32_vi
    UINT64_C(3624402944), UINT64_C(0),	// DS_DEC_U32_vi_gfx9
    UINT64_C(3641704448), UINT64_C(0),	// DS_DEC_U64_gfx10
    UINT64_C(3641704448), UINT64_C(0),	// DS_DEC_U64_gfx11
    UINT64_C(3641704448), UINT64_C(0),	// DS_DEC_U64_gfx12
    UINT64_C(3641704448), UINT64_C(0),	// DS_DEC_U64_gfx6_gfx7
    UINT64_C(3632791552), UINT64_C(0),	// DS_DEC_U64_vi
    UINT64_C(3632791552), UINT64_C(0),	// DS_DEC_U64_vi_gfx9
    UINT64_C(3457155072), UINT64_C(0),	// DS_DIRECT_LOAD_gfx12
    UINT64_C(3631611904), UINT64_C(0),	// DS_GWS_BARRIER_gfx10
    UINT64_C(3631611904), UINT64_C(0),	// DS_GWS_BARRIER_gfx11
    UINT64_C(3631611904), UINT64_C(0),	// DS_GWS_BARRIER_gfx6_gfx7
    UINT64_C(3644522496), UINT64_C(0),	// DS_GWS_BARRIER_vi
    UINT64_C(3630563328), UINT64_C(0),	// DS_GWS_INIT_gfx10
    UINT64_C(3630563328), UINT64_C(0),	// DS_GWS_INIT_gfx11
    UINT64_C(3630563328), UINT64_C(0),	// DS_GWS_INIT_gfx6_gfx7
    UINT64_C(3643998208), UINT64_C(0),	// DS_GWS_INIT_vi
    UINT64_C(3631087616), UINT64_C(0),	// DS_GWS_SEMA_BR_gfx10
    UINT64_C(3631087616), UINT64_C(0),	// DS_GWS_SEMA_BR_gfx11
    UINT64_C(3631087616), UINT64_C(0),	// DS_GWS_SEMA_BR_gfx6_gfx7
    UINT64_C(3644260352), UINT64_C(0),	// DS_GWS_SEMA_BR_vi
    UINT64_C(3631349760), UINT64_C(0),	// DS_GWS_SEMA_P_gfx10
    UINT64_C(3631349760), UINT64_C(0),	// DS_GWS_SEMA_P_gfx11
    UINT64_C(3631349760), UINT64_C(0),	// DS_GWS_SEMA_P_gfx6_gfx7
    UINT64_C(3644391424), UINT64_C(0),	// DS_GWS_SEMA_P_vi
    UINT64_C(3630301184), UINT64_C(0),	// DS_GWS_SEMA_RELEASE_ALL_gfx10
    UINT64_C(3630301184), UINT64_C(0),	// DS_GWS_SEMA_RELEASE_ALL_gfx11
    UINT64_C(3630301184), UINT64_C(0),	// DS_GWS_SEMA_RELEASE_ALL_gfx7
    UINT64_C(3643867136), UINT64_C(0),	// DS_GWS_SEMA_RELEASE_ALL_vi
    UINT64_C(3630825472), UINT64_C(0),	// DS_GWS_SEMA_V_gfx10
    UINT64_C(3630825472), UINT64_C(0),	// DS_GWS_SEMA_V_gfx11
    UINT64_C(3630825472), UINT64_C(0),	// DS_GWS_SEMA_V_gfx6_gfx7
    UINT64_C(3644129280), UINT64_C(0),	// DS_GWS_SEMA_V_vi
    UINT64_C(3633053696), UINT64_C(0),	// DS_INC_RTN_U32_gfx10
    UINT64_C(3633053696), UINT64_C(0),	// DS_INC_RTN_U32_gfx11
    UINT64_C(3633053696), UINT64_C(0),	// DS_INC_RTN_U32_gfx12
    UINT64_C(3633053696), UINT64_C(0),	// DS_INC_RTN_U32_gfx6_gfx7
    UINT64_C(3628466176), UINT64_C(0),	// DS_INC_RTN_U32_vi
    UINT64_C(3662020608), UINT64_C(0),	// DS_INC_RTN_U32_vi_agpr
    UINT64_C(3628466176), UINT64_C(0),	// DS_INC_RTN_U32_vi_gfx9
    UINT64_C(3649830912), UINT64_C(0),	// DS_INC_RTN_U64_gfx10
    UINT64_C(3649830912), UINT64_C(0),	// DS_INC_RTN_U64_gfx11
    UINT64_C(3649830912), UINT64_C(0),	// DS_INC_RTN_U64_gfx12
    UINT64_C(3649830912), UINT64_C(0),	// DS_INC_RTN_U64_gfx6_gfx7
    UINT64_C(3636854784), UINT64_C(0),	// DS_INC_RTN_U64_vi
    UINT64_C(3670409216), UINT64_C(0),	// DS_INC_RTN_U64_vi_agpr
    UINT64_C(3636854784), UINT64_C(0),	// DS_INC_RTN_U64_vi_gfx9
    UINT64_C(3658219520), UINT64_C(0),	// DS_INC_SRC2_U32_gfx10
    UINT64_C(3658219520), UINT64_C(0),	// DS_INC_SRC2_U32_gfx6_gfx7
    UINT64_C(3641049088), UINT64_C(0),	// DS_INC_SRC2_U32_vi
    UINT64_C(3674996736), UINT64_C(0),	// DS_INC_SRC2_U64_gfx10
    UINT64_C(3674996736), UINT64_C(0),	// DS_INC_SRC2_U64_gfx6_gfx7
    UINT64_C(3649437696), UINT64_C(0),	// DS_INC_SRC2_U64_vi
    UINT64_C(3624665088), UINT64_C(0),	// DS_INC_U32_gfx10
    UINT64_C(3624665088), UINT64_C(0),	// DS_INC_U32_gfx11
    UINT64_C(3624665088), UINT64_C(0),	// DS_INC_U32_gfx12
    UINT64_C(3624665088), UINT64_C(0),	// DS_INC_U32_gfx6_gfx7
    UINT64_C(3624271872), UINT64_C(0),	// DS_INC_U32_vi
    UINT64_C(3624271872), UINT64_C(0),	// DS_INC_U32_vi_gfx9
    UINT64_C(3641442304), UINT64_C(0),	// DS_INC_U64_gfx10
    UINT64_C(3641442304), UINT64_C(0),	// DS_INC_U64_gfx11
    UINT64_C(3641442304), UINT64_C(0),	// DS_INC_U64_gfx12
    UINT64_C(3641442304), UINT64_C(0),	// DS_INC_U64_gfx6_gfx7
    UINT64_C(3632660480), UINT64_C(0),	// DS_INC_U64_vi
    UINT64_C(3632660480), UINT64_C(0),	// DS_INC_U64_vi_gfx9
    UINT64_C(3689938944), UINT64_C(0),	// DS_LOAD_TR16_B128_gfx12
    UINT64_C(3689414656), UINT64_C(0),	// DS_LOAD_TR4_B64_gfx12
    UINT64_C(3689676800), UINT64_C(0),	// DS_LOAD_TR6_B96_gfx12
    UINT64_C(3690201088), UINT64_C(0),	// DS_LOAD_TR8_B64_gfx12
    UINT64_C(3628859392), UINT64_C(0),	// DS_MAX_F32_gfx10
    UINT64_C(3628859392), UINT64_C(0),	// DS_MAX_F32_gfx11
    UINT64_C(3628859392), UINT64_C(0),	// DS_MAX_F32_gfx12
    UINT64_C(3628859392), UINT64_C(0),	// DS_MAX_F32_gfx6_gfx7
    UINT64_C(3626369024), UINT64_C(0),	// DS_MAX_F32_vi
    UINT64_C(3626369024), UINT64_C(0),	// DS_MAX_F32_vi_gfx9
    UINT64_C(3645636608), UINT64_C(0),	// DS_MAX_F64_gfx10
    UINT64_C(3645636608), UINT64_C(0),	// DS_MAX_F64_gfx11
    UINT64_C(3645636608), UINT64_C(0),	// DS_MAX_F64_gfx12
    UINT64_C(3645636608), UINT64_C(0),	// DS_MAX_F64_gfx6_gfx7
    UINT64_C(3634757632), UINT64_C(0),	// DS_MAX_F64_vi
    UINT64_C(3634757632), UINT64_C(0),	// DS_MAX_F64_vi_gfx9
    UINT64_C(3625451520), UINT64_C(0),	// DS_MAX_I32_gfx10
    UINT64_C(3625451520), UINT64_C(0),	// DS_MAX_I32_gfx11
    UINT64_C(3625451520), UINT64_C(0),	// DS_MAX_I32_gfx12
    UINT64_C(3625451520), UINT64_C(0),	// DS_MAX_I32_gfx6_gfx7
    UINT64_C(3624665088), UINT64_C(0),	// DS_MAX_I32_vi
    UINT64_C(3624665088), UINT64_C(0),	// DS_MAX_I32_vi_gfx9
    UINT64_C(3642228736), UINT64_C(0),	// DS_MAX_I64_gfx10
    UINT64_C(3642228736), UINT64_C(0),	// DS_MAX_I64_gfx11
    UINT64_C(3642228736), UINT64_C(0),	// DS_MAX_I64_gfx12
    UINT64_C(3642228736), UINT64_C(0),	// DS_MAX_I64_gfx6_gfx7
    UINT64_C(3633053696), UINT64_C(0),	// DS_MAX_I64_vi
    UINT64_C(3633053696), UINT64_C(0),	// DS_MAX_I64_vi_gfx9
    UINT64_C(3637248000), UINT64_C(0),	// DS_MAX_RTN_F32_gfx10
    UINT64_C(3637248000), UINT64_C(0),	// DS_MAX_RTN_F32_gfx11
    UINT64_C(3637248000), UINT64_C(0),	// DS_MAX_RTN_F32_gfx12
    UINT64_C(3637248000), UINT64_C(0),	// DS_MAX_RTN_F32_gfx6_gfx7
    UINT64_C(3630563328), UINT64_C(0),	// DS_MAX_RTN_F32_vi
    UINT64_C(3664117760), UINT64_C(0),	// DS_MAX_RTN_F32_vi_agpr
    UINT64_C(3630563328), UINT64_C(0),	// DS_MAX_RTN_F32_vi_gfx9
    UINT64_C(3654025216), UINT64_C(0),	// DS_MAX_RTN_F64_gfx10
    UINT64_C(3654025216), UINT64_C(0),	// DS_MAX_RTN_F64_gfx11
    UINT64_C(3654025216), UINT64_C(0),	// DS_MAX_RTN_F64_gfx12
    UINT64_C(3654025216), UINT64_C(0),	// DS_MAX_RTN_F64_gfx6_gfx7
    UINT64_C(3638951936), UINT64_C(0),	// DS_MAX_RTN_F64_vi
    UINT64_C(3672506368), UINT64_C(0),	// DS_MAX_RTN_F64_vi_agpr
    UINT64_C(3638951936), UINT64_C(0),	// DS_MAX_RTN_F64_vi_gfx9
    UINT64_C(3633840128), UINT64_C(0),	// DS_MAX_RTN_I32_gfx10
    UINT64_C(3633840128), UINT64_C(0),	// DS_MAX_RTN_I32_gfx11
    UINT64_C(3633840128), UINT64_C(0),	// DS_MAX_RTN_I32_gfx12
    UINT64_C(3633840128), UINT64_C(0),	// DS_MAX_RTN_I32_gfx6_gfx7
    UINT64_C(3628859392), UINT64_C(0),	// DS_MAX_RTN_I32_vi
    UINT64_C(3662413824), UINT64_C(0),	// DS_MAX_RTN_I32_vi_agpr
    UINT64_C(3628859392), UINT64_C(0),	// DS_MAX_RTN_I32_vi_gfx9
    UINT64_C(3650617344), UINT64_C(0),	// DS_MAX_RTN_I64_gfx10
    UINT64_C(3650617344), UINT64_C(0),	// DS_MAX_RTN_I64_gfx11
    UINT64_C(3650617344), UINT64_C(0),	// DS_MAX_RTN_I64_gfx12
    UINT64_C(3650617344), UINT64_C(0),	// DS_MAX_RTN_I64_gfx6_gfx7
    UINT64_C(3637248000), UINT64_C(0),	// DS_MAX_RTN_I64_vi
    UINT64_C(3670802432), UINT64_C(0),	// DS_MAX_RTN_I64_vi_agpr
    UINT64_C(3637248000), UINT64_C(0),	// DS_MAX_RTN_I64_vi_gfx9
    UINT64_C(3634364416), UINT64_C(0),	// DS_MAX_RTN_U32_gfx10
    UINT64_C(3634364416), UINT64_C(0),	// DS_MAX_RTN_U32_gfx11
    UINT64_C(3634364416), UINT64_C(0),	// DS_MAX_RTN_U32_gfx12
    UINT64_C(3634364416), UINT64_C(0),	// DS_MAX_RTN_U32_gfx6_gfx7
    UINT64_C(3629121536), UINT64_C(0),	// DS_MAX_RTN_U32_vi
    UINT64_C(3662675968), UINT64_C(0),	// DS_MAX_RTN_U32_vi_agpr
    UINT64_C(3629121536), UINT64_C(0),	// DS_MAX_RTN_U32_vi_gfx9
    UINT64_C(3651141632), UINT64_C(0),	// DS_MAX_RTN_U64_gfx10
    UINT64_C(3651141632), UINT64_C(0),	// DS_MAX_RTN_U64_gfx11
    UINT64_C(3651141632), UINT64_C(0),	// DS_MAX_RTN_U64_gfx12
    UINT64_C(3651141632), UINT64_C(0),	// DS_MAX_RTN_U64_gfx6_gfx7
    UINT64_C(3637510144), UINT64_C(0),	// DS_MAX_RTN_U64_vi
    UINT64_C(3671064576), UINT64_C(0),	// DS_MAX_RTN_U64_vi_agpr
    UINT64_C(3637510144), UINT64_C(0),	// DS_MAX_RTN_U64_vi_gfx9
    UINT64_C(3662413824), UINT64_C(0),	// DS_MAX_SRC2_F32_gfx10
    UINT64_C(3662413824), UINT64_C(0),	// DS_MAX_SRC2_F32_gfx6_gfx7
    UINT64_C(3643146240), UINT64_C(0),	// DS_MAX_SRC2_F32_vi
    UINT64_C(3679191040), UINT64_C(0),	// DS_MAX_SRC2_F64_gfx10
    UINT64_C(3679191040), UINT64_C(0),	// DS_MAX_SRC2_F64_gfx6_gfx7
    UINT64_C(3651534848), UINT64_C(0),	// DS_MAX_SRC2_F64_vi
    UINT64_C(3659005952), UINT64_C(0),	// DS_MAX_SRC2_I32_gfx10
    UINT64_C(3659005952), UINT64_C(0),	// DS_MAX_SRC2_I32_gfx6_gfx7
    UINT64_C(3641442304), UINT64_C(0),	// DS_MAX_SRC2_I32_vi
    UINT64_C(3675783168), UINT64_C(0),	// DS_MAX_SRC2_I64_gfx10
    UINT64_C(3675783168), UINT64_C(0),	// DS_MAX_SRC2_I64_gfx6_gfx7
    UINT64_C(3649830912), UINT64_C(0),	// DS_MAX_SRC2_I64_vi
    UINT64_C(3659530240), UINT64_C(0),	// DS_MAX_SRC2_U32_gfx10
    UINT64_C(3659530240), UINT64_C(0),	// DS_MAX_SRC2_U32_gfx6_gfx7
    UINT64_C(3641704448), UINT64_C(0),	// DS_MAX_SRC2_U32_vi
    UINT64_C(3676307456), UINT64_C(0),	// DS_MAX_SRC2_U64_gfx10
    UINT64_C(3676307456), UINT64_C(0),	// DS_MAX_SRC2_U64_gfx6_gfx7
    UINT64_C(3650093056), UINT64_C(0),	// DS_MAX_SRC2_U64_vi
    UINT64_C(3625975808), UINT64_C(0),	// DS_MAX_U32_gfx10
    UINT64_C(3625975808), UINT64_C(0),	// DS_MAX_U32_gfx11
    UINT64_C(3625975808), UINT64_C(0),	// DS_MAX_U32_gfx12
    UINT64_C(3625975808), UINT64_C(0),	// DS_MAX_U32_gfx6_gfx7
    UINT64_C(3624927232), UINT64_C(0),	// DS_MAX_U32_vi
    UINT64_C(3624927232), UINT64_C(0),	// DS_MAX_U32_vi_gfx9
    UINT64_C(3642753024), UINT64_C(0),	// DS_MAX_U64_gfx10
    UINT64_C(3642753024), UINT64_C(0),	// DS_MAX_U64_gfx11
    UINT64_C(3642753024), UINT64_C(0),	// DS_MAX_U64_gfx12
    UINT64_C(3642753024), UINT64_C(0),	// DS_MAX_U64_gfx6_gfx7
    UINT64_C(3633315840), UINT64_C(0),	// DS_MAX_U64_vi
    UINT64_C(3633315840), UINT64_C(0),	// DS_MAX_U64_vi_gfx9
    UINT64_C(3628597248), UINT64_C(0),	// DS_MIN_F32_gfx10
    UINT64_C(3628597248), UINT64_C(0),	// DS_MIN_F32_gfx11
    UINT64_C(3628597248), UINT64_C(0),	// DS_MIN_F32_gfx12
    UINT64_C(3628597248), UINT64_C(0),	// DS_MIN_F32_gfx6_gfx7
    UINT64_C(3626237952), UINT64_C(0),	// DS_MIN_F32_vi
    UINT64_C(3626237952), UINT64_C(0),	// DS_MIN_F32_vi_gfx9
    UINT64_C(3645374464), UINT64_C(0),	// DS_MIN_F64_gfx10
    UINT64_C(3645374464), UINT64_C(0),	// DS_MIN_F64_gfx11
    UINT64_C(3645374464), UINT64_C(0),	// DS_MIN_F64_gfx12
    UINT64_C(3645374464), UINT64_C(0),	// DS_MIN_F64_gfx6_gfx7
    UINT64_C(3634626560), UINT64_C(0),	// DS_MIN_F64_vi
    UINT64_C(3634626560), UINT64_C(0),	// DS_MIN_F64_vi_gfx9
    UINT64_C(3625189376), UINT64_C(0),	// DS_MIN_I32_gfx10
    UINT64_C(3625189376), UINT64_C(0),	// DS_MIN_I32_gfx11
    UINT64_C(3625189376), UINT64_C(0),	// DS_MIN_I32_gfx12
    UINT64_C(3625189376), UINT64_C(0),	// DS_MIN_I32_gfx6_gfx7
    UINT64_C(3624534016), UINT64_C(0),	// DS_MIN_I32_vi
    UINT64_C(3624534016), UINT64_C(0),	// DS_MIN_I32_vi_gfx9
    UINT64_C(3641966592), UINT64_C(0),	// DS_MIN_I64_gfx10
    UINT64_C(3641966592), UINT64_C(0),	// DS_MIN_I64_gfx11
    UINT64_C(3641966592), UINT64_C(0),	// DS_MIN_I64_gfx12
    UINT64_C(3641966592), UINT64_C(0),	// DS_MIN_I64_gfx6_gfx7
    UINT64_C(3632922624), UINT64_C(0),	// DS_MIN_I64_vi
    UINT64_C(3632922624), UINT64_C(0),	// DS_MIN_I64_vi_gfx9
    UINT64_C(3636985856), UINT64_C(0),	// DS_MIN_RTN_F32_gfx10
    UINT64_C(3636985856), UINT64_C(0),	// DS_MIN_RTN_F32_gfx11
    UINT64_C(3636985856), UINT64_C(0),	// DS_MIN_RTN_F32_gfx12
    UINT64_C(3636985856), UINT64_C(0),	// DS_MIN_RTN_F32_gfx6_gfx7
    UINT64_C(3630432256), UINT64_C(0),	// DS_MIN_RTN_F32_vi
    UINT64_C(3663986688), UINT64_C(0),	// DS_MIN_RTN_F32_vi_agpr
    UINT64_C(3630432256), UINT64_C(0),	// DS_MIN_RTN_F32_vi_gfx9
    UINT64_C(3653763072), UINT64_C(0),	// DS_MIN_RTN_F64_gfx10
    UINT64_C(3653763072), UINT64_C(0),	// DS_MIN_RTN_F64_gfx11
    UINT64_C(3653763072), UINT64_C(0),	// DS_MIN_RTN_F64_gfx12
    UINT64_C(3653763072), UINT64_C(0),	// DS_MIN_RTN_F64_gfx6_gfx7
    UINT64_C(3638820864), UINT64_C(0),	// DS_MIN_RTN_F64_vi
    UINT64_C(3672375296), UINT64_C(0),	// DS_MIN_RTN_F64_vi_agpr
    UINT64_C(3638820864), UINT64_C(0),	// DS_MIN_RTN_F64_vi_gfx9
    UINT64_C(3633577984), UINT64_C(0),	// DS_MIN_RTN_I32_gfx10
    UINT64_C(3633577984), UINT64_C(0),	// DS_MIN_RTN_I32_gfx11
    UINT64_C(3633577984), UINT64_C(0),	// DS_MIN_RTN_I32_gfx12
    UINT64_C(3633577984), UINT64_C(0),	// DS_MIN_RTN_I32_gfx6_gfx7
    UINT64_C(3628728320), UINT64_C(0),	// DS_MIN_RTN_I32_vi
    UINT64_C(3662282752), UINT64_C(0),	// DS_MIN_RTN_I32_vi_agpr
    UINT64_C(3628728320), UINT64_C(0),	// DS_MIN_RTN_I32_vi_gfx9
    UINT64_C(3650355200), UINT64_C(0),	// DS_MIN_RTN_I64_gfx10
    UINT64_C(3650355200), UINT64_C(0),	// DS_MIN_RTN_I64_gfx11
    UINT64_C(3650355200), UINT64_C(0),	// DS_MIN_RTN_I64_gfx12
    UINT64_C(3650355200), UINT64_C(0),	// DS_MIN_RTN_I64_gfx6_gfx7
    UINT64_C(3637116928), UINT64_C(0),	// DS_MIN_RTN_I64_vi
    UINT64_C(3670671360), UINT64_C(0),	// DS_MIN_RTN_I64_vi_agpr
    UINT64_C(3637116928), UINT64_C(0),	// DS_MIN_RTN_I64_vi_gfx9
    UINT64_C(3634102272), UINT64_C(0),	// DS_MIN_RTN_U32_gfx10
    UINT64_C(3634102272), UINT64_C(0),	// DS_MIN_RTN_U32_gfx11
    UINT64_C(3634102272), UINT64_C(0),	// DS_MIN_RTN_U32_gfx12
    UINT64_C(3634102272), UINT64_C(0),	// DS_MIN_RTN_U32_gfx6_gfx7
    UINT64_C(3628990464), UINT64_C(0),	// DS_MIN_RTN_U32_vi
    UINT64_C(3662544896), UINT64_C(0),	// DS_MIN_RTN_U32_vi_agpr
    UINT64_C(3628990464), UINT64_C(0),	// DS_MIN_RTN_U32_vi_gfx9
    UINT64_C(3650879488), UINT64_C(0),	// DS_MIN_RTN_U64_gfx10
    UINT64_C(3650879488), UINT64_C(0),	// DS_MIN_RTN_U64_gfx11
    UINT64_C(3650879488), UINT64_C(0),	// DS_MIN_RTN_U64_gfx12
    UINT64_C(3650879488), UINT64_C(0),	// DS_MIN_RTN_U64_gfx6_gfx7
    UINT64_C(3637379072), UINT64_C(0),	// DS_MIN_RTN_U64_vi
    UINT64_C(3670933504), UINT64_C(0),	// DS_MIN_RTN_U64_vi_agpr
    UINT64_C(3637379072), UINT64_C(0),	// DS_MIN_RTN_U64_vi_gfx9
    UINT64_C(3662151680), UINT64_C(0),	// DS_MIN_SRC2_F32_gfx10
    UINT64_C(3662151680), UINT64_C(0),	// DS_MIN_SRC2_F32_gfx6_gfx7
    UINT64_C(3643015168), UINT64_C(0),	// DS_MIN_SRC2_F32_vi
    UINT64_C(3678928896), UINT64_C(0),	// DS_MIN_SRC2_F64_gfx10
    UINT64_C(3678928896), UINT64_C(0),	// DS_MIN_SRC2_F64_gfx6_gfx7
    UINT64_C(3651403776), UINT64_C(0),	// DS_MIN_SRC2_F64_vi
    UINT64_C(3658743808), UINT64_C(0),	// DS_MIN_SRC2_I32_gfx10
    UINT64_C(3658743808), UINT64_C(0),	// DS_MIN_SRC2_I32_gfx6_gfx7
    UINT64_C(3641311232), UINT64_C(0),	// DS_MIN_SRC2_I32_vi
    UINT64_C(3675521024), UINT64_C(0),	// DS_MIN_SRC2_I64_gfx10
    UINT64_C(3675521024), UINT64_C(0),	// DS_MIN_SRC2_I64_gfx6_gfx7
    UINT64_C(3649699840), UINT64_C(0),	// DS_MIN_SRC2_I64_vi
    UINT64_C(3659268096), UINT64_C(0),	// DS_MIN_SRC2_U32_gfx10
    UINT64_C(3659268096), UINT64_C(0),	// DS_MIN_SRC2_U32_gfx6_gfx7
    UINT64_C(3641573376), UINT64_C(0),	// DS_MIN_SRC2_U32_vi
    UINT64_C(3676045312), UINT64_C(0),	// DS_MIN_SRC2_U64_gfx10
    UINT64_C(3676045312), UINT64_C(0),	// DS_MIN_SRC2_U64_gfx6_gfx7
    UINT64_C(3649961984), UINT64_C(0),	// DS_MIN_SRC2_U64_vi
    UINT64_C(3625713664), UINT64_C(0),	// DS_MIN_U32_gfx10
    UINT64_C(3625713664), UINT64_C(0),	// DS_MIN_U32_gfx11
    UINT64_C(3625713664), UINT64_C(0),	// DS_MIN_U32_gfx12
    UINT64_C(3625713664), UINT64_C(0),	// DS_MIN_U32_gfx6_gfx7
    UINT64_C(3624796160), UINT64_C(0),	// DS_MIN_U32_vi
    UINT64_C(3624796160), UINT64_C(0),	// DS_MIN_U32_vi_gfx9
    UINT64_C(3642490880), UINT64_C(0),	// DS_MIN_U64_gfx10
    UINT64_C(3642490880), UINT64_C(0),	// DS_MIN_U64_gfx11
    UINT64_C(3642490880), UINT64_C(0),	// DS_MIN_U64_gfx12
    UINT64_C(3642490880), UINT64_C(0),	// DS_MIN_U64_gfx6_gfx7
    UINT64_C(3633184768), UINT64_C(0),	// DS_MIN_U64_vi
    UINT64_C(3633184768), UINT64_C(0),	// DS_MIN_U64_vi_gfx9
    UINT64_C(3627024384), UINT64_C(0),	// DS_MSKOR_B32_gfx10
    UINT64_C(3627024384), UINT64_C(0),	// DS_MSKOR_B32_gfx11
    UINT64_C(3627024384), UINT64_C(0),	// DS_MSKOR_B32_gfx12
    UINT64_C(3627024384), UINT64_C(0),	// DS_MSKOR_B32_gfx6_gfx7
    UINT64_C(3625451520), UINT64_C(0),	// DS_MSKOR_B32_vi
    UINT64_C(3659005952), UINT64_C(0),	// DS_MSKOR_B32_vi_agpr
    UINT64_C(3625451520), UINT64_C(0),	// DS_MSKOR_B32_vi_gfx9
    UINT64_C(3643801600), UINT64_C(0),	// DS_MSKOR_B64_gfx10
    UINT64_C(3643801600), UINT64_C(0),	// DS_MSKOR_B64_gfx11
    UINT64_C(3643801600), UINT64_C(0),	// DS_MSKOR_B64_gfx12
    UINT64_C(3643801600), UINT64_C(0),	// DS_MSKOR_B64_gfx6_gfx7
    UINT64_C(3633840128), UINT64_C(0),	// DS_MSKOR_B64_vi
    UINT64_C(3667394560), UINT64_C(0),	// DS_MSKOR_B64_vi_agpr
    UINT64_C(3633840128), UINT64_C(0),	// DS_MSKOR_B64_vi_gfx9
    UINT64_C(3635412992), UINT64_C(0),	// DS_MSKOR_RTN_B32_gfx10
    UINT64_C(3635412992), UINT64_C(0),	// DS_MSKOR_RTN_B32_gfx11
    UINT64_C(3635412992), UINT64_C(0),	// DS_MSKOR_RTN_B32_gfx12
    UINT64_C(3635412992), UINT64_C(0),	// DS_MSKOR_RTN_B32_gfx6_gfx7
    UINT64_C(3629645824), UINT64_C(0),	// DS_MSKOR_RTN_B32_vi
    UINT64_C(3663200256), UINT64_C(0),	// DS_MSKOR_RTN_B32_vi_agpr
    UINT64_C(3629645824), UINT64_C(0),	// DS_MSKOR_RTN_B32_vi_gfx9
    UINT64_C(3652190208), UINT64_C(0),	// DS_MSKOR_RTN_B64_gfx10
    UINT64_C(3652190208), UINT64_C(0),	// DS_MSKOR_RTN_B64_gfx11
    UINT64_C(3652190208), UINT64_C(0),	// DS_MSKOR_RTN_B64_gfx12
    UINT64_C(3652190208), UINT64_C(0),	// DS_MSKOR_RTN_B64_gfx6_gfx7
    UINT64_C(3638034432), UINT64_C(0),	// DS_MSKOR_RTN_B64_vi
    UINT64_C(3671588864), UINT64_C(0),	// DS_MSKOR_RTN_B64_vi_agpr
    UINT64_C(3638034432), UINT64_C(0),	// DS_MSKOR_RTN_B64_vi_gfx9
    UINT64_C(3629121536), UINT64_C(0),	// DS_NOP_gfx10
    UINT64_C(3629121536), UINT64_C(0),	// DS_NOP_gfx11
    UINT64_C(3629121536), UINT64_C(0),	// DS_NOP_gfx12
    UINT64_C(3629121536), UINT64_C(0),	// DS_NOP_gfx6_gfx7
    UINT64_C(3626500096), UINT64_C(0),	// DS_NOP_vi
    UINT64_C(3640524800), UINT64_C(0),	// DS_ORDERED_COUNT_gfx10
    UINT64_C(3640524800), UINT64_C(0),	// DS_ORDERED_COUNT_gfx11
    UINT64_C(3640524800), UINT64_C(0),	// DS_ORDERED_COUNT_gfx6_gfx7
    UINT64_C(3648978944), UINT64_C(0),	// DS_ORDERED_COUNT_vi
    UINT64_C(3626500096), UINT64_C(0),	// DS_OR_B32_gfx10
    UINT64_C(3626500096), UINT64_C(0),	// DS_OR_B32_gfx11
    UINT64_C(3626500096), UINT64_C(0),	// DS_OR_B32_gfx12
    UINT64_C(3626500096), UINT64_C(0),	// DS_OR_B32_gfx6_gfx7
    UINT64_C(3625189376), UINT64_C(0),	// DS_OR_B32_vi
    UINT64_C(3625189376), UINT64_C(0),	// DS_OR_B32_vi_gfx9
    UINT64_C(3643277312), UINT64_C(0),	// DS_OR_B64_gfx10
    UINT64_C(3643277312), UINT64_C(0),	// DS_OR_B64_gfx11
    UINT64_C(3643277312), UINT64_C(0),	// DS_OR_B64_gfx12
    UINT64_C(3643277312), UINT64_C(0),	// DS_OR_B64_gfx6_gfx7
    UINT64_C(3633577984), UINT64_C(0),	// DS_OR_B64_vi
    UINT64_C(3633577984), UINT64_C(0),	// DS_OR_B64_vi_gfx9
    UINT64_C(3634888704), UINT64_C(0),	// DS_OR_RTN_B32_gfx10
    UINT64_C(3634888704), UINT64_C(0),	// DS_OR_RTN_B32_gfx11
    UINT64_C(3634888704), UINT64_C(0),	// DS_OR_RTN_B32_gfx12
    UINT64_C(3634888704), UINT64_C(0),	// DS_OR_RTN_B32_gfx6_gfx7
    UINT64_C(3629383680), UINT64_C(0),	// DS_OR_RTN_B32_vi
    UINT64_C(3662938112), UINT64_C(0),	// DS_OR_RTN_B32_vi_agpr
    UINT64_C(3629383680), UINT64_C(0),	// DS_OR_RTN_B32_vi_gfx9
    UINT64_C(3651665920), UINT64_C(0),	// DS_OR_RTN_B64_gfx10
    UINT64_C(3651665920), UINT64_C(0),	// DS_OR_RTN_B64_gfx11
    UINT64_C(3651665920), UINT64_C(0),	// DS_OR_RTN_B64_gfx12
    UINT64_C(3651665920), UINT64_C(0),	// DS_OR_RTN_B64_gfx6_gfx7
    UINT64_C(3637772288), UINT64_C(0),	// DS_OR_RTN_B64_vi
    UINT64_C(3671326720), UINT64_C(0),	// DS_OR_RTN_B64_vi_agpr
    UINT64_C(3637772288), UINT64_C(0),	// DS_OR_RTN_B64_vi_gfx9
    UINT64_C(3660054528), UINT64_C(0),	// DS_OR_SRC2_B32_gfx10
    UINT64_C(3660054528), UINT64_C(0),	// DS_OR_SRC2_B32_gfx6_gfx7
    UINT64_C(3641966592), UINT64_C(0),	// DS_OR_SRC2_B32_vi
    UINT64_C(3676831744), UINT64_C(0),	// DS_OR_SRC2_B64_gfx10
    UINT64_C(3676831744), UINT64_C(0),	// DS_OR_SRC2_B64_gfx6_gfx7
    UINT64_C(3650355200), UINT64_C(0),	// DS_OR_SRC2_B64_vi
    UINT64_C(3456106496), UINT64_C(0),	// DS_PARAM_LOAD_gfx12
    UINT64_C(3670540288), UINT64_C(0),	// DS_PERMUTE_B32_gfx10
    UINT64_C(3670540288), UINT64_C(0),	// DS_PERMUTE_B32_gfx11
    UINT64_C(3670540288), UINT64_C(0),	// DS_PERMUTE_B32_gfx12
    UINT64_C(3632005120), UINT64_C(0),	// DS_PERMUTE_B32_vi
    UINT64_C(3665559552), UINT64_C(0),	// DS_PERMUTE_B32_vi_agpr
    UINT64_C(3664510976), UINT64_C(0),	// DS_PK_ADD_BF16_gfx12
    UINT64_C(3627024384), UINT64_C(0),	// DS_PK_ADD_BF16_vi
    UINT64_C(3664248832), UINT64_C(0),	// DS_PK_ADD_F16_gfx12
    UINT64_C(3626893312), UINT64_C(0),	// DS_PK_ADD_F16_vi
    UINT64_C(3668705280), UINT64_C(0),	// DS_PK_ADD_RTN_BF16_gfx12
    UINT64_C(3647995904), UINT64_C(0),	// DS_PK_ADD_RTN_BF16_vi
    UINT64_C(3681550336), UINT64_C(0),	// DS_PK_ADD_RTN_BF16_vi_agpr
    UINT64_C(3668443136), UINT64_C(0),	// DS_PK_ADD_RTN_F16_gfx12
    UINT64_C(3647864832), UINT64_C(0),	// DS_PK_ADD_RTN_F16_vi
    UINT64_C(3681419264), UINT64_C(0),	// DS_PK_ADD_RTN_F16_vi_agpr
    UINT64_C(3638558720), UINT64_C(0),	// DS_READ2ST64_B32_gfx10
    UINT64_C(3638558720), UINT64_C(0),	// DS_READ2ST64_B32_gfx11
    UINT64_C(3638558720), UINT64_C(0),	// DS_READ2ST64_B32_gfx12
    UINT64_C(3638558720), UINT64_C(0),	// DS_READ2ST64_B32_gfx6_gfx7
    UINT64_C(3631218688), UINT64_C(0),	// DS_READ2ST64_B32_vi
    UINT64_C(3631218688), UINT64_C(0),	// DS_READ2ST64_B32_vi_gfx9
    UINT64_C(3655335936), UINT64_C(0),	// DS_READ2ST64_B64_gfx10
    UINT64_C(3655335936), UINT64_C(0),	// DS_READ2ST64_B64_gfx11
    UINT64_C(3655335936), UINT64_C(0),	// DS_READ2ST64_B64_gfx12
    UINT64_C(3655335936), UINT64_C(0),	// DS_READ2ST64_B64_gfx6_gfx7
    UINT64_C(3639607296), UINT64_C(0),	// DS_READ2ST64_B64_vi
    UINT64_C(3639607296), UINT64_C(0),	// DS_READ2ST64_B64_vi_gfx9
    UINT64_C(3638296576), UINT64_C(0),	// DS_READ2_B32_gfx10
    UINT64_C(3638296576), UINT64_C(0),	// DS_READ2_B32_gfx11
    UINT64_C(3638296576), UINT64_C(0),	// DS_READ2_B32_gfx12
    UINT64_C(3638296576), UINT64_C(0),	// DS_READ2_B32_gfx6_gfx7
    UINT64_C(3631087616), UINT64_C(0),	// DS_READ2_B32_vi
    UINT64_C(3631087616), UINT64_C(0),	// DS_READ2_B32_vi_gfx9
    UINT64_C(3655073792), UINT64_C(0),	// DS_READ2_B64_gfx10
    UINT64_C(3655073792), UINT64_C(0),	// DS_READ2_B64_gfx11
    UINT64_C(3655073792), UINT64_C(0),	// DS_READ2_B64_gfx12
    UINT64_C(3655073792), UINT64_C(0),	// DS_READ2_B64_gfx6_gfx7
    UINT64_C(3639476224), UINT64_C(0),	// DS_READ2_B64_vi
    UINT64_C(3639476224), UINT64_C(0),	// DS_READ2_B64_vi_gfx9
    UINT64_C(3670278144), UINT64_C(0),	// DS_READ_ADDTID_B32_gfx10
    UINT64_C(3670278144), UINT64_C(0),	// DS_READ_ADDTID_B32_gfx11
    UINT64_C(3670278144), UINT64_C(0),	// DS_READ_ADDTID_B32_gfx12
    UINT64_C(3647733760), UINT64_C(0),	// DS_READ_ADDTID_B32_vi
    UINT64_C(3690725376), UINT64_C(0),	// DS_READ_B128_gfx10
    UINT64_C(3690725376), UINT64_C(0),	// DS_READ_B128_gfx11
    UINT64_C(3690725376), UINT64_C(0),	// DS_READ_B128_gfx12
    UINT64_C(3690725376), UINT64_C(0),	// DS_READ_B128_gfx7
    UINT64_C(3657302016), UINT64_C(0),	// DS_READ_B128_vi
    UINT64_C(3657302016), UINT64_C(0),	// DS_READ_B128_vi_gfx9
    UINT64_C(3638034432), UINT64_C(0),	// DS_READ_B32_gfx10
    UINT64_C(3638034432), UINT64_C(0),	// DS_READ_B32_gfx11
    UINT64_C(3638034432), UINT64_C(0),	// DS_READ_B32_gfx12
    UINT64_C(3638034432), UINT64_C(0),	// DS_READ_B32_gfx6_gfx7
    UINT64_C(3630956544), UINT64_C(0),	// DS_READ_B32_vi
    UINT64_C(3630956544), UINT64_C(0),	// DS_READ_B32_vi_gfx9
    UINT64_C(3653632000), UINT64_C(0),	// DS_READ_B64_TR_B16_vi
    UINT64_C(3653238784), UINT64_C(0),	// DS_READ_B64_TR_B4_vi
    UINT64_C(3653500928), UINT64_C(0),	// DS_READ_B64_TR_B8_vi
    UINT64_C(3654811648), UINT64_C(0),	// DS_READ_B64_gfx10
    UINT64_C(3654811648), UINT64_C(0),	// DS_READ_B64_gfx11
    UINT64_C(3654811648), UINT64_C(0),	// DS_READ_B64_gfx12
    UINT64_C(3654811648), UINT64_C(0),	// DS_READ_B64_gfx6_gfx7
    UINT64_C(3639345152), UINT64_C(0),	// DS_READ_B64_vi
    UINT64_C(3639345152), UINT64_C(0),	// DS_READ_B64_vi_gfx9
    UINT64_C(3653369856), UINT64_C(0),	// DS_READ_B96_TR_B6_vi
    UINT64_C(3690463232), UINT64_C(0),	// DS_READ_B96_gfx10
    UINT64_C(3690463232), UINT64_C(0),	// DS_READ_B96_gfx11
    UINT64_C(3690463232), UINT64_C(0),	// DS_READ_B96_gfx12
    UINT64_C(3690463232), UINT64_C(0),	// DS_READ_B96_gfx7
    UINT64_C(3657170944), UINT64_C(0),	// DS_READ_B96_vi
    UINT64_C(3657170944), UINT64_C(0),	// DS_READ_B96_vi_gfx9
    UINT64_C(3639345152), UINT64_C(0),	// DS_READ_I16_gfx10
    UINT64_C(3639345152), UINT64_C(0),	// DS_READ_I16_gfx11
    UINT64_C(3639345152), UINT64_C(0),	// DS_READ_I16_gfx12
    UINT64_C(3639345152), UINT64_C(0),	// DS_READ_I16_gfx6_gfx7
    UINT64_C(3631611904), UINT64_C(0),	// DS_READ_I16_vi
    UINT64_C(3631611904), UINT64_C(0),	// DS_READ_I16_vi_gfx9
    UINT64_C(3667132416), UINT64_C(0),	// DS_READ_I8_D16_HI_gfx10
    UINT64_C(3667132416), UINT64_C(0),	// DS_READ_I8_D16_HI_gfx11
    UINT64_C(3667132416), UINT64_C(0),	// DS_READ_I8_D16_HI_gfx12
    UINT64_C(3635544064), UINT64_C(0),	// DS_READ_I8_D16_HI_vi
    UINT64_C(3666870272), UINT64_C(0),	// DS_READ_I8_D16_gfx10
    UINT64_C(3666870272), UINT64_C(0),	// DS_READ_I8_D16_gfx11
    UINT64_C(3666870272), UINT64_C(0),	// DS_READ_I8_D16_gfx12
    UINT64_C(3635412992), UINT64_C(0),	// DS_READ_I8_D16_vi
    UINT64_C(3638820864), UINT64_C(0),	// DS_READ_I8_gfx10
    UINT64_C(3638820864), UINT64_C(0),	// DS_READ_I8_gfx11
    UINT64_C(3638820864), UINT64_C(0),	// DS_READ_I8_gfx12
    UINT64_C(3638820864), UINT64_C(0),	// DS_READ_I8_gfx6_gfx7
    UINT64_C(3631349760), UINT64_C(0),	// DS_READ_I8_vi
    UINT64_C(3631349760), UINT64_C(0),	// DS_READ_I8_vi_gfx9
    UINT64_C(3667656704), UINT64_C(0),	// DS_READ_U16_D16_HI_gfx10
    UINT64_C(3667656704), UINT64_C(0),	// DS_READ_U16_D16_HI_gfx11
    UINT64_C(3667656704), UINT64_C(0),	// DS_READ_U16_D16_HI_gfx12
    UINT64_C(3635806208), UINT64_C(0),	// DS_READ_U16_D16_HI_vi
    UINT64_C(3667394560), UINT64_C(0),	// DS_READ_U16_D16_gfx10
    UINT64_C(3667394560), UINT64_C(0),	// DS_READ_U16_D16_gfx11
    UINT64_C(3667394560), UINT64_C(0),	// DS_READ_U16_D16_gfx12
    UINT64_C(3635675136), UINT64_C(0),	// DS_READ_U16_D16_vi
    UINT64_C(3639607296), UINT64_C(0),	// DS_READ_U16_gfx10
    UINT64_C(3639607296), UINT64_C(0),	// DS_READ_U16_gfx11
    UINT64_C(3639607296), UINT64_C(0),	// DS_READ_U16_gfx12
    UINT64_C(3639607296), UINT64_C(0),	// DS_READ_U16_gfx6_gfx7
    UINT64_C(3631742976), UINT64_C(0),	// DS_READ_U16_vi
    UINT64_C(3631742976), UINT64_C(0),	// DS_READ_U16_vi_gfx9
    UINT64_C(3666608128), UINT64_C(0),	// DS_READ_U8_D16_HI_gfx10
    UINT64_C(3666608128), UINT64_C(0),	// DS_READ_U8_D16_HI_gfx11
    UINT64_C(3666608128), UINT64_C(0),	// DS_READ_U8_D16_HI_gfx12
    UINT64_C(3635281920), UINT64_C(0),	// DS_READ_U8_D16_HI_vi
    UINT64_C(3666345984), UINT64_C(0),	// DS_READ_U8_D16_gfx10
    UINT64_C(3666345984), UINT64_C(0),	// DS_READ_U8_D16_gfx11
    UINT64_C(3666345984), UINT64_C(0),	// DS_READ_U8_D16_gfx12
    UINT64_C(3635150848), UINT64_C(0),	// DS_READ_U8_D16_vi
    UINT64_C(3639083008), UINT64_C(0),	// DS_READ_U8_gfx10
    UINT64_C(3639083008), UINT64_C(0),	// DS_READ_U8_gfx11
    UINT64_C(3639083008), UINT64_C(0),	// DS_READ_U8_gfx12
    UINT64_C(3639083008), UINT64_C(0),	// DS_READ_U8_gfx6_gfx7
    UINT64_C(3631480832), UINT64_C(0),	// DS_READ_U8_vi
    UINT64_C(3631480832), UINT64_C(0),	// DS_READ_U8_vi_gfx9
    UINT64_C(3632791552), UINT64_C(0),	// DS_RSUB_RTN_U32_gfx10
    UINT64_C(3632791552), UINT64_C(0),	// DS_RSUB_RTN_U32_gfx11
    UINT64_C(3632791552), UINT64_C(0),	// DS_RSUB_RTN_U32_gfx12
    UINT64_C(3632791552), UINT64_C(0),	// DS_RSUB_RTN_U32_gfx6_gfx7
    UINT64_C(3628335104), UINT64_C(0),	// DS_RSUB_RTN_U32_vi
    UINT64_C(3661889536), UINT64_C(0),	// DS_RSUB_RTN_U32_vi_agpr
    UINT64_C(3628335104), UINT64_C(0),	// DS_RSUB_RTN_U32_vi_gfx9
    UINT64_C(3649568768), UINT64_C(0),	// DS_RSUB_RTN_U64_gfx10
    UINT64_C(3649568768), UINT64_C(0),	// DS_RSUB_RTN_U64_gfx11
    UINT64_C(3649568768), UINT64_C(0),	// DS_RSUB_RTN_U64_gfx12
    UINT64_C(3649568768), UINT64_C(0),	// DS_RSUB_RTN_U64_gfx6_gfx7
    UINT64_C(3636723712), UINT64_C(0),	// DS_RSUB_RTN_U64_vi
    UINT64_C(3670278144), UINT64_C(0),	// DS_RSUB_RTN_U64_vi_agpr
    UINT64_C(3636723712), UINT64_C(0),	// DS_RSUB_RTN_U64_vi_gfx9
    UINT64_C(3657957376), UINT64_C(0),	// DS_RSUB_SRC2_U32_gfx10
    UINT64_C(3657957376), UINT64_C(0),	// DS_RSUB_SRC2_U32_gfx6_gfx7
    UINT64_C(3640918016), UINT64_C(0),	// DS_RSUB_SRC2_U32_vi
    UINT64_C(3674734592), UINT64_C(0),	// DS_RSUB_SRC2_U64_gfx10
    UINT64_C(3674734592), UINT64_C(0),	// DS_RSUB_SRC2_U64_gfx6_gfx7
    UINT64_C(3649306624), UINT64_C(0),	// DS_RSUB_SRC2_U64_vi
    UINT64_C(3624402944), UINT64_C(0),	// DS_RSUB_U32_gfx10
    UINT64_C(3624402944), UINT64_C(0),	// DS_RSUB_U32_gfx11
    UINT64_C(3624402944), UINT64_C(0),	// DS_RSUB_U32_gfx12
    UINT64_C(3624402944), UINT64_C(0),	// DS_RSUB_U32_gfx6_gfx7
    UINT64_C(3624140800), UINT64_C(0),	// DS_RSUB_U32_vi
    UINT64_C(3624140800), UINT64_C(0),	// DS_RSUB_U32_vi_gfx9
    UINT64_C(3641180160), UINT64_C(0),	// DS_RSUB_U64_gfx10
    UINT64_C(3641180160), UINT64_C(0),	// DS_RSUB_U64_gfx11
    UINT64_C(3641180160), UINT64_C(0),	// DS_RSUB_U64_gfx12
    UINT64_C(3641180160), UINT64_C(0),	// DS_RSUB_U64_gfx6_gfx7
    UINT64_C(3632529408), UINT64_C(0),	// DS_RSUB_U64_vi
    UINT64_C(3632529408), UINT64_C(0),	// DS_RSUB_U64_vi_gfx9
    UINT64_C(3668180992), UINT64_C(0),	// DS_SUB_CLAMP_RTN_U32_gfx12
    UINT64_C(3663986688), UINT64_C(0),	// DS_SUB_CLAMP_U32_gfx12
    UINT64_C(3656253440), UINT64_C(0),	// DS_SUB_GS_REG_RTN_gfx11
    UINT64_C(3632529408), UINT64_C(0),	// DS_SUB_RTN_U32_gfx10
    UINT64_C(3632529408), UINT64_C(0),	// DS_SUB_RTN_U32_gfx11
    UINT64_C(3632529408), UINT64_C(0),	// DS_SUB_RTN_U32_gfx12
    UINT64_C(3632529408), UINT64_C(0),	// DS_SUB_RTN_U32_gfx6_gfx7
    UINT64_C(3628204032), UINT64_C(0),	// DS_SUB_RTN_U32_vi
    UINT64_C(3661758464), UINT64_C(0),	// DS_SUB_RTN_U32_vi_agpr
    UINT64_C(3628204032), UINT64_C(0),	// DS_SUB_RTN_U32_vi_gfx9
    UINT64_C(3649306624), UINT64_C(0),	// DS_SUB_RTN_U64_gfx10
    UINT64_C(3649306624), UINT64_C(0),	// DS_SUB_RTN_U64_gfx11
    UINT64_C(3649306624), UINT64_C(0),	// DS_SUB_RTN_U64_gfx12
    UINT64_C(3649306624), UINT64_C(0),	// DS_SUB_RTN_U64_gfx6_gfx7
    UINT64_C(3636592640), UINT64_C(0),	// DS_SUB_RTN_U64_vi
    UINT64_C(3670147072), UINT64_C(0),	// DS_SUB_RTN_U64_vi_agpr
    UINT64_C(3636592640), UINT64_C(0),	// DS_SUB_RTN_U64_vi_gfx9
    UINT64_C(3657695232), UINT64_C(0),	// DS_SUB_SRC2_U32_gfx10
    UINT64_C(3657695232), UINT64_C(0),	// DS_SUB_SRC2_U32_gfx6_gfx7
    UINT64_C(3640786944), UINT64_C(0),	// DS_SUB_SRC2_U32_vi
    UINT64_C(3674472448), UINT64_C(0),	// DS_SUB_SRC2_U64_gfx10
    UINT64_C(3674472448), UINT64_C(0),	// DS_SUB_SRC2_U64_gfx6_gfx7
    UINT64_C(3649175552), UINT64_C(0),	// DS_SUB_SRC2_U64_vi
    UINT64_C(3624140800), UINT64_C(0),	// DS_SUB_U32_gfx10
    UINT64_C(3624140800), UINT64_C(0),	// DS_SUB_U32_gfx11
    UINT64_C(3624140800), UINT64_C(0),	// DS_SUB_U32_gfx12
    UINT64_C(3624140800), UINT64_C(0),	// DS_SUB_U32_gfx6_gfx7
    UINT64_C(3624009728), UINT64_C(0),	// DS_SUB_U32_vi
    UINT64_C(3624009728), UINT64_C(0),	// DS_SUB_U32_vi_gfx9
    UINT64_C(3640918016), UINT64_C(0),	// DS_SUB_U64_gfx10
    UINT64_C(3640918016), UINT64_C(0),	// DS_SUB_U64_gfx11
    UINT64_C(3640918016), UINT64_C(0),	// DS_SUB_U64_gfx12
    UINT64_C(3640918016), UINT64_C(0),	// DS_SUB_U64_gfx6_gfx7
    UINT64_C(3632398336), UINT64_C(0),	// DS_SUB_U64_vi
    UINT64_C(3632398336), UINT64_C(0),	// DS_SUB_U64_vi_gfx9
    UINT64_C(3637772288), UINT64_C(0),	// DS_SWIZZLE_B32_gfx10
    UINT64_C(3637772288), UINT64_C(0),	// DS_SWIZZLE_B32_gfx11
    UINT64_C(3637772288), UINT64_C(0),	// DS_SWIZZLE_B32_gfx12
    UINT64_C(3637772288), UINT64_C(0),	// DS_SWIZZLE_B32_gfx6_gfx7
    UINT64_C(3631874048), UINT64_C(0),	// DS_SWIZZLE_B32_vi
    UINT64_C(3637510144), UINT64_C(0),	// DS_WRAP_RTN_B32_gfx10
    UINT64_C(3637510144), UINT64_C(0),	// DS_WRAP_RTN_B32_gfx11
    UINT64_C(3637510144), UINT64_C(0),	// DS_WRAP_RTN_B32_gfx7
    UINT64_C(3630694400), UINT64_C(0),	// DS_WRAP_RTN_B32_vi
    UINT64_C(3664248832), UINT64_C(0),	// DS_WRAP_RTN_B32_vi_agpr
    UINT64_C(3630694400), UINT64_C(0),	// DS_WRAP_RTN_B32_vi_gfx9
    UINT64_C(3627810816), UINT64_C(0),	// DS_WRITE2ST64_B32_gfx10
    UINT64_C(3627810816), UINT64_C(0),	// DS_WRITE2ST64_B32_gfx11
    UINT64_C(3627810816), UINT64_C(0),	// DS_WRITE2ST64_B32_gfx12
    UINT64_C(3627810816), UINT64_C(0),	// DS_WRITE2ST64_B32_gfx6_gfx7
    UINT64_C(3625844736), UINT64_C(0),	// DS_WRITE2ST64_B32_vi
    UINT64_C(3659399168), UINT64_C(0),	// DS_WRITE2ST64_B32_vi_agpr
    UINT64_C(3625844736), UINT64_C(0),	// DS_WRITE2ST64_B32_vi_gfx9
    UINT64_C(3644588032), UINT64_C(0),	// DS_WRITE2ST64_B64_gfx10
    UINT64_C(3644588032), UINT64_C(0),	// DS_WRITE2ST64_B64_gfx11
    UINT64_C(3644588032), UINT64_C(0),	// DS_WRITE2ST64_B64_gfx12
    UINT64_C(3644588032), UINT64_C(0),	// DS_WRITE2ST64_B64_gfx6_gfx7
    UINT64_C(3634233344), UINT64_C(0),	// DS_WRITE2ST64_B64_vi
    UINT64_C(3667787776), UINT64_C(0),	// DS_WRITE2ST64_B64_vi_agpr
    UINT64_C(3634233344), UINT64_C(0),	// DS_WRITE2ST64_B64_vi_gfx9
    UINT64_C(3627548672), UINT64_C(0),	// DS_WRITE2_B32_gfx10
    UINT64_C(3627548672), UINT64_C(0),	// DS_WRITE2_B32_gfx11
    UINT64_C(3627548672), UINT64_C(0),	// DS_WRITE2_B32_gfx12
    UINT64_C(3627548672), UINT64_C(0),	// DS_WRITE2_B32_gfx6_gfx7
    UINT64_C(3625713664), UINT64_C(0),	// DS_WRITE2_B32_vi
    UINT64_C(3659268096), UINT64_C(0),	// DS_WRITE2_B32_vi_agpr
    UINT64_C(3625713664), UINT64_C(0),	// DS_WRITE2_B32_vi_gfx9
    UINT64_C(3644325888), UINT64_C(0),	// DS_WRITE2_B64_gfx10
    UINT64_C(3644325888), UINT64_C(0),	// DS_WRITE2_B64_gfx11
    UINT64_C(3644325888), UINT64_C(0),	// DS_WRITE2_B64_gfx12
    UINT64_C(3644325888), UINT64_C(0),	// DS_WRITE2_B64_gfx6_gfx7
    UINT64_C(3634102272), UINT64_C(0),	// DS_WRITE2_B64_vi
    UINT64_C(3667656704), UINT64_C(0),	// DS_WRITE2_B64_vi_agpr
    UINT64_C(3634102272), UINT64_C(0),	// DS_WRITE2_B64_vi_gfx9
    UINT64_C(3670016000), UINT64_C(0),	// DS_WRITE_ADDTID_B32_gfx10
    UINT64_C(3670016000), UINT64_C(0),	// DS_WRITE_ADDTID_B32_gfx11
    UINT64_C(3670016000), UINT64_C(0),	// DS_WRITE_ADDTID_B32_gfx12
    UINT64_C(3627679744), UINT64_C(0),	// DS_WRITE_ADDTID_B32_vi
    UINT64_C(3682336768), UINT64_C(0),	// DS_WRITE_B128_gfx10
    UINT64_C(3682336768), UINT64_C(0),	// DS_WRITE_B128_gfx11
    UINT64_C(3682336768), UINT64_C(0),	// DS_WRITE_B128_gfx12
    UINT64_C(3682336768), UINT64_C(0),	// DS_WRITE_B128_gfx7
    UINT64_C(3653107712), UINT64_C(0),	// DS_WRITE_B128_vi
    UINT64_C(3653107712), UINT64_C(0),	// DS_WRITE_B128_vi_gfx9
    UINT64_C(3666083840), UINT64_C(0),	// DS_WRITE_B16_D16_HI_gfx10
    UINT64_C(3666083840), UINT64_C(0),	// DS_WRITE_B16_D16_HI_gfx11
    UINT64_C(3666083840), UINT64_C(0),	// DS_WRITE_B16_D16_HI_gfx12
    UINT64_C(3635019776), UINT64_C(0),	// DS_WRITE_B16_D16_HI_vi
    UINT64_C(3632005120), UINT64_C(0),	// DS_WRITE_B16_gfx10
    UINT64_C(3632005120), UINT64_C(0),	// DS_WRITE_B16_gfx11
    UINT64_C(3632005120), UINT64_C(0),	// DS_WRITE_B16_gfx12
    UINT64_C(3632005120), UINT64_C(0),	// DS_WRITE_B16_gfx6_gfx7
    UINT64_C(3627941888), UINT64_C(0),	// DS_WRITE_B16_vi
    UINT64_C(3627941888), UINT64_C(0),	// DS_WRITE_B16_vi_gfx9
    UINT64_C(3627286528), UINT64_C(0),	// DS_WRITE_B32_gfx10
    UINT64_C(3627286528), UINT64_C(0),	// DS_WRITE_B32_gfx11
    UINT64_C(3627286528), UINT64_C(0),	// DS_WRITE_B32_gfx12
    UINT64_C(3627286528), UINT64_C(0),	// DS_WRITE_B32_gfx6_gfx7
    UINT64_C(3625582592), UINT64_C(0),	// DS_WRITE_B32_vi
    UINT64_C(3625582592), UINT64_C(0),	// DS_WRITE_B32_vi_gfx9
    UINT64_C(3644063744), UINT64_C(0),	// DS_WRITE_B64_gfx10
    UINT64_C(3644063744), UINT64_C(0),	// DS_WRITE_B64_gfx11
    UINT64_C(3644063744), UINT64_C(0),	// DS_WRITE_B64_gfx12
    UINT64_C(3644063744), UINT64_C(0),	// DS_WRITE_B64_gfx6_gfx7
    UINT64_C(3633971200), UINT64_C(0),	// DS_WRITE_B64_vi
    UINT64_C(3633971200), UINT64_C(0),	// DS_WRITE_B64_vi_gfx9
    UINT64_C(3665821696), UINT64_C(0),	// DS_WRITE_B8_D16_HI_gfx10
    UINT64_C(3665821696), UINT64_C(0),	// DS_WRITE_B8_D16_HI_gfx11
    UINT64_C(3665821696), UINT64_C(0),	// DS_WRITE_B8_D16_HI_gfx12
    UINT64_C(3634888704), UINT64_C(0),	// DS_WRITE_B8_D16_HI_vi
    UINT64_C(3631742976), UINT64_C(0),	// DS_WRITE_B8_gfx10
    UINT64_C(3631742976), UINT64_C(0),	// DS_WRITE_B8_gfx11
    UINT64_C(3631742976), UINT64_C(0),	// DS_WRITE_B8_gfx12
    UINT64_C(3631742976), UINT64_C(0),	// DS_WRITE_B8_gfx6_gfx7
    UINT64_C(3627810816), UINT64_C(0),	// DS_WRITE_B8_vi
    UINT64_C(3627810816), UINT64_C(0),	// DS_WRITE_B8_vi_gfx9
    UINT64_C(3682074624), UINT64_C(0),	// DS_WRITE_B96_gfx10
    UINT64_C(3682074624), UINT64_C(0),	// DS_WRITE_B96_gfx11
    UINT64_C(3682074624), UINT64_C(0),	// DS_WRITE_B96_gfx12
    UINT64_C(3682074624), UINT64_C(0),	// DS_WRITE_B96_gfx7
    UINT64_C(3652976640), UINT64_C(0),	// DS_WRITE_B96_vi
    UINT64_C(3652976640), UINT64_C(0),	// DS_WRITE_B96_vi_gfx9
    UINT64_C(3660840960), UINT64_C(0),	// DS_WRITE_SRC2_B32_gfx10
    UINT64_C(3660840960), UINT64_C(0),	// DS_WRITE_SRC2_B32_gfx6_gfx7
    UINT64_C(3642359808), UINT64_C(0),	// DS_WRITE_SRC2_B32_vi
    UINT64_C(3677618176), UINT64_C(0),	// DS_WRITE_SRC2_B64_gfx10
    UINT64_C(3677618176), UINT64_C(0),	// DS_WRITE_SRC2_B64_gfx6_gfx7
    UINT64_C(3650748416), UINT64_C(0),	// DS_WRITE_SRC2_B64_vi
    UINT64_C(3636199424), UINT64_C(0),	// DS_WRXCHG2ST64_RTN_B32_gfx10
    UINT64_C(3636199424), UINT64_C(0),	// DS_WRXCHG2ST64_RTN_B32_gfx11
    UINT64_C(3636199424), UINT64_C(0),	// DS_WRXCHG2ST64_RTN_B32_gfx12
    UINT64_C(3636199424), UINT64_C(0),	// DS_WRXCHG2ST64_RTN_B32_gfx6_gfx7
    UINT64_C(3630039040), UINT64_C(0),	// DS_WRXCHG2ST64_RTN_B32_vi
    UINT64_C(3663593472), UINT64_C(0),	// DS_WRXCHG2ST64_RTN_B32_vi_agpr
    UINT64_C(3630039040), UINT64_C(0),	// DS_WRXCHG2ST64_RTN_B32_vi_gfx9
    UINT64_C(3652976640), UINT64_C(0),	// DS_WRXCHG2ST64_RTN_B64_gfx10
    UINT64_C(3652976640), UINT64_C(0),	// DS_WRXCHG2ST64_RTN_B64_gfx11
    UINT64_C(3652976640), UINT64_C(0),	// DS_WRXCHG2ST64_RTN_B64_gfx12
    UINT64_C(3652976640), UINT64_C(0),	// DS_WRXCHG2ST64_RTN_B64_gfx6_gfx7
    UINT64_C(3638427648), UINT64_C(0),	// DS_WRXCHG2ST64_RTN_B64_vi
    UINT64_C(3671982080), UINT64_C(0),	// DS_WRXCHG2ST64_RTN_B64_vi_agpr
    UINT64_C(3638427648), UINT64_C(0),	// DS_WRXCHG2ST64_RTN_B64_vi_gfx9
    UINT64_C(3635937280), UINT64_C(0),	// DS_WRXCHG2_RTN_B32_gfx10
    UINT64_C(3635937280), UINT64_C(0),	// DS_WRXCHG2_RTN_B32_gfx11
    UINT64_C(3635937280), UINT64_C(0),	// DS_WRXCHG2_RTN_B32_gfx12
    UINT64_C(3635937280), UINT64_C(0),	// DS_WRXCHG2_RTN_B32_gfx6_gfx7
    UINT64_C(3629907968), UINT64_C(0),	// DS_WRXCHG2_RTN_B32_vi
    UINT64_C(3663462400), UINT64_C(0),	// DS_WRXCHG2_RTN_B32_vi_agpr
    UINT64_C(3629907968), UINT64_C(0),	// DS_WRXCHG2_RTN_B32_vi_gfx9
    UINT64_C(3652714496), UINT64_C(0),	// DS_WRXCHG2_RTN_B64_gfx10
    UINT64_C(3652714496), UINT64_C(0),	// DS_WRXCHG2_RTN_B64_gfx11
    UINT64_C(3652714496), UINT64_C(0),	// DS_WRXCHG2_RTN_B64_gfx12
    UINT64_C(3652714496), UINT64_C(0),	// DS_WRXCHG2_RTN_B64_gfx6_gfx7
    UINT64_C(3638296576), UINT64_C(0),	// DS_WRXCHG2_RTN_B64_vi
    UINT64_C(3671851008), UINT64_C(0),	// DS_WRXCHG2_RTN_B64_vi_agpr
    UINT64_C(3638296576), UINT64_C(0),	// DS_WRXCHG2_RTN_B64_vi_gfx9
    UINT64_C(3635675136), UINT64_C(0),	// DS_WRXCHG_RTN_B32_gfx10
    UINT64_C(3635675136), UINT64_C(0),	// DS_WRXCHG_RTN_B32_gfx11
    UINT64_C(3635675136), UINT64_C(0),	// DS_WRXCHG_RTN_B32_gfx12
    UINT64_C(3635675136), UINT64_C(0),	// DS_WRXCHG_RTN_B32_gfx6_gfx7
    UINT64_C(3629776896), UINT64_C(0),	// DS_WRXCHG_RTN_B32_vi
    UINT64_C(3663331328), UINT64_C(0),	// DS_WRXCHG_RTN_B32_vi_agpr
    UINT64_C(3629776896), UINT64_C(0),	// DS_WRXCHG_RTN_B32_vi_gfx9
    UINT64_C(3652452352), UINT64_C(0),	// DS_WRXCHG_RTN_B64_gfx10
    UINT64_C(3652452352), UINT64_C(0),	// DS_WRXCHG_RTN_B64_gfx11
    UINT64_C(3652452352), UINT64_C(0),	// DS_WRXCHG_RTN_B64_gfx12
    UINT64_C(3652452352), UINT64_C(0),	// DS_WRXCHG_RTN_B64_gfx6_gfx7
    UINT64_C(3638165504), UINT64_C(0),	// DS_WRXCHG_RTN_B64_vi
    UINT64_C(3671719936), UINT64_C(0),	// DS_WRXCHG_RTN_B64_vi_agpr
    UINT64_C(3638165504), UINT64_C(0),	// DS_WRXCHG_RTN_B64_vi_gfx9
    UINT64_C(3626762240), UINT64_C(0),	// DS_XOR_B32_gfx10
    UINT64_C(3626762240), UINT64_C(0),	// DS_XOR_B32_gfx11
    UINT64_C(3626762240), UINT64_C(0),	// DS_XOR_B32_gfx12
    UINT64_C(3626762240), UINT64_C(0),	// DS_XOR_B32_gfx6_gfx7
    UINT64_C(3625320448), UINT64_C(0),	// DS_XOR_B32_vi
    UINT64_C(3625320448), UINT64_C(0),	// DS_XOR_B32_vi_gfx9
    UINT64_C(3643539456), UINT64_C(0),	// DS_XOR_B64_gfx10
    UINT64_C(3643539456), UINT64_C(0),	// DS_XOR_B64_gfx11
    UINT64_C(3643539456), UINT64_C(0),	// DS_XOR_B64_gfx12
    UINT64_C(3643539456), UINT64_C(0),	// DS_XOR_B64_gfx6_gfx7
    UINT64_C(3633709056), UINT64_C(0),	// DS_XOR_B64_vi
    UINT64_C(3633709056), UINT64_C(0),	// DS_XOR_B64_vi_gfx9
    UINT64_C(3635150848), UINT64_C(0),	// DS_XOR_RTN_B32_gfx10
    UINT64_C(3635150848), UINT64_C(0),	// DS_XOR_RTN_B32_gfx11
    UINT64_C(3635150848), UINT64_C(0),	// DS_XOR_RTN_B32_gfx12
    UINT64_C(3635150848), UINT64_C(0),	// DS_XOR_RTN_B32_gfx6_gfx7
    UINT64_C(3629514752), UINT64_C(0),	// DS_XOR_RTN_B32_vi
    UINT64_C(3663069184), UINT64_C(0),	// DS_XOR_RTN_B32_vi_agpr
    UINT64_C(3629514752), UINT64_C(0),	// DS_XOR_RTN_B32_vi_gfx9
    UINT64_C(3651928064), UINT64_C(0),	// DS_XOR_RTN_B64_gfx10
    UINT64_C(3651928064), UINT64_C(0),	// DS_XOR_RTN_B64_gfx11
    UINT64_C(3651928064), UINT64_C(0),	// DS_XOR_RTN_B64_gfx12
    UINT64_C(3651928064), UINT64_C(0),	// DS_XOR_RTN_B64_gfx6_gfx7
    UINT64_C(3637903360), UINT64_C(0),	// DS_XOR_RTN_B64_vi
    UINT64_C(3671457792), UINT64_C(0),	// DS_XOR_RTN_B64_vi_agpr
    UINT64_C(3637903360), UINT64_C(0),	// DS_XOR_RTN_B64_vi_gfx9
    UINT64_C(3660316672), UINT64_C(0),	// DS_XOR_SRC2_B32_gfx10
    UINT64_C(3660316672), UINT64_C(0),	// DS_XOR_SRC2_B32_gfx6_gfx7
    UINT64_C(3642097664), UINT64_C(0),	// DS_XOR_SRC2_B32_vi
    UINT64_C(3677093888), UINT64_C(0),	// DS_XOR_SRC2_B64_gfx10
    UINT64_C(3677093888), UINT64_C(0),	// DS_XOR_SRC2_B64_gfx6_gfx7
    UINT64_C(3650486272), UINT64_C(0),	// DS_XOR_SRC2_B64_vi
    UINT64_C(4160751616), UINT64_C(0),	// EXP_DONE_gfx10
    UINT64_C(4160751616), UINT64_C(0),	// EXP_DONE_gfx11
    UINT64_C(4160751616), UINT64_C(0),	// EXP_DONE_gfx12
    UINT64_C(4160751616), UINT64_C(0),	// EXP_DONE_si
    UINT64_C(3288336384), UINT64_C(0),	// EXP_DONE_vi
    UINT64_C(4160759808), UINT64_C(0),	// EXP_ROW_DONE_gfx11
    UINT64_C(4160759808), UINT64_C(0),	// EXP_ROW_DONE_gfx12
    UINT64_C(4160757760), UINT64_C(0),	// EXP_ROW_gfx11
    UINT64_C(4160757760), UINT64_C(0),	// EXP_ROW_gfx12
    UINT64_C(4160749568), UINT64_C(0),	// EXP_gfx10
    UINT64_C(4160749568), UINT64_C(0),	// EXP_gfx11
    UINT64_C(4160749568), UINT64_C(0),	// EXP_gfx12
    UINT64_C(4160749568), UINT64_C(0),	// EXP_si
    UINT64_C(3288334336), UINT64_C(0),	// EXP_vi
    UINT64_C(36028800730202112), UINT64_C(0),	// FLAT_ATOMIC_ADD_F32_RTN_agpr_vi
    UINT64_C(34902900825669632), UINT64_C(0),	// FLAT_ATOMIC_ADD_F32_RTN_gfx11
    UINT64_C(4503603588202620), UINT64_C(0),	// FLAT_ATOMIC_ADD_F32_RTN_gfx12
    UINT64_C(3711238144), UINT64_C(0),	// FLAT_ATOMIC_ADD_F32_RTN_vi
    UINT64_C(4503603588202496), UINT64_C(0),	// FLAT_ATOMIC_ADD_F32_SADDR_RTN_gfx12
    UINT64_C(3960832000), UINT64_C(0),	// FLAT_ATOMIC_ADD_F32_SADDR_gfx12
    UINT64_C(34902900825653248), UINT64_C(0),	// FLAT_ATOMIC_ADD_F32_gfx11
    UINT64_C(3960832124), UINT64_C(0),	// FLAT_ATOMIC_ADD_F32_gfx12
    UINT64_C(3711172608), UINT64_C(0),	// FLAT_ATOMIC_ADD_F32_vi
    UINT64_C(36028800730726400), UINT64_C(0),	// FLAT_ATOMIC_ADD_F64_RTN_agpr_vi
    UINT64_C(4503603588186236), UINT64_C(0),	// FLAT_ATOMIC_ADD_F64_RTN_gfx1250
    UINT64_C(3711762432), UINT64_C(0),	// FLAT_ATOMIC_ADD_F64_RTN_gfx940
    UINT64_C(3711762432), UINT64_C(0),	// FLAT_ATOMIC_ADD_F64_RTN_vi
    UINT64_C(4503603588186112), UINT64_C(0),	// FLAT_ATOMIC_ADD_F64_SADDR_RTN_gfx1250
    UINT64_C(3960815616), UINT64_C(0),	// FLAT_ATOMIC_ADD_F64_SADDR_gfx1250
    UINT64_C(3960815740), UINT64_C(0),	// FLAT_ATOMIC_ADD_F64_gfx1250
    UINT64_C(3711696896), UINT64_C(0),	// FLAT_ATOMIC_ADD_F64_gfx940
    UINT64_C(3711696896), UINT64_C(0),	// FLAT_ATOMIC_ADD_F64_vi
    UINT64_C(36028800727318528), UINT64_C(0),	// FLAT_ATOMIC_ADD_RTN_agpr_vi
    UINT64_C(3704160256), UINT64_C(0),	// FLAT_ATOMIC_ADD_RTN_ci
    UINT64_C(35184375792992256), UINT64_C(0),	// FLAT_ATOMIC_ADD_RTN_gfx10
    UINT64_C(34902900817018880), UINT64_C(0),	// FLAT_ATOMIC_ADD_RTN_gfx11
    UINT64_C(4503603587661948), UINT64_C(0),	// FLAT_ATOMIC_ADD_RTN_gfx12
    UINT64_C(3708354560), UINT64_C(0),	// FLAT_ATOMIC_ADD_RTN_vi
    UINT64_C(4503603587661824), UINT64_C(0),	// FLAT_ATOMIC_ADD_SADDR_RTN_gfx12
    UINT64_C(3960291328), UINT64_C(0),	// FLAT_ATOMIC_ADD_SADDR_gfx12
    UINT64_C(36028800735707136), UINT64_C(0),	// FLAT_ATOMIC_ADD_X2_RTN_agpr_vi
    UINT64_C(3712548864), UINT64_C(0),	// FLAT_ATOMIC_ADD_X2_RTN_ci
    UINT64_C(35184375801380864), UINT64_C(0),	// FLAT_ATOMIC_ADD_X2_RTN_gfx10
    UINT64_C(34902900820688896), UINT64_C(0),	// FLAT_ATOMIC_ADD_X2_RTN_gfx11
    UINT64_C(4503603587891324), UINT64_C(0),	// FLAT_ATOMIC_ADD_X2_RTN_gfx12
    UINT64_C(3716743168), UINT64_C(0),	// FLAT_ATOMIC_ADD_X2_RTN_vi
    UINT64_C(4503603587891200), UINT64_C(0),	// FLAT_ATOMIC_ADD_X2_SADDR_RTN_gfx12
    UINT64_C(3960520704), UINT64_C(0),	// FLAT_ATOMIC_ADD_X2_SADDR_gfx12
    UINT64_C(3712483328), UINT64_C(0),	// FLAT_ATOMIC_ADD_X2_ci
    UINT64_C(35184375801315328), UINT64_C(0),	// FLAT_ATOMIC_ADD_X2_gfx10
    UINT64_C(34902900820672512), UINT64_C(0),	// FLAT_ATOMIC_ADD_X2_gfx11
    UINT64_C(3960520828), UINT64_C(0),	// FLAT_ATOMIC_ADD_X2_gfx12
    UINT64_C(3716677632), UINT64_C(0),	// FLAT_ATOMIC_ADD_X2_vi
    UINT64_C(3704094720), UINT64_C(0),	// FLAT_ATOMIC_ADD_ci
    UINT64_C(35184375792926720), UINT64_C(0),	// FLAT_ATOMIC_ADD_gfx10
    UINT64_C(34902900817002496), UINT64_C(0),	// FLAT_ATOMIC_ADD_gfx11
    UINT64_C(3960291452), UINT64_C(0),	// FLAT_ATOMIC_ADD_gfx12
    UINT64_C(3708289024), UINT64_C(0),	// FLAT_ATOMIC_ADD_vi
    UINT64_C(36028800728891392), UINT64_C(0),	// FLAT_ATOMIC_AND_RTN_agpr_vi
    UINT64_C(3705995264), UINT64_C(0),	// FLAT_ATOMIC_AND_RTN_ci
    UINT64_C(35184375794827264), UINT64_C(0),	// FLAT_ATOMIC_AND_RTN_gfx10
    UINT64_C(34902900818853888), UINT64_C(0),	// FLAT_ATOMIC_AND_RTN_gfx11
    UINT64_C(4503603587776636), UINT64_C(0),	// FLAT_ATOMIC_AND_RTN_gfx12
    UINT64_C(3709927424), UINT64_C(0),	// FLAT_ATOMIC_AND_RTN_vi
    UINT64_C(4503603587776512), UINT64_C(0),	// FLAT_ATOMIC_AND_SADDR_RTN_gfx12
    UINT64_C(3960406016), UINT64_C(0),	// FLAT_ATOMIC_AND_SADDR_gfx12
    UINT64_C(36028800737280000), UINT64_C(0),	// FLAT_ATOMIC_AND_X2_RTN_agpr_vi
    UINT64_C(3714383872), UINT64_C(0),	// FLAT_ATOMIC_AND_X2_RTN_ci
    UINT64_C(35184375803215872), UINT64_C(0),	// FLAT_ATOMIC_AND_X2_RTN_gfx10
    UINT64_C(34902900822261760), UINT64_C(0),	// FLAT_ATOMIC_AND_X2_RTN_gfx11
    UINT64_C(4503603587989628), UINT64_C(0),	// FLAT_ATOMIC_AND_X2_RTN_gfx12
    UINT64_C(3718316032), UINT64_C(0),	// FLAT_ATOMIC_AND_X2_RTN_vi
    UINT64_C(4503603587989504), UINT64_C(0),	// FLAT_ATOMIC_AND_X2_SADDR_RTN_gfx12
    UINT64_C(3960619008), UINT64_C(0),	// FLAT_ATOMIC_AND_X2_SADDR_gfx12
    UINT64_C(3714318336), UINT64_C(0),	// FLAT_ATOMIC_AND_X2_ci
    UINT64_C(35184375803150336), UINT64_C(0),	// FLAT_ATOMIC_AND_X2_gfx10
    UINT64_C(34902900822245376), UINT64_C(0),	// FLAT_ATOMIC_AND_X2_gfx11
    UINT64_C(3960619132), UINT64_C(0),	// FLAT_ATOMIC_AND_X2_gfx12
    UINT64_C(3718250496), UINT64_C(0),	// FLAT_ATOMIC_AND_X2_vi
    UINT64_C(3705929728), UINT64_C(0),	// FLAT_ATOMIC_AND_ci
    UINT64_C(35184375794761728), UINT64_C(0),	// FLAT_ATOMIC_AND_gfx10
    UINT64_C(34902900818837504), UINT64_C(0),	// FLAT_ATOMIC_AND_gfx11
    UINT64_C(3960406140), UINT64_C(0),	// FLAT_ATOMIC_AND_gfx12
    UINT64_C(3709861888), UINT64_C(0),	// FLAT_ATOMIC_AND_vi
    UINT64_C(36028800727056384), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_RTN_agpr_vi
    UINT64_C(3703898112), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_RTN_ci
    UINT64_C(35184375792730112), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_RTN_gfx10
    UINT64_C(34902900816756736), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_RTN_gfx11
    UINT64_C(4503603587645564), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_RTN_gfx12
    UINT64_C(3708092416), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_RTN_vi
    UINT64_C(4503603587645440), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_SADDR_RTN_gfx12
    UINT64_C(3960274944), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_SADDR_gfx12
    UINT64_C(36028800735444992), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_X2_RTN_agpr_vi
    UINT64_C(3712286720), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_X2_RTN_ci
    UINT64_C(35184375801118720), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_X2_RTN_gfx10
    UINT64_C(34902900820426752), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_X2_RTN_gfx11
    UINT64_C(4503603587874940), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_X2_RTN_gfx12
    UINT64_C(3716481024), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_X2_RTN_vi
    UINT64_C(4503603587874816), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_X2_SADDR_RTN_gfx12
    UINT64_C(3960504320), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_X2_SADDR_gfx12
    UINT64_C(3712221184), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_X2_ci
    UINT64_C(35184375801053184), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_X2_gfx10
    UINT64_C(34902900820410368), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_X2_gfx11
    UINT64_C(3960504444), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_X2_gfx12
    UINT64_C(3716415488), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_X2_vi
    UINT64_C(3703832576), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_ci
    UINT64_C(35184375792664576), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_gfx10
    UINT64_C(34902900816740352), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_gfx11
    UINT64_C(3960275068), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_gfx12
    UINT64_C(3708026880), UINT64_C(0),	// FLAT_ATOMIC_CMPSWAP_vi
    UINT64_C(4503603588104316), UINT64_C(0),	// FLAT_ATOMIC_COND_SUB_U32_RTN_gfx12
    UINT64_C(4503603588104192), UINT64_C(0),	// FLAT_ATOMIC_COND_SUB_U32_SADDR_RTN_gfx12
    UINT64_C(3960733696), UINT64_C(0),	// FLAT_ATOMIC_COND_SUB_U32_SADDR_gfx12
    UINT64_C(3960733820), UINT64_C(0),	// FLAT_ATOMIC_COND_SUB_U32_gfx12
    UINT64_C(4503603587694716), UINT64_C(0),	// FLAT_ATOMIC_CSUB_U32_RTN_gfx12
    UINT64_C(4503603587694592), UINT64_C(0),	// FLAT_ATOMIC_CSUB_U32_SADDR_RTN_gfx12
    UINT64_C(3960324096), UINT64_C(0),	// FLAT_ATOMIC_CSUB_U32_SADDR_gfx12
    UINT64_C(3960324220), UINT64_C(0),	// FLAT_ATOMIC_CSUB_U32_gfx12
    UINT64_C(36028800729939968), UINT64_C(0),	// FLAT_ATOMIC_DEC_RTN_agpr_vi
    UINT64_C(3707043840), UINT64_C(0),	// FLAT_ATOMIC_DEC_RTN_ci
    UINT64_C(35184375795875840), UINT64_C(0),	// FLAT_ATOMIC_DEC_RTN_gfx10
    UINT64_C(34902900819902464), UINT64_C(0),	// FLAT_ATOMIC_DEC_RTN_gfx11
    UINT64_C(4503603587842172), UINT64_C(0),	// FLAT_ATOMIC_DEC_RTN_gfx12
    UINT64_C(3710976000), UINT64_C(0),	// FLAT_ATOMIC_DEC_RTN_vi
    UINT64_C(4503603587842048), UINT64_C(0),	// FLAT_ATOMIC_DEC_SADDR_RTN_gfx12
    UINT64_C(3960471552), UINT64_C(0),	// FLAT_ATOMIC_DEC_SADDR_gfx12
    UINT64_C(36028800738328576), UINT64_C(0),	// FLAT_ATOMIC_DEC_X2_RTN_agpr_vi
    UINT64_C(3715432448), UINT64_C(0),	// FLAT_ATOMIC_DEC_X2_RTN_ci
    UINT64_C(35184375804264448), UINT64_C(0),	// FLAT_ATOMIC_DEC_X2_RTN_gfx10
    UINT64_C(34902900823310336), UINT64_C(0),	// FLAT_ATOMIC_DEC_X2_RTN_gfx11
    UINT64_C(4503603588055164), UINT64_C(0),	// FLAT_ATOMIC_DEC_X2_RTN_gfx12
    UINT64_C(3719364608), UINT64_C(0),	// FLAT_ATOMIC_DEC_X2_RTN_vi
    UINT64_C(4503603588055040), UINT64_C(0),	// FLAT_ATOMIC_DEC_X2_SADDR_RTN_gfx12
    UINT64_C(3960684544), UINT64_C(0),	// FLAT_ATOMIC_DEC_X2_SADDR_gfx12
    UINT64_C(3715366912), UINT64_C(0),	// FLAT_ATOMIC_DEC_X2_ci
    UINT64_C(35184375804198912), UINT64_C(0),	// FLAT_ATOMIC_DEC_X2_gfx10
    UINT64_C(34902900823293952), UINT64_C(0),	// FLAT_ATOMIC_DEC_X2_gfx11
    UINT64_C(3960684668), UINT64_C(0),	// FLAT_ATOMIC_DEC_X2_gfx12
    UINT64_C(3719299072), UINT64_C(0),	// FLAT_ATOMIC_DEC_X2_vi
    UINT64_C(3706978304), UINT64_C(0),	// FLAT_ATOMIC_DEC_ci
    UINT64_C(35184375795810304), UINT64_C(0),	// FLAT_ATOMIC_DEC_gfx10
    UINT64_C(34902900819886080), UINT64_C(0),	// FLAT_ATOMIC_DEC_gfx11
    UINT64_C(3960471676), UINT64_C(0),	// FLAT_ATOMIC_DEC_gfx12
    UINT64_C(3710910464), UINT64_C(0),	// FLAT_ATOMIC_DEC_vi
    UINT64_C(3707305984), UINT64_C(0),	// FLAT_ATOMIC_FCMPSWAP_RTN_ci
    UINT64_C(35184375796137984), UINT64_C(0),	// FLAT_ATOMIC_FCMPSWAP_RTN_gfx10
    UINT64_C(34902900824096768), UINT64_C(0),	// FLAT_ATOMIC_FCMPSWAP_RTN_gfx11
    UINT64_C(3715694592), UINT64_C(0),	// FLAT_ATOMIC_FCMPSWAP_X2_RTN_ci
    UINT64_C(35184375804526592), UINT64_C(0),	// FLAT_ATOMIC_FCMPSWAP_X2_RTN_gfx10
    UINT64_C(3715629056), UINT64_C(0),	// FLAT_ATOMIC_FCMPSWAP_X2_ci
    UINT64_C(35184375804461056), UINT64_C(0),	// FLAT_ATOMIC_FCMPSWAP_X2_gfx10
    UINT64_C(3707240448), UINT64_C(0),	// FLAT_ATOMIC_FCMPSWAP_ci
    UINT64_C(35184375796072448), UINT64_C(0),	// FLAT_ATOMIC_FCMPSWAP_gfx10
    UINT64_C(34902900824080384), UINT64_C(0),	// FLAT_ATOMIC_FCMPSWAP_gfx11
    UINT64_C(3707830272), UINT64_C(0),	// FLAT_ATOMIC_FMAX_RTN_ci
    UINT64_C(35184375796662272), UINT64_C(0),	// FLAT_ATOMIC_FMAX_RTN_gfx10
    UINT64_C(34902900824621056), UINT64_C(0),	// FLAT_ATOMIC_FMAX_RTN_gfx11
    UINT64_C(4503603588137084), UINT64_C(0),	// FLAT_ATOMIC_FMAX_RTN_gfx12
    UINT64_C(4503603588136960), UINT64_C(0),	// FLAT_ATOMIC_FMAX_SADDR_RTN_gfx12
    UINT64_C(3960766464), UINT64_C(0),	// FLAT_ATOMIC_FMAX_SADDR_gfx12
    UINT64_C(3716218880), UINT64_C(0),	// FLAT_ATOMIC_FMAX_X2_RTN_ci
    UINT64_C(35184375805050880), UINT64_C(0),	// FLAT_ATOMIC_FMAX_X2_RTN_gfx10
    UINT64_C(3716153344), UINT64_C(0),	// FLAT_ATOMIC_FMAX_X2_ci
    UINT64_C(35184375804985344), UINT64_C(0),	// FLAT_ATOMIC_FMAX_X2_gfx10
    UINT64_C(3707764736), UINT64_C(0),	// FLAT_ATOMIC_FMAX_ci
    UINT64_C(35184375796596736), UINT64_C(0),	// FLAT_ATOMIC_FMAX_gfx10
    UINT64_C(34902900824604672), UINT64_C(0),	// FLAT_ATOMIC_FMAX_gfx11
    UINT64_C(3960766588), UINT64_C(0),	// FLAT_ATOMIC_FMAX_gfx12
    UINT64_C(3707568128), UINT64_C(0),	// FLAT_ATOMIC_FMIN_RTN_ci
    UINT64_C(35184375796400128), UINT64_C(0),	// FLAT_ATOMIC_FMIN_RTN_gfx10
    UINT64_C(34902900824358912), UINT64_C(0),	// FLAT_ATOMIC_FMIN_RTN_gfx11
    UINT64_C(4503603588120700), UINT64_C(0),	// FLAT_ATOMIC_FMIN_RTN_gfx12
    UINT64_C(4503603588120576), UINT64_C(0),	// FLAT_ATOMIC_FMIN_SADDR_RTN_gfx12
    UINT64_C(3960750080), UINT64_C(0),	// FLAT_ATOMIC_FMIN_SADDR_gfx12
    UINT64_C(3715956736), UINT64_C(0),	// FLAT_ATOMIC_FMIN_X2_RTN_ci
    UINT64_C(35184375804788736), UINT64_C(0),	// FLAT_ATOMIC_FMIN_X2_RTN_gfx10
    UINT64_C(3715891200), UINT64_C(0),	// FLAT_ATOMIC_FMIN_X2_ci
    UINT64_C(35184375804723200), UINT64_C(0),	// FLAT_ATOMIC_FMIN_X2_gfx10
    UINT64_C(3707502592), UINT64_C(0),	// FLAT_ATOMIC_FMIN_ci
    UINT64_C(35184375796334592), UINT64_C(0),	// FLAT_ATOMIC_FMIN_gfx10
    UINT64_C(34902900824342528), UINT64_C(0),	// FLAT_ATOMIC_FMIN_gfx11
    UINT64_C(3960750204), UINT64_C(0),	// FLAT_ATOMIC_FMIN_gfx12
    UINT64_C(36028800729677824), UINT64_C(0),	// FLAT_ATOMIC_INC_RTN_agpr_vi
    UINT64_C(3706781696), UINT64_C(0),	// FLAT_ATOMIC_INC_RTN_ci
    UINT64_C(35184375795613696), UINT64_C(0),	// FLAT_ATOMIC_INC_RTN_gfx10
    UINT64_C(34902900819640320), UINT64_C(0),	// FLAT_ATOMIC_INC_RTN_gfx11
    UINT64_C(4503603587825788), UINT64_C(0),	// FLAT_ATOMIC_INC_RTN_gfx12
    UINT64_C(3710713856), UINT64_C(0),	// FLAT_ATOMIC_INC_RTN_vi
    UINT64_C(4503603587825664), UINT64_C(0),	// FLAT_ATOMIC_INC_SADDR_RTN_gfx12
    UINT64_C(3960455168), UINT64_C(0),	// FLAT_ATOMIC_INC_SADDR_gfx12
    UINT64_C(36028800738066432), UINT64_C(0),	// FLAT_ATOMIC_INC_X2_RTN_agpr_vi
    UINT64_C(3715170304), UINT64_C(0),	// FLAT_ATOMIC_INC_X2_RTN_ci
    UINT64_C(35184375804002304), UINT64_C(0),	// FLAT_ATOMIC_INC_X2_RTN_gfx10
    UINT64_C(34902900823048192), UINT64_C(0),	// FLAT_ATOMIC_INC_X2_RTN_gfx11
    UINT64_C(4503603588038780), UINT64_C(0),	// FLAT_ATOMIC_INC_X2_RTN_gfx12
    UINT64_C(3719102464), UINT64_C(0),	// FLAT_ATOMIC_INC_X2_RTN_vi
    UINT64_C(4503603588038656), UINT64_C(0),	// FLAT_ATOMIC_INC_X2_SADDR_RTN_gfx12
    UINT64_C(3960668160), UINT64_C(0),	// FLAT_ATOMIC_INC_X2_SADDR_gfx12
    UINT64_C(3715104768), UINT64_C(0),	// FLAT_ATOMIC_INC_X2_ci
    UINT64_C(35184375803936768), UINT64_C(0),	// FLAT_ATOMIC_INC_X2_gfx10
    UINT64_C(34902900823031808), UINT64_C(0),	// FLAT_ATOMIC_INC_X2_gfx11
    UINT64_C(3960668284), UINT64_C(0),	// FLAT_ATOMIC_INC_X2_gfx12
    UINT64_C(3719036928), UINT64_C(0),	// FLAT_ATOMIC_INC_X2_vi
    UINT64_C(3706716160), UINT64_C(0),	// FLAT_ATOMIC_INC_ci
    UINT64_C(35184375795548160), UINT64_C(0),	// FLAT_ATOMIC_INC_gfx10
    UINT64_C(34902900819623936), UINT64_C(0),	// FLAT_ATOMIC_INC_gfx11
    UINT64_C(3960455292), UINT64_C(0),	// FLAT_ATOMIC_INC_gfx12
    UINT64_C(3710648320), UINT64_C(0),	// FLAT_ATOMIC_INC_vi
    UINT64_C(36028800731250688), UINT64_C(0),	// FLAT_ATOMIC_MAX_F64_RTN_agpr_vi
    UINT64_C(4503603588300924), UINT64_C(0),	// FLAT_ATOMIC_MAX_F64_RTN_gfx1250
    UINT64_C(3712286720), UINT64_C(0),	// FLAT_ATOMIC_MAX_F64_RTN_gfx940
    UINT64_C(3712286720), UINT64_C(0),	// FLAT_ATOMIC_MAX_F64_RTN_vi
    UINT64_C(4503603588300800), UINT64_C(0),	// FLAT_ATOMIC_MAX_F64_SADDR_RTN_gfx1250
    UINT64_C(3960930304), UINT64_C(0),	// FLAT_ATOMIC_MAX_F64_SADDR_gfx1250
    UINT64_C(3960930428), UINT64_C(0),	// FLAT_ATOMIC_MAX_F64_gfx1250
    UINT64_C(3712221184), UINT64_C(0),	// FLAT_ATOMIC_MAX_F64_gfx940
    UINT64_C(3712221184), UINT64_C(0),	// FLAT_ATOMIC_MAX_F64_vi
    UINT64_C(36028800730988544), UINT64_C(0),	// FLAT_ATOMIC_MIN_F64_RTN_agpr_vi
    UINT64_C(4503603588284540), UINT64_C(0),	// FLAT_ATOMIC_MIN_F64_RTN_gfx1250
    UINT64_C(3712024576), UINT64_C(0),	// FLAT_ATOMIC_MIN_F64_RTN_gfx940
    UINT64_C(3712024576), UINT64_C(0),	// FLAT_ATOMIC_MIN_F64_RTN_vi
    UINT64_C(4503603588284416), UINT64_C(0),	// FLAT_ATOMIC_MIN_F64_SADDR_RTN_gfx1250
    UINT64_C(3960913920), UINT64_C(0),	// FLAT_ATOMIC_MIN_F64_SADDR_gfx1250
    UINT64_C(3960914044), UINT64_C(0),	// FLAT_ATOMIC_MIN_F64_gfx1250
    UINT64_C(3711959040), UINT64_C(0),	// FLAT_ATOMIC_MIN_F64_gfx940
    UINT64_C(3711959040), UINT64_C(0),	// FLAT_ATOMIC_MIN_F64_vi
    UINT64_C(36028800729153536), UINT64_C(0),	// FLAT_ATOMIC_OR_RTN_agpr_vi
    UINT64_C(3706257408), UINT64_C(0),	// FLAT_ATOMIC_OR_RTN_ci
    UINT64_C(35184375795089408), UINT64_C(0),	// FLAT_ATOMIC_OR_RTN_gfx10
    UINT64_C(34902900819116032), UINT64_C(0),	// FLAT_ATOMIC_OR_RTN_gfx11
    UINT64_C(4503603587793020), UINT64_C(0),	// FLAT_ATOMIC_OR_RTN_gfx12
    UINT64_C(3710189568), UINT64_C(0),	// FLAT_ATOMIC_OR_RTN_vi
    UINT64_C(4503603587792896), UINT64_C(0),	// FLAT_ATOMIC_OR_SADDR_RTN_gfx12
    UINT64_C(3960422400), UINT64_C(0),	// FLAT_ATOMIC_OR_SADDR_gfx12
    UINT64_C(36028800737542144), UINT64_C(0),	// FLAT_ATOMIC_OR_X2_RTN_agpr_vi
    UINT64_C(3714646016), UINT64_C(0),	// FLAT_ATOMIC_OR_X2_RTN_ci
    UINT64_C(35184375803478016), UINT64_C(0),	// FLAT_ATOMIC_OR_X2_RTN_gfx10
    UINT64_C(34902900822523904), UINT64_C(0),	// FLAT_ATOMIC_OR_X2_RTN_gfx11
    UINT64_C(4503603588006012), UINT64_C(0),	// FLAT_ATOMIC_OR_X2_RTN_gfx12
    UINT64_C(3718578176), UINT64_C(0),	// FLAT_ATOMIC_OR_X2_RTN_vi
    UINT64_C(4503603588005888), UINT64_C(0),	// FLAT_ATOMIC_OR_X2_SADDR_RTN_gfx12
    UINT64_C(3960635392), UINT64_C(0),	// FLAT_ATOMIC_OR_X2_SADDR_gfx12
    UINT64_C(3714580480), UINT64_C(0),	// FLAT_ATOMIC_OR_X2_ci
    UINT64_C(35184375803412480), UINT64_C(0),	// FLAT_ATOMIC_OR_X2_gfx10
    UINT64_C(34902900822507520), UINT64_C(0),	// FLAT_ATOMIC_OR_X2_gfx11
    UINT64_C(3960635516), UINT64_C(0),	// FLAT_ATOMIC_OR_X2_gfx12
    UINT64_C(3718512640), UINT64_C(0),	// FLAT_ATOMIC_OR_X2_vi
    UINT64_C(3706191872), UINT64_C(0),	// FLAT_ATOMIC_OR_ci
    UINT64_C(35184375795023872), UINT64_C(0),	// FLAT_ATOMIC_OR_gfx10
    UINT64_C(34902900819099648), UINT64_C(0),	// FLAT_ATOMIC_OR_gfx11
    UINT64_C(3960422524), UINT64_C(0),	// FLAT_ATOMIC_OR_gfx12
    UINT64_C(3710124032), UINT64_C(0),	// FLAT_ATOMIC_OR_vi
    UINT64_C(36028800731512832), UINT64_C(0),	// FLAT_ATOMIC_PK_ADD_BF16_RTN_agpr_vi
    UINT64_C(4503603588268156), UINT64_C(0),	// FLAT_ATOMIC_PK_ADD_BF16_RTN_gfx12
    UINT64_C(3712548864), UINT64_C(0),	// FLAT_ATOMIC_PK_ADD_BF16_RTN_vi
    UINT64_C(4503603588268032), UINT64_C(0),	// FLAT_ATOMIC_PK_ADD_BF16_SADDR_RTN_gfx12
    UINT64_C(3960897536), UINT64_C(0),	// FLAT_ATOMIC_PK_ADD_BF16_SADDR_gfx12
    UINT64_C(3960897660), UINT64_C(0),	// FLAT_ATOMIC_PK_ADD_BF16_gfx12
    UINT64_C(3712483328), UINT64_C(0),	// FLAT_ATOMIC_PK_ADD_BF16_vi
    UINT64_C(36028800730464256), UINT64_C(0),	// FLAT_ATOMIC_PK_ADD_F16_RTN_agpr_vi
    UINT64_C(4503603588251772), UINT64_C(0),	// FLAT_ATOMIC_PK_ADD_F16_RTN_gfx12
    UINT64_C(3711500288), UINT64_C(0),	// FLAT_ATOMIC_PK_ADD_F16_RTN_vi
    UINT64_C(4503603588251648), UINT64_C(0),	// FLAT_ATOMIC_PK_ADD_F16_SADDR_RTN_gfx12
    UINT64_C(3960881152), UINT64_C(0),	// FLAT_ATOMIC_PK_ADD_F16_SADDR_gfx12
    UINT64_C(3960881276), UINT64_C(0),	// FLAT_ATOMIC_PK_ADD_F16_gfx12
    UINT64_C(3711434752), UINT64_C(0),	// FLAT_ATOMIC_PK_ADD_F16_vi
    UINT64_C(36028800728367104), UINT64_C(0),	// FLAT_ATOMIC_SMAX_RTN_agpr_vi
    UINT64_C(3705470976), UINT64_C(0),	// FLAT_ATOMIC_SMAX_RTN_ci
    UINT64_C(35184375794302976), UINT64_C(0),	// FLAT_ATOMIC_SMAX_RTN_gfx10
    UINT64_C(34902900818329600), UINT64_C(0),	// FLAT_ATOMIC_SMAX_RTN_gfx11
    UINT64_C(4503603587743868), UINT64_C(0),	// FLAT_ATOMIC_SMAX_RTN_gfx12
    UINT64_C(3709403136), UINT64_C(0),	// FLAT_ATOMIC_SMAX_RTN_vi
    UINT64_C(4503603587743744), UINT64_C(0),	// FLAT_ATOMIC_SMAX_SADDR_RTN_gfx12
    UINT64_C(3960373248), UINT64_C(0),	// FLAT_ATOMIC_SMAX_SADDR_gfx12
    UINT64_C(36028800736755712), UINT64_C(0),	// FLAT_ATOMIC_SMAX_X2_RTN_agpr_vi
    UINT64_C(3713859584), UINT64_C(0),	// FLAT_ATOMIC_SMAX_X2_RTN_ci
    UINT64_C(35184375802691584), UINT64_C(0),	// FLAT_ATOMIC_SMAX_X2_RTN_gfx10
    UINT64_C(34902900821737472), UINT64_C(0),	// FLAT_ATOMIC_SMAX_X2_RTN_gfx11
    UINT64_C(4503603587956860), UINT64_C(0),	// FLAT_ATOMIC_SMAX_X2_RTN_gfx12
    UINT64_C(3717791744), UINT64_C(0),	// FLAT_ATOMIC_SMAX_X2_RTN_vi
    UINT64_C(4503603587956736), UINT64_C(0),	// FLAT_ATOMIC_SMAX_X2_SADDR_RTN_gfx12
    UINT64_C(3960586240), UINT64_C(0),	// FLAT_ATOMIC_SMAX_X2_SADDR_gfx12
    UINT64_C(3713794048), UINT64_C(0),	// FLAT_ATOMIC_SMAX_X2_ci
    UINT64_C(35184375802626048), UINT64_C(0),	// FLAT_ATOMIC_SMAX_X2_gfx10
    UINT64_C(34902900821721088), UINT64_C(0),	// FLAT_ATOMIC_SMAX_X2_gfx11
    UINT64_C(3960586364), UINT64_C(0),	// FLAT_ATOMIC_SMAX_X2_gfx12
    UINT64_C(3717726208), UINT64_C(0),	// FLAT_ATOMIC_SMAX_X2_vi
    UINT64_C(3705405440), UINT64_C(0),	// FLAT_ATOMIC_SMAX_ci
    UINT64_C(35184375794237440), UINT64_C(0),	// FLAT_ATOMIC_SMAX_gfx10
    UINT64_C(34902900818313216), UINT64_C(0),	// FLAT_ATOMIC_SMAX_gfx11
    UINT64_C(3960373372), UINT64_C(0),	// FLAT_ATOMIC_SMAX_gfx12
    UINT64_C(3709337600), UINT64_C(0),	// FLAT_ATOMIC_SMAX_vi
    UINT64_C(36028800727842816), UINT64_C(0),	// FLAT_ATOMIC_SMIN_RTN_agpr_vi
    UINT64_C(3704946688), UINT64_C(0),	// FLAT_ATOMIC_SMIN_RTN_ci
    UINT64_C(35184375793778688), UINT64_C(0),	// FLAT_ATOMIC_SMIN_RTN_gfx10
    UINT64_C(34902900817805312), UINT64_C(0),	// FLAT_ATOMIC_SMIN_RTN_gfx11
    UINT64_C(4503603587711100), UINT64_C(0),	// FLAT_ATOMIC_SMIN_RTN_gfx12
    UINT64_C(3708878848), UINT64_C(0),	// FLAT_ATOMIC_SMIN_RTN_vi
    UINT64_C(4503603587710976), UINT64_C(0),	// FLAT_ATOMIC_SMIN_SADDR_RTN_gfx12
    UINT64_C(3960340480), UINT64_C(0),	// FLAT_ATOMIC_SMIN_SADDR_gfx12
    UINT64_C(36028800736231424), UINT64_C(0),	// FLAT_ATOMIC_SMIN_X2_RTN_agpr_vi
    UINT64_C(3713335296), UINT64_C(0),	// FLAT_ATOMIC_SMIN_X2_RTN_ci
    UINT64_C(35184375802167296), UINT64_C(0),	// FLAT_ATOMIC_SMIN_X2_RTN_gfx10
    UINT64_C(34902900821213184), UINT64_C(0),	// FLAT_ATOMIC_SMIN_X2_RTN_gfx11
    UINT64_C(4503603587924092), UINT64_C(0),	// FLAT_ATOMIC_SMIN_X2_RTN_gfx12
    UINT64_C(3717267456), UINT64_C(0),	// FLAT_ATOMIC_SMIN_X2_RTN_vi
    UINT64_C(4503603587923968), UINT64_C(0),	// FLAT_ATOMIC_SMIN_X2_SADDR_RTN_gfx12
    UINT64_C(3960553472), UINT64_C(0),	// FLAT_ATOMIC_SMIN_X2_SADDR_gfx12
    UINT64_C(3713269760), UINT64_C(0),	// FLAT_ATOMIC_SMIN_X2_ci
    UINT64_C(35184375802101760), UINT64_C(0),	// FLAT_ATOMIC_SMIN_X2_gfx10
    UINT64_C(34902900821196800), UINT64_C(0),	// FLAT_ATOMIC_SMIN_X2_gfx11
    UINT64_C(3960553596), UINT64_C(0),	// FLAT_ATOMIC_SMIN_X2_gfx12
    UINT64_C(3717201920), UINT64_C(0),	// FLAT_ATOMIC_SMIN_X2_vi
    UINT64_C(3704881152), UINT64_C(0),	// FLAT_ATOMIC_SMIN_ci
    UINT64_C(35184375793713152), UINT64_C(0),	// FLAT_ATOMIC_SMIN_gfx10
    UINT64_C(34902900817788928), UINT64_C(0),	// FLAT_ATOMIC_SMIN_gfx11
    UINT64_C(3960340604), UINT64_C(0),	// FLAT_ATOMIC_SMIN_gfx12
    UINT64_C(3708813312), UINT64_C(0),	// FLAT_ATOMIC_SMIN_vi
    UINT64_C(36028800727580672), UINT64_C(0),	// FLAT_ATOMIC_SUB_RTN_agpr_vi
    UINT64_C(3704422400), UINT64_C(0),	// FLAT_ATOMIC_SUB_RTN_ci
    UINT64_C(35184375793254400), UINT64_C(0),	// FLAT_ATOMIC_SUB_RTN_gfx10
    UINT64_C(34902900817281024), UINT64_C(0),	// FLAT_ATOMIC_SUB_RTN_gfx11
    UINT64_C(4503603587678332), UINT64_C(0),	// FLAT_ATOMIC_SUB_RTN_gfx12
    UINT64_C(3708616704), UINT64_C(0),	// FLAT_ATOMIC_SUB_RTN_vi
    UINT64_C(4503603587678208), UINT64_C(0),	// FLAT_ATOMIC_SUB_SADDR_RTN_gfx12
    UINT64_C(3960307712), UINT64_C(0),	// FLAT_ATOMIC_SUB_SADDR_gfx12
    UINT64_C(36028800735969280), UINT64_C(0),	// FLAT_ATOMIC_SUB_X2_RTN_agpr_vi
    UINT64_C(3712811008), UINT64_C(0),	// FLAT_ATOMIC_SUB_X2_RTN_ci
    UINT64_C(35184375801643008), UINT64_C(0),	// FLAT_ATOMIC_SUB_X2_RTN_gfx10
    UINT64_C(34902900820951040), UINT64_C(0),	// FLAT_ATOMIC_SUB_X2_RTN_gfx11
    UINT64_C(4503603587907708), UINT64_C(0),	// FLAT_ATOMIC_SUB_X2_RTN_gfx12
    UINT64_C(3717005312), UINT64_C(0),	// FLAT_ATOMIC_SUB_X2_RTN_vi
    UINT64_C(4503603587907584), UINT64_C(0),	// FLAT_ATOMIC_SUB_X2_SADDR_RTN_gfx12
    UINT64_C(3960537088), UINT64_C(0),	// FLAT_ATOMIC_SUB_X2_SADDR_gfx12
    UINT64_C(3712745472), UINT64_C(0),	// FLAT_ATOMIC_SUB_X2_ci
    UINT64_C(35184375801577472), UINT64_C(0),	// FLAT_ATOMIC_SUB_X2_gfx10
    UINT64_C(34902900820934656), UINT64_C(0),	// FLAT_ATOMIC_SUB_X2_gfx11
    UINT64_C(3960537212), UINT64_C(0),	// FLAT_ATOMIC_SUB_X2_gfx12
    UINT64_C(3716939776), UINT64_C(0),	// FLAT_ATOMIC_SUB_X2_vi
    UINT64_C(3704356864), UINT64_C(0),	// FLAT_ATOMIC_SUB_ci
    UINT64_C(35184375793188864), UINT64_C(0),	// FLAT_ATOMIC_SUB_gfx10
    UINT64_C(34902900817264640), UINT64_C(0),	// FLAT_ATOMIC_SUB_gfx11
    UINT64_C(3960307836), UINT64_C(0),	// FLAT_ATOMIC_SUB_gfx12
    UINT64_C(3708551168), UINT64_C(0),	// FLAT_ATOMIC_SUB_vi
    UINT64_C(36028800726794240), UINT64_C(0),	// FLAT_ATOMIC_SWAP_RTN_agpr_vi
    UINT64_C(3703635968), UINT64_C(0),	// FLAT_ATOMIC_SWAP_RTN_ci
    UINT64_C(35184375792467968), UINT64_C(0),	// FLAT_ATOMIC_SWAP_RTN_gfx10
    UINT64_C(34902900816494592), UINT64_C(0),	// FLAT_ATOMIC_SWAP_RTN_gfx11
    UINT64_C(4503603587629180), UINT64_C(0),	// FLAT_ATOMIC_SWAP_RTN_gfx12
    UINT64_C(3707830272), UINT64_C(0),	// FLAT_ATOMIC_SWAP_RTN_vi
    UINT64_C(4503603587629056), UINT64_C(0),	// FLAT_ATOMIC_SWAP_SADDR_RTN_gfx12
    UINT64_C(3960258560), UINT64_C(0),	// FLAT_ATOMIC_SWAP_SADDR_gfx12
    UINT64_C(36028800735182848), UINT64_C(0),	// FLAT_ATOMIC_SWAP_X2_RTN_agpr_vi
    UINT64_C(3712024576), UINT64_C(0),	// FLAT_ATOMIC_SWAP_X2_RTN_ci
    UINT64_C(35184375800856576), UINT64_C(0),	// FLAT_ATOMIC_SWAP_X2_RTN_gfx10
    UINT64_C(34902900820164608), UINT64_C(0),	// FLAT_ATOMIC_SWAP_X2_RTN_gfx11
    UINT64_C(4503603587858556), UINT64_C(0),	// FLAT_ATOMIC_SWAP_X2_RTN_gfx12
    UINT64_C(3716218880), UINT64_C(0),	// FLAT_ATOMIC_SWAP_X2_RTN_vi
    UINT64_C(4503603587858432), UINT64_C(0),	// FLAT_ATOMIC_SWAP_X2_SADDR_RTN_gfx12
    UINT64_C(3960487936), UINT64_C(0),	// FLAT_ATOMIC_SWAP_X2_SADDR_gfx12
    UINT64_C(3711959040), UINT64_C(0),	// FLAT_ATOMIC_SWAP_X2_ci
    UINT64_C(35184375800791040), UINT64_C(0),	// FLAT_ATOMIC_SWAP_X2_gfx10
    UINT64_C(34902900820148224), UINT64_C(0),	// FLAT_ATOMIC_SWAP_X2_gfx11
    UINT64_C(3960488060), UINT64_C(0),	// FLAT_ATOMIC_SWAP_X2_gfx12
    UINT64_C(3716153344), UINT64_C(0),	// FLAT_ATOMIC_SWAP_X2_vi
    UINT64_C(3703570432), UINT64_C(0),	// FLAT_ATOMIC_SWAP_ci
    UINT64_C(35184375792402432), UINT64_C(0),	// FLAT_ATOMIC_SWAP_gfx10
    UINT64_C(34902900816478208), UINT64_C(0),	// FLAT_ATOMIC_SWAP_gfx11
    UINT64_C(3960258684), UINT64_C(0),	// FLAT_ATOMIC_SWAP_gfx12
    UINT64_C(3707764736), UINT64_C(0),	// FLAT_ATOMIC_SWAP_vi
    UINT64_C(36028800728629248), UINT64_C(0),	// FLAT_ATOMIC_UMAX_RTN_agpr_vi
    UINT64_C(3705733120), UINT64_C(0),	// FLAT_ATOMIC_UMAX_RTN_ci
    UINT64_C(35184375794565120), UINT64_C(0),	// FLAT_ATOMIC_UMAX_RTN_gfx10
    UINT64_C(34902900818591744), UINT64_C(0),	// FLAT_ATOMIC_UMAX_RTN_gfx11
    UINT64_C(4503603587760252), UINT64_C(0),	// FLAT_ATOMIC_UMAX_RTN_gfx12
    UINT64_C(3709665280), UINT64_C(0),	// FLAT_ATOMIC_UMAX_RTN_vi
    UINT64_C(4503603587760128), UINT64_C(0),	// FLAT_ATOMIC_UMAX_SADDR_RTN_gfx12
    UINT64_C(3960389632), UINT64_C(0),	// FLAT_ATOMIC_UMAX_SADDR_gfx12
    UINT64_C(36028800737017856), UINT64_C(0),	// FLAT_ATOMIC_UMAX_X2_RTN_agpr_vi
    UINT64_C(3714121728), UINT64_C(0),	// FLAT_ATOMIC_UMAX_X2_RTN_ci
    UINT64_C(35184375802953728), UINT64_C(0),	// FLAT_ATOMIC_UMAX_X2_RTN_gfx10
    UINT64_C(34902900821999616), UINT64_C(0),	// FLAT_ATOMIC_UMAX_X2_RTN_gfx11
    UINT64_C(4503603587973244), UINT64_C(0),	// FLAT_ATOMIC_UMAX_X2_RTN_gfx12
    UINT64_C(3718053888), UINT64_C(0),	// FLAT_ATOMIC_UMAX_X2_RTN_vi
    UINT64_C(4503603587973120), UINT64_C(0),	// FLAT_ATOMIC_UMAX_X2_SADDR_RTN_gfx12
    UINT64_C(3960602624), UINT64_C(0),	// FLAT_ATOMIC_UMAX_X2_SADDR_gfx12
    UINT64_C(3714056192), UINT64_C(0),	// FLAT_ATOMIC_UMAX_X2_ci
    UINT64_C(35184375802888192), UINT64_C(0),	// FLAT_ATOMIC_UMAX_X2_gfx10
    UINT64_C(34902900821983232), UINT64_C(0),	// FLAT_ATOMIC_UMAX_X2_gfx11
    UINT64_C(3960602748), UINT64_C(0),	// FLAT_ATOMIC_UMAX_X2_gfx12
    UINT64_C(3717988352), UINT64_C(0),	// FLAT_ATOMIC_UMAX_X2_vi
    UINT64_C(3705667584), UINT64_C(0),	// FLAT_ATOMIC_UMAX_ci
    UINT64_C(35184375794499584), UINT64_C(0),	// FLAT_ATOMIC_UMAX_gfx10
    UINT64_C(34902900818575360), UINT64_C(0),	// FLAT_ATOMIC_UMAX_gfx11
    UINT64_C(3960389756), UINT64_C(0),	// FLAT_ATOMIC_UMAX_gfx12
    UINT64_C(3709599744), UINT64_C(0),	// FLAT_ATOMIC_UMAX_vi
    UINT64_C(36028800728104960), UINT64_C(0),	// FLAT_ATOMIC_UMIN_RTN_agpr_vi
    UINT64_C(3705208832), UINT64_C(0),	// FLAT_ATOMIC_UMIN_RTN_ci
    UINT64_C(35184375794040832), UINT64_C(0),	// FLAT_ATOMIC_UMIN_RTN_gfx10
    UINT64_C(34902900818067456), UINT64_C(0),	// FLAT_ATOMIC_UMIN_RTN_gfx11
    UINT64_C(4503603587727484), UINT64_C(0),	// FLAT_ATOMIC_UMIN_RTN_gfx12
    UINT64_C(3709140992), UINT64_C(0),	// FLAT_ATOMIC_UMIN_RTN_vi
    UINT64_C(4503603587727360), UINT64_C(0),	// FLAT_ATOMIC_UMIN_SADDR_RTN_gfx12
    UINT64_C(3960356864), UINT64_C(0),	// FLAT_ATOMIC_UMIN_SADDR_gfx12
    UINT64_C(36028800736493568), UINT64_C(0),	// FLAT_ATOMIC_UMIN_X2_RTN_agpr_vi
    UINT64_C(3713597440), UINT64_C(0),	// FLAT_ATOMIC_UMIN_X2_RTN_ci
    UINT64_C(35184375802429440), UINT64_C(0),	// FLAT_ATOMIC_UMIN_X2_RTN_gfx10
    UINT64_C(34902900821475328), UINT64_C(0),	// FLAT_ATOMIC_UMIN_X2_RTN_gfx11
    UINT64_C(4503603587940476), UINT64_C(0),	// FLAT_ATOMIC_UMIN_X2_RTN_gfx12
    UINT64_C(3717529600), UINT64_C(0),	// FLAT_ATOMIC_UMIN_X2_RTN_vi
    UINT64_C(4503603587940352), UINT64_C(0),	// FLAT_ATOMIC_UMIN_X2_SADDR_RTN_gfx12
    UINT64_C(3960569856), UINT64_C(0),	// FLAT_ATOMIC_UMIN_X2_SADDR_gfx12
    UINT64_C(3713531904), UINT64_C(0),	// FLAT_ATOMIC_UMIN_X2_ci
    UINT64_C(35184375802363904), UINT64_C(0),	// FLAT_ATOMIC_UMIN_X2_gfx10
    UINT64_C(34902900821458944), UINT64_C(0),	// FLAT_ATOMIC_UMIN_X2_gfx11
    UINT64_C(3960569980), UINT64_C(0),	// FLAT_ATOMIC_UMIN_X2_gfx12
    UINT64_C(3717464064), UINT64_C(0),	// FLAT_ATOMIC_UMIN_X2_vi
    UINT64_C(3705143296), UINT64_C(0),	// FLAT_ATOMIC_UMIN_ci
    UINT64_C(35184375793975296), UINT64_C(0),	// FLAT_ATOMIC_UMIN_gfx10
    UINT64_C(34902900818051072), UINT64_C(0),	// FLAT_ATOMIC_UMIN_gfx11
    UINT64_C(3960356988), UINT64_C(0),	// FLAT_ATOMIC_UMIN_gfx12
    UINT64_C(3709075456), UINT64_C(0),	// FLAT_ATOMIC_UMIN_vi
    UINT64_C(36028800729415680), UINT64_C(0),	// FLAT_ATOMIC_XOR_RTN_agpr_vi
    UINT64_C(3706519552), UINT64_C(0),	// FLAT_ATOMIC_XOR_RTN_ci
    UINT64_C(35184375795351552), UINT64_C(0),	// FLAT_ATOMIC_XOR_RTN_gfx10
    UINT64_C(34902900819378176), UINT64_C(0),	// FLAT_ATOMIC_XOR_RTN_gfx11
    UINT64_C(4503603587809404), UINT64_C(0),	// FLAT_ATOMIC_XOR_RTN_gfx12
    UINT64_C(3710451712), UINT64_C(0),	// FLAT_ATOMIC_XOR_RTN_vi
    UINT64_C(4503603587809280), UINT64_C(0),	// FLAT_ATOMIC_XOR_SADDR_RTN_gfx12
    UINT64_C(3960438784), UINT64_C(0),	// FLAT_ATOMIC_XOR_SADDR_gfx12
    UINT64_C(36028800737804288), UINT64_C(0),	// FLAT_ATOMIC_XOR_X2_RTN_agpr_vi
    UINT64_C(3714908160), UINT64_C(0),	// FLAT_ATOMIC_XOR_X2_RTN_ci
    UINT64_C(35184375803740160), UINT64_C(0),	// FLAT_ATOMIC_XOR_X2_RTN_gfx10
    UINT64_C(34902900822786048), UINT64_C(0),	// FLAT_ATOMIC_XOR_X2_RTN_gfx11
    UINT64_C(4503603588022396), UINT64_C(0),	// FLAT_ATOMIC_XOR_X2_RTN_gfx12
    UINT64_C(3718840320), UINT64_C(0),	// FLAT_ATOMIC_XOR_X2_RTN_vi
    UINT64_C(4503603588022272), UINT64_C(0),	// FLAT_ATOMIC_XOR_X2_SADDR_RTN_gfx12
    UINT64_C(3960651776), UINT64_C(0),	// FLAT_ATOMIC_XOR_X2_SADDR_gfx12
    UINT64_C(3714842624), UINT64_C(0),	// FLAT_ATOMIC_XOR_X2_ci
    UINT64_C(35184375803674624), UINT64_C(0),	// FLAT_ATOMIC_XOR_X2_gfx10
    UINT64_C(34902900822769664), UINT64_C(0),	// FLAT_ATOMIC_XOR_X2_gfx11
    UINT64_C(3960651900), UINT64_C(0),	// FLAT_ATOMIC_XOR_X2_gfx12
    UINT64_C(3718774784), UINT64_C(0),	// FLAT_ATOMIC_XOR_X2_vi
    UINT64_C(3706454016), UINT64_C(0),	// FLAT_ATOMIC_XOR_ci
    UINT64_C(35184375795286016), UINT64_C(0),	// FLAT_ATOMIC_XOR_gfx10
    UINT64_C(34902900819361792), UINT64_C(0),	// FLAT_ATOMIC_XOR_gfx11
    UINT64_C(3960438908), UINT64_C(0),	// FLAT_ATOMIC_XOR_gfx12
    UINT64_C(3710386176), UINT64_C(0),	// FLAT_ATOMIC_XOR_vi
    UINT64_C(3959767040), UINT64_C(0),	// FLAT_LOAD_DWORDX2_SADDR_gfx12
    UINT64_C(3694395392), UINT64_C(0),	// FLAT_LOAD_DWORDX2_ci
    UINT64_C(35184375783227392), UINT64_C(0),	// FLAT_LOAD_DWORDX2_gfx10
    UINT64_C(34902900808613888), UINT64_C(0),	// FLAT_LOAD_DWORDX2_gfx11
    UINT64_C(3959767164), UINT64_C(0),	// FLAT_LOAD_DWORDX2_gfx12
    UINT64_C(3696492544), UINT64_C(0),	// FLAT_LOAD_DWORDX2_vi
    UINT64_C(3959783424), UINT64_C(0),	// FLAT_LOAD_DWORDX3_SADDR_gfx12
    UINT64_C(3694919680), UINT64_C(0),	// FLAT_LOAD_DWORDX3_ci
    UINT64_C(35184375783751680), UINT64_C(0),	// FLAT_LOAD_DWORDX3_gfx10
    UINT64_C(34902900808876032), UINT64_C(0),	// FLAT_LOAD_DWORDX3_gfx11
    UINT64_C(3959783548), UINT64_C(0),	// FLAT_LOAD_DWORDX3_gfx12
    UINT64_C(3696754688), UINT64_C(0),	// FLAT_LOAD_DWORDX3_vi
    UINT64_C(3959799808), UINT64_C(0),	// FLAT_LOAD_DWORDX4_SADDR_gfx12
    UINT64_C(3694657536), UINT64_C(0),	// FLAT_LOAD_DWORDX4_ci
    UINT64_C(35184375783489536), UINT64_C(0),	// FLAT_LOAD_DWORDX4_gfx10
    UINT64_C(34902900809138176), UINT64_C(0),	// FLAT_LOAD_DWORDX4_gfx11
    UINT64_C(3959799932), UINT64_C(0),	// FLAT_LOAD_DWORDX4_gfx12
    UINT64_C(3697016832), UINT64_C(0),	// FLAT_LOAD_DWORDX4_vi
    UINT64_C(3959750656), UINT64_C(0),	// FLAT_LOAD_DWORD_SADDR_gfx12
    UINT64_C(3694133248), UINT64_C(0),	// FLAT_LOAD_DWORD_ci
    UINT64_C(35184375782965248), UINT64_C(0),	// FLAT_LOAD_DWORD_gfx10
    UINT64_C(34902900808351744), UINT64_C(0),	// FLAT_LOAD_DWORD_gfx11
    UINT64_C(3959750780), UINT64_C(0),	// FLAT_LOAD_DWORD_gfx12
    UINT64_C(3696230400), UINT64_C(0),	// FLAT_LOAD_DWORD_vi
    UINT64_C(3961290752), UINT64_C(0),	// FLAT_LOAD_MONITOR_B128_SADDR_gfx1250
    UINT64_C(3961290876), UINT64_C(0),	// FLAT_LOAD_MONITOR_B128_gfx1250
    UINT64_C(3961257984), UINT64_C(0),	// FLAT_LOAD_MONITOR_B32_SADDR_gfx1250
    UINT64_C(3961258108), UINT64_C(0),	// FLAT_LOAD_MONITOR_B32_gfx1250
    UINT64_C(3961274368), UINT64_C(0),	// FLAT_LOAD_MONITOR_B64_SADDR_gfx1250
    UINT64_C(3961274492), UINT64_C(0),	// FLAT_LOAD_MONITOR_B64_gfx1250
    UINT64_C(3959980032), UINT64_C(0),	// FLAT_LOAD_SBYTE_D16_HI_SADDR_gfx12
    UINT64_C(35184375788994560), UINT64_C(0),	// FLAT_LOAD_SBYTE_D16_HI_gfx10
    UINT64_C(34902900812021760), UINT64_C(0),	// FLAT_LOAD_SBYTE_D16_HI_gfx11
    UINT64_C(3959980156), UINT64_C(0),	// FLAT_LOAD_SBYTE_D16_HI_gfx12
    UINT64_C(3700162560), UINT64_C(0),	// FLAT_LOAD_SBYTE_D16_HI_vi
    UINT64_C(3959930880), UINT64_C(0),	// FLAT_LOAD_SBYTE_D16_SADDR_gfx12
    UINT64_C(35184375788732416), UINT64_C(0),	// FLAT_LOAD_SBYTE_D16_gfx10
    UINT64_C(34902900811235328), UINT64_C(0),	// FLAT_LOAD_SBYTE_D16_gfx11
    UINT64_C(3959931004), UINT64_C(0),	// FLAT_LOAD_SBYTE_D16_gfx12
    UINT64_C(3699900416), UINT64_C(0),	// FLAT_LOAD_SBYTE_D16_vi
    UINT64_C(3959701504), UINT64_C(0),	// FLAT_LOAD_SBYTE_SADDR_gfx12
    UINT64_C(3693346816), UINT64_C(0),	// FLAT_LOAD_SBYTE_ci
    UINT64_C(35184375782178816), UINT64_C(0),	// FLAT_LOAD_SBYTE_gfx10
    UINT64_C(34902900807565312), UINT64_C(0),	// FLAT_LOAD_SBYTE_gfx11
    UINT64_C(3959701628), UINT64_C(0),	// FLAT_LOAD_SBYTE_gfx12
    UINT64_C(3695443968), UINT64_C(0),	// FLAT_LOAD_SBYTE_vi
    UINT64_C(3959996416), UINT64_C(0),	// FLAT_LOAD_SHORT_D16_HI_SADDR_gfx12
    UINT64_C(35184375789518848), UINT64_C(0),	// FLAT_LOAD_SHORT_D16_HI_gfx10
    UINT64_C(34902900812283904), UINT64_C(0),	// FLAT_LOAD_SHORT_D16_HI_gfx11
    UINT64_C(3959996540), UINT64_C(0),	// FLAT_LOAD_SHORT_D16_HI_gfx12
    UINT64_C(3700686848), UINT64_C(0),	// FLAT_LOAD_SHORT_D16_HI_vi
    UINT64_C(3959947264), UINT64_C(0),	// FLAT_LOAD_SHORT_D16_SADDR_gfx12
    UINT64_C(35184375789256704), UINT64_C(0),	// FLAT_LOAD_SHORT_D16_gfx10
    UINT64_C(34902900811497472), UINT64_C(0),	// FLAT_LOAD_SHORT_D16_gfx11
    UINT64_C(3959947388), UINT64_C(0),	// FLAT_LOAD_SHORT_D16_gfx12
    UINT64_C(3700424704), UINT64_C(0),	// FLAT_LOAD_SHORT_D16_vi
    UINT64_C(3959734272), UINT64_C(0),	// FLAT_LOAD_SSHORT_SADDR_gfx12
    UINT64_C(3693871104), UINT64_C(0),	// FLAT_LOAD_SSHORT_ci
    UINT64_C(35184375782703104), UINT64_C(0),	// FLAT_LOAD_SSHORT_gfx10
    UINT64_C(34902900808089600), UINT64_C(0),	// FLAT_LOAD_SSHORT_gfx11
    UINT64_C(3959734396), UINT64_C(0),	// FLAT_LOAD_SSHORT_gfx12
    UINT64_C(3695968256), UINT64_C(0),	// FLAT_LOAD_SSHORT_vi
    UINT64_C(3959963648), UINT64_C(0),	// FLAT_LOAD_UBYTE_D16_HI_SADDR_gfx12
    UINT64_C(35184375788470272), UINT64_C(0),	// FLAT_LOAD_UBYTE_D16_HI_gfx10
    UINT64_C(34902900811759616), UINT64_C(0),	// FLAT_LOAD_UBYTE_D16_HI_gfx11
    UINT64_C(3959963772), UINT64_C(0),	// FLAT_LOAD_UBYTE_D16_HI_gfx12
    UINT64_C(3699638272), UINT64_C(0),	// FLAT_LOAD_UBYTE_D16_HI_vi
    UINT64_C(3959914496), UINT64_C(0),	// FLAT_LOAD_UBYTE_D16_SADDR_gfx12
    UINT64_C(35184375788208128), UINT64_C(0),	// FLAT_LOAD_UBYTE_D16_gfx10
    UINT64_C(34902900810973184), UINT64_C(0),	// FLAT_LOAD_UBYTE_D16_gfx11
    UINT64_C(3959914620), UINT64_C(0),	// FLAT_LOAD_UBYTE_D16_gfx12
    UINT64_C(3699376128), UINT64_C(0),	// FLAT_LOAD_UBYTE_D16_vi
    UINT64_C(3959685120), UINT64_C(0),	// FLAT_LOAD_UBYTE_SADDR_gfx12
    UINT64_C(3693084672), UINT64_C(0),	// FLAT_LOAD_UBYTE_ci
    UINT64_C(35184375781916672), UINT64_C(0),	// FLAT_LOAD_UBYTE_gfx10
    UINT64_C(34902900807303168), UINT64_C(0),	// FLAT_LOAD_UBYTE_gfx11
    UINT64_C(3959685244), UINT64_C(0),	// FLAT_LOAD_UBYTE_gfx12
    UINT64_C(3695181824), UINT64_C(0),	// FLAT_LOAD_UBYTE_vi
    UINT64_C(3959717888), UINT64_C(0),	// FLAT_LOAD_USHORT_SADDR_gfx12
    UINT64_C(3693608960), UINT64_C(0),	// FLAT_LOAD_USHORT_ci
    UINT64_C(35184375782440960), UINT64_C(0),	// FLAT_LOAD_USHORT_gfx10
    UINT64_C(34902900807827456), UINT64_C(0),	// FLAT_LOAD_USHORT_gfx11
    UINT64_C(3959718012), UINT64_C(0),	// FLAT_LOAD_USHORT_gfx12
    UINT64_C(3695706112), UINT64_C(0),	// FLAT_LOAD_USHORT_vi
    UINT64_C(3960946688), UINT64_C(0),	// FLAT_PREFETCH_B8_SADDR_gfx1250
    UINT64_C(3960946812), UINT64_C(0),	// FLAT_PREFETCH_B8_gfx1250
    UINT64_C(3960012800), UINT64_C(0),	// FLAT_STORE_BYTE_D16_HI_SADDR_gfx12
    UINT64_C(35184375786373120), UINT64_C(0),	// FLAT_STORE_BYTE_D16_HI_gfx10
    UINT64_C(34902900812546048), UINT64_C(0),	// FLAT_STORE_BYTE_D16_HI_gfx11
    UINT64_C(3960012924), UINT64_C(0),	// FLAT_STORE_BYTE_D16_HI_gfx12
    UINT64_C(3697541120), UINT64_C(0),	// FLAT_STORE_BYTE_D16_HI_vi
    UINT64_C(3959816192), UINT64_C(0),	// FLAT_STORE_BYTE_SADDR_gfx12
    UINT64_C(3697278976), UINT64_C(0),	// FLAT_STORE_BYTE_ci
    UINT64_C(35184375786110976), UINT64_C(0),	// FLAT_STORE_BYTE_gfx10
    UINT64_C(34902900809400320), UINT64_C(0),	// FLAT_STORE_BYTE_gfx11
    UINT64_C(3959816316), UINT64_C(0),	// FLAT_STORE_BYTE_gfx12
    UINT64_C(3697278976), UINT64_C(0),	// FLAT_STORE_BYTE_vi
    UINT64_C(3959865344), UINT64_C(0),	// FLAT_STORE_DWORDX2_SADDR_gfx12
    UINT64_C(3698589696), UINT64_C(0),	// FLAT_STORE_DWORDX2_ci
    UINT64_C(35184375787421696), UINT64_C(0),	// FLAT_STORE_DWORDX2_gfx10
    UINT64_C(34902900810186752), UINT64_C(0),	// FLAT_STORE_DWORDX2_gfx11
    UINT64_C(3959865468), UINT64_C(0),	// FLAT_STORE_DWORDX2_gfx12
    UINT64_C(3698589696), UINT64_C(0),	// FLAT_STORE_DWORDX2_vi
    UINT64_C(3959881728), UINT64_C(0),	// FLAT_STORE_DWORDX3_SADDR_gfx12
    UINT64_C(3699113984), UINT64_C(0),	// FLAT_STORE_DWORDX3_ci
    UINT64_C(35184375787945984), UINT64_C(0),	// FLAT_STORE_DWORDX3_gfx10
    UINT64_C(34902900810448896), UINT64_C(0),	// FLAT_STORE_DWORDX3_gfx11
    UINT64_C(3959881852), UINT64_C(0),	// FLAT_STORE_DWORDX3_gfx12
    UINT64_C(3698851840), UINT64_C(0),	// FLAT_STORE_DWORDX3_vi
    UINT64_C(3959898112), UINT64_C(0),	// FLAT_STORE_DWORDX4_SADDR_gfx12
    UINT64_C(3698851840), UINT64_C(0),	// FLAT_STORE_DWORDX4_ci
    UINT64_C(35184375787683840), UINT64_C(0),	// FLAT_STORE_DWORDX4_gfx10
    UINT64_C(34902900810711040), UINT64_C(0),	// FLAT_STORE_DWORDX4_gfx11
    UINT64_C(3959898236), UINT64_C(0),	// FLAT_STORE_DWORDX4_gfx12
    UINT64_C(3699113984), UINT64_C(0),	// FLAT_STORE_DWORDX4_vi
    UINT64_C(3959848960), UINT64_C(0),	// FLAT_STORE_DWORD_SADDR_gfx12
    UINT64_C(3698327552), UINT64_C(0),	// FLAT_STORE_DWORD_ci
    UINT64_C(35184375787159552), UINT64_C(0),	// FLAT_STORE_DWORD_gfx10
    UINT64_C(34902900809924608), UINT64_C(0),	// FLAT_STORE_DWORD_gfx11
    UINT64_C(3959849084), UINT64_C(0),	// FLAT_STORE_DWORD_gfx12
    UINT64_C(3698327552), UINT64_C(0),	// FLAT_STORE_DWORD_vi
    UINT64_C(3960029184), UINT64_C(0),	// FLAT_STORE_SHORT_D16_HI_SADDR_gfx12
    UINT64_C(35184375786897408), UINT64_C(0),	// FLAT_STORE_SHORT_D16_HI_gfx10
    UINT64_C(34902900812808192), UINT64_C(0),	// FLAT_STORE_SHORT_D16_HI_gfx11
    UINT64_C(3960029308), UINT64_C(0),	// FLAT_STORE_SHORT_D16_HI_gfx12
    UINT64_C(3698065408), UINT64_C(0),	// FLAT_STORE_SHORT_D16_HI_vi
    UINT64_C(3959832576), UINT64_C(0),	// FLAT_STORE_SHORT_SADDR_gfx12
    UINT64_C(3697803264), UINT64_C(0),	// FLAT_STORE_SHORT_ci
    UINT64_C(35184375786635264), UINT64_C(0),	// FLAT_STORE_SHORT_gfx10
    UINT64_C(34902900809662464), UINT64_C(0),	// FLAT_STORE_SHORT_gfx11
    UINT64_C(3959832700), UINT64_C(0),	// FLAT_STORE_SHORT_gfx12
    UINT64_C(3697803264), UINT64_C(0),	// FLAT_STORE_SHORT_vi
    UINT64_C(71776122772488192), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F32_RTN_agpr_vi
    UINT64_C(34902900825800704), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F32_RTN_gfx11
    UINT64_C(4503603621757052), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F32_RTN_gfx12
    UINT64_C(35747325753524224), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F32_RTN_gfx940
    UINT64_C(35747325753524224), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F32_RTN_vi
    UINT64_C(36028800730234880), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F32_SADDR_RTN_agpr_vi
    UINT64_C(3713679360), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F32_SADDR_RTN_gfx11
    UINT64_C(4503603621756928), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F32_SADDR_RTN_gfx12
    UINT64_C(3711270912), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F32_SADDR_RTN_gfx940
    UINT64_C(3711270912), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F32_SADDR_RTN_vi
    UINT64_C(3713662976), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F32_SADDR_gfx11
    UINT64_C(3994386432), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F32_SADDR_gfx12
    UINT64_C(3711205376), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F32_SADDR_gfx940
    UINT64_C(3711205376), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F32_SADDR_vi
    UINT64_C(34902900825784320), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F32_gfx11
    UINT64_C(3994386556), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F32_gfx12
    UINT64_C(35747325753458688), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F32_gfx940
    UINT64_C(35747325753458688), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F32_vi
    UINT64_C(71776122773012480), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F64_RTN_agpr_vi
    UINT64_C(4503603621740668), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F64_RTN_gfx1250
    UINT64_C(35747325754048512), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F64_RTN_gfx940
    UINT64_C(35747325754048512), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F64_RTN_vi
    UINT64_C(36028800730759168), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F64_SADDR_RTN_agpr_vi
    UINT64_C(4503603621740544), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F64_SADDR_RTN_gfx1250
    UINT64_C(3711795200), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F64_SADDR_RTN_gfx940
    UINT64_C(3711795200), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F64_SADDR_RTN_vi
    UINT64_C(3994370048), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F64_SADDR_gfx1250
    UINT64_C(3711729664), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F64_SADDR_gfx940
    UINT64_C(3711729664), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F64_SADDR_vi
    UINT64_C(3994370172), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F64_gfx1250
    UINT64_C(35747325753982976), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F64_gfx940
    UINT64_C(35747325753982976), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_F64_vi
    UINT64_C(71776122769604608), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_RTN_agpr_vi
    UINT64_C(35184375793025024), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_RTN_gfx10
    UINT64_C(34902900817149952), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_RTN_gfx11
    UINT64_C(4503603621216380), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_RTN_gfx12
    UINT64_C(35747325750640640), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_RTN_vi
    UINT64_C(36028800727351296), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_SADDR_RTN_agpr_vi
    UINT64_C(3704193024), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_SADDR_RTN_gfx10
    UINT64_C(3705028608), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_SADDR_RTN_gfx11
    UINT64_C(4503603621216256), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_SADDR_RTN_gfx12
    UINT64_C(3708387328), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_SADDR_RTN_vi
    UINT64_C(3704127488), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_SADDR_gfx10
    UINT64_C(3705012224), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_SADDR_gfx11
    UINT64_C(3993845760), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_SADDR_gfx12
    UINT64_C(3708321792), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_SADDR_vi
    UINT64_C(71776122777993216), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_X2_RTN_agpr_vi
    UINT64_C(35184375801413632), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_X2_RTN_gfx10
    UINT64_C(34902900820819968), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_X2_RTN_gfx11
    UINT64_C(4503603621445756), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_X2_RTN_gfx12
    UINT64_C(35747325759029248), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_X2_RTN_vi
    UINT64_C(36028800735739904), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_agpr_vi
    UINT64_C(3712581632), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_gfx10
    UINT64_C(3708698624), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_gfx11
    UINT64_C(4503603621445632), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_gfx12
    UINT64_C(3716775936), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_vi
    UINT64_C(3712516096), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_X2_SADDR_gfx10
    UINT64_C(3708682240), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_X2_SADDR_gfx11
    UINT64_C(3994075136), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_X2_SADDR_gfx12
    UINT64_C(3716710400), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_X2_SADDR_vi
    UINT64_C(35184375801348096), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_X2_gfx10
    UINT64_C(34902900820803584), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_X2_gfx11
    UINT64_C(3994075260), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_X2_gfx12
    UINT64_C(35747325758963712), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_X2_vi
    UINT64_C(35184375792959488), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_gfx10
    UINT64_C(34902900817133568), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_gfx11
    UINT64_C(3993845884), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_gfx12
    UINT64_C(35747325750575104), UINT64_C(0),	// GLOBAL_ATOMIC_ADD_vi
    UINT64_C(71776122771177472), UINT64_C(0),	// GLOBAL_ATOMIC_AND_RTN_agpr_vi
    UINT64_C(35184375794860032), UINT64_C(0),	// GLOBAL_ATOMIC_AND_RTN_gfx10
    UINT64_C(34902900818984960), UINT64_C(0),	// GLOBAL_ATOMIC_AND_RTN_gfx11
    UINT64_C(4503603621331068), UINT64_C(0),	// GLOBAL_ATOMIC_AND_RTN_gfx12
    UINT64_C(35747325752213504), UINT64_C(0),	// GLOBAL_ATOMIC_AND_RTN_vi
    UINT64_C(36028800728924160), UINT64_C(0),	// GLOBAL_ATOMIC_AND_SADDR_RTN_agpr_vi
    UINT64_C(3706028032), UINT64_C(0),	// GLOBAL_ATOMIC_AND_SADDR_RTN_gfx10
    UINT64_C(3706863616), UINT64_C(0),	// GLOBAL_ATOMIC_AND_SADDR_RTN_gfx11
    UINT64_C(4503603621330944), UINT64_C(0),	// GLOBAL_ATOMIC_AND_SADDR_RTN_gfx12
    UINT64_C(3709960192), UINT64_C(0),	// GLOBAL_ATOMIC_AND_SADDR_RTN_vi
    UINT64_C(3705962496), UINT64_C(0),	// GLOBAL_ATOMIC_AND_SADDR_gfx10
    UINT64_C(3706847232), UINT64_C(0),	// GLOBAL_ATOMIC_AND_SADDR_gfx11
    UINT64_C(3993960448), UINT64_C(0),	// GLOBAL_ATOMIC_AND_SADDR_gfx12
    UINT64_C(3709894656), UINT64_C(0),	// GLOBAL_ATOMIC_AND_SADDR_vi
    UINT64_C(71776122779566080), UINT64_C(0),	// GLOBAL_ATOMIC_AND_X2_RTN_agpr_vi
    UINT64_C(35184375803248640), UINT64_C(0),	// GLOBAL_ATOMIC_AND_X2_RTN_gfx10
    UINT64_C(34902900822392832), UINT64_C(0),	// GLOBAL_ATOMIC_AND_X2_RTN_gfx11
    UINT64_C(4503603621544060), UINT64_C(0),	// GLOBAL_ATOMIC_AND_X2_RTN_gfx12
    UINT64_C(35747325760602112), UINT64_C(0),	// GLOBAL_ATOMIC_AND_X2_RTN_vi
    UINT64_C(36028800737312768), UINT64_C(0),	// GLOBAL_ATOMIC_AND_X2_SADDR_RTN_agpr_vi
    UINT64_C(3714416640), UINT64_C(0),	// GLOBAL_ATOMIC_AND_X2_SADDR_RTN_gfx10
    UINT64_C(3710271488), UINT64_C(0),	// GLOBAL_ATOMIC_AND_X2_SADDR_RTN_gfx11
    UINT64_C(4503603621543936), UINT64_C(0),	// GLOBAL_ATOMIC_AND_X2_SADDR_RTN_gfx12
    UINT64_C(3718348800), UINT64_C(0),	// GLOBAL_ATOMIC_AND_X2_SADDR_RTN_vi
    UINT64_C(3714351104), UINT64_C(0),	// GLOBAL_ATOMIC_AND_X2_SADDR_gfx10
    UINT64_C(3710255104), UINT64_C(0),	// GLOBAL_ATOMIC_AND_X2_SADDR_gfx11
    UINT64_C(3994173440), UINT64_C(0),	// GLOBAL_ATOMIC_AND_X2_SADDR_gfx12
    UINT64_C(3718283264), UINT64_C(0),	// GLOBAL_ATOMIC_AND_X2_SADDR_vi
    UINT64_C(35184375803183104), UINT64_C(0),	// GLOBAL_ATOMIC_AND_X2_gfx10
    UINT64_C(34902900822376448), UINT64_C(0),	// GLOBAL_ATOMIC_AND_X2_gfx11
    UINT64_C(3994173564), UINT64_C(0),	// GLOBAL_ATOMIC_AND_X2_gfx12
    UINT64_C(35747325760536576), UINT64_C(0),	// GLOBAL_ATOMIC_AND_X2_vi
    UINT64_C(35184375794794496), UINT64_C(0),	// GLOBAL_ATOMIC_AND_gfx10
    UINT64_C(34902900818968576), UINT64_C(0),	// GLOBAL_ATOMIC_AND_gfx11
    UINT64_C(3993960572), UINT64_C(0),	// GLOBAL_ATOMIC_AND_gfx12
    UINT64_C(35747325752147968), UINT64_C(0),	// GLOBAL_ATOMIC_AND_vi
    UINT64_C(71776122769342464), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_RTN_agpr_vi
    UINT64_C(35184375792762880), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_RTN_gfx10
    UINT64_C(34902900816887808), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_RTN_gfx11
    UINT64_C(4503603621199996), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_RTN_gfx12
    UINT64_C(35747325750378496), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_RTN_vi
    UINT64_C(36028800727089152), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_agpr_vi
    UINT64_C(3703930880), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_gfx10
    UINT64_C(3704766464), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_gfx11
    UINT64_C(4503603621199872), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_gfx12
    UINT64_C(3708125184), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_vi
    UINT64_C(3703865344), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_SADDR_gfx10
    UINT64_C(3704750080), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_SADDR_gfx11
    UINT64_C(3993829376), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_SADDR_gfx12
    UINT64_C(3708059648), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_SADDR_vi
    UINT64_C(71776122777731072), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_X2_RTN_agpr_vi
    UINT64_C(35184375801151488), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_X2_RTN_gfx10
    UINT64_C(34902900820557824), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_X2_RTN_gfx11
    UINT64_C(4503603621429372), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_X2_RTN_gfx12
    UINT64_C(35747325758767104), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_X2_RTN_vi
    UINT64_C(36028800735477760), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_agpr_vi
    UINT64_C(3712319488), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_gfx10
    UINT64_C(3708436480), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_gfx11
    UINT64_C(4503603621429248), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_gfx12
    UINT64_C(3716513792), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_vi
    UINT64_C(3712253952), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_gfx10
    UINT64_C(3708420096), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_gfx11
    UINT64_C(3994058752), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_gfx12
    UINT64_C(3716448256), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_vi
    UINT64_C(35184375801085952), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_X2_gfx10
    UINT64_C(34902900820541440), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_X2_gfx11
    UINT64_C(3994058876), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_X2_gfx12
    UINT64_C(35747325758701568), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_X2_vi
    UINT64_C(35184375792697344), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_gfx10
    UINT64_C(34902900816871424), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_gfx11
    UINT64_C(3993829500), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_gfx12
    UINT64_C(35747325750312960), UINT64_C(0),	// GLOBAL_ATOMIC_CMPSWAP_vi
    UINT64_C(4503603621658748), UINT64_C(0),	// GLOBAL_ATOMIC_COND_SUB_U32_RTN_gfx12
    UINT64_C(4503603621658624), UINT64_C(0),	// GLOBAL_ATOMIC_COND_SUB_U32_SADDR_RTN_gfx12
    UINT64_C(3994288128), UINT64_C(0),	// GLOBAL_ATOMIC_COND_SUB_U32_SADDR_gfx12
    UINT64_C(3994288252), UINT64_C(0),	// GLOBAL_ATOMIC_COND_SUB_U32_gfx12
    UINT64_C(35184375793549312), UINT64_C(0),	// GLOBAL_ATOMIC_CSUB_RTN_gfx10
    UINT64_C(34902900817674240), UINT64_C(0),	// GLOBAL_ATOMIC_CSUB_RTN_gfx11
    UINT64_C(4503603621249148), UINT64_C(0),	// GLOBAL_ATOMIC_CSUB_RTN_gfx12
    UINT64_C(3704717312), UINT64_C(0),	// GLOBAL_ATOMIC_CSUB_SADDR_RTN_gfx10
    UINT64_C(3705552896), UINT64_C(0),	// GLOBAL_ATOMIC_CSUB_SADDR_RTN_gfx11
    UINT64_C(4503603621249024), UINT64_C(0),	// GLOBAL_ATOMIC_CSUB_SADDR_RTN_gfx12
    UINT64_C(3704651776), UINT64_C(0),	// GLOBAL_ATOMIC_CSUB_SADDR_gfx10
    UINT64_C(3705536512), UINT64_C(0),	// GLOBAL_ATOMIC_CSUB_SADDR_gfx11
    UINT64_C(3993878528), UINT64_C(0),	// GLOBAL_ATOMIC_CSUB_SADDR_gfx12
    UINT64_C(35184375793483776), UINT64_C(0),	// GLOBAL_ATOMIC_CSUB_gfx10
    UINT64_C(34902900817657856), UINT64_C(0),	// GLOBAL_ATOMIC_CSUB_gfx11
    UINT64_C(3993878652), UINT64_C(0),	// GLOBAL_ATOMIC_CSUB_gfx12
    UINT64_C(71776122772226048), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_RTN_agpr_vi
    UINT64_C(35184375795908608), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_RTN_gfx10
    UINT64_C(34902900820033536), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_RTN_gfx11
    UINT64_C(4503603621396604), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_RTN_gfx12
    UINT64_C(35747325753262080), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_RTN_vi
    UINT64_C(36028800729972736), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_SADDR_RTN_agpr_vi
    UINT64_C(3707076608), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_SADDR_RTN_gfx10
    UINT64_C(3707912192), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_SADDR_RTN_gfx11
    UINT64_C(4503603621396480), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_SADDR_RTN_gfx12
    UINT64_C(3711008768), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_SADDR_RTN_vi
    UINT64_C(3707011072), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_SADDR_gfx10
    UINT64_C(3707895808), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_SADDR_gfx11
    UINT64_C(3994025984), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_SADDR_gfx12
    UINT64_C(3710943232), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_SADDR_vi
    UINT64_C(71776122780614656), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_X2_RTN_agpr_vi
    UINT64_C(35184375804297216), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_X2_RTN_gfx10
    UINT64_C(34902900823441408), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_X2_RTN_gfx11
    UINT64_C(4503603621609596), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_X2_RTN_gfx12
    UINT64_C(35747325761650688), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_X2_RTN_vi
    UINT64_C(36028800738361344), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_agpr_vi
    UINT64_C(3715465216), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_gfx10
    UINT64_C(3711320064), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_gfx11
    UINT64_C(4503603621609472), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_gfx12
    UINT64_C(3719397376), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_vi
    UINT64_C(3715399680), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_X2_SADDR_gfx10
    UINT64_C(3711303680), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_X2_SADDR_gfx11
    UINT64_C(3994238976), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_X2_SADDR_gfx12
    UINT64_C(3719331840), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_X2_SADDR_vi
    UINT64_C(35184375804231680), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_X2_gfx10
    UINT64_C(34902900823425024), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_X2_gfx11
    UINT64_C(3994239100), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_X2_gfx12
    UINT64_C(35747325761585152), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_X2_vi
    UINT64_C(35184375795843072), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_gfx10
    UINT64_C(34902900820017152), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_gfx11
    UINT64_C(3994026108), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_gfx12
    UINT64_C(35747325753196544), UINT64_C(0),	// GLOBAL_ATOMIC_DEC_vi
    UINT64_C(35184375796170752), UINT64_C(0),	// GLOBAL_ATOMIC_FCMPSWAP_RTN_gfx10
    UINT64_C(34902900824227840), UINT64_C(0),	// GLOBAL_ATOMIC_FCMPSWAP_RTN_gfx11
    UINT64_C(3707338752), UINT64_C(0),	// GLOBAL_ATOMIC_FCMPSWAP_SADDR_RTN_gfx10
    UINT64_C(3712106496), UINT64_C(0),	// GLOBAL_ATOMIC_FCMPSWAP_SADDR_RTN_gfx11
    UINT64_C(3707273216), UINT64_C(0),	// GLOBAL_ATOMIC_FCMPSWAP_SADDR_gfx10
    UINT64_C(3712090112), UINT64_C(0),	// GLOBAL_ATOMIC_FCMPSWAP_SADDR_gfx11
    UINT64_C(35184375804559360), UINT64_C(0),	// GLOBAL_ATOMIC_FCMPSWAP_X2_RTN_gfx10
    UINT64_C(3715727360), UINT64_C(0),	// GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_RTN_gfx10
    UINT64_C(3715661824), UINT64_C(0),	// GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_gfx10
    UINT64_C(35184375804493824), UINT64_C(0),	// GLOBAL_ATOMIC_FCMPSWAP_X2_gfx10
    UINT64_C(35184375796105216), UINT64_C(0),	// GLOBAL_ATOMIC_FCMPSWAP_gfx10
    UINT64_C(34902900824211456), UINT64_C(0),	// GLOBAL_ATOMIC_FCMPSWAP_gfx11
    UINT64_C(35184375796695040), UINT64_C(0),	// GLOBAL_ATOMIC_FMAX_RTN_gfx10
    UINT64_C(34902900824752128), UINT64_C(0),	// GLOBAL_ATOMIC_FMAX_RTN_gfx11
    UINT64_C(4503603621691516), UINT64_C(0),	// GLOBAL_ATOMIC_FMAX_RTN_gfx12
    UINT64_C(3707863040), UINT64_C(0),	// GLOBAL_ATOMIC_FMAX_SADDR_RTN_gfx10
    UINT64_C(3712630784), UINT64_C(0),	// GLOBAL_ATOMIC_FMAX_SADDR_RTN_gfx11
    UINT64_C(4503603621691392), UINT64_C(0),	// GLOBAL_ATOMIC_FMAX_SADDR_RTN_gfx12
    UINT64_C(3707797504), UINT64_C(0),	// GLOBAL_ATOMIC_FMAX_SADDR_gfx10
    UINT64_C(3712614400), UINT64_C(0),	// GLOBAL_ATOMIC_FMAX_SADDR_gfx11
    UINT64_C(3994320896), UINT64_C(0),	// GLOBAL_ATOMIC_FMAX_SADDR_gfx12
    UINT64_C(35184375805083648), UINT64_C(0),	// GLOBAL_ATOMIC_FMAX_X2_RTN_gfx10
    UINT64_C(3716251648), UINT64_C(0),	// GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN_gfx10
    UINT64_C(3716186112), UINT64_C(0),	// GLOBAL_ATOMIC_FMAX_X2_SADDR_gfx10
    UINT64_C(35184375805018112), UINT64_C(0),	// GLOBAL_ATOMIC_FMAX_X2_gfx10
    UINT64_C(35184375796629504), UINT64_C(0),	// GLOBAL_ATOMIC_FMAX_gfx10
    UINT64_C(34902900824735744), UINT64_C(0),	// GLOBAL_ATOMIC_FMAX_gfx11
    UINT64_C(3994321020), UINT64_C(0),	// GLOBAL_ATOMIC_FMAX_gfx12
    UINT64_C(35184375796432896), UINT64_C(0),	// GLOBAL_ATOMIC_FMIN_RTN_gfx10
    UINT64_C(34902900824489984), UINT64_C(0),	// GLOBAL_ATOMIC_FMIN_RTN_gfx11
    UINT64_C(4503603621675132), UINT64_C(0),	// GLOBAL_ATOMIC_FMIN_RTN_gfx12
    UINT64_C(3707600896), UINT64_C(0),	// GLOBAL_ATOMIC_FMIN_SADDR_RTN_gfx10
    UINT64_C(3712368640), UINT64_C(0),	// GLOBAL_ATOMIC_FMIN_SADDR_RTN_gfx11
    UINT64_C(4503603621675008), UINT64_C(0),	// GLOBAL_ATOMIC_FMIN_SADDR_RTN_gfx12
    UINT64_C(3707535360), UINT64_C(0),	// GLOBAL_ATOMIC_FMIN_SADDR_gfx10
    UINT64_C(3712352256), UINT64_C(0),	// GLOBAL_ATOMIC_FMIN_SADDR_gfx11
    UINT64_C(3994304512), UINT64_C(0),	// GLOBAL_ATOMIC_FMIN_SADDR_gfx12
    UINT64_C(35184375804821504), UINT64_C(0),	// GLOBAL_ATOMIC_FMIN_X2_RTN_gfx10
    UINT64_C(3715989504), UINT64_C(0),	// GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN_gfx10
    UINT64_C(3715923968), UINT64_C(0),	// GLOBAL_ATOMIC_FMIN_X2_SADDR_gfx10
    UINT64_C(35184375804755968), UINT64_C(0),	// GLOBAL_ATOMIC_FMIN_X2_gfx10
    UINT64_C(35184375796367360), UINT64_C(0),	// GLOBAL_ATOMIC_FMIN_gfx10
    UINT64_C(34902900824473600), UINT64_C(0),	// GLOBAL_ATOMIC_FMIN_gfx11
    UINT64_C(3994304636), UINT64_C(0),	// GLOBAL_ATOMIC_FMIN_gfx12
    UINT64_C(71776122771963904), UINT64_C(0),	// GLOBAL_ATOMIC_INC_RTN_agpr_vi
    UINT64_C(35184375795646464), UINT64_C(0),	// GLOBAL_ATOMIC_INC_RTN_gfx10
    UINT64_C(34902900819771392), UINT64_C(0),	// GLOBAL_ATOMIC_INC_RTN_gfx11
    UINT64_C(4503603621380220), UINT64_C(0),	// GLOBAL_ATOMIC_INC_RTN_gfx12
    UINT64_C(35747325752999936), UINT64_C(0),	// GLOBAL_ATOMIC_INC_RTN_vi
    UINT64_C(36028800729710592), UINT64_C(0),	// GLOBAL_ATOMIC_INC_SADDR_RTN_agpr_vi
    UINT64_C(3706814464), UINT64_C(0),	// GLOBAL_ATOMIC_INC_SADDR_RTN_gfx10
    UINT64_C(3707650048), UINT64_C(0),	// GLOBAL_ATOMIC_INC_SADDR_RTN_gfx11
    UINT64_C(4503603621380096), UINT64_C(0),	// GLOBAL_ATOMIC_INC_SADDR_RTN_gfx12
    UINT64_C(3710746624), UINT64_C(0),	// GLOBAL_ATOMIC_INC_SADDR_RTN_vi
    UINT64_C(3706748928), UINT64_C(0),	// GLOBAL_ATOMIC_INC_SADDR_gfx10
    UINT64_C(3707633664), UINT64_C(0),	// GLOBAL_ATOMIC_INC_SADDR_gfx11
    UINT64_C(3994009600), UINT64_C(0),	// GLOBAL_ATOMIC_INC_SADDR_gfx12
    UINT64_C(3710681088), UINT64_C(0),	// GLOBAL_ATOMIC_INC_SADDR_vi
    UINT64_C(71776122780352512), UINT64_C(0),	// GLOBAL_ATOMIC_INC_X2_RTN_agpr_vi
    UINT64_C(35184375804035072), UINT64_C(0),	// GLOBAL_ATOMIC_INC_X2_RTN_gfx10
    UINT64_C(34902900823179264), UINT64_C(0),	// GLOBAL_ATOMIC_INC_X2_RTN_gfx11
    UINT64_C(4503603621593212), UINT64_C(0),	// GLOBAL_ATOMIC_INC_X2_RTN_gfx12
    UINT64_C(35747325761388544), UINT64_C(0),	// GLOBAL_ATOMIC_INC_X2_RTN_vi
    UINT64_C(36028800738099200), UINT64_C(0),	// GLOBAL_ATOMIC_INC_X2_SADDR_RTN_agpr_vi
    UINT64_C(3715203072), UINT64_C(0),	// GLOBAL_ATOMIC_INC_X2_SADDR_RTN_gfx10
    UINT64_C(3711057920), UINT64_C(0),	// GLOBAL_ATOMIC_INC_X2_SADDR_RTN_gfx11
    UINT64_C(4503603621593088), UINT64_C(0),	// GLOBAL_ATOMIC_INC_X2_SADDR_RTN_gfx12
    UINT64_C(3719135232), UINT64_C(0),	// GLOBAL_ATOMIC_INC_X2_SADDR_RTN_vi
    UINT64_C(3715137536), UINT64_C(0),	// GLOBAL_ATOMIC_INC_X2_SADDR_gfx10
    UINT64_C(3711041536), UINT64_C(0),	// GLOBAL_ATOMIC_INC_X2_SADDR_gfx11
    UINT64_C(3994222592), UINT64_C(0),	// GLOBAL_ATOMIC_INC_X2_SADDR_gfx12
    UINT64_C(3719069696), UINT64_C(0),	// GLOBAL_ATOMIC_INC_X2_SADDR_vi
    UINT64_C(35184375803969536), UINT64_C(0),	// GLOBAL_ATOMIC_INC_X2_gfx10
    UINT64_C(34902900823162880), UINT64_C(0),	// GLOBAL_ATOMIC_INC_X2_gfx11
    UINT64_C(3994222716), UINT64_C(0),	// GLOBAL_ATOMIC_INC_X2_gfx12
    UINT64_C(35747325761323008), UINT64_C(0),	// GLOBAL_ATOMIC_INC_X2_vi
    UINT64_C(35184375795580928), UINT64_C(0),	// GLOBAL_ATOMIC_INC_gfx10
    UINT64_C(34902900819755008), UINT64_C(0),	// GLOBAL_ATOMIC_INC_gfx11
    UINT64_C(3994009724), UINT64_C(0),	// GLOBAL_ATOMIC_INC_gfx12
    UINT64_C(35747325752934400), UINT64_C(0),	// GLOBAL_ATOMIC_INC_vi
    UINT64_C(71776122773536768), UINT64_C(0),	// GLOBAL_ATOMIC_MAX_F64_RTN_agpr_vi
    UINT64_C(4503603621855356), UINT64_C(0),	// GLOBAL_ATOMIC_MAX_F64_RTN_gfx1250
    UINT64_C(35747325754572800), UINT64_C(0),	// GLOBAL_ATOMIC_MAX_F64_RTN_gfx940
    UINT64_C(35747325754572800), UINT64_C(0),	// GLOBAL_ATOMIC_MAX_F64_RTN_vi
    UINT64_C(36028800731283456), UINT64_C(0),	// GLOBAL_ATOMIC_MAX_F64_SADDR_RTN_agpr_vi
    UINT64_C(4503603621855232), UINT64_C(0),	// GLOBAL_ATOMIC_MAX_F64_SADDR_RTN_gfx1250
    UINT64_C(3712319488), UINT64_C(0),	// GLOBAL_ATOMIC_MAX_F64_SADDR_RTN_gfx940
    UINT64_C(3712319488), UINT64_C(0),	// GLOBAL_ATOMIC_MAX_F64_SADDR_RTN_vi
    UINT64_C(3994484736), UINT64_C(0),	// GLOBAL_ATOMIC_MAX_F64_SADDR_gfx1250
    UINT64_C(3712253952), UINT64_C(0),	// GLOBAL_ATOMIC_MAX_F64_SADDR_gfx940
    UINT64_C(3712253952), UINT64_C(0),	// GLOBAL_ATOMIC_MAX_F64_SADDR_vi
    UINT64_C(3994484860), UINT64_C(0),	// GLOBAL_ATOMIC_MAX_F64_gfx1250
    UINT64_C(35747325754507264), UINT64_C(0),	// GLOBAL_ATOMIC_MAX_F64_gfx940
    UINT64_C(35747325754507264), UINT64_C(0),	// GLOBAL_ATOMIC_MAX_F64_vi
    UINT64_C(71776122773274624), UINT64_C(0),	// GLOBAL_ATOMIC_MIN_F64_RTN_agpr_vi
    UINT64_C(4503603621838972), UINT64_C(0),	// GLOBAL_ATOMIC_MIN_F64_RTN_gfx1250
    UINT64_C(35747325754310656), UINT64_C(0),	// GLOBAL_ATOMIC_MIN_F64_RTN_gfx940
    UINT64_C(35747325754310656), UINT64_C(0),	// GLOBAL_ATOMIC_MIN_F64_RTN_vi
    UINT64_C(36028800731021312), UINT64_C(0),	// GLOBAL_ATOMIC_MIN_F64_SADDR_RTN_agpr_vi
    UINT64_C(4503603621838848), UINT64_C(0),	// GLOBAL_ATOMIC_MIN_F64_SADDR_RTN_gfx1250
    UINT64_C(3712057344), UINT64_C(0),	// GLOBAL_ATOMIC_MIN_F64_SADDR_RTN_gfx940
    UINT64_C(3712057344), UINT64_C(0),	// GLOBAL_ATOMIC_MIN_F64_SADDR_RTN_vi
    UINT64_C(3994468352), UINT64_C(0),	// GLOBAL_ATOMIC_MIN_F64_SADDR_gfx1250
    UINT64_C(3711991808), UINT64_C(0),	// GLOBAL_ATOMIC_MIN_F64_SADDR_gfx940
    UINT64_C(3711991808), UINT64_C(0),	// GLOBAL_ATOMIC_MIN_F64_SADDR_vi
    UINT64_C(3994468476), UINT64_C(0),	// GLOBAL_ATOMIC_MIN_F64_gfx1250
    UINT64_C(35747325754245120), UINT64_C(0),	// GLOBAL_ATOMIC_MIN_F64_gfx940
    UINT64_C(35747325754245120), UINT64_C(0),	// GLOBAL_ATOMIC_MIN_F64_vi
    UINT64_C(4503603622232188), UINT64_C(0),	// GLOBAL_ATOMIC_ORDERED_ADD_B64_RTN_gfx12
    UINT64_C(4503603622232064), UINT64_C(0),	// GLOBAL_ATOMIC_ORDERED_ADD_B64_SADDR_RTN_gfx12
    UINT64_C(3994861568), UINT64_C(0),	// GLOBAL_ATOMIC_ORDERED_ADD_B64_SADDR_gfx12
    UINT64_C(3994861692), UINT64_C(0),	// GLOBAL_ATOMIC_ORDERED_ADD_B64_gfx12
    UINT64_C(71776122771439616), UINT64_C(0),	// GLOBAL_ATOMIC_OR_RTN_agpr_vi
    UINT64_C(35184375795122176), UINT64_C(0),	// GLOBAL_ATOMIC_OR_RTN_gfx10
    UINT64_C(34902900819247104), UINT64_C(0),	// GLOBAL_ATOMIC_OR_RTN_gfx11
    UINT64_C(4503603621347452), UINT64_C(0),	// GLOBAL_ATOMIC_OR_RTN_gfx12
    UINT64_C(35747325752475648), UINT64_C(0),	// GLOBAL_ATOMIC_OR_RTN_vi
    UINT64_C(36028800729186304), UINT64_C(0),	// GLOBAL_ATOMIC_OR_SADDR_RTN_agpr_vi
    UINT64_C(3706290176), UINT64_C(0),	// GLOBAL_ATOMIC_OR_SADDR_RTN_gfx10
    UINT64_C(3707125760), UINT64_C(0),	// GLOBAL_ATOMIC_OR_SADDR_RTN_gfx11
    UINT64_C(4503603621347328), UINT64_C(0),	// GLOBAL_ATOMIC_OR_SADDR_RTN_gfx12
    UINT64_C(3710222336), UINT64_C(0),	// GLOBAL_ATOMIC_OR_SADDR_RTN_vi
    UINT64_C(3706224640), UINT64_C(0),	// GLOBAL_ATOMIC_OR_SADDR_gfx10
    UINT64_C(3707109376), UINT64_C(0),	// GLOBAL_ATOMIC_OR_SADDR_gfx11
    UINT64_C(3993976832), UINT64_C(0),	// GLOBAL_ATOMIC_OR_SADDR_gfx12
    UINT64_C(3710156800), UINT64_C(0),	// GLOBAL_ATOMIC_OR_SADDR_vi
    UINT64_C(71776122779828224), UINT64_C(0),	// GLOBAL_ATOMIC_OR_X2_RTN_agpr_vi
    UINT64_C(35184375803510784), UINT64_C(0),	// GLOBAL_ATOMIC_OR_X2_RTN_gfx10
    UINT64_C(34902900822654976), UINT64_C(0),	// GLOBAL_ATOMIC_OR_X2_RTN_gfx11
    UINT64_C(4503603621560444), UINT64_C(0),	// GLOBAL_ATOMIC_OR_X2_RTN_gfx12
    UINT64_C(35747325760864256), UINT64_C(0),	// GLOBAL_ATOMIC_OR_X2_RTN_vi
    UINT64_C(36028800737574912), UINT64_C(0),	// GLOBAL_ATOMIC_OR_X2_SADDR_RTN_agpr_vi
    UINT64_C(3714678784), UINT64_C(0),	// GLOBAL_ATOMIC_OR_X2_SADDR_RTN_gfx10
    UINT64_C(3710533632), UINT64_C(0),	// GLOBAL_ATOMIC_OR_X2_SADDR_RTN_gfx11
    UINT64_C(4503603621560320), UINT64_C(0),	// GLOBAL_ATOMIC_OR_X2_SADDR_RTN_gfx12
    UINT64_C(3718610944), UINT64_C(0),	// GLOBAL_ATOMIC_OR_X2_SADDR_RTN_vi
    UINT64_C(3714613248), UINT64_C(0),	// GLOBAL_ATOMIC_OR_X2_SADDR_gfx10
    UINT64_C(3710517248), UINT64_C(0),	// GLOBAL_ATOMIC_OR_X2_SADDR_gfx11
    UINT64_C(3994189824), UINT64_C(0),	// GLOBAL_ATOMIC_OR_X2_SADDR_gfx12
    UINT64_C(3718545408), UINT64_C(0),	// GLOBAL_ATOMIC_OR_X2_SADDR_vi
    UINT64_C(35184375803445248), UINT64_C(0),	// GLOBAL_ATOMIC_OR_X2_gfx10
    UINT64_C(34902900822638592), UINT64_C(0),	// GLOBAL_ATOMIC_OR_X2_gfx11
    UINT64_C(3994189948), UINT64_C(0),	// GLOBAL_ATOMIC_OR_X2_gfx12
    UINT64_C(35747325760798720), UINT64_C(0),	// GLOBAL_ATOMIC_OR_X2_vi
    UINT64_C(35184375795056640), UINT64_C(0),	// GLOBAL_ATOMIC_OR_gfx10
    UINT64_C(34902900819230720), UINT64_C(0),	// GLOBAL_ATOMIC_OR_gfx11
    UINT64_C(3993976956), UINT64_C(0),	// GLOBAL_ATOMIC_OR_gfx12
    UINT64_C(35747325752410112), UINT64_C(0),	// GLOBAL_ATOMIC_OR_vi
    UINT64_C(71776122773798912), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_BF16_RTN_agpr_vi
    UINT64_C(4503603621822588), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_BF16_RTN_gfx12
    UINT64_C(35747325754834944), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_BF16_RTN_vi
    UINT64_C(36028800731545600), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_RTN_agpr_vi
    UINT64_C(4503603621822464), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_RTN_gfx12
    UINT64_C(3712581632), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_RTN_vi
    UINT64_C(3994451968), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_gfx12
    UINT64_C(3712516096), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_vi
    UINT64_C(3994452092), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_BF16_gfx12
    UINT64_C(35747325754769408), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_BF16_vi
    UINT64_C(71776122772750336), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_F16_RTN_agpr_vi
    UINT64_C(4503603621806204), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_F16_RTN_gfx12
    UINT64_C(35747325753786368), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_F16_RTN_gfx940
    UINT64_C(35747325753786368), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_F16_RTN_vi
    UINT64_C(36028800730497024), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN_agpr_vi
    UINT64_C(4503603621806080), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN_gfx12
    UINT64_C(3711533056), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN_gfx940
    UINT64_C(3711533056), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN_vi
    UINT64_C(3994435584), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_F16_SADDR_gfx12
    UINT64_C(3711467520), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_F16_SADDR_gfx940
    UINT64_C(3711467520), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_F16_SADDR_vi
    UINT64_C(3994435708), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_F16_gfx12
    UINT64_C(35747325753720832), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_F16_gfx940
    UINT64_C(35747325753720832), UINT64_C(0),	// GLOBAL_ATOMIC_PK_ADD_F16_vi
    UINT64_C(71776122770653184), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_RTN_agpr_vi
    UINT64_C(35184375794335744), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_RTN_gfx10
    UINT64_C(34902900818460672), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_RTN_gfx11
    UINT64_C(4503603621298300), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_RTN_gfx12
    UINT64_C(35747325751689216), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_RTN_vi
    UINT64_C(36028800728399872), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_SADDR_RTN_agpr_vi
    UINT64_C(3705503744), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_SADDR_RTN_gfx10
    UINT64_C(3706339328), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_SADDR_RTN_gfx11
    UINT64_C(4503603621298176), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_SADDR_RTN_gfx12
    UINT64_C(3709435904), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_SADDR_RTN_vi
    UINT64_C(3705438208), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_SADDR_gfx10
    UINT64_C(3706322944), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_SADDR_gfx11
    UINT64_C(3993927680), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_SADDR_gfx12
    UINT64_C(3709370368), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_SADDR_vi
    UINT64_C(71776122779041792), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_X2_RTN_agpr_vi
    UINT64_C(35184375802724352), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_X2_RTN_gfx10
    UINT64_C(34902900821868544), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_X2_RTN_gfx11
    UINT64_C(4503603621511292), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_X2_RTN_gfx12
    UINT64_C(35747325760077824), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_X2_RTN_vi
    UINT64_C(36028800736788480), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_agpr_vi
    UINT64_C(3713892352), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_gfx10
    UINT64_C(3709747200), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_gfx11
    UINT64_C(4503603621511168), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_gfx12
    UINT64_C(3717824512), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_vi
    UINT64_C(3713826816), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_X2_SADDR_gfx10
    UINT64_C(3709730816), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_X2_SADDR_gfx11
    UINT64_C(3994140672), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_X2_SADDR_gfx12
    UINT64_C(3717758976), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_X2_SADDR_vi
    UINT64_C(35184375802658816), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_X2_gfx10
    UINT64_C(34902900821852160), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_X2_gfx11
    UINT64_C(3994140796), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_X2_gfx12
    UINT64_C(35747325760012288), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_X2_vi
    UINT64_C(35184375794270208), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_gfx10
    UINT64_C(34902900818444288), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_gfx11
    UINT64_C(3993927804), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_gfx12
    UINT64_C(35747325751623680), UINT64_C(0),	// GLOBAL_ATOMIC_SMAX_vi
    UINT64_C(71776122770128896), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_RTN_agpr_vi
    UINT64_C(35184375793811456), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_RTN_gfx10
    UINT64_C(34902900817936384), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_RTN_gfx11
    UINT64_C(4503603621265532), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_RTN_gfx12
    UINT64_C(35747325751164928), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_RTN_vi
    UINT64_C(36028800727875584), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_SADDR_RTN_agpr_vi
    UINT64_C(3704979456), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_SADDR_RTN_gfx10
    UINT64_C(3705815040), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_SADDR_RTN_gfx11
    UINT64_C(4503603621265408), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_SADDR_RTN_gfx12
    UINT64_C(3708911616), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_SADDR_RTN_vi
    UINT64_C(3704913920), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_SADDR_gfx10
    UINT64_C(3705798656), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_SADDR_gfx11
    UINT64_C(3993894912), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_SADDR_gfx12
    UINT64_C(3708846080), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_SADDR_vi
    UINT64_C(71776122778517504), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_X2_RTN_agpr_vi
    UINT64_C(35184375802200064), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_X2_RTN_gfx10
    UINT64_C(34902900821344256), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_X2_RTN_gfx11
    UINT64_C(4503603621478524), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_X2_RTN_gfx12
    UINT64_C(35747325759553536), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_X2_RTN_vi
    UINT64_C(36028800736264192), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_agpr_vi
    UINT64_C(3713368064), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_gfx10
    UINT64_C(3709222912), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_gfx11
    UINT64_C(4503603621478400), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_gfx12
    UINT64_C(3717300224), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_vi
    UINT64_C(3713302528), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_X2_SADDR_gfx10
    UINT64_C(3709206528), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_X2_SADDR_gfx11
    UINT64_C(3994107904), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_X2_SADDR_gfx12
    UINT64_C(3717234688), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_X2_SADDR_vi
    UINT64_C(35184375802134528), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_X2_gfx10
    UINT64_C(34902900821327872), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_X2_gfx11
    UINT64_C(3994108028), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_X2_gfx12
    UINT64_C(35747325759488000), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_X2_vi
    UINT64_C(35184375793745920), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_gfx10
    UINT64_C(34902900817920000), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_gfx11
    UINT64_C(3993895036), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_gfx12
    UINT64_C(35747325751099392), UINT64_C(0),	// GLOBAL_ATOMIC_SMIN_vi
    UINT64_C(71776122769866752), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_RTN_agpr_vi
    UINT64_C(35184375793287168), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_RTN_gfx10
    UINT64_C(34902900817412096), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_RTN_gfx11
    UINT64_C(4503603621232764), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_RTN_gfx12
    UINT64_C(35747325750902784), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_RTN_vi
    UINT64_C(36028800727613440), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_SADDR_RTN_agpr_vi
    UINT64_C(3704455168), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_SADDR_RTN_gfx10
    UINT64_C(3705290752), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_SADDR_RTN_gfx11
    UINT64_C(4503603621232640), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_SADDR_RTN_gfx12
    UINT64_C(3708649472), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_SADDR_RTN_vi
    UINT64_C(3704389632), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_SADDR_gfx10
    UINT64_C(3705274368), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_SADDR_gfx11
    UINT64_C(3993862144), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_SADDR_gfx12
    UINT64_C(3708583936), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_SADDR_vi
    UINT64_C(71776122778255360), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_X2_RTN_agpr_vi
    UINT64_C(35184375801675776), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_X2_RTN_gfx10
    UINT64_C(34902900821082112), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_X2_RTN_gfx11
    UINT64_C(4503603621462140), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_X2_RTN_gfx12
    UINT64_C(35747325759291392), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_X2_RTN_vi
    UINT64_C(36028800736002048), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_agpr_vi
    UINT64_C(3712843776), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_gfx10
    UINT64_C(3708960768), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_gfx11
    UINT64_C(4503603621462016), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_gfx12
    UINT64_C(3717038080), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_vi
    UINT64_C(3712778240), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_X2_SADDR_gfx10
    UINT64_C(3708944384), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_X2_SADDR_gfx11
    UINT64_C(3994091520), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_X2_SADDR_gfx12
    UINT64_C(3716972544), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_X2_SADDR_vi
    UINT64_C(35184375801610240), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_X2_gfx10
    UINT64_C(34902900821065728), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_X2_gfx11
    UINT64_C(3994091644), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_X2_gfx12
    UINT64_C(35747325759225856), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_X2_vi
    UINT64_C(35184375793221632), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_gfx10
    UINT64_C(34902900817395712), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_gfx11
    UINT64_C(3993862268), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_gfx12
    UINT64_C(35747325750837248), UINT64_C(0),	// GLOBAL_ATOMIC_SUB_vi
    UINT64_C(71776122769080320), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_RTN_agpr_vi
    UINT64_C(35184375792500736), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_RTN_gfx10
    UINT64_C(34902900816625664), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_RTN_gfx11
    UINT64_C(4503603621183612), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_RTN_gfx12
    UINT64_C(35747325750116352), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_RTN_vi
    UINT64_C(36028800726827008), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_SADDR_RTN_agpr_vi
    UINT64_C(3703668736), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_SADDR_RTN_gfx10
    UINT64_C(3704504320), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_SADDR_RTN_gfx11
    UINT64_C(4503603621183488), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_SADDR_RTN_gfx12
    UINT64_C(3707863040), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_SADDR_RTN_vi
    UINT64_C(3703603200), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_SADDR_gfx10
    UINT64_C(3704487936), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_SADDR_gfx11
    UINT64_C(3993812992), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_SADDR_gfx12
    UINT64_C(3707797504), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_SADDR_vi
    UINT64_C(71776122777468928), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_X2_RTN_agpr_vi
    UINT64_C(35184375800889344), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_X2_RTN_gfx10
    UINT64_C(34902900820295680), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_X2_RTN_gfx11
    UINT64_C(4503603621412988), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_X2_RTN_gfx12
    UINT64_C(35747325758504960), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_X2_RTN_vi
    UINT64_C(36028800735215616), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_agpr_vi
    UINT64_C(3712057344), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_gfx10
    UINT64_C(3708174336), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_gfx11
    UINT64_C(4503603621412864), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_gfx12
    UINT64_C(3716251648), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_vi
    UINT64_C(3711991808), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_X2_SADDR_gfx10
    UINT64_C(3708157952), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_X2_SADDR_gfx11
    UINT64_C(3994042368), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_X2_SADDR_gfx12
    UINT64_C(3716186112), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_X2_SADDR_vi
    UINT64_C(35184375800823808), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_X2_gfx10
    UINT64_C(34902900820279296), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_X2_gfx11
    UINT64_C(3994042492), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_X2_gfx12
    UINT64_C(35747325758439424), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_X2_vi
    UINT64_C(35184375792435200), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_gfx10
    UINT64_C(34902900816609280), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_gfx11
    UINT64_C(3993813116), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_gfx12
    UINT64_C(35747325750050816), UINT64_C(0),	// GLOBAL_ATOMIC_SWAP_vi
    UINT64_C(71776122770915328), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_RTN_agpr_vi
    UINT64_C(35184375794597888), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_RTN_gfx10
    UINT64_C(34902900818722816), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_RTN_gfx11
    UINT64_C(4503603621314684), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_RTN_gfx12
    UINT64_C(35747325751951360), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_RTN_vi
    UINT64_C(36028800728662016), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_SADDR_RTN_agpr_vi
    UINT64_C(3705765888), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_SADDR_RTN_gfx10
    UINT64_C(3706601472), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_SADDR_RTN_gfx11
    UINT64_C(4503603621314560), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_SADDR_RTN_gfx12
    UINT64_C(3709698048), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_SADDR_RTN_vi
    UINT64_C(3705700352), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_SADDR_gfx10
    UINT64_C(3706585088), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_SADDR_gfx11
    UINT64_C(3993944064), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_SADDR_gfx12
    UINT64_C(3709632512), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_SADDR_vi
    UINT64_C(71776122779303936), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_X2_RTN_agpr_vi
    UINT64_C(35184375802986496), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_X2_RTN_gfx10
    UINT64_C(34902900822130688), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_X2_RTN_gfx11
    UINT64_C(4503603621527676), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_X2_RTN_gfx12
    UINT64_C(35747325760339968), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_X2_RTN_vi
    UINT64_C(36028800737050624), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_agpr_vi
    UINT64_C(3714154496), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_gfx10
    UINT64_C(3710009344), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_gfx11
    UINT64_C(4503603621527552), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_gfx12
    UINT64_C(3718086656), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_vi
    UINT64_C(3714088960), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_X2_SADDR_gfx10
    UINT64_C(3709992960), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_X2_SADDR_gfx11
    UINT64_C(3994157056), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_X2_SADDR_gfx12
    UINT64_C(3718021120), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_X2_SADDR_vi
    UINT64_C(35184375802920960), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_X2_gfx10
    UINT64_C(34902900822114304), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_X2_gfx11
    UINT64_C(3994157180), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_X2_gfx12
    UINT64_C(35747325760274432), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_X2_vi
    UINT64_C(35184375794532352), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_gfx10
    UINT64_C(34902900818706432), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_gfx11
    UINT64_C(3993944188), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_gfx12
    UINT64_C(35747325751885824), UINT64_C(0),	// GLOBAL_ATOMIC_UMAX_vi
    UINT64_C(71776122770391040), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_RTN_agpr_vi
    UINT64_C(35184375794073600), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_RTN_gfx10
    UINT64_C(34902900818198528), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_RTN_gfx11
    UINT64_C(4503603621281916), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_RTN_gfx12
    UINT64_C(35747325751427072), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_RTN_vi
    UINT64_C(36028800728137728), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_SADDR_RTN_agpr_vi
    UINT64_C(3705241600), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_SADDR_RTN_gfx10
    UINT64_C(3706077184), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_SADDR_RTN_gfx11
    UINT64_C(4503603621281792), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_SADDR_RTN_gfx12
    UINT64_C(3709173760), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_SADDR_RTN_vi
    UINT64_C(3705176064), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_SADDR_gfx10
    UINT64_C(3706060800), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_SADDR_gfx11
    UINT64_C(3993911296), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_SADDR_gfx12
    UINT64_C(3709108224), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_SADDR_vi
    UINT64_C(71776122778779648), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_X2_RTN_agpr_vi
    UINT64_C(35184375802462208), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_X2_RTN_gfx10
    UINT64_C(34902900821606400), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_X2_RTN_gfx11
    UINT64_C(4503603621494908), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_X2_RTN_gfx12
    UINT64_C(35747325759815680), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_X2_RTN_vi
    UINT64_C(36028800736526336), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_agpr_vi
    UINT64_C(3713630208), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_gfx10
    UINT64_C(3709485056), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_gfx11
    UINT64_C(4503603621494784), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_gfx12
    UINT64_C(3717562368), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_vi
    UINT64_C(3713564672), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_X2_SADDR_gfx10
    UINT64_C(3709468672), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_X2_SADDR_gfx11
    UINT64_C(3994124288), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_X2_SADDR_gfx12
    UINT64_C(3717496832), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_X2_SADDR_vi
    UINT64_C(35184375802396672), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_X2_gfx10
    UINT64_C(34902900821590016), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_X2_gfx11
    UINT64_C(3994124412), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_X2_gfx12
    UINT64_C(35747325759750144), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_X2_vi
    UINT64_C(35184375794008064), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_gfx10
    UINT64_C(34902900818182144), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_gfx11
    UINT64_C(3993911420), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_gfx12
    UINT64_C(35747325751361536), UINT64_C(0),	// GLOBAL_ATOMIC_UMIN_vi
    UINT64_C(71776122771701760), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_RTN_agpr_vi
    UINT64_C(35184375795384320), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_RTN_gfx10
    UINT64_C(34902900819509248), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_RTN_gfx11
    UINT64_C(4503603621363836), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_RTN_gfx12
    UINT64_C(35747325752737792), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_RTN_vi
    UINT64_C(36028800729448448), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_SADDR_RTN_agpr_vi
    UINT64_C(3706552320), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_SADDR_RTN_gfx10
    UINT64_C(3707387904), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_SADDR_RTN_gfx11
    UINT64_C(4503603621363712), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_SADDR_RTN_gfx12
    UINT64_C(3710484480), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_SADDR_RTN_vi
    UINT64_C(3706486784), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_SADDR_gfx10
    UINT64_C(3707371520), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_SADDR_gfx11
    UINT64_C(3993993216), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_SADDR_gfx12
    UINT64_C(3710418944), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_SADDR_vi
    UINT64_C(71776122780090368), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_X2_RTN_agpr_vi
    UINT64_C(35184375803772928), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_X2_RTN_gfx10
    UINT64_C(34902900822917120), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_X2_RTN_gfx11
    UINT64_C(4503603621576828), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_X2_RTN_gfx12
    UINT64_C(35747325761126400), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_X2_RTN_vi
    UINT64_C(36028800737837056), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_agpr_vi
    UINT64_C(3714940928), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_gfx10
    UINT64_C(3710795776), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_gfx11
    UINT64_C(4503603621576704), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_gfx12
    UINT64_C(3718873088), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_vi
    UINT64_C(3714875392), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_X2_SADDR_gfx10
    UINT64_C(3710779392), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_X2_SADDR_gfx11
    UINT64_C(3994206208), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_X2_SADDR_gfx12
    UINT64_C(3718807552), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_X2_SADDR_vi
    UINT64_C(35184375803707392), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_X2_gfx10
    UINT64_C(34902900822900736), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_X2_gfx11
    UINT64_C(3994206332), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_X2_gfx12
    UINT64_C(35747325761060864), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_X2_vi
    UINT64_C(35184375795318784), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_gfx10
    UINT64_C(34902900819492864), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_gfx11
    UINT64_C(3993993340), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_gfx12
    UINT64_C(35747325752672256), UINT64_C(0),	// GLOBAL_ATOMIC_XOR_vi
    UINT64_C(3993682044), UINT64_C(0),	// GLOBAL_INV_gfx12
    UINT64_C(3994583040), UINT64_C(0),	// GLOBAL_LOAD_ASYNC_TO_LDS_B128_SADDR_gfx1250
    UINT64_C(3994583164), UINT64_C(0),	// GLOBAL_LOAD_ASYNC_TO_LDS_B128_gfx1250
    UINT64_C(3994550272), UINT64_C(0),	// GLOBAL_LOAD_ASYNC_TO_LDS_B32_SADDR_gfx1250
    UINT64_C(3994550396), UINT64_C(0),	// GLOBAL_LOAD_ASYNC_TO_LDS_B32_gfx1250
    UINT64_C(3994566656), UINT64_C(0),	// GLOBAL_LOAD_ASYNC_TO_LDS_B64_SADDR_gfx1250
    UINT64_C(3994566780), UINT64_C(0),	// GLOBAL_LOAD_ASYNC_TO_LDS_B64_gfx1250
    UINT64_C(3994533888), UINT64_C(0),	// GLOBAL_LOAD_ASYNC_TO_LDS_B8_SADDR_gfx1250
    UINT64_C(3994534012), UINT64_C(0),	// GLOBAL_LOAD_ASYNC_TO_LDS_B8_gfx1250
    UINT64_C(3994337280), UINT64_C(0),	// GLOBAL_LOAD_BLOCK_SADDR_gfx12
    UINT64_C(3994337404), UINT64_C(0),	// GLOBAL_LOAD_BLOCK_gfx12
    UINT64_C(3694428160), UINT64_C(0),	// GLOBAL_LOAD_DWORDX2_SADDR_gfx10
    UINT64_C(3696623616), UINT64_C(0),	// GLOBAL_LOAD_DWORDX2_SADDR_gfx11
    UINT64_C(3993321472), UINT64_C(0),	// GLOBAL_LOAD_DWORDX2_SADDR_gfx12
    UINT64_C(3696525312), UINT64_C(0),	// GLOBAL_LOAD_DWORDX2_SADDR_vi
    UINT64_C(35184375783260160), UINT64_C(0),	// GLOBAL_LOAD_DWORDX2_gfx10
    UINT64_C(34902900808744960), UINT64_C(0),	// GLOBAL_LOAD_DWORDX2_gfx11
    UINT64_C(3993321596), UINT64_C(0),	// GLOBAL_LOAD_DWORDX2_gfx12
    UINT64_C(35747325738778624), UINT64_C(0),	// GLOBAL_LOAD_DWORDX2_vi
    UINT64_C(3694952448), UINT64_C(0),	// GLOBAL_LOAD_DWORDX3_SADDR_gfx10
    UINT64_C(3696885760), UINT64_C(0),	// GLOBAL_LOAD_DWORDX3_SADDR_gfx11
    UINT64_C(3993337856), UINT64_C(0),	// GLOBAL_LOAD_DWORDX3_SADDR_gfx12
    UINT64_C(3696787456), UINT64_C(0),	// GLOBAL_LOAD_DWORDX3_SADDR_vi
    UINT64_C(35184375783784448), UINT64_C(0),	// GLOBAL_LOAD_DWORDX3_gfx10
    UINT64_C(34902900809007104), UINT64_C(0),	// GLOBAL_LOAD_DWORDX3_gfx11
    UINT64_C(3993337980), UINT64_C(0),	// GLOBAL_LOAD_DWORDX3_gfx12
    UINT64_C(35747325739040768), UINT64_C(0),	// GLOBAL_LOAD_DWORDX3_vi
    UINT64_C(3694690304), UINT64_C(0),	// GLOBAL_LOAD_DWORDX4_SADDR_gfx10
    UINT64_C(3697147904), UINT64_C(0),	// GLOBAL_LOAD_DWORDX4_SADDR_gfx11
    UINT64_C(3993354240), UINT64_C(0),	// GLOBAL_LOAD_DWORDX4_SADDR_gfx12
    UINT64_C(3697049600), UINT64_C(0),	// GLOBAL_LOAD_DWORDX4_SADDR_vi
    UINT64_C(35184375783522304), UINT64_C(0),	// GLOBAL_LOAD_DWORDX4_gfx10
    UINT64_C(34902900809269248), UINT64_C(0),	// GLOBAL_LOAD_DWORDX4_gfx11
    UINT64_C(3993354364), UINT64_C(0),	// GLOBAL_LOAD_DWORDX4_gfx12
    UINT64_C(35747325739302912), UINT64_C(0),	// GLOBAL_LOAD_DWORDX4_vi
    UINT64_C(3696787456), UINT64_C(0),	// GLOBAL_LOAD_DWORD_ADDTID_SADDR_gfx10
    UINT64_C(3701604352), UINT64_C(0),	// GLOBAL_LOAD_DWORD_ADDTID_SADDR_gfx11
    UINT64_C(3993632768), UINT64_C(0),	// GLOBAL_LOAD_DWORD_ADDTID_SADDR_gfx12
    UINT64_C(35184375785619456), UINT64_C(0),	// GLOBAL_LOAD_DWORD_ADDTID_gfx10
    UINT64_C(34902900813725696), UINT64_C(0),	// GLOBAL_LOAD_DWORD_ADDTID_gfx11
    UINT64_C(3993632892), UINT64_C(0),	// GLOBAL_LOAD_DWORD_ADDTID_gfx12
    UINT64_C(3694166016), UINT64_C(0),	// GLOBAL_LOAD_DWORD_SADDR_gfx10
    UINT64_C(3696361472), UINT64_C(0),	// GLOBAL_LOAD_DWORD_SADDR_gfx11
    UINT64_C(3993305088), UINT64_C(0),	// GLOBAL_LOAD_DWORD_SADDR_gfx12
    UINT64_C(3696263168), UINT64_C(0),	// GLOBAL_LOAD_DWORD_SADDR_vi
    UINT64_C(35184375782998016), UINT64_C(0),	// GLOBAL_LOAD_DWORD_gfx10
    UINT64_C(34902900808482816), UINT64_C(0),	// GLOBAL_LOAD_DWORD_gfx11
    UINT64_C(3993305212), UINT64_C(0),	// GLOBAL_LOAD_DWORD_gfx12
    UINT64_C(35747325738516480), UINT64_C(0),	// GLOBAL_LOAD_DWORD_vi
    UINT64_C(3724050432), UINT64_C(0),	// GLOBAL_LOAD_LDS_DWORDX3_SADDR_gfx940
    UINT64_C(3724058624), UINT64_C(0),	// GLOBAL_LOAD_LDS_DWORDX3_SADDR_vi
    UINT64_C(35747325766303744), UINT64_C(0),	// GLOBAL_LOAD_LDS_DWORDX3_gfx940
    UINT64_C(35747325766311936), UINT64_C(0),	// GLOBAL_LOAD_LDS_DWORDX3_vi
    UINT64_C(3723788288), UINT64_C(0),	// GLOBAL_LOAD_LDS_DWORDX4_SADDR_gfx940
    UINT64_C(3723796480), UINT64_C(0),	// GLOBAL_LOAD_LDS_DWORDX4_SADDR_vi
    UINT64_C(35747325766041600), UINT64_C(0),	// GLOBAL_LOAD_LDS_DWORDX4_gfx940
    UINT64_C(35747325766049792), UINT64_C(0),	// GLOBAL_LOAD_LDS_DWORDX4_vi
    UINT64_C(3694174208), UINT64_C(0),	// GLOBAL_LOAD_LDS_DWORD_SADDR_gfx10
    UINT64_C(3702030336), UINT64_C(0),	// GLOBAL_LOAD_LDS_DWORD_SADDR_gfx940
    UINT64_C(3696271360), UINT64_C(0),	// GLOBAL_LOAD_LDS_DWORD_SADDR_vi
    UINT64_C(35184375783006208), UINT64_C(0),	// GLOBAL_LOAD_LDS_DWORD_gfx10
    UINT64_C(35747325744283648), UINT64_C(0),	// GLOBAL_LOAD_LDS_DWORD_gfx940
    UINT64_C(35747325738524672), UINT64_C(0),	// GLOBAL_LOAD_LDS_DWORD_vi
    UINT64_C(3693387776), UINT64_C(0),	// GLOBAL_LOAD_LDS_SBYTE_SADDR_gfx10
    UINT64_C(3701243904), UINT64_C(0),	// GLOBAL_LOAD_LDS_SBYTE_SADDR_gfx940
    UINT64_C(3695484928), UINT64_C(0),	// GLOBAL_LOAD_LDS_SBYTE_SADDR_vi
    UINT64_C(35184375782219776), UINT64_C(0),	// GLOBAL_LOAD_LDS_SBYTE_gfx10
    UINT64_C(35747325743497216), UINT64_C(0),	// GLOBAL_LOAD_LDS_SBYTE_gfx940
    UINT64_C(35747325737738240), UINT64_C(0),	// GLOBAL_LOAD_LDS_SBYTE_vi
    UINT64_C(3693912064), UINT64_C(0),	// GLOBAL_LOAD_LDS_SSHORT_SADDR_gfx10
    UINT64_C(3701768192), UINT64_C(0),	// GLOBAL_LOAD_LDS_SSHORT_SADDR_gfx940
    UINT64_C(3696009216), UINT64_C(0),	// GLOBAL_LOAD_LDS_SSHORT_SADDR_vi
    UINT64_C(35184375782744064), UINT64_C(0),	// GLOBAL_LOAD_LDS_SSHORT_gfx10
    UINT64_C(35747325744021504), UINT64_C(0),	// GLOBAL_LOAD_LDS_SSHORT_gfx940
    UINT64_C(35747325738262528), UINT64_C(0),	// GLOBAL_LOAD_LDS_SSHORT_vi
    UINT64_C(3693125632), UINT64_C(0),	// GLOBAL_LOAD_LDS_UBYTE_SADDR_gfx10
    UINT64_C(3700981760), UINT64_C(0),	// GLOBAL_LOAD_LDS_UBYTE_SADDR_gfx940
    UINT64_C(3695222784), UINT64_C(0),	// GLOBAL_LOAD_LDS_UBYTE_SADDR_vi
    UINT64_C(35184375781957632), UINT64_C(0),	// GLOBAL_LOAD_LDS_UBYTE_gfx10
    UINT64_C(35747325743235072), UINT64_C(0),	// GLOBAL_LOAD_LDS_UBYTE_gfx940
    UINT64_C(35747325737476096), UINT64_C(0),	// GLOBAL_LOAD_LDS_UBYTE_vi
    UINT64_C(3693649920), UINT64_C(0),	// GLOBAL_LOAD_LDS_USHORT_SADDR_gfx10
    UINT64_C(3701506048), UINT64_C(0),	// GLOBAL_LOAD_LDS_USHORT_SADDR_gfx940
    UINT64_C(3695747072), UINT64_C(0),	// GLOBAL_LOAD_LDS_USHORT_SADDR_vi
    UINT64_C(35184375782481920), UINT64_C(0),	// GLOBAL_LOAD_LDS_USHORT_gfx10
    UINT64_C(35747325743759360), UINT64_C(0),	// GLOBAL_LOAD_LDS_USHORT_gfx940
    UINT64_C(35747325738000384), UINT64_C(0),	// GLOBAL_LOAD_LDS_USHORT_vi
    UINT64_C(3994845184), UINT64_C(0),	// GLOBAL_LOAD_MONITOR_B128_SADDR_gfx1250
    UINT64_C(3994845308), UINT64_C(0),	// GLOBAL_LOAD_MONITOR_B128_gfx1250
    UINT64_C(3994812416), UINT64_C(0),	// GLOBAL_LOAD_MONITOR_B32_SADDR_gfx1250
    UINT64_C(3994812540), UINT64_C(0),	// GLOBAL_LOAD_MONITOR_B32_gfx1250
    UINT64_C(3994828800), UINT64_C(0),	// GLOBAL_LOAD_MONITOR_B64_SADDR_gfx1250
    UINT64_C(3994828924), UINT64_C(0),	// GLOBAL_LOAD_MONITOR_B64_gfx1250
    UINT64_C(3700195328), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_D16_HI_SADDR_gfx10
    UINT64_C(3700031488), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_D16_HI_SADDR_gfx11
    UINT64_C(3993534464), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_D16_HI_SADDR_gfx12
    UINT64_C(3700195328), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_D16_HI_SADDR_vi
    UINT64_C(35184375789027328), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_D16_HI_gfx10
    UINT64_C(34902900812152832), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_D16_HI_gfx11
    UINT64_C(3993534588), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_D16_HI_gfx12
    UINT64_C(35747325742448640), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_D16_HI_vi
    UINT64_C(3699933184), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_D16_SADDR_gfx10
    UINT64_C(3699245056), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_D16_SADDR_gfx11
    UINT64_C(3993485312), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_D16_SADDR_gfx12
    UINT64_C(3699933184), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_D16_SADDR_vi
    UINT64_C(35184375788765184), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_D16_gfx10
    UINT64_C(34902900811366400), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_D16_gfx11
    UINT64_C(3993485436), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_D16_gfx12
    UINT64_C(35747325742186496), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_D16_vi
    UINT64_C(3693379584), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_SADDR_gfx10
    UINT64_C(3695575040), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_SADDR_gfx11
    UINT64_C(3993255936), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_SADDR_gfx12
    UINT64_C(3695476736), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_SADDR_vi
    UINT64_C(35184375782211584), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_gfx10
    UINT64_C(34902900807696384), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_gfx11
    UINT64_C(3993256060), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_gfx12
    UINT64_C(35747325737730048), UINT64_C(0),	// GLOBAL_LOAD_SBYTE_vi
    UINT64_C(3700719616), UINT64_C(0),	// GLOBAL_LOAD_SHORT_D16_HI_SADDR_gfx10
    UINT64_C(3700293632), UINT64_C(0),	// GLOBAL_LOAD_SHORT_D16_HI_SADDR_gfx11
    UINT64_C(3993550848), UINT64_C(0),	// GLOBAL_LOAD_SHORT_D16_HI_SADDR_gfx12
    UINT64_C(3700719616), UINT64_C(0),	// GLOBAL_LOAD_SHORT_D16_HI_SADDR_vi
    UINT64_C(35184375789551616), UINT64_C(0),	// GLOBAL_LOAD_SHORT_D16_HI_gfx10
    UINT64_C(34902900812414976), UINT64_C(0),	// GLOBAL_LOAD_SHORT_D16_HI_gfx11
    UINT64_C(3993550972), UINT64_C(0),	// GLOBAL_LOAD_SHORT_D16_HI_gfx12
    UINT64_C(35747325742972928), UINT64_C(0),	// GLOBAL_LOAD_SHORT_D16_HI_vi
    UINT64_C(3700457472), UINT64_C(0),	// GLOBAL_LOAD_SHORT_D16_SADDR_gfx10
    UINT64_C(3699507200), UINT64_C(0),	// GLOBAL_LOAD_SHORT_D16_SADDR_gfx11
    UINT64_C(3993501696), UINT64_C(0),	// GLOBAL_LOAD_SHORT_D16_SADDR_gfx12
    UINT64_C(3700457472), UINT64_C(0),	// GLOBAL_LOAD_SHORT_D16_SADDR_vi
    UINT64_C(35184375789289472), UINT64_C(0),	// GLOBAL_LOAD_SHORT_D16_gfx10
    UINT64_C(34902900811628544), UINT64_C(0),	// GLOBAL_LOAD_SHORT_D16_gfx11
    UINT64_C(3993501820), UINT64_C(0),	// GLOBAL_LOAD_SHORT_D16_gfx12
    UINT64_C(35747325742710784), UINT64_C(0),	// GLOBAL_LOAD_SHORT_D16_vi
    UINT64_C(3693903872), UINT64_C(0),	// GLOBAL_LOAD_SSHORT_SADDR_gfx10
    UINT64_C(3696099328), UINT64_C(0),	// GLOBAL_LOAD_SSHORT_SADDR_gfx11
    UINT64_C(3993288704), UINT64_C(0),	// GLOBAL_LOAD_SSHORT_SADDR_gfx12
    UINT64_C(3696001024), UINT64_C(0),	// GLOBAL_LOAD_SSHORT_SADDR_vi
    UINT64_C(35184375782735872), UINT64_C(0),	// GLOBAL_LOAD_SSHORT_gfx10
    UINT64_C(34902900808220672), UINT64_C(0),	// GLOBAL_LOAD_SSHORT_gfx11
    UINT64_C(3993288828), UINT64_C(0),	// GLOBAL_LOAD_SSHORT_gfx12
    UINT64_C(35747325738254336), UINT64_C(0),	// GLOBAL_LOAD_SSHORT_vi
    UINT64_C(3994861568), UINT64_C(0),	// GLOBAL_LOAD_TR4_B64_SADDR_gfx1250
    UINT64_C(3994861692), UINT64_C(0),	// GLOBAL_LOAD_TR4_B64_gfx1250
    UINT64_C(3994877952), UINT64_C(0),	// GLOBAL_LOAD_TR6_B96_SADDR_gfx1250
    UINT64_C(3994878076), UINT64_C(0),	// GLOBAL_LOAD_TR6_B96_gfx1250
    UINT64_C(3994402816), UINT64_C(0),	// GLOBAL_LOAD_TR_B128_w32_SADDR_gfx12
    UINT64_C(3994402816), UINT64_C(0),	// GLOBAL_LOAD_TR_B128_w32_SADDR_gfx1250
    UINT64_C(3994402940), UINT64_C(0),	// GLOBAL_LOAD_TR_B128_w32_gfx12
    UINT64_C(3994402940), UINT64_C(0),	// GLOBAL_LOAD_TR_B128_w32_gfx1250
    UINT64_C(3994402816), UINT64_C(0),	// GLOBAL_LOAD_TR_B128_w64_SADDR_gfx12
    UINT64_C(3994402940), UINT64_C(0),	// GLOBAL_LOAD_TR_B128_w64_gfx12
    UINT64_C(3994419200), UINT64_C(0),	// GLOBAL_LOAD_TR_B64_w32_SADDR_gfx12
    UINT64_C(3994419200), UINT64_C(0),	// GLOBAL_LOAD_TR_B64_w32_SADDR_gfx1250
    UINT64_C(3994419324), UINT64_C(0),	// GLOBAL_LOAD_TR_B64_w32_gfx12
    UINT64_C(3994419324), UINT64_C(0),	// GLOBAL_LOAD_TR_B64_w32_gfx1250
    UINT64_C(3994419200), UINT64_C(0),	// GLOBAL_LOAD_TR_B64_w64_SADDR_gfx12
    UINT64_C(3994419324), UINT64_C(0),	// GLOBAL_LOAD_TR_B64_w64_gfx12
    UINT64_C(3699671040), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_D16_HI_SADDR_gfx10
    UINT64_C(3699769344), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_D16_HI_SADDR_gfx11
    UINT64_C(3993518080), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_D16_HI_SADDR_gfx12
    UINT64_C(3699671040), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_D16_HI_SADDR_vi
    UINT64_C(35184375788503040), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_D16_HI_gfx10
    UINT64_C(34902900811890688), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_D16_HI_gfx11
    UINT64_C(3993518204), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_D16_HI_gfx12
    UINT64_C(35747325741924352), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_D16_HI_vi
    UINT64_C(3699408896), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_D16_SADDR_gfx10
    UINT64_C(3698982912), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_D16_SADDR_gfx11
    UINT64_C(3993468928), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_D16_SADDR_gfx12
    UINT64_C(3699408896), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_D16_SADDR_vi
    UINT64_C(35184375788240896), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_D16_gfx10
    UINT64_C(34902900811104256), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_D16_gfx11
    UINT64_C(3993469052), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_D16_gfx12
    UINT64_C(35747325741662208), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_D16_vi
    UINT64_C(3693117440), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_SADDR_gfx10
    UINT64_C(3695312896), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_SADDR_gfx11
    UINT64_C(3993239552), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_SADDR_gfx12
    UINT64_C(3695214592), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_SADDR_vi
    UINT64_C(35184375781949440), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_gfx10
    UINT64_C(34902900807434240), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_gfx11
    UINT64_C(3993239676), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_gfx12
    UINT64_C(35747325737467904), UINT64_C(0),	// GLOBAL_LOAD_UBYTE_vi
    UINT64_C(3693641728), UINT64_C(0),	// GLOBAL_LOAD_USHORT_SADDR_gfx10
    UINT64_C(3695837184), UINT64_C(0),	// GLOBAL_LOAD_USHORT_SADDR_gfx11
    UINT64_C(3993272320), UINT64_C(0),	// GLOBAL_LOAD_USHORT_SADDR_gfx12
    UINT64_C(3695738880), UINT64_C(0),	// GLOBAL_LOAD_USHORT_SADDR_vi
    UINT64_C(35184375782473728), UINT64_C(0),	// GLOBAL_LOAD_USHORT_gfx10
    UINT64_C(34902900807958528), UINT64_C(0),	// GLOBAL_LOAD_USHORT_gfx11
    UINT64_C(3993272444), UINT64_C(0),	// GLOBAL_LOAD_USHORT_gfx12
    UINT64_C(35747325737992192), UINT64_C(0),	// GLOBAL_LOAD_USHORT_vi
    UINT64_C(3994501120), UINT64_C(0),	// GLOBAL_PREFETCH_B8_SADDR_gfx1250
    UINT64_C(3994501244), UINT64_C(0),	// GLOBAL_PREFETCH_B8_gfx1250
    UINT64_C(3994648576), UINT64_C(0),	// GLOBAL_STORE_ASYNC_FROM_LDS_B128_SADDR_gfx1250
    UINT64_C(3994648700), UINT64_C(0),	// GLOBAL_STORE_ASYNC_FROM_LDS_B128_gfx1250
    UINT64_C(3994615808), UINT64_C(0),	// GLOBAL_STORE_ASYNC_FROM_LDS_B32_SADDR_gfx1250
    UINT64_C(3994615932), UINT64_C(0),	// GLOBAL_STORE_ASYNC_FROM_LDS_B32_gfx1250
    UINT64_C(3994632192), UINT64_C(0),	// GLOBAL_STORE_ASYNC_FROM_LDS_B64_SADDR_gfx1250
    UINT64_C(3994632316), UINT64_C(0),	// GLOBAL_STORE_ASYNC_FROM_LDS_B64_gfx1250
    UINT64_C(3994599424), UINT64_C(0),	// GLOBAL_STORE_ASYNC_FROM_LDS_B8_SADDR_gfx1250
    UINT64_C(3994599548), UINT64_C(0),	// GLOBAL_STORE_ASYNC_FROM_LDS_B8_gfx1250
    UINT64_C(3994353664), UINT64_C(0),	// GLOBAL_STORE_BLOCK_SADDR_gfx12
    UINT64_C(3994353788), UINT64_C(0),	// GLOBAL_STORE_BLOCK_gfx12
    UINT64_C(3697573888), UINT64_C(0),	// GLOBAL_STORE_BYTE_D16_HI_SADDR_gfx10
    UINT64_C(3700555776), UINT64_C(0),	// GLOBAL_STORE_BYTE_D16_HI_SADDR_gfx11
    UINT64_C(3993567232), UINT64_C(0),	// GLOBAL_STORE_BYTE_D16_HI_SADDR_gfx12
    UINT64_C(3697573888), UINT64_C(0),	// GLOBAL_STORE_BYTE_D16_HI_SADDR_vi
    UINT64_C(35184375786405888), UINT64_C(0),	// GLOBAL_STORE_BYTE_D16_HI_gfx10
    UINT64_C(34902900812677120), UINT64_C(0),	// GLOBAL_STORE_BYTE_D16_HI_gfx11
    UINT64_C(3993567356), UINT64_C(0),	// GLOBAL_STORE_BYTE_D16_HI_gfx12
    UINT64_C(35747325739827200), UINT64_C(0),	// GLOBAL_STORE_BYTE_D16_HI_vi
    UINT64_C(3697311744), UINT64_C(0),	// GLOBAL_STORE_BYTE_SADDR_gfx10
    UINT64_C(3697410048), UINT64_C(0),	// GLOBAL_STORE_BYTE_SADDR_gfx11
    UINT64_C(3993370624), UINT64_C(0),	// GLOBAL_STORE_BYTE_SADDR_gfx12
    UINT64_C(3697311744), UINT64_C(0),	// GLOBAL_STORE_BYTE_SADDR_vi
    UINT64_C(35184375786143744), UINT64_C(0),	// GLOBAL_STORE_BYTE_gfx10
    UINT64_C(34902900809531392), UINT64_C(0),	// GLOBAL_STORE_BYTE_gfx11
    UINT64_C(3993370748), UINT64_C(0),	// GLOBAL_STORE_BYTE_gfx12
    UINT64_C(35747325739565056), UINT64_C(0),	// GLOBAL_STORE_BYTE_vi
    UINT64_C(3698622464), UINT64_C(0),	// GLOBAL_STORE_DWORDX2_SADDR_gfx10
    UINT64_C(3698196480), UINT64_C(0),	// GLOBAL_STORE_DWORDX2_SADDR_gfx11
    UINT64_C(3993419776), UINT64_C(0),	// GLOBAL_STORE_DWORDX2_SADDR_gfx12
    UINT64_C(3698622464), UINT64_C(0),	// GLOBAL_STORE_DWORDX2_SADDR_vi
    UINT64_C(35184375787454464), UINT64_C(0),	// GLOBAL_STORE_DWORDX2_gfx10
    UINT64_C(34902900810317824), UINT64_C(0),	// GLOBAL_STORE_DWORDX2_gfx11
    UINT64_C(3993419900), UINT64_C(0),	// GLOBAL_STORE_DWORDX2_gfx12
    UINT64_C(35747325740875776), UINT64_C(0),	// GLOBAL_STORE_DWORDX2_vi
    UINT64_C(3699146752), UINT64_C(0),	// GLOBAL_STORE_DWORDX3_SADDR_gfx10
    UINT64_C(3698458624), UINT64_C(0),	// GLOBAL_STORE_DWORDX3_SADDR_gfx11
    UINT64_C(3993436160), UINT64_C(0),	// GLOBAL_STORE_DWORDX3_SADDR_gfx12
    UINT64_C(3698884608), UINT64_C(0),	// GLOBAL_STORE_DWORDX3_SADDR_vi
    UINT64_C(35184375787978752), UINT64_C(0),	// GLOBAL_STORE_DWORDX3_gfx10
    UINT64_C(34902900810579968), UINT64_C(0),	// GLOBAL_STORE_DWORDX3_gfx11
    UINT64_C(3993436284), UINT64_C(0),	// GLOBAL_STORE_DWORDX3_gfx12
    UINT64_C(35747325741137920), UINT64_C(0),	// GLOBAL_STORE_DWORDX3_vi
    UINT64_C(3698884608), UINT64_C(0),	// GLOBAL_STORE_DWORDX4_SADDR_gfx10
    UINT64_C(3698720768), UINT64_C(0),	// GLOBAL_STORE_DWORDX4_SADDR_gfx11
    UINT64_C(3993452544), UINT64_C(0),	// GLOBAL_STORE_DWORDX4_SADDR_gfx12
    UINT64_C(3699146752), UINT64_C(0),	// GLOBAL_STORE_DWORDX4_SADDR_vi
    UINT64_C(35184375787716608), UINT64_C(0),	// GLOBAL_STORE_DWORDX4_gfx10
    UINT64_C(34902900810842112), UINT64_C(0),	// GLOBAL_STORE_DWORDX4_gfx11
    UINT64_C(3993452668), UINT64_C(0),	// GLOBAL_STORE_DWORDX4_gfx12
    UINT64_C(35747325741400064), UINT64_C(0),	// GLOBAL_STORE_DWORDX4_vi
    UINT64_C(3697049600), UINT64_C(0),	// GLOBAL_STORE_DWORD_ADDTID_SADDR_gfx10
    UINT64_C(3701866496), UINT64_C(0),	// GLOBAL_STORE_DWORD_ADDTID_SADDR_gfx11
    UINT64_C(3993649152), UINT64_C(0),	// GLOBAL_STORE_DWORD_ADDTID_SADDR_gfx12
    UINT64_C(35184375785881600), UINT64_C(0),	// GLOBAL_STORE_DWORD_ADDTID_gfx10
    UINT64_C(34902900813987840), UINT64_C(0),	// GLOBAL_STORE_DWORD_ADDTID_gfx11
    UINT64_C(3993649276), UINT64_C(0),	// GLOBAL_STORE_DWORD_ADDTID_gfx12
    UINT64_C(3698360320), UINT64_C(0),	// GLOBAL_STORE_DWORD_SADDR_gfx10
    UINT64_C(3697934336), UINT64_C(0),	// GLOBAL_STORE_DWORD_SADDR_gfx11
    UINT64_C(3993403392), UINT64_C(0),	// GLOBAL_STORE_DWORD_SADDR_gfx12
    UINT64_C(3698360320), UINT64_C(0),	// GLOBAL_STORE_DWORD_SADDR_vi
    UINT64_C(35184375787192320), UINT64_C(0),	// GLOBAL_STORE_DWORD_gfx10
    UINT64_C(34902900810055680), UINT64_C(0),	// GLOBAL_STORE_DWORD_gfx11
    UINT64_C(3993403516), UINT64_C(0),	// GLOBAL_STORE_DWORD_gfx12
    UINT64_C(35747325740613632), UINT64_C(0),	// GLOBAL_STORE_DWORD_vi
    UINT64_C(3698098176), UINT64_C(0),	// GLOBAL_STORE_SHORT_D16_HI_SADDR_gfx10
    UINT64_C(3700817920), UINT64_C(0),	// GLOBAL_STORE_SHORT_D16_HI_SADDR_gfx11
    UINT64_C(3993583616), UINT64_C(0),	// GLOBAL_STORE_SHORT_D16_HI_SADDR_gfx12
    UINT64_C(3698098176), UINT64_C(0),	// GLOBAL_STORE_SHORT_D16_HI_SADDR_vi
    UINT64_C(35184375786930176), UINT64_C(0),	// GLOBAL_STORE_SHORT_D16_HI_gfx10
    UINT64_C(34902900812939264), UINT64_C(0),	// GLOBAL_STORE_SHORT_D16_HI_gfx11
    UINT64_C(3993583740), UINT64_C(0),	// GLOBAL_STORE_SHORT_D16_HI_gfx12
    UINT64_C(35747325740351488), UINT64_C(0),	// GLOBAL_STORE_SHORT_D16_HI_vi
    UINT64_C(3697836032), UINT64_C(0),	// GLOBAL_STORE_SHORT_SADDR_gfx10
    UINT64_C(3697672192), UINT64_C(0),	// GLOBAL_STORE_SHORT_SADDR_gfx11
    UINT64_C(3993387008), UINT64_C(0),	// GLOBAL_STORE_SHORT_SADDR_gfx12
    UINT64_C(3697836032), UINT64_C(0),	// GLOBAL_STORE_SHORT_SADDR_vi
    UINT64_C(35184375786668032), UINT64_C(0),	// GLOBAL_STORE_SHORT_gfx10
    UINT64_C(34902900809793536), UINT64_C(0),	// GLOBAL_STORE_SHORT_gfx11
    UINT64_C(3993387132), UINT64_C(0),	// GLOBAL_STORE_SHORT_gfx12
    UINT64_C(35747325740089344), UINT64_C(0),	// GLOBAL_STORE_SHORT_vi
    UINT64_C(3994271868), UINT64_C(0),	// GLOBAL_WBINV_gfx12
    UINT64_C(3993698428), UINT64_C(0),	// GLOBAL_WB_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_NORTN_V1_V1_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_NORTN_V1_V2_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_NORTN_V1_V3_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_NORTN_V1_V4_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_NORTN_V2_V1_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_NORTN_V2_V2_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_NORTN_V2_V3_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_NORTN_V2_V4_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_NORTN_V3_V1_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_NORTN_V3_V2_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_NORTN_V3_V3_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_NORTN_V3_V4_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_V1_V1_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_V1_V2_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_V1_V3_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_V1_V4_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_V2_V1_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_V2_V2_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_V2_V3_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_V2_V4_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_V3_V1_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_V3_V2_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_V3_V3_gfx12
    UINT64_C(3491807232), UINT64_C(0),	// IMAGE_ATOMIC_ADD_FLT_V3_V4_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V1_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V1_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V1_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V1_gfx90a
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V1_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V1_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V2_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V2_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V2_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V2_gfx90a
    UINT64_C(4030988290), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V2_nsa_gfx10
    UINT64_C(4029677569), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V2_nsa_gfx11
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V2_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V2_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V3_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V3_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V3_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V3_gfx90a
    UINT64_C(4030988290), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V3_nsa_gfx10
    UINT64_C(4029677569), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V3_nsa_gfx11
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V3_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V3_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V4_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V4_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V4_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V4_gfx90a
    UINT64_C(4030988290), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V4_nsa_gfx10
    UINT64_C(4029677569), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V4_nsa_gfx11
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V4_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V1_V4_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V1_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V1_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V1_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V1_gfx90a
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V1_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V1_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V2_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V2_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V2_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V2_gfx90a
    UINT64_C(4030988290), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V2_nsa_gfx10
    UINT64_C(4029677569), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V2_nsa_gfx11
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V2_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V2_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V3_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V3_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V3_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V3_gfx90a
    UINT64_C(4030988290), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V3_nsa_gfx10
    UINT64_C(4029677569), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V3_nsa_gfx11
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V3_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V3_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V4_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V4_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V4_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V4_gfx90a
    UINT64_C(4030988290), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V4_nsa_gfx10
    UINT64_C(4029677569), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V4_nsa_gfx11
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V4_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V2_V4_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V1_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V1_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V1_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V1_gfx90a
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V1_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V1_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V2_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V2_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V2_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V2_gfx90a
    UINT64_C(4030988290), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V2_nsa_gfx10
    UINT64_C(4029677569), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V2_nsa_gfx11
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V2_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V2_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V3_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V3_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V3_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V3_gfx90a
    UINT64_C(4030988290), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V3_nsa_gfx10
    UINT64_C(4029677569), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V3_nsa_gfx11
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V3_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V3_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V4_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V4_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V4_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V4_gfx90a
    UINT64_C(4030988290), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V4_nsa_gfx10
    UINT64_C(4029677569), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V4_nsa_gfx11
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V4_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_NORTN_V3_V4_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V1_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V1_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V1_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V1_gfx90a
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V1_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V1_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V2_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V2_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V2_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V2_gfx90a
    UINT64_C(4030988290), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V2_nsa_gfx10
    UINT64_C(4029677569), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V2_nsa_gfx11
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V2_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V2_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V3_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V3_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V3_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V3_gfx90a
    UINT64_C(4030988290), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V3_nsa_gfx10
    UINT64_C(4029677569), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V3_nsa_gfx11
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V3_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V3_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V4_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V4_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V4_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V4_gfx90a
    UINT64_C(4030988290), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V4_nsa_gfx10
    UINT64_C(4029677569), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V4_nsa_gfx11
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V4_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V1_V4_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V1_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V1_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V1_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V1_gfx90a
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V1_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V1_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V2_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V2_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V2_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V2_gfx90a
    UINT64_C(4030988290), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V2_nsa_gfx10
    UINT64_C(4029677569), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V2_nsa_gfx11
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V2_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V2_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V3_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V3_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V3_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V3_gfx90a
    UINT64_C(4030988290), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V3_nsa_gfx10
    UINT64_C(4029677569), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V3_nsa_gfx11
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V3_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V3_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V4_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V4_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V4_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V4_gfx90a
    UINT64_C(4030988290), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V4_nsa_gfx10
    UINT64_C(4029677569), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V4_nsa_gfx11
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V4_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V2_V4_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V1_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V1_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V1_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V1_gfx90a
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V1_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V1_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V2_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V2_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V2_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V2_gfx90a
    UINT64_C(4030988290), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V2_nsa_gfx10
    UINT64_C(4029677569), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V2_nsa_gfx11
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V2_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V2_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V3_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V3_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V3_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V3_gfx90a
    UINT64_C(4030988290), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V3_nsa_gfx10
    UINT64_C(4029677569), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V3_nsa_gfx11
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V3_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V3_vi
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V4_gfx10
    UINT64_C(4029677568), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V4_gfx11
    UINT64_C(3489857536), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V4_gfx12
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V4_gfx90a
    UINT64_C(4030988290), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V4_nsa_gfx10
    UINT64_C(4029677569), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V4_nsa_gfx11
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V4_si
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_ADD_V3_V4_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V1_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V1_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V1_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V1_gfx90a
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V1_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V1_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V2_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V2_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V2_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V2_gfx90a
    UINT64_C(4032823298), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V2_nsa_gfx10
    UINT64_C(4031250433), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V2_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V2_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V2_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V3_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V3_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V3_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V3_gfx90a
    UINT64_C(4032823298), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V3_nsa_gfx10
    UINT64_C(4031250433), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V3_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V3_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V3_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V4_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V4_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V4_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V4_gfx90a
    UINT64_C(4032823298), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V4_nsa_gfx10
    UINT64_C(4031250433), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V4_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V4_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V1_V4_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V1_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V1_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V1_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V1_gfx90a
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V1_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V1_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V2_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V2_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V2_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V2_gfx90a
    UINT64_C(4032823298), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V2_nsa_gfx10
    UINT64_C(4031250433), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V2_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V2_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V2_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V3_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V3_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V3_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V3_gfx90a
    UINT64_C(4032823298), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V3_nsa_gfx10
    UINT64_C(4031250433), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V3_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V3_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V3_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V4_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V4_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V4_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V4_gfx90a
    UINT64_C(4032823298), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V4_nsa_gfx10
    UINT64_C(4031250433), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V4_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V4_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V2_V4_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V1_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V1_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V1_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V1_gfx90a
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V1_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V1_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V2_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V2_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V2_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V2_gfx90a
    UINT64_C(4032823298), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V2_nsa_gfx10
    UINT64_C(4031250433), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V2_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V2_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V2_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V3_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V3_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V3_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V3_gfx90a
    UINT64_C(4032823298), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V3_nsa_gfx10
    UINT64_C(4031250433), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V3_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V3_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V3_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V4_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V4_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V4_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V4_gfx90a
    UINT64_C(4032823298), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V4_nsa_gfx10
    UINT64_C(4031250433), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V4_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V4_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_NORTN_V3_V4_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V1_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V1_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V1_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V1_gfx90a
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V1_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V1_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V2_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V2_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V2_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V2_gfx90a
    UINT64_C(4032823298), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V2_nsa_gfx10
    UINT64_C(4031250433), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V2_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V2_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V2_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V3_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V3_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V3_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V3_gfx90a
    UINT64_C(4032823298), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V3_nsa_gfx10
    UINT64_C(4031250433), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V3_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V3_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V3_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V4_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V4_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V4_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V4_gfx90a
    UINT64_C(4032823298), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V4_nsa_gfx10
    UINT64_C(4031250433), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V4_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V4_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V1_V4_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V1_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V1_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V1_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V1_gfx90a
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V1_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V1_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V2_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V2_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V2_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V2_gfx90a
    UINT64_C(4032823298), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V2_nsa_gfx10
    UINT64_C(4031250433), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V2_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V2_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V2_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V3_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V3_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V3_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V3_gfx90a
    UINT64_C(4032823298), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V3_nsa_gfx10
    UINT64_C(4031250433), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V3_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V3_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V3_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V4_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V4_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V4_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V4_gfx90a
    UINT64_C(4032823298), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V4_nsa_gfx10
    UINT64_C(4031250433), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V4_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V4_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V2_V4_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V1_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V1_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V1_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V1_gfx90a
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V1_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V1_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V2_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V2_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V2_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V2_gfx90a
    UINT64_C(4032823298), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V2_nsa_gfx10
    UINT64_C(4031250433), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V2_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V2_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V2_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V3_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V3_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V3_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V3_gfx90a
    UINT64_C(4032823298), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V3_nsa_gfx10
    UINT64_C(4031250433), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V3_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V3_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V3_vi
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V4_gfx10
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V4_gfx11
    UINT64_C(3489955840), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V4_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V4_gfx90a
    UINT64_C(4032823298), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V4_nsa_gfx10
    UINT64_C(4031250433), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V4_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V4_si
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_ATOMIC_AND_V3_V4_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V1_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V1_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V1_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V1_gfx90a
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V1_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V1_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V1_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V1_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V1_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V1_gfx90a
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V1_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V1_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V1_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V1_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V1_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V1_gfx90a
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V1_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V1_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V1_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V1_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V1_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V1_gfx90a
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V1_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V1_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V1_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V1_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V1_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V1_gfx90a
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V1_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V1_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V2_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V2_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V2_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V2_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V2_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V2_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V2_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V2_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V3_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V3_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V3_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V3_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V3_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V3_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V3_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V3_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V4_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V4_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V4_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V4_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V4_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V4_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V4_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V2_V4_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V1_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V1_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V1_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V1_gfx90a
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V1_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V1_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V2_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V2_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V2_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V2_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V2_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V2_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V2_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V2_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V3_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V3_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V3_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V3_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V3_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V3_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V3_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V3_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V4_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V4_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V4_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V4_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V4_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V4_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V4_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V3_V4_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V1_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V1_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V1_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V1_gfx90a
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V1_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V1_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V2_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V2_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V2_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V2_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V2_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V2_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V2_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V2_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V3_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V3_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V3_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V3_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V3_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V3_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V3_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V3_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V4_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V4_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V4_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V4_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V4_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V4_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V4_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V4_V4_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V1_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V1_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V1_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V1_gfx90a
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V1_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V1_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V2_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V2_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V2_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V2_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V2_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V2_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V2_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V2_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V3_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V3_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V3_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V3_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V3_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V3_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V3_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V3_vi
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V4_gfx10
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V4_gfx11
    UINT64_C(3489841152), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V4_gfx12
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V4_gfx90a
    UINT64_C(4030726146), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V4_nsa_gfx10
    UINT64_C(4029415425), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V4_nsa_gfx11
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V4_si
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_CMPSWAP_V5_V4_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V1_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V1_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V1_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V1_gfx90a
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V1_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V1_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V2_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V2_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V2_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V2_gfx90a
    UINT64_C(4033871874), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V2_nsa_gfx10
    UINT64_C(4032299009), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V2_nsa_gfx11
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V2_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V2_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V3_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V3_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V3_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V3_gfx90a
    UINT64_C(4033871874), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V3_nsa_gfx10
    UINT64_C(4032299009), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V3_nsa_gfx11
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V3_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V3_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V4_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V4_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V4_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V4_gfx90a
    UINT64_C(4033871874), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V4_nsa_gfx10
    UINT64_C(4032299009), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V4_nsa_gfx11
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V4_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V1_V4_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V1_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V1_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V1_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V1_gfx90a
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V1_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V1_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V2_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V2_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V2_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V2_gfx90a
    UINT64_C(4033871874), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V2_nsa_gfx10
    UINT64_C(4032299009), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V2_nsa_gfx11
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V2_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V2_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V3_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V3_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V3_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V3_gfx90a
    UINT64_C(4033871874), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V3_nsa_gfx10
    UINT64_C(4032299009), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V3_nsa_gfx11
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V3_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V3_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V4_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V4_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V4_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V4_gfx90a
    UINT64_C(4033871874), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V4_nsa_gfx10
    UINT64_C(4032299009), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V4_nsa_gfx11
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V4_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V2_V4_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V1_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V1_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V1_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V1_gfx90a
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V1_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V1_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V2_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V2_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V2_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V2_gfx90a
    UINT64_C(4033871874), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V2_nsa_gfx10
    UINT64_C(4032299009), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V2_nsa_gfx11
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V2_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V2_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V3_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V3_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V3_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V3_gfx90a
    UINT64_C(4033871874), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V3_nsa_gfx10
    UINT64_C(4032299009), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V3_nsa_gfx11
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V3_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V3_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V4_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V4_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V4_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V4_gfx90a
    UINT64_C(4033871874), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V4_nsa_gfx10
    UINT64_C(4032299009), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V4_nsa_gfx11
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V4_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_NORTN_V3_V4_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V1_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V1_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V1_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V1_gfx90a
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V1_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V1_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V2_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V2_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V2_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V2_gfx90a
    UINT64_C(4033871874), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V2_nsa_gfx10
    UINT64_C(4032299009), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V2_nsa_gfx11
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V2_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V2_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V3_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V3_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V3_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V3_gfx90a
    UINT64_C(4033871874), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V3_nsa_gfx10
    UINT64_C(4032299009), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V3_nsa_gfx11
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V3_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V3_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V4_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V4_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V4_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V4_gfx90a
    UINT64_C(4033871874), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V4_nsa_gfx10
    UINT64_C(4032299009), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V4_nsa_gfx11
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V4_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V1_V4_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V1_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V1_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V1_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V1_gfx90a
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V1_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V1_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V2_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V2_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V2_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V2_gfx90a
    UINT64_C(4033871874), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V2_nsa_gfx10
    UINT64_C(4032299009), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V2_nsa_gfx11
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V2_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V2_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V3_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V3_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V3_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V3_gfx90a
    UINT64_C(4033871874), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V3_nsa_gfx10
    UINT64_C(4032299009), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V3_nsa_gfx11
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V3_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V3_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V4_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V4_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V4_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V4_gfx90a
    UINT64_C(4033871874), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V4_nsa_gfx10
    UINT64_C(4032299009), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V4_nsa_gfx11
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V4_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V2_V4_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V1_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V1_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V1_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V1_gfx90a
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V1_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V1_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V2_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V2_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V2_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V2_gfx90a
    UINT64_C(4033871874), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V2_nsa_gfx10
    UINT64_C(4032299009), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V2_nsa_gfx11
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V2_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V2_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V3_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V3_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V3_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V3_gfx90a
    UINT64_C(4033871874), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V3_nsa_gfx10
    UINT64_C(4032299009), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V3_nsa_gfx11
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V3_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V3_vi
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V4_gfx10
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V4_gfx11
    UINT64_C(3490021376), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V4_gfx12
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V4_gfx90a
    UINT64_C(4033871874), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V4_nsa_gfx10
    UINT64_C(4032299009), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V4_nsa_gfx11
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V4_si
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_ATOMIC_DEC_V3_V4_vi
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V1_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V1_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V2_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V2_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V2_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V3_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V3_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V3_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V4_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V4_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V4_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V1_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V1_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V2_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V2_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V2_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V3_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V3_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V3_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V4_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V4_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V4_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V1_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V1_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V2_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V2_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V2_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V3_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V3_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V3_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V4_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V4_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V4_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V1_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V1_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V2_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V2_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V2_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V3_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V3_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V3_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V4_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V4_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V4_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V2_V1_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V2_V1_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V2_V2_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V2_V2_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V2_V2_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V2_V3_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V2_V3_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V2_V3_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V2_V4_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V2_V4_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V2_V4_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V3_V1_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V3_V1_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V3_V2_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V3_V2_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V3_V2_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V3_V3_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V3_V3_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V3_V3_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V3_V4_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V3_V4_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V3_V4_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V4_V1_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V4_V1_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V4_V2_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V4_V2_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V4_V2_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V4_V3_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V4_V3_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V4_V3_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V4_V4_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V4_V4_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V4_V4_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V5_V1_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V5_V1_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V5_V2_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V5_V2_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V5_V2_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V5_V3_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V5_V3_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V5_V3_si
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V5_V4_gfx10
    UINT64_C(4034134018), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V5_V4_nsa_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_ATOMIC_FCMPSWAP_V5_V4_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V1_V1_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V1_V1_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V1_V2_gfx10
    UINT64_C(4034658306), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V1_V2_nsa_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V1_V2_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V1_V3_gfx10
    UINT64_C(4034658306), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V1_V3_nsa_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V1_V3_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V1_V4_gfx10
    UINT64_C(4034658306), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V1_V4_nsa_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V1_V4_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V2_V1_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V2_V1_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V2_V2_gfx10
    UINT64_C(4034658306), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V2_V2_nsa_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V2_V2_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V2_V3_gfx10
    UINT64_C(4034658306), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V2_V3_nsa_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V2_V3_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V2_V4_gfx10
    UINT64_C(4034658306), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V2_V4_nsa_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V2_V4_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V3_V1_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V3_V1_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V3_V2_gfx10
    UINT64_C(4034658306), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V3_V2_nsa_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V3_V2_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V3_V3_gfx10
    UINT64_C(4034658306), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V3_V3_nsa_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V3_V3_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V3_V4_gfx10
    UINT64_C(4034658306), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V3_V4_nsa_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_NORTN_V3_V4_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V1_V1_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V1_V1_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V1_V2_gfx10
    UINT64_C(4034658306), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V1_V2_nsa_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V1_V2_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V1_V3_gfx10
    UINT64_C(4034658306), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V1_V3_nsa_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V1_V3_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V1_V4_gfx10
    UINT64_C(4034658306), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V1_V4_nsa_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V1_V4_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V2_V1_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V2_V1_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V2_V2_gfx10
    UINT64_C(4034658306), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V2_V2_nsa_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V2_V2_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V2_V3_gfx10
    UINT64_C(4034658306), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V2_V3_nsa_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V2_V3_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V2_V4_gfx10
    UINT64_C(4034658306), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V2_V4_nsa_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V2_V4_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V3_V1_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V3_V1_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V3_V2_gfx10
    UINT64_C(4034658306), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V3_V2_nsa_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V3_V2_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V3_V3_gfx10
    UINT64_C(4034658306), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V3_V3_nsa_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V3_V3_si
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V3_V4_gfx10
    UINT64_C(4034658306), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V3_V4_nsa_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_ATOMIC_FMAX_V3_V4_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V1_V1_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V1_V1_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V1_V2_gfx10
    UINT64_C(4034396162), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V1_V2_nsa_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V1_V2_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V1_V3_gfx10
    UINT64_C(4034396162), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V1_V3_nsa_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V1_V3_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V1_V4_gfx10
    UINT64_C(4034396162), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V1_V4_nsa_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V1_V4_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V2_V1_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V2_V1_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V2_V2_gfx10
    UINT64_C(4034396162), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V2_V2_nsa_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V2_V2_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V2_V3_gfx10
    UINT64_C(4034396162), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V2_V3_nsa_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V2_V3_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V2_V4_gfx10
    UINT64_C(4034396162), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V2_V4_nsa_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V2_V4_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V3_V1_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V3_V1_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V3_V2_gfx10
    UINT64_C(4034396162), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V3_V2_nsa_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V3_V2_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V3_V3_gfx10
    UINT64_C(4034396162), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V3_V3_nsa_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V3_V3_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V3_V4_gfx10
    UINT64_C(4034396162), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V3_V4_nsa_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_NORTN_V3_V4_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V1_V1_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V1_V1_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V1_V2_gfx10
    UINT64_C(4034396162), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V1_V2_nsa_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V1_V2_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V1_V3_gfx10
    UINT64_C(4034396162), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V1_V3_nsa_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V1_V3_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V1_V4_gfx10
    UINT64_C(4034396162), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V1_V4_nsa_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V1_V4_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V2_V1_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V2_V1_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V2_V2_gfx10
    UINT64_C(4034396162), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V2_V2_nsa_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V2_V2_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V2_V3_gfx10
    UINT64_C(4034396162), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V2_V3_nsa_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V2_V3_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V2_V4_gfx10
    UINT64_C(4034396162), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V2_V4_nsa_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V2_V4_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V3_V1_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V3_V1_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V3_V2_gfx10
    UINT64_C(4034396162), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V3_V2_nsa_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V3_V2_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V3_V3_gfx10
    UINT64_C(4034396162), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V3_V3_nsa_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V3_V3_si
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V3_V4_gfx10
    UINT64_C(4034396162), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V3_V4_nsa_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_ATOMIC_FMIN_V3_V4_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V1_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V1_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V1_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V1_gfx90a
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V1_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V1_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V2_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V2_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V2_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V2_gfx90a
    UINT64_C(4033609730), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V2_nsa_gfx10
    UINT64_C(4032036865), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V2_nsa_gfx11
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V2_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V2_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V3_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V3_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V3_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V3_gfx90a
    UINT64_C(4033609730), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V3_nsa_gfx10
    UINT64_C(4032036865), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V3_nsa_gfx11
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V3_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V3_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V4_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V4_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V4_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V4_gfx90a
    UINT64_C(4033609730), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V4_nsa_gfx10
    UINT64_C(4032036865), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V4_nsa_gfx11
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V4_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V1_V4_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V1_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V1_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V1_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V1_gfx90a
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V1_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V1_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V2_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V2_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V2_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V2_gfx90a
    UINT64_C(4033609730), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V2_nsa_gfx10
    UINT64_C(4032036865), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V2_nsa_gfx11
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V2_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V2_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V3_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V3_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V3_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V3_gfx90a
    UINT64_C(4033609730), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V3_nsa_gfx10
    UINT64_C(4032036865), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V3_nsa_gfx11
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V3_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V3_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V4_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V4_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V4_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V4_gfx90a
    UINT64_C(4033609730), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V4_nsa_gfx10
    UINT64_C(4032036865), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V4_nsa_gfx11
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V4_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V2_V4_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V1_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V1_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V1_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V1_gfx90a
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V1_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V1_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V2_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V2_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V2_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V2_gfx90a
    UINT64_C(4033609730), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V2_nsa_gfx10
    UINT64_C(4032036865), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V2_nsa_gfx11
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V2_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V2_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V3_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V3_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V3_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V3_gfx90a
    UINT64_C(4033609730), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V3_nsa_gfx10
    UINT64_C(4032036865), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V3_nsa_gfx11
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V3_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V3_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V4_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V4_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V4_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V4_gfx90a
    UINT64_C(4033609730), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V4_nsa_gfx10
    UINT64_C(4032036865), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V4_nsa_gfx11
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V4_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_NORTN_V3_V4_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V1_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V1_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V1_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V1_gfx90a
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V1_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V1_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V2_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V2_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V2_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V2_gfx90a
    UINT64_C(4033609730), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V2_nsa_gfx10
    UINT64_C(4032036865), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V2_nsa_gfx11
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V2_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V2_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V3_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V3_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V3_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V3_gfx90a
    UINT64_C(4033609730), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V3_nsa_gfx10
    UINT64_C(4032036865), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V3_nsa_gfx11
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V3_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V3_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V4_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V4_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V4_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V4_gfx90a
    UINT64_C(4033609730), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V4_nsa_gfx10
    UINT64_C(4032036865), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V4_nsa_gfx11
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V4_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V1_V4_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V1_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V1_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V1_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V1_gfx90a
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V1_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V1_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V2_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V2_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V2_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V2_gfx90a
    UINT64_C(4033609730), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V2_nsa_gfx10
    UINT64_C(4032036865), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V2_nsa_gfx11
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V2_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V2_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V3_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V3_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V3_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V3_gfx90a
    UINT64_C(4033609730), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V3_nsa_gfx10
    UINT64_C(4032036865), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V3_nsa_gfx11
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V3_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V3_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V4_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V4_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V4_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V4_gfx90a
    UINT64_C(4033609730), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V4_nsa_gfx10
    UINT64_C(4032036865), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V4_nsa_gfx11
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V4_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V2_V4_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V1_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V1_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V1_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V1_gfx90a
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V1_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V1_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V2_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V2_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V2_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V2_gfx90a
    UINT64_C(4033609730), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V2_nsa_gfx10
    UINT64_C(4032036865), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V2_nsa_gfx11
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V2_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V2_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V3_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V3_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V3_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V3_gfx90a
    UINT64_C(4033609730), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V3_nsa_gfx10
    UINT64_C(4032036865), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V3_nsa_gfx11
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V3_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V3_vi
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V4_gfx10
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V4_gfx11
    UINT64_C(3490004992), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V4_gfx12
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V4_gfx90a
    UINT64_C(4033609730), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V4_nsa_gfx10
    UINT64_C(4032036865), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V4_nsa_gfx11
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V4_si
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_ATOMIC_INC_V3_V4_vi
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_NORTN_V1_V1_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_NORTN_V1_V2_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_NORTN_V1_V3_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_NORTN_V1_V4_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_NORTN_V2_V1_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_NORTN_V2_V2_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_NORTN_V2_V3_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_NORTN_V2_V4_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_NORTN_V3_V1_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_NORTN_V3_V2_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_NORTN_V3_V3_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_NORTN_V3_V4_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_V1_V1_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_V1_V2_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_V1_V3_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_V1_V4_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_V2_V1_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_V2_V2_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_V2_V3_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_V2_V4_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_V3_V1_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_V3_V2_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_V3_V3_gfx12
    UINT64_C(3491840000), UINT64_C(0),	// IMAGE_ATOMIC_MAX_FLT_V3_V4_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_NORTN_V1_V1_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_NORTN_V1_V2_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_NORTN_V1_V3_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_NORTN_V1_V4_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_NORTN_V2_V1_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_NORTN_V2_V2_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_NORTN_V2_V3_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_NORTN_V2_V4_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_NORTN_V3_V1_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_NORTN_V3_V2_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_NORTN_V3_V3_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_NORTN_V3_V4_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_V1_V1_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_V1_V2_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_V1_V3_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_V1_V4_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_V2_V1_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_V2_V2_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_V2_V3_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_V2_V4_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_V3_V1_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_V3_V2_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_V3_V3_gfx12
    UINT64_C(3491823616), UINT64_C(0),	// IMAGE_ATOMIC_MIN_FLT_V3_V4_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V1_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V1_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V1_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V1_gfx90a
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V1_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V1_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V2_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V2_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V2_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V2_gfx90a
    UINT64_C(4033085442), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V2_nsa_gfx10
    UINT64_C(4031512577), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V2_nsa_gfx11
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V2_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V2_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V3_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V3_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V3_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V3_gfx90a
    UINT64_C(4033085442), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V3_nsa_gfx10
    UINT64_C(4031512577), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V3_nsa_gfx11
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V3_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V3_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V4_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V4_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V4_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V4_gfx90a
    UINT64_C(4033085442), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V4_nsa_gfx10
    UINT64_C(4031512577), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V4_nsa_gfx11
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V4_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V1_V4_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V1_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V1_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V1_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V1_gfx90a
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V1_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V1_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V2_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V2_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V2_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V2_gfx90a
    UINT64_C(4033085442), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V2_nsa_gfx10
    UINT64_C(4031512577), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V2_nsa_gfx11
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V2_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V2_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V3_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V3_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V3_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V3_gfx90a
    UINT64_C(4033085442), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V3_nsa_gfx10
    UINT64_C(4031512577), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V3_nsa_gfx11
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V3_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V3_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V4_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V4_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V4_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V4_gfx90a
    UINT64_C(4033085442), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V4_nsa_gfx10
    UINT64_C(4031512577), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V4_nsa_gfx11
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V4_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V2_V4_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V1_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V1_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V1_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V1_gfx90a
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V1_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V1_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V2_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V2_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V2_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V2_gfx90a
    UINT64_C(4033085442), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V2_nsa_gfx10
    UINT64_C(4031512577), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V2_nsa_gfx11
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V2_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V2_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V3_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V3_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V3_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V3_gfx90a
    UINT64_C(4033085442), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V3_nsa_gfx10
    UINT64_C(4031512577), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V3_nsa_gfx11
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V3_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V3_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V4_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V4_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V4_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V4_gfx90a
    UINT64_C(4033085442), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V4_nsa_gfx10
    UINT64_C(4031512577), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V4_nsa_gfx11
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V4_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_NORTN_V3_V4_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V1_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V1_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V1_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V1_gfx90a
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V1_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V1_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V2_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V2_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V2_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V2_gfx90a
    UINT64_C(4033085442), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V2_nsa_gfx10
    UINT64_C(4031512577), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V2_nsa_gfx11
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V2_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V2_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V3_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V3_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V3_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V3_gfx90a
    UINT64_C(4033085442), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V3_nsa_gfx10
    UINT64_C(4031512577), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V3_nsa_gfx11
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V3_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V3_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V4_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V4_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V4_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V4_gfx90a
    UINT64_C(4033085442), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V4_nsa_gfx10
    UINT64_C(4031512577), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V4_nsa_gfx11
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V4_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V1_V4_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V1_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V1_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V1_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V1_gfx90a
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V1_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V1_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V2_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V2_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V2_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V2_gfx90a
    UINT64_C(4033085442), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V2_nsa_gfx10
    UINT64_C(4031512577), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V2_nsa_gfx11
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V2_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V2_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V3_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V3_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V3_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V3_gfx90a
    UINT64_C(4033085442), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V3_nsa_gfx10
    UINT64_C(4031512577), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V3_nsa_gfx11
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V3_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V3_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V4_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V4_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V4_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V4_gfx90a
    UINT64_C(4033085442), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V4_nsa_gfx10
    UINT64_C(4031512577), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V4_nsa_gfx11
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V4_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V2_V4_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V1_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V1_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V1_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V1_gfx90a
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V1_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V1_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V2_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V2_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V2_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V2_gfx90a
    UINT64_C(4033085442), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V2_nsa_gfx10
    UINT64_C(4031512577), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V2_nsa_gfx11
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V2_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V2_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V3_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V3_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V3_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V3_gfx90a
    UINT64_C(4033085442), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V3_nsa_gfx10
    UINT64_C(4031512577), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V3_nsa_gfx11
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V3_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V3_vi
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V4_gfx10
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V4_gfx11
    UINT64_C(3489972224), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V4_gfx12
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V4_gfx90a
    UINT64_C(4033085442), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V4_nsa_gfx10
    UINT64_C(4031512577), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V4_nsa_gfx11
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V4_si
    UINT64_C(4033085440), UINT64_C(0),	// IMAGE_ATOMIC_OR_V3_V4_vi
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V1_V1_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V1_V2_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V1_V3_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V1_V4_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V2_V1_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V2_V2_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V2_V3_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V2_V4_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V3_V1_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V3_V2_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V3_V3_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V3_V4_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_V1_V1_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_V1_V2_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_V1_V3_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_V1_V4_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_V2_V1_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_V2_V2_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_V2_V3_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_V2_V4_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_V3_V1_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_V3_V2_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_V3_V3_gfx12
    UINT64_C(3491872768), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_BF16_V3_V4_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_NORTN_V1_V1_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_NORTN_V1_V2_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_NORTN_V1_V3_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_NORTN_V1_V4_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_NORTN_V2_V1_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_NORTN_V2_V2_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_NORTN_V2_V3_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_NORTN_V2_V4_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_NORTN_V3_V1_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_NORTN_V3_V2_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_NORTN_V3_V3_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_NORTN_V3_V4_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_V1_V1_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_V1_V2_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_V1_V3_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_V1_V4_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_V2_V1_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_V2_V2_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_V2_V3_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_V2_V4_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_V3_V1_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_V3_V2_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_V3_V3_gfx12
    UINT64_C(3491856384), UINT64_C(0),	// IMAGE_ATOMIC_PK_ADD_F16_V3_V4_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_NORTN_V1_V1_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_NORTN_V1_V2_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_NORTN_V1_V3_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_NORTN_V1_V4_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_NORTN_V2_V1_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_NORTN_V2_V2_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_NORTN_V2_V3_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_NORTN_V2_V4_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_NORTN_V3_V1_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_NORTN_V3_V2_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_NORTN_V3_V3_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_NORTN_V3_V4_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_V1_V1_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_V1_V2_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_V1_V3_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_V1_V4_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_V2_V1_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_V2_V2_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_V2_V3_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_V2_V4_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_V3_V1_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_V3_V2_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_V3_V3_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_RSUB_V3_V4_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V1_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V1_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V1_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V1_gfx90a
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V1_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V1_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V2_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V2_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V2_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V2_gfx90a
    UINT64_C(4032299010), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V2_nsa_gfx10
    UINT64_C(4030726145), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V2_nsa_gfx11
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V2_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V2_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V3_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V3_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V3_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V3_gfx90a
    UINT64_C(4032299010), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V3_nsa_gfx10
    UINT64_C(4030726145), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V3_nsa_gfx11
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V3_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V3_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V4_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V4_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V4_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V4_gfx90a
    UINT64_C(4032299010), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V4_nsa_gfx10
    UINT64_C(4030726145), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V4_nsa_gfx11
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V4_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V1_V4_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V1_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V1_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V1_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V1_gfx90a
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V1_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V1_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V2_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V2_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V2_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V2_gfx90a
    UINT64_C(4032299010), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V2_nsa_gfx10
    UINT64_C(4030726145), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V2_nsa_gfx11
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V2_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V2_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V3_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V3_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V3_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V3_gfx90a
    UINT64_C(4032299010), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V3_nsa_gfx10
    UINT64_C(4030726145), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V3_nsa_gfx11
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V3_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V3_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V4_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V4_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V4_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V4_gfx90a
    UINT64_C(4032299010), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V4_nsa_gfx10
    UINT64_C(4030726145), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V4_nsa_gfx11
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V4_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V2_V4_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V1_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V1_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V1_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V1_gfx90a
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V1_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V1_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V2_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V2_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V2_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V2_gfx90a
    UINT64_C(4032299010), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V2_nsa_gfx10
    UINT64_C(4030726145), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V2_nsa_gfx11
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V2_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V2_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V3_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V3_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V3_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V3_gfx90a
    UINT64_C(4032299010), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V3_nsa_gfx10
    UINT64_C(4030726145), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V3_nsa_gfx11
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V3_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V3_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V4_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V4_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V4_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V4_gfx90a
    UINT64_C(4032299010), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V4_nsa_gfx10
    UINT64_C(4030726145), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V4_nsa_gfx11
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V4_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_NORTN_V3_V4_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V1_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V1_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V1_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V1_gfx90a
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V1_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V1_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V2_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V2_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V2_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V2_gfx90a
    UINT64_C(4032299010), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V2_nsa_gfx10
    UINT64_C(4030726145), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V2_nsa_gfx11
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V2_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V2_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V3_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V3_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V3_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V3_gfx90a
    UINT64_C(4032299010), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V3_nsa_gfx10
    UINT64_C(4030726145), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V3_nsa_gfx11
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V3_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V3_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V4_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V4_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V4_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V4_gfx90a
    UINT64_C(4032299010), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V4_nsa_gfx10
    UINT64_C(4030726145), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V4_nsa_gfx11
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V4_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V1_V4_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V1_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V1_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V1_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V1_gfx90a
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V1_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V1_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V2_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V2_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V2_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V2_gfx90a
    UINT64_C(4032299010), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V2_nsa_gfx10
    UINT64_C(4030726145), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V2_nsa_gfx11
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V2_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V2_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V3_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V3_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V3_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V3_gfx90a
    UINT64_C(4032299010), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V3_nsa_gfx10
    UINT64_C(4030726145), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V3_nsa_gfx11
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V3_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V3_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V4_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V4_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V4_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V4_gfx90a
    UINT64_C(4032299010), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V4_nsa_gfx10
    UINT64_C(4030726145), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V4_nsa_gfx11
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V4_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V2_V4_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V1_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V1_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V1_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V1_gfx90a
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V1_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V1_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V2_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V2_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V2_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V2_gfx90a
    UINT64_C(4032299010), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V2_nsa_gfx10
    UINT64_C(4030726145), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V2_nsa_gfx11
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V2_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V2_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V3_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V3_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V3_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V3_gfx90a
    UINT64_C(4032299010), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V3_nsa_gfx10
    UINT64_C(4030726145), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V3_nsa_gfx11
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V3_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V3_vi
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V4_gfx10
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V4_gfx11
    UINT64_C(3489923072), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V4_gfx12
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V4_gfx90a
    UINT64_C(4032299010), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V4_nsa_gfx10
    UINT64_C(4030726145), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V4_nsa_gfx11
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V4_si
    UINT64_C(4032299008), UINT64_C(0),	// IMAGE_ATOMIC_SMAX_V3_V4_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V1_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V1_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V1_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V1_gfx90a
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V1_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V1_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V2_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V2_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V2_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V2_gfx90a
    UINT64_C(4031774722), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V2_nsa_gfx10
    UINT64_C(4030201857), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V2_nsa_gfx11
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V2_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V2_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V3_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V3_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V3_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V3_gfx90a
    UINT64_C(4031774722), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V3_nsa_gfx10
    UINT64_C(4030201857), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V3_nsa_gfx11
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V3_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V3_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V4_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V4_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V4_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V4_gfx90a
    UINT64_C(4031774722), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V4_nsa_gfx10
    UINT64_C(4030201857), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V4_nsa_gfx11
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V4_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V1_V4_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V1_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V1_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V1_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V1_gfx90a
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V1_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V1_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V2_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V2_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V2_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V2_gfx90a
    UINT64_C(4031774722), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V2_nsa_gfx10
    UINT64_C(4030201857), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V2_nsa_gfx11
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V2_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V2_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V3_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V3_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V3_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V3_gfx90a
    UINT64_C(4031774722), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V3_nsa_gfx10
    UINT64_C(4030201857), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V3_nsa_gfx11
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V3_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V3_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V4_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V4_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V4_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V4_gfx90a
    UINT64_C(4031774722), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V4_nsa_gfx10
    UINT64_C(4030201857), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V4_nsa_gfx11
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V4_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V2_V4_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V1_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V1_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V1_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V1_gfx90a
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V1_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V1_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V2_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V2_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V2_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V2_gfx90a
    UINT64_C(4031774722), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V2_nsa_gfx10
    UINT64_C(4030201857), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V2_nsa_gfx11
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V2_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V2_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V3_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V3_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V3_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V3_gfx90a
    UINT64_C(4031774722), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V3_nsa_gfx10
    UINT64_C(4030201857), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V3_nsa_gfx11
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V3_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V3_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V4_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V4_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V4_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V4_gfx90a
    UINT64_C(4031774722), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V4_nsa_gfx10
    UINT64_C(4030201857), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V4_nsa_gfx11
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V4_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_NORTN_V3_V4_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V1_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V1_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V1_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V1_gfx90a
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V1_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V1_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V2_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V2_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V2_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V2_gfx90a
    UINT64_C(4031774722), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V2_nsa_gfx10
    UINT64_C(4030201857), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V2_nsa_gfx11
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V2_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V2_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V3_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V3_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V3_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V3_gfx90a
    UINT64_C(4031774722), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V3_nsa_gfx10
    UINT64_C(4030201857), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V3_nsa_gfx11
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V3_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V3_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V4_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V4_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V4_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V4_gfx90a
    UINT64_C(4031774722), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V4_nsa_gfx10
    UINT64_C(4030201857), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V4_nsa_gfx11
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V4_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V1_V4_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V1_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V1_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V1_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V1_gfx90a
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V1_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V1_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V2_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V2_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V2_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V2_gfx90a
    UINT64_C(4031774722), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V2_nsa_gfx10
    UINT64_C(4030201857), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V2_nsa_gfx11
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V2_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V2_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V3_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V3_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V3_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V3_gfx90a
    UINT64_C(4031774722), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V3_nsa_gfx10
    UINT64_C(4030201857), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V3_nsa_gfx11
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V3_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V3_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V4_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V4_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V4_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V4_gfx90a
    UINT64_C(4031774722), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V4_nsa_gfx10
    UINT64_C(4030201857), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V4_nsa_gfx11
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V4_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V2_V4_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V1_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V1_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V1_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V1_gfx90a
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V1_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V1_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V2_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V2_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V2_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V2_gfx90a
    UINT64_C(4031774722), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V2_nsa_gfx10
    UINT64_C(4030201857), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V2_nsa_gfx11
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V2_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V2_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V3_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V3_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V3_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V3_gfx90a
    UINT64_C(4031774722), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V3_nsa_gfx10
    UINT64_C(4030201857), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V3_nsa_gfx11
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V3_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V3_vi
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V4_gfx10
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V4_gfx11
    UINT64_C(3489890304), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V4_gfx12
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V4_gfx90a
    UINT64_C(4031774722), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V4_nsa_gfx10
    UINT64_C(4030201857), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V4_nsa_gfx11
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V4_si
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_SMIN_V3_V4_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V1_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V1_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V1_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V1_gfx90a
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V1_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V1_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V2_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V2_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V2_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V2_gfx90a
    UINT64_C(4031250434), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V2_nsa_gfx10
    UINT64_C(4029939713), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V2_nsa_gfx11
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V2_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V2_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V3_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V3_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V3_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V3_gfx90a
    UINT64_C(4031250434), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V3_nsa_gfx10
    UINT64_C(4029939713), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V3_nsa_gfx11
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V3_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V3_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V4_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V4_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V4_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V4_gfx90a
    UINT64_C(4031250434), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V4_nsa_gfx10
    UINT64_C(4029939713), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V4_nsa_gfx11
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V4_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V1_V4_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V1_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V1_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V1_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V1_gfx90a
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V1_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V1_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V2_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V2_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V2_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V2_gfx90a
    UINT64_C(4031250434), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V2_nsa_gfx10
    UINT64_C(4029939713), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V2_nsa_gfx11
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V2_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V2_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V3_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V3_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V3_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V3_gfx90a
    UINT64_C(4031250434), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V3_nsa_gfx10
    UINT64_C(4029939713), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V3_nsa_gfx11
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V3_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V3_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V4_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V4_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V4_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V4_gfx90a
    UINT64_C(4031250434), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V4_nsa_gfx10
    UINT64_C(4029939713), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V4_nsa_gfx11
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V4_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V2_V4_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V1_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V1_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V1_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V1_gfx90a
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V1_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V1_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V2_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V2_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V2_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V2_gfx90a
    UINT64_C(4031250434), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V2_nsa_gfx10
    UINT64_C(4029939713), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V2_nsa_gfx11
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V2_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V2_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V3_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V3_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V3_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V3_gfx90a
    UINT64_C(4031250434), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V3_nsa_gfx10
    UINT64_C(4029939713), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V3_nsa_gfx11
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V3_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V3_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V4_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V4_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V4_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V4_gfx90a
    UINT64_C(4031250434), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V4_nsa_gfx10
    UINT64_C(4029939713), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V4_nsa_gfx11
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V4_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_NORTN_V3_V4_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V1_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V1_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V1_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V1_gfx90a
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V1_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V1_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V2_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V2_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V2_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V2_gfx90a
    UINT64_C(4031250434), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V2_nsa_gfx10
    UINT64_C(4029939713), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V2_nsa_gfx11
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V2_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V2_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V3_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V3_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V3_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V3_gfx90a
    UINT64_C(4031250434), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V3_nsa_gfx10
    UINT64_C(4029939713), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V3_nsa_gfx11
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V3_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V3_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V4_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V4_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V4_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V4_gfx90a
    UINT64_C(4031250434), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V4_nsa_gfx10
    UINT64_C(4029939713), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V4_nsa_gfx11
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V4_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V1_V4_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V1_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V1_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V1_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V1_gfx90a
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V1_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V1_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V2_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V2_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V2_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V2_gfx90a
    UINT64_C(4031250434), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V2_nsa_gfx10
    UINT64_C(4029939713), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V2_nsa_gfx11
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V2_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V2_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V3_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V3_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V3_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V3_gfx90a
    UINT64_C(4031250434), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V3_nsa_gfx10
    UINT64_C(4029939713), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V3_nsa_gfx11
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V3_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V3_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V4_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V4_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V4_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V4_gfx90a
    UINT64_C(4031250434), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V4_nsa_gfx10
    UINT64_C(4029939713), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V4_nsa_gfx11
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V4_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V2_V4_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V1_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V1_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V1_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V1_gfx90a
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V1_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V1_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V2_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V2_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V2_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V2_gfx90a
    UINT64_C(4031250434), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V2_nsa_gfx10
    UINT64_C(4029939713), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V2_nsa_gfx11
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V2_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V2_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V3_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V3_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V3_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V3_gfx90a
    UINT64_C(4031250434), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V3_nsa_gfx10
    UINT64_C(4029939713), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V3_nsa_gfx11
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V3_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V3_vi
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V4_gfx10
    UINT64_C(4029939712), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V4_gfx11
    UINT64_C(3489873920), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V4_gfx12
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V4_gfx90a
    UINT64_C(4031250434), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V4_nsa_gfx10
    UINT64_C(4029939713), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V4_nsa_gfx11
    UINT64_C(4031250432), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V4_si
    UINT64_C(4031512576), UINT64_C(0),	// IMAGE_ATOMIC_SUB_V3_V4_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V1_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V1_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V1_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V1_gfx90a
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V1_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V1_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V2_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V2_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V2_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V2_gfx90a
    UINT64_C(4030464002), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V2_nsa_gfx10
    UINT64_C(4029153281), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V2_nsa_gfx11
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V2_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V2_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V3_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V3_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V3_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V3_gfx90a
    UINT64_C(4030464002), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V3_nsa_gfx10
    UINT64_C(4029153281), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V3_nsa_gfx11
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V3_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V3_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V4_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V4_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V4_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V4_gfx90a
    UINT64_C(4030464002), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V4_nsa_gfx10
    UINT64_C(4029153281), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V4_nsa_gfx11
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V4_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V1_V4_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V1_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V1_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V1_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V1_gfx90a
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V1_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V1_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V2_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V2_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V2_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V2_gfx90a
    UINT64_C(4030464002), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V2_nsa_gfx10
    UINT64_C(4029153281), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V2_nsa_gfx11
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V2_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V2_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V3_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V3_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V3_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V3_gfx90a
    UINT64_C(4030464002), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V3_nsa_gfx10
    UINT64_C(4029153281), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V3_nsa_gfx11
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V3_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V3_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V4_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V4_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V4_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V4_gfx90a
    UINT64_C(4030464002), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V4_nsa_gfx10
    UINT64_C(4029153281), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V4_nsa_gfx11
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V4_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V2_V4_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V1_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V1_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V1_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V1_gfx90a
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V1_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V1_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V2_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V2_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V2_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V2_gfx90a
    UINT64_C(4030464002), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V2_nsa_gfx10
    UINT64_C(4029153281), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V2_nsa_gfx11
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V2_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V2_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V3_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V3_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V3_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V3_gfx90a
    UINT64_C(4030464002), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V3_nsa_gfx10
    UINT64_C(4029153281), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V3_nsa_gfx11
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V3_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V3_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V4_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V4_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V4_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V4_gfx90a
    UINT64_C(4030464002), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V4_nsa_gfx10
    UINT64_C(4029153281), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V4_nsa_gfx11
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V4_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_NORTN_V3_V4_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V1_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V1_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V1_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V1_gfx90a
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V1_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V1_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V2_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V2_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V2_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V2_gfx90a
    UINT64_C(4030464002), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V2_nsa_gfx10
    UINT64_C(4029153281), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V2_nsa_gfx11
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V2_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V2_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V3_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V3_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V3_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V3_gfx90a
    UINT64_C(4030464002), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V3_nsa_gfx10
    UINT64_C(4029153281), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V3_nsa_gfx11
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V3_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V3_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V4_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V4_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V4_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V4_gfx90a
    UINT64_C(4030464002), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V4_nsa_gfx10
    UINT64_C(4029153281), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V4_nsa_gfx11
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V4_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V1_V4_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V1_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V1_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V1_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V1_gfx90a
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V1_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V1_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V2_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V2_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V2_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V2_gfx90a
    UINT64_C(4030464002), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V2_nsa_gfx10
    UINT64_C(4029153281), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V2_nsa_gfx11
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V2_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V2_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V3_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V3_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V3_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V3_gfx90a
    UINT64_C(4030464002), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V3_nsa_gfx10
    UINT64_C(4029153281), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V3_nsa_gfx11
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V3_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V3_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V4_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V4_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V4_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V4_gfx90a
    UINT64_C(4030464002), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V4_nsa_gfx10
    UINT64_C(4029153281), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V4_nsa_gfx11
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V4_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V2_V4_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V1_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V1_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V1_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V1_gfx90a
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V1_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V1_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V2_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V2_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V2_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V2_gfx90a
    UINT64_C(4030464002), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V2_nsa_gfx10
    UINT64_C(4029153281), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V2_nsa_gfx11
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V2_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V2_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V3_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V3_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V3_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V3_gfx90a
    UINT64_C(4030464002), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V3_nsa_gfx10
    UINT64_C(4029153281), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V3_nsa_gfx11
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V3_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V3_vi
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V4_gfx10
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V4_gfx11
    UINT64_C(3489824768), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V4_gfx12
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V4_gfx90a
    UINT64_C(4030464002), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V4_nsa_gfx10
    UINT64_C(4029153281), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V4_nsa_gfx11
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V4_si
    UINT64_C(4030726144), UINT64_C(0),	// IMAGE_ATOMIC_SWAP_V3_V4_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V1_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V1_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V1_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V1_gfx90a
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V1_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V1_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V2_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V2_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V2_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V2_gfx90a
    UINT64_C(4032561154), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V2_nsa_gfx10
    UINT64_C(4030988289), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V2_nsa_gfx11
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V2_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V2_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V3_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V3_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V3_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V3_gfx90a
    UINT64_C(4032561154), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V3_nsa_gfx10
    UINT64_C(4030988289), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V3_nsa_gfx11
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V3_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V3_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V4_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V4_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V4_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V4_gfx90a
    UINT64_C(4032561154), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V4_nsa_gfx10
    UINT64_C(4030988289), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V4_nsa_gfx11
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V4_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V1_V4_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V1_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V1_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V1_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V1_gfx90a
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V1_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V1_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V2_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V2_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V2_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V2_gfx90a
    UINT64_C(4032561154), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V2_nsa_gfx10
    UINT64_C(4030988289), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V2_nsa_gfx11
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V2_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V2_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V3_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V3_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V3_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V3_gfx90a
    UINT64_C(4032561154), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V3_nsa_gfx10
    UINT64_C(4030988289), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V3_nsa_gfx11
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V3_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V3_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V4_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V4_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V4_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V4_gfx90a
    UINT64_C(4032561154), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V4_nsa_gfx10
    UINT64_C(4030988289), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V4_nsa_gfx11
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V4_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V2_V4_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V1_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V1_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V1_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V1_gfx90a
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V1_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V1_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V2_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V2_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V2_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V2_gfx90a
    UINT64_C(4032561154), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V2_nsa_gfx10
    UINT64_C(4030988289), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V2_nsa_gfx11
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V2_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V2_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V3_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V3_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V3_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V3_gfx90a
    UINT64_C(4032561154), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V3_nsa_gfx10
    UINT64_C(4030988289), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V3_nsa_gfx11
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V3_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V3_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V4_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V4_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V4_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V4_gfx90a
    UINT64_C(4032561154), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V4_nsa_gfx10
    UINT64_C(4030988289), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V4_nsa_gfx11
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V4_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_NORTN_V3_V4_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V1_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V1_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V1_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V1_gfx90a
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V1_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V1_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V2_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V2_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V2_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V2_gfx90a
    UINT64_C(4032561154), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V2_nsa_gfx10
    UINT64_C(4030988289), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V2_nsa_gfx11
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V2_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V2_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V3_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V3_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V3_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V3_gfx90a
    UINT64_C(4032561154), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V3_nsa_gfx10
    UINT64_C(4030988289), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V3_nsa_gfx11
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V3_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V3_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V4_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V4_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V4_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V4_gfx90a
    UINT64_C(4032561154), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V4_nsa_gfx10
    UINT64_C(4030988289), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V4_nsa_gfx11
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V4_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V1_V4_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V1_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V1_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V1_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V1_gfx90a
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V1_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V1_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V2_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V2_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V2_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V2_gfx90a
    UINT64_C(4032561154), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V2_nsa_gfx10
    UINT64_C(4030988289), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V2_nsa_gfx11
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V2_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V2_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V3_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V3_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V3_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V3_gfx90a
    UINT64_C(4032561154), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V3_nsa_gfx10
    UINT64_C(4030988289), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V3_nsa_gfx11
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V3_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V3_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V4_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V4_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V4_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V4_gfx90a
    UINT64_C(4032561154), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V4_nsa_gfx10
    UINT64_C(4030988289), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V4_nsa_gfx11
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V4_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V2_V4_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V1_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V1_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V1_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V1_gfx90a
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V1_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V1_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V2_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V2_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V2_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V2_gfx90a
    UINT64_C(4032561154), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V2_nsa_gfx10
    UINT64_C(4030988289), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V2_nsa_gfx11
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V2_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V2_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V3_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V3_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V3_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V3_gfx90a
    UINT64_C(4032561154), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V3_nsa_gfx10
    UINT64_C(4030988289), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V3_nsa_gfx11
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V3_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V3_vi
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V4_gfx10
    UINT64_C(4030988288), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V4_gfx11
    UINT64_C(3489939456), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V4_gfx12
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V4_gfx90a
    UINT64_C(4032561154), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V4_nsa_gfx10
    UINT64_C(4030988289), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V4_nsa_gfx11
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V4_si
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_ATOMIC_UMAX_V3_V4_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V1_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V1_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V1_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V1_gfx90a
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V1_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V1_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V2_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V2_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V2_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V2_gfx90a
    UINT64_C(4032036866), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V2_nsa_gfx10
    UINT64_C(4030464001), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V2_nsa_gfx11
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V2_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V2_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V3_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V3_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V3_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V3_gfx90a
    UINT64_C(4032036866), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V3_nsa_gfx10
    UINT64_C(4030464001), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V3_nsa_gfx11
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V3_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V3_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V4_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V4_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V4_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V4_gfx90a
    UINT64_C(4032036866), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V4_nsa_gfx10
    UINT64_C(4030464001), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V4_nsa_gfx11
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V4_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V1_V4_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V1_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V1_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V1_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V1_gfx90a
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V1_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V1_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V2_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V2_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V2_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V2_gfx90a
    UINT64_C(4032036866), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V2_nsa_gfx10
    UINT64_C(4030464001), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V2_nsa_gfx11
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V2_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V2_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V3_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V3_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V3_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V3_gfx90a
    UINT64_C(4032036866), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V3_nsa_gfx10
    UINT64_C(4030464001), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V3_nsa_gfx11
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V3_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V3_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V4_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V4_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V4_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V4_gfx90a
    UINT64_C(4032036866), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V4_nsa_gfx10
    UINT64_C(4030464001), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V4_nsa_gfx11
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V4_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V2_V4_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V1_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V1_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V1_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V1_gfx90a
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V1_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V1_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V2_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V2_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V2_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V2_gfx90a
    UINT64_C(4032036866), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V2_nsa_gfx10
    UINT64_C(4030464001), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V2_nsa_gfx11
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V2_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V2_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V3_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V3_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V3_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V3_gfx90a
    UINT64_C(4032036866), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V3_nsa_gfx10
    UINT64_C(4030464001), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V3_nsa_gfx11
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V3_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V3_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V4_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V4_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V4_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V4_gfx90a
    UINT64_C(4032036866), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V4_nsa_gfx10
    UINT64_C(4030464001), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V4_nsa_gfx11
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V4_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_NORTN_V3_V4_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V1_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V1_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V1_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V1_gfx90a
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V1_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V1_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V2_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V2_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V2_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V2_gfx90a
    UINT64_C(4032036866), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V2_nsa_gfx10
    UINT64_C(4030464001), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V2_nsa_gfx11
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V2_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V2_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V3_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V3_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V3_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V3_gfx90a
    UINT64_C(4032036866), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V3_nsa_gfx10
    UINT64_C(4030464001), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V3_nsa_gfx11
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V3_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V3_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V4_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V4_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V4_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V4_gfx90a
    UINT64_C(4032036866), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V4_nsa_gfx10
    UINT64_C(4030464001), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V4_nsa_gfx11
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V4_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V1_V4_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V1_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V1_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V1_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V1_gfx90a
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V1_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V1_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V2_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V2_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V2_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V2_gfx90a
    UINT64_C(4032036866), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V2_nsa_gfx10
    UINT64_C(4030464001), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V2_nsa_gfx11
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V2_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V2_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V3_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V3_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V3_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V3_gfx90a
    UINT64_C(4032036866), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V3_nsa_gfx10
    UINT64_C(4030464001), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V3_nsa_gfx11
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V3_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V3_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V4_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V4_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V4_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V4_gfx90a
    UINT64_C(4032036866), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V4_nsa_gfx10
    UINT64_C(4030464001), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V4_nsa_gfx11
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V4_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V2_V4_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V1_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V1_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V1_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V1_gfx90a
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V1_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V1_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V2_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V2_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V2_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V2_gfx90a
    UINT64_C(4032036866), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V2_nsa_gfx10
    UINT64_C(4030464001), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V2_nsa_gfx11
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V2_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V2_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V3_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V3_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V3_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V3_gfx90a
    UINT64_C(4032036866), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V3_nsa_gfx10
    UINT64_C(4030464001), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V3_nsa_gfx11
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V3_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V3_vi
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V4_gfx10
    UINT64_C(4030464000), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V4_gfx11
    UINT64_C(3489906688), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V4_gfx12
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V4_gfx90a
    UINT64_C(4032036866), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V4_nsa_gfx10
    UINT64_C(4030464001), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V4_nsa_gfx11
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V4_si
    UINT64_C(4032036864), UINT64_C(0),	// IMAGE_ATOMIC_UMIN_V3_V4_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V1_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V1_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V1_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V1_gfx90a
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V1_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V1_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V2_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V2_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V2_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V2_gfx90a
    UINT64_C(4033347586), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V2_nsa_gfx10
    UINT64_C(4031774721), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V2_nsa_gfx11
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V2_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V2_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V3_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V3_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V3_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V3_gfx90a
    UINT64_C(4033347586), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V3_nsa_gfx10
    UINT64_C(4031774721), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V3_nsa_gfx11
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V3_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V3_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V4_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V4_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V4_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V4_gfx90a
    UINT64_C(4033347586), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V4_nsa_gfx10
    UINT64_C(4031774721), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V4_nsa_gfx11
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V4_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V1_V4_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V1_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V1_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V1_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V1_gfx90a
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V1_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V1_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V2_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V2_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V2_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V2_gfx90a
    UINT64_C(4033347586), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V2_nsa_gfx10
    UINT64_C(4031774721), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V2_nsa_gfx11
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V2_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V2_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V3_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V3_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V3_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V3_gfx90a
    UINT64_C(4033347586), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V3_nsa_gfx10
    UINT64_C(4031774721), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V3_nsa_gfx11
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V3_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V3_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V4_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V4_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V4_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V4_gfx90a
    UINT64_C(4033347586), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V4_nsa_gfx10
    UINT64_C(4031774721), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V4_nsa_gfx11
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V4_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V2_V4_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V1_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V1_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V1_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V1_gfx90a
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V1_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V1_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V2_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V2_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V2_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V2_gfx90a
    UINT64_C(4033347586), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V2_nsa_gfx10
    UINT64_C(4031774721), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V2_nsa_gfx11
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V2_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V2_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V3_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V3_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V3_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V3_gfx90a
    UINT64_C(4033347586), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V3_nsa_gfx10
    UINT64_C(4031774721), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V3_nsa_gfx11
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V3_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V3_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V4_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V4_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V4_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V4_gfx90a
    UINT64_C(4033347586), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V4_nsa_gfx10
    UINT64_C(4031774721), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V4_nsa_gfx11
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V4_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_NORTN_V3_V4_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V1_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V1_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V1_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V1_gfx90a
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V1_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V1_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V2_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V2_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V2_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V2_gfx90a
    UINT64_C(4033347586), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V2_nsa_gfx10
    UINT64_C(4031774721), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V2_nsa_gfx11
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V2_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V2_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V3_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V3_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V3_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V3_gfx90a
    UINT64_C(4033347586), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V3_nsa_gfx10
    UINT64_C(4031774721), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V3_nsa_gfx11
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V3_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V3_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V4_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V4_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V4_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V4_gfx90a
    UINT64_C(4033347586), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V4_nsa_gfx10
    UINT64_C(4031774721), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V4_nsa_gfx11
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V4_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V1_V4_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V1_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V1_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V1_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V1_gfx90a
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V1_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V1_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V2_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V2_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V2_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V2_gfx90a
    UINT64_C(4033347586), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V2_nsa_gfx10
    UINT64_C(4031774721), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V2_nsa_gfx11
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V2_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V2_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V3_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V3_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V3_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V3_gfx90a
    UINT64_C(4033347586), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V3_nsa_gfx10
    UINT64_C(4031774721), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V3_nsa_gfx11
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V3_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V3_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V4_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V4_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V4_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V4_gfx90a
    UINT64_C(4033347586), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V4_nsa_gfx10
    UINT64_C(4031774721), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V4_nsa_gfx11
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V4_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V2_V4_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V1_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V1_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V1_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V1_gfx90a
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V1_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V1_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V2_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V2_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V2_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V2_gfx90a
    UINT64_C(4033347586), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V2_nsa_gfx10
    UINT64_C(4031774721), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V2_nsa_gfx11
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V2_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V2_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V3_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V3_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V3_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V3_gfx90a
    UINT64_C(4033347586), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V3_nsa_gfx10
    UINT64_C(4031774721), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V3_nsa_gfx11
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V3_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V3_vi
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V4_gfx10
    UINT64_C(4031774720), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V4_gfx11
    UINT64_C(3489988608), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V4_gfx12
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V4_gfx90a
    UINT64_C(4033347586), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V4_nsa_gfx10
    UINT64_C(4031774721), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V4_nsa_gfx11
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V4_si
    UINT64_C(4033347584), UINT64_C(0),	// IMAGE_ATOMIC_XOR_V3_V4_vi
    UINT64_C(3553001552), UINT64_C(0),	// IMAGE_BVH64_INTERSECT_RAY_a16_gfx12
    UINT64_C(4611686022480961285), UINT64_C(0),	// IMAGE_BVH64_INTERSECT_RAY_a16_nsa_gfx10
    UINT64_C(4033449857), UINT64_C(0),	// IMAGE_BVH64_INTERSECT_RAY_a16_nsa_gfx11
    UINT64_C(4611686022480961281), UINT64_C(0),	// IMAGE_BVH64_INTERSECT_RAY_a16_sa_gfx10
    UINT64_C(4033449856), UINT64_C(0),	// IMAGE_BVH64_INTERSECT_RAY_a16_sa_gfx11
    UINT64_C(3553001488), UINT64_C(0),	// IMAGE_BVH64_INTERSECT_RAY_gfx12
    UINT64_C(4053573383), UINT64_C(0),	// IMAGE_BVH64_INTERSECT_RAY_nsa_gfx10
    UINT64_C(4033384321), UINT64_C(0),	// IMAGE_BVH64_INTERSECT_RAY_nsa_gfx11
    UINT64_C(4053573377), UINT64_C(0),	// IMAGE_BVH64_INTERSECT_RAY_sa_gfx10
    UINT64_C(4033384320), UINT64_C(0),	// IMAGE_BVH64_INTERSECT_RAY_sa_gfx11
    UINT64_C(3554689040), UINT64_C(0),	// IMAGE_BVH8_INTERSECT_RAY_gfx12
    UINT64_C(3554672656), UINT64_C(0),	// IMAGE_BVH_DUAL_INTERSECT_RAY_gfx12
    UINT64_C(3552985168), UINT64_C(0),	// IMAGE_BVH_INTERSECT_RAY_a16_gfx12
    UINT64_C(4611686022480699141), UINT64_C(0),	// IMAGE_BVH_INTERSECT_RAY_a16_nsa_gfx10
    UINT64_C(4033187713), UINT64_C(0),	// IMAGE_BVH_INTERSECT_RAY_a16_nsa_gfx11
    UINT64_C(4611686022480699137), UINT64_C(0),	// IMAGE_BVH_INTERSECT_RAY_a16_sa_gfx10
    UINT64_C(4033187712), UINT64_C(0),	// IMAGE_BVH_INTERSECT_RAY_a16_sa_gfx11
    UINT64_C(3552985104), UINT64_C(0),	// IMAGE_BVH_INTERSECT_RAY_gfx12
    UINT64_C(4053311239), UINT64_C(0),	// IMAGE_BVH_INTERSECT_RAY_nsa_gfx10
    UINT64_C(4033122177), UINT64_C(0),	// IMAGE_BVH_INTERSECT_RAY_nsa_gfx11
    UINT64_C(4053311233), UINT64_C(0),	// IMAGE_BVH_INTERSECT_RAY_sa_gfx10
    UINT64_C(4033122176), UINT64_C(0),	// IMAGE_BVH_INTERSECT_RAY_sa_gfx11
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_GATHER4H_V2_V1
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4H_V2_V1_gfx10
    UINT64_C(4064280576), UINT64_C(0),	// IMAGE_GATHER4H_V2_V1_gfx11
    UINT64_C(3827564544), UINT64_C(0),	// IMAGE_GATHER4H_V2_V1_gfx12
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_GATHER4H_V2_V2
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4H_V2_V2_gfx10
    UINT64_C(4064280576), UINT64_C(0),	// IMAGE_GATHER4H_V2_V2_gfx11
    UINT64_C(3827564544), UINT64_C(0),	// IMAGE_GATHER4H_V2_V2_gfx12
    UINT64_C(4051959810), UINT64_C(0),	// IMAGE_GATHER4H_V2_V2_nsa_gfx10
    UINT64_C(4064280577), UINT64_C(0),	// IMAGE_GATHER4H_V2_V2_nsa_gfx11
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_GATHER4H_V2_V3
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4H_V2_V3_gfx10
    UINT64_C(4064280576), UINT64_C(0),	// IMAGE_GATHER4H_V2_V3_gfx11
    UINT64_C(3827564544), UINT64_C(0),	// IMAGE_GATHER4H_V2_V3_gfx12
    UINT64_C(4051959810), UINT64_C(0),	// IMAGE_GATHER4H_V2_V3_nsa_gfx10
    UINT64_C(4064280577), UINT64_C(0),	// IMAGE_GATHER4H_V2_V3_nsa_gfx11
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_GATHER4H_V2_V4
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4H_V2_V4_gfx10
    UINT64_C(4064280576), UINT64_C(0),	// IMAGE_GATHER4H_V2_V4_gfx11
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_GATHER4H_V4_V1
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4H_V4_V1_gfx10
    UINT64_C(4064280576), UINT64_C(0),	// IMAGE_GATHER4H_V4_V1_gfx11
    UINT64_C(3827564544), UINT64_C(0),	// IMAGE_GATHER4H_V4_V1_gfx12
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_GATHER4H_V4_V2
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4H_V4_V2_gfx10
    UINT64_C(4064280576), UINT64_C(0),	// IMAGE_GATHER4H_V4_V2_gfx11
    UINT64_C(3827564544), UINT64_C(0),	// IMAGE_GATHER4H_V4_V2_gfx12
    UINT64_C(4051959810), UINT64_C(0),	// IMAGE_GATHER4H_V4_V2_nsa_gfx10
    UINT64_C(4064280577), UINT64_C(0),	// IMAGE_GATHER4H_V4_V2_nsa_gfx11
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_GATHER4H_V4_V3
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4H_V4_V3_gfx10
    UINT64_C(4064280576), UINT64_C(0),	// IMAGE_GATHER4H_V4_V3_gfx11
    UINT64_C(3827564544), UINT64_C(0),	// IMAGE_GATHER4H_V4_V3_gfx12
    UINT64_C(4051959810), UINT64_C(0),	// IMAGE_GATHER4H_V4_V3_nsa_gfx10
    UINT64_C(4064280577), UINT64_C(0),	// IMAGE_GATHER4H_V4_V3_nsa_gfx11
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_GATHER4H_V4_V4
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4H_V4_V4_gfx10
    UINT64_C(4064280576), UINT64_C(0),	// IMAGE_GATHER4H_V4_V4_gfx11
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_GATHER4H_V5_V1
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4H_V5_V1_gfx10
    UINT64_C(4064280576), UINT64_C(0),	// IMAGE_GATHER4H_V5_V1_gfx11
    UINT64_C(3827564544), UINT64_C(0),	// IMAGE_GATHER4H_V5_V1_gfx12
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_GATHER4H_V5_V2
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4H_V5_V2_gfx10
    UINT64_C(4064280576), UINT64_C(0),	// IMAGE_GATHER4H_V5_V2_gfx11
    UINT64_C(3827564544), UINT64_C(0),	// IMAGE_GATHER4H_V5_V2_gfx12
    UINT64_C(4051959810), UINT64_C(0),	// IMAGE_GATHER4H_V5_V2_nsa_gfx10
    UINT64_C(4064280577), UINT64_C(0),	// IMAGE_GATHER4H_V5_V2_nsa_gfx11
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_GATHER4H_V5_V3
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4H_V5_V3_gfx10
    UINT64_C(4064280576), UINT64_C(0),	// IMAGE_GATHER4H_V5_V3_gfx11
    UINT64_C(3827564544), UINT64_C(0),	// IMAGE_GATHER4H_V5_V3_gfx12
    UINT64_C(4051959810), UINT64_C(0),	// IMAGE_GATHER4H_V5_V3_nsa_gfx10
    UINT64_C(4064280577), UINT64_C(0),	// IMAGE_GATHER4H_V5_V3_nsa_gfx11
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_GATHER4H_V5_V4
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4H_V5_V4_gfx10
    UINT64_C(4064280576), UINT64_C(0),	// IMAGE_GATHER4H_V5_V4_gfx11
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V2_V3
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V2_V3_gfx10
    UINT64_C(4049076226), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V2_V3_nsa_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V2_V4
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V2_V4_gfx10
    UINT64_C(4049076226), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V2_V4_nsa_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V2_V5
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V2_V5_gfx10
    UINT64_C(4049076226), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V2_V5_nsa_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V2_V6
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V2_V6_gfx10
    UINT64_C(4049076228), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V2_V6_nsa_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V2_V8
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V2_V8_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V4_V3
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V4_V3_gfx10
    UINT64_C(4049076226), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V4_V3_nsa_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V4_V4
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V4_V4_gfx10
    UINT64_C(4049076226), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V4_V4_nsa_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V4_V5
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V4_V5_gfx10
    UINT64_C(4049076226), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V4_V5_nsa_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V4_V6
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V4_V6_gfx10
    UINT64_C(4049076228), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V4_V6_nsa_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V4_V8
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V4_V8_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V5_V3
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V5_V3_gfx10
    UINT64_C(4049076226), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V5_V3_nsa_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V5_V4
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V5_V4_gfx10
    UINT64_C(4049076226), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V5_V4_nsa_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V5_V5
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V5_V5_gfx10
    UINT64_C(4049076226), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V5_V5_nsa_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V5_V6
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V5_V6_gfx10
    UINT64_C(4049076228), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V5_V6_nsa_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V5_V8
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_GATHER4_B_CL_O_V5_V8_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V2
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V2_gfx10
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V2_gfx11
    UINT64_C(3826794496), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V2_gfx12
    UINT64_C(4044881922), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V2_nsa_gfx10
    UINT64_C(4051959809), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V2_nsa_gfx11
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V3
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V3_gfx10
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V3_gfx11
    UINT64_C(3826794496), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V3_gfx12
    UINT64_C(4044881922), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V3_nsa_gfx10
    UINT64_C(4051959809), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V3_nsa_gfx11
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V4
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V4_gfx10
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V4_gfx11
    UINT64_C(3826794496), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V4_gfx12
    UINT64_C(4044881922), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V4_nsa_gfx10
    UINT64_C(4051959809), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V4_nsa_gfx11
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V5
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V5_gfx10
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V5_gfx11
    UINT64_C(3826794496), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V5_gfx12
    UINT64_C(4044881922), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V5_nsa_gfx10
    UINT64_C(4051959809), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V5_nsa_gfx11
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V8
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V8_gfx10
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V2_V8_gfx11
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V2
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V2_gfx10
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V2_gfx11
    UINT64_C(3826794496), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V2_gfx12
    UINT64_C(4044881922), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V2_nsa_gfx10
    UINT64_C(4051959809), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V2_nsa_gfx11
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V3
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V3_gfx10
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V3_gfx11
    UINT64_C(3826794496), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V3_gfx12
    UINT64_C(4044881922), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V3_nsa_gfx10
    UINT64_C(4051959809), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V3_nsa_gfx11
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V4
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V4_gfx10
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V4_gfx11
    UINT64_C(3826794496), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V4_gfx12
    UINT64_C(4044881922), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V4_nsa_gfx10
    UINT64_C(4051959809), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V4_nsa_gfx11
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V5
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V5_gfx10
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V5_gfx11
    UINT64_C(3826794496), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V5_gfx12
    UINT64_C(4044881922), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V5_nsa_gfx10
    UINT64_C(4051959809), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V5_nsa_gfx11
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V8
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V8_gfx10
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V4_V8_gfx11
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V2
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V2_gfx10
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V2_gfx11
    UINT64_C(3826794496), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V2_gfx12
    UINT64_C(4044881922), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V2_nsa_gfx10
    UINT64_C(4051959809), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V2_nsa_gfx11
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V3
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V3_gfx10
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V3_gfx11
    UINT64_C(3826794496), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V3_gfx12
    UINT64_C(4044881922), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V3_nsa_gfx10
    UINT64_C(4051959809), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V3_nsa_gfx11
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V4
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V4_gfx10
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V4_gfx11
    UINT64_C(3826794496), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V4_gfx12
    UINT64_C(4044881922), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V4_nsa_gfx10
    UINT64_C(4051959809), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V4_nsa_gfx11
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V5
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V5_gfx10
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V5_gfx11
    UINT64_C(3826794496), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V5_gfx12
    UINT64_C(4044881922), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V5_nsa_gfx10
    UINT64_C(4051959809), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V5_nsa_gfx11
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V8
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V8_gfx10
    UINT64_C(4051959808), UINT64_C(0),	// IMAGE_GATHER4_B_CL_V5_V8_gfx11
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V2_V3
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V2_V3_gfx10
    UINT64_C(4048814082), UINT64_C(0),	// IMAGE_GATHER4_B_O_V2_V3_nsa_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V2_V4
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V2_V4_gfx10
    UINT64_C(4048814082), UINT64_C(0),	// IMAGE_GATHER4_B_O_V2_V4_nsa_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V2_V5
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V2_V5_gfx10
    UINT64_C(4048814082), UINT64_C(0),	// IMAGE_GATHER4_B_O_V2_V5_nsa_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V2_V8
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V2_V8_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V4_V3
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V4_V3_gfx10
    UINT64_C(4048814082), UINT64_C(0),	// IMAGE_GATHER4_B_O_V4_V3_nsa_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V4_V4
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V4_V4_gfx10
    UINT64_C(4048814082), UINT64_C(0),	// IMAGE_GATHER4_B_O_V4_V4_nsa_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V4_V5
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V4_V5_gfx10
    UINT64_C(4048814082), UINT64_C(0),	// IMAGE_GATHER4_B_O_V4_V5_nsa_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V4_V8
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V4_V8_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V5_V3
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V5_V3_gfx10
    UINT64_C(4048814082), UINT64_C(0),	// IMAGE_GATHER4_B_O_V5_V3_nsa_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V5_V4
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V5_V4_gfx10
    UINT64_C(4048814082), UINT64_C(0),	// IMAGE_GATHER4_B_O_V5_V4_nsa_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V5_V5
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V5_V5_gfx10
    UINT64_C(4048814082), UINT64_C(0),	// IMAGE_GATHER4_B_O_V5_V5_nsa_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V5_V8
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_GATHER4_B_O_V5_V8_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_GATHER4_B_V2_V2
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_GATHER4_B_V2_V2_gfx10
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_GATHER4_B_V2_V2_gfx11
    UINT64_C(3826008064), UINT64_C(0),	// IMAGE_GATHER4_B_V2_V2_gfx12
    UINT64_C(4044619778), UINT64_C(0),	// IMAGE_GATHER4_B_V2_V2_nsa_gfx10
    UINT64_C(4039376897), UINT64_C(0),	// IMAGE_GATHER4_B_V2_V2_nsa_gfx11
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_GATHER4_B_V2_V3
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_GATHER4_B_V2_V3_gfx10
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_GATHER4_B_V2_V3_gfx11
    UINT64_C(3826008064), UINT64_C(0),	// IMAGE_GATHER4_B_V2_V3_gfx12
    UINT64_C(4044619778), UINT64_C(0),	// IMAGE_GATHER4_B_V2_V3_nsa_gfx10
    UINT64_C(4039376897), UINT64_C(0),	// IMAGE_GATHER4_B_V2_V3_nsa_gfx11
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_GATHER4_B_V2_V4
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_GATHER4_B_V2_V4_gfx10
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_GATHER4_B_V2_V4_gfx11
    UINT64_C(3826008064), UINT64_C(0),	// IMAGE_GATHER4_B_V2_V4_gfx12
    UINT64_C(4044619778), UINT64_C(0),	// IMAGE_GATHER4_B_V2_V4_nsa_gfx10
    UINT64_C(4039376897), UINT64_C(0),	// IMAGE_GATHER4_B_V2_V4_nsa_gfx11
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_GATHER4_B_V4_V2
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_GATHER4_B_V4_V2_gfx10
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_GATHER4_B_V4_V2_gfx11
    UINT64_C(3826008064), UINT64_C(0),	// IMAGE_GATHER4_B_V4_V2_gfx12
    UINT64_C(4044619778), UINT64_C(0),	// IMAGE_GATHER4_B_V4_V2_nsa_gfx10
    UINT64_C(4039376897), UINT64_C(0),	// IMAGE_GATHER4_B_V4_V2_nsa_gfx11
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_GATHER4_B_V4_V3
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_GATHER4_B_V4_V3_gfx10
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_GATHER4_B_V4_V3_gfx11
    UINT64_C(3826008064), UINT64_C(0),	// IMAGE_GATHER4_B_V4_V3_gfx12
    UINT64_C(4044619778), UINT64_C(0),	// IMAGE_GATHER4_B_V4_V3_nsa_gfx10
    UINT64_C(4039376897), UINT64_C(0),	// IMAGE_GATHER4_B_V4_V3_nsa_gfx11
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_GATHER4_B_V4_V4
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_GATHER4_B_V4_V4_gfx10
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_GATHER4_B_V4_V4_gfx11
    UINT64_C(3826008064), UINT64_C(0),	// IMAGE_GATHER4_B_V4_V4_gfx12
    UINT64_C(4044619778), UINT64_C(0),	// IMAGE_GATHER4_B_V4_V4_nsa_gfx10
    UINT64_C(4039376897), UINT64_C(0),	// IMAGE_GATHER4_B_V4_V4_nsa_gfx11
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_GATHER4_B_V5_V2
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_GATHER4_B_V5_V2_gfx10
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_GATHER4_B_V5_V2_gfx11
    UINT64_C(3826008064), UINT64_C(0),	// IMAGE_GATHER4_B_V5_V2_gfx12
    UINT64_C(4044619778), UINT64_C(0),	// IMAGE_GATHER4_B_V5_V2_nsa_gfx10
    UINT64_C(4039376897), UINT64_C(0),	// IMAGE_GATHER4_B_V5_V2_nsa_gfx11
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_GATHER4_B_V5_V3
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_GATHER4_B_V5_V3_gfx10
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_GATHER4_B_V5_V3_gfx11
    UINT64_C(3826008064), UINT64_C(0),	// IMAGE_GATHER4_B_V5_V3_gfx12
    UINT64_C(4044619778), UINT64_C(0),	// IMAGE_GATHER4_B_V5_V3_nsa_gfx10
    UINT64_C(4039376897), UINT64_C(0),	// IMAGE_GATHER4_B_V5_V3_nsa_gfx11
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_GATHER4_B_V5_V4
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_GATHER4_B_V5_V4_gfx10
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_GATHER4_B_V5_V4_gfx11
    UINT64_C(3826008064), UINT64_C(0),	// IMAGE_GATHER4_B_V5_V4_gfx12
    UINT64_C(4044619778), UINT64_C(0),	// IMAGE_GATHER4_B_V5_V4_nsa_gfx10
    UINT64_C(4039376897), UINT64_C(0),	// IMAGE_GATHER4_B_V5_V4_nsa_gfx11
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V2_V2
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V2_V2_gfx10
    UINT64_C(4047765506), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V2_V2_nsa_gfx10
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V2_V3
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V2_V3_gfx10
    UINT64_C(4047765506), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V2_V3_nsa_gfx10
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V2_V4
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V2_V4_gfx10
    UINT64_C(4047765506), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V2_V4_nsa_gfx10
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V2_V5
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V2_V5_gfx10
    UINT64_C(4047765506), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V2_V5_nsa_gfx10
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V2_V8
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V2_V8_gfx10
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V4_V2
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V4_V2_gfx10
    UINT64_C(4047765506), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V4_V2_nsa_gfx10
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V4_V3
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V4_V3_gfx10
    UINT64_C(4047765506), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V4_V3_nsa_gfx10
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V4_V4
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V4_V4_gfx10
    UINT64_C(4047765506), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V4_V4_nsa_gfx10
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V4_V5
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V4_V5_gfx10
    UINT64_C(4047765506), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V4_V5_nsa_gfx10
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V4_V8
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V4_V8_gfx10
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V5_V2
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V5_V2_gfx10
    UINT64_C(4047765506), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V5_V2_nsa_gfx10
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V5_V3
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V5_V3_gfx10
    UINT64_C(4047765506), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V5_V3_nsa_gfx10
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V5_V4
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V5_V4_gfx10
    UINT64_C(4047765506), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V5_V4_nsa_gfx10
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V5_V5
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V5_V5_gfx10
    UINT64_C(4047765506), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V5_V5_nsa_gfx10
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V5_V8
    UINT64_C(4047765504), UINT64_C(0),	// IMAGE_GATHER4_CL_O_V5_V8_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V1
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V1_gfx10
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V1_gfx11
    UINT64_C(3826778112), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V1_gfx12
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V2
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V2_gfx10
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V2_gfx11
    UINT64_C(3826778112), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V2_gfx12
    UINT64_C(4043571202), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V2_nsa_gfx10
    UINT64_C(4051697665), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V2_nsa_gfx11
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V3
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V3_gfx10
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V3_gfx11
    UINT64_C(3826778112), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V3_gfx12
    UINT64_C(4043571202), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V3_nsa_gfx10
    UINT64_C(4051697665), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V3_nsa_gfx11
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V4
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V4_gfx10
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V4_gfx11
    UINT64_C(3826778112), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V4_gfx12
    UINT64_C(4043571202), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V4_nsa_gfx10
    UINT64_C(4051697665), UINT64_C(0),	// IMAGE_GATHER4_CL_V2_V4_nsa_gfx11
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V1
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V1_gfx10
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V1_gfx11
    UINT64_C(3826778112), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V1_gfx12
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V2
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V2_gfx10
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V2_gfx11
    UINT64_C(3826778112), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V2_gfx12
    UINT64_C(4043571202), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V2_nsa_gfx10
    UINT64_C(4051697665), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V2_nsa_gfx11
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V3
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V3_gfx10
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V3_gfx11
    UINT64_C(3826778112), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V3_gfx12
    UINT64_C(4043571202), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V3_nsa_gfx10
    UINT64_C(4051697665), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V3_nsa_gfx11
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V4
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V4_gfx10
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V4_gfx11
    UINT64_C(3826778112), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V4_gfx12
    UINT64_C(4043571202), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V4_nsa_gfx10
    UINT64_C(4051697665), UINT64_C(0),	// IMAGE_GATHER4_CL_V4_V4_nsa_gfx11
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V1
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V1_gfx10
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V1_gfx11
    UINT64_C(3826778112), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V1_gfx12
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V2
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V2_gfx10
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V2_gfx11
    UINT64_C(3826778112), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V2_gfx12
    UINT64_C(4043571202), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V2_nsa_gfx10
    UINT64_C(4051697665), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V2_nsa_gfx11
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V3
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V3_gfx10
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V3_gfx11
    UINT64_C(3826778112), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V3_gfx12
    UINT64_C(4043571202), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V3_nsa_gfx10
    UINT64_C(4051697665), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V3_nsa_gfx11
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V4
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V4_gfx10
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V4_gfx11
    UINT64_C(3826778112), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V4_gfx12
    UINT64_C(4043571202), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V4_nsa_gfx10
    UINT64_C(4051697665), UINT64_C(0),	// IMAGE_GATHER4_CL_V5_V4_nsa_gfx11
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V2_V4
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V2_V4_gfx10
    UINT64_C(4051173378), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V2_V4_nsa_gfx10
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V2_V5
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V2_V5_gfx10
    UINT64_C(4051173378), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V2_V5_nsa_gfx10
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V2_V6
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V2_V6_gfx10
    UINT64_C(4051173380), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V2_V6_nsa_gfx10
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V2_V7
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V2_V7_gfx10
    UINT64_C(4051173380), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V2_V7_nsa_gfx10
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V2_V8
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V2_V8_gfx10
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V4_V4
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V4_V4_gfx10
    UINT64_C(4051173378), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V4_V4_nsa_gfx10
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V4_V5
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V4_V5_gfx10
    UINT64_C(4051173378), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V4_V5_nsa_gfx10
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V4_V6
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V4_V6_gfx10
    UINT64_C(4051173380), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V4_V6_nsa_gfx10
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V4_V7
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V4_V7_gfx10
    UINT64_C(4051173380), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V4_V7_nsa_gfx10
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V4_V8
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V4_V8_gfx10
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V5_V4
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V5_V4_gfx10
    UINT64_C(4051173378), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V5_V4_nsa_gfx10
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V5_V5
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V5_V5_gfx10
    UINT64_C(4051173378), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V5_V5_nsa_gfx10
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V5_V6
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V5_V6_gfx10
    UINT64_C(4051173380), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V5_V6_nsa_gfx10
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V5_V7
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V5_V7_gfx10
    UINT64_C(4051173380), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V5_V7_nsa_gfx10
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V5_V8
    UINT64_C(4051173376), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_O_V5_V8_gfx10
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V3
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V3_gfx10
    UINT64_C(4053008384), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V3_gfx11
    UINT64_C(3826860032), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V3_gfx12
    UINT64_C(4046979074), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V3_nsa_gfx10
    UINT64_C(4053008385), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V3_nsa_gfx11
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V4
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V4_gfx10
    UINT64_C(4053008384), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V4_gfx11
    UINT64_C(3826860032), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V4_gfx12
    UINT64_C(4046979074), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V4_nsa_gfx10
    UINT64_C(4053008385), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V4_nsa_gfx11
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V5
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V5_gfx10
    UINT64_C(4053008384), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V5_gfx11
    UINT64_C(3826860032), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V5_gfx12
    UINT64_C(4046979074), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V5_nsa_gfx10
    UINT64_C(4053008385), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V5_nsa_gfx11
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V6
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V6_gfx10
    UINT64_C(4053008384), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V6_gfx11
    UINT64_C(3826860032), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V6_gfx12
    UINT64_C(4046979076), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V6_nsa_gfx10
    UINT64_C(4053008385), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V6_nsa_gfx11
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V8
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V8_gfx10
    UINT64_C(4053008384), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V2_V8_gfx11
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V3
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V3_gfx10
    UINT64_C(4053008384), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V3_gfx11
    UINT64_C(3826860032), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V3_gfx12
    UINT64_C(4046979074), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V3_nsa_gfx10
    UINT64_C(4053008385), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V3_nsa_gfx11
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V4
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V4_gfx10
    UINT64_C(4053008384), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V4_gfx11
    UINT64_C(3826860032), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V4_gfx12
    UINT64_C(4046979074), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V4_nsa_gfx10
    UINT64_C(4053008385), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V4_nsa_gfx11
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V5
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V5_gfx10
    UINT64_C(4053008384), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V5_gfx11
    UINT64_C(3826860032), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V5_gfx12
    UINT64_C(4046979074), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V5_nsa_gfx10
    UINT64_C(4053008385), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V5_nsa_gfx11
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V6
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V6_gfx10
    UINT64_C(4053008384), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V6_gfx11
    UINT64_C(3826860032), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V6_gfx12
    UINT64_C(4046979076), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V6_nsa_gfx10
    UINT64_C(4053008385), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V6_nsa_gfx11
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V8
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V8_gfx10
    UINT64_C(4053008384), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V4_V8_gfx11
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V3
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V3_gfx10
    UINT64_C(4053008384), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V3_gfx11
    UINT64_C(3826860032), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V3_gfx12
    UINT64_C(4046979074), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V3_nsa_gfx10
    UINT64_C(4053008385), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V3_nsa_gfx11
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V4
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V4_gfx10
    UINT64_C(4053008384), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V4_gfx11
    UINT64_C(3826860032), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V4_gfx12
    UINT64_C(4046979074), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V4_nsa_gfx10
    UINT64_C(4053008385), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V4_nsa_gfx11
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V5
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V5_gfx10
    UINT64_C(4053008384), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V5_gfx11
    UINT64_C(3826860032), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V5_gfx12
    UINT64_C(4046979074), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V5_nsa_gfx10
    UINT64_C(4053008385), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V5_nsa_gfx11
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V6
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V6_gfx10
    UINT64_C(4053008384), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V6_gfx11
    UINT64_C(3826860032), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V6_gfx12
    UINT64_C(4046979076), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V6_nsa_gfx10
    UINT64_C(4053008385), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V6_nsa_gfx11
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V8
    UINT64_C(4046979072), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V8_gfx10
    UINT64_C(4053008384), UINT64_C(0),	// IMAGE_GATHER4_C_B_CL_V5_V8_gfx11
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V2_V4
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V2_V4_gfx10
    UINT64_C(4050911234), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V2_V4_nsa_gfx10
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V2_V5
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V2_V5_gfx10
    UINT64_C(4050911234), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V2_V5_nsa_gfx10
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V2_V6
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V2_V6_gfx10
    UINT64_C(4050911236), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V2_V6_nsa_gfx10
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V2_V8
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V2_V8_gfx10
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V4_V4
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V4_V4_gfx10
    UINT64_C(4050911234), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V4_V4_nsa_gfx10
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V4_V5
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V4_V5_gfx10
    UINT64_C(4050911234), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V4_V5_nsa_gfx10
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V4_V6
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V4_V6_gfx10
    UINT64_C(4050911236), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V4_V6_nsa_gfx10
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V4_V8
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V4_V8_gfx10
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V5_V4
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V5_V4_gfx10
    UINT64_C(4050911234), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V5_V4_nsa_gfx10
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V5_V5
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V5_V5_gfx10
    UINT64_C(4050911234), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V5_V5_nsa_gfx10
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V5_V6
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V5_V6_gfx10
    UINT64_C(4050911236), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V5_V6_nsa_gfx10
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V5_V8
    UINT64_C(4050911232), UINT64_C(0),	// IMAGE_GATHER4_C_B_O_V5_V8_gfx10
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V3
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V3_gfx10
    UINT64_C(4052746240), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V3_gfx11
    UINT64_C(3826843648), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V3_gfx12
    UINT64_C(4046716930), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V3_nsa_gfx10
    UINT64_C(4052746241), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V3_nsa_gfx11
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V4
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V4_gfx10
    UINT64_C(4052746240), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V4_gfx11
    UINT64_C(3826843648), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V4_gfx12
    UINT64_C(4046716930), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V4_nsa_gfx10
    UINT64_C(4052746241), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V4_nsa_gfx11
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V5
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V5_gfx10
    UINT64_C(4052746240), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V5_gfx11
    UINT64_C(3826843648), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V5_gfx12
    UINT64_C(4046716930), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V5_nsa_gfx10
    UINT64_C(4052746241), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V5_nsa_gfx11
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V8
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V8_gfx10
    UINT64_C(4052746240), UINT64_C(0),	// IMAGE_GATHER4_C_B_V2_V8_gfx11
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V3
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V3_gfx10
    UINT64_C(4052746240), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V3_gfx11
    UINT64_C(3826843648), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V3_gfx12
    UINT64_C(4046716930), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V3_nsa_gfx10
    UINT64_C(4052746241), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V3_nsa_gfx11
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V4
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V4_gfx10
    UINT64_C(4052746240), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V4_gfx11
    UINT64_C(3826843648), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V4_gfx12
    UINT64_C(4046716930), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V4_nsa_gfx10
    UINT64_C(4052746241), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V4_nsa_gfx11
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V5
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V5_gfx10
    UINT64_C(4052746240), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V5_gfx11
    UINT64_C(3826843648), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V5_gfx12
    UINT64_C(4046716930), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V5_nsa_gfx10
    UINT64_C(4052746241), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V5_nsa_gfx11
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V8
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V8_gfx10
    UINT64_C(4052746240), UINT64_C(0),	// IMAGE_GATHER4_C_B_V4_V8_gfx11
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V3
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V3_gfx10
    UINT64_C(4052746240), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V3_gfx11
    UINT64_C(3826843648), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V3_gfx12
    UINT64_C(4046716930), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V3_nsa_gfx10
    UINT64_C(4052746241), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V3_nsa_gfx11
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V4
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V4_gfx10
    UINT64_C(4052746240), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V4_gfx11
    UINT64_C(3826843648), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V4_gfx12
    UINT64_C(4046716930), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V4_nsa_gfx10
    UINT64_C(4052746241), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V4_nsa_gfx11
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V5
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V5_gfx10
    UINT64_C(4052746240), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V5_gfx11
    UINT64_C(3826843648), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V5_gfx12
    UINT64_C(4046716930), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V5_nsa_gfx10
    UINT64_C(4052746241), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V5_nsa_gfx11
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V8
    UINT64_C(4046716928), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V8_gfx10
    UINT64_C(4052746240), UINT64_C(0),	// IMAGE_GATHER4_C_B_V5_V8_gfx11
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V2_V3
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V2_V3_gfx10
    UINT64_C(4049862658), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V2_V3_nsa_gfx10
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V2_V4
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V2_V4_gfx10
    UINT64_C(4049862658), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V2_V4_nsa_gfx10
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V2_V5
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V2_V5_gfx10
    UINT64_C(4049862658), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V2_V5_nsa_gfx10
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V2_V6
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V2_V6_gfx10
    UINT64_C(4049862660), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V2_V6_nsa_gfx10
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V2_V8
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V2_V8_gfx10
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V4_V3
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V4_V3_gfx10
    UINT64_C(4049862658), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V4_V3_nsa_gfx10
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V4_V4
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V4_V4_gfx10
    UINT64_C(4049862658), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V4_V4_nsa_gfx10
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V4_V5
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V4_V5_gfx10
    UINT64_C(4049862658), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V4_V5_nsa_gfx10
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V4_V6
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V4_V6_gfx10
    UINT64_C(4049862660), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V4_V6_nsa_gfx10
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V4_V8
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V4_V8_gfx10
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V5_V3
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V5_V3_gfx10
    UINT64_C(4049862658), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V5_V3_nsa_gfx10
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V5_V4
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V5_V4_gfx10
    UINT64_C(4049862658), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V5_V4_nsa_gfx10
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V5_V5
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V5_V5_gfx10
    UINT64_C(4049862658), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V5_V5_nsa_gfx10
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V5_V6
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V5_V6_gfx10
    UINT64_C(4049862660), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V5_V6_nsa_gfx10
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V5_V8
    UINT64_C(4049862656), UINT64_C(0),	// IMAGE_GATHER4_C_CL_O_V5_V8_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V2
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V2_gfx10
    UINT64_C(4052221952), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V2_gfx11
    UINT64_C(3826810880), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V2_gfx12
    UINT64_C(4045668354), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V2_nsa_gfx10
    UINT64_C(4052221953), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V2_nsa_gfx11
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V3
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V3_gfx10
    UINT64_C(4052221952), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V3_gfx11
    UINT64_C(3826810880), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V3_gfx12
    UINT64_C(4045668354), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V3_nsa_gfx10
    UINT64_C(4052221953), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V3_nsa_gfx11
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V4
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V4_gfx10
    UINT64_C(4052221952), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V4_gfx11
    UINT64_C(3826810880), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V4_gfx12
    UINT64_C(4045668354), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V4_nsa_gfx10
    UINT64_C(4052221953), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V4_nsa_gfx11
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V5
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V5_gfx10
    UINT64_C(4052221952), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V5_gfx11
    UINT64_C(3826810880), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V5_gfx12
    UINT64_C(4045668354), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V5_nsa_gfx10
    UINT64_C(4052221953), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V5_nsa_gfx11
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V8
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V8_gfx10
    UINT64_C(4052221952), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V2_V8_gfx11
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V2
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V2_gfx10
    UINT64_C(4052221952), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V2_gfx11
    UINT64_C(3826810880), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V2_gfx12
    UINT64_C(4045668354), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V2_nsa_gfx10
    UINT64_C(4052221953), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V2_nsa_gfx11
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V3
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V3_gfx10
    UINT64_C(4052221952), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V3_gfx11
    UINT64_C(3826810880), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V3_gfx12
    UINT64_C(4045668354), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V3_nsa_gfx10
    UINT64_C(4052221953), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V3_nsa_gfx11
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V4
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V4_gfx10
    UINT64_C(4052221952), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V4_gfx11
    UINT64_C(3826810880), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V4_gfx12
    UINT64_C(4045668354), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V4_nsa_gfx10
    UINT64_C(4052221953), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V4_nsa_gfx11
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V5
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V5_gfx10
    UINT64_C(4052221952), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V5_gfx11
    UINT64_C(3826810880), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V5_gfx12
    UINT64_C(4045668354), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V5_nsa_gfx10
    UINT64_C(4052221953), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V5_nsa_gfx11
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V8
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V8_gfx10
    UINT64_C(4052221952), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V4_V8_gfx11
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V2
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V2_gfx10
    UINT64_C(4052221952), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V2_gfx11
    UINT64_C(3826810880), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V2_gfx12
    UINT64_C(4045668354), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V2_nsa_gfx10
    UINT64_C(4052221953), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V2_nsa_gfx11
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V3
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V3_gfx10
    UINT64_C(4052221952), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V3_gfx11
    UINT64_C(3826810880), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V3_gfx12
    UINT64_C(4045668354), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V3_nsa_gfx10
    UINT64_C(4052221953), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V3_nsa_gfx11
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V4
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V4_gfx10
    UINT64_C(4052221952), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V4_gfx11
    UINT64_C(3826810880), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V4_gfx12
    UINT64_C(4045668354), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V4_nsa_gfx10
    UINT64_C(4052221953), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V4_nsa_gfx11
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V5
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V5_gfx10
    UINT64_C(4052221952), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V5_gfx11
    UINT64_C(3826810880), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V5_gfx12
    UINT64_C(4045668354), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V5_nsa_gfx10
    UINT64_C(4052221953), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V5_nsa_gfx11
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V8
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V8_gfx10
    UINT64_C(4052221952), UINT64_C(0),	// IMAGE_GATHER4_C_CL_V5_V8_gfx11
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V3
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V3_gfx10
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V3_gfx11
    UINT64_C(3826106368), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V3_gfx12
    UINT64_C(4051435522), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V3_nsa_gfx10
    UINT64_C(4040949761), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V3_nsa_gfx11
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V4
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V4_gfx10
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V4_gfx11
    UINT64_C(3826106368), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V4_gfx12
    UINT64_C(4051435522), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V4_nsa_gfx10
    UINT64_C(4040949761), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V4_nsa_gfx11
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V5
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V5_gfx10
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V5_gfx11
    UINT64_C(3826106368), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V5_gfx12
    UINT64_C(4051435522), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V5_nsa_gfx10
    UINT64_C(4040949761), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V5_nsa_gfx11
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V8
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V8_gfx10
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V2_V8_gfx11
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V3
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V3_gfx10
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V3_gfx11
    UINT64_C(3826106368), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V3_gfx12
    UINT64_C(4051435522), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V3_nsa_gfx10
    UINT64_C(4040949761), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V3_nsa_gfx11
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V4
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V4_gfx10
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V4_gfx11
    UINT64_C(3826106368), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V4_gfx12
    UINT64_C(4051435522), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V4_nsa_gfx10
    UINT64_C(4040949761), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V4_nsa_gfx11
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V5
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V5_gfx10
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V5_gfx11
    UINT64_C(3826106368), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V5_gfx12
    UINT64_C(4051435522), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V5_nsa_gfx10
    UINT64_C(4040949761), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V5_nsa_gfx11
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V8
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V8_gfx10
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V4_V8_gfx11
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V3
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V3_gfx10
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V3_gfx11
    UINT64_C(3826106368), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V3_gfx12
    UINT64_C(4051435522), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V3_nsa_gfx10
    UINT64_C(4040949761), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V3_nsa_gfx11
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V4
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V4_gfx10
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V4_gfx11
    UINT64_C(3826106368), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V4_gfx12
    UINT64_C(4051435522), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V4_nsa_gfx10
    UINT64_C(4040949761), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V4_nsa_gfx11
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V5
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V5_gfx10
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V5_gfx11
    UINT64_C(3826106368), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V5_gfx12
    UINT64_C(4051435522), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V5_nsa_gfx10
    UINT64_C(4040949761), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V5_nsa_gfx11
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V8
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V8_gfx10
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_O_V5_V8_gfx11
    UINT64_C(4047241216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V2_V2
    UINT64_C(4047241216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V2_V2_gfx10
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V2_V2_gfx11
    UINT64_C(3826057216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V2_V2_gfx12
    UINT64_C(4047241218), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V2_V2_nsa_gfx10
    UINT64_C(4040163329), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V2_V2_nsa_gfx11
    UINT64_C(4047241216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V2_V3
    UINT64_C(4047241216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V2_V3_gfx10
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V2_V3_gfx11
    UINT64_C(3826057216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V2_V3_gfx12
    UINT64_C(4047241218), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V2_V3_nsa_gfx10
    UINT64_C(4040163329), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V2_V3_nsa_gfx11
    UINT64_C(4047241216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V2_V4
    UINT64_C(4047241216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V2_V4_gfx10
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V2_V4_gfx11
    UINT64_C(3826057216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V2_V4_gfx12
    UINT64_C(4047241218), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V2_V4_nsa_gfx10
    UINT64_C(4040163329), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V2_V4_nsa_gfx11
    UINT64_C(4047241216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V4_V2
    UINT64_C(4047241216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V4_V2_gfx10
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V4_V2_gfx11
    UINT64_C(3826057216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V4_V2_gfx12
    UINT64_C(4047241218), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V4_V2_nsa_gfx10
    UINT64_C(4040163329), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V4_V2_nsa_gfx11
    UINT64_C(4047241216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V4_V3
    UINT64_C(4047241216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V4_V3_gfx10
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V4_V3_gfx11
    UINT64_C(3826057216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V4_V3_gfx12
    UINT64_C(4047241218), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V4_V3_nsa_gfx10
    UINT64_C(4040163329), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V4_V3_nsa_gfx11
    UINT64_C(4047241216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V4_V4
    UINT64_C(4047241216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V4_V4_gfx10
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V4_V4_gfx11
    UINT64_C(3826057216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V4_V4_gfx12
    UINT64_C(4047241218), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V4_V4_nsa_gfx10
    UINT64_C(4040163329), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V4_V4_nsa_gfx11
    UINT64_C(4047241216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V5_V2
    UINT64_C(4047241216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V5_V2_gfx10
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V5_V2_gfx11
    UINT64_C(3826057216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V5_V2_gfx12
    UINT64_C(4047241218), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V5_V2_nsa_gfx10
    UINT64_C(4040163329), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V5_V2_nsa_gfx11
    UINT64_C(4047241216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V5_V3
    UINT64_C(4047241216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V5_V3_gfx10
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V5_V3_gfx11
    UINT64_C(3826057216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V5_V3_gfx12
    UINT64_C(4047241218), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V5_V3_nsa_gfx10
    UINT64_C(4040163329), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V5_V3_nsa_gfx11
    UINT64_C(4047241216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V5_V4
    UINT64_C(4047241216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V5_V4_gfx10
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V5_V4_gfx11
    UINT64_C(3826057216), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V5_V4_gfx12
    UINT64_C(4047241218), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V5_V4_nsa_gfx10
    UINT64_C(4040163329), UINT64_C(0),	// IMAGE_GATHER4_C_LZ_V5_V4_nsa_gfx11
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V2_V3
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V2_V3_gfx10
    UINT64_C(4050649090), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V2_V3_nsa_gfx10
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V2_V4
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V2_V4_gfx10
    UINT64_C(4050649090), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V2_V4_nsa_gfx10
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V2_V5
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V2_V5_gfx10
    UINT64_C(4050649090), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V2_V5_nsa_gfx10
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V2_V6
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V2_V6_gfx10
    UINT64_C(4050649092), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V2_V6_nsa_gfx10
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V2_V8
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V2_V8_gfx10
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V4_V3
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V4_V3_gfx10
    UINT64_C(4050649090), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V4_V3_nsa_gfx10
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V4_V4
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V4_V4_gfx10
    UINT64_C(4050649090), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V4_V4_nsa_gfx10
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V4_V5
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V4_V5_gfx10
    UINT64_C(4050649090), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V4_V5_nsa_gfx10
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V4_V6
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V4_V6_gfx10
    UINT64_C(4050649092), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V4_V6_nsa_gfx10
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V4_V8
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V4_V8_gfx10
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V5_V3
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V5_V3_gfx10
    UINT64_C(4050649090), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V5_V3_nsa_gfx10
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V5_V4
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V5_V4_gfx10
    UINT64_C(4050649090), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V5_V4_nsa_gfx10
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V5_V5
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V5_V5_gfx10
    UINT64_C(4050649090), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V5_V5_nsa_gfx10
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V5_V6
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V5_V6_gfx10
    UINT64_C(4050649092), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V5_V6_nsa_gfx10
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V5_V8
    UINT64_C(4050649088), UINT64_C(0),	// IMAGE_GATHER4_C_L_O_V5_V8_gfx10
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V2
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V2_gfx10
    UINT64_C(4052484096), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V2_gfx11
    UINT64_C(3826827264), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V2_gfx12
    UINT64_C(4046454786), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V2_nsa_gfx10
    UINT64_C(4052484097), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V2_nsa_gfx11
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V3
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V3_gfx10
    UINT64_C(4052484096), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V3_gfx11
    UINT64_C(3826827264), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V3_gfx12
    UINT64_C(4046454786), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V3_nsa_gfx10
    UINT64_C(4052484097), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V3_nsa_gfx11
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V4
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V4_gfx10
    UINT64_C(4052484096), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V4_gfx11
    UINT64_C(3826827264), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V4_gfx12
    UINT64_C(4046454786), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V4_nsa_gfx10
    UINT64_C(4052484097), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V4_nsa_gfx11
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V5
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V5_gfx10
    UINT64_C(4052484096), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V5_gfx11
    UINT64_C(3826827264), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V5_gfx12
    UINT64_C(4046454786), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V5_nsa_gfx10
    UINT64_C(4052484097), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V5_nsa_gfx11
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V8
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V8_gfx10
    UINT64_C(4052484096), UINT64_C(0),	// IMAGE_GATHER4_C_L_V2_V8_gfx11
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V2
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V2_gfx10
    UINT64_C(4052484096), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V2_gfx11
    UINT64_C(3826827264), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V2_gfx12
    UINT64_C(4046454786), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V2_nsa_gfx10
    UINT64_C(4052484097), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V2_nsa_gfx11
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V3
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V3_gfx10
    UINT64_C(4052484096), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V3_gfx11
    UINT64_C(3826827264), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V3_gfx12
    UINT64_C(4046454786), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V3_nsa_gfx10
    UINT64_C(4052484097), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V3_nsa_gfx11
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V4
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V4_gfx10
    UINT64_C(4052484096), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V4_gfx11
    UINT64_C(3826827264), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V4_gfx12
    UINT64_C(4046454786), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V4_nsa_gfx10
    UINT64_C(4052484097), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V4_nsa_gfx11
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V5
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V5_gfx10
    UINT64_C(4052484096), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V5_gfx11
    UINT64_C(3826827264), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V5_gfx12
    UINT64_C(4046454786), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V5_nsa_gfx10
    UINT64_C(4052484097), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V5_nsa_gfx11
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V8
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V8_gfx10
    UINT64_C(4052484096), UINT64_C(0),	// IMAGE_GATHER4_C_L_V4_V8_gfx11
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V2
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V2_gfx10
    UINT64_C(4052484096), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V2_gfx11
    UINT64_C(3826827264), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V2_gfx12
    UINT64_C(4046454786), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V2_nsa_gfx10
    UINT64_C(4052484097), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V2_nsa_gfx11
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V3
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V3_gfx10
    UINT64_C(4052484096), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V3_gfx11
    UINT64_C(3826827264), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V3_gfx12
    UINT64_C(4046454786), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V3_nsa_gfx10
    UINT64_C(4052484097), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V3_nsa_gfx11
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V4
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V4_gfx10
    UINT64_C(4052484096), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V4_gfx11
    UINT64_C(3826827264), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V4_gfx12
    UINT64_C(4046454786), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V4_nsa_gfx10
    UINT64_C(4052484097), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V4_nsa_gfx11
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V5
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V5_gfx10
    UINT64_C(4052484096), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V5_gfx11
    UINT64_C(3826827264), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V5_gfx12
    UINT64_C(4046454786), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V5_nsa_gfx10
    UINT64_C(4052484097), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V5_nsa_gfx11
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V8
    UINT64_C(4046454784), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V8_gfx10
    UINT64_C(4052484096), UINT64_C(0),	// IMAGE_GATHER4_C_L_V5_V8_gfx11
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V2_V3
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V2_V3_gfx10
    UINT64_C(4049600514), UINT64_C(0),	// IMAGE_GATHER4_C_O_V2_V3_nsa_gfx10
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V2_V4
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V2_V4_gfx10
    UINT64_C(4049600514), UINT64_C(0),	// IMAGE_GATHER4_C_O_V2_V4_nsa_gfx10
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V2_V5
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V2_V5_gfx10
    UINT64_C(4049600514), UINT64_C(0),	// IMAGE_GATHER4_C_O_V2_V5_nsa_gfx10
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V2_V8
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V2_V8_gfx10
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V4_V3
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V4_V3_gfx10
    UINT64_C(4049600514), UINT64_C(0),	// IMAGE_GATHER4_C_O_V4_V3_nsa_gfx10
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V4_V4
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V4_V4_gfx10
    UINT64_C(4049600514), UINT64_C(0),	// IMAGE_GATHER4_C_O_V4_V4_nsa_gfx10
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V4_V5
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V4_V5_gfx10
    UINT64_C(4049600514), UINT64_C(0),	// IMAGE_GATHER4_C_O_V4_V5_nsa_gfx10
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V4_V8
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V4_V8_gfx10
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V5_V3
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V5_V3_gfx10
    UINT64_C(4049600514), UINT64_C(0),	// IMAGE_GATHER4_C_O_V5_V3_nsa_gfx10
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V5_V4
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V5_V4_gfx10
    UINT64_C(4049600514), UINT64_C(0),	// IMAGE_GATHER4_C_O_V5_V4_nsa_gfx10
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V5_V5
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V5_V5_gfx10
    UINT64_C(4049600514), UINT64_C(0),	// IMAGE_GATHER4_C_O_V5_V5_nsa_gfx10
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V5_V8
    UINT64_C(4049600512), UINT64_C(0),	// IMAGE_GATHER4_C_O_V5_V8_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_GATHER4_C_V2_V2
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_GATHER4_C_V2_V2_gfx10
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_GATHER4_C_V2_V2_gfx11
    UINT64_C(3826040832), UINT64_C(0),	// IMAGE_GATHER4_C_V2_V2_gfx12
    UINT64_C(4045406210), UINT64_C(0),	// IMAGE_GATHER4_C_V2_V2_nsa_gfx10
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_GATHER4_C_V2_V2_nsa_gfx11
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_GATHER4_C_V2_V3
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_GATHER4_C_V2_V3_gfx10
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_GATHER4_C_V2_V3_gfx11
    UINT64_C(3826040832), UINT64_C(0),	// IMAGE_GATHER4_C_V2_V3_gfx12
    UINT64_C(4045406210), UINT64_C(0),	// IMAGE_GATHER4_C_V2_V3_nsa_gfx10
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_GATHER4_C_V2_V3_nsa_gfx11
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_GATHER4_C_V2_V4
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_GATHER4_C_V2_V4_gfx10
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_GATHER4_C_V2_V4_gfx11
    UINT64_C(3826040832), UINT64_C(0),	// IMAGE_GATHER4_C_V2_V4_gfx12
    UINT64_C(4045406210), UINT64_C(0),	// IMAGE_GATHER4_C_V2_V4_nsa_gfx10
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_GATHER4_C_V2_V4_nsa_gfx11
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_GATHER4_C_V4_V2
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_GATHER4_C_V4_V2_gfx10
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_GATHER4_C_V4_V2_gfx11
    UINT64_C(3826040832), UINT64_C(0),	// IMAGE_GATHER4_C_V4_V2_gfx12
    UINT64_C(4045406210), UINT64_C(0),	// IMAGE_GATHER4_C_V4_V2_nsa_gfx10
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_GATHER4_C_V4_V2_nsa_gfx11
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_GATHER4_C_V4_V3
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_GATHER4_C_V4_V3_gfx10
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_GATHER4_C_V4_V3_gfx11
    UINT64_C(3826040832), UINT64_C(0),	// IMAGE_GATHER4_C_V4_V3_gfx12
    UINT64_C(4045406210), UINT64_C(0),	// IMAGE_GATHER4_C_V4_V3_nsa_gfx10
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_GATHER4_C_V4_V3_nsa_gfx11
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_GATHER4_C_V4_V4
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_GATHER4_C_V4_V4_gfx10
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_GATHER4_C_V4_V4_gfx11
    UINT64_C(3826040832), UINT64_C(0),	// IMAGE_GATHER4_C_V4_V4_gfx12
    UINT64_C(4045406210), UINT64_C(0),	// IMAGE_GATHER4_C_V4_V4_nsa_gfx10
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_GATHER4_C_V4_V4_nsa_gfx11
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_GATHER4_C_V5_V2
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_GATHER4_C_V5_V2_gfx10
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_GATHER4_C_V5_V2_gfx11
    UINT64_C(3826040832), UINT64_C(0),	// IMAGE_GATHER4_C_V5_V2_gfx12
    UINT64_C(4045406210), UINT64_C(0),	// IMAGE_GATHER4_C_V5_V2_nsa_gfx10
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_GATHER4_C_V5_V2_nsa_gfx11
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_GATHER4_C_V5_V3
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_GATHER4_C_V5_V3_gfx10
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_GATHER4_C_V5_V3_gfx11
    UINT64_C(3826040832), UINT64_C(0),	// IMAGE_GATHER4_C_V5_V3_gfx12
    UINT64_C(4045406210), UINT64_C(0),	// IMAGE_GATHER4_C_V5_V3_nsa_gfx10
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_GATHER4_C_V5_V3_nsa_gfx11
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_GATHER4_C_V5_V4
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_GATHER4_C_V5_V4_gfx10
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_GATHER4_C_V5_V4_gfx11
    UINT64_C(3826040832), UINT64_C(0),	// IMAGE_GATHER4_C_V5_V4_gfx12
    UINT64_C(4045406210), UINT64_C(0),	// IMAGE_GATHER4_C_V5_V4_nsa_gfx10
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_GATHER4_C_V5_V4_nsa_gfx11
    UINT64_C(4049338368), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V2_V2
    UINT64_C(4049338368), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V2_V2_gfx10
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V2_V2_gfx11
    UINT64_C(3826089984), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V2_V2_gfx12
    UINT64_C(4049338370), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V2_V2_nsa_gfx10
    UINT64_C(4040687617), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V2_V2_nsa_gfx11
    UINT64_C(4049338368), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V2_V3
    UINT64_C(4049338368), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V2_V3_gfx10
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V2_V3_gfx11
    UINT64_C(3826089984), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V2_V3_gfx12
    UINT64_C(4049338370), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V2_V3_nsa_gfx10
    UINT64_C(4040687617), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V2_V3_nsa_gfx11
    UINT64_C(4049338368), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V2_V4
    UINT64_C(4049338368), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V2_V4_gfx10
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V2_V4_gfx11
    UINT64_C(3826089984), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V2_V4_gfx12
    UINT64_C(4049338370), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V2_V4_nsa_gfx10
    UINT64_C(4040687617), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V2_V4_nsa_gfx11
    UINT64_C(4049338368), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V4_V2
    UINT64_C(4049338368), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V4_V2_gfx10
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V4_V2_gfx11
    UINT64_C(3826089984), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V4_V2_gfx12
    UINT64_C(4049338370), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V4_V2_nsa_gfx10
    UINT64_C(4040687617), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V4_V2_nsa_gfx11
    UINT64_C(4049338368), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V4_V3
    UINT64_C(4049338368), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V4_V3_gfx10
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V4_V3_gfx11
    UINT64_C(3826089984), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V4_V3_gfx12
    UINT64_C(4049338370), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V4_V3_nsa_gfx10
    UINT64_C(4040687617), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V4_V3_nsa_gfx11
    UINT64_C(4049338368), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V4_V4
    UINT64_C(4049338368), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V4_V4_gfx10
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V4_V4_gfx11
    UINT64_C(3826089984), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V4_V4_gfx12
    UINT64_C(4049338370), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V4_V4_nsa_gfx10
    UINT64_C(4040687617), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V4_V4_nsa_gfx11
    UINT64_C(4049338368), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V5_V2
    UINT64_C(4049338368), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V5_V2_gfx10
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V5_V2_gfx11
    UINT64_C(3826089984), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V5_V2_gfx12
    UINT64_C(4049338370), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V5_V2_nsa_gfx10
    UINT64_C(4040687617), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V5_V2_nsa_gfx11
    UINT64_C(4049338368), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V5_V3
    UINT64_C(4049338368), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V5_V3_gfx10
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V5_V3_gfx11
    UINT64_C(3826089984), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V5_V3_gfx12
    UINT64_C(4049338370), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V5_V3_nsa_gfx10
    UINT64_C(4040687617), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V5_V3_nsa_gfx11
    UINT64_C(4049338368), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V5_V4
    UINT64_C(4049338368), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V5_V4_gfx10
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V5_V4_gfx11
    UINT64_C(3826089984), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V5_V4_gfx12
    UINT64_C(4049338370), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V5_V4_nsa_gfx10
    UINT64_C(4040687617), UINT64_C(0),	// IMAGE_GATHER4_LZ_O_V5_V4_nsa_gfx11
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V2_V1
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V2_V1_gfx10
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_GATHER4_LZ_V2_V1_gfx11
    UINT64_C(3826024448), UINT64_C(0),	// IMAGE_GATHER4_LZ_V2_V1_gfx12
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V2_V2
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V2_V2_gfx10
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_GATHER4_LZ_V2_V2_gfx11
    UINT64_C(3826024448), UINT64_C(0),	// IMAGE_GATHER4_LZ_V2_V2_gfx12
    UINT64_C(4045144066), UINT64_C(0),	// IMAGE_GATHER4_LZ_V2_V2_nsa_gfx10
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_GATHER4_LZ_V2_V2_nsa_gfx11
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V2_V3
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V2_V3_gfx10
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_GATHER4_LZ_V2_V3_gfx11
    UINT64_C(3826024448), UINT64_C(0),	// IMAGE_GATHER4_LZ_V2_V3_gfx12
    UINT64_C(4045144066), UINT64_C(0),	// IMAGE_GATHER4_LZ_V2_V3_nsa_gfx10
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_GATHER4_LZ_V2_V3_nsa_gfx11
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V2_V4
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V2_V4_gfx10
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_GATHER4_LZ_V2_V4_gfx11
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V4_V1
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V4_V1_gfx10
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_GATHER4_LZ_V4_V1_gfx11
    UINT64_C(3826024448), UINT64_C(0),	// IMAGE_GATHER4_LZ_V4_V1_gfx12
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V4_V2
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V4_V2_gfx10
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_GATHER4_LZ_V4_V2_gfx11
    UINT64_C(3826024448), UINT64_C(0),	// IMAGE_GATHER4_LZ_V4_V2_gfx12
    UINT64_C(4045144066), UINT64_C(0),	// IMAGE_GATHER4_LZ_V4_V2_nsa_gfx10
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_GATHER4_LZ_V4_V2_nsa_gfx11
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V4_V3
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V4_V3_gfx10
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_GATHER4_LZ_V4_V3_gfx11
    UINT64_C(3826024448), UINT64_C(0),	// IMAGE_GATHER4_LZ_V4_V3_gfx12
    UINT64_C(4045144066), UINT64_C(0),	// IMAGE_GATHER4_LZ_V4_V3_nsa_gfx10
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_GATHER4_LZ_V4_V3_nsa_gfx11
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V4_V4
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V4_V4_gfx10
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_GATHER4_LZ_V4_V4_gfx11
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V5_V1
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V5_V1_gfx10
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_GATHER4_LZ_V5_V1_gfx11
    UINT64_C(3826024448), UINT64_C(0),	// IMAGE_GATHER4_LZ_V5_V1_gfx12
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V5_V2
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V5_V2_gfx10
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_GATHER4_LZ_V5_V2_gfx11
    UINT64_C(3826024448), UINT64_C(0),	// IMAGE_GATHER4_LZ_V5_V2_gfx12
    UINT64_C(4045144066), UINT64_C(0),	// IMAGE_GATHER4_LZ_V5_V2_nsa_gfx10
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_GATHER4_LZ_V5_V2_nsa_gfx11
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V5_V3
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V5_V3_gfx10
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_GATHER4_LZ_V5_V3_gfx11
    UINT64_C(3826024448), UINT64_C(0),	// IMAGE_GATHER4_LZ_V5_V3_gfx12
    UINT64_C(4045144066), UINT64_C(0),	// IMAGE_GATHER4_LZ_V5_V3_nsa_gfx10
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_GATHER4_LZ_V5_V3_nsa_gfx11
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V5_V4
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_GATHER4_LZ_V5_V4_gfx10
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_GATHER4_LZ_V5_V4_gfx11
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V2_V2
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V2_V2_gfx10
    UINT64_C(4048551938), UINT64_C(0),	// IMAGE_GATHER4_L_O_V2_V2_nsa_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V2_V3
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V2_V3_gfx10
    UINT64_C(4048551938), UINT64_C(0),	// IMAGE_GATHER4_L_O_V2_V3_nsa_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V2_V4
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V2_V4_gfx10
    UINT64_C(4048551938), UINT64_C(0),	// IMAGE_GATHER4_L_O_V2_V4_nsa_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V2_V5
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V2_V5_gfx10
    UINT64_C(4048551938), UINT64_C(0),	// IMAGE_GATHER4_L_O_V2_V5_nsa_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V2_V8
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V2_V8_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V4_V2
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V4_V2_gfx10
    UINT64_C(4048551938), UINT64_C(0),	// IMAGE_GATHER4_L_O_V4_V2_nsa_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V4_V3
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V4_V3_gfx10
    UINT64_C(4048551938), UINT64_C(0),	// IMAGE_GATHER4_L_O_V4_V3_nsa_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V4_V4
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V4_V4_gfx10
    UINT64_C(4048551938), UINT64_C(0),	// IMAGE_GATHER4_L_O_V4_V4_nsa_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V4_V5
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V4_V5_gfx10
    UINT64_C(4048551938), UINT64_C(0),	// IMAGE_GATHER4_L_O_V4_V5_nsa_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V4_V8
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V4_V8_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V5_V2
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V5_V2_gfx10
    UINT64_C(4048551938), UINT64_C(0),	// IMAGE_GATHER4_L_O_V5_V2_nsa_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V5_V3
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V5_V3_gfx10
    UINT64_C(4048551938), UINT64_C(0),	// IMAGE_GATHER4_L_O_V5_V3_nsa_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V5_V4
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V5_V4_gfx10
    UINT64_C(4048551938), UINT64_C(0),	// IMAGE_GATHER4_L_O_V5_V4_nsa_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V5_V5
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V5_V5_gfx10
    UINT64_C(4048551938), UINT64_C(0),	// IMAGE_GATHER4_L_O_V5_V5_nsa_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V5_V8
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_GATHER4_L_O_V5_V8_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V1
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V1_gfx10
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V1_gfx11
    UINT64_C(3825991680), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V1_gfx12
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V2
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V2_gfx10
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V2_gfx11
    UINT64_C(3825991680), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V2_gfx12
    UINT64_C(4044357634), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V2_nsa_gfx10
    UINT64_C(4039114753), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V2_nsa_gfx11
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V3
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V3_gfx10
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V3_gfx11
    UINT64_C(3825991680), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V3_gfx12
    UINT64_C(4044357634), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V3_nsa_gfx10
    UINT64_C(4039114753), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V3_nsa_gfx11
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V4
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V4_gfx10
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V4_gfx11
    UINT64_C(3825991680), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V4_gfx12
    UINT64_C(4044357634), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V4_nsa_gfx10
    UINT64_C(4039114753), UINT64_C(0),	// IMAGE_GATHER4_L_V2_V4_nsa_gfx11
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V1
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V1_gfx10
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V1_gfx11
    UINT64_C(3825991680), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V1_gfx12
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V2
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V2_gfx10
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V2_gfx11
    UINT64_C(3825991680), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V2_gfx12
    UINT64_C(4044357634), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V2_nsa_gfx10
    UINT64_C(4039114753), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V2_nsa_gfx11
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V3
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V3_gfx10
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V3_gfx11
    UINT64_C(3825991680), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V3_gfx12
    UINT64_C(4044357634), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V3_nsa_gfx10
    UINT64_C(4039114753), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V3_nsa_gfx11
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V4
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V4_gfx10
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V4_gfx11
    UINT64_C(3825991680), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V4_gfx12
    UINT64_C(4044357634), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V4_nsa_gfx10
    UINT64_C(4039114753), UINT64_C(0),	// IMAGE_GATHER4_L_V4_V4_nsa_gfx11
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V1
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V1_gfx10
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V1_gfx11
    UINT64_C(3825991680), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V1_gfx12
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V2
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V2_gfx10
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V2_gfx11
    UINT64_C(3825991680), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V2_gfx12
    UINT64_C(4044357634), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V2_nsa_gfx10
    UINT64_C(4039114753), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V2_nsa_gfx11
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V3
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V3_gfx10
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V3_gfx11
    UINT64_C(3825991680), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V3_gfx12
    UINT64_C(4044357634), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V3_nsa_gfx10
    UINT64_C(4039114753), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V3_nsa_gfx11
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V4
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V4_gfx10
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V4_gfx11
    UINT64_C(3825991680), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V4_gfx12
    UINT64_C(4044357634), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V4_nsa_gfx10
    UINT64_C(4039114753), UINT64_C(0),	// IMAGE_GATHER4_L_V5_V4_nsa_gfx11
    UINT64_C(4047503360), UINT64_C(0),	// IMAGE_GATHER4_O_V2_V2
    UINT64_C(4047503360), UINT64_C(0),	// IMAGE_GATHER4_O_V2_V2_gfx10
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_GATHER4_O_V2_V2_gfx11
    UINT64_C(3826073600), UINT64_C(0),	// IMAGE_GATHER4_O_V2_V2_gfx12
    UINT64_C(4047503362), UINT64_C(0),	// IMAGE_GATHER4_O_V2_V2_nsa_gfx10
    UINT64_C(4040425473), UINT64_C(0),	// IMAGE_GATHER4_O_V2_V2_nsa_gfx11
    UINT64_C(4047503360), UINT64_C(0),	// IMAGE_GATHER4_O_V2_V3
    UINT64_C(4047503360), UINT64_C(0),	// IMAGE_GATHER4_O_V2_V3_gfx10
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_GATHER4_O_V2_V3_gfx11
    UINT64_C(3826073600), UINT64_C(0),	// IMAGE_GATHER4_O_V2_V3_gfx12
    UINT64_C(4047503362), UINT64_C(0),	// IMAGE_GATHER4_O_V2_V3_nsa_gfx10
    UINT64_C(4040425473), UINT64_C(0),	// IMAGE_GATHER4_O_V2_V3_nsa_gfx11
    UINT64_C(4047503360), UINT64_C(0),	// IMAGE_GATHER4_O_V2_V4
    UINT64_C(4047503360), UINT64_C(0),	// IMAGE_GATHER4_O_V2_V4_gfx10
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_GATHER4_O_V2_V4_gfx11
    UINT64_C(3826073600), UINT64_C(0),	// IMAGE_GATHER4_O_V2_V4_gfx12
    UINT64_C(4047503362), UINT64_C(0),	// IMAGE_GATHER4_O_V2_V4_nsa_gfx10
    UINT64_C(4040425473), UINT64_C(0),	// IMAGE_GATHER4_O_V2_V4_nsa_gfx11
    UINT64_C(4047503360), UINT64_C(0),	// IMAGE_GATHER4_O_V4_V2
    UINT64_C(4047503360), UINT64_C(0),	// IMAGE_GATHER4_O_V4_V2_gfx10
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_GATHER4_O_V4_V2_gfx11
    UINT64_C(3826073600), UINT64_C(0),	// IMAGE_GATHER4_O_V4_V2_gfx12
    UINT64_C(4047503362), UINT64_C(0),	// IMAGE_GATHER4_O_V4_V2_nsa_gfx10
    UINT64_C(4040425473), UINT64_C(0),	// IMAGE_GATHER4_O_V4_V2_nsa_gfx11
    UINT64_C(4047503360), UINT64_C(0),	// IMAGE_GATHER4_O_V4_V3
    UINT64_C(4047503360), UINT64_C(0),	// IMAGE_GATHER4_O_V4_V3_gfx10
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_GATHER4_O_V4_V3_gfx11
    UINT64_C(3826073600), UINT64_C(0),	// IMAGE_GATHER4_O_V4_V3_gfx12
    UINT64_C(4047503362), UINT64_C(0),	// IMAGE_GATHER4_O_V4_V3_nsa_gfx10
    UINT64_C(4040425473), UINT64_C(0),	// IMAGE_GATHER4_O_V4_V3_nsa_gfx11
    UINT64_C(4047503360), UINT64_C(0),	// IMAGE_GATHER4_O_V4_V4
    UINT64_C(4047503360), UINT64_C(0),	// IMAGE_GATHER4_O_V4_V4_gfx10
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_GATHER4_O_V4_V4_gfx11
    UINT64_C(3826073600), UINT64_C(0),	// IMAGE_GATHER4_O_V4_V4_gfx12
    UINT64_C(4047503362), UINT64_C(0),	// IMAGE_GATHER4_O_V4_V4_nsa_gfx10
    UINT64_C(4040425473), UINT64_C(0),	// IMAGE_GATHER4_O_V4_V4_nsa_gfx11
    UINT64_C(4047503360), UINT64_C(0),	// IMAGE_GATHER4_O_V5_V2
    UINT64_C(4047503360), UINT64_C(0),	// IMAGE_GATHER4_O_V5_V2_gfx10
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_GATHER4_O_V5_V2_gfx11
    UINT64_C(3826073600), UINT64_C(0),	// IMAGE_GATHER4_O_V5_V2_gfx12
    UINT64_C(4047503362), UINT64_C(0),	// IMAGE_GATHER4_O_V5_V2_nsa_gfx10
    UINT64_C(4040425473), UINT64_C(0),	// IMAGE_GATHER4_O_V5_V2_nsa_gfx11
    UINT64_C(4047503360), UINT64_C(0),	// IMAGE_GATHER4_O_V5_V3
    UINT64_C(4047503360), UINT64_C(0),	// IMAGE_GATHER4_O_V5_V3_gfx10
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_GATHER4_O_V5_V3_gfx11
    UINT64_C(3826073600), UINT64_C(0),	// IMAGE_GATHER4_O_V5_V3_gfx12
    UINT64_C(4047503362), UINT64_C(0),	// IMAGE_GATHER4_O_V5_V3_nsa_gfx10
    UINT64_C(4040425473), UINT64_C(0),	// IMAGE_GATHER4_O_V5_V3_nsa_gfx11
    UINT64_C(4047503360), UINT64_C(0),	// IMAGE_GATHER4_O_V5_V4
    UINT64_C(4047503360), UINT64_C(0),	// IMAGE_GATHER4_O_V5_V4_gfx10
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_GATHER4_O_V5_V4_gfx11
    UINT64_C(3826073600), UINT64_C(0),	// IMAGE_GATHER4_O_V5_V4_gfx12
    UINT64_C(4047503362), UINT64_C(0),	// IMAGE_GATHER4_O_V5_V4_nsa_gfx10
    UINT64_C(4040425473), UINT64_C(0),	// IMAGE_GATHER4_O_V5_V4_nsa_gfx11
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V2_V1
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V2_V1_gfx10
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_GATHER4_V2_V1_gfx11
    UINT64_C(3825975296), UINT64_C(0),	// IMAGE_GATHER4_V2_V1_gfx12
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V2_V2
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V2_V2_gfx10
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_GATHER4_V2_V2_gfx11
    UINT64_C(3825975296), UINT64_C(0),	// IMAGE_GATHER4_V2_V2_gfx12
    UINT64_C(4043309058), UINT64_C(0),	// IMAGE_GATHER4_V2_V2_nsa_gfx10
    UINT64_C(4038852609), UINT64_C(0),	// IMAGE_GATHER4_V2_V2_nsa_gfx11
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V2_V3
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V2_V3_gfx10
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_GATHER4_V2_V3_gfx11
    UINT64_C(3825975296), UINT64_C(0),	// IMAGE_GATHER4_V2_V3_gfx12
    UINT64_C(4043309058), UINT64_C(0),	// IMAGE_GATHER4_V2_V3_nsa_gfx10
    UINT64_C(4038852609), UINT64_C(0),	// IMAGE_GATHER4_V2_V3_nsa_gfx11
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V2_V4
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V2_V4_gfx10
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_GATHER4_V2_V4_gfx11
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V4_V1
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V4_V1_gfx10
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_GATHER4_V4_V1_gfx11
    UINT64_C(3825975296), UINT64_C(0),	// IMAGE_GATHER4_V4_V1_gfx12
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V4_V2
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V4_V2_gfx10
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_GATHER4_V4_V2_gfx11
    UINT64_C(3825975296), UINT64_C(0),	// IMAGE_GATHER4_V4_V2_gfx12
    UINT64_C(4043309058), UINT64_C(0),	// IMAGE_GATHER4_V4_V2_nsa_gfx10
    UINT64_C(4038852609), UINT64_C(0),	// IMAGE_GATHER4_V4_V2_nsa_gfx11
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V4_V3
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V4_V3_gfx10
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_GATHER4_V4_V3_gfx11
    UINT64_C(3825975296), UINT64_C(0),	// IMAGE_GATHER4_V4_V3_gfx12
    UINT64_C(4043309058), UINT64_C(0),	// IMAGE_GATHER4_V4_V3_nsa_gfx10
    UINT64_C(4038852609), UINT64_C(0),	// IMAGE_GATHER4_V4_V3_nsa_gfx11
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V4_V4
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V4_V4_gfx10
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_GATHER4_V4_V4_gfx11
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V5_V1
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V5_V1_gfx10
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_GATHER4_V5_V1_gfx11
    UINT64_C(3825975296), UINT64_C(0),	// IMAGE_GATHER4_V5_V1_gfx12
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V5_V2
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V5_V2_gfx10
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_GATHER4_V5_V2_gfx11
    UINT64_C(3825975296), UINT64_C(0),	// IMAGE_GATHER4_V5_V2_gfx12
    UINT64_C(4043309058), UINT64_C(0),	// IMAGE_GATHER4_V5_V2_nsa_gfx10
    UINT64_C(4038852609), UINT64_C(0),	// IMAGE_GATHER4_V5_V2_nsa_gfx11
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V5_V3
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V5_V3_gfx10
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_GATHER4_V5_V3_gfx11
    UINT64_C(3825975296), UINT64_C(0),	// IMAGE_GATHER4_V5_V3_gfx12
    UINT64_C(4043309058), UINT64_C(0),	// IMAGE_GATHER4_V5_V3_nsa_gfx10
    UINT64_C(4038852609), UINT64_C(0),	// IMAGE_GATHER4_V5_V3_nsa_gfx11
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V5_V4
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_GATHER4_V5_V4_gfx10
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_GATHER4_V5_V4_gfx11
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V1_V1
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V1_V1_gfx10
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_GET_LOD_V1_V1_gfx11
    UINT64_C(3826122752), UINT64_C(0),	// IMAGE_GET_LOD_V1_V1_gfx12
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V1_V1_gfx90a
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V1_V2
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V1_V2_gfx10
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_GET_LOD_V1_V2_gfx11
    UINT64_C(3826122752), UINT64_C(0),	// IMAGE_GET_LOD_V1_V2_gfx12
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V1_V2_gfx90a
    UINT64_C(4051697666), UINT64_C(0),	// IMAGE_GET_LOD_V1_V2_nsa_gfx10
    UINT64_C(4041211905), UINT64_C(0),	// IMAGE_GET_LOD_V1_V2_nsa_gfx11
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V1_V3
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V1_V3_gfx10
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_GET_LOD_V1_V3_gfx11
    UINT64_C(3826122752), UINT64_C(0),	// IMAGE_GET_LOD_V1_V3_gfx12
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V1_V3_gfx90a
    UINT64_C(4051697666), UINT64_C(0),	// IMAGE_GET_LOD_V1_V3_nsa_gfx10
    UINT64_C(4041211905), UINT64_C(0),	// IMAGE_GET_LOD_V1_V3_nsa_gfx11
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V1_V4
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V1_V4_gfx10
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_GET_LOD_V1_V4_gfx11
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V1_V4_gfx90a
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V2_V1
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V2_V1_gfx10
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_GET_LOD_V2_V1_gfx11
    UINT64_C(3826122752), UINT64_C(0),	// IMAGE_GET_LOD_V2_V1_gfx12
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V2_V1_gfx90a
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V2_V2
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V2_V2_gfx10
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_GET_LOD_V2_V2_gfx11
    UINT64_C(3826122752), UINT64_C(0),	// IMAGE_GET_LOD_V2_V2_gfx12
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V2_V2_gfx90a
    UINT64_C(4051697666), UINT64_C(0),	// IMAGE_GET_LOD_V2_V2_nsa_gfx10
    UINT64_C(4041211905), UINT64_C(0),	// IMAGE_GET_LOD_V2_V2_nsa_gfx11
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V2_V3
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V2_V3_gfx10
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_GET_LOD_V2_V3_gfx11
    UINT64_C(3826122752), UINT64_C(0),	// IMAGE_GET_LOD_V2_V3_gfx12
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V2_V3_gfx90a
    UINT64_C(4051697666), UINT64_C(0),	// IMAGE_GET_LOD_V2_V3_nsa_gfx10
    UINT64_C(4041211905), UINT64_C(0),	// IMAGE_GET_LOD_V2_V3_nsa_gfx11
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V2_V4
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V2_V4_gfx10
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_GET_LOD_V2_V4_gfx11
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V2_V4_gfx90a
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V3_V1
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V3_V1_gfx10
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_GET_LOD_V3_V1_gfx11
    UINT64_C(3826122752), UINT64_C(0),	// IMAGE_GET_LOD_V3_V1_gfx12
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V3_V1_gfx90a
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V3_V2
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V3_V2_gfx10
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_GET_LOD_V3_V2_gfx11
    UINT64_C(3826122752), UINT64_C(0),	// IMAGE_GET_LOD_V3_V2_gfx12
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V3_V2_gfx90a
    UINT64_C(4051697666), UINT64_C(0),	// IMAGE_GET_LOD_V3_V2_nsa_gfx10
    UINT64_C(4041211905), UINT64_C(0),	// IMAGE_GET_LOD_V3_V2_nsa_gfx11
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V3_V3
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V3_V3_gfx10
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_GET_LOD_V3_V3_gfx11
    UINT64_C(3826122752), UINT64_C(0),	// IMAGE_GET_LOD_V3_V3_gfx12
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V3_V3_gfx90a
    UINT64_C(4051697666), UINT64_C(0),	// IMAGE_GET_LOD_V3_V3_nsa_gfx10
    UINT64_C(4041211905), UINT64_C(0),	// IMAGE_GET_LOD_V3_V3_nsa_gfx11
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V3_V4
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V3_V4_gfx10
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_GET_LOD_V3_V4_gfx11
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V3_V4_gfx90a
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V4_V1
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V4_V1_gfx10
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_GET_LOD_V4_V1_gfx11
    UINT64_C(3826122752), UINT64_C(0),	// IMAGE_GET_LOD_V4_V1_gfx12
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V4_V1_gfx90a
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V4_V2
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V4_V2_gfx10
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_GET_LOD_V4_V2_gfx11
    UINT64_C(3826122752), UINT64_C(0),	// IMAGE_GET_LOD_V4_V2_gfx12
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V4_V2_gfx90a
    UINT64_C(4051697666), UINT64_C(0),	// IMAGE_GET_LOD_V4_V2_nsa_gfx10
    UINT64_C(4041211905), UINT64_C(0),	// IMAGE_GET_LOD_V4_V2_nsa_gfx11
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V4_V3
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V4_V3_gfx10
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_GET_LOD_V4_V3_gfx11
    UINT64_C(3826122752), UINT64_C(0),	// IMAGE_GET_LOD_V4_V3_gfx12
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V4_V3_gfx90a
    UINT64_C(4051697666), UINT64_C(0),	// IMAGE_GET_LOD_V4_V3_nsa_gfx10
    UINT64_C(4041211905), UINT64_C(0),	// IMAGE_GET_LOD_V4_V3_nsa_gfx11
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V4_V4
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V4_V4_gfx10
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_GET_LOD_V4_V4_gfx11
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V4_V4_gfx90a
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V5_V1
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V5_V1_gfx10
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_GET_LOD_V5_V1_gfx11
    UINT64_C(3826122752), UINT64_C(0),	// IMAGE_GET_LOD_V5_V1_gfx12
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V5_V1_gfx90a
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V5_V2
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V5_V2_gfx10
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_GET_LOD_V5_V2_gfx11
    UINT64_C(3826122752), UINT64_C(0),	// IMAGE_GET_LOD_V5_V2_gfx12
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V5_V2_gfx90a
    UINT64_C(4051697666), UINT64_C(0),	// IMAGE_GET_LOD_V5_V2_nsa_gfx10
    UINT64_C(4041211905), UINT64_C(0),	// IMAGE_GET_LOD_V5_V2_nsa_gfx11
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V5_V3
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V5_V3_gfx10
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_GET_LOD_V5_V3_gfx11
    UINT64_C(3826122752), UINT64_C(0),	// IMAGE_GET_LOD_V5_V3_gfx12
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V5_V3_gfx90a
    UINT64_C(4051697666), UINT64_C(0),	// IMAGE_GET_LOD_V5_V3_nsa_gfx10
    UINT64_C(4041211905), UINT64_C(0),	// IMAGE_GET_LOD_V5_V3_nsa_gfx11
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V5_V4
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V5_V4_gfx10
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_GET_LOD_V5_V4_gfx11
    UINT64_C(4051697664), UINT64_C(0),	// IMAGE_GET_LOD_V5_V4_gfx90a
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V1
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V1_gfx10
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V1_gfx11
    UINT64_C(3490037760), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V1_gfx12
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V1_gfx90a
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V2
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V2_gfx10
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V2_gfx11
    UINT64_C(3490037760), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V2_gfx12
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V2_gfx90a
    UINT64_C(4030201858), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V2_nsa_gfx10
    UINT64_C(4032561153), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V2_nsa_gfx11
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V3
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V3_gfx10
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V3_gfx11
    UINT64_C(3490037760), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V3_gfx12
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V3_gfx90a
    UINT64_C(4030201858), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V3_nsa_gfx10
    UINT64_C(4032561153), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V3_nsa_gfx11
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V4
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V4_gfx10
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V4_gfx11
    UINT64_C(3490037760), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V4_gfx12
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V4_gfx90a
    UINT64_C(4030201858), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V4_nsa_gfx10
    UINT64_C(4032561153), UINT64_C(0),	// IMAGE_GET_RESINFO_V1_V4_nsa_gfx11
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V1
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V1_gfx10
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V1_gfx11
    UINT64_C(3490037760), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V1_gfx12
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V1_gfx90a
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V2
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V2_gfx10
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V2_gfx11
    UINT64_C(3490037760), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V2_gfx12
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V2_gfx90a
    UINT64_C(4030201858), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V2_nsa_gfx10
    UINT64_C(4032561153), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V2_nsa_gfx11
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V3
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V3_gfx10
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V3_gfx11
    UINT64_C(3490037760), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V3_gfx12
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V3_gfx90a
    UINT64_C(4030201858), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V3_nsa_gfx10
    UINT64_C(4032561153), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V3_nsa_gfx11
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V4
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V4_gfx10
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V4_gfx11
    UINT64_C(3490037760), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V4_gfx12
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V4_gfx90a
    UINT64_C(4030201858), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V4_nsa_gfx10
    UINT64_C(4032561153), UINT64_C(0),	// IMAGE_GET_RESINFO_V2_V4_nsa_gfx11
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V1
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V1_gfx10
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V1_gfx11
    UINT64_C(3490037760), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V1_gfx12
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V1_gfx90a
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V2
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V2_gfx10
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V2_gfx11
    UINT64_C(3490037760), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V2_gfx12
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V2_gfx90a
    UINT64_C(4030201858), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V2_nsa_gfx10
    UINT64_C(4032561153), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V2_nsa_gfx11
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V3
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V3_gfx10
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V3_gfx11
    UINT64_C(3490037760), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V3_gfx12
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V3_gfx90a
    UINT64_C(4030201858), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V3_nsa_gfx10
    UINT64_C(4032561153), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V3_nsa_gfx11
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V4
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V4_gfx10
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V4_gfx11
    UINT64_C(3490037760), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V4_gfx12
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V4_gfx90a
    UINT64_C(4030201858), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V4_nsa_gfx10
    UINT64_C(4032561153), UINT64_C(0),	// IMAGE_GET_RESINFO_V3_V4_nsa_gfx11
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V1
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V1_gfx10
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V1_gfx11
    UINT64_C(3490037760), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V1_gfx12
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V1_gfx90a
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V2
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V2_gfx10
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V2_gfx11
    UINT64_C(3490037760), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V2_gfx12
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V2_gfx90a
    UINT64_C(4030201858), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V2_nsa_gfx10
    UINT64_C(4032561153), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V2_nsa_gfx11
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V3
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V3_gfx10
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V3_gfx11
    UINT64_C(3490037760), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V3_gfx12
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V3_gfx90a
    UINT64_C(4030201858), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V3_nsa_gfx10
    UINT64_C(4032561153), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V3_nsa_gfx11
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V4
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V4_gfx10
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V4_gfx11
    UINT64_C(3490037760), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V4_gfx12
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V4_gfx90a
    UINT64_C(4030201858), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V4_nsa_gfx10
    UINT64_C(4032561153), UINT64_C(0),	// IMAGE_GET_RESINFO_V4_V4_nsa_gfx11
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V1
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V1_gfx10
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V1_gfx11
    UINT64_C(3490037760), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V1_gfx12
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V1_gfx90a
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V2
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V2_gfx10
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V2_gfx11
    UINT64_C(3490037760), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V2_gfx12
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V2_gfx90a
    UINT64_C(4030201858), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V2_nsa_gfx10
    UINT64_C(4032561153), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V2_nsa_gfx11
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V3
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V3_gfx10
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V3_gfx11
    UINT64_C(3490037760), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V3_gfx12
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V3_gfx90a
    UINT64_C(4030201858), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V3_nsa_gfx10
    UINT64_C(4032561153), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V3_nsa_gfx11
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V4
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V4_gfx10
    UINT64_C(4032561152), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V4_gfx11
    UINT64_C(3490037760), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V4_gfx12
    UINT64_C(4030201856), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V4_gfx90a
    UINT64_C(4030201858), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V4_nsa_gfx10
    UINT64_C(4032561153), UINT64_C(0),	// IMAGE_GET_RESINFO_V5_V4_nsa_gfx11
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V1
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V1_gfx10
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V1_gfx11
    UINT64_C(3489742848), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V1_gfx12
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V1_gfx90a
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V2
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V2_gfx10
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V2_gfx11
    UINT64_C(3489742848), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V2_gfx12
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V2_gfx90a
    UINT64_C(4027842562), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V2_nsa_gfx10
    UINT64_C(4027842561), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V2_nsa_gfx11
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V3
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V3_gfx10
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V3_gfx11
    UINT64_C(3489742848), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V3_gfx12
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V3_gfx90a
    UINT64_C(4027842562), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V3_nsa_gfx10
    UINT64_C(4027842561), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V3_nsa_gfx11
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V4
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V4_gfx10
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V4_gfx11
    UINT64_C(3489742848), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V4_gfx12
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V4_gfx90a
    UINT64_C(4027842562), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V4_nsa_gfx10
    UINT64_C(4027842561), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V1_V4_nsa_gfx11
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V1
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V1_gfx10
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V1_gfx11
    UINT64_C(3489742848), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V1_gfx12
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V1_gfx90a
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V2
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V2_gfx10
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V2_gfx11
    UINT64_C(3489742848), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V2_gfx12
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V2_gfx90a
    UINT64_C(4027842562), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V2_nsa_gfx10
    UINT64_C(4027842561), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V2_nsa_gfx11
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V3
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V3_gfx10
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V3_gfx11
    UINT64_C(3489742848), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V3_gfx12
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V3_gfx90a
    UINT64_C(4027842562), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V3_nsa_gfx10
    UINT64_C(4027842561), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V3_nsa_gfx11
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V4
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V4_gfx10
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V4_gfx11
    UINT64_C(3489742848), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V4_gfx12
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V4_gfx90a
    UINT64_C(4027842562), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V4_nsa_gfx10
    UINT64_C(4027842561), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V2_V4_nsa_gfx11
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V1
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V1_gfx10
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V1_gfx11
    UINT64_C(3489742848), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V1_gfx12
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V1_gfx90a
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V2
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V2_gfx10
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V2_gfx11
    UINT64_C(3489742848), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V2_gfx12
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V2_gfx90a
    UINT64_C(4027842562), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V2_nsa_gfx10
    UINT64_C(4027842561), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V2_nsa_gfx11
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V3
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V3_gfx10
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V3_gfx11
    UINT64_C(3489742848), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V3_gfx12
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V3_gfx90a
    UINT64_C(4027842562), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V3_nsa_gfx10
    UINT64_C(4027842561), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V3_nsa_gfx11
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V4
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V4_gfx10
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V4_gfx11
    UINT64_C(3489742848), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V4_gfx12
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V4_gfx90a
    UINT64_C(4027842562), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V4_nsa_gfx10
    UINT64_C(4027842561), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V3_V4_nsa_gfx11
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V1
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V1_gfx10
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V1_gfx11
    UINT64_C(3489742848), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V1_gfx12
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V1_gfx90a
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V2
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V2_gfx10
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V2_gfx11
    UINT64_C(3489742848), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V2_gfx12
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V2_gfx90a
    UINT64_C(4027842562), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V2_nsa_gfx10
    UINT64_C(4027842561), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V2_nsa_gfx11
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V3
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V3_gfx10
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V3_gfx11
    UINT64_C(3489742848), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V3_gfx12
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V3_gfx90a
    UINT64_C(4027842562), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V3_nsa_gfx10
    UINT64_C(4027842561), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V3_nsa_gfx11
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V4
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V4_gfx10
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V4_gfx11
    UINT64_C(3489742848), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V4_gfx12
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V4_gfx90a
    UINT64_C(4027842562), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V4_nsa_gfx10
    UINT64_C(4027842561), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V4_V4_nsa_gfx11
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V1
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V1_gfx10
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V1_gfx11
    UINT64_C(3489742848), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V1_gfx12
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V1_gfx90a
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V2
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V2_gfx10
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V2_gfx11
    UINT64_C(3489742848), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V2_gfx12
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V2_gfx90a
    UINT64_C(4027842562), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V2_nsa_gfx10
    UINT64_C(4027842561), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V2_nsa_gfx11
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V3
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V3_gfx10
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V3_gfx11
    UINT64_C(3489742848), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V3_gfx12
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V3_gfx90a
    UINT64_C(4027842562), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V3_nsa_gfx10
    UINT64_C(4027842561), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V3_nsa_gfx11
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V4
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V4_gfx10
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V4_gfx11
    UINT64_C(3489742848), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V4_gfx12
    UINT64_C(4027842560), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V4_gfx90a
    UINT64_C(4027842562), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V4_nsa_gfx10
    UINT64_C(4027842561), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_SGN_V5_V4_nsa_gfx11
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V1
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V1_gfx10
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V1_gfx11
    UINT64_C(3489726464), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V1_gfx12
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V1_gfx90a
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V2
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V2_gfx10
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V2_gfx11
    UINT64_C(3489726464), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V2_gfx12
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V2_gfx90a
    UINT64_C(4027580418), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V2_nsa_gfx10
    UINT64_C(4027580417), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V2_nsa_gfx11
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V3
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V3_gfx10
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V3_gfx11
    UINT64_C(3489726464), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V3_gfx12
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V3_gfx90a
    UINT64_C(4027580418), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V3_nsa_gfx10
    UINT64_C(4027580417), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V3_nsa_gfx11
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V4
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V4_gfx10
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V4_gfx11
    UINT64_C(3489726464), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V4_gfx12
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V4_gfx90a
    UINT64_C(4027580418), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V4_nsa_gfx10
    UINT64_C(4027580417), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V1_V4_nsa_gfx11
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V1
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V1_gfx10
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V1_gfx11
    UINT64_C(3489726464), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V1_gfx12
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V1_gfx90a
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V2
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V2_gfx10
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V2_gfx11
    UINT64_C(3489726464), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V2_gfx12
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V2_gfx90a
    UINT64_C(4027580418), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V2_nsa_gfx10
    UINT64_C(4027580417), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V2_nsa_gfx11
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V3
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V3_gfx10
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V3_gfx11
    UINT64_C(3489726464), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V3_gfx12
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V3_gfx90a
    UINT64_C(4027580418), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V3_nsa_gfx10
    UINT64_C(4027580417), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V3_nsa_gfx11
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V4
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V4_gfx10
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V4_gfx11
    UINT64_C(3489726464), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V4_gfx12
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V4_gfx90a
    UINT64_C(4027580418), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V4_nsa_gfx10
    UINT64_C(4027580417), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V2_V4_nsa_gfx11
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V1
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V1_gfx10
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V1_gfx11
    UINT64_C(3489726464), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V1_gfx12
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V1_gfx90a
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V2
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V2_gfx10
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V2_gfx11
    UINT64_C(3489726464), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V2_gfx12
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V2_gfx90a
    UINT64_C(4027580418), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V2_nsa_gfx10
    UINT64_C(4027580417), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V2_nsa_gfx11
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V3
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V3_gfx10
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V3_gfx11
    UINT64_C(3489726464), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V3_gfx12
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V3_gfx90a
    UINT64_C(4027580418), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V3_nsa_gfx10
    UINT64_C(4027580417), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V3_nsa_gfx11
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V4
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V4_gfx10
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V4_gfx11
    UINT64_C(3489726464), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V4_gfx12
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V4_gfx90a
    UINT64_C(4027580418), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V4_nsa_gfx10
    UINT64_C(4027580417), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V3_V4_nsa_gfx11
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V1
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V1_gfx10
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V1_gfx11
    UINT64_C(3489726464), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V1_gfx12
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V1_gfx90a
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V2
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V2_gfx10
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V2_gfx11
    UINT64_C(3489726464), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V2_gfx12
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V2_gfx90a
    UINT64_C(4027580418), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V2_nsa_gfx10
    UINT64_C(4027580417), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V2_nsa_gfx11
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V3
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V3_gfx10
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V3_gfx11
    UINT64_C(3489726464), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V3_gfx12
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V3_gfx90a
    UINT64_C(4027580418), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V3_nsa_gfx10
    UINT64_C(4027580417), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V3_nsa_gfx11
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V4
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V4_gfx10
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V4_gfx11
    UINT64_C(3489726464), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V4_gfx12
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V4_gfx90a
    UINT64_C(4027580418), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V4_nsa_gfx10
    UINT64_C(4027580417), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V4_V4_nsa_gfx11
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V1
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V1_gfx10
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V1_gfx11
    UINT64_C(3489726464), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V1_gfx12
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V1_gfx90a
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V2
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V2_gfx10
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V2_gfx11
    UINT64_C(3489726464), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V2_gfx12
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V2_gfx90a
    UINT64_C(4027580418), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V2_nsa_gfx10
    UINT64_C(4027580417), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V2_nsa_gfx11
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V3
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V3_gfx10
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V3_gfx11
    UINT64_C(3489726464), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V3_gfx12
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V3_gfx90a
    UINT64_C(4027580418), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V3_nsa_gfx10
    UINT64_C(4027580417), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V3_nsa_gfx11
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V4
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V4_gfx10
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V4_gfx11
    UINT64_C(3489726464), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V4_gfx12
    UINT64_C(4027580416), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V4_gfx90a
    UINT64_C(4027580418), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V4_nsa_gfx10
    UINT64_C(4027580417), UINT64_C(0),	// IMAGE_LOAD_MIP_PCK_V5_V4_nsa_gfx11
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V1
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V1_gfx10
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V1_gfx11
    UINT64_C(3489677312), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V1_gfx12
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V1_gfx90a
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V2
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V2_gfx10
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V2_gfx11
    UINT64_C(3489677312), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V2_gfx12
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V2_gfx90a
    UINT64_C(4026793986), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V2_nsa_gfx10
    UINT64_C(4026793985), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V2_nsa_gfx11
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V3
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V3_gfx10
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V3_gfx11
    UINT64_C(3489677312), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V3_gfx12
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V3_gfx90a
    UINT64_C(4026793986), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V3_nsa_gfx10
    UINT64_C(4026793985), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V3_nsa_gfx11
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V4
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V4_gfx10
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V4_gfx11
    UINT64_C(3489677312), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V4_gfx12
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V4_gfx90a
    UINT64_C(4026793986), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V4_nsa_gfx10
    UINT64_C(4026793985), UINT64_C(0),	// IMAGE_LOAD_MIP_V1_V4_nsa_gfx11
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V1
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V1_gfx10
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V1_gfx11
    UINT64_C(3489677312), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V1_gfx12
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V1_gfx90a
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V2
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V2_gfx10
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V2_gfx11
    UINT64_C(3489677312), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V2_gfx12
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V2_gfx90a
    UINT64_C(4026793986), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V2_nsa_gfx10
    UINT64_C(4026793985), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V2_nsa_gfx11
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V3
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V3_gfx10
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V3_gfx11
    UINT64_C(3489677312), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V3_gfx12
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V3_gfx90a
    UINT64_C(4026793986), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V3_nsa_gfx10
    UINT64_C(4026793985), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V3_nsa_gfx11
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V4
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V4_gfx10
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V4_gfx11
    UINT64_C(3489677312), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V4_gfx12
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V4_gfx90a
    UINT64_C(4026793986), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V4_nsa_gfx10
    UINT64_C(4026793985), UINT64_C(0),	// IMAGE_LOAD_MIP_V2_V4_nsa_gfx11
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V1
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V1_gfx10
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V1_gfx11
    UINT64_C(3489677312), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V1_gfx12
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V1_gfx90a
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V2
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V2_gfx10
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V2_gfx11
    UINT64_C(3489677312), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V2_gfx12
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V2_gfx90a
    UINT64_C(4026793986), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V2_nsa_gfx10
    UINT64_C(4026793985), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V2_nsa_gfx11
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V3
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V3_gfx10
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V3_gfx11
    UINT64_C(3489677312), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V3_gfx12
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V3_gfx90a
    UINT64_C(4026793986), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V3_nsa_gfx10
    UINT64_C(4026793985), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V3_nsa_gfx11
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V4
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V4_gfx10
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V4_gfx11
    UINT64_C(3489677312), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V4_gfx12
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V4_gfx90a
    UINT64_C(4026793986), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V4_nsa_gfx10
    UINT64_C(4026793985), UINT64_C(0),	// IMAGE_LOAD_MIP_V3_V4_nsa_gfx11
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V1
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V1_gfx10
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V1_gfx11
    UINT64_C(3489677312), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V1_gfx12
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V1_gfx90a
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V2
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V2_gfx10
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V2_gfx11
    UINT64_C(3489677312), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V2_gfx12
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V2_gfx90a
    UINT64_C(4026793986), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V2_nsa_gfx10
    UINT64_C(4026793985), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V2_nsa_gfx11
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V3
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V3_gfx10
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V3_gfx11
    UINT64_C(3489677312), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V3_gfx12
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V3_gfx90a
    UINT64_C(4026793986), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V3_nsa_gfx10
    UINT64_C(4026793985), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V3_nsa_gfx11
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V4
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V4_gfx10
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V4_gfx11
    UINT64_C(3489677312), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V4_gfx12
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V4_gfx90a
    UINT64_C(4026793986), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V4_nsa_gfx10
    UINT64_C(4026793985), UINT64_C(0),	// IMAGE_LOAD_MIP_V4_V4_nsa_gfx11
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V1
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V1_gfx10
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V1_gfx11
    UINT64_C(3489677312), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V1_gfx12
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V1_gfx90a
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V2
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V2_gfx10
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V2_gfx11
    UINT64_C(3489677312), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V2_gfx12
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V2_gfx90a
    UINT64_C(4026793986), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V2_nsa_gfx10
    UINT64_C(4026793985), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V2_nsa_gfx11
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V3
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V3_gfx10
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V3_gfx11
    UINT64_C(3489677312), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V3_gfx12
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V3_gfx90a
    UINT64_C(4026793986), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V3_nsa_gfx10
    UINT64_C(4026793985), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V3_nsa_gfx11
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V4
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V4_gfx10
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V4_gfx11
    UINT64_C(3489677312), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V4_gfx12
    UINT64_C(4026793984), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V4_gfx90a
    UINT64_C(4026793986), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V4_nsa_gfx10
    UINT64_C(4026793985), UINT64_C(0),	// IMAGE_LOAD_MIP_V5_V4_nsa_gfx11
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V1
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V1_gfx10
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V1_gfx11
    UINT64_C(3489710080), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V1_gfx12
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V1_gfx90a
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V2
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V2_gfx10
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V2_gfx11
    UINT64_C(3489710080), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V2_gfx12
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V2_gfx90a
    UINT64_C(4027318274), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V2_nsa_gfx10
    UINT64_C(4027318273), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V2_nsa_gfx11
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V3
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V3_gfx10
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V3_gfx11
    UINT64_C(3489710080), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V3_gfx12
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V3_gfx90a
    UINT64_C(4027318274), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V3_nsa_gfx10
    UINT64_C(4027318273), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V3_nsa_gfx11
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V4
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V4_gfx10
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V4_gfx11
    UINT64_C(3489710080), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V4_gfx12
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V4_gfx90a
    UINT64_C(4027318274), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V4_nsa_gfx10
    UINT64_C(4027318273), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V1_V4_nsa_gfx11
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V1
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V1_gfx10
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V1_gfx11
    UINT64_C(3489710080), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V1_gfx12
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V1_gfx90a
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V2
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V2_gfx10
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V2_gfx11
    UINT64_C(3489710080), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V2_gfx12
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V2_gfx90a
    UINT64_C(4027318274), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V2_nsa_gfx10
    UINT64_C(4027318273), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V2_nsa_gfx11
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V3
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V3_gfx10
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V3_gfx11
    UINT64_C(3489710080), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V3_gfx12
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V3_gfx90a
    UINT64_C(4027318274), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V3_nsa_gfx10
    UINT64_C(4027318273), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V3_nsa_gfx11
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V4
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V4_gfx10
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V4_gfx11
    UINT64_C(3489710080), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V4_gfx12
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V4_gfx90a
    UINT64_C(4027318274), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V4_nsa_gfx10
    UINT64_C(4027318273), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V2_V4_nsa_gfx11
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V1
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V1_gfx10
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V1_gfx11
    UINT64_C(3489710080), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V1_gfx12
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V1_gfx90a
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V2
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V2_gfx10
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V2_gfx11
    UINT64_C(3489710080), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V2_gfx12
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V2_gfx90a
    UINT64_C(4027318274), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V2_nsa_gfx10
    UINT64_C(4027318273), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V2_nsa_gfx11
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V3
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V3_gfx10
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V3_gfx11
    UINT64_C(3489710080), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V3_gfx12
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V3_gfx90a
    UINT64_C(4027318274), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V3_nsa_gfx10
    UINT64_C(4027318273), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V3_nsa_gfx11
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V4
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V4_gfx10
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V4_gfx11
    UINT64_C(3489710080), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V4_gfx12
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V4_gfx90a
    UINT64_C(4027318274), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V4_nsa_gfx10
    UINT64_C(4027318273), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V3_V4_nsa_gfx11
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V1
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V1_gfx10
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V1_gfx11
    UINT64_C(3489710080), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V1_gfx12
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V1_gfx90a
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V2
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V2_gfx10
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V2_gfx11
    UINT64_C(3489710080), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V2_gfx12
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V2_gfx90a
    UINT64_C(4027318274), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V2_nsa_gfx10
    UINT64_C(4027318273), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V2_nsa_gfx11
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V3
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V3_gfx10
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V3_gfx11
    UINT64_C(3489710080), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V3_gfx12
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V3_gfx90a
    UINT64_C(4027318274), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V3_nsa_gfx10
    UINT64_C(4027318273), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V3_nsa_gfx11
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V4
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V4_gfx10
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V4_gfx11
    UINT64_C(3489710080), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V4_gfx12
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V4_gfx90a
    UINT64_C(4027318274), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V4_nsa_gfx10
    UINT64_C(4027318273), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V4_V4_nsa_gfx11
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V1
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V1_gfx10
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V1_gfx11
    UINT64_C(3489710080), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V1_gfx12
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V1_gfx90a
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V2
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V2_gfx10
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V2_gfx11
    UINT64_C(3489710080), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V2_gfx12
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V2_gfx90a
    UINT64_C(4027318274), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V2_nsa_gfx10
    UINT64_C(4027318273), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V2_nsa_gfx11
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V3
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V3_gfx10
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V3_gfx11
    UINT64_C(3489710080), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V3_gfx12
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V3_gfx90a
    UINT64_C(4027318274), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V3_nsa_gfx10
    UINT64_C(4027318273), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V3_nsa_gfx11
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V4
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V4_gfx10
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V4_gfx11
    UINT64_C(3489710080), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V4_gfx12
    UINT64_C(4027318272), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V4_gfx90a
    UINT64_C(4027318274), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V4_nsa_gfx10
    UINT64_C(4027318273), UINT64_C(0),	// IMAGE_LOAD_PCK_SGN_V5_V4_nsa_gfx11
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V1
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V1_gfx10
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V1_gfx11
    UINT64_C(3489693696), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V1_gfx12
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V1_gfx90a
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V2
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V2_gfx10
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V2_gfx11
    UINT64_C(3489693696), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V2_gfx12
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V2_gfx90a
    UINT64_C(4027056130), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V2_nsa_gfx10
    UINT64_C(4027056129), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V2_nsa_gfx11
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V3
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V3_gfx10
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V3_gfx11
    UINT64_C(3489693696), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V3_gfx12
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V3_gfx90a
    UINT64_C(4027056130), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V3_nsa_gfx10
    UINT64_C(4027056129), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V3_nsa_gfx11
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V4
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V4_gfx10
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V4_gfx11
    UINT64_C(3489693696), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V4_gfx12
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V4_gfx90a
    UINT64_C(4027056130), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V4_nsa_gfx10
    UINT64_C(4027056129), UINT64_C(0),	// IMAGE_LOAD_PCK_V1_V4_nsa_gfx11
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V1
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V1_gfx10
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V1_gfx11
    UINT64_C(3489693696), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V1_gfx12
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V1_gfx90a
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V2
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V2_gfx10
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V2_gfx11
    UINT64_C(3489693696), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V2_gfx12
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V2_gfx90a
    UINT64_C(4027056130), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V2_nsa_gfx10
    UINT64_C(4027056129), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V2_nsa_gfx11
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V3
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V3_gfx10
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V3_gfx11
    UINT64_C(3489693696), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V3_gfx12
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V3_gfx90a
    UINT64_C(4027056130), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V3_nsa_gfx10
    UINT64_C(4027056129), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V3_nsa_gfx11
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V4
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V4_gfx10
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V4_gfx11
    UINT64_C(3489693696), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V4_gfx12
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V4_gfx90a
    UINT64_C(4027056130), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V4_nsa_gfx10
    UINT64_C(4027056129), UINT64_C(0),	// IMAGE_LOAD_PCK_V2_V4_nsa_gfx11
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V1
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V1_gfx10
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V1_gfx11
    UINT64_C(3489693696), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V1_gfx12
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V1_gfx90a
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V2
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V2_gfx10
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V2_gfx11
    UINT64_C(3489693696), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V2_gfx12
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V2_gfx90a
    UINT64_C(4027056130), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V2_nsa_gfx10
    UINT64_C(4027056129), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V2_nsa_gfx11
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V3
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V3_gfx10
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V3_gfx11
    UINT64_C(3489693696), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V3_gfx12
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V3_gfx90a
    UINT64_C(4027056130), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V3_nsa_gfx10
    UINT64_C(4027056129), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V3_nsa_gfx11
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V4
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V4_gfx10
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V4_gfx11
    UINT64_C(3489693696), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V4_gfx12
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V4_gfx90a
    UINT64_C(4027056130), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V4_nsa_gfx10
    UINT64_C(4027056129), UINT64_C(0),	// IMAGE_LOAD_PCK_V3_V4_nsa_gfx11
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V1
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V1_gfx10
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V1_gfx11
    UINT64_C(3489693696), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V1_gfx12
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V1_gfx90a
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V2
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V2_gfx10
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V2_gfx11
    UINT64_C(3489693696), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V2_gfx12
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V2_gfx90a
    UINT64_C(4027056130), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V2_nsa_gfx10
    UINT64_C(4027056129), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V2_nsa_gfx11
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V3
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V3_gfx10
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V3_gfx11
    UINT64_C(3489693696), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V3_gfx12
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V3_gfx90a
    UINT64_C(4027056130), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V3_nsa_gfx10
    UINT64_C(4027056129), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V3_nsa_gfx11
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V4
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V4_gfx10
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V4_gfx11
    UINT64_C(3489693696), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V4_gfx12
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V4_gfx90a
    UINT64_C(4027056130), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V4_nsa_gfx10
    UINT64_C(4027056129), UINT64_C(0),	// IMAGE_LOAD_PCK_V4_V4_nsa_gfx11
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V1
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V1_gfx10
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V1_gfx11
    UINT64_C(3489693696), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V1_gfx12
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V1_gfx90a
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V2
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V2_gfx10
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V2_gfx11
    UINT64_C(3489693696), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V2_gfx12
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V2_gfx90a
    UINT64_C(4027056130), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V2_nsa_gfx10
    UINT64_C(4027056129), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V2_nsa_gfx11
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V3
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V3_gfx10
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V3_gfx11
    UINT64_C(3489693696), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V3_gfx12
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V3_gfx90a
    UINT64_C(4027056130), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V3_nsa_gfx10
    UINT64_C(4027056129), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V3_nsa_gfx11
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V4
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V4_gfx10
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V4_gfx11
    UINT64_C(3489693696), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V4_gfx12
    UINT64_C(4027056128), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V4_gfx90a
    UINT64_C(4027056130), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V4_nsa_gfx10
    UINT64_C(4027056129), UINT64_C(0),	// IMAGE_LOAD_PCK_V5_V4_nsa_gfx11
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V1_V1
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V1_V1_gfx10
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V1_V1_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// IMAGE_LOAD_V1_V1_gfx12
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V1_V1_gfx90a
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V1_V2
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V1_V2_gfx10
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V1_V2_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// IMAGE_LOAD_V1_V2_gfx12
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V1_V2_gfx90a
    UINT64_C(4026531842), UINT64_C(0),	// IMAGE_LOAD_V1_V2_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_LOAD_V1_V2_nsa_gfx11
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V1_V3
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V1_V3_gfx10
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V1_V3_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// IMAGE_LOAD_V1_V3_gfx12
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V1_V3_gfx90a
    UINT64_C(4026531842), UINT64_C(0),	// IMAGE_LOAD_V1_V3_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_LOAD_V1_V3_nsa_gfx11
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V1_V4
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V1_V4_gfx10
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V1_V4_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// IMAGE_LOAD_V1_V4_gfx12
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V1_V4_gfx90a
    UINT64_C(4026531842), UINT64_C(0),	// IMAGE_LOAD_V1_V4_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_LOAD_V1_V4_nsa_gfx11
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V2_V1
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V2_V1_gfx10
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V2_V1_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// IMAGE_LOAD_V2_V1_gfx12
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V2_V1_gfx90a
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V2_V2
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V2_V2_gfx10
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V2_V2_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// IMAGE_LOAD_V2_V2_gfx12
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V2_V2_gfx90a
    UINT64_C(4026531842), UINT64_C(0),	// IMAGE_LOAD_V2_V2_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_LOAD_V2_V2_nsa_gfx11
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V2_V3
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V2_V3_gfx10
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V2_V3_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// IMAGE_LOAD_V2_V3_gfx12
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V2_V3_gfx90a
    UINT64_C(4026531842), UINT64_C(0),	// IMAGE_LOAD_V2_V3_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_LOAD_V2_V3_nsa_gfx11
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V2_V4
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V2_V4_gfx10
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V2_V4_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// IMAGE_LOAD_V2_V4_gfx12
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V2_V4_gfx90a
    UINT64_C(4026531842), UINT64_C(0),	// IMAGE_LOAD_V2_V4_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_LOAD_V2_V4_nsa_gfx11
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V3_V1
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V3_V1_gfx10
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V3_V1_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// IMAGE_LOAD_V3_V1_gfx12
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V3_V1_gfx90a
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V3_V2
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V3_V2_gfx10
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V3_V2_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// IMAGE_LOAD_V3_V2_gfx12
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V3_V2_gfx90a
    UINT64_C(4026531842), UINT64_C(0),	// IMAGE_LOAD_V3_V2_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_LOAD_V3_V2_nsa_gfx11
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V3_V3
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V3_V3_gfx10
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V3_V3_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// IMAGE_LOAD_V3_V3_gfx12
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V3_V3_gfx90a
    UINT64_C(4026531842), UINT64_C(0),	// IMAGE_LOAD_V3_V3_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_LOAD_V3_V3_nsa_gfx11
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V3_V4
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V3_V4_gfx10
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V3_V4_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// IMAGE_LOAD_V3_V4_gfx12
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V3_V4_gfx90a
    UINT64_C(4026531842), UINT64_C(0),	// IMAGE_LOAD_V3_V4_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_LOAD_V3_V4_nsa_gfx11
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V4_V1
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V4_V1_gfx10
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V4_V1_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// IMAGE_LOAD_V4_V1_gfx12
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V4_V1_gfx90a
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V4_V2
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V4_V2_gfx10
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V4_V2_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// IMAGE_LOAD_V4_V2_gfx12
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V4_V2_gfx90a
    UINT64_C(4026531842), UINT64_C(0),	// IMAGE_LOAD_V4_V2_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_LOAD_V4_V2_nsa_gfx11
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V4_V3
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V4_V3_gfx10
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V4_V3_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// IMAGE_LOAD_V4_V3_gfx12
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V4_V3_gfx90a
    UINT64_C(4026531842), UINT64_C(0),	// IMAGE_LOAD_V4_V3_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_LOAD_V4_V3_nsa_gfx11
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V4_V4
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V4_V4_gfx10
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V4_V4_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// IMAGE_LOAD_V4_V4_gfx12
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V4_V4_gfx90a
    UINT64_C(4026531842), UINT64_C(0),	// IMAGE_LOAD_V4_V4_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_LOAD_V4_V4_nsa_gfx11
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V5_V1
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V5_V1_gfx10
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V5_V1_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// IMAGE_LOAD_V5_V1_gfx12
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V5_V1_gfx90a
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V5_V2
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V5_V2_gfx10
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V5_V2_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// IMAGE_LOAD_V5_V2_gfx12
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V5_V2_gfx90a
    UINT64_C(4026531842), UINT64_C(0),	// IMAGE_LOAD_V5_V2_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_LOAD_V5_V2_nsa_gfx11
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V5_V3
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V5_V3_gfx10
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V5_V3_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// IMAGE_LOAD_V5_V3_gfx12
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V5_V3_gfx90a
    UINT64_C(4026531842), UINT64_C(0),	// IMAGE_LOAD_V5_V3_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_LOAD_V5_V3_nsa_gfx11
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V5_V4
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V5_V4_gfx10
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V5_V4_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// IMAGE_LOAD_V5_V4_gfx12
    UINT64_C(4026531840), UINT64_C(0),	// IMAGE_LOAD_V5_V4_gfx90a
    UINT64_C(4026531842), UINT64_C(0),	// IMAGE_LOAD_V5_V4_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_LOAD_V5_V4_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_MSAA_LOAD_V2_V1_gfx11
    UINT64_C(3825598464), UINT64_C(0),	// IMAGE_MSAA_LOAD_V2_V1_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_MSAA_LOAD_V2_V2_gfx11
    UINT64_C(3825598464), UINT64_C(0),	// IMAGE_MSAA_LOAD_V2_V2_gfx12
    UINT64_C(4032823297), UINT64_C(0),	// IMAGE_MSAA_LOAD_V2_V2_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_MSAA_LOAD_V2_V3_gfx11
    UINT64_C(3825598464), UINT64_C(0),	// IMAGE_MSAA_LOAD_V2_V3_gfx12
    UINT64_C(4032823297), UINT64_C(0),	// IMAGE_MSAA_LOAD_V2_V3_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_MSAA_LOAD_V2_V4_gfx11
    UINT64_C(3825598464), UINT64_C(0),	// IMAGE_MSAA_LOAD_V2_V4_gfx12
    UINT64_C(4032823297), UINT64_C(0),	// IMAGE_MSAA_LOAD_V2_V4_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_MSAA_LOAD_V3_V1_gfx11
    UINT64_C(3825598464), UINT64_C(0),	// IMAGE_MSAA_LOAD_V3_V1_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_MSAA_LOAD_V3_V2_gfx11
    UINT64_C(3825598464), UINT64_C(0),	// IMAGE_MSAA_LOAD_V3_V2_gfx12
    UINT64_C(4032823297), UINT64_C(0),	// IMAGE_MSAA_LOAD_V3_V2_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_MSAA_LOAD_V3_V3_gfx11
    UINT64_C(3825598464), UINT64_C(0),	// IMAGE_MSAA_LOAD_V3_V3_gfx12
    UINT64_C(4032823297), UINT64_C(0),	// IMAGE_MSAA_LOAD_V3_V3_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_MSAA_LOAD_V3_V4_gfx11
    UINT64_C(3825598464), UINT64_C(0),	// IMAGE_MSAA_LOAD_V3_V4_gfx12
    UINT64_C(4032823297), UINT64_C(0),	// IMAGE_MSAA_LOAD_V3_V4_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_MSAA_LOAD_V4_V1_gfx11
    UINT64_C(3825598464), UINT64_C(0),	// IMAGE_MSAA_LOAD_V4_V1_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_MSAA_LOAD_V4_V2_gfx11
    UINT64_C(3825598464), UINT64_C(0),	// IMAGE_MSAA_LOAD_V4_V2_gfx12
    UINT64_C(4032823297), UINT64_C(0),	// IMAGE_MSAA_LOAD_V4_V2_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_MSAA_LOAD_V4_V3_gfx11
    UINT64_C(3825598464), UINT64_C(0),	// IMAGE_MSAA_LOAD_V4_V3_gfx12
    UINT64_C(4032823297), UINT64_C(0),	// IMAGE_MSAA_LOAD_V4_V3_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_MSAA_LOAD_V4_V4_gfx11
    UINT64_C(3825598464), UINT64_C(0),	// IMAGE_MSAA_LOAD_V4_V4_gfx12
    UINT64_C(4032823297), UINT64_C(0),	// IMAGE_MSAA_LOAD_V4_V4_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_MSAA_LOAD_V5_V1_gfx11
    UINT64_C(3825598464), UINT64_C(0),	// IMAGE_MSAA_LOAD_V5_V1_gfx12
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_MSAA_LOAD_V5_V2_gfx11
    UINT64_C(3825598464), UINT64_C(0),	// IMAGE_MSAA_LOAD_V5_V2_gfx12
    UINT64_C(4032823297), UINT64_C(0),	// IMAGE_MSAA_LOAD_V5_V2_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_MSAA_LOAD_V5_V3_gfx11
    UINT64_C(3825598464), UINT64_C(0),	// IMAGE_MSAA_LOAD_V5_V3_gfx12
    UINT64_C(4032823297), UINT64_C(0),	// IMAGE_MSAA_LOAD_V5_V3_nsa_gfx11
    UINT64_C(4032823296), UINT64_C(0),	// IMAGE_MSAA_LOAD_V5_V4_gfx11
    UINT64_C(3825598464), UINT64_C(0),	// IMAGE_MSAA_LOAD_V5_V4_gfx12
    UINT64_C(4032823297), UINT64_C(0),	// IMAGE_MSAA_LOAD_V5_V4_nsa_gfx11
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V1_V1
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V1_V1_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V1_V2
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V1_V2_gfx10
    UINT64_C(4026531843), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V1_V2_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V1_V3
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V1_V3_gfx10
    UINT64_C(4026531843), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V1_V3_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V1_V4
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V1_V4_gfx10
    UINT64_C(4026531843), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V1_V4_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V2_V1
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V2_V1_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V2_V2
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V2_V2_gfx10
    UINT64_C(4026531843), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V2_V2_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V2_V3
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V2_V3_gfx10
    UINT64_C(4026531843), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V2_V3_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V2_V4
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V2_V4_gfx10
    UINT64_C(4026531843), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V2_V4_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V3_V1
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V3_V1_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V3_V2
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V3_V2_gfx10
    UINT64_C(4026531843), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V3_V2_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V3_V3
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V3_V3_gfx10
    UINT64_C(4026531843), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V3_V3_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V3_V4
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V3_V4_gfx10
    UINT64_C(4026531843), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V3_V4_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V4_V1
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V4_V1_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V4_V2
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V4_V2_gfx10
    UINT64_C(4026531843), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V4_V2_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V4_V3
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V4_V3_gfx10
    UINT64_C(4026531843), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V4_V3_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V4_V4
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V4_V4_gfx10
    UINT64_C(4026531843), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V4_V4_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V5_V1
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V5_V1_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V5_V2
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V5_V2_gfx10
    UINT64_C(4026531843), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V5_V2_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V5_V3
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V5_V3_gfx10
    UINT64_C(4026531843), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V5_V3_nsa_gfx10
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V5_V4
    UINT64_C(4026531841), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V5_V4_gfx10
    UINT64_C(4026531843), UINT64_C(0),	// IMAGE_MSAA_LOAD_X_V5_V4_nsa_gfx10
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V3
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V3_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V3_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V3_gfx12
    UINT64_C(4040687618), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V3_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V3_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V4
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V4_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V4_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V4_gfx12
    UINT64_C(4040687618), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V4_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V4_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V5
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V5_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V5_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V5_gfx12
    UINT64_C(4040687618), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V5_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V5_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V6
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V6_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V6_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V6_gfx12
    UINT64_C(4040687620), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V6_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V6_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V8
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V8_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V1_V8_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V3
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V3_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V3_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V3_gfx12
    UINT64_C(4040687618), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V3_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V3_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V4
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V4_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V4_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V4_gfx12
    UINT64_C(4040687618), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V4_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V4_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V5
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V5_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V5_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V5_gfx12
    UINT64_C(4040687618), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V5_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V5_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V6
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V6_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V6_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V6_gfx12
    UINT64_C(4040687620), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V6_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V6_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V8
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V8_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V2_V8_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V3
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V3_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V3_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V3_gfx12
    UINT64_C(4040687618), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V3_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V3_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V4
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V4_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V4_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V4_gfx12
    UINT64_C(4040687618), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V4_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V4_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V5
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V5_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V5_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V5_gfx12
    UINT64_C(4040687618), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V5_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V5_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V6
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V6_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V6_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V6_gfx12
    UINT64_C(4040687620), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V6_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V6_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V8
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V8_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V3_V8_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V3
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V3_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V3_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V3_gfx12
    UINT64_C(4040687618), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V3_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V3_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V4
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V4_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V4_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V4_gfx12
    UINT64_C(4040687618), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V4_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V4_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V5
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V5_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V5_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V5_gfx12
    UINT64_C(4040687618), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V5_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V5_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V6
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V6_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V6_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V6_gfx12
    UINT64_C(4040687620), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V6_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V6_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V8
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V8_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V4_V8_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V3
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V3_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V3_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V3_gfx12
    UINT64_C(4040687618), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V3_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V3_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V4
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V4_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V4_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V4_gfx12
    UINT64_C(4040687618), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V4_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V4_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V5
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V5_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V5_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V5_gfx12
    UINT64_C(4040687618), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V5_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V5_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V6
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V6_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V6_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V6_gfx12
    UINT64_C(4040687620), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V6_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V6_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V8
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V8_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_V5_V8_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V3_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V3_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V3_gfx12
    UINT64_C(4040687618), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V3_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V3_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V4_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V4_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V4_gfx12
    UINT64_C(4040687618), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V4_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V4_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V5_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V5_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V5_gfx12
    UINT64_C(4040687618), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V5_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V5_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V6_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V6_gfx11
    UINT64_C(3826384896), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V6_gfx12
    UINT64_C(4040687620), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V6_nsa_gfx10
    UINT64_C(4045406209), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V6_nsa_gfx11
    UINT64_C(4040687616), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V8_gfx10
    UINT64_C(4045406208), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_O_nortn_V8_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V2
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V2_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V2_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V2_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V2_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V2_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V3
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V3_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V3_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V3_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V3_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V3_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V4
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V4_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V4_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V4_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V4_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V4_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V5
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V5_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V5_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V5_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V5_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V5_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V8
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V8_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V1_V8_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V2
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V2_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V2_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V2_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V2_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V2_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V3
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V3_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V3_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V3_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V3_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V3_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V4
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V4_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V4_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V4_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V4_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V4_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V5
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V5_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V5_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V5_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V5_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V5_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V8
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V8_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V2_V8_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V2
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V2_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V2_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V2_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V2_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V2_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V3
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V3_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V3_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V3_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V3_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V3_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V4
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V4_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V4_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V4_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V4_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V4_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V5
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V5_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V5_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V5_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V5_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V5_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V8
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V8_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V3_V8_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V2
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V2_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V2_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V2_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V2_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V2_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V3
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V3_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V3_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V3_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V3_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V3_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V4
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V4_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V4_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V4_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V4_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V4_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V5
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V5_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V5_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V5_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V5_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V5_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V8
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V8_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V4_V8_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V2
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V2_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V2_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V2_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V2_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V2_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V3
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V3_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V3_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V3_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V3_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V3_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V4
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V4_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V4_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V4_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V4_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V4_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V5
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V5_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V5_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V5_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V5_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V5_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V8
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V8_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_V5_V8_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V2_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V2_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V2_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V2_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V2_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V3_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V3_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V3_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V3_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V3_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V4_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V4_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V4_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V4_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V4_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V5_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V5_gfx11
    UINT64_C(3826286592), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V5_gfx12
    UINT64_C(4036493314), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V5_nsa_gfx10
    UINT64_C(4043833345), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V5_nsa_gfx11
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V8_gfx10
    UINT64_C(4043833344), UINT64_C(0),	// IMAGE_SAMPLE_B_CL_nortn_V8_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V3
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V3_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V3_gfx11
    UINT64_C(3825860608), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V3_gfx12
    UINT64_C(4040425474), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V3_nsa_gfx10
    UINT64_C(4037017601), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V3_nsa_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V4
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V4_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V4_gfx11
    UINT64_C(3825860608), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V4_gfx12
    UINT64_C(4040425474), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V4_nsa_gfx10
    UINT64_C(4037017601), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V4_nsa_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V5
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V5_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V5_gfx11
    UINT64_C(3825860608), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V5_gfx12
    UINT64_C(4040425474), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V5_nsa_gfx10
    UINT64_C(4037017601), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V5_nsa_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V8
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V8_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V1_V8_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V3
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V3_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V3_gfx11
    UINT64_C(3825860608), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V3_gfx12
    UINT64_C(4040425474), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V3_nsa_gfx10
    UINT64_C(4037017601), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V3_nsa_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V4
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V4_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V4_gfx11
    UINT64_C(3825860608), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V4_gfx12
    UINT64_C(4040425474), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V4_nsa_gfx10
    UINT64_C(4037017601), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V4_nsa_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V5
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V5_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V5_gfx11
    UINT64_C(3825860608), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V5_gfx12
    UINT64_C(4040425474), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V5_nsa_gfx10
    UINT64_C(4037017601), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V5_nsa_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V8
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V8_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V2_V8_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V3
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V3_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V3_gfx11
    UINT64_C(3825860608), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V3_gfx12
    UINT64_C(4040425474), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V3_nsa_gfx10
    UINT64_C(4037017601), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V3_nsa_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V4
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V4_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V4_gfx11
    UINT64_C(3825860608), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V4_gfx12
    UINT64_C(4040425474), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V4_nsa_gfx10
    UINT64_C(4037017601), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V4_nsa_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V5
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V5_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V5_gfx11
    UINT64_C(3825860608), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V5_gfx12
    UINT64_C(4040425474), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V5_nsa_gfx10
    UINT64_C(4037017601), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V5_nsa_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V8
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V8_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V3_V8_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V3
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V3_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V3_gfx11
    UINT64_C(3825860608), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V3_gfx12
    UINT64_C(4040425474), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V3_nsa_gfx10
    UINT64_C(4037017601), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V3_nsa_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V4
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V4_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V4_gfx11
    UINT64_C(3825860608), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V4_gfx12
    UINT64_C(4040425474), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V4_nsa_gfx10
    UINT64_C(4037017601), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V4_nsa_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V5
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V5_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V5_gfx11
    UINT64_C(3825860608), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V5_gfx12
    UINT64_C(4040425474), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V5_nsa_gfx10
    UINT64_C(4037017601), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V5_nsa_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V8
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V8_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V4_V8_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V3
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V3_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V3_gfx11
    UINT64_C(3825860608), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V3_gfx12
    UINT64_C(4040425474), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V3_nsa_gfx10
    UINT64_C(4037017601), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V3_nsa_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V4
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V4_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V4_gfx11
    UINT64_C(3825860608), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V4_gfx12
    UINT64_C(4040425474), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V4_nsa_gfx10
    UINT64_C(4037017601), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V4_nsa_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V5
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V5_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V5_gfx11
    UINT64_C(3825860608), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V5_gfx12
    UINT64_C(4040425474), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V5_nsa_gfx10
    UINT64_C(4037017601), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V5_nsa_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V8
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V8_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_V5_V8_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_nortn_V3_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_nortn_V3_gfx11
    UINT64_C(3825860608), UINT64_C(0),	// IMAGE_SAMPLE_B_O_nortn_V3_gfx12
    UINT64_C(4040425474), UINT64_C(0),	// IMAGE_SAMPLE_B_O_nortn_V3_nsa_gfx10
    UINT64_C(4037017601), UINT64_C(0),	// IMAGE_SAMPLE_B_O_nortn_V3_nsa_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_nortn_V4_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_nortn_V4_gfx11
    UINT64_C(3825860608), UINT64_C(0),	// IMAGE_SAMPLE_B_O_nortn_V4_gfx12
    UINT64_C(4040425474), UINT64_C(0),	// IMAGE_SAMPLE_B_O_nortn_V4_nsa_gfx10
    UINT64_C(4037017601), UINT64_C(0),	// IMAGE_SAMPLE_B_O_nortn_V4_nsa_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_nortn_V5_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_nortn_V5_gfx11
    UINT64_C(3825860608), UINT64_C(0),	// IMAGE_SAMPLE_B_O_nortn_V5_gfx12
    UINT64_C(4040425474), UINT64_C(0),	// IMAGE_SAMPLE_B_O_nortn_V5_nsa_gfx10
    UINT64_C(4037017601), UINT64_C(0),	// IMAGE_SAMPLE_B_O_nortn_V5_nsa_gfx11
    UINT64_C(4040425472), UINT64_C(0),	// IMAGE_SAMPLE_B_O_nortn_V8_gfx10
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_B_O_nortn_V8_gfx11
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V1_V2
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V1_V2_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_SAMPLE_B_V1_V2_gfx11
    UINT64_C(3825696768), UINT64_C(0),	// IMAGE_SAMPLE_B_V1_V2_gfx12
    UINT64_C(4036231170), UINT64_C(0),	// IMAGE_SAMPLE_B_V1_V2_nsa_gfx10
    UINT64_C(4034396161), UINT64_C(0),	// IMAGE_SAMPLE_B_V1_V2_nsa_gfx11
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V1_V3
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V1_V3_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_SAMPLE_B_V1_V3_gfx11
    UINT64_C(3825696768), UINT64_C(0),	// IMAGE_SAMPLE_B_V1_V3_gfx12
    UINT64_C(4036231170), UINT64_C(0),	// IMAGE_SAMPLE_B_V1_V3_nsa_gfx10
    UINT64_C(4034396161), UINT64_C(0),	// IMAGE_SAMPLE_B_V1_V3_nsa_gfx11
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V1_V4
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V1_V4_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_SAMPLE_B_V1_V4_gfx11
    UINT64_C(3825696768), UINT64_C(0),	// IMAGE_SAMPLE_B_V1_V4_gfx12
    UINT64_C(4036231170), UINT64_C(0),	// IMAGE_SAMPLE_B_V1_V4_nsa_gfx10
    UINT64_C(4034396161), UINT64_C(0),	// IMAGE_SAMPLE_B_V1_V4_nsa_gfx11
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V2_V2
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V2_V2_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_SAMPLE_B_V2_V2_gfx11
    UINT64_C(3825696768), UINT64_C(0),	// IMAGE_SAMPLE_B_V2_V2_gfx12
    UINT64_C(4036231170), UINT64_C(0),	// IMAGE_SAMPLE_B_V2_V2_nsa_gfx10
    UINT64_C(4034396161), UINT64_C(0),	// IMAGE_SAMPLE_B_V2_V2_nsa_gfx11
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V2_V3
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V2_V3_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_SAMPLE_B_V2_V3_gfx11
    UINT64_C(3825696768), UINT64_C(0),	// IMAGE_SAMPLE_B_V2_V3_gfx12
    UINT64_C(4036231170), UINT64_C(0),	// IMAGE_SAMPLE_B_V2_V3_nsa_gfx10
    UINT64_C(4034396161), UINT64_C(0),	// IMAGE_SAMPLE_B_V2_V3_nsa_gfx11
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V2_V4
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V2_V4_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_SAMPLE_B_V2_V4_gfx11
    UINT64_C(3825696768), UINT64_C(0),	// IMAGE_SAMPLE_B_V2_V4_gfx12
    UINT64_C(4036231170), UINT64_C(0),	// IMAGE_SAMPLE_B_V2_V4_nsa_gfx10
    UINT64_C(4034396161), UINT64_C(0),	// IMAGE_SAMPLE_B_V2_V4_nsa_gfx11
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V3_V2
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V3_V2_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_SAMPLE_B_V3_V2_gfx11
    UINT64_C(3825696768), UINT64_C(0),	// IMAGE_SAMPLE_B_V3_V2_gfx12
    UINT64_C(4036231170), UINT64_C(0),	// IMAGE_SAMPLE_B_V3_V2_nsa_gfx10
    UINT64_C(4034396161), UINT64_C(0),	// IMAGE_SAMPLE_B_V3_V2_nsa_gfx11
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V3_V3
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V3_V3_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_SAMPLE_B_V3_V3_gfx11
    UINT64_C(3825696768), UINT64_C(0),	// IMAGE_SAMPLE_B_V3_V3_gfx12
    UINT64_C(4036231170), UINT64_C(0),	// IMAGE_SAMPLE_B_V3_V3_nsa_gfx10
    UINT64_C(4034396161), UINT64_C(0),	// IMAGE_SAMPLE_B_V3_V3_nsa_gfx11
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V3_V4
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V3_V4_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_SAMPLE_B_V3_V4_gfx11
    UINT64_C(3825696768), UINT64_C(0),	// IMAGE_SAMPLE_B_V3_V4_gfx12
    UINT64_C(4036231170), UINT64_C(0),	// IMAGE_SAMPLE_B_V3_V4_nsa_gfx10
    UINT64_C(4034396161), UINT64_C(0),	// IMAGE_SAMPLE_B_V3_V4_nsa_gfx11
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V4_V2
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V4_V2_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_SAMPLE_B_V4_V2_gfx11
    UINT64_C(3825696768), UINT64_C(0),	// IMAGE_SAMPLE_B_V4_V2_gfx12
    UINT64_C(4036231170), UINT64_C(0),	// IMAGE_SAMPLE_B_V4_V2_nsa_gfx10
    UINT64_C(4034396161), UINT64_C(0),	// IMAGE_SAMPLE_B_V4_V2_nsa_gfx11
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V4_V3
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V4_V3_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_SAMPLE_B_V4_V3_gfx11
    UINT64_C(3825696768), UINT64_C(0),	// IMAGE_SAMPLE_B_V4_V3_gfx12
    UINT64_C(4036231170), UINT64_C(0),	// IMAGE_SAMPLE_B_V4_V3_nsa_gfx10
    UINT64_C(4034396161), UINT64_C(0),	// IMAGE_SAMPLE_B_V4_V3_nsa_gfx11
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V4_V4
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V4_V4_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_SAMPLE_B_V4_V4_gfx11
    UINT64_C(3825696768), UINT64_C(0),	// IMAGE_SAMPLE_B_V4_V4_gfx12
    UINT64_C(4036231170), UINT64_C(0),	// IMAGE_SAMPLE_B_V4_V4_nsa_gfx10
    UINT64_C(4034396161), UINT64_C(0),	// IMAGE_SAMPLE_B_V4_V4_nsa_gfx11
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V5_V2
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V5_V2_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_SAMPLE_B_V5_V2_gfx11
    UINT64_C(3825696768), UINT64_C(0),	// IMAGE_SAMPLE_B_V5_V2_gfx12
    UINT64_C(4036231170), UINT64_C(0),	// IMAGE_SAMPLE_B_V5_V2_nsa_gfx10
    UINT64_C(4034396161), UINT64_C(0),	// IMAGE_SAMPLE_B_V5_V2_nsa_gfx11
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V5_V3
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V5_V3_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_SAMPLE_B_V5_V3_gfx11
    UINT64_C(3825696768), UINT64_C(0),	// IMAGE_SAMPLE_B_V5_V3_gfx12
    UINT64_C(4036231170), UINT64_C(0),	// IMAGE_SAMPLE_B_V5_V3_nsa_gfx10
    UINT64_C(4034396161), UINT64_C(0),	// IMAGE_SAMPLE_B_V5_V3_nsa_gfx11
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V5_V4
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_V5_V4_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_SAMPLE_B_V5_V4_gfx11
    UINT64_C(3825696768), UINT64_C(0),	// IMAGE_SAMPLE_B_V5_V4_gfx12
    UINT64_C(4036231170), UINT64_C(0),	// IMAGE_SAMPLE_B_V5_V4_nsa_gfx10
    UINT64_C(4034396161), UINT64_C(0),	// IMAGE_SAMPLE_B_V5_V4_nsa_gfx11
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_nortn_V2_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_SAMPLE_B_nortn_V2_gfx11
    UINT64_C(3825696768), UINT64_C(0),	// IMAGE_SAMPLE_B_nortn_V2_gfx12
    UINT64_C(4036231170), UINT64_C(0),	// IMAGE_SAMPLE_B_nortn_V2_nsa_gfx10
    UINT64_C(4034396161), UINT64_C(0),	// IMAGE_SAMPLE_B_nortn_V2_nsa_gfx11
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_nortn_V3_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_SAMPLE_B_nortn_V3_gfx11
    UINT64_C(3825696768), UINT64_C(0),	// IMAGE_SAMPLE_B_nortn_V3_gfx12
    UINT64_C(4036231170), UINT64_C(0),	// IMAGE_SAMPLE_B_nortn_V3_nsa_gfx10
    UINT64_C(4034396161), UINT64_C(0),	// IMAGE_SAMPLE_B_nortn_V3_nsa_gfx11
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_B_nortn_V4_gfx10
    UINT64_C(4034396160), UINT64_C(0),	// IMAGE_SAMPLE_B_nortn_V4_gfx11
    UINT64_C(3825696768), UINT64_C(0),	// IMAGE_SAMPLE_B_nortn_V4_gfx12
    UINT64_C(4036231170), UINT64_C(0),	// IMAGE_SAMPLE_B_nortn_V4_nsa_gfx10
    UINT64_C(4034396161), UINT64_C(0),	// IMAGE_SAMPLE_B_nortn_V4_nsa_gfx11
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V2
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V2_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V2_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V3
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V3_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V3_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V4
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V4_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V4_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V5
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V5_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V5_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V6
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V6_gfx10
    UINT64_C(4054056965), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V6_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V7
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V7_gfx10
    UINT64_C(4054056965), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V7_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V8
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V8_gfx10
    UINT64_C(4054056965), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V1_V8_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V2
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V2_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V2_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V3
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V3_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V3_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V4
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V4_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V4_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V5
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V5_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V5_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V6
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V6_gfx10
    UINT64_C(4054056965), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V6_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V7
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V7_gfx10
    UINT64_C(4054056965), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V7_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V8
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V8_gfx10
    UINT64_C(4054056965), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V2_V8_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V2
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V2_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V2_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V3
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V3_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V3_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V4
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V4_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V4_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V5
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V5_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V5_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V6
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V6_gfx10
    UINT64_C(4054056965), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V6_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V7
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V7_gfx10
    UINT64_C(4054056965), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V7_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V8
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V8_gfx10
    UINT64_C(4054056965), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V3_V8_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V2
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V2_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V2_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V3
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V3_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V3_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V4
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V4_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V4_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V5
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V5_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V5_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V6
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V6_gfx10
    UINT64_C(4054056965), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V6_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V7
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V7_gfx10
    UINT64_C(4054056965), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V7_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V8
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V8_gfx10
    UINT64_C(4054056965), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V4_V8_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V2
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V2_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V2_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V3
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V3_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V3_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V4
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V4_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V4_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V5
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V5_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V5_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V6
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V6_gfx10
    UINT64_C(4054056965), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V6_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V7
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V7_gfx10
    UINT64_C(4054056965), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V7_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V8
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V8_gfx10
    UINT64_C(4054056965), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_V5_V8_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_nortn_V2_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_nortn_V2_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_nortn_V3_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_nortn_V3_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_nortn_V4_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_nortn_V4_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_nortn_V5_gfx10
    UINT64_C(4054056963), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_nortn_V5_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_nortn_V6_gfx10
    UINT64_C(4054056965), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_nortn_V6_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_nortn_V7_gfx10
    UINT64_C(4054056965), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_nortn_V7_nsa_gfx10
    UINT64_C(4054056961), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_nortn_V8_gfx10
    UINT64_C(4054056965), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_G16_nortn_V8_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V3
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V3_gfx10
    UINT64_C(4055105539), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V3_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V4
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V4_gfx10
    UINT64_C(4055105539), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V4_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V5
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V5_gfx10
    UINT64_C(4055105539), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V5_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V6
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V6_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V6_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V7
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V7_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V7_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V8
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V8_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V8_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V9
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V9_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V1_V9_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V3
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V3_gfx10
    UINT64_C(4055105539), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V3_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V4
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V4_gfx10
    UINT64_C(4055105539), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V4_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V5
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V5_gfx10
    UINT64_C(4055105539), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V5_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V6
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V6_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V6_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V7
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V7_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V7_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V8
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V8_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V8_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V9
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V9_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V2_V9_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V3
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V3_gfx10
    UINT64_C(4055105539), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V3_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V4
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V4_gfx10
    UINT64_C(4055105539), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V4_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V5
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V5_gfx10
    UINT64_C(4055105539), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V5_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V6
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V6_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V6_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V7
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V7_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V7_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V8
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V8_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V8_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V9
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V9_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V3_V9_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V3
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V3_gfx10
    UINT64_C(4055105539), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V3_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V4
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V4_gfx10
    UINT64_C(4055105539), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V4_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V5
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V5_gfx10
    UINT64_C(4055105539), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V5_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V6
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V6_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V6_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V7
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V7_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V7_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V8
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V8_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V8_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V9
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V9_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V4_V9_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V3
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V3_gfx10
    UINT64_C(4055105539), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V3_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V4
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V4_gfx10
    UINT64_C(4055105539), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V4_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V5
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V5_gfx10
    UINT64_C(4055105539), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V5_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V6
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V6_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V6_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V7
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V7_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V7_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V8
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V8_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V8_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V9
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V9_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_V5_V9_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_nortn_V3_gfx10
    UINT64_C(4055105539), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_nortn_V3_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_nortn_V4_gfx10
    UINT64_C(4055105539), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_nortn_V4_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_nortn_V5_gfx10
    UINT64_C(4055105539), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_nortn_V5_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_nortn_V6_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_nortn_V6_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_nortn_V7_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_nortn_V7_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_nortn_V8_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_nortn_V8_nsa_gfx10
    UINT64_C(4055105537), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_nortn_V9_gfx10
    UINT64_C(4055105541), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_G16_nortn_V9_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V10_gfx10
    UINT64_C(4055105542), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V10_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V11
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V11_gfx10
    UINT64_C(4055105542), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V11_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V3
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V3_gfx10
    UINT64_C(4055105538), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V3_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V4
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V4_gfx10
    UINT64_C(4055105538), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V4_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V5
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V5_gfx10
    UINT64_C(4055105538), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V5_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V6
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V6_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V6_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V7
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V7_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V7_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V8
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V8_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V8_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V9
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V9_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V1_V9_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V10_gfx10
    UINT64_C(4055105542), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V10_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V11
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V11_gfx10
    UINT64_C(4055105542), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V11_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V3
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V3_gfx10
    UINT64_C(4055105538), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V3_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V4
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V4_gfx10
    UINT64_C(4055105538), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V4_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V5
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V5_gfx10
    UINT64_C(4055105538), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V5_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V6
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V6_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V6_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V7
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V7_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V7_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V8
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V8_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V8_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V9
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V9_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V2_V9_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V10_gfx10
    UINT64_C(4055105542), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V10_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V11
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V11_gfx10
    UINT64_C(4055105542), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V11_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V3
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V3_gfx10
    UINT64_C(4055105538), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V3_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V4
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V4_gfx10
    UINT64_C(4055105538), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V4_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V5
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V5_gfx10
    UINT64_C(4055105538), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V5_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V6
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V6_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V6_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V7
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V7_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V7_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V8
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V8_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V8_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V9
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V9_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V3_V9_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V10_gfx10
    UINT64_C(4055105542), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V10_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V11
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V11_gfx10
    UINT64_C(4055105542), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V11_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V3
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V3_gfx10
    UINT64_C(4055105538), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V3_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V4
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V4_gfx10
    UINT64_C(4055105538), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V4_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V5
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V5_gfx10
    UINT64_C(4055105538), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V5_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V6
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V6_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V6_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V7
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V7_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V7_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V8
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V8_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V8_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V9
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V9_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V4_V9_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V10_gfx10
    UINT64_C(4055105542), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V10_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V11
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V11_gfx10
    UINT64_C(4055105542), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V11_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V3
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V3_gfx10
    UINT64_C(4055105538), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V3_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V4
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V4_gfx10
    UINT64_C(4055105538), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V4_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V5
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V5_gfx10
    UINT64_C(4055105538), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V5_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V6
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V6_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V6_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V7
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V7_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V7_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V8
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V8_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V8_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V9
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V9_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_V5_V9_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_nortn_V10_gfx10
    UINT64_C(4055105542), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_nortn_V10_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_nortn_V11_gfx10
    UINT64_C(4055105542), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_nortn_V11_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_nortn_V3_gfx10
    UINT64_C(4055105538), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_nortn_V3_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_nortn_V4_gfx10
    UINT64_C(4055105538), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_nortn_V4_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_nortn_V5_gfx10
    UINT64_C(4055105538), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_nortn_V5_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_nortn_V6_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_nortn_V6_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_nortn_V7_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_nortn_V7_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_nortn_V8_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_nortn_V8_nsa_gfx10
    UINT64_C(4055105536), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_nortn_V9_gfx10
    UINT64_C(4055105540), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_O_nortn_V9_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V10_gfx10
    UINT64_C(4054056966), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V10_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V2
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V2_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V2_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V3
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V3_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V3_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V4
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V4_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V4_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V5
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V5_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V5_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V6
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V6_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V6_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V7
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V7_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V7_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V8
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V8_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V8_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V9
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V9_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V1_V9_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V10_gfx10
    UINT64_C(4054056966), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V10_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V2
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V2_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V2_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V3
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V3_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V3_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V4
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V4_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V4_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V5
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V5_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V5_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V6
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V6_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V6_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V7
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V7_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V7_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V8
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V8_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V8_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V9
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V9_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V2_V9_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V10_gfx10
    UINT64_C(4054056966), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V10_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V2
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V2_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V2_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V3
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V3_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V3_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V4
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V4_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V4_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V5
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V5_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V5_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V6
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V6_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V6_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V7
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V7_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V7_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V8
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V8_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V8_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V9
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V9_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V3_V9_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V10_gfx10
    UINT64_C(4054056966), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V10_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V2
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V2_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V2_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V3
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V3_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V3_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V4
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V4_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V4_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V5
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V5_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V5_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V6
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V6_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V6_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V7
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V7_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V7_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V8
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V8_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V8_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V9
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V9_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V4_V9_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V10_gfx10
    UINT64_C(4054056966), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V10_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V2
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V2_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V2_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V3
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V3_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V3_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V4
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V4_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V4_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V5
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V5_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V5_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V6
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V6_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V6_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V7
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V7_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V7_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V8
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V8_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V8_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V9
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V9_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_V5_V9_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_nortn_V10_gfx10
    UINT64_C(4054056966), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_nortn_V10_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_nortn_V2_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_nortn_V2_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_nortn_V3_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_nortn_V3_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_nortn_V4_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_nortn_V4_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_nortn_V5_gfx10
    UINT64_C(4054056962), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_nortn_V5_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_nortn_V6_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_nortn_V6_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_nortn_V7_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_nortn_V7_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_nortn_V8_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_nortn_V8_nsa_gfx10
    UINT64_C(4054056960), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_nortn_V9_gfx10
    UINT64_C(4054056964), UINT64_C(0),	// IMAGE_SAMPLE_CD_CL_nortn_V9_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V1_V2
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V1_V2_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V1_V2_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V1_V3
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V1_V3_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V1_V3_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V1_V4
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V1_V4_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V1_V4_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V1_V5
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V1_V5_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V1_V5_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V1_V6
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V1_V6_gfx10
    UINT64_C(4053794821), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V1_V6_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V1_V7
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V1_V7_gfx10
    UINT64_C(4053794821), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V1_V7_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V1_V8
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V1_V8_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V2_V2
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V2_V2_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V2_V2_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V2_V3
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V2_V3_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V2_V3_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V2_V4
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V2_V4_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V2_V4_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V2_V5
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V2_V5_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V2_V5_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V2_V6
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V2_V6_gfx10
    UINT64_C(4053794821), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V2_V6_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V2_V7
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V2_V7_gfx10
    UINT64_C(4053794821), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V2_V7_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V2_V8
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V2_V8_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V3_V2
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V3_V2_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V3_V2_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V3_V3
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V3_V3_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V3_V3_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V3_V4
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V3_V4_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V3_V4_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V3_V5
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V3_V5_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V3_V5_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V3_V6
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V3_V6_gfx10
    UINT64_C(4053794821), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V3_V6_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V3_V7
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V3_V7_gfx10
    UINT64_C(4053794821), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V3_V7_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V3_V8
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V3_V8_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V4_V2
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V4_V2_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V4_V2_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V4_V3
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V4_V3_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V4_V3_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V4_V4
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V4_V4_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V4_V4_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V4_V5
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V4_V5_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V4_V5_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V4_V6
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V4_V6_gfx10
    UINT64_C(4053794821), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V4_V6_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V4_V7
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V4_V7_gfx10
    UINT64_C(4053794821), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V4_V7_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V4_V8
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V4_V8_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V5_V2
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V5_V2_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V5_V2_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V5_V3
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V5_V3_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V5_V3_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V5_V4
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V5_V4_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V5_V4_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V5_V5
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V5_V5_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V5_V5_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V5_V6
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V5_V6_gfx10
    UINT64_C(4053794821), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V5_V6_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V5_V7
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V5_V7_gfx10
    UINT64_C(4053794821), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V5_V7_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V5_V8
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_V5_V8_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_nortn_V2_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_nortn_V2_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_nortn_V3_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_nortn_V3_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_nortn_V4_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_nortn_V4_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_nortn_V5_gfx10
    UINT64_C(4053794819), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_nortn_V5_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_nortn_V6_gfx10
    UINT64_C(4053794821), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_nortn_V6_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_nortn_V7_gfx10
    UINT64_C(4053794821), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_nortn_V7_nsa_gfx10
    UINT64_C(4053794817), UINT64_C(0),	// IMAGE_SAMPLE_CD_G16_nortn_V8_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V1_V3
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V1_V3_gfx10
    UINT64_C(4054843395), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V1_V3_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V1_V4
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V1_V4_gfx10
    UINT64_C(4054843395), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V1_V4_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V1_V5
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V1_V5_gfx10
    UINT64_C(4054843395), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V1_V5_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V1_V6
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V1_V6_gfx10
    UINT64_C(4054843397), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V1_V6_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V1_V7
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V1_V7_gfx10
    UINT64_C(4054843397), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V1_V7_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V1_V8
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V1_V8_gfx10
    UINT64_C(4054843397), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V1_V8_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V2_V3
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V2_V3_gfx10
    UINT64_C(4054843395), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V2_V3_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V2_V4
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V2_V4_gfx10
    UINT64_C(4054843395), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V2_V4_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V2_V5
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V2_V5_gfx10
    UINT64_C(4054843395), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V2_V5_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V2_V6
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V2_V6_gfx10
    UINT64_C(4054843397), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V2_V6_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V2_V7
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V2_V7_gfx10
    UINT64_C(4054843397), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V2_V7_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V2_V8
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V2_V8_gfx10
    UINT64_C(4054843397), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V2_V8_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V3_V3
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V3_V3_gfx10
    UINT64_C(4054843395), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V3_V3_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V3_V4
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V3_V4_gfx10
    UINT64_C(4054843395), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V3_V4_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V3_V5
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V3_V5_gfx10
    UINT64_C(4054843395), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V3_V5_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V3_V6
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V3_V6_gfx10
    UINT64_C(4054843397), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V3_V6_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V3_V7
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V3_V7_gfx10
    UINT64_C(4054843397), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V3_V7_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V3_V8
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V3_V8_gfx10
    UINT64_C(4054843397), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V3_V8_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V4_V3
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V4_V3_gfx10
    UINT64_C(4054843395), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V4_V3_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V4_V4
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V4_V4_gfx10
    UINT64_C(4054843395), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V4_V4_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V4_V5
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V4_V5_gfx10
    UINT64_C(4054843395), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V4_V5_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V4_V6
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V4_V6_gfx10
    UINT64_C(4054843397), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V4_V6_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V4_V7
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V4_V7_gfx10
    UINT64_C(4054843397), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V4_V7_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V4_V8
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V4_V8_gfx10
    UINT64_C(4054843397), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V4_V8_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V5_V3
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V5_V3_gfx10
    UINT64_C(4054843395), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V5_V3_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V5_V4
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V5_V4_gfx10
    UINT64_C(4054843395), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V5_V4_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V5_V5
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V5_V5_gfx10
    UINT64_C(4054843395), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V5_V5_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V5_V6
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V5_V6_gfx10
    UINT64_C(4054843397), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V5_V6_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V5_V7
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V5_V7_gfx10
    UINT64_C(4054843397), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V5_V7_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V5_V8
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V5_V8_gfx10
    UINT64_C(4054843397), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_V5_V8_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_nortn_V3_gfx10
    UINT64_C(4054843395), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_nortn_V3_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_nortn_V4_gfx10
    UINT64_C(4054843395), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_nortn_V4_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_nortn_V5_gfx10
    UINT64_C(4054843395), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_nortn_V5_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_nortn_V6_gfx10
    UINT64_C(4054843397), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_nortn_V6_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_nortn_V7_gfx10
    UINT64_C(4054843397), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_nortn_V7_nsa_gfx10
    UINT64_C(4054843393), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_nortn_V8_gfx10
    UINT64_C(4054843397), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_G16_nortn_V8_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V10_gfx10
    UINT64_C(4054843398), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V10_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V3
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V3_gfx10
    UINT64_C(4054843394), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V3_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V4
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V4_gfx10
    UINT64_C(4054843394), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V4_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V5
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V5_gfx10
    UINT64_C(4054843394), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V5_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V6
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V6_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V6_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V7
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V7_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V7_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V8
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V8_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V8_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V9
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V9_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V1_V9_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V10_gfx10
    UINT64_C(4054843398), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V10_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V3
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V3_gfx10
    UINT64_C(4054843394), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V3_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V4
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V4_gfx10
    UINT64_C(4054843394), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V4_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V5
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V5_gfx10
    UINT64_C(4054843394), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V5_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V6
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V6_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V6_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V7
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V7_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V7_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V8
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V8_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V8_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V9
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V9_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V2_V9_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V10_gfx10
    UINT64_C(4054843398), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V10_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V3
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V3_gfx10
    UINT64_C(4054843394), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V3_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V4
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V4_gfx10
    UINT64_C(4054843394), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V4_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V5
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V5_gfx10
    UINT64_C(4054843394), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V5_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V6
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V6_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V6_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V7
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V7_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V7_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V8
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V8_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V8_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V9
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V9_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V3_V9_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V10_gfx10
    UINT64_C(4054843398), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V10_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V3
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V3_gfx10
    UINT64_C(4054843394), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V3_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V4
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V4_gfx10
    UINT64_C(4054843394), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V4_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V5
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V5_gfx10
    UINT64_C(4054843394), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V5_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V6
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V6_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V6_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V7
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V7_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V7_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V8
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V8_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V8_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V9
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V9_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V4_V9_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V10_gfx10
    UINT64_C(4054843398), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V10_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V3
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V3_gfx10
    UINT64_C(4054843394), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V3_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V4
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V4_gfx10
    UINT64_C(4054843394), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V4_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V5
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V5_gfx10
    UINT64_C(4054843394), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V5_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V6
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V6_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V6_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V7
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V7_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V7_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V8
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V8_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V8_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V9
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V9_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_V5_V9_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_nortn_V10_gfx10
    UINT64_C(4054843398), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_nortn_V10_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_nortn_V3_gfx10
    UINT64_C(4054843394), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_nortn_V3_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_nortn_V4_gfx10
    UINT64_C(4054843394), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_nortn_V4_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_nortn_V5_gfx10
    UINT64_C(4054843394), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_nortn_V5_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_nortn_V6_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_nortn_V6_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_nortn_V7_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_nortn_V7_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_nortn_V8_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_nortn_V8_nsa_gfx10
    UINT64_C(4054843392), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_nortn_V9_gfx10
    UINT64_C(4054843396), UINT64_C(0),	// IMAGE_SAMPLE_CD_O_nortn_V9_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V2
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V2_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V2_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V3
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V3_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V3_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V4
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V4_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V4_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V5
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V5_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V5_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V6
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V6_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V6_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V7
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V7_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V7_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V8
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V8_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V8_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V9
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V9_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_V1_V9_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V2
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V2_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V2_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V3
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V3_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V3_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V4
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V4_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V4_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V5
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V5_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V5_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V6
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V6_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V6_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V7
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V7_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V7_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V8
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V8_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V8_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V9
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V9_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_V2_V9_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V2
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V2_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V2_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V3
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V3_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V3_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V4
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V4_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V4_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V5
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V5_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V5_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V6
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V6_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V6_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V7
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V7_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V7_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V8
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V8_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V8_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V9
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V9_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_V3_V9_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V2
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V2_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V2_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V3
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V3_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V3_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V4
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V4_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V4_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V5
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V5_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V5_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V6
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V6_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V6_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V7
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V7_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V7_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V8
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V8_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V8_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V9
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V9_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_V4_V9_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V2
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V2_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V2_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V3
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V3_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V3_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V4
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V4_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V4_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V5
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V5_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V5_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V6
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V6_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V6_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V7
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V7_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V7_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V8
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V8_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V8_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V9
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V9_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_V5_V9_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_nortn_V2_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_nortn_V2_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_nortn_V3_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_nortn_V3_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_nortn_V4_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_nortn_V4_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_nortn_V5_gfx10
    UINT64_C(4053794818), UINT64_C(0),	// IMAGE_SAMPLE_CD_nortn_V5_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_nortn_V6_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_nortn_V6_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_nortn_V7_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_nortn_V7_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_nortn_V8_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_nortn_V8_nsa_gfx10
    UINT64_C(4053794816), UINT64_C(0),	// IMAGE_SAMPLE_CD_nortn_V9_gfx10
    UINT64_C(4053794820), UINT64_C(0),	// IMAGE_SAMPLE_CD_nortn_V9_nsa_gfx10
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V2
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V2_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V2_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V2_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V2_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V2_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V3
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V3_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V3_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V3_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V3_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V3_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V4
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V4_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V4_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V4_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V4_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V4_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V5
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V5_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V5_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V5_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V5_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V5_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V8
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V8_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V1_V8_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V2
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V2_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V2_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V2_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V2_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V2_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V3
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V3_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V3_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V3_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V3_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V3_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V4
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V4_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V4_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V4_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V4_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V4_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V5
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V5_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V5_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V5_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V5_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V5_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V8
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V8_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V2_V8_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V2
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V2_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V2_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V2_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V2_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V2_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V3
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V3_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V3_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V3_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V3_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V3_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V4
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V4_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V4_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V4_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V4_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V4_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V5
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V5_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V5_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V5_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V5_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V5_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V8
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V8_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V3_V8_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V2
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V2_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V2_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V2_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V2_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V2_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V3
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V3_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V3_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V3_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V3_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V3_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V4
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V4_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V4_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V4_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V4_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V4_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V5
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V5_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V5_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V5_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V5_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V5_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V8
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V8_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V4_V8_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V2
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V2_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V2_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V2_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V2_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V2_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V3
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V3_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V3_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V3_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V3_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V3_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V4
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V4_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V4_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V4_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V4_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V4_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V5
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V5_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V5_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V5_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V5_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V5_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V8
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V8_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_V5_V8_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V2_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V2_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V2_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V2_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V2_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V3_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V3_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V3_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V3_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V3_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V4_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V4_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V4_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V4_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V4_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V5_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V5_gfx11
    UINT64_C(3826352128), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V5_gfx12
    UINT64_C(4039376898), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V5_nsa_gfx10
    UINT64_C(4044881921), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V5_nsa_gfx11
    UINT64_C(4039376896), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V8_gfx10
    UINT64_C(4044881920), UINT64_C(0),	// IMAGE_SAMPLE_CL_O_nortn_V8_gfx11
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V1
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V1_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V1_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V1_gfx12
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V2
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V2_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V2_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V2_gfx12
    UINT64_C(4035182594), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V2_nsa_gfx10
    UINT64_C(4043309057), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V2_nsa_gfx11
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V3
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V3_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V3_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V3_gfx12
    UINT64_C(4035182594), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V3_nsa_gfx10
    UINT64_C(4043309057), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V3_nsa_gfx11
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V4
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V4_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V4_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V4_gfx12
    UINT64_C(4035182594), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V4_nsa_gfx10
    UINT64_C(4043309057), UINT64_C(0),	// IMAGE_SAMPLE_CL_V1_V4_nsa_gfx11
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V1
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V1_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V1_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V1_gfx12
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V2
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V2_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V2_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V2_gfx12
    UINT64_C(4035182594), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V2_nsa_gfx10
    UINT64_C(4043309057), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V2_nsa_gfx11
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V3
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V3_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V3_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V3_gfx12
    UINT64_C(4035182594), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V3_nsa_gfx10
    UINT64_C(4043309057), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V3_nsa_gfx11
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V4
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V4_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V4_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V4_gfx12
    UINT64_C(4035182594), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V4_nsa_gfx10
    UINT64_C(4043309057), UINT64_C(0),	// IMAGE_SAMPLE_CL_V2_V4_nsa_gfx11
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V1
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V1_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V1_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V1_gfx12
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V2
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V2_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V2_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V2_gfx12
    UINT64_C(4035182594), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V2_nsa_gfx10
    UINT64_C(4043309057), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V2_nsa_gfx11
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V3
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V3_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V3_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V3_gfx12
    UINT64_C(4035182594), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V3_nsa_gfx10
    UINT64_C(4043309057), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V3_nsa_gfx11
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V4
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V4_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V4_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V4_gfx12
    UINT64_C(4035182594), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V4_nsa_gfx10
    UINT64_C(4043309057), UINT64_C(0),	// IMAGE_SAMPLE_CL_V3_V4_nsa_gfx11
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V1
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V1_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V1_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V1_gfx12
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V2
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V2_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V2_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V2_gfx12
    UINT64_C(4035182594), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V2_nsa_gfx10
    UINT64_C(4043309057), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V2_nsa_gfx11
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V3
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V3_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V3_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V3_gfx12
    UINT64_C(4035182594), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V3_nsa_gfx10
    UINT64_C(4043309057), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V3_nsa_gfx11
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V4
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V4_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V4_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V4_gfx12
    UINT64_C(4035182594), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V4_nsa_gfx10
    UINT64_C(4043309057), UINT64_C(0),	// IMAGE_SAMPLE_CL_V4_V4_nsa_gfx11
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V1
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V1_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V1_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V1_gfx12
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V2
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V2_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V2_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V2_gfx12
    UINT64_C(4035182594), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V2_nsa_gfx10
    UINT64_C(4043309057), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V2_nsa_gfx11
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V3
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V3_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V3_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V3_gfx12
    UINT64_C(4035182594), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V3_nsa_gfx10
    UINT64_C(4043309057), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V3_nsa_gfx11
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V4
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V4_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V4_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V4_gfx12
    UINT64_C(4035182594), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V4_nsa_gfx10
    UINT64_C(4043309057), UINT64_C(0),	// IMAGE_SAMPLE_CL_V5_V4_nsa_gfx11
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_nortn_V1_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_nortn_V1_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_nortn_V1_gfx12
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_nortn_V2_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_nortn_V2_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_nortn_V2_gfx12
    UINT64_C(4035182594), UINT64_C(0),	// IMAGE_SAMPLE_CL_nortn_V2_nsa_gfx10
    UINT64_C(4043309057), UINT64_C(0),	// IMAGE_SAMPLE_CL_nortn_V2_nsa_gfx11
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_nortn_V3_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_nortn_V3_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_nortn_V3_gfx12
    UINT64_C(4035182594), UINT64_C(0),	// IMAGE_SAMPLE_CL_nortn_V3_nsa_gfx10
    UINT64_C(4043309057), UINT64_C(0),	// IMAGE_SAMPLE_CL_nortn_V3_nsa_gfx11
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_CL_nortn_V4_gfx10
    UINT64_C(4043309056), UINT64_C(0),	// IMAGE_SAMPLE_CL_nortn_V4_gfx11
    UINT64_C(3826253824), UINT64_C(0),	// IMAGE_SAMPLE_CL_nortn_V4_gfx12
    UINT64_C(4035182594), UINT64_C(0),	// IMAGE_SAMPLE_CL_nortn_V4_nsa_gfx10
    UINT64_C(4043309057), UINT64_C(0),	// IMAGE_SAMPLE_CL_nortn_V4_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V4
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V4_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V4_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V4_gfx12
    UINT64_C(4042784770), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V4_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V4_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V5
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V5_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V5_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V5_gfx12
    UINT64_C(4042784770), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V5_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V5_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V6
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V6_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V6_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V6_gfx12
    UINT64_C(4042784772), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V6_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V6_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V7
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V7_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V7_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V7_gfx12
    UINT64_C(4042784772), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V7_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V7_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V8
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V8_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V1_V8_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V4
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V4_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V4_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V4_gfx12
    UINT64_C(4042784770), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V4_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V4_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V5
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V5_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V5_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V5_gfx12
    UINT64_C(4042784770), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V5_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V5_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V6
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V6_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V6_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V6_gfx12
    UINT64_C(4042784772), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V6_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V6_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V7
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V7_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V7_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V7_gfx12
    UINT64_C(4042784772), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V7_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V7_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V8
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V8_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V2_V8_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V4
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V4_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V4_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V4_gfx12
    UINT64_C(4042784770), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V4_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V4_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V5
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V5_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V5_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V5_gfx12
    UINT64_C(4042784770), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V5_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V5_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V6
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V6_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V6_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V6_gfx12
    UINT64_C(4042784772), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V6_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V6_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V7
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V7_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V7_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V7_gfx12
    UINT64_C(4042784772), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V7_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V7_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V8
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V8_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V3_V8_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V4
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V4_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V4_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V4_gfx12
    UINT64_C(4042784770), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V4_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V4_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V5
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V5_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V5_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V5_gfx12
    UINT64_C(4042784770), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V5_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V5_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V6
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V6_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V6_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V6_gfx12
    UINT64_C(4042784772), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V6_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V6_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V7
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V7_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V7_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V7_gfx12
    UINT64_C(4042784772), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V7_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V7_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V8
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V8_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V4_V8_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V4
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V4_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V4_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V4_gfx12
    UINT64_C(4042784770), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V4_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V4_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V5
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V5_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V5_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V5_gfx12
    UINT64_C(4042784770), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V5_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V5_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V6
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V6_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V6_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V6_gfx12
    UINT64_C(4042784772), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V6_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V6_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V7
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V7_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V7_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V7_gfx12
    UINT64_C(4042784772), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V7_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V7_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V8
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V8_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_V5_V8_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V4_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V4_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V4_gfx12
    UINT64_C(4042784770), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V4_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V4_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V5_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V5_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V5_gfx12
    UINT64_C(4042784770), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V5_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V5_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V6_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V6_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V6_gfx12
    UINT64_C(4042784772), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V6_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V6_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V7_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V7_gfx11
    UINT64_C(3826434048), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V7_gfx12
    UINT64_C(4042784772), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V7_nsa_gfx10
    UINT64_C(4046192641), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V7_nsa_gfx11
    UINT64_C(4042784768), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V8_gfx10
    UINT64_C(4046192640), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_O_nortn_V8_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V3
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V3_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V3_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V3_gfx12
    UINT64_C(4038590466), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V3_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V3_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V4
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V4_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V4_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V4_gfx12
    UINT64_C(4038590466), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V4_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V4_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V5
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V5_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V5_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V5_gfx12
    UINT64_C(4038590466), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V5_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V5_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V6
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V6_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V6_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V6_gfx12
    UINT64_C(4038590468), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V6_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V6_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V8
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V8_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V1_V8_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V3
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V3_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V3_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V3_gfx12
    UINT64_C(4038590466), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V3_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V3_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V4
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V4_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V4_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V4_gfx12
    UINT64_C(4038590466), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V4_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V4_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V5
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V5_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V5_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V5_gfx12
    UINT64_C(4038590466), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V5_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V5_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V6
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V6_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V6_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V6_gfx12
    UINT64_C(4038590468), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V6_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V6_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V8
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V8_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V2_V8_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V3
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V3_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V3_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V3_gfx12
    UINT64_C(4038590466), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V3_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V3_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V4
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V4_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V4_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V4_gfx12
    UINT64_C(4038590466), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V4_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V4_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V5
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V5_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V5_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V5_gfx12
    UINT64_C(4038590466), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V5_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V5_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V6
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V6_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V6_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V6_gfx12
    UINT64_C(4038590468), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V6_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V6_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V8
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V8_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V3_V8_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V3
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V3_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V3_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V3_gfx12
    UINT64_C(4038590466), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V3_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V3_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V4
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V4_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V4_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V4_gfx12
    UINT64_C(4038590466), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V4_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V4_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V5
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V5_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V5_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V5_gfx12
    UINT64_C(4038590466), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V5_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V5_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V6
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V6_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V6_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V6_gfx12
    UINT64_C(4038590468), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V6_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V6_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V8
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V8_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V4_V8_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V3
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V3_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V3_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V3_gfx12
    UINT64_C(4038590466), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V3_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V3_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V4
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V4_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V4_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V4_gfx12
    UINT64_C(4038590466), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V4_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V4_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V5
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V5_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V5_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V5_gfx12
    UINT64_C(4038590466), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V5_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V5_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V6
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V6_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V6_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V6_gfx12
    UINT64_C(4038590468), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V6_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V6_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V8
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V8_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_V5_V8_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V3_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V3_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V3_gfx12
    UINT64_C(4038590466), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V3_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V3_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V4_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V4_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V4_gfx12
    UINT64_C(4038590466), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V4_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V4_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V5_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V5_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V5_gfx12
    UINT64_C(4038590466), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V5_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V5_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V6_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V6_gfx11
    UINT64_C(3826335744), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V6_gfx12
    UINT64_C(4038590468), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V6_nsa_gfx10
    UINT64_C(4044619777), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V6_nsa_gfx11
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V8_gfx10
    UINT64_C(4044619776), UINT64_C(0),	// IMAGE_SAMPLE_C_B_CL_nortn_V8_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V4
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V4_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V4_gfx11
    UINT64_C(3825942528), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V4_gfx12
    UINT64_C(4042522626), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V4_nsa_gfx10
    UINT64_C(4038328321), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V4_nsa_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V5
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V5_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V5_gfx11
    UINT64_C(3825942528), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V5_gfx12
    UINT64_C(4042522626), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V5_nsa_gfx10
    UINT64_C(4038328321), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V5_nsa_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V6
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V6_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V6_gfx11
    UINT64_C(3825942528), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V6_gfx12
    UINT64_C(4042522628), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V6_nsa_gfx10
    UINT64_C(4038328321), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V6_nsa_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V8
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V8_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V1_V8_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V4
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V4_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V4_gfx11
    UINT64_C(3825942528), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V4_gfx12
    UINT64_C(4042522626), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V4_nsa_gfx10
    UINT64_C(4038328321), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V4_nsa_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V5
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V5_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V5_gfx11
    UINT64_C(3825942528), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V5_gfx12
    UINT64_C(4042522626), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V5_nsa_gfx10
    UINT64_C(4038328321), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V5_nsa_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V6
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V6_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V6_gfx11
    UINT64_C(3825942528), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V6_gfx12
    UINT64_C(4042522628), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V6_nsa_gfx10
    UINT64_C(4038328321), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V6_nsa_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V8
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V8_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V2_V8_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V4
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V4_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V4_gfx11
    UINT64_C(3825942528), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V4_gfx12
    UINT64_C(4042522626), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V4_nsa_gfx10
    UINT64_C(4038328321), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V4_nsa_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V5
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V5_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V5_gfx11
    UINT64_C(3825942528), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V5_gfx12
    UINT64_C(4042522626), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V5_nsa_gfx10
    UINT64_C(4038328321), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V5_nsa_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V6
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V6_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V6_gfx11
    UINT64_C(3825942528), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V6_gfx12
    UINT64_C(4042522628), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V6_nsa_gfx10
    UINT64_C(4038328321), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V6_nsa_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V8
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V8_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V3_V8_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V4
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V4_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V4_gfx11
    UINT64_C(3825942528), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V4_gfx12
    UINT64_C(4042522626), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V4_nsa_gfx10
    UINT64_C(4038328321), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V4_nsa_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V5
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V5_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V5_gfx11
    UINT64_C(3825942528), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V5_gfx12
    UINT64_C(4042522626), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V5_nsa_gfx10
    UINT64_C(4038328321), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V5_nsa_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V6
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V6_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V6_gfx11
    UINT64_C(3825942528), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V6_gfx12
    UINT64_C(4042522628), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V6_nsa_gfx10
    UINT64_C(4038328321), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V6_nsa_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V8
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V8_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V4_V8_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V4
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V4_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V4_gfx11
    UINT64_C(3825942528), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V4_gfx12
    UINT64_C(4042522626), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V4_nsa_gfx10
    UINT64_C(4038328321), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V4_nsa_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V5
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V5_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V5_gfx11
    UINT64_C(3825942528), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V5_gfx12
    UINT64_C(4042522626), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V5_nsa_gfx10
    UINT64_C(4038328321), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V5_nsa_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V6
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V6_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V6_gfx11
    UINT64_C(3825942528), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V6_gfx12
    UINT64_C(4042522628), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V6_nsa_gfx10
    UINT64_C(4038328321), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V6_nsa_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V8
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V8_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_V5_V8_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_nortn_V4_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_nortn_V4_gfx11
    UINT64_C(3825942528), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_nortn_V4_gfx12
    UINT64_C(4042522626), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_nortn_V4_nsa_gfx10
    UINT64_C(4038328321), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_nortn_V4_nsa_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_nortn_V5_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_nortn_V5_gfx11
    UINT64_C(3825942528), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_nortn_V5_gfx12
    UINT64_C(4042522626), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_nortn_V5_nsa_gfx10
    UINT64_C(4038328321), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_nortn_V5_nsa_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_nortn_V6_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_nortn_V6_gfx11
    UINT64_C(3825942528), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_nortn_V6_gfx12
    UINT64_C(4042522628), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_nortn_V6_nsa_gfx10
    UINT64_C(4038328321), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_nortn_V6_nsa_gfx11
    UINT64_C(4042522624), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_nortn_V8_gfx10
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_O_nortn_V8_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V3
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V3_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V3_gfx11
    UINT64_C(3825778688), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V3_gfx12
    UINT64_C(4038328322), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V3_nsa_gfx10
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V3_nsa_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V4
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V4_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V4_gfx11
    UINT64_C(3825778688), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V4_gfx12
    UINT64_C(4038328322), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V4_nsa_gfx10
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V4_nsa_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V5
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V5_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V5_gfx11
    UINT64_C(3825778688), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V5_gfx12
    UINT64_C(4038328322), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V5_nsa_gfx10
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V5_nsa_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V8
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V8_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V1_V8_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V3
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V3_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V3_gfx11
    UINT64_C(3825778688), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V3_gfx12
    UINT64_C(4038328322), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V3_nsa_gfx10
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V3_nsa_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V4
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V4_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V4_gfx11
    UINT64_C(3825778688), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V4_gfx12
    UINT64_C(4038328322), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V4_nsa_gfx10
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V4_nsa_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V5
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V5_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V5_gfx11
    UINT64_C(3825778688), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V5_gfx12
    UINT64_C(4038328322), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V5_nsa_gfx10
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V5_nsa_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V8
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V8_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V2_V8_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V3
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V3_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V3_gfx11
    UINT64_C(3825778688), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V3_gfx12
    UINT64_C(4038328322), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V3_nsa_gfx10
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V3_nsa_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V4
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V4_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V4_gfx11
    UINT64_C(3825778688), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V4_gfx12
    UINT64_C(4038328322), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V4_nsa_gfx10
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V4_nsa_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V5
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V5_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V5_gfx11
    UINT64_C(3825778688), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V5_gfx12
    UINT64_C(4038328322), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V5_nsa_gfx10
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V5_nsa_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V8
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V8_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V3_V8_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V3
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V3_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V3_gfx11
    UINT64_C(3825778688), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V3_gfx12
    UINT64_C(4038328322), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V3_nsa_gfx10
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V3_nsa_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V4
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V4_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V4_gfx11
    UINT64_C(3825778688), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V4_gfx12
    UINT64_C(4038328322), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V4_nsa_gfx10
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V4_nsa_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V5
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V5_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V5_gfx11
    UINT64_C(3825778688), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V5_gfx12
    UINT64_C(4038328322), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V5_nsa_gfx10
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V5_nsa_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V8
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V8_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V4_V8_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V3
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V3_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V3_gfx11
    UINT64_C(3825778688), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V3_gfx12
    UINT64_C(4038328322), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V3_nsa_gfx10
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V3_nsa_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V4
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V4_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V4_gfx11
    UINT64_C(3825778688), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V4_gfx12
    UINT64_C(4038328322), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V4_nsa_gfx10
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V4_nsa_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V5
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V5_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V5_gfx11
    UINT64_C(3825778688), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V5_gfx12
    UINT64_C(4038328322), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V5_nsa_gfx10
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V5_nsa_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V8
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V8_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_V5_V8_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_nortn_V3_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_nortn_V3_gfx11
    UINT64_C(3825778688), UINT64_C(0),	// IMAGE_SAMPLE_C_B_nortn_V3_gfx12
    UINT64_C(4038328322), UINT64_C(0),	// IMAGE_SAMPLE_C_B_nortn_V3_nsa_gfx10
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_C_B_nortn_V3_nsa_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_nortn_V4_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_nortn_V4_gfx11
    UINT64_C(3825778688), UINT64_C(0),	// IMAGE_SAMPLE_C_B_nortn_V4_gfx12
    UINT64_C(4038328322), UINT64_C(0),	// IMAGE_SAMPLE_C_B_nortn_V4_nsa_gfx10
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_C_B_nortn_V4_nsa_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_nortn_V5_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_nortn_V5_gfx11
    UINT64_C(3825778688), UINT64_C(0),	// IMAGE_SAMPLE_C_B_nortn_V5_gfx12
    UINT64_C(4038328322), UINT64_C(0),	// IMAGE_SAMPLE_C_B_nortn_V5_nsa_gfx10
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_C_B_nortn_V5_nsa_gfx11
    UINT64_C(4038328320), UINT64_C(0),	// IMAGE_SAMPLE_C_B_nortn_V8_gfx10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_C_B_nortn_V8_gfx11
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V3
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V3_gfx10
    UINT64_C(4054581251), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V3_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V4
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V4_gfx10
    UINT64_C(4054581251), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V4_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V5
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V5_gfx10
    UINT64_C(4054581251), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V5_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V6
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V6_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V6_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V7
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V7_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V7_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V8
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V8_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V8_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V9
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V9_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V1_V9_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V3
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V3_gfx10
    UINT64_C(4054581251), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V3_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V4
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V4_gfx10
    UINT64_C(4054581251), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V4_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V5
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V5_gfx10
    UINT64_C(4054581251), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V5_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V6
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V6_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V6_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V7
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V7_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V7_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V8
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V8_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V8_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V9
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V9_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V2_V9_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V3
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V3_gfx10
    UINT64_C(4054581251), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V3_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V4
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V4_gfx10
    UINT64_C(4054581251), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V4_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V5
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V5_gfx10
    UINT64_C(4054581251), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V5_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V6
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V6_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V6_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V7
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V7_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V7_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V8
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V8_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V8_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V9
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V9_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V3_V9_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V3
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V3_gfx10
    UINT64_C(4054581251), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V3_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V4
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V4_gfx10
    UINT64_C(4054581251), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V4_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V5
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V5_gfx10
    UINT64_C(4054581251), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V5_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V6
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V6_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V6_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V7
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V7_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V7_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V8
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V8_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V8_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V9
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V9_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V4_V9_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V3
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V3_gfx10
    UINT64_C(4054581251), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V3_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V4
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V4_gfx10
    UINT64_C(4054581251), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V4_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V5
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V5_gfx10
    UINT64_C(4054581251), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V5_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V6
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V6_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V6_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V7
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V7_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V7_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V8
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V8_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V8_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V9
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V9_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_V5_V9_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_nortn_V3_gfx10
    UINT64_C(4054581251), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_nortn_V3_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_nortn_V4_gfx10
    UINT64_C(4054581251), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_nortn_V4_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_nortn_V5_gfx10
    UINT64_C(4054581251), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_nortn_V5_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_nortn_V6_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_nortn_V6_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_nortn_V7_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_nortn_V7_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_nortn_V8_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_nortn_V8_nsa_gfx10
    UINT64_C(4054581249), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_nortn_V9_gfx10
    UINT64_C(4054581253), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_G16_nortn_V9_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V10_gfx10
    UINT64_C(4055629831), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V10_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V4
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V4_gfx10
    UINT64_C(4055629827), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V4_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V5
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V5_gfx10
    UINT64_C(4055629827), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V5_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V6
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V6_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V6_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V7
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V7_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V7_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V8
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V8_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V8_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V9
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V9_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V9_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V10_gfx10
    UINT64_C(4055629831), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V10_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V4
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V4_gfx10
    UINT64_C(4055629827), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V4_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V5
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V5_gfx10
    UINT64_C(4055629827), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V5_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V6
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V6_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V6_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V7
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V7_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V7_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V8
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V8_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V8_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V9
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V9_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V9_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V10_gfx10
    UINT64_C(4055629831), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V10_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V4
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V4_gfx10
    UINT64_C(4055629827), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V4_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V5
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V5_gfx10
    UINT64_C(4055629827), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V5_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V6
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V6_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V6_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V7
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V7_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V7_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V8
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V8_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V8_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V9
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V9_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V9_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V10_gfx10
    UINT64_C(4055629831), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V10_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V4
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V4_gfx10
    UINT64_C(4055629827), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V4_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V5
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V5_gfx10
    UINT64_C(4055629827), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V5_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V6
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V6_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V6_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V7
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V7_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V7_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V8
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V8_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V8_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V9
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V9_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V9_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V10_gfx10
    UINT64_C(4055629831), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V10_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V4
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V4_gfx10
    UINT64_C(4055629827), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V4_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V5
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V5_gfx10
    UINT64_C(4055629827), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V5_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V6
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V6_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V6_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V7
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V7_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V7_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V8
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V8_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V8_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V9
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V9_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V9_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V10_gfx10
    UINT64_C(4055629831), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V10_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V4_gfx10
    UINT64_C(4055629827), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V4_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V5_gfx10
    UINT64_C(4055629827), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V5_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V6_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V6_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V7_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V7_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V8_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V8_nsa_gfx10
    UINT64_C(4055629825), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V9_gfx10
    UINT64_C(4055629829), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V9_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V10_gfx10
    UINT64_C(4055629830), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V10_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V11
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V11_gfx10
    UINT64_C(4055629830), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V11_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V12
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V12_gfx10
    UINT64_C(4055629830), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V12_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V4
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V4_gfx10
    UINT64_C(4055629826), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V4_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V5
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V5_gfx10
    UINT64_C(4055629826), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V5_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V6
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V6_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V6_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V7
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V7_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V7_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V8
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V8_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V8_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V9
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V9_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V1_V9_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V10_gfx10
    UINT64_C(4055629830), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V10_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V11
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V11_gfx10
    UINT64_C(4055629830), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V11_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V12
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V12_gfx10
    UINT64_C(4055629830), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V12_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V4
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V4_gfx10
    UINT64_C(4055629826), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V4_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V5
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V5_gfx10
    UINT64_C(4055629826), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V5_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V6
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V6_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V6_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V7
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V7_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V7_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V8
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V8_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V8_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V9
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V9_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V2_V9_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V10_gfx10
    UINT64_C(4055629830), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V10_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V11
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V11_gfx10
    UINT64_C(4055629830), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V11_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V12
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V12_gfx10
    UINT64_C(4055629830), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V12_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V4
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V4_gfx10
    UINT64_C(4055629826), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V4_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V5
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V5_gfx10
    UINT64_C(4055629826), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V5_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V6
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V6_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V6_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V7
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V7_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V7_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V8
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V8_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V8_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V9
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V9_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V3_V9_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V10_gfx10
    UINT64_C(4055629830), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V10_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V11
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V11_gfx10
    UINT64_C(4055629830), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V11_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V12
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V12_gfx10
    UINT64_C(4055629830), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V12_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V4
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V4_gfx10
    UINT64_C(4055629826), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V4_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V5
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V5_gfx10
    UINT64_C(4055629826), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V5_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V6
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V6_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V6_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V7
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V7_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V7_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V8
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V8_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V8_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V9
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V9_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V4_V9_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V10_gfx10
    UINT64_C(4055629830), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V10_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V11
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V11_gfx10
    UINT64_C(4055629830), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V11_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V12
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V12_gfx10
    UINT64_C(4055629830), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V12_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V4
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V4_gfx10
    UINT64_C(4055629826), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V4_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V5
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V5_gfx10
    UINT64_C(4055629826), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V5_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V6
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V6_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V6_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V7
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V7_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V7_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V8
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V8_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V8_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V9
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V9_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_V5_V9_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_nortn_V10_gfx10
    UINT64_C(4055629830), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_nortn_V10_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_nortn_V11_gfx10
    UINT64_C(4055629830), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_nortn_V11_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_nortn_V12_gfx10
    UINT64_C(4055629830), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_nortn_V12_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_nortn_V4_gfx10
    UINT64_C(4055629826), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_nortn_V4_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_nortn_V5_gfx10
    UINT64_C(4055629826), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_nortn_V5_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_nortn_V6_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_nortn_V6_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_nortn_V7_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_nortn_V7_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_nortn_V8_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_nortn_V8_nsa_gfx10
    UINT64_C(4055629824), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_nortn_V9_gfx10
    UINT64_C(4055629828), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_O_nortn_V9_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V10_gfx10
    UINT64_C(4054581254), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V10_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V11
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V11_gfx10
    UINT64_C(4054581254), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V11_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V3
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V3_gfx10
    UINT64_C(4054581250), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V3_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V4
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V4_gfx10
    UINT64_C(4054581250), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V4_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V5
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V5_gfx10
    UINT64_C(4054581250), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V5_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V6
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V6_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V6_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V7
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V7_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V7_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V8
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V8_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V8_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V9
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V9_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V1_V9_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V10_gfx10
    UINT64_C(4054581254), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V10_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V11
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V11_gfx10
    UINT64_C(4054581254), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V11_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V3
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V3_gfx10
    UINT64_C(4054581250), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V3_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V4
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V4_gfx10
    UINT64_C(4054581250), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V4_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V5
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V5_gfx10
    UINT64_C(4054581250), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V5_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V6
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V6_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V6_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V7
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V7_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V7_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V8
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V8_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V8_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V9
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V9_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V2_V9_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V10_gfx10
    UINT64_C(4054581254), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V10_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V11
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V11_gfx10
    UINT64_C(4054581254), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V11_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V3
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V3_gfx10
    UINT64_C(4054581250), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V3_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V4
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V4_gfx10
    UINT64_C(4054581250), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V4_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V5
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V5_gfx10
    UINT64_C(4054581250), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V5_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V6
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V6_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V6_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V7
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V7_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V7_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V8
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V8_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V8_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V9
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V9_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V3_V9_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V10_gfx10
    UINT64_C(4054581254), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V10_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V11
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V11_gfx10
    UINT64_C(4054581254), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V11_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V3
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V3_gfx10
    UINT64_C(4054581250), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V3_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V4
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V4_gfx10
    UINT64_C(4054581250), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V4_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V5
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V5_gfx10
    UINT64_C(4054581250), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V5_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V6
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V6_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V6_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V7
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V7_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V7_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V8
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V8_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V8_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V9
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V9_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V4_V9_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V10_gfx10
    UINT64_C(4054581254), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V10_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V11
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V11_gfx10
    UINT64_C(4054581254), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V11_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V3
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V3_gfx10
    UINT64_C(4054581250), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V3_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V4
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V4_gfx10
    UINT64_C(4054581250), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V4_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V5
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V5_gfx10
    UINT64_C(4054581250), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V5_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V6
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V6_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V6_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V7
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V7_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V7_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V8
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V8_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V8_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V9
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V9_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_V5_V9_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_nortn_V10_gfx10
    UINT64_C(4054581254), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_nortn_V10_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_nortn_V11_gfx10
    UINT64_C(4054581254), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_nortn_V11_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_nortn_V3_gfx10
    UINT64_C(4054581250), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_nortn_V3_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_nortn_V4_gfx10
    UINT64_C(4054581250), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_nortn_V4_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_nortn_V5_gfx10
    UINT64_C(4054581250), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_nortn_V5_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_nortn_V6_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_nortn_V6_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_nortn_V7_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_nortn_V7_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_nortn_V8_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_nortn_V8_nsa_gfx10
    UINT64_C(4054581248), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_nortn_V9_gfx10
    UINT64_C(4054581252), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_CL_nortn_V9_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V1_V3
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V1_V3_gfx10
    UINT64_C(4054319107), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V1_V3_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V1_V4
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V1_V4_gfx10
    UINT64_C(4054319107), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V1_V4_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V1_V5
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V1_V5_gfx10
    UINT64_C(4054319107), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V1_V5_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V1_V6
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V1_V6_gfx10
    UINT64_C(4054319109), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V1_V6_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V1_V7
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V1_V7_gfx10
    UINT64_C(4054319109), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V1_V7_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V1_V8
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V1_V8_gfx10
    UINT64_C(4054319109), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V1_V8_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V2_V3
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V2_V3_gfx10
    UINT64_C(4054319107), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V2_V3_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V2_V4
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V2_V4_gfx10
    UINT64_C(4054319107), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V2_V4_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V2_V5
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V2_V5_gfx10
    UINT64_C(4054319107), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V2_V5_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V2_V6
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V2_V6_gfx10
    UINT64_C(4054319109), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V2_V6_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V2_V7
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V2_V7_gfx10
    UINT64_C(4054319109), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V2_V7_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V2_V8
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V2_V8_gfx10
    UINT64_C(4054319109), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V2_V8_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V3_V3
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V3_V3_gfx10
    UINT64_C(4054319107), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V3_V3_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V3_V4
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V3_V4_gfx10
    UINT64_C(4054319107), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V3_V4_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V3_V5
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V3_V5_gfx10
    UINT64_C(4054319107), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V3_V5_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V3_V6
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V3_V6_gfx10
    UINT64_C(4054319109), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V3_V6_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V3_V7
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V3_V7_gfx10
    UINT64_C(4054319109), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V3_V7_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V3_V8
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V3_V8_gfx10
    UINT64_C(4054319109), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V3_V8_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V4_V3
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V4_V3_gfx10
    UINT64_C(4054319107), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V4_V3_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V4_V4
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V4_V4_gfx10
    UINT64_C(4054319107), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V4_V4_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V4_V5
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V4_V5_gfx10
    UINT64_C(4054319107), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V4_V5_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V4_V6
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V4_V6_gfx10
    UINT64_C(4054319109), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V4_V6_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V4_V7
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V4_V7_gfx10
    UINT64_C(4054319109), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V4_V7_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V4_V8
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V4_V8_gfx10
    UINT64_C(4054319109), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V4_V8_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V5_V3
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V5_V3_gfx10
    UINT64_C(4054319107), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V5_V3_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V5_V4
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V5_V4_gfx10
    UINT64_C(4054319107), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V5_V4_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V5_V5
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V5_V5_gfx10
    UINT64_C(4054319107), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V5_V5_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V5_V6
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V5_V6_gfx10
    UINT64_C(4054319109), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V5_V6_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V5_V7
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V5_V7_gfx10
    UINT64_C(4054319109), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V5_V7_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V5_V8
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V5_V8_gfx10
    UINT64_C(4054319109), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_V5_V8_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_nortn_V3_gfx10
    UINT64_C(4054319107), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_nortn_V3_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_nortn_V4_gfx10
    UINT64_C(4054319107), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_nortn_V4_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_nortn_V5_gfx10
    UINT64_C(4054319107), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_nortn_V5_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_nortn_V6_gfx10
    UINT64_C(4054319109), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_nortn_V6_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_nortn_V7_gfx10
    UINT64_C(4054319109), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_nortn_V7_nsa_gfx10
    UINT64_C(4054319105), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_nortn_V8_gfx10
    UINT64_C(4054319109), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_G16_nortn_V8_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V1_V4
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V1_V4_gfx10
    UINT64_C(4055367683), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V1_V4_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V1_V5
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V1_V5_gfx10
    UINT64_C(4055367683), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V1_V5_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V1_V6
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V1_V6_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V1_V6_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V1_V7
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V1_V7_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V1_V7_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V1_V8
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V1_V8_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V1_V8_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V1_V9
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V1_V9_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V1_V9_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V2_V4
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V2_V4_gfx10
    UINT64_C(4055367683), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V2_V4_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V2_V5
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V2_V5_gfx10
    UINT64_C(4055367683), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V2_V5_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V2_V6
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V2_V6_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V2_V6_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V2_V7
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V2_V7_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V2_V7_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V2_V8
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V2_V8_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V2_V8_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V2_V9
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V2_V9_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V2_V9_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V3_V4
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V3_V4_gfx10
    UINT64_C(4055367683), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V3_V4_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V3_V5
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V3_V5_gfx10
    UINT64_C(4055367683), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V3_V5_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V3_V6
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V3_V6_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V3_V6_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V3_V7
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V3_V7_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V3_V7_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V3_V8
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V3_V8_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V3_V8_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V3_V9
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V3_V9_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V3_V9_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V4_V4
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V4_V4_gfx10
    UINT64_C(4055367683), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V4_V4_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V4_V5
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V4_V5_gfx10
    UINT64_C(4055367683), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V4_V5_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V4_V6
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V4_V6_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V4_V6_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V4_V7
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V4_V7_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V4_V7_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V4_V8
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V4_V8_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V4_V8_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V4_V9
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V4_V9_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V4_V9_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V5_V4
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V5_V4_gfx10
    UINT64_C(4055367683), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V5_V4_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V5_V5
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V5_V5_gfx10
    UINT64_C(4055367683), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V5_V5_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V5_V6
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V5_V6_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V5_V6_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V5_V7
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V5_V7_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V5_V7_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V5_V8
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V5_V8_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V5_V8_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V5_V9
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V5_V9_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_V5_V9_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_nortn_V4_gfx10
    UINT64_C(4055367683), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_nortn_V4_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_nortn_V5_gfx10
    UINT64_C(4055367683), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_nortn_V5_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_nortn_V6_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_nortn_V6_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_nortn_V7_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_nortn_V7_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_nortn_V8_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_nortn_V8_nsa_gfx10
    UINT64_C(4055367681), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_nortn_V9_gfx10
    UINT64_C(4055367685), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_G16_nortn_V9_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V10_gfx10
    UINT64_C(4055367686), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V10_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V11
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V11_gfx10
    UINT64_C(4055367686), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V11_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V4
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V4_gfx10
    UINT64_C(4055367682), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V4_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V5
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V5_gfx10
    UINT64_C(4055367682), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V5_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V6
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V6_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V6_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V7
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V7_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V7_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V8
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V8_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V8_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V9
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V9_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V1_V9_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V10_gfx10
    UINT64_C(4055367686), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V10_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V11
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V11_gfx10
    UINT64_C(4055367686), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V11_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V4
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V4_gfx10
    UINT64_C(4055367682), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V4_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V5
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V5_gfx10
    UINT64_C(4055367682), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V5_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V6
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V6_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V6_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V7
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V7_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V7_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V8
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V8_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V8_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V9
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V9_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V2_V9_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V10_gfx10
    UINT64_C(4055367686), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V10_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V11
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V11_gfx10
    UINT64_C(4055367686), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V11_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V4
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V4_gfx10
    UINT64_C(4055367682), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V4_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V5
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V5_gfx10
    UINT64_C(4055367682), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V5_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V6
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V6_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V6_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V7
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V7_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V7_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V8
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V8_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V8_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V9
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V9_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V3_V9_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V10_gfx10
    UINT64_C(4055367686), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V10_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V11
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V11_gfx10
    UINT64_C(4055367686), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V11_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V4
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V4_gfx10
    UINT64_C(4055367682), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V4_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V5
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V5_gfx10
    UINT64_C(4055367682), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V5_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V6
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V6_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V6_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V7
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V7_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V7_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V8
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V8_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V8_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V9
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V9_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V4_V9_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V10_gfx10
    UINT64_C(4055367686), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V10_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V11
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V11_gfx10
    UINT64_C(4055367686), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V11_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V4
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V4_gfx10
    UINT64_C(4055367682), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V4_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V5
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V5_gfx10
    UINT64_C(4055367682), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V5_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V6
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V6_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V6_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V7
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V7_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V7_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V8
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V8_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V8_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V9
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V9_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_V5_V9_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_nortn_V10_gfx10
    UINT64_C(4055367686), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_nortn_V10_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_nortn_V11_gfx10
    UINT64_C(4055367686), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_nortn_V11_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_nortn_V4_gfx10
    UINT64_C(4055367682), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_nortn_V4_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_nortn_V5_gfx10
    UINT64_C(4055367682), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_nortn_V5_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_nortn_V6_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_nortn_V6_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_nortn_V7_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_nortn_V7_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_nortn_V8_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_nortn_V8_nsa_gfx10
    UINT64_C(4055367680), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_nortn_V9_gfx10
    UINT64_C(4055367684), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_O_nortn_V9_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V10_gfx10
    UINT64_C(4054319110), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V10_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V3
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V3_gfx10
    UINT64_C(4054319106), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V3_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V4
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V4_gfx10
    UINT64_C(4054319106), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V4_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V5
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V5_gfx10
    UINT64_C(4054319106), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V5_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V6
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V6_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V6_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V7
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V7_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V7_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V8
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V8_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V8_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V9
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V9_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V1_V9_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V10_gfx10
    UINT64_C(4054319110), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V10_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V3
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V3_gfx10
    UINT64_C(4054319106), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V3_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V4
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V4_gfx10
    UINT64_C(4054319106), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V4_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V5
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V5_gfx10
    UINT64_C(4054319106), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V5_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V6
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V6_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V6_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V7
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V7_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V7_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V8
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V8_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V8_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V9
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V9_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V2_V9_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V10_gfx10
    UINT64_C(4054319110), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V10_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V3
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V3_gfx10
    UINT64_C(4054319106), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V3_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V4
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V4_gfx10
    UINT64_C(4054319106), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V4_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V5
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V5_gfx10
    UINT64_C(4054319106), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V5_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V6
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V6_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V6_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V7
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V7_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V7_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V8
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V8_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V8_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V9
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V9_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V3_V9_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V10_gfx10
    UINT64_C(4054319110), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V10_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V3
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V3_gfx10
    UINT64_C(4054319106), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V3_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V4
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V4_gfx10
    UINT64_C(4054319106), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V4_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V5
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V5_gfx10
    UINT64_C(4054319106), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V5_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V6
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V6_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V6_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V7
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V7_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V7_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V8
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V8_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V8_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V9
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V9_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V4_V9_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V10_gfx10
    UINT64_C(4054319110), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V10_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V3
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V3_gfx10
    UINT64_C(4054319106), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V3_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V4
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V4_gfx10
    UINT64_C(4054319106), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V4_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V5
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V5_gfx10
    UINT64_C(4054319106), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V5_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V6
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V6_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V6_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V7
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V7_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V7_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V8
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V8_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V8_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V9
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V9_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_V5_V9_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_nortn_V10_gfx10
    UINT64_C(4054319110), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_nortn_V10_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_nortn_V3_gfx10
    UINT64_C(4054319106), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_nortn_V3_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_nortn_V4_gfx10
    UINT64_C(4054319106), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_nortn_V4_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_nortn_V5_gfx10
    UINT64_C(4054319106), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_nortn_V5_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_nortn_V6_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_nortn_V6_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_nortn_V7_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_nortn_V7_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_nortn_V8_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_nortn_V8_nsa_gfx10
    UINT64_C(4054319104), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_nortn_V9_gfx10
    UINT64_C(4054319108), UINT64_C(0),	// IMAGE_SAMPLE_C_CD_nortn_V9_nsa_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V3
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V3_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V3_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V3_gfx12
    UINT64_C(4041474050), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V3_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V3_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V4
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V4_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V4_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V4_gfx12
    UINT64_C(4041474050), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V4_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V4_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V5
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V5_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V5_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V5_gfx12
    UINT64_C(4041474050), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V5_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V5_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V6
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V6_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V6_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V6_gfx12
    UINT64_C(4041474052), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V6_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V6_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V8
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V8_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V1_V8_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V3
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V3_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V3_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V3_gfx12
    UINT64_C(4041474050), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V3_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V3_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V4
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V4_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V4_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V4_gfx12
    UINT64_C(4041474050), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V4_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V4_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V5
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V5_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V5_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V5_gfx12
    UINT64_C(4041474050), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V5_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V5_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V6
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V6_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V6_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V6_gfx12
    UINT64_C(4041474052), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V6_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V6_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V8
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V8_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V2_V8_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V3
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V3_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V3_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V3_gfx12
    UINT64_C(4041474050), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V3_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V3_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V4
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V4_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V4_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V4_gfx12
    UINT64_C(4041474050), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V4_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V4_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V5
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V5_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V5_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V5_gfx12
    UINT64_C(4041474050), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V5_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V5_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V6
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V6_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V6_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V6_gfx12
    UINT64_C(4041474052), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V6_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V6_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V8
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V8_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V3_V8_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V3
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V3_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V3_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V3_gfx12
    UINT64_C(4041474050), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V3_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V3_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V4
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V4_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V4_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V4_gfx12
    UINT64_C(4041474050), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V4_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V4_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V5
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V5_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V5_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V5_gfx12
    UINT64_C(4041474050), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V5_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V5_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V6
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V6_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V6_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V6_gfx12
    UINT64_C(4041474052), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V6_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V6_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V8
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V8_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V4_V8_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V3
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V3_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V3_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V3_gfx12
    UINT64_C(4041474050), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V3_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V3_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V4
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V4_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V4_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V4_gfx12
    UINT64_C(4041474050), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V4_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V4_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V5
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V5_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V5_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V5_gfx12
    UINT64_C(4041474050), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V5_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V5_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V6
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V6_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V6_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V6_gfx12
    UINT64_C(4041474052), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V6_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V6_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V8
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V8_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_V5_V8_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V3_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V3_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V3_gfx12
    UINT64_C(4041474050), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V3_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V3_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V4_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V4_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V4_gfx12
    UINT64_C(4041474050), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V4_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V4_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V5_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V5_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V5_gfx12
    UINT64_C(4041474050), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V5_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V5_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V6_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V6_gfx11
    UINT64_C(3826401280), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V6_gfx12
    UINT64_C(4041474052), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V6_nsa_gfx10
    UINT64_C(4045668353), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V6_nsa_gfx11
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V8_gfx10
    UINT64_C(4045668352), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_O_nortn_V8_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V2
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V2_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V2_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V2_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V2_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V2_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V3
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V3_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V3_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V3_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V3_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V3_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V4
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V4_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V4_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V4_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V4_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V4_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V5
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V5_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V5_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V5_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V5_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V5_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V8
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V8_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V1_V8_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V2
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V2_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V2_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V2_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V2_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V2_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V3
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V3_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V3_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V3_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V3_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V3_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V4
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V4_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V4_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V4_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V4_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V4_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V5
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V5_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V5_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V5_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V5_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V5_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V8
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V8_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V2_V8_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V2
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V2_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V2_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V2_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V2_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V2_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V3
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V3_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V3_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V3_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V3_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V3_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V4
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V4_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V4_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V4_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V4_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V4_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V5
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V5_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V5_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V5_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V5_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V5_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V8
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V8_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V3_V8_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V2
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V2_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V2_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V2_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V2_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V2_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V3
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V3_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V3_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V3_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V3_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V3_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V4
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V4_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V4_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V4_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V4_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V4_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V5
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V5_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V5_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V5_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V5_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V5_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V8
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V8_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V4_V8_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V2
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V2_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V2_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V2_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V2_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V2_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V3
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V3_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V3_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V3_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V3_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V3_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V4
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V4_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V4_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V4_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V4_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V4_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V5
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V5_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V5_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V5_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V5_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V5_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V8
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V8_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_V5_V8_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V2_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V2_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V2_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V2_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V2_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V3_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V3_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V3_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V3_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V3_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V4_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V4_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V4_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V4_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V4_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V5_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V5_gfx11
    UINT64_C(3826302976), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V5_gfx12
    UINT64_C(4037279746), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V5_nsa_gfx10
    UINT64_C(4044095489), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V5_nsa_gfx11
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V8_gfx10
    UINT64_C(4044095488), UINT64_C(0),	// IMAGE_SAMPLE_C_CL_nortn_V8_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V3
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V3_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V3_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V3_gfx12
    UINT64_C(4037804035), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V3_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V3_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V4
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V4_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V4_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V4_gfx12
    UINT64_C(4037804035), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V4_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V4_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V5
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V5_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V5_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V5_gfx12
    UINT64_C(4037804035), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V5_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V5_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V6
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V6_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V6_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V6_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V6_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V6_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V7
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V7_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V7_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V7_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V7_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V7_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V8
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V8_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V8_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V8_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V8_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V8_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V9
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V9_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V9_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V9_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V9_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V1_V9_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V3
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V3_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V3_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V3_gfx12
    UINT64_C(4037804035), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V3_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V3_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V4
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V4_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V4_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V4_gfx12
    UINT64_C(4037804035), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V4_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V4_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V5
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V5_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V5_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V5_gfx12
    UINT64_C(4037804035), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V5_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V5_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V6
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V6_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V6_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V6_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V6_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V6_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V7
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V7_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V7_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V7_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V7_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V7_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V8
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V8_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V8_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V8_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V8_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V8_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V9
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V9_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V9_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V9_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V9_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V2_V9_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V3
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V3_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V3_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V3_gfx12
    UINT64_C(4037804035), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V3_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V3_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V4
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V4_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V4_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V4_gfx12
    UINT64_C(4037804035), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V4_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V4_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V5
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V5_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V5_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V5_gfx12
    UINT64_C(4037804035), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V5_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V5_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V6
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V6_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V6_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V6_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V6_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V6_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V7
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V7_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V7_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V7_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V7_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V7_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V8
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V8_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V8_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V8_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V8_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V8_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V9
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V9_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V9_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V9_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V9_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V3_V9_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V3
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V3_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V3_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V3_gfx12
    UINT64_C(4037804035), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V3_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V3_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V4
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V4_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V4_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V4_gfx12
    UINT64_C(4037804035), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V4_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V4_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V5
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V5_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V5_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V5_gfx12
    UINT64_C(4037804035), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V5_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V5_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V6
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V6_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V6_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V6_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V6_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V6_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V7
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V7_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V7_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V7_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V7_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V7_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V8
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V8_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V8_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V8_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V8_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V8_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V9
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V9_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V9_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V9_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V9_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V4_V9_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V3
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V3_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V3_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V3_gfx12
    UINT64_C(4037804035), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V3_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V3_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V4
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V4_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V4_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V4_gfx12
    UINT64_C(4037804035), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V4_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V4_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V5
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V5_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V5_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V5_gfx12
    UINT64_C(4037804035), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V5_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V5_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V6
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V6_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V6_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V6_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V6_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V6_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V7
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V7_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V7_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V7_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V7_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V7_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V8
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V8_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V8_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V8_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V8_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V8_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V9
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V9_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V9_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V9_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V9_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_V5_V9_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V3_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V3_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V3_gfx12
    UINT64_C(4037804035), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V3_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V3_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V4_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V4_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V4_gfx12
    UINT64_C(4037804035), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V4_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V4_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V5_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V5_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V5_gfx12
    UINT64_C(4037804035), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V5_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V5_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V6_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V6_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V6_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V6_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V6_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V7_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V7_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V7_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V7_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V7_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V8_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V8_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V8_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V8_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V8_nsa_gfx11
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V9_gfx10
    UINT64_C(4048551936), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V9_gfx11
    UINT64_C(3826581504), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V9_gfx12
    UINT64_C(4037804037), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V9_nsa_gfx10
    UINT64_C(4048551937), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_G16_nortn_V9_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V10_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V10_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V10_gfx12
    UINT64_C(4041998343), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V10_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V10_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V4
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V4_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V4_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V4_gfx12
    UINT64_C(4041998339), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V4_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V4_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V5
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V5_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V5_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V5_gfx12
    UINT64_C(4041998339), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V5_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V5_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V6
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V6_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V6_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V6_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V6_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V6_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V7
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V7_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V7_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V7_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V7_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V7_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V8
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V8_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V8_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V8_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V8_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V8_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V9
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V9_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V9_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V9_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V9_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V1_V9_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V10_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V10_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V10_gfx12
    UINT64_C(4041998343), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V10_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V10_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V4
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V4_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V4_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V4_gfx12
    UINT64_C(4041998339), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V4_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V4_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V5
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V5_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V5_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V5_gfx12
    UINT64_C(4041998339), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V5_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V5_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V6
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V6_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V6_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V6_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V6_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V6_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V7
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V7_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V7_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V7_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V7_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V7_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V8
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V8_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V8_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V8_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V8_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V8_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V9
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V9_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V9_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V9_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V9_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V2_V9_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V10_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V10_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V10_gfx12
    UINT64_C(4041998343), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V10_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V10_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V4
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V4_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V4_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V4_gfx12
    UINT64_C(4041998339), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V4_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V4_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V5
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V5_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V5_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V5_gfx12
    UINT64_C(4041998339), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V5_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V5_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V6
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V6_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V6_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V6_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V6_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V6_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V7
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V7_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V7_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V7_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V7_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V7_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V8
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V8_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V8_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V8_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V8_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V8_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V9
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V9_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V9_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V9_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V9_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V3_V9_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V10_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V10_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V10_gfx12
    UINT64_C(4041998343), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V10_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V10_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V4
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V4_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V4_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V4_gfx12
    UINT64_C(4041998339), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V4_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V4_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V5
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V5_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V5_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V5_gfx12
    UINT64_C(4041998339), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V5_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V5_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V6
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V6_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V6_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V6_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V6_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V6_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V7
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V7_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V7_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V7_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V7_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V7_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V8
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V8_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V8_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V8_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V8_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V8_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V9
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V9_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V9_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V9_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V9_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V4_V9_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V10_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V10_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V10_gfx12
    UINT64_C(4041998343), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V10_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V10_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V4
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V4_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V4_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V4_gfx12
    UINT64_C(4041998339), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V4_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V4_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V5
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V5_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V5_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V5_gfx12
    UINT64_C(4041998339), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V5_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V5_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V6
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V6_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V6_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V6_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V6_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V6_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V7
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V7_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V7_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V7_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V7_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V7_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V8
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V8_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V8_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V8_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V8_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V8_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V9
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V9_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V9_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V9_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V9_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_V5_V9_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V10_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V10_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V10_gfx12
    UINT64_C(4041998343), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V10_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V10_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V4_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V4_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V4_gfx12
    UINT64_C(4041998339), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V4_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V4_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V5_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V5_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V5_gfx12
    UINT64_C(4041998339), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V5_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V5_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V6_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V6_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V6_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V6_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V6_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V7_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V7_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V7_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V7_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V7_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V8_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V8_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V8_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V8_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V8_nsa_gfx11
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V9_gfx10
    UINT64_C(4049076224), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V9_gfx11
    UINT64_C(3826614272), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V9_gfx12
    UINT64_C(4041998341), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V9_nsa_gfx10
    UINT64_C(4049076225), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V9_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V10_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V10_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V10_gfx12
    UINT64_C(4041998342), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V10_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V10_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V11_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V11_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V11_gfx12
    UINT64_C(4041998342), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V11_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V11_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V12
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V12_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V12_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V12_gfx12
    UINT64_C(4041998342), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V12_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V12_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V4
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V4_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V4_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V4_gfx12
    UINT64_C(4041998338), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V4_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V4_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V5
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V5_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V5_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V5_gfx12
    UINT64_C(4041998338), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V5_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V5_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V6
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V6_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V6_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V6_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V6_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V6_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V7
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V7_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V7_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V7_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V7_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V7_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V8
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V8_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V8_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V8_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V8_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V8_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V9
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V9_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V9_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V9_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V9_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V1_V9_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V10_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V10_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V10_gfx12
    UINT64_C(4041998342), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V10_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V10_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V11_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V11_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V11_gfx12
    UINT64_C(4041998342), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V11_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V11_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V12
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V12_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V12_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V12_gfx12
    UINT64_C(4041998342), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V12_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V12_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V4
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V4_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V4_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V4_gfx12
    UINT64_C(4041998338), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V4_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V4_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V5
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V5_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V5_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V5_gfx12
    UINT64_C(4041998338), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V5_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V5_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V6
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V6_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V6_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V6_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V6_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V6_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V7
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V7_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V7_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V7_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V7_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V7_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V8
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V8_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V8_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V8_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V8_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V8_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V9
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V9_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V9_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V9_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V9_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V2_V9_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V10_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V10_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V10_gfx12
    UINT64_C(4041998342), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V10_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V10_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V11_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V11_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V11_gfx12
    UINT64_C(4041998342), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V11_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V11_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V12
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V12_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V12_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V12_gfx12
    UINT64_C(4041998342), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V12_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V12_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V4
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V4_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V4_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V4_gfx12
    UINT64_C(4041998338), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V4_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V4_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V5
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V5_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V5_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V5_gfx12
    UINT64_C(4041998338), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V5_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V5_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V6
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V6_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V6_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V6_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V6_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V6_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V7
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V7_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V7_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V7_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V7_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V7_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V8
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V8_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V8_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V8_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V8_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V8_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V9
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V9_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V9_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V9_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V9_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V3_V9_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V10_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V10_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V10_gfx12
    UINT64_C(4041998342), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V10_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V10_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V11_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V11_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V11_gfx12
    UINT64_C(4041998342), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V11_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V11_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V12
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V12_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V12_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V12_gfx12
    UINT64_C(4041998342), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V12_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V12_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V4
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V4_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V4_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V4_gfx12
    UINT64_C(4041998338), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V4_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V4_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V5
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V5_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V5_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V5_gfx12
    UINT64_C(4041998338), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V5_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V5_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V6
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V6_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V6_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V6_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V6_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V6_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V7
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V7_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V7_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V7_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V7_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V7_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V8
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V8_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V8_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V8_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V8_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V8_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V9
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V9_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V9_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V9_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V9_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V4_V9_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V10_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V10_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V10_gfx12
    UINT64_C(4041998342), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V10_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V10_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V11_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V11_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V11_gfx12
    UINT64_C(4041998342), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V11_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V11_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V12
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V12_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V12_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V12_gfx12
    UINT64_C(4041998342), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V12_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V12_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V4
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V4_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V4_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V4_gfx12
    UINT64_C(4041998338), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V4_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V4_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V5
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V5_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V5_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V5_gfx12
    UINT64_C(4041998338), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V5_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V5_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V6
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V6_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V6_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V6_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V6_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V6_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V7
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V7_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V7_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V7_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V7_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V7_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V8
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V8_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V8_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V8_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V8_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V8_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V9
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V9_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V9_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V9_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V9_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_V5_V9_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V10_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V10_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V10_gfx12
    UINT64_C(4041998342), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V10_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V10_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V11_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V11_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V11_gfx12
    UINT64_C(4041998342), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V11_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V11_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V12_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V12_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V12_gfx12
    UINT64_C(4041998342), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V12_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V12_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V4_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V4_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V4_gfx12
    UINT64_C(4041998338), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V4_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V4_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V5_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V5_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V5_gfx12
    UINT64_C(4041998338), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V5_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V5_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V6_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V6_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V6_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V6_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V6_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V7_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V7_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V7_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V7_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V7_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V8_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V8_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V8_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V8_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V8_nsa_gfx11
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V9_gfx10
    UINT64_C(4045930496), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V9_gfx11
    UINT64_C(3826417664), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V9_gfx12
    UINT64_C(4041998340), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V9_nsa_gfx10
    UINT64_C(4045930497), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_O_nortn_V9_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V10_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V10_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V10_gfx12
    UINT64_C(4037804038), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V10_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V10_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V11_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V11_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V11_gfx12
    UINT64_C(4037804038), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V11_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V11_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V3
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V3_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V3_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V3_gfx12
    UINT64_C(4037804034), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V3_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V3_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V4
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V4_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V4_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V4_gfx12
    UINT64_C(4037804034), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V4_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V4_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V5
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V5_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V5_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V5_gfx12
    UINT64_C(4037804034), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V5_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V5_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V6
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V6_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V6_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V6_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V6_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V6_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V7
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V7_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V7_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V7_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V7_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V7_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V8
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V8_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V8_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V8_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V8_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V8_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V9
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V9_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V9_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V9_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V9_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V1_V9_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V10_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V10_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V10_gfx12
    UINT64_C(4037804038), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V10_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V10_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V11_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V11_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V11_gfx12
    UINT64_C(4037804038), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V11_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V11_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V3
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V3_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V3_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V3_gfx12
    UINT64_C(4037804034), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V3_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V3_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V4
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V4_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V4_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V4_gfx12
    UINT64_C(4037804034), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V4_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V4_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V5
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V5_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V5_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V5_gfx12
    UINT64_C(4037804034), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V5_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V5_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V6
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V6_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V6_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V6_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V6_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V6_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V7
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V7_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V7_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V7_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V7_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V7_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V8
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V8_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V8_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V8_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V8_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V8_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V9
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V9_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V9_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V9_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V9_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V2_V9_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V10_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V10_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V10_gfx12
    UINT64_C(4037804038), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V10_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V10_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V11_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V11_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V11_gfx12
    UINT64_C(4037804038), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V11_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V11_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V3
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V3_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V3_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V3_gfx12
    UINT64_C(4037804034), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V3_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V3_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V4
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V4_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V4_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V4_gfx12
    UINT64_C(4037804034), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V4_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V4_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V5
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V5_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V5_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V5_gfx12
    UINT64_C(4037804034), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V5_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V5_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V6
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V6_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V6_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V6_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V6_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V6_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V7
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V7_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V7_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V7_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V7_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V7_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V8
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V8_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V8_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V8_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V8_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V8_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V9
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V9_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V9_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V9_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V9_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V3_V9_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V10_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V10_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V10_gfx12
    UINT64_C(4037804038), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V10_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V10_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V11_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V11_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V11_gfx12
    UINT64_C(4037804038), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V11_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V11_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V3
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V3_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V3_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V3_gfx12
    UINT64_C(4037804034), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V3_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V3_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V4
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V4_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V4_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V4_gfx12
    UINT64_C(4037804034), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V4_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V4_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V5
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V5_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V5_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V5_gfx12
    UINT64_C(4037804034), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V5_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V5_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V6
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V6_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V6_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V6_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V6_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V6_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V7
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V7_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V7_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V7_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V7_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V7_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V8
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V8_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V8_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V8_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V8_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V8_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V9
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V9_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V9_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V9_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V9_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V4_V9_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V10_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V10_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V10_gfx12
    UINT64_C(4037804038), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V10_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V10_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V11_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V11_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V11_gfx12
    UINT64_C(4037804038), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V11_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V11_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V3
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V3_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V3_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V3_gfx12
    UINT64_C(4037804034), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V3_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V3_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V4
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V4_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V4_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V4_gfx12
    UINT64_C(4037804034), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V4_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V4_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V5
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V5_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V5_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V5_gfx12
    UINT64_C(4037804034), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V5_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V5_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V6
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V6_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V6_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V6_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V6_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V6_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V7
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V7_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V7_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V7_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V7_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V7_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V8
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V8_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V8_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V8_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V8_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V8_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V9
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V9_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V9_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V9_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V9_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_V5_V9_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V10_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V10_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V10_gfx12
    UINT64_C(4037804038), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V10_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V10_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V11_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V11_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V11_gfx12
    UINT64_C(4037804038), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V11_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V11_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V3_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V3_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V3_gfx12
    UINT64_C(4037804034), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V3_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V3_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V4_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V4_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V4_gfx12
    UINT64_C(4037804034), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V4_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V4_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V5_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V5_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V5_gfx12
    UINT64_C(4037804034), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V5_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V5_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V6_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V6_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V6_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V6_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V6_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V7_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V7_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V7_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V7_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V7_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V8_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V8_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V8_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V8_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V8_nsa_gfx11
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V9_gfx10
    UINT64_C(4044357632), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V9_gfx11
    UINT64_C(3826319360), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V9_gfx12
    UINT64_C(4037804036), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V9_nsa_gfx10
    UINT64_C(4044357633), UINT64_C(0),	// IMAGE_SAMPLE_C_D_CL_nortn_V9_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V3
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V3_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V3_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V3_gfx12
    UINT64_C(4037541891), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V3_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V3_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V4
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V4_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V4_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V4_gfx12
    UINT64_C(4037541891), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V4_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V4_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V5
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V5_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V5_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V5_gfx12
    UINT64_C(4037541891), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V5_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V5_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V6
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V6_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V6_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V6_gfx12
    UINT64_C(4037541893), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V6_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V6_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V7
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V7_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V7_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V7_gfx12
    UINT64_C(4037541893), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V7_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V7_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V8
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V8_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V8_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V8_gfx12
    UINT64_C(4037541893), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V8_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V1_V8_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V3
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V3_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V3_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V3_gfx12
    UINT64_C(4037541891), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V3_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V3_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V4
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V4_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V4_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V4_gfx12
    UINT64_C(4037541891), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V4_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V4_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V5
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V5_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V5_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V5_gfx12
    UINT64_C(4037541891), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V5_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V5_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V6
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V6_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V6_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V6_gfx12
    UINT64_C(4037541893), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V6_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V6_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V7
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V7_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V7_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V7_gfx12
    UINT64_C(4037541893), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V7_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V7_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V8
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V8_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V8_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V8_gfx12
    UINT64_C(4037541893), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V8_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V2_V8_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V3
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V3_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V3_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V3_gfx12
    UINT64_C(4037541891), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V3_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V3_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V4
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V4_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V4_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V4_gfx12
    UINT64_C(4037541891), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V4_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V4_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V5
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V5_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V5_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V5_gfx12
    UINT64_C(4037541891), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V5_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V5_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V6
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V6_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V6_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V6_gfx12
    UINT64_C(4037541893), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V6_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V6_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V7
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V7_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V7_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V7_gfx12
    UINT64_C(4037541893), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V7_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V7_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V8
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V8_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V8_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V8_gfx12
    UINT64_C(4037541893), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V8_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V3_V8_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V3
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V3_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V3_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V3_gfx12
    UINT64_C(4037541891), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V3_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V3_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V4
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V4_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V4_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V4_gfx12
    UINT64_C(4037541891), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V4_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V4_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V5
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V5_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V5_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V5_gfx12
    UINT64_C(4037541891), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V5_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V5_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V6
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V6_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V6_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V6_gfx12
    UINT64_C(4037541893), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V6_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V6_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V7
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V7_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V7_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V7_gfx12
    UINT64_C(4037541893), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V7_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V7_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V8
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V8_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V8_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V8_gfx12
    UINT64_C(4037541893), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V8_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V4_V8_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V3
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V3_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V3_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V3_gfx12
    UINT64_C(4037541891), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V3_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V3_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V4
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V4_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V4_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V4_gfx12
    UINT64_C(4037541891), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V4_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V4_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V5
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V5_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V5_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V5_gfx12
    UINT64_C(4037541891), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V5_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V5_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V6
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V6_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V6_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V6_gfx12
    UINT64_C(4037541893), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V6_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V6_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V7
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V7_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V7_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V7_gfx12
    UINT64_C(4037541893), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V7_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V7_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V8
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V8_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V8_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V8_gfx12
    UINT64_C(4037541893), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V8_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_V5_V8_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V3_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V3_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V3_gfx12
    UINT64_C(4037541891), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V3_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V3_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V4_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V4_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V4_gfx12
    UINT64_C(4037541891), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V4_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V4_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V5_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V5_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V5_gfx12
    UINT64_C(4037541891), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V5_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V5_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V6_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V6_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V6_gfx12
    UINT64_C(4037541893), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V6_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V6_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V7_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V7_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V7_gfx12
    UINT64_C(4037541893), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V7_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V7_nsa_gfx11
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V8_gfx10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V8_gfx11
    UINT64_C(3826155520), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V8_gfx12
    UINT64_C(4037541893), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V8_nsa_gfx10
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_G16_nortn_V8_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V4
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V4_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V4_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V4_gfx12
    UINT64_C(4041736195), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V4_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V4_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V5
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V5_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V5_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V5_gfx12
    UINT64_C(4041736195), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V5_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V5_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V6
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V6_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V6_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V6_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V6_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V6_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V7
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V7_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V7_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V7_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V7_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V7_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V8
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V8_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V8_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V8_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V8_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V8_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V9
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V9_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V9_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V9_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V9_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V1_V9_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V4
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V4_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V4_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V4_gfx12
    UINT64_C(4041736195), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V4_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V4_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V5
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V5_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V5_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V5_gfx12
    UINT64_C(4041736195), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V5_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V5_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V6
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V6_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V6_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V6_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V6_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V6_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V7
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V7_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V7_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V7_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V7_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V7_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V8
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V8_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V8_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V8_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V8_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V8_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V9
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V9_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V9_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V9_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V9_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V2_V9_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V4
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V4_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V4_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V4_gfx12
    UINT64_C(4041736195), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V4_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V4_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V5
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V5_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V5_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V5_gfx12
    UINT64_C(4041736195), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V5_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V5_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V6
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V6_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V6_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V6_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V6_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V6_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V7
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V7_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V7_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V7_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V7_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V7_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V8
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V8_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V8_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V8_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V8_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V8_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V9
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V9_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V9_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V9_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V9_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V3_V9_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V4
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V4_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V4_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V4_gfx12
    UINT64_C(4041736195), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V4_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V4_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V5
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V5_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V5_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V5_gfx12
    UINT64_C(4041736195), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V5_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V5_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V6
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V6_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V6_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V6_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V6_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V6_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V7
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V7_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V7_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V7_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V7_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V7_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V8
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V8_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V8_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V8_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V8_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V8_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V9
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V9_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V9_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V9_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V9_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V4_V9_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V4
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V4_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V4_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V4_gfx12
    UINT64_C(4041736195), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V4_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V4_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V5
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V5_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V5_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V5_gfx12
    UINT64_C(4041736195), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V5_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V5_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V6
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V6_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V6_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V6_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V6_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V6_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V7
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V7_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V7_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V7_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V7_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V7_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V8
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V8_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V8_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V8_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V8_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V8_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V9
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V9_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V9_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V9_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V9_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_V5_V9_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V4_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V4_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V4_gfx12
    UINT64_C(4041736195), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V4_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V4_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V5_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V5_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V5_gfx12
    UINT64_C(4041736195), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V5_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V5_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V6_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V6_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V6_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V6_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V6_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V7_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V7_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V7_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V7_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V7_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V8_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V8_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V8_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V8_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V8_nsa_gfx11
    UINT64_C(4041736193), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V9_gfx10
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V9_gfx11
    UINT64_C(3826188288), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V9_gfx12
    UINT64_C(4041736197), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V9_nsa_gfx10
    UINT64_C(4042260481), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_G16_nortn_V9_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V10_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V10_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V10_gfx12
    UINT64_C(4041736198), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V10_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V10_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V11_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V11_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V11_gfx12
    UINT64_C(4041736198), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V11_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V11_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V4
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V4_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V4_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V4_gfx12
    UINT64_C(4041736194), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V4_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V4_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V5
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V5_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V5_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V5_gfx12
    UINT64_C(4041736194), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V5_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V5_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V6
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V6_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V6_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V6_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V6_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V6_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V7
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V7_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V7_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V7_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V7_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V7_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V8
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V8_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V8_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V8_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V8_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V8_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V9
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V9_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V9_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V9_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V9_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V1_V9_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V10_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V10_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V10_gfx12
    UINT64_C(4041736198), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V10_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V10_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V11_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V11_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V11_gfx12
    UINT64_C(4041736198), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V11_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V11_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V4
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V4_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V4_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V4_gfx12
    UINT64_C(4041736194), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V4_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V4_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V5
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V5_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V5_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V5_gfx12
    UINT64_C(4041736194), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V5_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V5_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V6
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V6_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V6_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V6_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V6_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V6_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V7
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V7_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V7_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V7_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V7_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V7_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V8
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V8_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V8_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V8_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V8_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V8_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V9
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V9_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V9_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V9_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V9_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V2_V9_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V10_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V10_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V10_gfx12
    UINT64_C(4041736198), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V10_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V10_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V11_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V11_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V11_gfx12
    UINT64_C(4041736198), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V11_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V11_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V4
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V4_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V4_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V4_gfx12
    UINT64_C(4041736194), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V4_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V4_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V5
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V5_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V5_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V5_gfx12
    UINT64_C(4041736194), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V5_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V5_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V6
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V6_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V6_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V6_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V6_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V6_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V7
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V7_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V7_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V7_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V7_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V7_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V8
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V8_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V8_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V8_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V8_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V8_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V9
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V9_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V9_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V9_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V9_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V3_V9_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V10_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V10_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V10_gfx12
    UINT64_C(4041736198), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V10_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V10_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V11_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V11_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V11_gfx12
    UINT64_C(4041736198), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V11_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V11_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V4
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V4_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V4_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V4_gfx12
    UINT64_C(4041736194), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V4_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V4_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V5
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V5_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V5_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V5_gfx12
    UINT64_C(4041736194), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V5_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V5_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V6
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V6_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V6_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V6_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V6_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V6_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V7
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V7_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V7_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V7_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V7_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V7_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V8
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V8_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V8_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V8_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V8_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V8_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V9
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V9_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V9_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V9_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V9_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V4_V9_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V10
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V10_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V10_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V10_gfx12
    UINT64_C(4041736198), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V10_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V10_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V11_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V11_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V11_gfx12
    UINT64_C(4041736198), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V11_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V11_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V4
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V4_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V4_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V4_gfx12
    UINT64_C(4041736194), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V4_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V4_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V5
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V5_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V5_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V5_gfx12
    UINT64_C(4041736194), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V5_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V5_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V6
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V6_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V6_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V6_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V6_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V6_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V7
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V7_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V7_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V7_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V7_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V7_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V8
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V8_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V8_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V8_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V8_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V8_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V9
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V9_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V9_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V9_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V9_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_V5_V9_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V10_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V10_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V10_gfx12
    UINT64_C(4041736198), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V10_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V10_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V11_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V11_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V11_gfx12
    UINT64_C(4041736198), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V11_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V11_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V4_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V4_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V4_gfx12
    UINT64_C(4041736194), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V4_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V4_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V5_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V5_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V5_gfx12
    UINT64_C(4041736194), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V5_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V5_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V6_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V6_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V6_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V6_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V6_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V7_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V7_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V7_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V7_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V7_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V8_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V8_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V8_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V8_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V8_nsa_gfx11
    UINT64_C(4041736192), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V9_gfx10
    UINT64_C(4037804032), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V9_gfx11
    UINT64_C(3825909760), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V9_gfx12
    UINT64_C(4041736196), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V9_nsa_gfx10
    UINT64_C(4037804033), UINT64_C(0),	// IMAGE_SAMPLE_C_D_O_nortn_V9_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V10_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V10_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V10_gfx12
    UINT64_C(4037541894), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V10_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V10_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V3
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V3_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V3_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V3_gfx12
    UINT64_C(4037541890), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V3_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V3_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V4
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V4_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V4_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V4_gfx12
    UINT64_C(4037541890), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V4_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V4_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V5
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V5_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V5_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V5_gfx12
    UINT64_C(4037541890), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V5_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V5_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V6
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V6_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V6_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V6_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V6_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V6_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V7
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V7_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V7_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V7_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V7_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V7_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V8
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V8_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V8_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V8_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V8_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V8_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V9
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V9_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V9_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V9_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V9_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V1_V9_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V10_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V10_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V10_gfx12
    UINT64_C(4037541894), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V10_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V10_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V3
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V3_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V3_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V3_gfx12
    UINT64_C(4037541890), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V3_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V3_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V4
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V4_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V4_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V4_gfx12
    UINT64_C(4037541890), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V4_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V4_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V5
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V5_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V5_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V5_gfx12
    UINT64_C(4037541890), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V5_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V5_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V6
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V6_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V6_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V6_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V6_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V6_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V7
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V7_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V7_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V7_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V7_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V7_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V8
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V8_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V8_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V8_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V8_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V8_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V9
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V9_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V9_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V9_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V9_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V2_V9_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V10_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V10_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V10_gfx12
    UINT64_C(4037541894), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V10_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V10_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V3
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V3_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V3_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V3_gfx12
    UINT64_C(4037541890), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V3_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V3_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V4
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V4_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V4_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V4_gfx12
    UINT64_C(4037541890), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V4_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V4_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V5
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V5_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V5_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V5_gfx12
    UINT64_C(4037541890), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V5_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V5_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V6
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V6_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V6_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V6_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V6_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V6_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V7
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V7_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V7_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V7_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V7_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V7_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V8
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V8_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V8_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V8_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V8_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V8_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V9
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V9_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V9_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V9_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V9_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V3_V9_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V10_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V10_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V10_gfx12
    UINT64_C(4037541894), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V10_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V10_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V3
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V3_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V3_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V3_gfx12
    UINT64_C(4037541890), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V3_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V3_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V4
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V4_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V4_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V4_gfx12
    UINT64_C(4037541890), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V4_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V4_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V5
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V5_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V5_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V5_gfx12
    UINT64_C(4037541890), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V5_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V5_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V6
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V6_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V6_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V6_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V6_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V6_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V7
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V7_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V7_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V7_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V7_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V7_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V8
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V8_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V8_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V8_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V8_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V8_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V9
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V9_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V9_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V9_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V9_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V4_V9_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V10_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V10_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V10_gfx12
    UINT64_C(4037541894), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V10_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V10_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V3
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V3_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V3_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V3_gfx12
    UINT64_C(4037541890), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V3_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V3_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V4
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V4_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V4_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V4_gfx12
    UINT64_C(4037541890), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V4_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V4_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V5
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V5_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V5_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V5_gfx12
    UINT64_C(4037541890), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V5_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V5_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V6
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V6_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V6_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V6_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V6_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V6_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V7
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V7_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V7_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V7_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V7_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V7_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V8
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V8_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V8_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V8_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V8_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V8_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V9
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V9_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V9_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V9_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V9_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_V5_V9_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V10_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V10_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V10_gfx12
    UINT64_C(4037541894), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V10_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V10_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V3_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V3_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V3_gfx12
    UINT64_C(4037541890), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V3_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V3_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V4_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V4_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V4_gfx12
    UINT64_C(4037541890), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V4_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V4_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V5_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V5_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V5_gfx12
    UINT64_C(4037541890), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V5_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V5_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V6_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V6_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V6_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V6_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V6_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V7_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V7_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V7_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V7_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V7_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V8_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V8_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V8_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V8_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V8_nsa_gfx11
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V9_gfx10
    UINT64_C(4035182592), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V9_gfx11
    UINT64_C(3825745920), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V9_gfx12
    UINT64_C(4037541892), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V9_nsa_gfx10
    UINT64_C(4035182593), UINT64_C(0),	// IMAGE_SAMPLE_C_D_nortn_V9_nsa_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V3
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V3_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V3_gfx11
    UINT64_C(3825958912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V3_gfx12
    UINT64_C(4043046914), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V3_nsa_gfx10
    UINT64_C(4038590465), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V3_nsa_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V4
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V4_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V4_gfx11
    UINT64_C(3825958912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V4_gfx12
    UINT64_C(4043046914), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V4_nsa_gfx10
    UINT64_C(4038590465), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V4_nsa_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V5
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V5_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V5_gfx11
    UINT64_C(3825958912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V5_gfx12
    UINT64_C(4043046914), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V5_nsa_gfx10
    UINT64_C(4038590465), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V5_nsa_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V8
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V8_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V1_V8_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V3
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V3_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V3_gfx11
    UINT64_C(3825958912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V3_gfx12
    UINT64_C(4043046914), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V3_nsa_gfx10
    UINT64_C(4038590465), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V3_nsa_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V4
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V4_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V4_gfx11
    UINT64_C(3825958912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V4_gfx12
    UINT64_C(4043046914), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V4_nsa_gfx10
    UINT64_C(4038590465), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V4_nsa_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V5
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V5_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V5_gfx11
    UINT64_C(3825958912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V5_gfx12
    UINT64_C(4043046914), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V5_nsa_gfx10
    UINT64_C(4038590465), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V5_nsa_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V8
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V8_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V2_V8_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V3
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V3_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V3_gfx11
    UINT64_C(3825958912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V3_gfx12
    UINT64_C(4043046914), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V3_nsa_gfx10
    UINT64_C(4038590465), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V3_nsa_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V4
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V4_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V4_gfx11
    UINT64_C(3825958912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V4_gfx12
    UINT64_C(4043046914), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V4_nsa_gfx10
    UINT64_C(4038590465), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V4_nsa_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V5
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V5_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V5_gfx11
    UINT64_C(3825958912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V5_gfx12
    UINT64_C(4043046914), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V5_nsa_gfx10
    UINT64_C(4038590465), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V5_nsa_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V8
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V8_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V3_V8_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V3
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V3_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V3_gfx11
    UINT64_C(3825958912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V3_gfx12
    UINT64_C(4043046914), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V3_nsa_gfx10
    UINT64_C(4038590465), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V3_nsa_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V4
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V4_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V4_gfx11
    UINT64_C(3825958912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V4_gfx12
    UINT64_C(4043046914), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V4_nsa_gfx10
    UINT64_C(4038590465), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V4_nsa_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V5
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V5_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V5_gfx11
    UINT64_C(3825958912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V5_gfx12
    UINT64_C(4043046914), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V5_nsa_gfx10
    UINT64_C(4038590465), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V5_nsa_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V8
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V8_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V4_V8_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V3
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V3_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V3_gfx11
    UINT64_C(3825958912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V3_gfx12
    UINT64_C(4043046914), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V3_nsa_gfx10
    UINT64_C(4038590465), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V3_nsa_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V4
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V4_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V4_gfx11
    UINT64_C(3825958912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V4_gfx12
    UINT64_C(4043046914), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V4_nsa_gfx10
    UINT64_C(4038590465), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V4_nsa_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V5
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V5_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V5_gfx11
    UINT64_C(3825958912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V5_gfx12
    UINT64_C(4043046914), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V5_nsa_gfx10
    UINT64_C(4038590465), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V5_nsa_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V8
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V8_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_V5_V8_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_nortn_V3_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_nortn_V3_gfx11
    UINT64_C(3825958912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_nortn_V3_gfx12
    UINT64_C(4043046914), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_nortn_V3_nsa_gfx10
    UINT64_C(4038590465), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_nortn_V3_nsa_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_nortn_V4_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_nortn_V4_gfx11
    UINT64_C(3825958912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_nortn_V4_gfx12
    UINT64_C(4043046914), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_nortn_V4_nsa_gfx10
    UINT64_C(4038590465), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_nortn_V4_nsa_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_nortn_V5_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_nortn_V5_gfx11
    UINT64_C(3825958912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_nortn_V5_gfx12
    UINT64_C(4043046914), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_nortn_V5_nsa_gfx10
    UINT64_C(4038590465), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_nortn_V5_nsa_gfx11
    UINT64_C(4043046912), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_nortn_V8_gfx10
    UINT64_C(4038590464), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_O_nortn_V8_gfx11
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V1_V2
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V1_V2_gfx10
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V1_V2_gfx11
    UINT64_C(3825795072), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V1_V2_gfx12
    UINT64_C(4038852610), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V1_V2_nsa_gfx10
    UINT64_C(4035969025), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V1_V2_nsa_gfx11
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V1_V3
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V1_V3_gfx10
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V1_V3_gfx11
    UINT64_C(3825795072), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V1_V3_gfx12
    UINT64_C(4038852610), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V1_V3_nsa_gfx10
    UINT64_C(4035969025), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V1_V3_nsa_gfx11
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V1_V4
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V1_V4_gfx10
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V1_V4_gfx11
    UINT64_C(3825795072), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V1_V4_gfx12
    UINT64_C(4038852610), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V1_V4_nsa_gfx10
    UINT64_C(4035969025), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V1_V4_nsa_gfx11
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V2_V2
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V2_V2_gfx10
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V2_V2_gfx11
    UINT64_C(3825795072), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V2_V2_gfx12
    UINT64_C(4038852610), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V2_V2_nsa_gfx10
    UINT64_C(4035969025), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V2_V2_nsa_gfx11
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V2_V3
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V2_V3_gfx10
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V2_V3_gfx11
    UINT64_C(3825795072), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V2_V3_gfx12
    UINT64_C(4038852610), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V2_V3_nsa_gfx10
    UINT64_C(4035969025), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V2_V3_nsa_gfx11
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V2_V4
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V2_V4_gfx10
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V2_V4_gfx11
    UINT64_C(3825795072), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V2_V4_gfx12
    UINT64_C(4038852610), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V2_V4_nsa_gfx10
    UINT64_C(4035969025), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V2_V4_nsa_gfx11
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V3_V2
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V3_V2_gfx10
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V3_V2_gfx11
    UINT64_C(3825795072), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V3_V2_gfx12
    UINT64_C(4038852610), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V3_V2_nsa_gfx10
    UINT64_C(4035969025), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V3_V2_nsa_gfx11
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V3_V3
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V3_V3_gfx10
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V3_V3_gfx11
    UINT64_C(3825795072), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V3_V3_gfx12
    UINT64_C(4038852610), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V3_V3_nsa_gfx10
    UINT64_C(4035969025), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V3_V3_nsa_gfx11
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V3_V4
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V3_V4_gfx10
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V3_V4_gfx11
    UINT64_C(3825795072), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V3_V4_gfx12
    UINT64_C(4038852610), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V3_V4_nsa_gfx10
    UINT64_C(4035969025), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V3_V4_nsa_gfx11
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V4_V2
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V4_V2_gfx10
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V4_V2_gfx11
    UINT64_C(3825795072), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V4_V2_gfx12
    UINT64_C(4038852610), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V4_V2_nsa_gfx10
    UINT64_C(4035969025), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V4_V2_nsa_gfx11
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V4_V3
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V4_V3_gfx10
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V4_V3_gfx11
    UINT64_C(3825795072), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V4_V3_gfx12
    UINT64_C(4038852610), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V4_V3_nsa_gfx10
    UINT64_C(4035969025), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V4_V3_nsa_gfx11
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V4_V4
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V4_V4_gfx10
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V4_V4_gfx11
    UINT64_C(3825795072), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V4_V4_gfx12
    UINT64_C(4038852610), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V4_V4_nsa_gfx10
    UINT64_C(4035969025), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V4_V4_nsa_gfx11
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V5_V2
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V5_V2_gfx10
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V5_V2_gfx11
    UINT64_C(3825795072), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V5_V2_gfx12
    UINT64_C(4038852610), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V5_V2_nsa_gfx10
    UINT64_C(4035969025), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V5_V2_nsa_gfx11
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V5_V3
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V5_V3_gfx10
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V5_V3_gfx11
    UINT64_C(3825795072), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V5_V3_gfx12
    UINT64_C(4038852610), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V5_V3_nsa_gfx10
    UINT64_C(4035969025), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V5_V3_nsa_gfx11
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V5_V4
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V5_V4_gfx10
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V5_V4_gfx11
    UINT64_C(3825795072), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V5_V4_gfx12
    UINT64_C(4038852610), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V5_V4_nsa_gfx10
    UINT64_C(4035969025), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_V5_V4_nsa_gfx11
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_nortn_V2_gfx10
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_nortn_V2_gfx11
    UINT64_C(3825795072), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_nortn_V2_gfx12
    UINT64_C(4038852610), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_nortn_V2_nsa_gfx10
    UINT64_C(4035969025), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_nortn_V2_nsa_gfx11
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_nortn_V3_gfx10
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_nortn_V3_gfx11
    UINT64_C(3825795072), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_nortn_V3_gfx12
    UINT64_C(4038852610), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_nortn_V3_nsa_gfx10
    UINT64_C(4035969025), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_nortn_V3_nsa_gfx11
    UINT64_C(4038852608), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_nortn_V4_gfx10
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_nortn_V4_gfx11
    UINT64_C(3825795072), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_nortn_V4_gfx12
    UINT64_C(4038852610), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_nortn_V4_nsa_gfx10
    UINT64_C(4035969025), UINT64_C(0),	// IMAGE_SAMPLE_C_LZ_nortn_V4_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V3
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V3_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V3_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V3_gfx12
    UINT64_C(4042260482), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V3_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V3_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V4
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V4_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V4_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V4_gfx12
    UINT64_C(4042260482), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V4_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V4_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V5
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V5_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V5_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V5_gfx12
    UINT64_C(4042260482), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V5_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V5_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V6
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V6_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V6_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V6_gfx12
    UINT64_C(4042260484), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V6_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V6_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V8
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V8_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V1_V8_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V3
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V3_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V3_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V3_gfx12
    UINT64_C(4042260482), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V3_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V3_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V4
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V4_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V4_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V4_gfx12
    UINT64_C(4042260482), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V4_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V4_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V5
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V5_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V5_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V5_gfx12
    UINT64_C(4042260482), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V5_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V5_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V6
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V6_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V6_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V6_gfx12
    UINT64_C(4042260484), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V6_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V6_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V8
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V8_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V2_V8_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V3
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V3_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V3_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V3_gfx12
    UINT64_C(4042260482), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V3_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V3_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V4
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V4_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V4_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V4_gfx12
    UINT64_C(4042260482), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V4_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V4_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V5
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V5_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V5_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V5_gfx12
    UINT64_C(4042260482), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V5_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V5_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V6
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V6_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V6_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V6_gfx12
    UINT64_C(4042260484), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V6_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V6_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V8
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V8_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V3_V8_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V3
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V3_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V3_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V3_gfx12
    UINT64_C(4042260482), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V3_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V3_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V4
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V4_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V4_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V4_gfx12
    UINT64_C(4042260482), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V4_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V4_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V5
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V5_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V5_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V5_gfx12
    UINT64_C(4042260482), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V5_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V5_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V6
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V6_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V6_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V6_gfx12
    UINT64_C(4042260484), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V6_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V6_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V8
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V8_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V4_V8_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V3
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V3_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V3_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V3_gfx12
    UINT64_C(4042260482), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V3_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V3_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V4
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V4_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V4_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V4_gfx12
    UINT64_C(4042260482), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V4_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V4_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V5
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V5_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V5_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V5_gfx12
    UINT64_C(4042260482), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V5_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V5_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V6
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V6_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V6_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V6_gfx12
    UINT64_C(4042260484), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V6_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V6_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V8
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V8_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_V5_V8_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V3_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V3_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V3_gfx12
    UINT64_C(4042260482), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V3_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V3_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V4_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V4_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V4_gfx12
    UINT64_C(4042260482), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V4_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V4_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V5_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V5_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V5_gfx12
    UINT64_C(4042260482), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V5_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V5_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V6_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V6_gfx11
    UINT64_C(3825926144), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V6_gfx12
    UINT64_C(4042260484), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V6_nsa_gfx10
    UINT64_C(4038066177), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V6_nsa_gfx11
    UINT64_C(4042260480), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V8_gfx10
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_O_nortn_V8_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V2
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V2_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V2_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V2_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V2_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V2_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V3
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V3_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V3_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V3_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V3_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V3_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V4
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V4_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V4_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V4_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V4_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V4_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V5
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V5_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V5_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V5_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V5_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V5_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V8
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V8_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V1_V8_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V2
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V2_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V2_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V2_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V2_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V2_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V3
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V3_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V3_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V3_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V3_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V3_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V4
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V4_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V4_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V4_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V4_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V4_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V5
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V5_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V5_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V5_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V5_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V5_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V8
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V8_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V2_V8_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V2
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V2_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V2_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V2_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V2_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V2_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V3
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V3_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V3_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V3_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V3_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V3_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V4
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V4_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V4_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V4_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V4_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V4_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V5
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V5_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V5_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V5_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V5_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V5_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V8
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V8_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V3_V8_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V2
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V2_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V2_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V2_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V2_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V2_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V3
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V3_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V3_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V3_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V3_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V3_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V4
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V4_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V4_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V4_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V4_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V4_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V5
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V5_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V5_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V5_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V5_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V5_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V8
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V8_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V4_V8_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V2
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V2_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V2_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V2_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V2_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V2_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V3
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V3_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V3_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V3_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V3_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V3_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V4
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V4_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V4_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V4_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V4_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V4_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V5
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V5_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V5_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V5_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V5_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V5_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V8
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V8_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_V5_V8_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V2_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V2_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V2_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V2_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V2_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V3_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V3_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V3_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V3_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V3_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V4_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V4_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V4_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V4_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V4_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V5_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V5_gfx11
    UINT64_C(3825762304), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V5_gfx12
    UINT64_C(4038066178), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V5_nsa_gfx10
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V5_nsa_gfx11
    UINT64_C(4038066176), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V8_gfx10
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_C_L_nortn_V8_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V3
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V3_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V3_gfx11
    UINT64_C(3825893376), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V3_gfx12
    UINT64_C(4041211906), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V3_nsa_gfx10
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V3_nsa_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V4
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V4_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V4_gfx11
    UINT64_C(3825893376), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V4_gfx12
    UINT64_C(4041211906), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V4_nsa_gfx10
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V4_nsa_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V5
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V5_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V5_gfx11
    UINT64_C(3825893376), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V5_gfx12
    UINT64_C(4041211906), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V5_nsa_gfx10
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V5_nsa_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V8
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V8_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V1_V8_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V3
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V3_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V3_gfx11
    UINT64_C(3825893376), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V3_gfx12
    UINT64_C(4041211906), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V3_nsa_gfx10
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V3_nsa_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V4
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V4_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V4_gfx11
    UINT64_C(3825893376), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V4_gfx12
    UINT64_C(4041211906), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V4_nsa_gfx10
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V4_nsa_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V5
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V5_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V5_gfx11
    UINT64_C(3825893376), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V5_gfx12
    UINT64_C(4041211906), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V5_nsa_gfx10
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V5_nsa_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V8
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V8_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V2_V8_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V3
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V3_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V3_gfx11
    UINT64_C(3825893376), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V3_gfx12
    UINT64_C(4041211906), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V3_nsa_gfx10
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V3_nsa_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V4
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V4_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V4_gfx11
    UINT64_C(3825893376), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V4_gfx12
    UINT64_C(4041211906), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V4_nsa_gfx10
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V4_nsa_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V5
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V5_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V5_gfx11
    UINT64_C(3825893376), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V5_gfx12
    UINT64_C(4041211906), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V5_nsa_gfx10
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V5_nsa_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V8
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V8_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V3_V8_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V3
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V3_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V3_gfx11
    UINT64_C(3825893376), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V3_gfx12
    UINT64_C(4041211906), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V3_nsa_gfx10
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V3_nsa_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V4
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V4_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V4_gfx11
    UINT64_C(3825893376), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V4_gfx12
    UINT64_C(4041211906), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V4_nsa_gfx10
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V4_nsa_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V5
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V5_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V5_gfx11
    UINT64_C(3825893376), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V5_gfx12
    UINT64_C(4041211906), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V5_nsa_gfx10
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V5_nsa_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V8
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V8_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V4_V8_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V3
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V3_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V3_gfx11
    UINT64_C(3825893376), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V3_gfx12
    UINT64_C(4041211906), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V3_nsa_gfx10
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V3_nsa_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V4
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V4_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V4_gfx11
    UINT64_C(3825893376), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V4_gfx12
    UINT64_C(4041211906), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V4_nsa_gfx10
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V4_nsa_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V5
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V5_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V5_gfx11
    UINT64_C(3825893376), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V5_gfx12
    UINT64_C(4041211906), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V5_nsa_gfx10
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V5_nsa_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V8
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V8_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_V5_V8_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_nortn_V3_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_nortn_V3_gfx11
    UINT64_C(3825893376), UINT64_C(0),	// IMAGE_SAMPLE_C_O_nortn_V3_gfx12
    UINT64_C(4041211906), UINT64_C(0),	// IMAGE_SAMPLE_C_O_nortn_V3_nsa_gfx10
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_O_nortn_V3_nsa_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_nortn_V4_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_nortn_V4_gfx11
    UINT64_C(3825893376), UINT64_C(0),	// IMAGE_SAMPLE_C_O_nortn_V4_gfx12
    UINT64_C(4041211906), UINT64_C(0),	// IMAGE_SAMPLE_C_O_nortn_V4_nsa_gfx10
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_O_nortn_V4_nsa_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_nortn_V5_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_nortn_V5_gfx11
    UINT64_C(3825893376), UINT64_C(0),	// IMAGE_SAMPLE_C_O_nortn_V5_gfx12
    UINT64_C(4041211906), UINT64_C(0),	// IMAGE_SAMPLE_C_O_nortn_V5_nsa_gfx10
    UINT64_C(4037541889), UINT64_C(0),	// IMAGE_SAMPLE_C_O_nortn_V5_nsa_gfx11
    UINT64_C(4041211904), UINT64_C(0),	// IMAGE_SAMPLE_C_O_nortn_V8_gfx10
    UINT64_C(4037541888), UINT64_C(0),	// IMAGE_SAMPLE_C_O_nortn_V8_gfx11
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V1_V2
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V1_V2_gfx10
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_C_V1_V2_gfx11
    UINT64_C(3825729536), UINT64_C(0),	// IMAGE_SAMPLE_C_V1_V2_gfx12
    UINT64_C(4037017602), UINT64_C(0),	// IMAGE_SAMPLE_C_V1_V2_nsa_gfx10
    UINT64_C(4034920449), UINT64_C(0),	// IMAGE_SAMPLE_C_V1_V2_nsa_gfx11
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V1_V3
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V1_V3_gfx10
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_C_V1_V3_gfx11
    UINT64_C(3825729536), UINT64_C(0),	// IMAGE_SAMPLE_C_V1_V3_gfx12
    UINT64_C(4037017602), UINT64_C(0),	// IMAGE_SAMPLE_C_V1_V3_nsa_gfx10
    UINT64_C(4034920449), UINT64_C(0),	// IMAGE_SAMPLE_C_V1_V3_nsa_gfx11
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V1_V4
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V1_V4_gfx10
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_C_V1_V4_gfx11
    UINT64_C(3825729536), UINT64_C(0),	// IMAGE_SAMPLE_C_V1_V4_gfx12
    UINT64_C(4037017602), UINT64_C(0),	// IMAGE_SAMPLE_C_V1_V4_nsa_gfx10
    UINT64_C(4034920449), UINT64_C(0),	// IMAGE_SAMPLE_C_V1_V4_nsa_gfx11
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V2_V2
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V2_V2_gfx10
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_C_V2_V2_gfx11
    UINT64_C(3825729536), UINT64_C(0),	// IMAGE_SAMPLE_C_V2_V2_gfx12
    UINT64_C(4037017602), UINT64_C(0),	// IMAGE_SAMPLE_C_V2_V2_nsa_gfx10
    UINT64_C(4034920449), UINT64_C(0),	// IMAGE_SAMPLE_C_V2_V2_nsa_gfx11
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V2_V3
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V2_V3_gfx10
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_C_V2_V3_gfx11
    UINT64_C(3825729536), UINT64_C(0),	// IMAGE_SAMPLE_C_V2_V3_gfx12
    UINT64_C(4037017602), UINT64_C(0),	// IMAGE_SAMPLE_C_V2_V3_nsa_gfx10
    UINT64_C(4034920449), UINT64_C(0),	// IMAGE_SAMPLE_C_V2_V3_nsa_gfx11
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V2_V4
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V2_V4_gfx10
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_C_V2_V4_gfx11
    UINT64_C(3825729536), UINT64_C(0),	// IMAGE_SAMPLE_C_V2_V4_gfx12
    UINT64_C(4037017602), UINT64_C(0),	// IMAGE_SAMPLE_C_V2_V4_nsa_gfx10
    UINT64_C(4034920449), UINT64_C(0),	// IMAGE_SAMPLE_C_V2_V4_nsa_gfx11
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V3_V2
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V3_V2_gfx10
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_C_V3_V2_gfx11
    UINT64_C(3825729536), UINT64_C(0),	// IMAGE_SAMPLE_C_V3_V2_gfx12
    UINT64_C(4037017602), UINT64_C(0),	// IMAGE_SAMPLE_C_V3_V2_nsa_gfx10
    UINT64_C(4034920449), UINT64_C(0),	// IMAGE_SAMPLE_C_V3_V2_nsa_gfx11
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V3_V3
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V3_V3_gfx10
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_C_V3_V3_gfx11
    UINT64_C(3825729536), UINT64_C(0),	// IMAGE_SAMPLE_C_V3_V3_gfx12
    UINT64_C(4037017602), UINT64_C(0),	// IMAGE_SAMPLE_C_V3_V3_nsa_gfx10
    UINT64_C(4034920449), UINT64_C(0),	// IMAGE_SAMPLE_C_V3_V3_nsa_gfx11
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V3_V4
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V3_V4_gfx10
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_C_V3_V4_gfx11
    UINT64_C(3825729536), UINT64_C(0),	// IMAGE_SAMPLE_C_V3_V4_gfx12
    UINT64_C(4037017602), UINT64_C(0),	// IMAGE_SAMPLE_C_V3_V4_nsa_gfx10
    UINT64_C(4034920449), UINT64_C(0),	// IMAGE_SAMPLE_C_V3_V4_nsa_gfx11
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V4_V2
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V4_V2_gfx10
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_C_V4_V2_gfx11
    UINT64_C(3825729536), UINT64_C(0),	// IMAGE_SAMPLE_C_V4_V2_gfx12
    UINT64_C(4037017602), UINT64_C(0),	// IMAGE_SAMPLE_C_V4_V2_nsa_gfx10
    UINT64_C(4034920449), UINT64_C(0),	// IMAGE_SAMPLE_C_V4_V2_nsa_gfx11
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V4_V3
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V4_V3_gfx10
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_C_V4_V3_gfx11
    UINT64_C(3825729536), UINT64_C(0),	// IMAGE_SAMPLE_C_V4_V3_gfx12
    UINT64_C(4037017602), UINT64_C(0),	// IMAGE_SAMPLE_C_V4_V3_nsa_gfx10
    UINT64_C(4034920449), UINT64_C(0),	// IMAGE_SAMPLE_C_V4_V3_nsa_gfx11
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V4_V4
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V4_V4_gfx10
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_C_V4_V4_gfx11
    UINT64_C(3825729536), UINT64_C(0),	// IMAGE_SAMPLE_C_V4_V4_gfx12
    UINT64_C(4037017602), UINT64_C(0),	// IMAGE_SAMPLE_C_V4_V4_nsa_gfx10
    UINT64_C(4034920449), UINT64_C(0),	// IMAGE_SAMPLE_C_V4_V4_nsa_gfx11
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V5_V2
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V5_V2_gfx10
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_C_V5_V2_gfx11
    UINT64_C(3825729536), UINT64_C(0),	// IMAGE_SAMPLE_C_V5_V2_gfx12
    UINT64_C(4037017602), UINT64_C(0),	// IMAGE_SAMPLE_C_V5_V2_nsa_gfx10
    UINT64_C(4034920449), UINT64_C(0),	// IMAGE_SAMPLE_C_V5_V2_nsa_gfx11
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V5_V3
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V5_V3_gfx10
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_C_V5_V3_gfx11
    UINT64_C(3825729536), UINT64_C(0),	// IMAGE_SAMPLE_C_V5_V3_gfx12
    UINT64_C(4037017602), UINT64_C(0),	// IMAGE_SAMPLE_C_V5_V3_nsa_gfx10
    UINT64_C(4034920449), UINT64_C(0),	// IMAGE_SAMPLE_C_V5_V3_nsa_gfx11
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V5_V4
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_V5_V4_gfx10
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_C_V5_V4_gfx11
    UINT64_C(3825729536), UINT64_C(0),	// IMAGE_SAMPLE_C_V5_V4_gfx12
    UINT64_C(4037017602), UINT64_C(0),	// IMAGE_SAMPLE_C_V5_V4_nsa_gfx10
    UINT64_C(4034920449), UINT64_C(0),	// IMAGE_SAMPLE_C_V5_V4_nsa_gfx11
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_nortn_V2_gfx10
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_C_nortn_V2_gfx11
    UINT64_C(3825729536), UINT64_C(0),	// IMAGE_SAMPLE_C_nortn_V2_gfx12
    UINT64_C(4037017602), UINT64_C(0),	// IMAGE_SAMPLE_C_nortn_V2_nsa_gfx10
    UINT64_C(4034920449), UINT64_C(0),	// IMAGE_SAMPLE_C_nortn_V2_nsa_gfx11
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_nortn_V3_gfx10
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_C_nortn_V3_gfx11
    UINT64_C(3825729536), UINT64_C(0),	// IMAGE_SAMPLE_C_nortn_V3_gfx12
    UINT64_C(4037017602), UINT64_C(0),	// IMAGE_SAMPLE_C_nortn_V3_nsa_gfx10
    UINT64_C(4034920449), UINT64_C(0),	// IMAGE_SAMPLE_C_nortn_V3_nsa_gfx11
    UINT64_C(4037017600), UINT64_C(0),	// IMAGE_SAMPLE_C_nortn_V4_gfx10
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_C_nortn_V4_gfx11
    UINT64_C(3825729536), UINT64_C(0),	// IMAGE_SAMPLE_C_nortn_V4_gfx12
    UINT64_C(4037017602), UINT64_C(0),	// IMAGE_SAMPLE_C_nortn_V4_nsa_gfx10
    UINT64_C(4034920449), UINT64_C(0),	// IMAGE_SAMPLE_C_nortn_V4_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V2
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V2_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V2_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V2_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V2_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V2_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V3
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V3_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V3_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V3_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V3_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V3_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V4
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V4_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V4_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V4_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V4_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V4_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V5
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V5_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V5_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V5_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V5_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V5_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V6
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V6_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V6_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V6_gfx12
    UINT64_C(4035706885), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V6_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V6_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V7
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V7_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V7_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V7_gfx12
    UINT64_C(4035706885), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V7_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V7_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V8
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V8_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V8_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V8_gfx12
    UINT64_C(4035706885), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V8_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V1_V8_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V2
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V2_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V2_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V2_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V2_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V2_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V3
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V3_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V3_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V3_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V3_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V3_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V4
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V4_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V4_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V4_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V4_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V4_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V5
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V5_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V5_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V5_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V5_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V5_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V6
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V6_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V6_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V6_gfx12
    UINT64_C(4035706885), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V6_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V6_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V7
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V7_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V7_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V7_gfx12
    UINT64_C(4035706885), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V7_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V7_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V8
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V8_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V8_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V8_gfx12
    UINT64_C(4035706885), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V8_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V2_V8_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V2
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V2_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V2_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V2_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V2_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V2_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V3
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V3_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V3_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V3_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V3_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V3_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V4
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V4_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V4_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V4_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V4_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V4_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V5
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V5_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V5_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V5_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V5_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V5_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V6
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V6_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V6_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V6_gfx12
    UINT64_C(4035706885), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V6_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V6_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V7
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V7_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V7_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V7_gfx12
    UINT64_C(4035706885), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V7_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V7_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V8
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V8_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V8_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V8_gfx12
    UINT64_C(4035706885), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V8_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V3_V8_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V2
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V2_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V2_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V2_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V2_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V2_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V3
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V3_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V3_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V3_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V3_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V3_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V4
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V4_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V4_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V4_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V4_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V4_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V5
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V5_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V5_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V5_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V5_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V5_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V6
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V6_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V6_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V6_gfx12
    UINT64_C(4035706885), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V6_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V6_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V7
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V7_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V7_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V7_gfx12
    UINT64_C(4035706885), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V7_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V7_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V8
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V8_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V8_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V8_gfx12
    UINT64_C(4035706885), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V8_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V4_V8_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V2
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V2_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V2_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V2_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V2_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V2_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V3
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V3_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V3_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V3_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V3_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V3_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V4
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V4_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V4_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V4_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V4_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V4_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V5
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V5_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V5_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V5_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V5_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V5_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V6
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V6_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V6_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V6_gfx12
    UINT64_C(4035706885), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V6_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V6_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V7
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V7_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V7_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V7_gfx12
    UINT64_C(4035706885), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V7_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V7_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V8
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V8_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V8_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V8_gfx12
    UINT64_C(4035706885), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V8_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_V5_V8_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V2_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V2_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V2_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V2_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V2_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V3_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V3_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V3_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V3_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V3_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V4_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V4_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V4_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V4_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V4_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V5_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V5_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V5_gfx12
    UINT64_C(4035706883), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V5_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V5_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V6_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V6_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V6_gfx12
    UINT64_C(4035706885), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V6_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V6_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V7_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V7_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V7_gfx12
    UINT64_C(4035706885), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V7_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V7_nsa_gfx11
    UINT64_C(4035706881), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V8_gfx10
    UINT64_C(4051435520), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V8_gfx11
    UINT64_C(3826761728), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V8_gfx12
    UINT64_C(4035706885), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V8_nsa_gfx10
    UINT64_C(4051435521), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_G16_nortn_V8_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V3
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V3_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V3_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V3_gfx12
    UINT64_C(4039901187), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V3_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V3_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V4
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V4_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V4_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V4_gfx12
    UINT64_C(4039901187), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V4_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V4_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V5
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V5_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V5_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V5_gfx12
    UINT64_C(4039901187), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V5_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V5_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V6
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V6_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V6_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V6_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V6_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V6_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V7
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V7_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V7_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V7_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V7_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V7_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V8
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V8_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V8_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V8_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V8_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V8_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V9
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V9_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V9_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V9_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V9_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V1_V9_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V3
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V3_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V3_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V3_gfx12
    UINT64_C(4039901187), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V3_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V3_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V4
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V4_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V4_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V4_gfx12
    UINT64_C(4039901187), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V4_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V4_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V5
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V5_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V5_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V5_gfx12
    UINT64_C(4039901187), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V5_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V5_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V6
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V6_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V6_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V6_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V6_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V6_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V7
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V7_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V7_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V7_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V7_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V7_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V8
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V8_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V8_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V8_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V8_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V8_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V9
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V9_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V9_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V9_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V9_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V2_V9_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V3
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V3_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V3_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V3_gfx12
    UINT64_C(4039901187), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V3_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V3_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V4
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V4_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V4_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V4_gfx12
    UINT64_C(4039901187), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V4_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V4_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V5
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V5_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V5_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V5_gfx12
    UINT64_C(4039901187), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V5_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V5_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V6
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V6_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V6_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V6_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V6_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V6_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V7
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V7_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V7_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V7_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V7_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V7_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V8
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V8_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V8_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V8_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V8_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V8_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V9
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V9_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V9_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V9_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V9_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V3_V9_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V3
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V3_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V3_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V3_gfx12
    UINT64_C(4039901187), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V3_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V3_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V4
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V4_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V4_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V4_gfx12
    UINT64_C(4039901187), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V4_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V4_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V5
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V5_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V5_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V5_gfx12
    UINT64_C(4039901187), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V5_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V5_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V6
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V6_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V6_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V6_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V6_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V6_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V7
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V7_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V7_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V7_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V7_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V7_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V8
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V8_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V8_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V8_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V8_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V8_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V9
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V9_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V9_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V9_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V9_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V4_V9_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V3
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V3_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V3_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V3_gfx12
    UINT64_C(4039901187), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V3_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V3_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V4
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V4_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V4_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V4_gfx12
    UINT64_C(4039901187), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V4_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V4_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V5
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V5_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V5_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V5_gfx12
    UINT64_C(4039901187), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V5_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V5_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V6
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V6_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V6_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V6_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V6_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V6_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V7
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V7_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V7_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V7_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V7_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V7_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V8
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V8_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V8_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V8_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V8_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V8_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V9
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V9_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V9_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V9_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V9_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_V5_V9_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V3_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V3_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V3_gfx12
    UINT64_C(4039901187), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V3_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V3_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V4_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V4_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V4_gfx12
    UINT64_C(4039901187), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V4_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V4_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V5_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V5_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V5_gfx12
    UINT64_C(4039901187), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V5_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V5_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V6_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V6_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V6_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V6_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V6_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V7_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V7_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V7_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V7_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V7_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V8_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V8_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V8_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V8_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V8_nsa_gfx11
    UINT64_C(4039901185), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V9_gfx10
    UINT64_C(4048814080), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V9_gfx11
    UINT64_C(3826597888), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V9_gfx12
    UINT64_C(4039901189), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V9_nsa_gfx10
    UINT64_C(4048814081), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_G16_nortn_V9_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V10
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V10_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V10_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V10_gfx12
    UINT64_C(4039901190), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V10_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V10_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V11_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V11_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V11_gfx12
    UINT64_C(4039901190), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V11_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V11_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V3
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V3_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V3_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V3_gfx12
    UINT64_C(4039901186), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V3_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V3_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V4
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V4_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V4_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V4_gfx12
    UINT64_C(4039901186), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V4_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V4_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V5
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V5_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V5_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V5_gfx12
    UINT64_C(4039901186), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V5_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V5_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V6
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V6_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V6_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V6_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V6_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V6_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V7
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V7_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V7_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V7_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V7_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V7_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V8
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V8_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V8_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V8_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V8_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V8_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V9
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V9_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V9_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V9_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V9_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V1_V9_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V10
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V10_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V10_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V10_gfx12
    UINT64_C(4039901190), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V10_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V10_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V11_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V11_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V11_gfx12
    UINT64_C(4039901190), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V11_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V11_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V3
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V3_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V3_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V3_gfx12
    UINT64_C(4039901186), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V3_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V3_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V4
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V4_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V4_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V4_gfx12
    UINT64_C(4039901186), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V4_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V4_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V5
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V5_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V5_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V5_gfx12
    UINT64_C(4039901186), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V5_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V5_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V6
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V6_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V6_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V6_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V6_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V6_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V7
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V7_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V7_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V7_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V7_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V7_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V8
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V8_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V8_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V8_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V8_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V8_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V9
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V9_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V9_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V9_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V9_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V2_V9_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V10
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V10_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V10_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V10_gfx12
    UINT64_C(4039901190), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V10_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V10_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V11_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V11_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V11_gfx12
    UINT64_C(4039901190), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V11_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V11_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V3
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V3_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V3_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V3_gfx12
    UINT64_C(4039901186), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V3_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V3_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V4
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V4_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V4_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V4_gfx12
    UINT64_C(4039901186), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V4_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V4_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V5
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V5_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V5_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V5_gfx12
    UINT64_C(4039901186), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V5_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V5_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V6
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V6_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V6_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V6_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V6_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V6_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V7
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V7_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V7_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V7_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V7_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V7_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V8
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V8_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V8_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V8_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V8_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V8_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V9
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V9_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V9_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V9_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V9_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V3_V9_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V10
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V10_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V10_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V10_gfx12
    UINT64_C(4039901190), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V10_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V10_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V11_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V11_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V11_gfx12
    UINT64_C(4039901190), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V11_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V11_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V3
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V3_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V3_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V3_gfx12
    UINT64_C(4039901186), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V3_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V3_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V4
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V4_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V4_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V4_gfx12
    UINT64_C(4039901186), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V4_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V4_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V5
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V5_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V5_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V5_gfx12
    UINT64_C(4039901186), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V5_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V5_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V6
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V6_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V6_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V6_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V6_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V6_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V7
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V7_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V7_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V7_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V7_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V7_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V8
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V8_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V8_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V8_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V8_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V8_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V9
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V9_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V9_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V9_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V9_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V4_V9_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V10
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V10_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V10_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V10_gfx12
    UINT64_C(4039901190), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V10_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V10_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V11_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V11_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V11_gfx12
    UINT64_C(4039901190), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V11_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V11_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V3
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V3_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V3_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V3_gfx12
    UINT64_C(4039901186), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V3_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V3_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V4
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V4_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V4_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V4_gfx12
    UINT64_C(4039901186), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V4_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V4_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V5
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V5_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V5_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V5_gfx12
    UINT64_C(4039901186), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V5_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V5_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V6
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V6_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V6_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V6_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V6_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V6_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V7
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V7_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V7_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V7_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V7_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V7_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V8
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V8_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V8_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V8_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V8_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V8_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V9
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V9_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V9_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V9_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V9_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_V5_V9_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V10_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V10_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V10_gfx12
    UINT64_C(4039901190), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V10_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V10_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V11_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V11_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V11_gfx12
    UINT64_C(4039901190), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V11_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V11_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V3_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V3_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V3_gfx12
    UINT64_C(4039901186), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V3_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V3_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V4_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V4_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V4_gfx12
    UINT64_C(4039901186), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V4_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V4_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V5_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V5_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V5_gfx12
    UINT64_C(4039901186), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V5_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V5_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V6_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V6_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V6_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V6_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V6_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V7_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V7_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V7_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V7_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V7_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V8_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V8_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V8_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V8_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V8_nsa_gfx11
    UINT64_C(4039901184), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V9_gfx10
    UINT64_C(4045144064), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V9_gfx11
    UINT64_C(3826368512), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V9_gfx12
    UINT64_C(4039901188), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V9_nsa_gfx10
    UINT64_C(4045144065), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_O_nortn_V9_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V10_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V10_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V10_gfx12
    UINT64_C(4035706886), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V10_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V10_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V2
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V2_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V2_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V2_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V2_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V2_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V3
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V3_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V3_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V3_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V3_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V3_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V4
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V4_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V4_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V4_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V4_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V4_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V5
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V5_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V5_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V5_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V5_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V5_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V6
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V6_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V6_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V6_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V6_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V6_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V7
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V7_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V7_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V7_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V7_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V7_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V8
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V8_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V8_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V8_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V8_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V8_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V9
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V9_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V9_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V9_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V9_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V1_V9_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V10_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V10_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V10_gfx12
    UINT64_C(4035706886), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V10_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V10_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V2
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V2_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V2_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V2_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V2_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V2_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V3
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V3_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V3_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V3_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V3_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V3_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V4
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V4_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V4_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V4_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V4_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V4_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V5
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V5_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V5_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V5_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V5_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V5_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V6
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V6_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V6_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V6_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V6_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V6_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V7
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V7_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V7_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V7_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V7_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V7_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V8
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V8_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V8_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V8_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V8_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V8_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V9
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V9_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V9_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V9_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V9_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V2_V9_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V10_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V10_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V10_gfx12
    UINT64_C(4035706886), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V10_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V10_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V2
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V2_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V2_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V2_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V2_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V2_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V3
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V3_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V3_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V3_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V3_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V3_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V4
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V4_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V4_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V4_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V4_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V4_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V5
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V5_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V5_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V5_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V5_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V5_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V6
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V6_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V6_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V6_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V6_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V6_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V7
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V7_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V7_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V7_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V7_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V7_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V8
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V8_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V8_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V8_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V8_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V8_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V9
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V9_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V9_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V9_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V9_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V3_V9_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V10_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V10_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V10_gfx12
    UINT64_C(4035706886), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V10_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V10_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V2
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V2_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V2_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V2_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V2_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V2_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V3
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V3_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V3_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V3_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V3_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V3_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V4
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V4_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V4_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V4_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V4_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V4_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V5
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V5_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V5_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V5_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V5_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V5_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V6
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V6_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V6_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V6_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V6_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V6_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V7
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V7_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V7_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V7_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V7_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V7_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V8
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V8_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V8_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V8_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V8_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V8_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V9
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V9_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V9_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V9_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V9_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V4_V9_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V10
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V10_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V10_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V10_gfx12
    UINT64_C(4035706886), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V10_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V10_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V2
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V2_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V2_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V2_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V2_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V2_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V3
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V3_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V3_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V3_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V3_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V3_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V4
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V4_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V4_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V4_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V4_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V4_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V5
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V5_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V5_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V5_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V5_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V5_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V6
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V6_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V6_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V6_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V6_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V6_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V7
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V7_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V7_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V7_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V7_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V7_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V8
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V8_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V8_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V8_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V8_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V8_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V9
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V9_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V9_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V9_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V9_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_V5_V9_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V10_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V10_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V10_gfx12
    UINT64_C(4035706886), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V10_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V10_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V2_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V2_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V2_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V2_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V2_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V3_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V3_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V3_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V3_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V3_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V4_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V4_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V4_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V4_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V4_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V5_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V5_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V5_gfx12
    UINT64_C(4035706882), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V5_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V5_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V6_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V6_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V6_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V6_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V6_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V7_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V7_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V7_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V7_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V7_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V8_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V8_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V8_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V8_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V8_nsa_gfx11
    UINT64_C(4035706880), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V9_gfx10
    UINT64_C(4043571200), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V9_gfx11
    UINT64_C(3826270208), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V9_gfx12
    UINT64_C(4035706884), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V9_nsa_gfx10
    UINT64_C(4043571201), UINT64_C(0),	// IMAGE_SAMPLE_D_CL_nortn_V9_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V2
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V2_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V2_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V2_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V2_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V2_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V3
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V3_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V3_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V3_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V3_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V3_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V4
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V4_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V4_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V4_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V4_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V4_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V5
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V5_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V5_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V5_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V5_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V5_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V6
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V6_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V6_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V6_gfx12
    UINT64_C(4035444741), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V6_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V6_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V7
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V7_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V7_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V7_gfx12
    UINT64_C(4035444741), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V7_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V7_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V8
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V8_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V1_V8_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V2
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V2_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V2_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V2_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V2_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V2_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V3
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V3_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V3_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V3_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V3_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V3_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V4
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V4_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V4_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V4_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V4_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V4_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V5
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V5_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V5_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V5_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V5_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V5_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V6
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V6_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V6_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V6_gfx12
    UINT64_C(4035444741), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V6_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V6_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V7
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V7_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V7_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V7_gfx12
    UINT64_C(4035444741), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V7_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V7_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V8
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V8_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V2_V8_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V2
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V2_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V2_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V2_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V2_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V2_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V3
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V3_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V3_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V3_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V3_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V3_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V4
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V4_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V4_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V4_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V4_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V4_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V5
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V5_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V5_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V5_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V5_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V5_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V6
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V6_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V6_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V6_gfx12
    UINT64_C(4035444741), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V6_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V6_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V7
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V7_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V7_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V7_gfx12
    UINT64_C(4035444741), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V7_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V7_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V8
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V8_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V3_V8_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V2
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V2_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V2_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V2_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V2_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V2_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V3
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V3_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V3_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V3_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V3_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V3_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V4
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V4_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V4_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V4_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V4_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V4_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V5
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V5_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V5_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V5_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V5_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V5_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V6
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V6_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V6_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V6_gfx12
    UINT64_C(4035444741), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V6_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V6_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V7
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V7_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V7_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V7_gfx12
    UINT64_C(4035444741), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V7_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V7_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V8
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V8_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V4_V8_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V2
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V2_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V2_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V2_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V2_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V2_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V3
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V3_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V3_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V3_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V3_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V3_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V4
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V4_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V4_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V4_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V4_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V4_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V5
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V5_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V5_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V5_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V5_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V5_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V6
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V6_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V6_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V6_gfx12
    UINT64_C(4035444741), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V6_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V6_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V7
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V7_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V7_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V7_gfx12
    UINT64_C(4035444741), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V7_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V7_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V8
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V8_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_V5_V8_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V2_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V2_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V2_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V2_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V2_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V3_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V3_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V3_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V3_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V3_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V4_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V4_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V4_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V4_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V4_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V5_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V5_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V5_gfx12
    UINT64_C(4035444739), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V5_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V5_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V6_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V6_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V6_gfx12
    UINT64_C(4035444741), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V6_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V6_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V7_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V7_gfx11
    UINT64_C(3826139136), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V7_gfx12
    UINT64_C(4035444741), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V7_nsa_gfx10
    UINT64_C(4041474049), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V7_nsa_gfx11
    UINT64_C(4035444737), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V8_gfx10
    UINT64_C(4041474048), UINT64_C(0),	// IMAGE_SAMPLE_D_G16_nortn_V8_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V3
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V3_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V3_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V3_gfx12
    UINT64_C(4039639043), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V3_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V3_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V4
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V4_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V4_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V4_gfx12
    UINT64_C(4039639043), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V4_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V4_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V5
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V5_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V5_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V5_gfx12
    UINT64_C(4039639043), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V5_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V5_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V6
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V6_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V6_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V6_gfx12
    UINT64_C(4039639045), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V6_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V6_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V7
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V7_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V7_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V7_gfx12
    UINT64_C(4039639045), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V7_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V7_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V8
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V8_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V8_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V8_gfx12
    UINT64_C(4039639045), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V8_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V1_V8_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V3
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V3_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V3_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V3_gfx12
    UINT64_C(4039639043), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V3_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V3_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V4
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V4_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V4_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V4_gfx12
    UINT64_C(4039639043), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V4_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V4_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V5
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V5_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V5_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V5_gfx12
    UINT64_C(4039639043), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V5_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V5_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V6
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V6_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V6_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V6_gfx12
    UINT64_C(4039639045), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V6_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V6_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V7
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V7_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V7_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V7_gfx12
    UINT64_C(4039639045), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V7_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V7_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V8
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V8_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V8_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V8_gfx12
    UINT64_C(4039639045), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V8_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V2_V8_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V3
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V3_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V3_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V3_gfx12
    UINT64_C(4039639043), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V3_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V3_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V4
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V4_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V4_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V4_gfx12
    UINT64_C(4039639043), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V4_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V4_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V5
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V5_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V5_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V5_gfx12
    UINT64_C(4039639043), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V5_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V5_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V6
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V6_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V6_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V6_gfx12
    UINT64_C(4039639045), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V6_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V6_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V7
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V7_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V7_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V7_gfx12
    UINT64_C(4039639045), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V7_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V7_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V8
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V8_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V8_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V8_gfx12
    UINT64_C(4039639045), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V8_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V3_V8_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V3
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V3_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V3_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V3_gfx12
    UINT64_C(4039639043), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V3_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V3_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V4
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V4_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V4_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V4_gfx12
    UINT64_C(4039639043), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V4_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V4_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V5
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V5_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V5_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V5_gfx12
    UINT64_C(4039639043), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V5_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V5_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V6
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V6_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V6_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V6_gfx12
    UINT64_C(4039639045), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V6_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V6_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V7
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V7_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V7_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V7_gfx12
    UINT64_C(4039639045), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V7_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V7_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V8
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V8_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V8_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V8_gfx12
    UINT64_C(4039639045), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V8_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V4_V8_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V3
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V3_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V3_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V3_gfx12
    UINT64_C(4039639043), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V3_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V3_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V4
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V4_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V4_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V4_gfx12
    UINT64_C(4039639043), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V4_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V4_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V5
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V5_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V5_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V5_gfx12
    UINT64_C(4039639043), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V5_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V5_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V6
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V6_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V6_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V6_gfx12
    UINT64_C(4039639045), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V6_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V6_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V7
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V7_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V7_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V7_gfx12
    UINT64_C(4039639045), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V7_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V7_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V8
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V8_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V8_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V8_gfx12
    UINT64_C(4039639045), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V8_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_V5_V8_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V3_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V3_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V3_gfx12
    UINT64_C(4039639043), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V3_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V3_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V4_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V4_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V4_gfx12
    UINT64_C(4039639043), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V4_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V4_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V5_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V5_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V5_gfx12
    UINT64_C(4039639043), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V5_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V5_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V6_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V6_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V6_gfx12
    UINT64_C(4039639045), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V6_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V6_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V7_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V7_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V7_gfx12
    UINT64_C(4039639045), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V7_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V7_nsa_gfx11
    UINT64_C(4039639041), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V8_gfx10
    UINT64_C(4041998336), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V8_gfx11
    UINT64_C(3826171904), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V8_gfx12
    UINT64_C(4039639045), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V8_nsa_gfx10
    UINT64_C(4041998337), UINT64_C(0),	// IMAGE_SAMPLE_D_O_G16_nortn_V8_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V10
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V10_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V10_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V10_gfx12
    UINT64_C(4039639046), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V10_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V10_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V3
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V3_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V3_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V3_gfx12
    UINT64_C(4039639042), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V3_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V3_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V4
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V4_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V4_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V4_gfx12
    UINT64_C(4039639042), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V4_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V4_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V5
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V5_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V5_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V5_gfx12
    UINT64_C(4039639042), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V5_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V5_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V6
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V6_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V6_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V6_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V6_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V6_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V7
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V7_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V7_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V7_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V7_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V7_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V8
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V8_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V8_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V8_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V8_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V8_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V9
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V9_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V9_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V9_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V9_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V1_V9_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V10
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V10_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V10_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V10_gfx12
    UINT64_C(4039639046), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V10_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V10_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V3
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V3_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V3_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V3_gfx12
    UINT64_C(4039639042), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V3_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V3_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V4
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V4_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V4_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V4_gfx12
    UINT64_C(4039639042), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V4_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V4_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V5
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V5_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V5_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V5_gfx12
    UINT64_C(4039639042), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V5_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V5_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V6
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V6_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V6_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V6_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V6_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V6_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V7
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V7_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V7_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V7_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V7_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V7_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V8
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V8_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V8_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V8_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V8_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V8_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V9
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V9_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V9_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V9_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V9_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V2_V9_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V10
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V10_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V10_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V10_gfx12
    UINT64_C(4039639046), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V10_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V10_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V3
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V3_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V3_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V3_gfx12
    UINT64_C(4039639042), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V3_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V3_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V4
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V4_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V4_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V4_gfx12
    UINT64_C(4039639042), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V4_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V4_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V5
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V5_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V5_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V5_gfx12
    UINT64_C(4039639042), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V5_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V5_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V6
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V6_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V6_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V6_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V6_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V6_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V7
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V7_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V7_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V7_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V7_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V7_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V8
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V8_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V8_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V8_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V8_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V8_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V9
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V9_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V9_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V9_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V9_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V3_V9_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V10
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V10_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V10_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V10_gfx12
    UINT64_C(4039639046), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V10_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V10_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V3
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V3_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V3_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V3_gfx12
    UINT64_C(4039639042), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V3_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V3_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V4
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V4_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V4_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V4_gfx12
    UINT64_C(4039639042), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V4_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V4_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V5
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V5_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V5_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V5_gfx12
    UINT64_C(4039639042), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V5_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V5_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V6
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V6_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V6_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V6_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V6_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V6_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V7
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V7_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V7_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V7_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V7_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V7_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V8
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V8_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V8_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V8_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V8_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V8_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V9
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V9_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V9_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V9_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V9_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V4_V9_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V10
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V10_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V10_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V10_gfx12
    UINT64_C(4039639046), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V10_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V10_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V3
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V3_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V3_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V3_gfx12
    UINT64_C(4039639042), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V3_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V3_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V4
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V4_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V4_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V4_gfx12
    UINT64_C(4039639042), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V4_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V4_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V5
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V5_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V5_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V5_gfx12
    UINT64_C(4039639042), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V5_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V5_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V6
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V6_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V6_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V6_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V6_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V6_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V7
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V7_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V7_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V7_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V7_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V7_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V8
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V8_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V8_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V8_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V8_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V8_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V9
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V9_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V9_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V9_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V9_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_V5_V9_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V10_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V10_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V10_gfx12
    UINT64_C(4039639046), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V10_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V10_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V3_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V3_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V3_gfx12
    UINT64_C(4039639042), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V3_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V3_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V4_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V4_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V4_gfx12
    UINT64_C(4039639042), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V4_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V4_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V5_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V5_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V5_gfx12
    UINT64_C(4039639042), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V5_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V5_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V6_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V6_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V6_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V6_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V6_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V7_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V7_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V7_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V7_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V7_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V8_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V8_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V8_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V8_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V8_nsa_gfx11
    UINT64_C(4039639040), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V9_gfx10
    UINT64_C(4036493312), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V9_gfx11
    UINT64_C(3825827840), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V9_gfx12
    UINT64_C(4039639044), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V9_nsa_gfx10
    UINT64_C(4036493313), UINT64_C(0),	// IMAGE_SAMPLE_D_O_nortn_V9_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V2
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V2_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V2_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V2_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V2_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V2_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V3
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V3_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V3_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V3_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V3_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V3_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V4
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V4_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V4_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V4_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V4_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V4_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V5
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V5_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V5_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V5_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V5_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V5_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V6
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V6_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V6_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V6_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V6_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V6_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V7
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V7_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V7_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V7_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V7_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V7_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V8
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V8_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V8_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V8_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V8_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V8_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V9
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V9_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V9_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V9_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V9_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V1_V9_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V2
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V2_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V2_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V2_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V2_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V2_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V3
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V3_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V3_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V3_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V3_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V3_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V4
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V4_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V4_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V4_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V4_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V4_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V5
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V5_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V5_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V5_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V5_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V5_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V6
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V6_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V6_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V6_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V6_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V6_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V7
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V7_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V7_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V7_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V7_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V7_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V8
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V8_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V8_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V8_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V8_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V8_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V9
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V9_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V9_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V9_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V9_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V2_V9_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V2
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V2_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V2_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V2_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V2_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V2_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V3
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V3_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V3_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V3_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V3_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V3_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V4
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V4_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V4_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V4_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V4_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V4_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V5
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V5_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V5_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V5_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V5_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V5_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V6
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V6_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V6_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V6_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V6_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V6_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V7
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V7_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V7_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V7_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V7_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V7_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V8
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V8_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V8_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V8_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V8_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V8_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V9
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V9_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V9_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V9_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V9_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V3_V9_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V2
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V2_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V2_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V2_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V2_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V2_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V3
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V3_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V3_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V3_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V3_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V3_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V4
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V4_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V4_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V4_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V4_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V4_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V5
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V5_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V5_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V5_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V5_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V5_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V6
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V6_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V6_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V6_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V6_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V6_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V7
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V7_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V7_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V7_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V7_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V7_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V8
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V8_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V8_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V8_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V8_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V8_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V9
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V9_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V9_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V9_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V9_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V4_V9_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V2
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V2_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V2_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V2_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V2_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V2_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V3
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V3_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V3_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V3_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V3_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V3_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V4
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V4_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V4_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V4_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V4_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V4_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V5
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V5_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V5_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V5_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V5_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V5_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V6
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V6_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V6_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V6_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V6_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V6_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V7
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V7_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V7_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V7_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V7_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V7_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V8
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V8_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V8_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V8_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V8_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V8_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V9
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V9_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V9_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V9_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V9_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_V5_V9_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V2_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V2_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V2_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V2_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V2_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V3_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V3_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V3_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V3_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V3_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V4_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V4_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V4_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V4_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V4_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V5_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V5_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V5_gfx12
    UINT64_C(4035444738), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V5_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V5_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V6_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V6_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V6_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V6_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V6_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V7_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V7_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V7_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V7_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V7_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V8_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V8_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V8_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V8_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V8_nsa_gfx11
    UINT64_C(4035444736), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V9_gfx10
    UINT64_C(4033871872), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V9_gfx11
    UINT64_C(3825664000), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V9_gfx12
    UINT64_C(4035444740), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V9_nsa_gfx10
    UINT64_C(4033871873), UINT64_C(0),	// IMAGE_SAMPLE_D_nortn_V9_nsa_gfx11
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V1_V2
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V1_V2_gfx10
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V1_V2_gfx11
    UINT64_C(3825876992), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V1_V2_gfx12
    UINT64_C(4040949762), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V1_V2_nsa_gfx10
    UINT64_C(4037279745), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V1_V2_nsa_gfx11
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V1_V3
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V1_V3_gfx10
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V1_V3_gfx11
    UINT64_C(3825876992), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V1_V3_gfx12
    UINT64_C(4040949762), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V1_V3_nsa_gfx10
    UINT64_C(4037279745), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V1_V3_nsa_gfx11
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V1_V4
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V1_V4_gfx10
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V1_V4_gfx11
    UINT64_C(3825876992), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V1_V4_gfx12
    UINT64_C(4040949762), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V1_V4_nsa_gfx10
    UINT64_C(4037279745), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V1_V4_nsa_gfx11
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V2_V2
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V2_V2_gfx10
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V2_V2_gfx11
    UINT64_C(3825876992), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V2_V2_gfx12
    UINT64_C(4040949762), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V2_V2_nsa_gfx10
    UINT64_C(4037279745), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V2_V2_nsa_gfx11
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V2_V3
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V2_V3_gfx10
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V2_V3_gfx11
    UINT64_C(3825876992), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V2_V3_gfx12
    UINT64_C(4040949762), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V2_V3_nsa_gfx10
    UINT64_C(4037279745), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V2_V3_nsa_gfx11
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V2_V4
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V2_V4_gfx10
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V2_V4_gfx11
    UINT64_C(3825876992), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V2_V4_gfx12
    UINT64_C(4040949762), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V2_V4_nsa_gfx10
    UINT64_C(4037279745), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V2_V4_nsa_gfx11
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V3_V2
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V3_V2_gfx10
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V3_V2_gfx11
    UINT64_C(3825876992), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V3_V2_gfx12
    UINT64_C(4040949762), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V3_V2_nsa_gfx10
    UINT64_C(4037279745), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V3_V2_nsa_gfx11
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V3_V3
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V3_V3_gfx10
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V3_V3_gfx11
    UINT64_C(3825876992), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V3_V3_gfx12
    UINT64_C(4040949762), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V3_V3_nsa_gfx10
    UINT64_C(4037279745), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V3_V3_nsa_gfx11
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V3_V4
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V3_V4_gfx10
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V3_V4_gfx11
    UINT64_C(3825876992), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V3_V4_gfx12
    UINT64_C(4040949762), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V3_V4_nsa_gfx10
    UINT64_C(4037279745), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V3_V4_nsa_gfx11
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V4_V2
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V4_V2_gfx10
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V4_V2_gfx11
    UINT64_C(3825876992), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V4_V2_gfx12
    UINT64_C(4040949762), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V4_V2_nsa_gfx10
    UINT64_C(4037279745), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V4_V2_nsa_gfx11
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V4_V3
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V4_V3_gfx10
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V4_V3_gfx11
    UINT64_C(3825876992), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V4_V3_gfx12
    UINT64_C(4040949762), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V4_V3_nsa_gfx10
    UINT64_C(4037279745), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V4_V3_nsa_gfx11
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V4_V4
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V4_V4_gfx10
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V4_V4_gfx11
    UINT64_C(3825876992), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V4_V4_gfx12
    UINT64_C(4040949762), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V4_V4_nsa_gfx10
    UINT64_C(4037279745), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V4_V4_nsa_gfx11
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V5_V2
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V5_V2_gfx10
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V5_V2_gfx11
    UINT64_C(3825876992), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V5_V2_gfx12
    UINT64_C(4040949762), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V5_V2_nsa_gfx10
    UINT64_C(4037279745), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V5_V2_nsa_gfx11
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V5_V3
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V5_V3_gfx10
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V5_V3_gfx11
    UINT64_C(3825876992), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V5_V3_gfx12
    UINT64_C(4040949762), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V5_V3_nsa_gfx10
    UINT64_C(4037279745), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V5_V3_nsa_gfx11
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V5_V4
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V5_V4_gfx10
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V5_V4_gfx11
    UINT64_C(3825876992), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V5_V4_gfx12
    UINT64_C(4040949762), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V5_V4_nsa_gfx10
    UINT64_C(4037279745), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_V5_V4_nsa_gfx11
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_nortn_V2_gfx10
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_nortn_V2_gfx11
    UINT64_C(3825876992), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_nortn_V2_gfx12
    UINT64_C(4040949762), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_nortn_V2_nsa_gfx10
    UINT64_C(4037279745), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_nortn_V2_nsa_gfx11
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_nortn_V3_gfx10
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_nortn_V3_gfx11
    UINT64_C(3825876992), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_nortn_V3_gfx12
    UINT64_C(4040949762), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_nortn_V3_nsa_gfx10
    UINT64_C(4037279745), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_nortn_V3_nsa_gfx11
    UINT64_C(4040949760), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_nortn_V4_gfx10
    UINT64_C(4037279744), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_nortn_V4_gfx11
    UINT64_C(3825876992), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_nortn_V4_gfx12
    UINT64_C(4040949762), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_nortn_V4_nsa_gfx10
    UINT64_C(4037279745), UINT64_C(0),	// IMAGE_SAMPLE_LZ_O_nortn_V4_nsa_gfx11
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V1_V1
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V1_V1_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V1_V1_gfx11
    UINT64_C(3825713152), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V1_V1_gfx12
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V1_V2
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V1_V2_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V1_V2_gfx11
    UINT64_C(3825713152), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V1_V2_gfx12
    UINT64_C(4036755458), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V1_V2_nsa_gfx10
    UINT64_C(4034658305), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V1_V2_nsa_gfx11
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V1_V3
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V1_V3_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V1_V3_gfx11
    UINT64_C(3825713152), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V1_V3_gfx12
    UINT64_C(4036755458), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V1_V3_nsa_gfx10
    UINT64_C(4034658305), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V1_V3_nsa_gfx11
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V1_V4
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V1_V4_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V1_V4_gfx11
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V2_V1
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V2_V1_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V2_V1_gfx11
    UINT64_C(3825713152), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V2_V1_gfx12
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V2_V2
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V2_V2_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V2_V2_gfx11
    UINT64_C(3825713152), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V2_V2_gfx12
    UINT64_C(4036755458), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V2_V2_nsa_gfx10
    UINT64_C(4034658305), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V2_V2_nsa_gfx11
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V2_V3
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V2_V3_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V2_V3_gfx11
    UINT64_C(3825713152), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V2_V3_gfx12
    UINT64_C(4036755458), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V2_V3_nsa_gfx10
    UINT64_C(4034658305), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V2_V3_nsa_gfx11
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V2_V4
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V2_V4_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V2_V4_gfx11
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V3_V1
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V3_V1_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V3_V1_gfx11
    UINT64_C(3825713152), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V3_V1_gfx12
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V3_V2
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V3_V2_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V3_V2_gfx11
    UINT64_C(3825713152), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V3_V2_gfx12
    UINT64_C(4036755458), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V3_V2_nsa_gfx10
    UINT64_C(4034658305), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V3_V2_nsa_gfx11
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V3_V3
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V3_V3_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V3_V3_gfx11
    UINT64_C(3825713152), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V3_V3_gfx12
    UINT64_C(4036755458), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V3_V3_nsa_gfx10
    UINT64_C(4034658305), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V3_V3_nsa_gfx11
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V3_V4
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V3_V4_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V3_V4_gfx11
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V4_V1
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V4_V1_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V4_V1_gfx11
    UINT64_C(3825713152), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V4_V1_gfx12
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V4_V2
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V4_V2_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V4_V2_gfx11
    UINT64_C(3825713152), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V4_V2_gfx12
    UINT64_C(4036755458), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V4_V2_nsa_gfx10
    UINT64_C(4034658305), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V4_V2_nsa_gfx11
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V4_V3
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V4_V3_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V4_V3_gfx11
    UINT64_C(3825713152), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V4_V3_gfx12
    UINT64_C(4036755458), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V4_V3_nsa_gfx10
    UINT64_C(4034658305), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V4_V3_nsa_gfx11
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V4_V4
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V4_V4_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V4_V4_gfx11
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V5_V1
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V5_V1_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V5_V1_gfx11
    UINT64_C(3825713152), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V5_V1_gfx12
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V5_V2
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V5_V2_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V5_V2_gfx11
    UINT64_C(3825713152), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V5_V2_gfx12
    UINT64_C(4036755458), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V5_V2_nsa_gfx10
    UINT64_C(4034658305), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V5_V2_nsa_gfx11
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V5_V3
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V5_V3_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V5_V3_gfx11
    UINT64_C(3825713152), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V5_V3_gfx12
    UINT64_C(4036755458), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V5_V3_nsa_gfx10
    UINT64_C(4034658305), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V5_V3_nsa_gfx11
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V5_V4
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V5_V4_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_V5_V4_gfx11
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_nortn_V1_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_nortn_V1_gfx11
    UINT64_C(3825713152), UINT64_C(0),	// IMAGE_SAMPLE_LZ_nortn_V1_gfx12
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_nortn_V2_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_nortn_V2_gfx11
    UINT64_C(3825713152), UINT64_C(0),	// IMAGE_SAMPLE_LZ_nortn_V2_gfx12
    UINT64_C(4036755458), UINT64_C(0),	// IMAGE_SAMPLE_LZ_nortn_V2_nsa_gfx10
    UINT64_C(4034658305), UINT64_C(0),	// IMAGE_SAMPLE_LZ_nortn_V2_nsa_gfx11
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_nortn_V3_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_nortn_V3_gfx11
    UINT64_C(3825713152), UINT64_C(0),	// IMAGE_SAMPLE_LZ_nortn_V3_gfx12
    UINT64_C(4036755458), UINT64_C(0),	// IMAGE_SAMPLE_LZ_nortn_V3_nsa_gfx10
    UINT64_C(4034658305), UINT64_C(0),	// IMAGE_SAMPLE_LZ_nortn_V3_nsa_gfx11
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_LZ_nortn_V4_gfx10
    UINT64_C(4034658304), UINT64_C(0),	// IMAGE_SAMPLE_LZ_nortn_V4_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V2
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V2_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V2_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V2_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V2_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V2_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V3
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V3_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V3_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V3_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V3_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V3_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V4
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V4_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V4_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V4_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V4_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V4_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V5
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V5_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V5_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V5_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V5_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V5_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V8
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V8_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V1_V8_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V2
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V2_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V2_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V2_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V2_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V2_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V3
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V3_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V3_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V3_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V3_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V3_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V4
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V4_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V4_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V4_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V4_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V4_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V5
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V5_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V5_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V5_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V5_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V5_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V8
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V8_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V2_V8_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V2
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V2_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V2_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V2_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V2_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V2_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V3
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V3_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V3_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V3_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V3_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V3_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V4
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V4_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V4_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V4_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V4_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V4_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V5
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V5_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V5_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V5_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V5_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V5_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V8
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V8_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V3_V8_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V2
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V2_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V2_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V2_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V2_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V2_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V3
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V3_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V3_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V3_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V3_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V3_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V4
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V4_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V4_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V4_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V4_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V4_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V5
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V5_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V5_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V5_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V5_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V5_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V8
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V8_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V4_V8_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V2
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V2_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V2_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V2_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V2_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V2_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V3
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V3_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V3_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V3_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V3_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V3_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V4
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V4_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V4_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V4_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V4_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V4_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V5
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V5_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V5_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V5_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V5_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V5_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V8
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V8_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_V5_V8_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V2_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V2_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V2_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V2_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V2_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V3_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V3_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V3_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V3_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V3_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V4_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V4_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V4_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V4_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V4_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V5_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V5_gfx11
    UINT64_C(3825844224), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V5_gfx12
    UINT64_C(4040163330), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V5_nsa_gfx10
    UINT64_C(4036755457), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V5_nsa_gfx11
    UINT64_C(4040163328), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V8_gfx10
    UINT64_C(4036755456), UINT64_C(0),	// IMAGE_SAMPLE_L_O_nortn_V8_gfx11
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V1
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V1_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V1_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V1_gfx12
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V2
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V2_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V2_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V2_gfx12
    UINT64_C(4035969026), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V2_nsa_gfx10
    UINT64_C(4034134017), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V2_nsa_gfx11
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V3
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V3_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V3_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V3_gfx12
    UINT64_C(4035969026), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V3_nsa_gfx10
    UINT64_C(4034134017), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V3_nsa_gfx11
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V4
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V4_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V4_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V4_gfx12
    UINT64_C(4035969026), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V4_nsa_gfx10
    UINT64_C(4034134017), UINT64_C(0),	// IMAGE_SAMPLE_L_V1_V4_nsa_gfx11
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V1
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V1_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V1_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V1_gfx12
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V2
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V2_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V2_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V2_gfx12
    UINT64_C(4035969026), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V2_nsa_gfx10
    UINT64_C(4034134017), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V2_nsa_gfx11
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V3
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V3_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V3_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V3_gfx12
    UINT64_C(4035969026), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V3_nsa_gfx10
    UINT64_C(4034134017), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V3_nsa_gfx11
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V4
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V4_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V4_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V4_gfx12
    UINT64_C(4035969026), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V4_nsa_gfx10
    UINT64_C(4034134017), UINT64_C(0),	// IMAGE_SAMPLE_L_V2_V4_nsa_gfx11
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V1
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V1_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V1_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V1_gfx12
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V2
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V2_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V2_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V2_gfx12
    UINT64_C(4035969026), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V2_nsa_gfx10
    UINT64_C(4034134017), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V2_nsa_gfx11
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V3
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V3_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V3_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V3_gfx12
    UINT64_C(4035969026), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V3_nsa_gfx10
    UINT64_C(4034134017), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V3_nsa_gfx11
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V4
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V4_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V4_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V4_gfx12
    UINT64_C(4035969026), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V4_nsa_gfx10
    UINT64_C(4034134017), UINT64_C(0),	// IMAGE_SAMPLE_L_V3_V4_nsa_gfx11
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V1
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V1_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V1_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V1_gfx12
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V2
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V2_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V2_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V2_gfx12
    UINT64_C(4035969026), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V2_nsa_gfx10
    UINT64_C(4034134017), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V2_nsa_gfx11
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V3
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V3_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V3_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V3_gfx12
    UINT64_C(4035969026), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V3_nsa_gfx10
    UINT64_C(4034134017), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V3_nsa_gfx11
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V4
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V4_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V4_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V4_gfx12
    UINT64_C(4035969026), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V4_nsa_gfx10
    UINT64_C(4034134017), UINT64_C(0),	// IMAGE_SAMPLE_L_V4_V4_nsa_gfx11
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V1
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V1_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V1_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V1_gfx12
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V2
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V2_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V2_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V2_gfx12
    UINT64_C(4035969026), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V2_nsa_gfx10
    UINT64_C(4034134017), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V2_nsa_gfx11
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V3
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V3_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V3_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V3_gfx12
    UINT64_C(4035969026), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V3_nsa_gfx10
    UINT64_C(4034134017), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V3_nsa_gfx11
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V4
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V4_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V4_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V4_gfx12
    UINT64_C(4035969026), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V4_nsa_gfx10
    UINT64_C(4034134017), UINT64_C(0),	// IMAGE_SAMPLE_L_V5_V4_nsa_gfx11
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_nortn_V1_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_nortn_V1_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_nortn_V1_gfx12
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_nortn_V2_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_nortn_V2_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_nortn_V2_gfx12
    UINT64_C(4035969026), UINT64_C(0),	// IMAGE_SAMPLE_L_nortn_V2_nsa_gfx10
    UINT64_C(4034134017), UINT64_C(0),	// IMAGE_SAMPLE_L_nortn_V2_nsa_gfx11
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_nortn_V3_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_nortn_V3_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_nortn_V3_gfx12
    UINT64_C(4035969026), UINT64_C(0),	// IMAGE_SAMPLE_L_nortn_V3_nsa_gfx10
    UINT64_C(4034134017), UINT64_C(0),	// IMAGE_SAMPLE_L_nortn_V3_nsa_gfx11
    UINT64_C(4035969024), UINT64_C(0),	// IMAGE_SAMPLE_L_nortn_V4_gfx10
    UINT64_C(4034134016), UINT64_C(0),	// IMAGE_SAMPLE_L_nortn_V4_gfx11
    UINT64_C(3825680384), UINT64_C(0),	// IMAGE_SAMPLE_L_nortn_V4_gfx12
    UINT64_C(4035969026), UINT64_C(0),	// IMAGE_SAMPLE_L_nortn_V4_nsa_gfx10
    UINT64_C(4034134017), UINT64_C(0),	// IMAGE_SAMPLE_L_nortn_V4_nsa_gfx11
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V1_V2
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V1_V2_gfx10
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_O_V1_V2_gfx11
    UINT64_C(3825811456), UINT64_C(0),	// IMAGE_SAMPLE_O_V1_V2_gfx12
    UINT64_C(4039114754), UINT64_C(0),	// IMAGE_SAMPLE_O_V1_V2_nsa_gfx10
    UINT64_C(4036231169), UINT64_C(0),	// IMAGE_SAMPLE_O_V1_V2_nsa_gfx11
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V1_V3
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V1_V3_gfx10
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_O_V1_V3_gfx11
    UINT64_C(3825811456), UINT64_C(0),	// IMAGE_SAMPLE_O_V1_V3_gfx12
    UINT64_C(4039114754), UINT64_C(0),	// IMAGE_SAMPLE_O_V1_V3_nsa_gfx10
    UINT64_C(4036231169), UINT64_C(0),	// IMAGE_SAMPLE_O_V1_V3_nsa_gfx11
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V1_V4
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V1_V4_gfx10
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_O_V1_V4_gfx11
    UINT64_C(3825811456), UINT64_C(0),	// IMAGE_SAMPLE_O_V1_V4_gfx12
    UINT64_C(4039114754), UINT64_C(0),	// IMAGE_SAMPLE_O_V1_V4_nsa_gfx10
    UINT64_C(4036231169), UINT64_C(0),	// IMAGE_SAMPLE_O_V1_V4_nsa_gfx11
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V2_V2
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V2_V2_gfx10
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_O_V2_V2_gfx11
    UINT64_C(3825811456), UINT64_C(0),	// IMAGE_SAMPLE_O_V2_V2_gfx12
    UINT64_C(4039114754), UINT64_C(0),	// IMAGE_SAMPLE_O_V2_V2_nsa_gfx10
    UINT64_C(4036231169), UINT64_C(0),	// IMAGE_SAMPLE_O_V2_V2_nsa_gfx11
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V2_V3
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V2_V3_gfx10
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_O_V2_V3_gfx11
    UINT64_C(3825811456), UINT64_C(0),	// IMAGE_SAMPLE_O_V2_V3_gfx12
    UINT64_C(4039114754), UINT64_C(0),	// IMAGE_SAMPLE_O_V2_V3_nsa_gfx10
    UINT64_C(4036231169), UINT64_C(0),	// IMAGE_SAMPLE_O_V2_V3_nsa_gfx11
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V2_V4
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V2_V4_gfx10
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_O_V2_V4_gfx11
    UINT64_C(3825811456), UINT64_C(0),	// IMAGE_SAMPLE_O_V2_V4_gfx12
    UINT64_C(4039114754), UINT64_C(0),	// IMAGE_SAMPLE_O_V2_V4_nsa_gfx10
    UINT64_C(4036231169), UINT64_C(0),	// IMAGE_SAMPLE_O_V2_V4_nsa_gfx11
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V3_V2
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V3_V2_gfx10
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_O_V3_V2_gfx11
    UINT64_C(3825811456), UINT64_C(0),	// IMAGE_SAMPLE_O_V3_V2_gfx12
    UINT64_C(4039114754), UINT64_C(0),	// IMAGE_SAMPLE_O_V3_V2_nsa_gfx10
    UINT64_C(4036231169), UINT64_C(0),	// IMAGE_SAMPLE_O_V3_V2_nsa_gfx11
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V3_V3
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V3_V3_gfx10
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_O_V3_V3_gfx11
    UINT64_C(3825811456), UINT64_C(0),	// IMAGE_SAMPLE_O_V3_V3_gfx12
    UINT64_C(4039114754), UINT64_C(0),	// IMAGE_SAMPLE_O_V3_V3_nsa_gfx10
    UINT64_C(4036231169), UINT64_C(0),	// IMAGE_SAMPLE_O_V3_V3_nsa_gfx11
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V3_V4
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V3_V4_gfx10
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_O_V3_V4_gfx11
    UINT64_C(3825811456), UINT64_C(0),	// IMAGE_SAMPLE_O_V3_V4_gfx12
    UINT64_C(4039114754), UINT64_C(0),	// IMAGE_SAMPLE_O_V3_V4_nsa_gfx10
    UINT64_C(4036231169), UINT64_C(0),	// IMAGE_SAMPLE_O_V3_V4_nsa_gfx11
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V4_V2
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V4_V2_gfx10
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_O_V4_V2_gfx11
    UINT64_C(3825811456), UINT64_C(0),	// IMAGE_SAMPLE_O_V4_V2_gfx12
    UINT64_C(4039114754), UINT64_C(0),	// IMAGE_SAMPLE_O_V4_V2_nsa_gfx10
    UINT64_C(4036231169), UINT64_C(0),	// IMAGE_SAMPLE_O_V4_V2_nsa_gfx11
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V4_V3
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V4_V3_gfx10
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_O_V4_V3_gfx11
    UINT64_C(3825811456), UINT64_C(0),	// IMAGE_SAMPLE_O_V4_V3_gfx12
    UINT64_C(4039114754), UINT64_C(0),	// IMAGE_SAMPLE_O_V4_V3_nsa_gfx10
    UINT64_C(4036231169), UINT64_C(0),	// IMAGE_SAMPLE_O_V4_V3_nsa_gfx11
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V4_V4
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V4_V4_gfx10
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_O_V4_V4_gfx11
    UINT64_C(3825811456), UINT64_C(0),	// IMAGE_SAMPLE_O_V4_V4_gfx12
    UINT64_C(4039114754), UINT64_C(0),	// IMAGE_SAMPLE_O_V4_V4_nsa_gfx10
    UINT64_C(4036231169), UINT64_C(0),	// IMAGE_SAMPLE_O_V4_V4_nsa_gfx11
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V5_V2
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V5_V2_gfx10
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_O_V5_V2_gfx11
    UINT64_C(3825811456), UINT64_C(0),	// IMAGE_SAMPLE_O_V5_V2_gfx12
    UINT64_C(4039114754), UINT64_C(0),	// IMAGE_SAMPLE_O_V5_V2_nsa_gfx10
    UINT64_C(4036231169), UINT64_C(0),	// IMAGE_SAMPLE_O_V5_V2_nsa_gfx11
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V5_V3
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V5_V3_gfx10
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_O_V5_V3_gfx11
    UINT64_C(3825811456), UINT64_C(0),	// IMAGE_SAMPLE_O_V5_V3_gfx12
    UINT64_C(4039114754), UINT64_C(0),	// IMAGE_SAMPLE_O_V5_V3_nsa_gfx10
    UINT64_C(4036231169), UINT64_C(0),	// IMAGE_SAMPLE_O_V5_V3_nsa_gfx11
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V5_V4
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_V5_V4_gfx10
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_O_V5_V4_gfx11
    UINT64_C(3825811456), UINT64_C(0),	// IMAGE_SAMPLE_O_V5_V4_gfx12
    UINT64_C(4039114754), UINT64_C(0),	// IMAGE_SAMPLE_O_V5_V4_nsa_gfx10
    UINT64_C(4036231169), UINT64_C(0),	// IMAGE_SAMPLE_O_V5_V4_nsa_gfx11
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_nortn_V2_gfx10
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_O_nortn_V2_gfx11
    UINT64_C(3825811456), UINT64_C(0),	// IMAGE_SAMPLE_O_nortn_V2_gfx12
    UINT64_C(4039114754), UINT64_C(0),	// IMAGE_SAMPLE_O_nortn_V2_nsa_gfx10
    UINT64_C(4036231169), UINT64_C(0),	// IMAGE_SAMPLE_O_nortn_V2_nsa_gfx11
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_nortn_V3_gfx10
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_O_nortn_V3_gfx11
    UINT64_C(3825811456), UINT64_C(0),	// IMAGE_SAMPLE_O_nortn_V3_gfx12
    UINT64_C(4039114754), UINT64_C(0),	// IMAGE_SAMPLE_O_nortn_V3_nsa_gfx10
    UINT64_C(4036231169), UINT64_C(0),	// IMAGE_SAMPLE_O_nortn_V3_nsa_gfx11
    UINT64_C(4039114752), UINT64_C(0),	// IMAGE_SAMPLE_O_nortn_V4_gfx10
    UINT64_C(4036231168), UINT64_C(0),	// IMAGE_SAMPLE_O_nortn_V4_gfx11
    UINT64_C(3825811456), UINT64_C(0),	// IMAGE_SAMPLE_O_nortn_V4_gfx12
    UINT64_C(4039114754), UINT64_C(0),	// IMAGE_SAMPLE_O_nortn_V4_nsa_gfx10
    UINT64_C(4036231169), UINT64_C(0),	// IMAGE_SAMPLE_O_nortn_V4_nsa_gfx11
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V1_V1
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V1_V1_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_V1_V1_gfx11
    UINT64_C(3825647616), UINT64_C(0),	// IMAGE_SAMPLE_V1_V1_gfx12
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V1_V1_gfx90a
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V1_V2
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V1_V2_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_V1_V2_gfx11
    UINT64_C(3825647616), UINT64_C(0),	// IMAGE_SAMPLE_V1_V2_gfx12
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V1_V2_gfx90a
    UINT64_C(4034920450), UINT64_C(0),	// IMAGE_SAMPLE_V1_V2_nsa_gfx10
    UINT64_C(4033609729), UINT64_C(0),	// IMAGE_SAMPLE_V1_V2_nsa_gfx11
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V1_V3
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V1_V3_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_V1_V3_gfx11
    UINT64_C(3825647616), UINT64_C(0),	// IMAGE_SAMPLE_V1_V3_gfx12
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V1_V3_gfx90a
    UINT64_C(4034920450), UINT64_C(0),	// IMAGE_SAMPLE_V1_V3_nsa_gfx10
    UINT64_C(4033609729), UINT64_C(0),	// IMAGE_SAMPLE_V1_V3_nsa_gfx11
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V1_V4
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V1_V4_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_V1_V4_gfx11
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V1_V4_gfx90a
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V2_V1
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V2_V1_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_V2_V1_gfx11
    UINT64_C(3825647616), UINT64_C(0),	// IMAGE_SAMPLE_V2_V1_gfx12
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V2_V1_gfx90a
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V2_V2
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V2_V2_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_V2_V2_gfx11
    UINT64_C(3825647616), UINT64_C(0),	// IMAGE_SAMPLE_V2_V2_gfx12
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V2_V2_gfx90a
    UINT64_C(4034920450), UINT64_C(0),	// IMAGE_SAMPLE_V2_V2_nsa_gfx10
    UINT64_C(4033609729), UINT64_C(0),	// IMAGE_SAMPLE_V2_V2_nsa_gfx11
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V2_V3
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V2_V3_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_V2_V3_gfx11
    UINT64_C(3825647616), UINT64_C(0),	// IMAGE_SAMPLE_V2_V3_gfx12
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V2_V3_gfx90a
    UINT64_C(4034920450), UINT64_C(0),	// IMAGE_SAMPLE_V2_V3_nsa_gfx10
    UINT64_C(4033609729), UINT64_C(0),	// IMAGE_SAMPLE_V2_V3_nsa_gfx11
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V2_V4
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V2_V4_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_V2_V4_gfx11
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V2_V4_gfx90a
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V3_V1
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V3_V1_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_V3_V1_gfx11
    UINT64_C(3825647616), UINT64_C(0),	// IMAGE_SAMPLE_V3_V1_gfx12
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V3_V1_gfx90a
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V3_V2
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V3_V2_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_V3_V2_gfx11
    UINT64_C(3825647616), UINT64_C(0),	// IMAGE_SAMPLE_V3_V2_gfx12
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V3_V2_gfx90a
    UINT64_C(4034920450), UINT64_C(0),	// IMAGE_SAMPLE_V3_V2_nsa_gfx10
    UINT64_C(4033609729), UINT64_C(0),	// IMAGE_SAMPLE_V3_V2_nsa_gfx11
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V3_V3
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V3_V3_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_V3_V3_gfx11
    UINT64_C(3825647616), UINT64_C(0),	// IMAGE_SAMPLE_V3_V3_gfx12
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V3_V3_gfx90a
    UINT64_C(4034920450), UINT64_C(0),	// IMAGE_SAMPLE_V3_V3_nsa_gfx10
    UINT64_C(4033609729), UINT64_C(0),	// IMAGE_SAMPLE_V3_V3_nsa_gfx11
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V3_V4
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V3_V4_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_V3_V4_gfx11
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V3_V4_gfx90a
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V4_V1
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V4_V1_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_V4_V1_gfx11
    UINT64_C(3825647616), UINT64_C(0),	// IMAGE_SAMPLE_V4_V1_gfx12
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V4_V1_gfx90a
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V4_V2
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V4_V2_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_V4_V2_gfx11
    UINT64_C(3825647616), UINT64_C(0),	// IMAGE_SAMPLE_V4_V2_gfx12
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V4_V2_gfx90a
    UINT64_C(4034920450), UINT64_C(0),	// IMAGE_SAMPLE_V4_V2_nsa_gfx10
    UINT64_C(4033609729), UINT64_C(0),	// IMAGE_SAMPLE_V4_V2_nsa_gfx11
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V4_V3
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V4_V3_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_V4_V3_gfx11
    UINT64_C(3825647616), UINT64_C(0),	// IMAGE_SAMPLE_V4_V3_gfx12
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V4_V3_gfx90a
    UINT64_C(4034920450), UINT64_C(0),	// IMAGE_SAMPLE_V4_V3_nsa_gfx10
    UINT64_C(4033609729), UINT64_C(0),	// IMAGE_SAMPLE_V4_V3_nsa_gfx11
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V4_V4
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V4_V4_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_V4_V4_gfx11
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V4_V4_gfx90a
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V5_V1
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V5_V1_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_V5_V1_gfx11
    UINT64_C(3825647616), UINT64_C(0),	// IMAGE_SAMPLE_V5_V1_gfx12
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V5_V1_gfx90a
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V5_V2
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V5_V2_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_V5_V2_gfx11
    UINT64_C(3825647616), UINT64_C(0),	// IMAGE_SAMPLE_V5_V2_gfx12
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V5_V2_gfx90a
    UINT64_C(4034920450), UINT64_C(0),	// IMAGE_SAMPLE_V5_V2_nsa_gfx10
    UINT64_C(4033609729), UINT64_C(0),	// IMAGE_SAMPLE_V5_V2_nsa_gfx11
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V5_V3
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V5_V3_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_V5_V3_gfx11
    UINT64_C(3825647616), UINT64_C(0),	// IMAGE_SAMPLE_V5_V3_gfx12
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V5_V3_gfx90a
    UINT64_C(4034920450), UINT64_C(0),	// IMAGE_SAMPLE_V5_V3_nsa_gfx10
    UINT64_C(4033609729), UINT64_C(0),	// IMAGE_SAMPLE_V5_V3_nsa_gfx11
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V5_V4
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V5_V4_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_V5_V4_gfx11
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_V5_V4_gfx90a
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_nortn_V1_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_nortn_V1_gfx11
    UINT64_C(3825647616), UINT64_C(0),	// IMAGE_SAMPLE_nortn_V1_gfx12
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_nortn_V2_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_nortn_V2_gfx11
    UINT64_C(3825647616), UINT64_C(0),	// IMAGE_SAMPLE_nortn_V2_gfx12
    UINT64_C(4034920450), UINT64_C(0),	// IMAGE_SAMPLE_nortn_V2_nsa_gfx10
    UINT64_C(4033609729), UINT64_C(0),	// IMAGE_SAMPLE_nortn_V2_nsa_gfx11
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_nortn_V3_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_nortn_V3_gfx11
    UINT64_C(3825647616), UINT64_C(0),	// IMAGE_SAMPLE_nortn_V3_gfx12
    UINT64_C(4034920450), UINT64_C(0),	// IMAGE_SAMPLE_nortn_V3_nsa_gfx10
    UINT64_C(4033609729), UINT64_C(0),	// IMAGE_SAMPLE_nortn_V3_nsa_gfx11
    UINT64_C(4034920448), UINT64_C(0),	// IMAGE_SAMPLE_nortn_V4_gfx10
    UINT64_C(4033609728), UINT64_C(0),	// IMAGE_SAMPLE_nortn_V4_gfx11
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V1
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V1_gfx10
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V1_gfx11
    UINT64_C(3489808384), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V1_gfx12
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V1_gfx90a
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V2
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V2_gfx10
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V2_gfx11
    UINT64_C(3489808384), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V2_gfx12
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V2_gfx90a
    UINT64_C(4029415426), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V2_nsa_gfx10
    UINT64_C(4028891137), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V2_nsa_gfx11
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V3
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V3_gfx10
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V3_gfx11
    UINT64_C(3489808384), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V3_gfx12
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V3_gfx90a
    UINT64_C(4029415426), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V3_nsa_gfx10
    UINT64_C(4028891137), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V3_nsa_gfx11
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V4
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V4_gfx10
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V4_gfx11
    UINT64_C(3489808384), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V4_gfx12
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V4_gfx90a
    UINT64_C(4029415426), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V4_nsa_gfx10
    UINT64_C(4028891137), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V1_V4_nsa_gfx11
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V1
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V1_gfx10
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V1_gfx11
    UINT64_C(3489808384), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V1_gfx12
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V1_gfx90a
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V2
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V2_gfx10
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V2_gfx11
    UINT64_C(3489808384), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V2_gfx12
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V2_gfx90a
    UINT64_C(4029415426), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V2_nsa_gfx10
    UINT64_C(4028891137), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V2_nsa_gfx11
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V3
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V3_gfx10
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V3_gfx11
    UINT64_C(3489808384), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V3_gfx12
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V3_gfx90a
    UINT64_C(4029415426), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V3_nsa_gfx10
    UINT64_C(4028891137), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V3_nsa_gfx11
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V4
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V4_gfx10
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V4_gfx11
    UINT64_C(3489808384), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V4_gfx12
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V4_gfx90a
    UINT64_C(4029415426), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V4_nsa_gfx10
    UINT64_C(4028891137), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V2_V4_nsa_gfx11
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V1
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V1_gfx10
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V1_gfx11
    UINT64_C(3489808384), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V1_gfx12
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V1_gfx90a
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V2
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V2_gfx10
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V2_gfx11
    UINT64_C(3489808384), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V2_gfx12
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V2_gfx90a
    UINT64_C(4029415426), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V2_nsa_gfx10
    UINT64_C(4028891137), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V2_nsa_gfx11
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V3
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V3_gfx10
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V3_gfx11
    UINT64_C(3489808384), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V3_gfx12
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V3_gfx90a
    UINT64_C(4029415426), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V3_nsa_gfx10
    UINT64_C(4028891137), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V3_nsa_gfx11
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V4
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V4_gfx10
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V4_gfx11
    UINT64_C(3489808384), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V4_gfx12
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V4_gfx90a
    UINT64_C(4029415426), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V4_nsa_gfx10
    UINT64_C(4028891137), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V3_V4_nsa_gfx11
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V1
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V1_gfx10
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V1_gfx11
    UINT64_C(3489808384), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V1_gfx12
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V1_gfx90a
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V2
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V2_gfx10
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V2_gfx11
    UINT64_C(3489808384), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V2_gfx12
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V2_gfx90a
    UINT64_C(4029415426), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V2_nsa_gfx10
    UINT64_C(4028891137), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V2_nsa_gfx11
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V3
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V3_gfx10
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V3_gfx11
    UINT64_C(3489808384), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V3_gfx12
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V3_gfx90a
    UINT64_C(4029415426), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V3_nsa_gfx10
    UINT64_C(4028891137), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V3_nsa_gfx11
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V4
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V4_gfx10
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V4_gfx11
    UINT64_C(3489808384), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V4_gfx12
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V4_gfx90a
    UINT64_C(4029415426), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V4_nsa_gfx10
    UINT64_C(4028891137), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V4_V4_nsa_gfx11
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V1
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V1_gfx10
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V1_gfx11
    UINT64_C(3489808384), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V1_gfx12
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V1_gfx90a
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V2
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V2_gfx10
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V2_gfx11
    UINT64_C(3489808384), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V2_gfx12
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V2_gfx90a
    UINT64_C(4029415426), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V2_nsa_gfx10
    UINT64_C(4028891137), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V2_nsa_gfx11
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V3
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V3_gfx10
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V3_gfx11
    UINT64_C(3489808384), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V3_gfx12
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V3_gfx90a
    UINT64_C(4029415426), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V3_nsa_gfx10
    UINT64_C(4028891137), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V3_nsa_gfx11
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V4
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V4_gfx10
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V4_gfx11
    UINT64_C(3489808384), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V4_gfx12
    UINT64_C(4029415424), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V4_gfx90a
    UINT64_C(4029415426), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V4_nsa_gfx10
    UINT64_C(4028891137), UINT64_C(0),	// IMAGE_STORE_MIP_PCK_V5_V4_nsa_gfx11
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V1
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V1_gfx10
    UINT64_C(4028366848), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V1_gfx11
    UINT64_C(3489775616), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V1_gfx12
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V1_gfx90a
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V2
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V2_gfx10
    UINT64_C(4028366848), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V2_gfx11
    UINT64_C(3489775616), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V2_gfx12
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V2_gfx90a
    UINT64_C(4028891138), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V2_nsa_gfx10
    UINT64_C(4028366849), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V2_nsa_gfx11
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V3
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V3_gfx10
    UINT64_C(4028366848), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V3_gfx11
    UINT64_C(3489775616), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V3_gfx12
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V3_gfx90a
    UINT64_C(4028891138), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V3_nsa_gfx10
    UINT64_C(4028366849), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V3_nsa_gfx11
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V4
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V4_gfx10
    UINT64_C(4028366848), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V4_gfx11
    UINT64_C(3489775616), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V4_gfx12
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V4_gfx90a
    UINT64_C(4028891138), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V4_nsa_gfx10
    UINT64_C(4028366849), UINT64_C(0),	// IMAGE_STORE_MIP_V1_V4_nsa_gfx11
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V1
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V1_gfx10
    UINT64_C(4028366848), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V1_gfx11
    UINT64_C(3489775616), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V1_gfx12
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V1_gfx90a
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V2
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V2_gfx10
    UINT64_C(4028366848), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V2_gfx11
    UINT64_C(3489775616), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V2_gfx12
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V2_gfx90a
    UINT64_C(4028891138), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V2_nsa_gfx10
    UINT64_C(4028366849), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V2_nsa_gfx11
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V3
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V3_gfx10
    UINT64_C(4028366848), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V3_gfx11
    UINT64_C(3489775616), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V3_gfx12
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V3_gfx90a
    UINT64_C(4028891138), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V3_nsa_gfx10
    UINT64_C(4028366849), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V3_nsa_gfx11
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V4
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V4_gfx10
    UINT64_C(4028366848), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V4_gfx11
    UINT64_C(3489775616), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V4_gfx12
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V4_gfx90a
    UINT64_C(4028891138), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V4_nsa_gfx10
    UINT64_C(4028366849), UINT64_C(0),	// IMAGE_STORE_MIP_V2_V4_nsa_gfx11
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V1
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V1_gfx10
    UINT64_C(4028366848), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V1_gfx11
    UINT64_C(3489775616), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V1_gfx12
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V1_gfx90a
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V2
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V2_gfx10
    UINT64_C(4028366848), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V2_gfx11
    UINT64_C(3489775616), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V2_gfx12
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V2_gfx90a
    UINT64_C(4028891138), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V2_nsa_gfx10
    UINT64_C(4028366849), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V2_nsa_gfx11
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V3
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V3_gfx10
    UINT64_C(4028366848), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V3_gfx11
    UINT64_C(3489775616), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V3_gfx12
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V3_gfx90a
    UINT64_C(4028891138), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V3_nsa_gfx10
    UINT64_C(4028366849), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V3_nsa_gfx11
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V4
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V4_gfx10
    UINT64_C(4028366848), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V4_gfx11
    UINT64_C(3489775616), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V4_gfx12
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V4_gfx90a
    UINT64_C(4028891138), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V4_nsa_gfx10
    UINT64_C(4028366849), UINT64_C(0),	// IMAGE_STORE_MIP_V3_V4_nsa_gfx11
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V1
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V1_gfx10
    UINT64_C(4028366848), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V1_gfx11
    UINT64_C(3489775616), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V1_gfx12
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V1_gfx90a
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V2
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V2_gfx10
    UINT64_C(4028366848), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V2_gfx11
    UINT64_C(3489775616), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V2_gfx12
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V2_gfx90a
    UINT64_C(4028891138), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V2_nsa_gfx10
    UINT64_C(4028366849), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V2_nsa_gfx11
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V3
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V3_gfx10
    UINT64_C(4028366848), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V3_gfx11
    UINT64_C(3489775616), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V3_gfx12
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V3_gfx90a
    UINT64_C(4028891138), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V3_nsa_gfx10
    UINT64_C(4028366849), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V3_nsa_gfx11
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V4
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V4_gfx10
    UINT64_C(4028366848), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V4_gfx11
    UINT64_C(3489775616), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V4_gfx12
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V4_gfx90a
    UINT64_C(4028891138), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V4_nsa_gfx10
    UINT64_C(4028366849), UINT64_C(0),	// IMAGE_STORE_MIP_V4_V4_nsa_gfx11
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V1
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V1_gfx10
    UINT64_C(4028366848), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V1_gfx11
    UINT64_C(3489775616), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V1_gfx12
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V1_gfx90a
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V2
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V2_gfx10
    UINT64_C(4028366848), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V2_gfx11
    UINT64_C(3489775616), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V2_gfx12
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V2_gfx90a
    UINT64_C(4028891138), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V2_nsa_gfx10
    UINT64_C(4028366849), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V2_nsa_gfx11
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V3
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V3_gfx10
    UINT64_C(4028366848), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V3_gfx11
    UINT64_C(3489775616), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V3_gfx12
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V3_gfx90a
    UINT64_C(4028891138), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V3_nsa_gfx10
    UINT64_C(4028366849), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V3_nsa_gfx11
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V4
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V4_gfx10
    UINT64_C(4028366848), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V4_gfx11
    UINT64_C(3489775616), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V4_gfx12
    UINT64_C(4028891136), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V4_gfx90a
    UINT64_C(4028891138), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V4_nsa_gfx10
    UINT64_C(4028366849), UINT64_C(0),	// IMAGE_STORE_MIP_V5_V4_nsa_gfx11
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V1
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V1_gfx10
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V1_gfx11
    UINT64_C(3489792000), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V1_gfx12
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V1_gfx90a
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V2
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V2_gfx10
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V2_gfx11
    UINT64_C(3489792000), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V2_gfx12
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V2_gfx90a
    UINT64_C(4029153282), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V2_nsa_gfx10
    UINT64_C(4028628993), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V2_nsa_gfx11
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V3
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V3_gfx10
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V3_gfx11
    UINT64_C(3489792000), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V3_gfx12
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V3_gfx90a
    UINT64_C(4029153282), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V3_nsa_gfx10
    UINT64_C(4028628993), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V3_nsa_gfx11
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V4
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V4_gfx10
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V4_gfx11
    UINT64_C(3489792000), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V4_gfx12
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V4_gfx90a
    UINT64_C(4029153282), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V4_nsa_gfx10
    UINT64_C(4028628993), UINT64_C(0),	// IMAGE_STORE_PCK_V1_V4_nsa_gfx11
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V1
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V1_gfx10
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V1_gfx11
    UINT64_C(3489792000), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V1_gfx12
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V1_gfx90a
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V2
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V2_gfx10
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V2_gfx11
    UINT64_C(3489792000), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V2_gfx12
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V2_gfx90a
    UINT64_C(4029153282), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V2_nsa_gfx10
    UINT64_C(4028628993), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V2_nsa_gfx11
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V3
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V3_gfx10
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V3_gfx11
    UINT64_C(3489792000), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V3_gfx12
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V3_gfx90a
    UINT64_C(4029153282), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V3_nsa_gfx10
    UINT64_C(4028628993), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V3_nsa_gfx11
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V4
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V4_gfx10
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V4_gfx11
    UINT64_C(3489792000), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V4_gfx12
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V4_gfx90a
    UINT64_C(4029153282), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V4_nsa_gfx10
    UINT64_C(4028628993), UINT64_C(0),	// IMAGE_STORE_PCK_V2_V4_nsa_gfx11
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V1
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V1_gfx10
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V1_gfx11
    UINT64_C(3489792000), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V1_gfx12
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V1_gfx90a
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V2
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V2_gfx10
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V2_gfx11
    UINT64_C(3489792000), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V2_gfx12
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V2_gfx90a
    UINT64_C(4029153282), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V2_nsa_gfx10
    UINT64_C(4028628993), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V2_nsa_gfx11
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V3
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V3_gfx10
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V3_gfx11
    UINT64_C(3489792000), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V3_gfx12
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V3_gfx90a
    UINT64_C(4029153282), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V3_nsa_gfx10
    UINT64_C(4028628993), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V3_nsa_gfx11
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V4
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V4_gfx10
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V4_gfx11
    UINT64_C(3489792000), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V4_gfx12
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V4_gfx90a
    UINT64_C(4029153282), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V4_nsa_gfx10
    UINT64_C(4028628993), UINT64_C(0),	// IMAGE_STORE_PCK_V3_V4_nsa_gfx11
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V1
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V1_gfx10
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V1_gfx11
    UINT64_C(3489792000), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V1_gfx12
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V1_gfx90a
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V2
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V2_gfx10
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V2_gfx11
    UINT64_C(3489792000), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V2_gfx12
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V2_gfx90a
    UINT64_C(4029153282), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V2_nsa_gfx10
    UINT64_C(4028628993), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V2_nsa_gfx11
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V3
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V3_gfx10
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V3_gfx11
    UINT64_C(3489792000), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V3_gfx12
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V3_gfx90a
    UINT64_C(4029153282), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V3_nsa_gfx10
    UINT64_C(4028628993), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V3_nsa_gfx11
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V4
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V4_gfx10
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V4_gfx11
    UINT64_C(3489792000), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V4_gfx12
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V4_gfx90a
    UINT64_C(4029153282), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V4_nsa_gfx10
    UINT64_C(4028628993), UINT64_C(0),	// IMAGE_STORE_PCK_V4_V4_nsa_gfx11
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V1
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V1_gfx10
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V1_gfx11
    UINT64_C(3489792000), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V1_gfx12
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V1_gfx90a
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V2
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V2_gfx10
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V2_gfx11
    UINT64_C(3489792000), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V2_gfx12
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V2_gfx90a
    UINT64_C(4029153282), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V2_nsa_gfx10
    UINT64_C(4028628993), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V2_nsa_gfx11
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V3
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V3_gfx10
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V3_gfx11
    UINT64_C(3489792000), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V3_gfx12
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V3_gfx90a
    UINT64_C(4029153282), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V3_nsa_gfx10
    UINT64_C(4028628993), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V3_nsa_gfx11
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V4
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V4_gfx10
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V4_gfx11
    UINT64_C(3489792000), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V4_gfx12
    UINT64_C(4029153280), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V4_gfx90a
    UINT64_C(4029153282), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V4_nsa_gfx10
    UINT64_C(4028628993), UINT64_C(0),	// IMAGE_STORE_PCK_V5_V4_nsa_gfx11
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V1_V1
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V1_V1_gfx10
    UINT64_C(4028104704), UINT64_C(0),	// IMAGE_STORE_V1_V1_gfx11
    UINT64_C(3489759232), UINT64_C(0),	// IMAGE_STORE_V1_V1_gfx12
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V1_V1_gfx90a
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V1_V2
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V1_V2_gfx10
    UINT64_C(4028104704), UINT64_C(0),	// IMAGE_STORE_V1_V2_gfx11
    UINT64_C(3489759232), UINT64_C(0),	// IMAGE_STORE_V1_V2_gfx12
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V1_V2_gfx90a
    UINT64_C(4028628994), UINT64_C(0),	// IMAGE_STORE_V1_V2_nsa_gfx10
    UINT64_C(4028104705), UINT64_C(0),	// IMAGE_STORE_V1_V2_nsa_gfx11
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V1_V3
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V1_V3_gfx10
    UINT64_C(4028104704), UINT64_C(0),	// IMAGE_STORE_V1_V3_gfx11
    UINT64_C(3489759232), UINT64_C(0),	// IMAGE_STORE_V1_V3_gfx12
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V1_V3_gfx90a
    UINT64_C(4028628994), UINT64_C(0),	// IMAGE_STORE_V1_V3_nsa_gfx10
    UINT64_C(4028104705), UINT64_C(0),	// IMAGE_STORE_V1_V3_nsa_gfx11
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V1_V4
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V1_V4_gfx10
    UINT64_C(4028104704), UINT64_C(0),	// IMAGE_STORE_V1_V4_gfx11
    UINT64_C(3489759232), UINT64_C(0),	// IMAGE_STORE_V1_V4_gfx12
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V1_V4_gfx90a
    UINT64_C(4028628994), UINT64_C(0),	// IMAGE_STORE_V1_V4_nsa_gfx10
    UINT64_C(4028104705), UINT64_C(0),	// IMAGE_STORE_V1_V4_nsa_gfx11
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V2_V1
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V2_V1_gfx10
    UINT64_C(4028104704), UINT64_C(0),	// IMAGE_STORE_V2_V1_gfx11
    UINT64_C(3489759232), UINT64_C(0),	// IMAGE_STORE_V2_V1_gfx12
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V2_V1_gfx90a
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V2_V2
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V2_V2_gfx10
    UINT64_C(4028104704), UINT64_C(0),	// IMAGE_STORE_V2_V2_gfx11
    UINT64_C(3489759232), UINT64_C(0),	// IMAGE_STORE_V2_V2_gfx12
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V2_V2_gfx90a
    UINT64_C(4028628994), UINT64_C(0),	// IMAGE_STORE_V2_V2_nsa_gfx10
    UINT64_C(4028104705), UINT64_C(0),	// IMAGE_STORE_V2_V2_nsa_gfx11
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V2_V3
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V2_V3_gfx10
    UINT64_C(4028104704), UINT64_C(0),	// IMAGE_STORE_V2_V3_gfx11
    UINT64_C(3489759232), UINT64_C(0),	// IMAGE_STORE_V2_V3_gfx12
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V2_V3_gfx90a
    UINT64_C(4028628994), UINT64_C(0),	// IMAGE_STORE_V2_V3_nsa_gfx10
    UINT64_C(4028104705), UINT64_C(0),	// IMAGE_STORE_V2_V3_nsa_gfx11
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V2_V4
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V2_V4_gfx10
    UINT64_C(4028104704), UINT64_C(0),	// IMAGE_STORE_V2_V4_gfx11
    UINT64_C(3489759232), UINT64_C(0),	// IMAGE_STORE_V2_V4_gfx12
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V2_V4_gfx90a
    UINT64_C(4028628994), UINT64_C(0),	// IMAGE_STORE_V2_V4_nsa_gfx10
    UINT64_C(4028104705), UINT64_C(0),	// IMAGE_STORE_V2_V4_nsa_gfx11
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V3_V1
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V3_V1_gfx10
    UINT64_C(4028104704), UINT64_C(0),	// IMAGE_STORE_V3_V1_gfx11
    UINT64_C(3489759232), UINT64_C(0),	// IMAGE_STORE_V3_V1_gfx12
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V3_V1_gfx90a
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V3_V2
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V3_V2_gfx10
    UINT64_C(4028104704), UINT64_C(0),	// IMAGE_STORE_V3_V2_gfx11
    UINT64_C(3489759232), UINT64_C(0),	// IMAGE_STORE_V3_V2_gfx12
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V3_V2_gfx90a
    UINT64_C(4028628994), UINT64_C(0),	// IMAGE_STORE_V3_V2_nsa_gfx10
    UINT64_C(4028104705), UINT64_C(0),	// IMAGE_STORE_V3_V2_nsa_gfx11
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V3_V3
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V3_V3_gfx10
    UINT64_C(4028104704), UINT64_C(0),	// IMAGE_STORE_V3_V3_gfx11
    UINT64_C(3489759232), UINT64_C(0),	// IMAGE_STORE_V3_V3_gfx12
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V3_V3_gfx90a
    UINT64_C(4028628994), UINT64_C(0),	// IMAGE_STORE_V3_V3_nsa_gfx10
    UINT64_C(4028104705), UINT64_C(0),	// IMAGE_STORE_V3_V3_nsa_gfx11
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V3_V4
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V3_V4_gfx10
    UINT64_C(4028104704), UINT64_C(0),	// IMAGE_STORE_V3_V4_gfx11
    UINT64_C(3489759232), UINT64_C(0),	// IMAGE_STORE_V3_V4_gfx12
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V3_V4_gfx90a
    UINT64_C(4028628994), UINT64_C(0),	// IMAGE_STORE_V3_V4_nsa_gfx10
    UINT64_C(4028104705), UINT64_C(0),	// IMAGE_STORE_V3_V4_nsa_gfx11
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V4_V1
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V4_V1_gfx10
    UINT64_C(4028104704), UINT64_C(0),	// IMAGE_STORE_V4_V1_gfx11
    UINT64_C(3489759232), UINT64_C(0),	// IMAGE_STORE_V4_V1_gfx12
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V4_V1_gfx90a
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V4_V2
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V4_V2_gfx10
    UINT64_C(4028104704), UINT64_C(0),	// IMAGE_STORE_V4_V2_gfx11
    UINT64_C(3489759232), UINT64_C(0),	// IMAGE_STORE_V4_V2_gfx12
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V4_V2_gfx90a
    UINT64_C(4028628994), UINT64_C(0),	// IMAGE_STORE_V4_V2_nsa_gfx10
    UINT64_C(4028104705), UINT64_C(0),	// IMAGE_STORE_V4_V2_nsa_gfx11
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V4_V3
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V4_V3_gfx10
    UINT64_C(4028104704), UINT64_C(0),	// IMAGE_STORE_V4_V3_gfx11
    UINT64_C(3489759232), UINT64_C(0),	// IMAGE_STORE_V4_V3_gfx12
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V4_V3_gfx90a
    UINT64_C(4028628994), UINT64_C(0),	// IMAGE_STORE_V4_V3_nsa_gfx10
    UINT64_C(4028104705), UINT64_C(0),	// IMAGE_STORE_V4_V3_nsa_gfx11
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V4_V4
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V4_V4_gfx10
    UINT64_C(4028104704), UINT64_C(0),	// IMAGE_STORE_V4_V4_gfx11
    UINT64_C(3489759232), UINT64_C(0),	// IMAGE_STORE_V4_V4_gfx12
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V4_V4_gfx90a
    UINT64_C(4028628994), UINT64_C(0),	// IMAGE_STORE_V4_V4_nsa_gfx10
    UINT64_C(4028104705), UINT64_C(0),	// IMAGE_STORE_V4_V4_nsa_gfx11
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V5_V1
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V5_V1_gfx10
    UINT64_C(4028104704), UINT64_C(0),	// IMAGE_STORE_V5_V1_gfx11
    UINT64_C(3489759232), UINT64_C(0),	// IMAGE_STORE_V5_V1_gfx12
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V5_V1_gfx90a
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V5_V2
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V5_V2_gfx10
    UINT64_C(4028104704), UINT64_C(0),	// IMAGE_STORE_V5_V2_gfx11
    UINT64_C(3489759232), UINT64_C(0),	// IMAGE_STORE_V5_V2_gfx12
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V5_V2_gfx90a
    UINT64_C(4028628994), UINT64_C(0),	// IMAGE_STORE_V5_V2_nsa_gfx10
    UINT64_C(4028104705), UINT64_C(0),	// IMAGE_STORE_V5_V2_nsa_gfx11
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V5_V3
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V5_V3_gfx10
    UINT64_C(4028104704), UINT64_C(0),	// IMAGE_STORE_V5_V3_gfx11
    UINT64_C(3489759232), UINT64_C(0),	// IMAGE_STORE_V5_V3_gfx12
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V5_V3_gfx90a
    UINT64_C(4028628994), UINT64_C(0),	// IMAGE_STORE_V5_V3_nsa_gfx10
    UINT64_C(4028104705), UINT64_C(0),	// IMAGE_STORE_V5_V3_nsa_gfx11
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V5_V4
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V5_V4_gfx10
    UINT64_C(4028104704), UINT64_C(0),	// IMAGE_STORE_V5_V4_gfx11
    UINT64_C(3489759232), UINT64_C(0),	// IMAGE_STORE_V5_V4_gfx12
    UINT64_C(4028628992), UINT64_C(0),	// IMAGE_STORE_V5_V4_gfx90a
    UINT64_C(4028628994), UINT64_C(0),	// IMAGE_STORE_V5_V4_nsa_gfx10
    UINT64_C(4028104705), UINT64_C(0),	// IMAGE_STORE_V5_V4_nsa_gfx11
    UINT64_C(3457155072), UINT64_C(0),	// LDS_DIRECT_LOAD_gfx11
    UINT64_C(3456106496), UINT64_C(0),	// LDS_PARAM_LOAD_gfx11
    UINT64_C(3977560064), UINT64_C(0),	// SCRATCH_LOAD_BLOCK_SADDR_gfx12
    UINT64_C(3977560188), UINT64_C(0),	// SCRATCH_LOAD_BLOCK_ST_gfx12
    UINT64_C(562953930981376), UINT64_C(0),	// SCRATCH_LOAD_BLOCK_SVS_gfx12
    UINT64_C(562953930981500), UINT64_C(0),	// SCRATCH_LOAD_BLOCK_gfx12
    UINT64_C(3694411776), UINT64_C(0),	// SCRATCH_LOAD_DWORDX2_SADDR_gfx10
    UINT64_C(3696558080), UINT64_C(0),	// SCRATCH_LOAD_DWORDX2_SADDR_gfx11
    UINT64_C(3976544256), UINT64_C(0),	// SCRATCH_LOAD_DWORDX2_SADDR_gfx12
    UINT64_C(3696508928), UINT64_C(0),	// SCRATCH_LOAD_DWORDX2_SADDR_vi
    UINT64_C(35747325736665088), UINT64_C(0),	// SCRATCH_LOAD_DWORDX2_ST_gfx10
    UINT64_C(34902900808679424), UINT64_C(0),	// SCRATCH_LOAD_DWORDX2_ST_gfx11
    UINT64_C(3976544380), UINT64_C(0),	// SCRATCH_LOAD_DWORDX2_ST_gfx12
    UINT64_C(35747325738762240), UINT64_C(0),	// SCRATCH_LOAD_DWORDX2_ST_gfx940
    UINT64_C(36028800715522048), UINT64_C(0),	// SCRATCH_LOAD_DWORDX2_SVS_gfx11
    UINT64_C(562953929965568), UINT64_C(0),	// SCRATCH_LOAD_DWORDX2_SVS_gfx12
    UINT64_C(3696517120), UINT64_C(0),	// SCRATCH_LOAD_DWORDX2_SVS_gfx940
    UINT64_C(35747325738770432), UINT64_C(0),	// SCRATCH_LOAD_DWORDX2_VE_gfx940
    UINT64_C(35184375783243776), UINT64_C(0),	// SCRATCH_LOAD_DWORDX2_gfx10
    UINT64_C(70931697827643392), UINT64_C(0),	// SCRATCH_LOAD_DWORDX2_gfx11
    UINT64_C(562953929965692), UINT64_C(0),	// SCRATCH_LOAD_DWORDX2_gfx12
    UINT64_C(35747325738762240), UINT64_C(0),	// SCRATCH_LOAD_DWORDX2_vi
    UINT64_C(3694936064), UINT64_C(0),	// SCRATCH_LOAD_DWORDX3_SADDR_gfx10
    UINT64_C(3696820224), UINT64_C(0),	// SCRATCH_LOAD_DWORDX3_SADDR_gfx11
    UINT64_C(3976560640), UINT64_C(0),	// SCRATCH_LOAD_DWORDX3_SADDR_gfx12
    UINT64_C(3696771072), UINT64_C(0),	// SCRATCH_LOAD_DWORDX3_SADDR_vi
    UINT64_C(35747325737189376), UINT64_C(0),	// SCRATCH_LOAD_DWORDX3_ST_gfx10
    UINT64_C(34902900808941568), UINT64_C(0),	// SCRATCH_LOAD_DWORDX3_ST_gfx11
    UINT64_C(3976560764), UINT64_C(0),	// SCRATCH_LOAD_DWORDX3_ST_gfx12
    UINT64_C(35747325739024384), UINT64_C(0),	// SCRATCH_LOAD_DWORDX3_ST_gfx940
    UINT64_C(36028800715784192), UINT64_C(0),	// SCRATCH_LOAD_DWORDX3_SVS_gfx11
    UINT64_C(562953929981952), UINT64_C(0),	// SCRATCH_LOAD_DWORDX3_SVS_gfx12
    UINT64_C(3696779264), UINT64_C(0),	// SCRATCH_LOAD_DWORDX3_SVS_gfx940
    UINT64_C(35747325739032576), UINT64_C(0),	// SCRATCH_LOAD_DWORDX3_VE_gfx940
    UINT64_C(35184375783768064), UINT64_C(0),	// SCRATCH_LOAD_DWORDX3_gfx10
    UINT64_C(70931697827905536), UINT64_C(0),	// SCRATCH_LOAD_DWORDX3_gfx11
    UINT64_C(562953929982076), UINT64_C(0),	// SCRATCH_LOAD_DWORDX3_gfx12
    UINT64_C(35747325739024384), UINT64_C(0),	// SCRATCH_LOAD_DWORDX3_vi
    UINT64_C(3694673920), UINT64_C(0),	// SCRATCH_LOAD_DWORDX4_SADDR_gfx10
    UINT64_C(3697082368), UINT64_C(0),	// SCRATCH_LOAD_DWORDX4_SADDR_gfx11
    UINT64_C(3976577024), UINT64_C(0),	// SCRATCH_LOAD_DWORDX4_SADDR_gfx12
    UINT64_C(3697033216), UINT64_C(0),	// SCRATCH_LOAD_DWORDX4_SADDR_vi
    UINT64_C(35747325736927232), UINT64_C(0),	// SCRATCH_LOAD_DWORDX4_ST_gfx10
    UINT64_C(34902900809203712), UINT64_C(0),	// SCRATCH_LOAD_DWORDX4_ST_gfx11
    UINT64_C(3976577148), UINT64_C(0),	// SCRATCH_LOAD_DWORDX4_ST_gfx12
    UINT64_C(35747325739286528), UINT64_C(0),	// SCRATCH_LOAD_DWORDX4_ST_gfx940
    UINT64_C(36028800716046336), UINT64_C(0),	// SCRATCH_LOAD_DWORDX4_SVS_gfx11
    UINT64_C(562953929998336), UINT64_C(0),	// SCRATCH_LOAD_DWORDX4_SVS_gfx12
    UINT64_C(3697041408), UINT64_C(0),	// SCRATCH_LOAD_DWORDX4_SVS_gfx940
    UINT64_C(35747325739294720), UINT64_C(0),	// SCRATCH_LOAD_DWORDX4_VE_gfx940
    UINT64_C(35184375783505920), UINT64_C(0),	// SCRATCH_LOAD_DWORDX4_gfx10
    UINT64_C(70931697828167680), UINT64_C(0),	// SCRATCH_LOAD_DWORDX4_gfx11
    UINT64_C(562953929998460), UINT64_C(0),	// SCRATCH_LOAD_DWORDX4_gfx12
    UINT64_C(35747325739286528), UINT64_C(0),	// SCRATCH_LOAD_DWORDX4_vi
    UINT64_C(3694149632), UINT64_C(0),	// SCRATCH_LOAD_DWORD_SADDR_gfx10
    UINT64_C(3696295936), UINT64_C(0),	// SCRATCH_LOAD_DWORD_SADDR_gfx11
    UINT64_C(3976527872), UINT64_C(0),	// SCRATCH_LOAD_DWORD_SADDR_gfx12
    UINT64_C(3696246784), UINT64_C(0),	// SCRATCH_LOAD_DWORD_SADDR_vi
    UINT64_C(35747325736402944), UINT64_C(0),	// SCRATCH_LOAD_DWORD_ST_gfx10
    UINT64_C(34902900808417280), UINT64_C(0),	// SCRATCH_LOAD_DWORD_ST_gfx11
    UINT64_C(3976527996), UINT64_C(0),	// SCRATCH_LOAD_DWORD_ST_gfx12
    UINT64_C(35747325738500096), UINT64_C(0),	// SCRATCH_LOAD_DWORD_ST_gfx940
    UINT64_C(36028800715259904), UINT64_C(0),	// SCRATCH_LOAD_DWORD_SVS_gfx11
    UINT64_C(562953929949184), UINT64_C(0),	// SCRATCH_LOAD_DWORD_SVS_gfx12
    UINT64_C(3696254976), UINT64_C(0),	// SCRATCH_LOAD_DWORD_SVS_gfx940
    UINT64_C(35747325738508288), UINT64_C(0),	// SCRATCH_LOAD_DWORD_VE_gfx940
    UINT64_C(35184375782981632), UINT64_C(0),	// SCRATCH_LOAD_DWORD_gfx10
    UINT64_C(70931697827381248), UINT64_C(0),	// SCRATCH_LOAD_DWORD_gfx11
    UINT64_C(562953929949308), UINT64_C(0),	// SCRATCH_LOAD_DWORD_gfx12
    UINT64_C(35747325738500096), UINT64_C(0),	// SCRATCH_LOAD_DWORD_vi
    UINT64_C(3694157824), UINT64_C(0),	// SCRATCH_LOAD_LDS_DWORD_SADDR_gfx10
    UINT64_C(3702013952), UINT64_C(0),	// SCRATCH_LOAD_LDS_DWORD_SADDR_gfx940
    UINT64_C(3696254976), UINT64_C(0),	// SCRATCH_LOAD_LDS_DWORD_SADDR_vi
    UINT64_C(35747325736411136), UINT64_C(0),	// SCRATCH_LOAD_LDS_DWORD_ST_gfx10
    UINT64_C(35747325744267264), UINT64_C(0),	// SCRATCH_LOAD_LDS_DWORD_ST_gfx940
    UINT64_C(3702022144), UINT64_C(0),	// SCRATCH_LOAD_LDS_DWORD_SVS_gfx940
    UINT64_C(35184375782989824), UINT64_C(0),	// SCRATCH_LOAD_LDS_DWORD_gfx10
    UINT64_C(35747325744275456), UINT64_C(0),	// SCRATCH_LOAD_LDS_DWORD_gfx940
    UINT64_C(35747325738508288), UINT64_C(0),	// SCRATCH_LOAD_LDS_DWORD_vi
    UINT64_C(3693371392), UINT64_C(0),	// SCRATCH_LOAD_LDS_SBYTE_SADDR_gfx10
    UINT64_C(3701227520), UINT64_C(0),	// SCRATCH_LOAD_LDS_SBYTE_SADDR_gfx940
    UINT64_C(3695468544), UINT64_C(0),	// SCRATCH_LOAD_LDS_SBYTE_SADDR_vi
    UINT64_C(35747325735624704), UINT64_C(0),	// SCRATCH_LOAD_LDS_SBYTE_ST_gfx10
    UINT64_C(35747325743480832), UINT64_C(0),	// SCRATCH_LOAD_LDS_SBYTE_ST_gfx940
    UINT64_C(3701235712), UINT64_C(0),	// SCRATCH_LOAD_LDS_SBYTE_SVS_gfx940
    UINT64_C(35184375782203392), UINT64_C(0),	// SCRATCH_LOAD_LDS_SBYTE_gfx10
    UINT64_C(35747325743489024), UINT64_C(0),	// SCRATCH_LOAD_LDS_SBYTE_gfx940
    UINT64_C(35747325737721856), UINT64_C(0),	// SCRATCH_LOAD_LDS_SBYTE_vi
    UINT64_C(3693895680), UINT64_C(0),	// SCRATCH_LOAD_LDS_SSHORT_SADDR_gfx10
    UINT64_C(3701751808), UINT64_C(0),	// SCRATCH_LOAD_LDS_SSHORT_SADDR_gfx940
    UINT64_C(3695992832), UINT64_C(0),	// SCRATCH_LOAD_LDS_SSHORT_SADDR_vi
    UINT64_C(35747325736148992), UINT64_C(0),	// SCRATCH_LOAD_LDS_SSHORT_ST_gfx10
    UINT64_C(35747325744005120), UINT64_C(0),	// SCRATCH_LOAD_LDS_SSHORT_ST_gfx940
    UINT64_C(3701760000), UINT64_C(0),	// SCRATCH_LOAD_LDS_SSHORT_SVS_gfx940
    UINT64_C(35184375782727680), UINT64_C(0),	// SCRATCH_LOAD_LDS_SSHORT_gfx10
    UINT64_C(35747325744013312), UINT64_C(0),	// SCRATCH_LOAD_LDS_SSHORT_gfx940
    UINT64_C(35747325738246144), UINT64_C(0),	// SCRATCH_LOAD_LDS_SSHORT_vi
    UINT64_C(3693109248), UINT64_C(0),	// SCRATCH_LOAD_LDS_UBYTE_SADDR_gfx10
    UINT64_C(3700965376), UINT64_C(0),	// SCRATCH_LOAD_LDS_UBYTE_SADDR_gfx940
    UINT64_C(3695206400), UINT64_C(0),	// SCRATCH_LOAD_LDS_UBYTE_SADDR_vi
    UINT64_C(35747325735362560), UINT64_C(0),	// SCRATCH_LOAD_LDS_UBYTE_ST_gfx10
    UINT64_C(35747325743218688), UINT64_C(0),	// SCRATCH_LOAD_LDS_UBYTE_ST_gfx940
    UINT64_C(3700973568), UINT64_C(0),	// SCRATCH_LOAD_LDS_UBYTE_SVS_gfx940
    UINT64_C(35184375781941248), UINT64_C(0),	// SCRATCH_LOAD_LDS_UBYTE_gfx10
    UINT64_C(35747325743226880), UINT64_C(0),	// SCRATCH_LOAD_LDS_UBYTE_gfx940
    UINT64_C(35747325737459712), UINT64_C(0),	// SCRATCH_LOAD_LDS_UBYTE_vi
    UINT64_C(3693633536), UINT64_C(0),	// SCRATCH_LOAD_LDS_USHORT_SADDR_gfx10
    UINT64_C(3701489664), UINT64_C(0),	// SCRATCH_LOAD_LDS_USHORT_SADDR_gfx940
    UINT64_C(3695730688), UINT64_C(0),	// SCRATCH_LOAD_LDS_USHORT_SADDR_vi
    UINT64_C(35747325735886848), UINT64_C(0),	// SCRATCH_LOAD_LDS_USHORT_ST_gfx10
    UINT64_C(35747325743742976), UINT64_C(0),	// SCRATCH_LOAD_LDS_USHORT_ST_gfx940
    UINT64_C(3701497856), UINT64_C(0),	// SCRATCH_LOAD_LDS_USHORT_SVS_gfx940
    UINT64_C(35184375782465536), UINT64_C(0),	// SCRATCH_LOAD_LDS_USHORT_gfx10
    UINT64_C(35747325743751168), UINT64_C(0),	// SCRATCH_LOAD_LDS_USHORT_gfx940
    UINT64_C(35747325737984000), UINT64_C(0),	// SCRATCH_LOAD_LDS_USHORT_vi
    UINT64_C(3700178944), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_HI_SADDR_gfx10
    UINT64_C(3699965952), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_HI_SADDR_gfx11
    UINT64_C(3976757248), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_HI_SADDR_gfx12
    UINT64_C(3700178944), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_HI_SADDR_vi
    UINT64_C(35747325742432256), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_HI_ST_gfx10
    UINT64_C(34902900812087296), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_HI_ST_gfx11
    UINT64_C(3976757372), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_HI_ST_gfx12
    UINT64_C(35747325742432256), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_HI_ST_gfx940
    UINT64_C(36028800718929920), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_HI_SVS_gfx11
    UINT64_C(562953930178560), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_HI_SVS_gfx12
    UINT64_C(3700187136), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_HI_SVS_gfx940
    UINT64_C(35747325742440448), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_HI_VE_gfx940
    UINT64_C(35184375789010944), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_HI_gfx10
    UINT64_C(70931697831051264), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_HI_gfx11
    UINT64_C(562953930178684), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_HI_gfx12
    UINT64_C(35747325742432256), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_HI_vi
    UINT64_C(3699916800), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_SADDR_gfx10
    UINT64_C(3699179520), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_SADDR_gfx11
    UINT64_C(3976708096), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_SADDR_gfx12
    UINT64_C(3699916800), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_SADDR_vi
    UINT64_C(35747325742170112), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_ST_gfx10
    UINT64_C(34902900811300864), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_ST_gfx11
    UINT64_C(3976708220), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_ST_gfx12
    UINT64_C(35747325742170112), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_ST_gfx940
    UINT64_C(36028800718143488), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_SVS_gfx11
    UINT64_C(562953930129408), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_SVS_gfx12
    UINT64_C(3699924992), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_SVS_gfx940
    UINT64_C(35747325742178304), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_VE_gfx940
    UINT64_C(35184375788748800), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_gfx10
    UINT64_C(70931697830264832), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_gfx11
    UINT64_C(562953930129532), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_gfx12
    UINT64_C(35747325742170112), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_D16_vi
    UINT64_C(3693363200), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_SADDR_gfx10
    UINT64_C(3695509504), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_SADDR_gfx11
    UINT64_C(3976478720), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_SADDR_gfx12
    UINT64_C(3695460352), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_SADDR_vi
    UINT64_C(35747325735616512), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_ST_gfx10
    UINT64_C(34902900807630848), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_ST_gfx11
    UINT64_C(3976478844), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_ST_gfx12
    UINT64_C(35747325737713664), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_ST_gfx940
    UINT64_C(36028800714473472), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_SVS_gfx11
    UINT64_C(562953929900032), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_SVS_gfx12
    UINT64_C(3695468544), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_SVS_gfx940
    UINT64_C(35747325737721856), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_VE_gfx940
    UINT64_C(35184375782195200), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_gfx10
    UINT64_C(70931697826594816), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_gfx11
    UINT64_C(562953929900156), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_gfx12
    UINT64_C(35747325737713664), UINT64_C(0),	// SCRATCH_LOAD_SBYTE_vi
    UINT64_C(3700703232), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_HI_SADDR_gfx10
    UINT64_C(3700228096), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_HI_SADDR_gfx11
    UINT64_C(3976773632), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_HI_SADDR_gfx12
    UINT64_C(3700703232), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_HI_SADDR_vi
    UINT64_C(35747325742956544), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_HI_ST_gfx10
    UINT64_C(34902900812349440), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_HI_ST_gfx11
    UINT64_C(3976773756), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_HI_ST_gfx12
    UINT64_C(35747325742956544), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_HI_ST_gfx940
    UINT64_C(36028800719192064), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_HI_SVS_gfx11
    UINT64_C(562953930194944), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_HI_SVS_gfx12
    UINT64_C(3700711424), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_HI_SVS_gfx940
    UINT64_C(35747325742964736), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_HI_VE_gfx940
    UINT64_C(35184375789535232), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_HI_gfx10
    UINT64_C(70931697831313408), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_HI_gfx11
    UINT64_C(562953930195068), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_HI_gfx12
    UINT64_C(35747325742956544), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_HI_vi
    UINT64_C(3700441088), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_SADDR_gfx10
    UINT64_C(3699441664), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_SADDR_gfx11
    UINT64_C(3976724480), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_SADDR_gfx12
    UINT64_C(3700441088), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_SADDR_vi
    UINT64_C(35747325742694400), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_ST_gfx10
    UINT64_C(34902900811563008), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_ST_gfx11
    UINT64_C(3976724604), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_ST_gfx12
    UINT64_C(35747325742694400), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_ST_gfx940
    UINT64_C(36028800718405632), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_SVS_gfx11
    UINT64_C(562953930145792), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_SVS_gfx12
    UINT64_C(3700449280), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_SVS_gfx940
    UINT64_C(35747325742702592), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_VE_gfx940
    UINT64_C(35184375789273088), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_gfx10
    UINT64_C(70931697830526976), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_gfx11
    UINT64_C(562953930145916), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_gfx12
    UINT64_C(35747325742694400), UINT64_C(0),	// SCRATCH_LOAD_SHORT_D16_vi
    UINT64_C(3693887488), UINT64_C(0),	// SCRATCH_LOAD_SSHORT_SADDR_gfx10
    UINT64_C(3696033792), UINT64_C(0),	// SCRATCH_LOAD_SSHORT_SADDR_gfx11
    UINT64_C(3976511488), UINT64_C(0),	// SCRATCH_LOAD_SSHORT_SADDR_gfx12
    UINT64_C(3695984640), UINT64_C(0),	// SCRATCH_LOAD_SSHORT_SADDR_vi
    UINT64_C(35747325736140800), UINT64_C(0),	// SCRATCH_LOAD_SSHORT_ST_gfx10
    UINT64_C(34902900808155136), UINT64_C(0),	// SCRATCH_LOAD_SSHORT_ST_gfx11
    UINT64_C(3976511612), UINT64_C(0),	// SCRATCH_LOAD_SSHORT_ST_gfx12
    UINT64_C(35747325738237952), UINT64_C(0),	// SCRATCH_LOAD_SSHORT_ST_gfx940
    UINT64_C(36028800714997760), UINT64_C(0),	// SCRATCH_LOAD_SSHORT_SVS_gfx11
    UINT64_C(562953929932800), UINT64_C(0),	// SCRATCH_LOAD_SSHORT_SVS_gfx12
    UINT64_C(3695992832), UINT64_C(0),	// SCRATCH_LOAD_SSHORT_SVS_gfx940
    UINT64_C(35747325738246144), UINT64_C(0),	// SCRATCH_LOAD_SSHORT_VE_gfx940
    UINT64_C(35184375782719488), UINT64_C(0),	// SCRATCH_LOAD_SSHORT_gfx10
    UINT64_C(70931697827119104), UINT64_C(0),	// SCRATCH_LOAD_SSHORT_gfx11
    UINT64_C(562953929932924), UINT64_C(0),	// SCRATCH_LOAD_SSHORT_gfx12
    UINT64_C(35747325738237952), UINT64_C(0),	// SCRATCH_LOAD_SSHORT_vi
    UINT64_C(3699654656), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_HI_SADDR_gfx10
    UINT64_C(3699703808), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_HI_SADDR_gfx11
    UINT64_C(3976740864), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_HI_SADDR_gfx12
    UINT64_C(3699654656), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_HI_SADDR_vi
    UINT64_C(35747325741907968), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_HI_ST_gfx10
    UINT64_C(34902900811825152), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_HI_ST_gfx11
    UINT64_C(3976740988), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_HI_ST_gfx12
    UINT64_C(35747325741907968), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_HI_ST_gfx940
    UINT64_C(36028800718667776), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_HI_SVS_gfx11
    UINT64_C(562953930162176), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_HI_SVS_gfx12
    UINT64_C(3699662848), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_HI_SVS_gfx940
    UINT64_C(35747325741916160), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_HI_VE_gfx940
    UINT64_C(35184375788486656), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_HI_gfx10
    UINT64_C(70931697830789120), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_HI_gfx11
    UINT64_C(562953930162300), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_HI_gfx12
    UINT64_C(35747325741907968), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_HI_vi
    UINT64_C(3699392512), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_SADDR_gfx10
    UINT64_C(3698917376), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_SADDR_gfx11
    UINT64_C(3976691712), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_SADDR_gfx12
    UINT64_C(3699392512), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_SADDR_vi
    UINT64_C(35747325741645824), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_ST_gfx10
    UINT64_C(34902900811038720), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_ST_gfx11
    UINT64_C(3976691836), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_ST_gfx12
    UINT64_C(35747325741645824), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_ST_gfx940
    UINT64_C(36028800717881344), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_SVS_gfx11
    UINT64_C(562953930113024), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_SVS_gfx12
    UINT64_C(3699400704), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_SVS_gfx940
    UINT64_C(35747325741654016), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_VE_gfx940
    UINT64_C(35184375788224512), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_gfx10
    UINT64_C(70931697830002688), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_gfx11
    UINT64_C(562953930113148), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_gfx12
    UINT64_C(35747325741645824), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_D16_vi
    UINT64_C(3693101056), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_SADDR_gfx10
    UINT64_C(3695247360), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_SADDR_gfx11
    UINT64_C(3976462336), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_SADDR_gfx12
    UINT64_C(3695198208), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_SADDR_vi
    UINT64_C(35747325735354368), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_ST_gfx10
    UINT64_C(34902900807368704), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_ST_gfx11
    UINT64_C(3976462460), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_ST_gfx12
    UINT64_C(35747325737451520), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_ST_gfx940
    UINT64_C(36028800714211328), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_SVS_gfx11
    UINT64_C(562953929883648), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_SVS_gfx12
    UINT64_C(3695206400), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_SVS_gfx940
    UINT64_C(35747325737459712), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_VE_gfx940
    UINT64_C(35184375781933056), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_gfx10
    UINT64_C(70931697826332672), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_gfx11
    UINT64_C(562953929883772), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_gfx12
    UINT64_C(35747325737451520), UINT64_C(0),	// SCRATCH_LOAD_UBYTE_vi
    UINT64_C(3693625344), UINT64_C(0),	// SCRATCH_LOAD_USHORT_SADDR_gfx10
    UINT64_C(3695771648), UINT64_C(0),	// SCRATCH_LOAD_USHORT_SADDR_gfx11
    UINT64_C(3976495104), UINT64_C(0),	// SCRATCH_LOAD_USHORT_SADDR_gfx12
    UINT64_C(3695722496), UINT64_C(0),	// SCRATCH_LOAD_USHORT_SADDR_vi
    UINT64_C(35747325735878656), UINT64_C(0),	// SCRATCH_LOAD_USHORT_ST_gfx10
    UINT64_C(34902900807892992), UINT64_C(0),	// SCRATCH_LOAD_USHORT_ST_gfx11
    UINT64_C(3976495228), UINT64_C(0),	// SCRATCH_LOAD_USHORT_ST_gfx12
    UINT64_C(35747325737975808), UINT64_C(0),	// SCRATCH_LOAD_USHORT_ST_gfx940
    UINT64_C(36028800714735616), UINT64_C(0),	// SCRATCH_LOAD_USHORT_SVS_gfx11
    UINT64_C(562953929916416), UINT64_C(0),	// SCRATCH_LOAD_USHORT_SVS_gfx12
    UINT64_C(3695730688), UINT64_C(0),	// SCRATCH_LOAD_USHORT_SVS_gfx940
    UINT64_C(35747325737984000), UINT64_C(0),	// SCRATCH_LOAD_USHORT_VE_gfx940
    UINT64_C(35184375782457344), UINT64_C(0),	// SCRATCH_LOAD_USHORT_gfx10
    UINT64_C(70931697826856960), UINT64_C(0),	// SCRATCH_LOAD_USHORT_gfx11
    UINT64_C(562953929916540), UINT64_C(0),	// SCRATCH_LOAD_USHORT_gfx12
    UINT64_C(35747325737975808), UINT64_C(0),	// SCRATCH_LOAD_USHORT_vi
    UINT64_C(3977576448), UINT64_C(0),	// SCRATCH_STORE_BLOCK_SADDR_gfx12
    UINT64_C(3977576572), UINT64_C(0),	// SCRATCH_STORE_BLOCK_ST_gfx12
    UINT64_C(562953930997760), UINT64_C(0),	// SCRATCH_STORE_BLOCK_SVS_gfx12
    UINT64_C(562953930997884), UINT64_C(0),	// SCRATCH_STORE_BLOCK_gfx12
    UINT64_C(3697557504), UINT64_C(0),	// SCRATCH_STORE_BYTE_D16_HI_SADDR_gfx10
    UINT64_C(3700490240), UINT64_C(0),	// SCRATCH_STORE_BYTE_D16_HI_SADDR_gfx11
    UINT64_C(3976790016), UINT64_C(0),	// SCRATCH_STORE_BYTE_D16_HI_SADDR_gfx12
    UINT64_C(3697557504), UINT64_C(0),	// SCRATCH_STORE_BYTE_D16_HI_SADDR_vi
    UINT64_C(35747325739810816), UINT64_C(0),	// SCRATCH_STORE_BYTE_D16_HI_ST_gfx10
    UINT64_C(34902900812611584), UINT64_C(0),	// SCRATCH_STORE_BYTE_D16_HI_ST_gfx11
    UINT64_C(3976790140), UINT64_C(0),	// SCRATCH_STORE_BYTE_D16_HI_ST_gfx12
    UINT64_C(35747325739810816), UINT64_C(0),	// SCRATCH_STORE_BYTE_D16_HI_ST_gfx940
    UINT64_C(36028800719454208), UINT64_C(0),	// SCRATCH_STORE_BYTE_D16_HI_SVS_gfx11
    UINT64_C(562953930211328), UINT64_C(0),	// SCRATCH_STORE_BYTE_D16_HI_SVS_gfx12
    UINT64_C(3697565696), UINT64_C(0),	// SCRATCH_STORE_BYTE_D16_HI_SVS_gfx940
    UINT64_C(35747325739819008), UINT64_C(0),	// SCRATCH_STORE_BYTE_D16_HI_VE_gfx940
    UINT64_C(35184375786389504), UINT64_C(0),	// SCRATCH_STORE_BYTE_D16_HI_gfx10
    UINT64_C(70931697831575552), UINT64_C(0),	// SCRATCH_STORE_BYTE_D16_HI_gfx11
    UINT64_C(562953930211452), UINT64_C(0),	// SCRATCH_STORE_BYTE_D16_HI_gfx12
    UINT64_C(35747325739810816), UINT64_C(0),	// SCRATCH_STORE_BYTE_D16_HI_vi
    UINT64_C(3697295360), UINT64_C(0),	// SCRATCH_STORE_BYTE_SADDR_gfx10
    UINT64_C(3697344512), UINT64_C(0),	// SCRATCH_STORE_BYTE_SADDR_gfx11
    UINT64_C(3976593408), UINT64_C(0),	// SCRATCH_STORE_BYTE_SADDR_gfx12
    UINT64_C(3697295360), UINT64_C(0),	// SCRATCH_STORE_BYTE_SADDR_vi
    UINT64_C(35747325739548672), UINT64_C(0),	// SCRATCH_STORE_BYTE_ST_gfx10
    UINT64_C(34902900809465856), UINT64_C(0),	// SCRATCH_STORE_BYTE_ST_gfx11
    UINT64_C(3976593532), UINT64_C(0),	// SCRATCH_STORE_BYTE_ST_gfx12
    UINT64_C(35747325739548672), UINT64_C(0),	// SCRATCH_STORE_BYTE_ST_gfx940
    UINT64_C(36028800716308480), UINT64_C(0),	// SCRATCH_STORE_BYTE_SVS_gfx11
    UINT64_C(562953930014720), UINT64_C(0),	// SCRATCH_STORE_BYTE_SVS_gfx12
    UINT64_C(3697303552), UINT64_C(0),	// SCRATCH_STORE_BYTE_SVS_gfx940
    UINT64_C(35747325739556864), UINT64_C(0),	// SCRATCH_STORE_BYTE_VE_gfx940
    UINT64_C(35184375786127360), UINT64_C(0),	// SCRATCH_STORE_BYTE_gfx10
    UINT64_C(70931697828429824), UINT64_C(0),	// SCRATCH_STORE_BYTE_gfx11
    UINT64_C(562953930014844), UINT64_C(0),	// SCRATCH_STORE_BYTE_gfx12
    UINT64_C(35747325739548672), UINT64_C(0),	// SCRATCH_STORE_BYTE_vi
    UINT64_C(3698606080), UINT64_C(0),	// SCRATCH_STORE_DWORDX2_SADDR_gfx10
    UINT64_C(3698130944), UINT64_C(0),	// SCRATCH_STORE_DWORDX2_SADDR_gfx11
    UINT64_C(3976642560), UINT64_C(0),	// SCRATCH_STORE_DWORDX2_SADDR_gfx12
    UINT64_C(3698606080), UINT64_C(0),	// SCRATCH_STORE_DWORDX2_SADDR_vi
    UINT64_C(35747325740859392), UINT64_C(0),	// SCRATCH_STORE_DWORDX2_ST_gfx10
    UINT64_C(34902900810252288), UINT64_C(0),	// SCRATCH_STORE_DWORDX2_ST_gfx11
    UINT64_C(3976642684), UINT64_C(0),	// SCRATCH_STORE_DWORDX2_ST_gfx12
    UINT64_C(35747325740859392), UINT64_C(0),	// SCRATCH_STORE_DWORDX2_ST_gfx940
    UINT64_C(36028800717094912), UINT64_C(0),	// SCRATCH_STORE_DWORDX2_SVS_gfx11
    UINT64_C(562953930063872), UINT64_C(0),	// SCRATCH_STORE_DWORDX2_SVS_gfx12
    UINT64_C(3698614272), UINT64_C(0),	// SCRATCH_STORE_DWORDX2_SVS_gfx940
    UINT64_C(35747325740867584), UINT64_C(0),	// SCRATCH_STORE_DWORDX2_VE_gfx940
    UINT64_C(35184375787438080), UINT64_C(0),	// SCRATCH_STORE_DWORDX2_gfx10
    UINT64_C(70931697829216256), UINT64_C(0),	// SCRATCH_STORE_DWORDX2_gfx11
    UINT64_C(562953930063996), UINT64_C(0),	// SCRATCH_STORE_DWORDX2_gfx12
    UINT64_C(35747325740859392), UINT64_C(0),	// SCRATCH_STORE_DWORDX2_vi
    UINT64_C(3699130368), UINT64_C(0),	// SCRATCH_STORE_DWORDX3_SADDR_gfx10
    UINT64_C(3698393088), UINT64_C(0),	// SCRATCH_STORE_DWORDX3_SADDR_gfx11
    UINT64_C(3976658944), UINT64_C(0),	// SCRATCH_STORE_DWORDX3_SADDR_gfx12
    UINT64_C(3698868224), UINT64_C(0),	// SCRATCH_STORE_DWORDX3_SADDR_vi
    UINT64_C(35747325741383680), UINT64_C(0),	// SCRATCH_STORE_DWORDX3_ST_gfx10
    UINT64_C(34902900810514432), UINT64_C(0),	// SCRATCH_STORE_DWORDX3_ST_gfx11
    UINT64_C(3976659068), UINT64_C(0),	// SCRATCH_STORE_DWORDX3_ST_gfx12
    UINT64_C(35747325741121536), UINT64_C(0),	// SCRATCH_STORE_DWORDX3_ST_gfx940
    UINT64_C(36028800717357056), UINT64_C(0),	// SCRATCH_STORE_DWORDX3_SVS_gfx11
    UINT64_C(562953930080256), UINT64_C(0),	// SCRATCH_STORE_DWORDX3_SVS_gfx12
    UINT64_C(3698876416), UINT64_C(0),	// SCRATCH_STORE_DWORDX3_SVS_gfx940
    UINT64_C(35747325741129728), UINT64_C(0),	// SCRATCH_STORE_DWORDX3_VE_gfx940
    UINT64_C(35184375787962368), UINT64_C(0),	// SCRATCH_STORE_DWORDX3_gfx10
    UINT64_C(70931697829478400), UINT64_C(0),	// SCRATCH_STORE_DWORDX3_gfx11
    UINT64_C(562953930080380), UINT64_C(0),	// SCRATCH_STORE_DWORDX3_gfx12
    UINT64_C(35747325741121536), UINT64_C(0),	// SCRATCH_STORE_DWORDX3_vi
    UINT64_C(3698868224), UINT64_C(0),	// SCRATCH_STORE_DWORDX4_SADDR_gfx10
    UINT64_C(3698655232), UINT64_C(0),	// SCRATCH_STORE_DWORDX4_SADDR_gfx11
    UINT64_C(3976675328), UINT64_C(0),	// SCRATCH_STORE_DWORDX4_SADDR_gfx12
    UINT64_C(3699130368), UINT64_C(0),	// SCRATCH_STORE_DWORDX4_SADDR_vi
    UINT64_C(35747325741121536), UINT64_C(0),	// SCRATCH_STORE_DWORDX4_ST_gfx10
    UINT64_C(34902900810776576), UINT64_C(0),	// SCRATCH_STORE_DWORDX4_ST_gfx11
    UINT64_C(3976675452), UINT64_C(0),	// SCRATCH_STORE_DWORDX4_ST_gfx12
    UINT64_C(35747325741383680), UINT64_C(0),	// SCRATCH_STORE_DWORDX4_ST_gfx940
    UINT64_C(36028800717619200), UINT64_C(0),	// SCRATCH_STORE_DWORDX4_SVS_gfx11
    UINT64_C(562953930096640), UINT64_C(0),	// SCRATCH_STORE_DWORDX4_SVS_gfx12
    UINT64_C(3699138560), UINT64_C(0),	// SCRATCH_STORE_DWORDX4_SVS_gfx940
    UINT64_C(35747325741391872), UINT64_C(0),	// SCRATCH_STORE_DWORDX4_VE_gfx940
    UINT64_C(35184375787700224), UINT64_C(0),	// SCRATCH_STORE_DWORDX4_gfx10
    UINT64_C(70931697829740544), UINT64_C(0),	// SCRATCH_STORE_DWORDX4_gfx11
    UINT64_C(562953930096764), UINT64_C(0),	// SCRATCH_STORE_DWORDX4_gfx12
    UINT64_C(35747325741383680), UINT64_C(0),	// SCRATCH_STORE_DWORDX4_vi
    UINT64_C(3698343936), UINT64_C(0),	// SCRATCH_STORE_DWORD_SADDR_gfx10
    UINT64_C(3697868800), UINT64_C(0),	// SCRATCH_STORE_DWORD_SADDR_gfx11
    UINT64_C(3976626176), UINT64_C(0),	// SCRATCH_STORE_DWORD_SADDR_gfx12
    UINT64_C(3698343936), UINT64_C(0),	// SCRATCH_STORE_DWORD_SADDR_vi
    UINT64_C(35747325740597248), UINT64_C(0),	// SCRATCH_STORE_DWORD_ST_gfx10
    UINT64_C(34902900809990144), UINT64_C(0),	// SCRATCH_STORE_DWORD_ST_gfx11
    UINT64_C(3976626300), UINT64_C(0),	// SCRATCH_STORE_DWORD_ST_gfx12
    UINT64_C(35747325740597248), UINT64_C(0),	// SCRATCH_STORE_DWORD_ST_gfx940
    UINT64_C(36028800716832768), UINT64_C(0),	// SCRATCH_STORE_DWORD_SVS_gfx11
    UINT64_C(562953930047488), UINT64_C(0),	// SCRATCH_STORE_DWORD_SVS_gfx12
    UINT64_C(3698352128), UINT64_C(0),	// SCRATCH_STORE_DWORD_SVS_gfx940
    UINT64_C(35747325740605440), UINT64_C(0),	// SCRATCH_STORE_DWORD_VE_gfx940
    UINT64_C(35184375787175936), UINT64_C(0),	// SCRATCH_STORE_DWORD_gfx10
    UINT64_C(70931697828954112), UINT64_C(0),	// SCRATCH_STORE_DWORD_gfx11
    UINT64_C(562953930047612), UINT64_C(0),	// SCRATCH_STORE_DWORD_gfx12
    UINT64_C(35747325740597248), UINT64_C(0),	// SCRATCH_STORE_DWORD_vi
    UINT64_C(3698081792), UINT64_C(0),	// SCRATCH_STORE_SHORT_D16_HI_SADDR_gfx10
    UINT64_C(3700752384), UINT64_C(0),	// SCRATCH_STORE_SHORT_D16_HI_SADDR_gfx11
    UINT64_C(3976806400), UINT64_C(0),	// SCRATCH_STORE_SHORT_D16_HI_SADDR_gfx12
    UINT64_C(3698081792), UINT64_C(0),	// SCRATCH_STORE_SHORT_D16_HI_SADDR_vi
    UINT64_C(35747325740335104), UINT64_C(0),	// SCRATCH_STORE_SHORT_D16_HI_ST_gfx10
    UINT64_C(34902900812873728), UINT64_C(0),	// SCRATCH_STORE_SHORT_D16_HI_ST_gfx11
    UINT64_C(3976806524), UINT64_C(0),	// SCRATCH_STORE_SHORT_D16_HI_ST_gfx12
    UINT64_C(35747325740335104), UINT64_C(0),	// SCRATCH_STORE_SHORT_D16_HI_ST_gfx940
    UINT64_C(36028800719716352), UINT64_C(0),	// SCRATCH_STORE_SHORT_D16_HI_SVS_gfx11
    UINT64_C(562953930227712), UINT64_C(0),	// SCRATCH_STORE_SHORT_D16_HI_SVS_gfx12
    UINT64_C(3698089984), UINT64_C(0),	// SCRATCH_STORE_SHORT_D16_HI_SVS_gfx940
    UINT64_C(35747325740343296), UINT64_C(0),	// SCRATCH_STORE_SHORT_D16_HI_VE_gfx940
    UINT64_C(35184375786913792), UINT64_C(0),	// SCRATCH_STORE_SHORT_D16_HI_gfx10
    UINT64_C(70931697831837696), UINT64_C(0),	// SCRATCH_STORE_SHORT_D16_HI_gfx11
    UINT64_C(562953930227836), UINT64_C(0),	// SCRATCH_STORE_SHORT_D16_HI_gfx12
    UINT64_C(35747325740335104), UINT64_C(0),	// SCRATCH_STORE_SHORT_D16_HI_vi
    UINT64_C(3697819648), UINT64_C(0),	// SCRATCH_STORE_SHORT_SADDR_gfx10
    UINT64_C(3697606656), UINT64_C(0),	// SCRATCH_STORE_SHORT_SADDR_gfx11
    UINT64_C(3976609792), UINT64_C(0),	// SCRATCH_STORE_SHORT_SADDR_gfx12
    UINT64_C(3697819648), UINT64_C(0),	// SCRATCH_STORE_SHORT_SADDR_vi
    UINT64_C(35747325740072960), UINT64_C(0),	// SCRATCH_STORE_SHORT_ST_gfx10
    UINT64_C(34902900809728000), UINT64_C(0),	// SCRATCH_STORE_SHORT_ST_gfx11
    UINT64_C(3976609916), UINT64_C(0),	// SCRATCH_STORE_SHORT_ST_gfx12
    UINT64_C(35747325740072960), UINT64_C(0),	// SCRATCH_STORE_SHORT_ST_gfx940
    UINT64_C(36028800716570624), UINT64_C(0),	// SCRATCH_STORE_SHORT_SVS_gfx11
    UINT64_C(562953930031104), UINT64_C(0),	// SCRATCH_STORE_SHORT_SVS_gfx12
    UINT64_C(3697827840), UINT64_C(0),	// SCRATCH_STORE_SHORT_SVS_gfx940
    UINT64_C(35747325740081152), UINT64_C(0),	// SCRATCH_STORE_SHORT_VE_gfx940
    UINT64_C(35184375786651648), UINT64_C(0),	// SCRATCH_STORE_SHORT_gfx10
    UINT64_C(70931697828691968), UINT64_C(0),	// SCRATCH_STORE_SHORT_gfx11
    UINT64_C(562953930031228), UINT64_C(0),	// SCRATCH_STORE_SHORT_gfx12
    UINT64_C(35747325740072960), UINT64_C(0),	// SCRATCH_STORE_SHORT_vi
    UINT64_C(2516582400), UINT64_C(0),	// S_ABSDIFF_I32_gfx10
    UINT64_C(2197815296), UINT64_C(0),	// S_ABSDIFF_I32_gfx11
    UINT64_C(2197815296), UINT64_C(0),	// S_ABSDIFF_I32_gfx12
    UINT64_C(2516582400), UINT64_C(0),	// S_ABSDIFF_I32_gfx6_gfx7
    UINT64_C(2499805184), UINT64_C(0),	// S_ABSDIFF_I32_vi
    UINT64_C(3196072960), UINT64_C(0),	// S_ABS_I32_gfx10
    UINT64_C(3196065024), UINT64_C(0),	// S_ABS_I32_gfx11
    UINT64_C(3196065024), UINT64_C(0),	// S_ABS_I32_gfx12
    UINT64_C(3196072960), UINT64_C(0),	// S_ABS_I32_gfx6_gfx7
    UINT64_C(3196071936), UINT64_C(0),	// S_ABS_I32_vi
    UINT64_C(2181038080), UINT64_C(0),	// S_ADDC_U32_gfx10
    UINT64_C(2181038080), UINT64_C(0),	// S_ADDC_U32_gfx11
    UINT64_C(2181038080), UINT64_C(0),	// S_ADDC_U32_gfx12
    UINT64_C(2181038080), UINT64_C(0),	// S_ADDC_U32_gfx6_gfx7
    UINT64_C(2181038080), UINT64_C(0),	// S_ADDC_U32_vi
    UINT64_C(3078619136), UINT64_C(0),	// S_ADDK_I32_gfx10
    UINT64_C(3078619136), UINT64_C(0),	// S_ADDK_I32_gfx11
    UINT64_C(3078619136), UINT64_C(0),	// S_ADDK_I32_gfx12
    UINT64_C(3078619136), UINT64_C(0),	// S_ADDK_I32_gfx6_gfx7
    UINT64_C(3070230528), UINT64_C(0),	// S_ADDK_I32_vi
    UINT64_C(2759852032), UINT64_C(0),	// S_ADD_F16_gfx11
    UINT64_C(2759852032), UINT64_C(0),	// S_ADD_F16_gfx12
    UINT64_C(2684354560), UINT64_C(0),	// S_ADD_F32_gfx11
    UINT64_C(2684354560), UINT64_C(0),	// S_ADD_F32_gfx12
    UINT64_C(2164260864), UINT64_C(0),	// S_ADD_I32_gfx10
    UINT64_C(2164260864), UINT64_C(0),	// S_ADD_I32_gfx11
    UINT64_C(2164260864), UINT64_C(0),	// S_ADD_I32_gfx12
    UINT64_C(2164260864), UINT64_C(0),	// S_ADD_I32_gfx6_gfx7
    UINT64_C(2164260864), UINT64_C(0),	// S_ADD_I32_vi
    UINT64_C(3196078848), UINT64_C(0),	// S_ADD_PC_I64_gfx12
    UINT64_C(2147483648), UINT64_C(0),	// S_ADD_U32_gfx10
    UINT64_C(2147483648), UINT64_C(0),	// S_ADD_U32_gfx11
    UINT64_C(2147483648), UINT64_C(0),	// S_ADD_U32_gfx12
    UINT64_C(2147483648), UINT64_C(0),	// S_ADD_U32_gfx6_gfx7
    UINT64_C(2147483648), UINT64_C(0),	// S_ADD_U32_vi
    UINT64_C(2843738112), UINT64_C(0),	// S_ADD_U64_gfx12
    UINT64_C(3196080896), UINT64_C(0),	// S_ALLOC_VGPR_gfx12
    UINT64_C(3196077056), UINT64_C(0),	// S_ANDN1_SAVEEXEC_B32_gfx10
    UINT64_C(3196070912), UINT64_C(0),	// S_ANDN1_SAVEEXEC_B32_gfx11
    UINT64_C(3196070912), UINT64_C(0),	// S_ANDN1_SAVEEXEC_B32_gfx12
    UINT64_C(3196073728), UINT64_C(0),	// S_ANDN1_SAVEEXEC_B64_gfx10
    UINT64_C(3196071168), UINT64_C(0),	// S_ANDN1_SAVEEXEC_B64_gfx11
    UINT64_C(3196071168), UINT64_C(0),	// S_ANDN1_SAVEEXEC_B64_gfx12
    UINT64_C(3196072704), UINT64_C(0),	// S_ANDN1_SAVEEXEC_B64_vi
    UINT64_C(3196077568), UINT64_C(0),	// S_ANDN1_WREXEC_B32_gfx10
    UINT64_C(3196072960), UINT64_C(0),	// S_ANDN1_WREXEC_B32_gfx11
    UINT64_C(3196072960), UINT64_C(0),	// S_ANDN1_WREXEC_B32_gfx12
    UINT64_C(3196074240), UINT64_C(0),	// S_ANDN1_WREXEC_B64_gfx10
    UINT64_C(3196073216), UINT64_C(0),	// S_ANDN1_WREXEC_B64_gfx11
    UINT64_C(3196073216), UINT64_C(0),	// S_ANDN1_WREXEC_B64_gfx12
    UINT64_C(3196073216), UINT64_C(0),	// S_ANDN1_WREXEC_B64_vi
    UINT64_C(2315255808), UINT64_C(0),	// S_ANDN2_B32_gfx10
    UINT64_C(2432696320), UINT64_C(0),	// S_ANDN2_B32_gfx11
    UINT64_C(2432696320), UINT64_C(0),	// S_ANDN2_B32_gfx12
    UINT64_C(2315255808), UINT64_C(0),	// S_ANDN2_B32_gfx6_gfx7
    UINT64_C(2298478592), UINT64_C(0),	// S_ANDN2_B32_vi
    UINT64_C(2323644416), UINT64_C(0),	// S_ANDN2_B64_gfx10
    UINT64_C(2441084928), UINT64_C(0),	// S_ANDN2_B64_gfx11
    UINT64_C(2441084928), UINT64_C(0),	// S_ANDN2_B64_gfx12
    UINT64_C(2323644416), UINT64_C(0),	// S_ANDN2_B64_gfx6_gfx7
    UINT64_C(2306867200), UINT64_C(0),	// S_ANDN2_B64_vi
    UINT64_C(3196075776), UINT64_C(0),	// S_ANDN2_SAVEEXEC_B32_gfx10
    UINT64_C(3196071936), UINT64_C(0),	// S_ANDN2_SAVEEXEC_B32_gfx11
    UINT64_C(3196071936), UINT64_C(0),	// S_ANDN2_SAVEEXEC_B32_gfx12
    UINT64_C(3196069632), UINT64_C(0),	// S_ANDN2_SAVEEXEC_B64_gfx10
    UINT64_C(3196072192), UINT64_C(0),	// S_ANDN2_SAVEEXEC_B64_gfx11
    UINT64_C(3196072192), UINT64_C(0),	// S_ANDN2_SAVEEXEC_B64_gfx12
    UINT64_C(3196069632), UINT64_C(0),	// S_ANDN2_SAVEEXEC_B64_gfx6_gfx7
    UINT64_C(3196068608), UINT64_C(0),	// S_ANDN2_SAVEEXEC_B64_vi
    UINT64_C(3196077824), UINT64_C(0),	// S_ANDN2_WREXEC_B32_gfx10
    UINT64_C(3196073472), UINT64_C(0),	// S_ANDN2_WREXEC_B32_gfx11
    UINT64_C(3196073472), UINT64_C(0),	// S_ANDN2_WREXEC_B32_gfx12
    UINT64_C(3196074496), UINT64_C(0),	// S_ANDN2_WREXEC_B64_gfx10
    UINT64_C(3196073728), UINT64_C(0),	// S_ANDN2_WREXEC_B64_gfx11
    UINT64_C(3196073728), UINT64_C(0),	// S_ANDN2_WREXEC_B64_gfx12
    UINT64_C(3196073472), UINT64_C(0),	// S_ANDN2_WREXEC_B64_vi
    UINT64_C(2264924160), UINT64_C(0),	// S_AND_B32_gfx10
    UINT64_C(2332033024), UINT64_C(0),	// S_AND_B32_gfx11
    UINT64_C(2332033024), UINT64_C(0),	// S_AND_B32_gfx12
    UINT64_C(2264924160), UINT64_C(0),	// S_AND_B32_gfx6_gfx7
    UINT64_C(2248146944), UINT64_C(0),	// S_AND_B32_vi
    UINT64_C(2273312768), UINT64_C(0),	// S_AND_B64_gfx10
    UINT64_C(2340421632), UINT64_C(0),	// S_AND_B64_gfx11
    UINT64_C(2340421632), UINT64_C(0),	// S_AND_B64_gfx12
    UINT64_C(2273312768), UINT64_C(0),	// S_AND_B64_gfx6_gfx7
    UINT64_C(2256535552), UINT64_C(0),	// S_AND_B64_vi
    UINT64_C(3196075008), UINT64_C(0),	// S_AND_SAVEEXEC_B32_gfx10
    UINT64_C(3196067840), UINT64_C(0),	// S_AND_SAVEEXEC_B32_gfx11
    UINT64_C(3196067840), UINT64_C(0),	// S_AND_SAVEEXEC_B32_gfx12
    UINT64_C(3196068864), UINT64_C(0),	// S_AND_SAVEEXEC_B64_gfx10
    UINT64_C(3196068096), UINT64_C(0),	// S_AND_SAVEEXEC_B64_gfx11
    UINT64_C(3196068096), UINT64_C(0),	// S_AND_SAVEEXEC_B64_gfx12
    UINT64_C(3196068864), UINT64_C(0),	// S_AND_SAVEEXEC_B64_gfx6_gfx7
    UINT64_C(3196067840), UINT64_C(0),	// S_AND_SAVEEXEC_B64_vi
    UINT64_C(2432696320), UINT64_C(0),	// S_ASHR_I32_gfx10
    UINT64_C(2248146944), UINT64_C(0),	// S_ASHR_I32_gfx11
    UINT64_C(2248146944), UINT64_C(0),	// S_ASHR_I32_gfx12
    UINT64_C(2432696320), UINT64_C(0),	// S_ASHR_I32_gfx6_gfx7
    UINT64_C(2415919104), UINT64_C(0),	// S_ASHR_I32_vi
    UINT64_C(2441084928), UINT64_C(0),	// S_ASHR_I64_gfx10
    UINT64_C(2256535552), UINT64_C(0),	// S_ASHR_I64_gfx11
    UINT64_C(2256535552), UINT64_C(0),	// S_ASHR_I64_gfx12
    UINT64_C(2441084928), UINT64_C(0),	// S_ASHR_I64_gfx6_gfx7
    UINT64_C(2424307712), UINT64_C(0),	// S_ASHR_I64_vi
    UINT64_C(18014398513585848320), UINT64_C(0),	// S_ATC_PROBE_BUFFER_IMM_gfx10
    UINT64_C(17870283325508943872), UINT64_C(0),	// S_ATC_PROBE_BUFFER_IMM_gfx11
    UINT64_C(17870283325500055552), UINT64_C(0),	// S_ATC_PROBE_BUFFER_IMM_gfx12
    UINT64_C(3231580160), UINT64_C(0),	// S_ATC_PROBE_BUFFER_IMM_vi
    UINT64_C(4103864320), UINT64_C(0),	// S_ATC_PROBE_BUFFER_SGPR_IMM_gfx10
    UINT64_C(4102815744), UINT64_C(0),	// S_ATC_PROBE_BUFFER_SGPR_IMM_gfx11
    UINT64_C(4093927424), UINT64_C(0),	// S_ATC_PROBE_BUFFER_SGPR_IMM_gfx12
    UINT64_C(3231596544), UINT64_C(0),	// S_ATC_PROBE_BUFFER_SGPR_IMM_gfx9
    UINT64_C(3231465472), UINT64_C(0),	// S_ATC_PROBE_BUFFER_SGPR_alt_gfx9
    UINT64_C(4103864320), UINT64_C(0),	// S_ATC_PROBE_BUFFER_SGPR_gfx10
    UINT64_C(4102815744), UINT64_C(0),	// S_ATC_PROBE_BUFFER_SGPR_gfx11
    UINT64_C(3231449088), UINT64_C(0),	// S_ATC_PROBE_BUFFER_SGPR_vi
    UINT64_C(18014398513585586176), UINT64_C(0),	// S_ATC_PROBE_IMM_gfx10
    UINT64_C(17870283325508681728), UINT64_C(0),	// S_ATC_PROBE_IMM_gfx11
    UINT64_C(17870283325500047360), UINT64_C(0),	// S_ATC_PROBE_IMM_gfx12
    UINT64_C(3231318016), UINT64_C(0),	// S_ATC_PROBE_IMM_vi
    UINT64_C(4103602176), UINT64_C(0),	// S_ATC_PROBE_SGPR_IMM_gfx10
    UINT64_C(4102553600), UINT64_C(0),	// S_ATC_PROBE_SGPR_IMM_gfx11
    UINT64_C(4093919232), UINT64_C(0),	// S_ATC_PROBE_SGPR_IMM_gfx12
    UINT64_C(3231334400), UINT64_C(0),	// S_ATC_PROBE_SGPR_IMM_gfx9
    UINT64_C(3231203328), UINT64_C(0),	// S_ATC_PROBE_SGPR_alt_gfx9
    UINT64_C(4103602176), UINT64_C(0),	// S_ATC_PROBE_SGPR_gfx10
    UINT64_C(4102553600), UINT64_C(0),	// S_ATC_PROBE_SGPR_gfx11
    UINT64_C(3231186944), UINT64_C(0),	// S_ATC_PROBE_SGPR_vi
    UINT64_C(18014398513609768960), UINT64_C(0),	// S_ATOMIC_ADD_IMM_RTN_gfx10
    UINT64_C(3255500800), UINT64_C(0),	// S_ATOMIC_ADD_IMM_RTN_vi
    UINT64_C(18014398513609703424), UINT64_C(0),	// S_ATOMIC_ADD_IMM_gfx10
    UINT64_C(3255435264), UINT64_C(0),	// S_ATOMIC_ADD_IMM_vi
    UINT64_C(4127784960), UINT64_C(0),	// S_ATOMIC_ADD_SGPR_IMM_RTN_gfx10
    UINT64_C(3255517184), UINT64_C(0),	// S_ATOMIC_ADD_SGPR_IMM_RTN_gfx9
    UINT64_C(4127719424), UINT64_C(0),	// S_ATOMIC_ADD_SGPR_IMM_gfx10
    UINT64_C(3255451648), UINT64_C(0),	// S_ATOMIC_ADD_SGPR_IMM_gfx9
    UINT64_C(3255386112), UINT64_C(0),	// S_ATOMIC_ADD_SGPR_RTN_alt_gfx9
    UINT64_C(4127784960), UINT64_C(0),	// S_ATOMIC_ADD_SGPR_RTN_gfx10
    UINT64_C(3255369728), UINT64_C(0),	// S_ATOMIC_ADD_SGPR_RTN_vi
    UINT64_C(3255320576), UINT64_C(0),	// S_ATOMIC_ADD_SGPR_alt_gfx9
    UINT64_C(4127719424), UINT64_C(0),	// S_ATOMIC_ADD_SGPR_gfx10
    UINT64_C(3255304192), UINT64_C(0),	// S_ATOMIC_ADD_SGPR_vi
    UINT64_C(18014398513618157568), UINT64_C(0),	// S_ATOMIC_ADD_X2_IMM_RTN_gfx10
    UINT64_C(3263889408), UINT64_C(0),	// S_ATOMIC_ADD_X2_IMM_RTN_vi
    UINT64_C(18014398513618092032), UINT64_C(0),	// S_ATOMIC_ADD_X2_IMM_gfx10
    UINT64_C(3263823872), UINT64_C(0),	// S_ATOMIC_ADD_X2_IMM_vi
    UINT64_C(4136173568), UINT64_C(0),	// S_ATOMIC_ADD_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3263905792), UINT64_C(0),	// S_ATOMIC_ADD_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4136108032), UINT64_C(0),	// S_ATOMIC_ADD_X2_SGPR_IMM_gfx10
    UINT64_C(3263840256), UINT64_C(0),	// S_ATOMIC_ADD_X2_SGPR_IMM_gfx9
    UINT64_C(3263774720), UINT64_C(0),	// S_ATOMIC_ADD_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4136173568), UINT64_C(0),	// S_ATOMIC_ADD_X2_SGPR_RTN_gfx10
    UINT64_C(3263758336), UINT64_C(0),	// S_ATOMIC_ADD_X2_SGPR_RTN_vi
    UINT64_C(3263709184), UINT64_C(0),	// S_ATOMIC_ADD_X2_SGPR_alt_gfx9
    UINT64_C(4136108032), UINT64_C(0),	// S_ATOMIC_ADD_X2_SGPR_gfx10
    UINT64_C(3263692800), UINT64_C(0),	// S_ATOMIC_ADD_X2_SGPR_vi
    UINT64_C(18014398513611341824), UINT64_C(0),	// S_ATOMIC_AND_IMM_RTN_gfx10
    UINT64_C(3257073664), UINT64_C(0),	// S_ATOMIC_AND_IMM_RTN_vi
    UINT64_C(18014398513611276288), UINT64_C(0),	// S_ATOMIC_AND_IMM_gfx10
    UINT64_C(3257008128), UINT64_C(0),	// S_ATOMIC_AND_IMM_vi
    UINT64_C(4129357824), UINT64_C(0),	// S_ATOMIC_AND_SGPR_IMM_RTN_gfx10
    UINT64_C(3257090048), UINT64_C(0),	// S_ATOMIC_AND_SGPR_IMM_RTN_gfx9
    UINT64_C(4129292288), UINT64_C(0),	// S_ATOMIC_AND_SGPR_IMM_gfx10
    UINT64_C(3257024512), UINT64_C(0),	// S_ATOMIC_AND_SGPR_IMM_gfx9
    UINT64_C(3256958976), UINT64_C(0),	// S_ATOMIC_AND_SGPR_RTN_alt_gfx9
    UINT64_C(4129357824), UINT64_C(0),	// S_ATOMIC_AND_SGPR_RTN_gfx10
    UINT64_C(3256942592), UINT64_C(0),	// S_ATOMIC_AND_SGPR_RTN_vi
    UINT64_C(3256893440), UINT64_C(0),	// S_ATOMIC_AND_SGPR_alt_gfx9
    UINT64_C(4129292288), UINT64_C(0),	// S_ATOMIC_AND_SGPR_gfx10
    UINT64_C(3256877056), UINT64_C(0),	// S_ATOMIC_AND_SGPR_vi
    UINT64_C(18014398513619730432), UINT64_C(0),	// S_ATOMIC_AND_X2_IMM_RTN_gfx10
    UINT64_C(3265462272), UINT64_C(0),	// S_ATOMIC_AND_X2_IMM_RTN_vi
    UINT64_C(18014398513619664896), UINT64_C(0),	// S_ATOMIC_AND_X2_IMM_gfx10
    UINT64_C(3265396736), UINT64_C(0),	// S_ATOMIC_AND_X2_IMM_vi
    UINT64_C(4137746432), UINT64_C(0),	// S_ATOMIC_AND_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3265478656), UINT64_C(0),	// S_ATOMIC_AND_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4137680896), UINT64_C(0),	// S_ATOMIC_AND_X2_SGPR_IMM_gfx10
    UINT64_C(3265413120), UINT64_C(0),	// S_ATOMIC_AND_X2_SGPR_IMM_gfx9
    UINT64_C(3265347584), UINT64_C(0),	// S_ATOMIC_AND_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4137746432), UINT64_C(0),	// S_ATOMIC_AND_X2_SGPR_RTN_gfx10
    UINT64_C(3265331200), UINT64_C(0),	// S_ATOMIC_AND_X2_SGPR_RTN_vi
    UINT64_C(3265282048), UINT64_C(0),	// S_ATOMIC_AND_X2_SGPR_alt_gfx9
    UINT64_C(4137680896), UINT64_C(0),	// S_ATOMIC_AND_X2_SGPR_gfx10
    UINT64_C(3265265664), UINT64_C(0),	// S_ATOMIC_AND_X2_SGPR_vi
    UINT64_C(18014398513609506816), UINT64_C(0),	// S_ATOMIC_CMPSWAP_IMM_RTN_gfx10
    UINT64_C(3255238656), UINT64_C(0),	// S_ATOMIC_CMPSWAP_IMM_RTN_vi
    UINT64_C(18014398513609441280), UINT64_C(0),	// S_ATOMIC_CMPSWAP_IMM_gfx10
    UINT64_C(3255173120), UINT64_C(0),	// S_ATOMIC_CMPSWAP_IMM_vi
    UINT64_C(4127522816), UINT64_C(0),	// S_ATOMIC_CMPSWAP_SGPR_IMM_RTN_gfx10
    UINT64_C(3255255040), UINT64_C(0),	// S_ATOMIC_CMPSWAP_SGPR_IMM_RTN_gfx9
    UINT64_C(4127457280), UINT64_C(0),	// S_ATOMIC_CMPSWAP_SGPR_IMM_gfx10
    UINT64_C(3255189504), UINT64_C(0),	// S_ATOMIC_CMPSWAP_SGPR_IMM_gfx9
    UINT64_C(3255123968), UINT64_C(0),	// S_ATOMIC_CMPSWAP_SGPR_RTN_alt_gfx9
    UINT64_C(4127522816), UINT64_C(0),	// S_ATOMIC_CMPSWAP_SGPR_RTN_gfx10
    UINT64_C(3255107584), UINT64_C(0),	// S_ATOMIC_CMPSWAP_SGPR_RTN_vi
    UINT64_C(3255058432), UINT64_C(0),	// S_ATOMIC_CMPSWAP_SGPR_alt_gfx9
    UINT64_C(4127457280), UINT64_C(0),	// S_ATOMIC_CMPSWAP_SGPR_gfx10
    UINT64_C(3255042048), UINT64_C(0),	// S_ATOMIC_CMPSWAP_SGPR_vi
    UINT64_C(18014398513617895424), UINT64_C(0),	// S_ATOMIC_CMPSWAP_X2_IMM_RTN_gfx10
    UINT64_C(3263627264), UINT64_C(0),	// S_ATOMIC_CMPSWAP_X2_IMM_RTN_vi
    UINT64_C(18014398513617829888), UINT64_C(0),	// S_ATOMIC_CMPSWAP_X2_IMM_gfx10
    UINT64_C(3263561728), UINT64_C(0),	// S_ATOMIC_CMPSWAP_X2_IMM_vi
    UINT64_C(4135911424), UINT64_C(0),	// S_ATOMIC_CMPSWAP_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3263643648), UINT64_C(0),	// S_ATOMIC_CMPSWAP_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4135845888), UINT64_C(0),	// S_ATOMIC_CMPSWAP_X2_SGPR_IMM_gfx10
    UINT64_C(3263578112), UINT64_C(0),	// S_ATOMIC_CMPSWAP_X2_SGPR_IMM_gfx9
    UINT64_C(3263512576), UINT64_C(0),	// S_ATOMIC_CMPSWAP_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4135911424), UINT64_C(0),	// S_ATOMIC_CMPSWAP_X2_SGPR_RTN_gfx10
    UINT64_C(3263496192), UINT64_C(0),	// S_ATOMIC_CMPSWAP_X2_SGPR_RTN_vi
    UINT64_C(3263447040), UINT64_C(0),	// S_ATOMIC_CMPSWAP_X2_SGPR_alt_gfx9
    UINT64_C(4135845888), UINT64_C(0),	// S_ATOMIC_CMPSWAP_X2_SGPR_gfx10
    UINT64_C(3263430656), UINT64_C(0),	// S_ATOMIC_CMPSWAP_X2_SGPR_vi
    UINT64_C(18014398513612390400), UINT64_C(0),	// S_ATOMIC_DEC_IMM_RTN_gfx10
    UINT64_C(3258122240), UINT64_C(0),	// S_ATOMIC_DEC_IMM_RTN_vi
    UINT64_C(18014398513612324864), UINT64_C(0),	// S_ATOMIC_DEC_IMM_gfx10
    UINT64_C(3258056704), UINT64_C(0),	// S_ATOMIC_DEC_IMM_vi
    UINT64_C(4130406400), UINT64_C(0),	// S_ATOMIC_DEC_SGPR_IMM_RTN_gfx10
    UINT64_C(3258138624), UINT64_C(0),	// S_ATOMIC_DEC_SGPR_IMM_RTN_gfx9
    UINT64_C(4130340864), UINT64_C(0),	// S_ATOMIC_DEC_SGPR_IMM_gfx10
    UINT64_C(3258073088), UINT64_C(0),	// S_ATOMIC_DEC_SGPR_IMM_gfx9
    UINT64_C(3258007552), UINT64_C(0),	// S_ATOMIC_DEC_SGPR_RTN_alt_gfx9
    UINT64_C(4130406400), UINT64_C(0),	// S_ATOMIC_DEC_SGPR_RTN_gfx10
    UINT64_C(3257991168), UINT64_C(0),	// S_ATOMIC_DEC_SGPR_RTN_vi
    UINT64_C(3257942016), UINT64_C(0),	// S_ATOMIC_DEC_SGPR_alt_gfx9
    UINT64_C(4130340864), UINT64_C(0),	// S_ATOMIC_DEC_SGPR_gfx10
    UINT64_C(3257925632), UINT64_C(0),	// S_ATOMIC_DEC_SGPR_vi
    UINT64_C(18014398513620779008), UINT64_C(0),	// S_ATOMIC_DEC_X2_IMM_RTN_gfx10
    UINT64_C(3266510848), UINT64_C(0),	// S_ATOMIC_DEC_X2_IMM_RTN_vi
    UINT64_C(18014398513620713472), UINT64_C(0),	// S_ATOMIC_DEC_X2_IMM_gfx10
    UINT64_C(3266445312), UINT64_C(0),	// S_ATOMIC_DEC_X2_IMM_vi
    UINT64_C(4138795008), UINT64_C(0),	// S_ATOMIC_DEC_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3266527232), UINT64_C(0),	// S_ATOMIC_DEC_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4138729472), UINT64_C(0),	// S_ATOMIC_DEC_X2_SGPR_IMM_gfx10
    UINT64_C(3266461696), UINT64_C(0),	// S_ATOMIC_DEC_X2_SGPR_IMM_gfx9
    UINT64_C(3266396160), UINT64_C(0),	// S_ATOMIC_DEC_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4138795008), UINT64_C(0),	// S_ATOMIC_DEC_X2_SGPR_RTN_gfx10
    UINT64_C(3266379776), UINT64_C(0),	// S_ATOMIC_DEC_X2_SGPR_RTN_vi
    UINT64_C(3266330624), UINT64_C(0),	// S_ATOMIC_DEC_X2_SGPR_alt_gfx9
    UINT64_C(4138729472), UINT64_C(0),	// S_ATOMIC_DEC_X2_SGPR_gfx10
    UINT64_C(3266314240), UINT64_C(0),	// S_ATOMIC_DEC_X2_SGPR_vi
    UINT64_C(18014398513612128256), UINT64_C(0),	// S_ATOMIC_INC_IMM_RTN_gfx10
    UINT64_C(3257860096), UINT64_C(0),	// S_ATOMIC_INC_IMM_RTN_vi
    UINT64_C(18014398513612062720), UINT64_C(0),	// S_ATOMIC_INC_IMM_gfx10
    UINT64_C(3257794560), UINT64_C(0),	// S_ATOMIC_INC_IMM_vi
    UINT64_C(4130144256), UINT64_C(0),	// S_ATOMIC_INC_SGPR_IMM_RTN_gfx10
    UINT64_C(3257876480), UINT64_C(0),	// S_ATOMIC_INC_SGPR_IMM_RTN_gfx9
    UINT64_C(4130078720), UINT64_C(0),	// S_ATOMIC_INC_SGPR_IMM_gfx10
    UINT64_C(3257810944), UINT64_C(0),	// S_ATOMIC_INC_SGPR_IMM_gfx9
    UINT64_C(3257745408), UINT64_C(0),	// S_ATOMIC_INC_SGPR_RTN_alt_gfx9
    UINT64_C(4130144256), UINT64_C(0),	// S_ATOMIC_INC_SGPR_RTN_gfx10
    UINT64_C(3257729024), UINT64_C(0),	// S_ATOMIC_INC_SGPR_RTN_vi
    UINT64_C(3257679872), UINT64_C(0),	// S_ATOMIC_INC_SGPR_alt_gfx9
    UINT64_C(4130078720), UINT64_C(0),	// S_ATOMIC_INC_SGPR_gfx10
    UINT64_C(3257663488), UINT64_C(0),	// S_ATOMIC_INC_SGPR_vi
    UINT64_C(18014398513620516864), UINT64_C(0),	// S_ATOMIC_INC_X2_IMM_RTN_gfx10
    UINT64_C(3266248704), UINT64_C(0),	// S_ATOMIC_INC_X2_IMM_RTN_vi
    UINT64_C(18014398513620451328), UINT64_C(0),	// S_ATOMIC_INC_X2_IMM_gfx10
    UINT64_C(3266183168), UINT64_C(0),	// S_ATOMIC_INC_X2_IMM_vi
    UINT64_C(4138532864), UINT64_C(0),	// S_ATOMIC_INC_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3266265088), UINT64_C(0),	// S_ATOMIC_INC_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4138467328), UINT64_C(0),	// S_ATOMIC_INC_X2_SGPR_IMM_gfx10
    UINT64_C(3266199552), UINT64_C(0),	// S_ATOMIC_INC_X2_SGPR_IMM_gfx9
    UINT64_C(3266134016), UINT64_C(0),	// S_ATOMIC_INC_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4138532864), UINT64_C(0),	// S_ATOMIC_INC_X2_SGPR_RTN_gfx10
    UINT64_C(3266117632), UINT64_C(0),	// S_ATOMIC_INC_X2_SGPR_RTN_vi
    UINT64_C(3266068480), UINT64_C(0),	// S_ATOMIC_INC_X2_SGPR_alt_gfx9
    UINT64_C(4138467328), UINT64_C(0),	// S_ATOMIC_INC_X2_SGPR_gfx10
    UINT64_C(3266052096), UINT64_C(0),	// S_ATOMIC_INC_X2_SGPR_vi
    UINT64_C(18014398513611603968), UINT64_C(0),	// S_ATOMIC_OR_IMM_RTN_gfx10
    UINT64_C(3257335808), UINT64_C(0),	// S_ATOMIC_OR_IMM_RTN_vi
    UINT64_C(18014398513611538432), UINT64_C(0),	// S_ATOMIC_OR_IMM_gfx10
    UINT64_C(3257270272), UINT64_C(0),	// S_ATOMIC_OR_IMM_vi
    UINT64_C(4129619968), UINT64_C(0),	// S_ATOMIC_OR_SGPR_IMM_RTN_gfx10
    UINT64_C(3257352192), UINT64_C(0),	// S_ATOMIC_OR_SGPR_IMM_RTN_gfx9
    UINT64_C(4129554432), UINT64_C(0),	// S_ATOMIC_OR_SGPR_IMM_gfx10
    UINT64_C(3257286656), UINT64_C(0),	// S_ATOMIC_OR_SGPR_IMM_gfx9
    UINT64_C(3257221120), UINT64_C(0),	// S_ATOMIC_OR_SGPR_RTN_alt_gfx9
    UINT64_C(4129619968), UINT64_C(0),	// S_ATOMIC_OR_SGPR_RTN_gfx10
    UINT64_C(3257204736), UINT64_C(0),	// S_ATOMIC_OR_SGPR_RTN_vi
    UINT64_C(3257155584), UINT64_C(0),	// S_ATOMIC_OR_SGPR_alt_gfx9
    UINT64_C(4129554432), UINT64_C(0),	// S_ATOMIC_OR_SGPR_gfx10
    UINT64_C(3257139200), UINT64_C(0),	// S_ATOMIC_OR_SGPR_vi
    UINT64_C(18014398513619992576), UINT64_C(0),	// S_ATOMIC_OR_X2_IMM_RTN_gfx10
    UINT64_C(3265724416), UINT64_C(0),	// S_ATOMIC_OR_X2_IMM_RTN_vi
    UINT64_C(18014398513619927040), UINT64_C(0),	// S_ATOMIC_OR_X2_IMM_gfx10
    UINT64_C(3265658880), UINT64_C(0),	// S_ATOMIC_OR_X2_IMM_vi
    UINT64_C(4138008576), UINT64_C(0),	// S_ATOMIC_OR_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3265740800), UINT64_C(0),	// S_ATOMIC_OR_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4137943040), UINT64_C(0),	// S_ATOMIC_OR_X2_SGPR_IMM_gfx10
    UINT64_C(3265675264), UINT64_C(0),	// S_ATOMIC_OR_X2_SGPR_IMM_gfx9
    UINT64_C(3265609728), UINT64_C(0),	// S_ATOMIC_OR_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4138008576), UINT64_C(0),	// S_ATOMIC_OR_X2_SGPR_RTN_gfx10
    UINT64_C(3265593344), UINT64_C(0),	// S_ATOMIC_OR_X2_SGPR_RTN_vi
    UINT64_C(3265544192), UINT64_C(0),	// S_ATOMIC_OR_X2_SGPR_alt_gfx9
    UINT64_C(4137943040), UINT64_C(0),	// S_ATOMIC_OR_X2_SGPR_gfx10
    UINT64_C(3265527808), UINT64_C(0),	// S_ATOMIC_OR_X2_SGPR_vi
    UINT64_C(18014398513610817536), UINT64_C(0),	// S_ATOMIC_SMAX_IMM_RTN_gfx10
    UINT64_C(3256549376), UINT64_C(0),	// S_ATOMIC_SMAX_IMM_RTN_vi
    UINT64_C(18014398513610752000), UINT64_C(0),	// S_ATOMIC_SMAX_IMM_gfx10
    UINT64_C(3256483840), UINT64_C(0),	// S_ATOMIC_SMAX_IMM_vi
    UINT64_C(4128833536), UINT64_C(0),	// S_ATOMIC_SMAX_SGPR_IMM_RTN_gfx10
    UINT64_C(3256565760), UINT64_C(0),	// S_ATOMIC_SMAX_SGPR_IMM_RTN_gfx9
    UINT64_C(4128768000), UINT64_C(0),	// S_ATOMIC_SMAX_SGPR_IMM_gfx10
    UINT64_C(3256500224), UINT64_C(0),	// S_ATOMIC_SMAX_SGPR_IMM_gfx9
    UINT64_C(3256434688), UINT64_C(0),	// S_ATOMIC_SMAX_SGPR_RTN_alt_gfx9
    UINT64_C(4128833536), UINT64_C(0),	// S_ATOMIC_SMAX_SGPR_RTN_gfx10
    UINT64_C(3256418304), UINT64_C(0),	// S_ATOMIC_SMAX_SGPR_RTN_vi
    UINT64_C(3256369152), UINT64_C(0),	// S_ATOMIC_SMAX_SGPR_alt_gfx9
    UINT64_C(4128768000), UINT64_C(0),	// S_ATOMIC_SMAX_SGPR_gfx10
    UINT64_C(3256352768), UINT64_C(0),	// S_ATOMIC_SMAX_SGPR_vi
    UINT64_C(18014398513619206144), UINT64_C(0),	// S_ATOMIC_SMAX_X2_IMM_RTN_gfx10
    UINT64_C(3264937984), UINT64_C(0),	// S_ATOMIC_SMAX_X2_IMM_RTN_vi
    UINT64_C(18014398513619140608), UINT64_C(0),	// S_ATOMIC_SMAX_X2_IMM_gfx10
    UINT64_C(3264872448), UINT64_C(0),	// S_ATOMIC_SMAX_X2_IMM_vi
    UINT64_C(4137222144), UINT64_C(0),	// S_ATOMIC_SMAX_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3264954368), UINT64_C(0),	// S_ATOMIC_SMAX_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4137156608), UINT64_C(0),	// S_ATOMIC_SMAX_X2_SGPR_IMM_gfx10
    UINT64_C(3264888832), UINT64_C(0),	// S_ATOMIC_SMAX_X2_SGPR_IMM_gfx9
    UINT64_C(3264823296), UINT64_C(0),	// S_ATOMIC_SMAX_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4137222144), UINT64_C(0),	// S_ATOMIC_SMAX_X2_SGPR_RTN_gfx10
    UINT64_C(3264806912), UINT64_C(0),	// S_ATOMIC_SMAX_X2_SGPR_RTN_vi
    UINT64_C(3264757760), UINT64_C(0),	// S_ATOMIC_SMAX_X2_SGPR_alt_gfx9
    UINT64_C(4137156608), UINT64_C(0),	// S_ATOMIC_SMAX_X2_SGPR_gfx10
    UINT64_C(3264741376), UINT64_C(0),	// S_ATOMIC_SMAX_X2_SGPR_vi
    UINT64_C(18014398513610293248), UINT64_C(0),	// S_ATOMIC_SMIN_IMM_RTN_gfx10
    UINT64_C(3256025088), UINT64_C(0),	// S_ATOMIC_SMIN_IMM_RTN_vi
    UINT64_C(18014398513610227712), UINT64_C(0),	// S_ATOMIC_SMIN_IMM_gfx10
    UINT64_C(3255959552), UINT64_C(0),	// S_ATOMIC_SMIN_IMM_vi
    UINT64_C(4128309248), UINT64_C(0),	// S_ATOMIC_SMIN_SGPR_IMM_RTN_gfx10
    UINT64_C(3256041472), UINT64_C(0),	// S_ATOMIC_SMIN_SGPR_IMM_RTN_gfx9
    UINT64_C(4128243712), UINT64_C(0),	// S_ATOMIC_SMIN_SGPR_IMM_gfx10
    UINT64_C(3255975936), UINT64_C(0),	// S_ATOMIC_SMIN_SGPR_IMM_gfx9
    UINT64_C(3255910400), UINT64_C(0),	// S_ATOMIC_SMIN_SGPR_RTN_alt_gfx9
    UINT64_C(4128309248), UINT64_C(0),	// S_ATOMIC_SMIN_SGPR_RTN_gfx10
    UINT64_C(3255894016), UINT64_C(0),	// S_ATOMIC_SMIN_SGPR_RTN_vi
    UINT64_C(3255844864), UINT64_C(0),	// S_ATOMIC_SMIN_SGPR_alt_gfx9
    UINT64_C(4128243712), UINT64_C(0),	// S_ATOMIC_SMIN_SGPR_gfx10
    UINT64_C(3255828480), UINT64_C(0),	// S_ATOMIC_SMIN_SGPR_vi
    UINT64_C(18014398513618681856), UINT64_C(0),	// S_ATOMIC_SMIN_X2_IMM_RTN_gfx10
    UINT64_C(3264413696), UINT64_C(0),	// S_ATOMIC_SMIN_X2_IMM_RTN_vi
    UINT64_C(18014398513618616320), UINT64_C(0),	// S_ATOMIC_SMIN_X2_IMM_gfx10
    UINT64_C(3264348160), UINT64_C(0),	// S_ATOMIC_SMIN_X2_IMM_vi
    UINT64_C(4136697856), UINT64_C(0),	// S_ATOMIC_SMIN_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3264430080), UINT64_C(0),	// S_ATOMIC_SMIN_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4136632320), UINT64_C(0),	// S_ATOMIC_SMIN_X2_SGPR_IMM_gfx10
    UINT64_C(3264364544), UINT64_C(0),	// S_ATOMIC_SMIN_X2_SGPR_IMM_gfx9
    UINT64_C(3264299008), UINT64_C(0),	// S_ATOMIC_SMIN_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4136697856), UINT64_C(0),	// S_ATOMIC_SMIN_X2_SGPR_RTN_gfx10
    UINT64_C(3264282624), UINT64_C(0),	// S_ATOMIC_SMIN_X2_SGPR_RTN_vi
    UINT64_C(3264233472), UINT64_C(0),	// S_ATOMIC_SMIN_X2_SGPR_alt_gfx9
    UINT64_C(4136632320), UINT64_C(0),	// S_ATOMIC_SMIN_X2_SGPR_gfx10
    UINT64_C(3264217088), UINT64_C(0),	// S_ATOMIC_SMIN_X2_SGPR_vi
    UINT64_C(18014398513610031104), UINT64_C(0),	// S_ATOMIC_SUB_IMM_RTN_gfx10
    UINT64_C(3255762944), UINT64_C(0),	// S_ATOMIC_SUB_IMM_RTN_vi
    UINT64_C(18014398513609965568), UINT64_C(0),	// S_ATOMIC_SUB_IMM_gfx10
    UINT64_C(3255697408), UINT64_C(0),	// S_ATOMIC_SUB_IMM_vi
    UINT64_C(4128047104), UINT64_C(0),	// S_ATOMIC_SUB_SGPR_IMM_RTN_gfx10
    UINT64_C(3255779328), UINT64_C(0),	// S_ATOMIC_SUB_SGPR_IMM_RTN_gfx9
    UINT64_C(4127981568), UINT64_C(0),	// S_ATOMIC_SUB_SGPR_IMM_gfx10
    UINT64_C(3255713792), UINT64_C(0),	// S_ATOMIC_SUB_SGPR_IMM_gfx9
    UINT64_C(3255648256), UINT64_C(0),	// S_ATOMIC_SUB_SGPR_RTN_alt_gfx9
    UINT64_C(4128047104), UINT64_C(0),	// S_ATOMIC_SUB_SGPR_RTN_gfx10
    UINT64_C(3255631872), UINT64_C(0),	// S_ATOMIC_SUB_SGPR_RTN_vi
    UINT64_C(3255582720), UINT64_C(0),	// S_ATOMIC_SUB_SGPR_alt_gfx9
    UINT64_C(4127981568), UINT64_C(0),	// S_ATOMIC_SUB_SGPR_gfx10
    UINT64_C(3255566336), UINT64_C(0),	// S_ATOMIC_SUB_SGPR_vi
    UINT64_C(18014398513618419712), UINT64_C(0),	// S_ATOMIC_SUB_X2_IMM_RTN_gfx10
    UINT64_C(3264151552), UINT64_C(0),	// S_ATOMIC_SUB_X2_IMM_RTN_vi
    UINT64_C(18014398513618354176), UINT64_C(0),	// S_ATOMIC_SUB_X2_IMM_gfx10
    UINT64_C(3264086016), UINT64_C(0),	// S_ATOMIC_SUB_X2_IMM_vi
    UINT64_C(4136435712), UINT64_C(0),	// S_ATOMIC_SUB_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3264167936), UINT64_C(0),	// S_ATOMIC_SUB_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4136370176), UINT64_C(0),	// S_ATOMIC_SUB_X2_SGPR_IMM_gfx10
    UINT64_C(3264102400), UINT64_C(0),	// S_ATOMIC_SUB_X2_SGPR_IMM_gfx9
    UINT64_C(3264036864), UINT64_C(0),	// S_ATOMIC_SUB_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4136435712), UINT64_C(0),	// S_ATOMIC_SUB_X2_SGPR_RTN_gfx10
    UINT64_C(3264020480), UINT64_C(0),	// S_ATOMIC_SUB_X2_SGPR_RTN_vi
    UINT64_C(3263971328), UINT64_C(0),	// S_ATOMIC_SUB_X2_SGPR_alt_gfx9
    UINT64_C(4136370176), UINT64_C(0),	// S_ATOMIC_SUB_X2_SGPR_gfx10
    UINT64_C(3263954944), UINT64_C(0),	// S_ATOMIC_SUB_X2_SGPR_vi
    UINT64_C(18014398513609244672), UINT64_C(0),	// S_ATOMIC_SWAP_IMM_RTN_gfx10
    UINT64_C(3254976512), UINT64_C(0),	// S_ATOMIC_SWAP_IMM_RTN_vi
    UINT64_C(18014398513609179136), UINT64_C(0),	// S_ATOMIC_SWAP_IMM_gfx10
    UINT64_C(3254910976), UINT64_C(0),	// S_ATOMIC_SWAP_IMM_vi
    UINT64_C(4127260672), UINT64_C(0),	// S_ATOMIC_SWAP_SGPR_IMM_RTN_gfx10
    UINT64_C(3254992896), UINT64_C(0),	// S_ATOMIC_SWAP_SGPR_IMM_RTN_gfx9
    UINT64_C(4127195136), UINT64_C(0),	// S_ATOMIC_SWAP_SGPR_IMM_gfx10
    UINT64_C(3254927360), UINT64_C(0),	// S_ATOMIC_SWAP_SGPR_IMM_gfx9
    UINT64_C(3254861824), UINT64_C(0),	// S_ATOMIC_SWAP_SGPR_RTN_alt_gfx9
    UINT64_C(4127260672), UINT64_C(0),	// S_ATOMIC_SWAP_SGPR_RTN_gfx10
    UINT64_C(3254845440), UINT64_C(0),	// S_ATOMIC_SWAP_SGPR_RTN_vi
    UINT64_C(3254796288), UINT64_C(0),	// S_ATOMIC_SWAP_SGPR_alt_gfx9
    UINT64_C(4127195136), UINT64_C(0),	// S_ATOMIC_SWAP_SGPR_gfx10
    UINT64_C(3254779904), UINT64_C(0),	// S_ATOMIC_SWAP_SGPR_vi
    UINT64_C(18014398513617633280), UINT64_C(0),	// S_ATOMIC_SWAP_X2_IMM_RTN_gfx10
    UINT64_C(3263365120), UINT64_C(0),	// S_ATOMIC_SWAP_X2_IMM_RTN_vi
    UINT64_C(18014398513617567744), UINT64_C(0),	// S_ATOMIC_SWAP_X2_IMM_gfx10
    UINT64_C(3263299584), UINT64_C(0),	// S_ATOMIC_SWAP_X2_IMM_vi
    UINT64_C(4135649280), UINT64_C(0),	// S_ATOMIC_SWAP_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3263381504), UINT64_C(0),	// S_ATOMIC_SWAP_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4135583744), UINT64_C(0),	// S_ATOMIC_SWAP_X2_SGPR_IMM_gfx10
    UINT64_C(3263315968), UINT64_C(0),	// S_ATOMIC_SWAP_X2_SGPR_IMM_gfx9
    UINT64_C(3263250432), UINT64_C(0),	// S_ATOMIC_SWAP_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4135649280), UINT64_C(0),	// S_ATOMIC_SWAP_X2_SGPR_RTN_gfx10
    UINT64_C(3263234048), UINT64_C(0),	// S_ATOMIC_SWAP_X2_SGPR_RTN_vi
    UINT64_C(3263184896), UINT64_C(0),	// S_ATOMIC_SWAP_X2_SGPR_alt_gfx9
    UINT64_C(4135583744), UINT64_C(0),	// S_ATOMIC_SWAP_X2_SGPR_gfx10
    UINT64_C(3263168512), UINT64_C(0),	// S_ATOMIC_SWAP_X2_SGPR_vi
    UINT64_C(18014398513611079680), UINT64_C(0),	// S_ATOMIC_UMAX_IMM_RTN_gfx10
    UINT64_C(3256811520), UINT64_C(0),	// S_ATOMIC_UMAX_IMM_RTN_vi
    UINT64_C(18014398513611014144), UINT64_C(0),	// S_ATOMIC_UMAX_IMM_gfx10
    UINT64_C(3256745984), UINT64_C(0),	// S_ATOMIC_UMAX_IMM_vi
    UINT64_C(4129095680), UINT64_C(0),	// S_ATOMIC_UMAX_SGPR_IMM_RTN_gfx10
    UINT64_C(3256827904), UINT64_C(0),	// S_ATOMIC_UMAX_SGPR_IMM_RTN_gfx9
    UINT64_C(4129030144), UINT64_C(0),	// S_ATOMIC_UMAX_SGPR_IMM_gfx10
    UINT64_C(3256762368), UINT64_C(0),	// S_ATOMIC_UMAX_SGPR_IMM_gfx9
    UINT64_C(3256696832), UINT64_C(0),	// S_ATOMIC_UMAX_SGPR_RTN_alt_gfx9
    UINT64_C(4129095680), UINT64_C(0),	// S_ATOMIC_UMAX_SGPR_RTN_gfx10
    UINT64_C(3256680448), UINT64_C(0),	// S_ATOMIC_UMAX_SGPR_RTN_vi
    UINT64_C(3256631296), UINT64_C(0),	// S_ATOMIC_UMAX_SGPR_alt_gfx9
    UINT64_C(4129030144), UINT64_C(0),	// S_ATOMIC_UMAX_SGPR_gfx10
    UINT64_C(3256614912), UINT64_C(0),	// S_ATOMIC_UMAX_SGPR_vi
    UINT64_C(18014398513619468288), UINT64_C(0),	// S_ATOMIC_UMAX_X2_IMM_RTN_gfx10
    UINT64_C(3265200128), UINT64_C(0),	// S_ATOMIC_UMAX_X2_IMM_RTN_vi
    UINT64_C(18014398513619402752), UINT64_C(0),	// S_ATOMIC_UMAX_X2_IMM_gfx10
    UINT64_C(3265134592), UINT64_C(0),	// S_ATOMIC_UMAX_X2_IMM_vi
    UINT64_C(4137484288), UINT64_C(0),	// S_ATOMIC_UMAX_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3265216512), UINT64_C(0),	// S_ATOMIC_UMAX_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4137418752), UINT64_C(0),	// S_ATOMIC_UMAX_X2_SGPR_IMM_gfx10
    UINT64_C(3265150976), UINT64_C(0),	// S_ATOMIC_UMAX_X2_SGPR_IMM_gfx9
    UINT64_C(3265085440), UINT64_C(0),	// S_ATOMIC_UMAX_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4137484288), UINT64_C(0),	// S_ATOMIC_UMAX_X2_SGPR_RTN_gfx10
    UINT64_C(3265069056), UINT64_C(0),	// S_ATOMIC_UMAX_X2_SGPR_RTN_vi
    UINT64_C(3265019904), UINT64_C(0),	// S_ATOMIC_UMAX_X2_SGPR_alt_gfx9
    UINT64_C(4137418752), UINT64_C(0),	// S_ATOMIC_UMAX_X2_SGPR_gfx10
    UINT64_C(3265003520), UINT64_C(0),	// S_ATOMIC_UMAX_X2_SGPR_vi
    UINT64_C(18014398513610555392), UINT64_C(0),	// S_ATOMIC_UMIN_IMM_RTN_gfx10
    UINT64_C(3256287232), UINT64_C(0),	// S_ATOMIC_UMIN_IMM_RTN_vi
    UINT64_C(18014398513610489856), UINT64_C(0),	// S_ATOMIC_UMIN_IMM_gfx10
    UINT64_C(3256221696), UINT64_C(0),	// S_ATOMIC_UMIN_IMM_vi
    UINT64_C(4128571392), UINT64_C(0),	// S_ATOMIC_UMIN_SGPR_IMM_RTN_gfx10
    UINT64_C(3256303616), UINT64_C(0),	// S_ATOMIC_UMIN_SGPR_IMM_RTN_gfx9
    UINT64_C(4128505856), UINT64_C(0),	// S_ATOMIC_UMIN_SGPR_IMM_gfx10
    UINT64_C(3256238080), UINT64_C(0),	// S_ATOMIC_UMIN_SGPR_IMM_gfx9
    UINT64_C(3256172544), UINT64_C(0),	// S_ATOMIC_UMIN_SGPR_RTN_alt_gfx9
    UINT64_C(4128571392), UINT64_C(0),	// S_ATOMIC_UMIN_SGPR_RTN_gfx10
    UINT64_C(3256156160), UINT64_C(0),	// S_ATOMIC_UMIN_SGPR_RTN_vi
    UINT64_C(3256107008), UINT64_C(0),	// S_ATOMIC_UMIN_SGPR_alt_gfx9
    UINT64_C(4128505856), UINT64_C(0),	// S_ATOMIC_UMIN_SGPR_gfx10
    UINT64_C(3256090624), UINT64_C(0),	// S_ATOMIC_UMIN_SGPR_vi
    UINT64_C(18014398513618944000), UINT64_C(0),	// S_ATOMIC_UMIN_X2_IMM_RTN_gfx10
    UINT64_C(3264675840), UINT64_C(0),	// S_ATOMIC_UMIN_X2_IMM_RTN_vi
    UINT64_C(18014398513618878464), UINT64_C(0),	// S_ATOMIC_UMIN_X2_IMM_gfx10
    UINT64_C(3264610304), UINT64_C(0),	// S_ATOMIC_UMIN_X2_IMM_vi
    UINT64_C(4136960000), UINT64_C(0),	// S_ATOMIC_UMIN_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3264692224), UINT64_C(0),	// S_ATOMIC_UMIN_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4136894464), UINT64_C(0),	// S_ATOMIC_UMIN_X2_SGPR_IMM_gfx10
    UINT64_C(3264626688), UINT64_C(0),	// S_ATOMIC_UMIN_X2_SGPR_IMM_gfx9
    UINT64_C(3264561152), UINT64_C(0),	// S_ATOMIC_UMIN_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4136960000), UINT64_C(0),	// S_ATOMIC_UMIN_X2_SGPR_RTN_gfx10
    UINT64_C(3264544768), UINT64_C(0),	// S_ATOMIC_UMIN_X2_SGPR_RTN_vi
    UINT64_C(3264495616), UINT64_C(0),	// S_ATOMIC_UMIN_X2_SGPR_alt_gfx9
    UINT64_C(4136894464), UINT64_C(0),	// S_ATOMIC_UMIN_X2_SGPR_gfx10
    UINT64_C(3264479232), UINT64_C(0),	// S_ATOMIC_UMIN_X2_SGPR_vi
    UINT64_C(18014398513611866112), UINT64_C(0),	// S_ATOMIC_XOR_IMM_RTN_gfx10
    UINT64_C(3257597952), UINT64_C(0),	// S_ATOMIC_XOR_IMM_RTN_vi
    UINT64_C(18014398513611800576), UINT64_C(0),	// S_ATOMIC_XOR_IMM_gfx10
    UINT64_C(3257532416), UINT64_C(0),	// S_ATOMIC_XOR_IMM_vi
    UINT64_C(4129882112), UINT64_C(0),	// S_ATOMIC_XOR_SGPR_IMM_RTN_gfx10
    UINT64_C(3257614336), UINT64_C(0),	// S_ATOMIC_XOR_SGPR_IMM_RTN_gfx9
    UINT64_C(4129816576), UINT64_C(0),	// S_ATOMIC_XOR_SGPR_IMM_gfx10
    UINT64_C(3257548800), UINT64_C(0),	// S_ATOMIC_XOR_SGPR_IMM_gfx9
    UINT64_C(3257483264), UINT64_C(0),	// S_ATOMIC_XOR_SGPR_RTN_alt_gfx9
    UINT64_C(4129882112), UINT64_C(0),	// S_ATOMIC_XOR_SGPR_RTN_gfx10
    UINT64_C(3257466880), UINT64_C(0),	// S_ATOMIC_XOR_SGPR_RTN_vi
    UINT64_C(3257417728), UINT64_C(0),	// S_ATOMIC_XOR_SGPR_alt_gfx9
    UINT64_C(4129816576), UINT64_C(0),	// S_ATOMIC_XOR_SGPR_gfx10
    UINT64_C(3257401344), UINT64_C(0),	// S_ATOMIC_XOR_SGPR_vi
    UINT64_C(18014398513620254720), UINT64_C(0),	// S_ATOMIC_XOR_X2_IMM_RTN_gfx10
    UINT64_C(3265986560), UINT64_C(0),	// S_ATOMIC_XOR_X2_IMM_RTN_vi
    UINT64_C(18014398513620189184), UINT64_C(0),	// S_ATOMIC_XOR_X2_IMM_gfx10
    UINT64_C(3265921024), UINT64_C(0),	// S_ATOMIC_XOR_X2_IMM_vi
    UINT64_C(4138270720), UINT64_C(0),	// S_ATOMIC_XOR_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3266002944), UINT64_C(0),	// S_ATOMIC_XOR_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4138205184), UINT64_C(0),	// S_ATOMIC_XOR_X2_SGPR_IMM_gfx10
    UINT64_C(3265937408), UINT64_C(0),	// S_ATOMIC_XOR_X2_SGPR_IMM_gfx9
    UINT64_C(3265871872), UINT64_C(0),	// S_ATOMIC_XOR_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4138270720), UINT64_C(0),	// S_ATOMIC_XOR_X2_SGPR_RTN_gfx10
    UINT64_C(3265855488), UINT64_C(0),	// S_ATOMIC_XOR_X2_SGPR_RTN_vi
    UINT64_C(3265806336), UINT64_C(0),	// S_ATOMIC_XOR_X2_SGPR_alt_gfx9
    UINT64_C(4138205184), UINT64_C(0),	// S_ATOMIC_XOR_X2_SGPR_gfx10
    UINT64_C(3265789952), UINT64_C(0),	// S_ATOMIC_XOR_X2_SGPR_vi
    UINT64_C(3196080384), UINT64_C(0),	// S_BARRIER_INIT_IMM_gfx12
    UINT64_C(3196080509), UINT64_C(0),	// S_BARRIER_INIT_M0_gfx12
    UINT64_C(3196080640), UINT64_C(0),	// S_BARRIER_JOIN_IMM_gfx12
    UINT64_C(3196080765), UINT64_C(0),	// S_BARRIER_JOIN_M0_gfx12
    UINT64_C(3214213120), UINT64_C(0),	// S_BARRIER_LEAVE_gfx12
    UINT64_C(3196079616), UINT64_C(0),	// S_BARRIER_SIGNAL_IMM_gfx12
    UINT64_C(3196079872), UINT64_C(0),	// S_BARRIER_SIGNAL_ISFIRST_IMM_gfx12
    UINT64_C(3196079997), UINT64_C(0),	// S_BARRIER_SIGNAL_ISFIRST_M0_gfx12
    UINT64_C(3196079741), UINT64_C(0),	// S_BARRIER_SIGNAL_M0_gfx12
    UINT64_C(3214147584), UINT64_C(0),	// S_BARRIER_WAIT_gfx12
    UINT64_C(3213492224), UINT64_C(0),	// S_BARRIER_gfx10
    UINT64_C(3216834560), UINT64_C(0),	// S_BARRIER_gfx11
    UINT64_C(3213492224), UINT64_C(0),	// S_BARRIER_gfx6_gfx7
    UINT64_C(3213492224), UINT64_C(0),	// S_BARRIER_vi
    UINT64_C(3196062976), UINT64_C(0),	// S_BCNT0_I32_B32_gfx10
    UINT64_C(3196065280), UINT64_C(0),	// S_BCNT0_I32_B32_gfx11
    UINT64_C(3196065280), UINT64_C(0),	// S_BCNT0_I32_B32_gfx12
    UINT64_C(3196062976), UINT64_C(0),	// S_BCNT0_I32_B32_gfx6_gfx7
    UINT64_C(3196062208), UINT64_C(0),	// S_BCNT0_I32_B32_vi
    UINT64_C(3196063232), UINT64_C(0),	// S_BCNT0_I32_B64_gfx10
    UINT64_C(3196065536), UINT64_C(0),	// S_BCNT0_I32_B64_gfx11
    UINT64_C(3196065536), UINT64_C(0),	// S_BCNT0_I32_B64_gfx12
    UINT64_C(3196063232), UINT64_C(0),	// S_BCNT0_I32_B64_gfx6_gfx7
    UINT64_C(3196062464), UINT64_C(0),	// S_BCNT0_I32_B64_vi
    UINT64_C(3196063488), UINT64_C(0),	// S_BCNT1_I32_B32_gfx10
    UINT64_C(3196065792), UINT64_C(0),	// S_BCNT1_I32_B32_gfx11
    UINT64_C(3196065792), UINT64_C(0),	// S_BCNT1_I32_B32_gfx12
    UINT64_C(3196063488), UINT64_C(0),	// S_BCNT1_I32_B32_gfx6_gfx7
    UINT64_C(3196062720), UINT64_C(0),	// S_BCNT1_I32_B32_vi
    UINT64_C(3196063744), UINT64_C(0),	// S_BCNT1_I32_B64_gfx10
    UINT64_C(3196066048), UINT64_C(0),	// S_BCNT1_I32_B64_gfx11
    UINT64_C(3196066048), UINT64_C(0),	// S_BCNT1_I32_B64_gfx12
    UINT64_C(3196063744), UINT64_C(0),	// S_BCNT1_I32_B64_gfx6_gfx7
    UINT64_C(3196062976), UINT64_C(0),	// S_BCNT1_I32_B64_vi
    UINT64_C(2483027968), UINT64_C(0),	// S_BFE_I32_gfx10
    UINT64_C(2474639360), UINT64_C(0),	// S_BFE_I32_gfx11
    UINT64_C(2474639360), UINT64_C(0),	// S_BFE_I32_gfx12
    UINT64_C(2483027968), UINT64_C(0),	// S_BFE_I32_gfx6_gfx7
    UINT64_C(2466250752), UINT64_C(0),	// S_BFE_I32_vi
    UINT64_C(2499805184), UINT64_C(0),	// S_BFE_I64_gfx10
    UINT64_C(2491416576), UINT64_C(0),	// S_BFE_I64_gfx11
    UINT64_C(2491416576), UINT64_C(0),	// S_BFE_I64_gfx12
    UINT64_C(2499805184), UINT64_C(0),	// S_BFE_I64_gfx6_gfx7
    UINT64_C(2483027968), UINT64_C(0),	// S_BFE_I64_vi
    UINT64_C(2474639360), UINT64_C(0),	// S_BFE_U32_gfx10
    UINT64_C(2466250752), UINT64_C(0),	// S_BFE_U32_gfx11
    UINT64_C(2466250752), UINT64_C(0),	// S_BFE_U32_gfx12
    UINT64_C(2474639360), UINT64_C(0),	// S_BFE_U32_gfx6_gfx7
    UINT64_C(2457862144), UINT64_C(0),	// S_BFE_U32_vi
    UINT64_C(2491416576), UINT64_C(0),	// S_BFE_U64_gfx10
    UINT64_C(2483027968), UINT64_C(0),	// S_BFE_U64_gfx11
    UINT64_C(2483027968), UINT64_C(0),	// S_BFE_U64_gfx12
    UINT64_C(2491416576), UINT64_C(0),	// S_BFE_U64_gfx6_gfx7
    UINT64_C(2474639360), UINT64_C(0),	// S_BFE_U64_vi
    UINT64_C(2449473536), UINT64_C(0),	// S_BFM_B32_gfx10
    UINT64_C(2499805184), UINT64_C(0),	// S_BFM_B32_gfx11
    UINT64_C(2499805184), UINT64_C(0),	// S_BFM_B32_gfx12
    UINT64_C(2449473536), UINT64_C(0),	// S_BFM_B32_gfx6_gfx7
    UINT64_C(2432696320), UINT64_C(0),	// S_BFM_B32_vi
    UINT64_C(2457862144), UINT64_C(0),	// S_BFM_B64_gfx10
    UINT64_C(2508193792), UINT64_C(0),	// S_BFM_B64_gfx11
    UINT64_C(2508193792), UINT64_C(0),	// S_BFM_B64_gfx12
    UINT64_C(2457862144), UINT64_C(0),	// S_BFM_B64_gfx6_gfx7
    UINT64_C(2441084928), UINT64_C(0),	// S_BFM_B64_vi
    UINT64_C(3205234688), UINT64_C(0),	// S_BITCMP0_B32_gfx10
    UINT64_C(3205234688), UINT64_C(0),	// S_BITCMP0_B32_gfx11
    UINT64_C(3205234688), UINT64_C(0),	// S_BITCMP0_B32_gfx12
    UINT64_C(3205234688), UINT64_C(0),	// S_BITCMP0_B32_gfx6_gfx7
    UINT64_C(3205234688), UINT64_C(0),	// S_BITCMP0_B32_vi
    UINT64_C(3205365760), UINT64_C(0),	// S_BITCMP0_B64_gfx10
    UINT64_C(3205365760), UINT64_C(0),	// S_BITCMP0_B64_gfx11
    UINT64_C(3205365760), UINT64_C(0),	// S_BITCMP0_B64_gfx12
    UINT64_C(3205365760), UINT64_C(0),	// S_BITCMP0_B64_gfx6_gfx7
    UINT64_C(3205365760), UINT64_C(0),	// S_BITCMP0_B64_vi
    UINT64_C(3205300224), UINT64_C(0),	// S_BITCMP1_B32_gfx10
    UINT64_C(3205300224), UINT64_C(0),	// S_BITCMP1_B32_gfx11
    UINT64_C(3205300224), UINT64_C(0),	// S_BITCMP1_B32_gfx12
    UINT64_C(3205300224), UINT64_C(0),	// S_BITCMP1_B32_gfx6_gfx7
    UINT64_C(3205300224), UINT64_C(0),	// S_BITCMP1_B32_vi
    UINT64_C(3205431296), UINT64_C(0),	// S_BITCMP1_B64_gfx10
    UINT64_C(3205431296), UINT64_C(0),	// S_BITCMP1_B64_gfx11
    UINT64_C(3205431296), UINT64_C(0),	// S_BITCMP1_B64_gfx12
    UINT64_C(3205431296), UINT64_C(0),	// S_BITCMP1_B64_gfx6_gfx7
    UINT64_C(3205431296), UINT64_C(0),	// S_BITCMP1_B64_vi
    UINT64_C(3196074752), UINT64_C(0),	// S_BITREPLICATE_B64_B32_gfx10
    UINT64_C(3196064768), UINT64_C(0),	// S_BITREPLICATE_B64_B32_gfx11
    UINT64_C(3196064768), UINT64_C(0),	// S_BITREPLICATE_B64_B32_gfx12
    UINT64_C(3196073728), UINT64_C(0),	// S_BITREPLICATE_B64_B32_vi
    UINT64_C(3196066560), UINT64_C(0),	// S_BITSET0_B32_gfx10
    UINT64_C(3196063744), UINT64_C(0),	// S_BITSET0_B32_gfx11
    UINT64_C(3196063744), UINT64_C(0),	// S_BITSET0_B32_gfx12
    UINT64_C(3196066560), UINT64_C(0),	// S_BITSET0_B32_gfx6_gfx7
    UINT64_C(3196065792), UINT64_C(0),	// S_BITSET0_B32_vi
    UINT64_C(3196066816), UINT64_C(0),	// S_BITSET0_B64_gfx10
    UINT64_C(3196064000), UINT64_C(0),	// S_BITSET0_B64_gfx11
    UINT64_C(3196064000), UINT64_C(0),	// S_BITSET0_B64_gfx12
    UINT64_C(3196066816), UINT64_C(0),	// S_BITSET0_B64_gfx6_gfx7
    UINT64_C(3196066048), UINT64_C(0),	// S_BITSET0_B64_vi
    UINT64_C(3196067072), UINT64_C(0),	// S_BITSET1_B32_gfx10
    UINT64_C(3196064256), UINT64_C(0),	// S_BITSET1_B32_gfx11
    UINT64_C(3196064256), UINT64_C(0),	// S_BITSET1_B32_gfx12
    UINT64_C(3196067072), UINT64_C(0),	// S_BITSET1_B32_gfx6_gfx7
    UINT64_C(3196066304), UINT64_C(0),	// S_BITSET1_B32_vi
    UINT64_C(3196067328), UINT64_C(0),	// S_BITSET1_B64_gfx10
    UINT64_C(3196064512), UINT64_C(0),	// S_BITSET1_B64_gfx11
    UINT64_C(3196064512), UINT64_C(0),	// S_BITSET1_B64_gfx12
    UINT64_C(3196067328), UINT64_C(0),	// S_BITSET1_B64_gfx6_gfx7
    UINT64_C(3196066560), UINT64_C(0),	// S_BITSET1_B64_vi
    UINT64_C(3212967936), UINT64_C(0),	// S_BRANCH_gfx10
    UINT64_C(3214934016), UINT64_C(0),	// S_BRANCH_gfx11
    UINT64_C(3214934016), UINT64_C(0),	// S_BRANCH_gfx12
    UINT64_C(3212967936), UINT64_C(0),	// S_BRANCH_gfx6_gfx7
    UINT64_C(13799029261476167680), UINT64_C(0),	// S_BRANCH_pad_s_nop_gfx10
    UINT64_C(13799029261478133760), UINT64_C(0),	// S_BRANCH_pad_s_nop_gfx11
    UINT64_C(13799029261478133760), UINT64_C(0),	// S_BRANCH_pad_s_nop_gfx12
    UINT64_C(13799029261476167680), UINT64_C(0),	// S_BRANCH_pad_s_nop_gfx6_gfx7
    UINT64_C(13799029261476167680), UINT64_C(0),	// S_BRANCH_pad_s_nop_vi
    UINT64_C(3212967936), UINT64_C(0),	// S_BRANCH_vi
    UINT64_C(3196062464), UINT64_C(0),	// S_BREV_B32_gfx10
    UINT64_C(3196060672), UINT64_C(0),	// S_BREV_B32_gfx11
    UINT64_C(3196060672), UINT64_C(0),	// S_BREV_B32_gfx12
    UINT64_C(3196062464), UINT64_C(0),	// S_BREV_B32_gfx6_gfx7
    UINT64_C(3196061696), UINT64_C(0),	// S_BREV_B32_vi
    UINT64_C(3196062720), UINT64_C(0),	// S_BREV_B64_gfx10
    UINT64_C(3196060928), UINT64_C(0),	// S_BREV_B64_gfx11
    UINT64_C(3196060928), UINT64_C(0),	// S_BREV_B64_gfx12
    UINT64_C(3196062720), UINT64_C(0),	// S_BREV_B64_gfx6_gfx7
    UINT64_C(3196061952), UINT64_C(0),	// S_BREV_B64_vi
    UINT64_C(18014398513592991744), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_IMM_RTN_gfx10
    UINT64_C(3238723584), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_IMM_RTN_vi
    UINT64_C(18014398513592926208), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_IMM_gfx10
    UINT64_C(3238658048), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_IMM_vi
    UINT64_C(4111007744), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_SGPR_IMM_RTN_gfx10
    UINT64_C(3238739968), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_SGPR_IMM_RTN_gfx9
    UINT64_C(4110942208), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_SGPR_IMM_gfx10
    UINT64_C(3238674432), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_SGPR_IMM_gfx9
    UINT64_C(3238608896), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_SGPR_RTN_alt_gfx9
    UINT64_C(4111007744), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_SGPR_RTN_gfx10
    UINT64_C(3238592512), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_SGPR_RTN_vi
    UINT64_C(3238543360), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_SGPR_alt_gfx9
    UINT64_C(4110942208), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_SGPR_gfx10
    UINT64_C(3238526976), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_SGPR_vi
    UINT64_C(18014398513601380352), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_X2_IMM_RTN_gfx10
    UINT64_C(3247112192), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_X2_IMM_RTN_vi
    UINT64_C(18014398513601314816), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_X2_IMM_gfx10
    UINT64_C(3247046656), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_X2_IMM_vi
    UINT64_C(4119396352), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3247128576), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4119330816), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_X2_SGPR_IMM_gfx10
    UINT64_C(3247063040), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_X2_SGPR_IMM_gfx9
    UINT64_C(3246997504), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4119396352), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_X2_SGPR_RTN_gfx10
    UINT64_C(3246981120), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_X2_SGPR_RTN_vi
    UINT64_C(3246931968), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_X2_SGPR_alt_gfx9
    UINT64_C(4119330816), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_X2_SGPR_gfx10
    UINT64_C(3246915584), UINT64_C(0),	// S_BUFFER_ATOMIC_ADD_X2_SGPR_vi
    UINT64_C(18014398513594564608), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_IMM_RTN_gfx10
    UINT64_C(3240296448), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_IMM_RTN_vi
    UINT64_C(18014398513594499072), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_IMM_gfx10
    UINT64_C(3240230912), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_IMM_vi
    UINT64_C(4112580608), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_SGPR_IMM_RTN_gfx10
    UINT64_C(3240312832), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_SGPR_IMM_RTN_gfx9
    UINT64_C(4112515072), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_SGPR_IMM_gfx10
    UINT64_C(3240247296), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_SGPR_IMM_gfx9
    UINT64_C(3240181760), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_SGPR_RTN_alt_gfx9
    UINT64_C(4112580608), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_SGPR_RTN_gfx10
    UINT64_C(3240165376), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_SGPR_RTN_vi
    UINT64_C(3240116224), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_SGPR_alt_gfx9
    UINT64_C(4112515072), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_SGPR_gfx10
    UINT64_C(3240099840), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_SGPR_vi
    UINT64_C(18014398513602953216), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_X2_IMM_RTN_gfx10
    UINT64_C(3248685056), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_X2_IMM_RTN_vi
    UINT64_C(18014398513602887680), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_X2_IMM_gfx10
    UINT64_C(3248619520), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_X2_IMM_vi
    UINT64_C(4120969216), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3248701440), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4120903680), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_X2_SGPR_IMM_gfx10
    UINT64_C(3248635904), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_X2_SGPR_IMM_gfx9
    UINT64_C(3248570368), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4120969216), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_X2_SGPR_RTN_gfx10
    UINT64_C(3248553984), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_X2_SGPR_RTN_vi
    UINT64_C(3248504832), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_X2_SGPR_alt_gfx9
    UINT64_C(4120903680), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_X2_SGPR_gfx10
    UINT64_C(3248488448), UINT64_C(0),	// S_BUFFER_ATOMIC_AND_X2_SGPR_vi
    UINT64_C(18014398513592729600), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_IMM_RTN_gfx10
    UINT64_C(3238461440), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_IMM_RTN_vi
    UINT64_C(18014398513592664064), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_IMM_gfx10
    UINT64_C(3238395904), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_IMM_vi
    UINT64_C(4110745600), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_SGPR_IMM_RTN_gfx10
    UINT64_C(3238477824), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_SGPR_IMM_RTN_gfx9
    UINT64_C(4110680064), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_SGPR_IMM_gfx10
    UINT64_C(3238412288), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_SGPR_IMM_gfx9
    UINT64_C(3238346752), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_SGPR_RTN_alt_gfx9
    UINT64_C(4110745600), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_SGPR_RTN_gfx10
    UINT64_C(3238330368), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_SGPR_RTN_vi
    UINT64_C(3238281216), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_SGPR_alt_gfx9
    UINT64_C(4110680064), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_SGPR_gfx10
    UINT64_C(3238264832), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_SGPR_vi
    UINT64_C(18014398513601118208), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_RTN_gfx10
    UINT64_C(3246850048), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_RTN_vi
    UINT64_C(18014398513601052672), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_gfx10
    UINT64_C(3246784512), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_vi
    UINT64_C(4119134208), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3246866432), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4119068672), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_IMM_gfx10
    UINT64_C(3246800896), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_IMM_gfx9
    UINT64_C(3246735360), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4119134208), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_RTN_gfx10
    UINT64_C(3246718976), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_RTN_vi
    UINT64_C(3246669824), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_alt_gfx9
    UINT64_C(4119068672), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_gfx10
    UINT64_C(3246653440), UINT64_C(0),	// S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_vi
    UINT64_C(18014398513595613184), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_IMM_RTN_gfx10
    UINT64_C(3241345024), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_IMM_RTN_vi
    UINT64_C(18014398513595547648), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_IMM_gfx10
    UINT64_C(3241279488), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_IMM_vi
    UINT64_C(4113629184), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_SGPR_IMM_RTN_gfx10
    UINT64_C(3241361408), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_SGPR_IMM_RTN_gfx9
    UINT64_C(4113563648), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_SGPR_IMM_gfx10
    UINT64_C(3241295872), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_SGPR_IMM_gfx9
    UINT64_C(3241230336), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_SGPR_RTN_alt_gfx9
    UINT64_C(4113629184), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_SGPR_RTN_gfx10
    UINT64_C(3241213952), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_SGPR_RTN_vi
    UINT64_C(3241164800), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_SGPR_alt_gfx9
    UINT64_C(4113563648), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_SGPR_gfx10
    UINT64_C(3241148416), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_SGPR_vi
    UINT64_C(18014398513604001792), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_X2_IMM_RTN_gfx10
    UINT64_C(3249733632), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_X2_IMM_RTN_vi
    UINT64_C(18014398513603936256), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_X2_IMM_gfx10
    UINT64_C(3249668096), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_X2_IMM_vi
    UINT64_C(4122017792), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3249750016), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4121952256), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_X2_SGPR_IMM_gfx10
    UINT64_C(3249684480), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_X2_SGPR_IMM_gfx9
    UINT64_C(3249618944), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4122017792), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_X2_SGPR_RTN_gfx10
    UINT64_C(3249602560), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_X2_SGPR_RTN_vi
    UINT64_C(3249553408), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_X2_SGPR_alt_gfx9
    UINT64_C(4121952256), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_X2_SGPR_gfx10
    UINT64_C(3249537024), UINT64_C(0),	// S_BUFFER_ATOMIC_DEC_X2_SGPR_vi
    UINT64_C(18014398513595351040), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_IMM_RTN_gfx10
    UINT64_C(3241082880), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_IMM_RTN_vi
    UINT64_C(18014398513595285504), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_IMM_gfx10
    UINT64_C(3241017344), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_IMM_vi
    UINT64_C(4113367040), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_SGPR_IMM_RTN_gfx10
    UINT64_C(3241099264), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_SGPR_IMM_RTN_gfx9
    UINT64_C(4113301504), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_SGPR_IMM_gfx10
    UINT64_C(3241033728), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_SGPR_IMM_gfx9
    UINT64_C(3240968192), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_SGPR_RTN_alt_gfx9
    UINT64_C(4113367040), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_SGPR_RTN_gfx10
    UINT64_C(3240951808), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_SGPR_RTN_vi
    UINT64_C(3240902656), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_SGPR_alt_gfx9
    UINT64_C(4113301504), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_SGPR_gfx10
    UINT64_C(3240886272), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_SGPR_vi
    UINT64_C(18014398513603739648), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_X2_IMM_RTN_gfx10
    UINT64_C(3249471488), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_X2_IMM_RTN_vi
    UINT64_C(18014398513603674112), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_X2_IMM_gfx10
    UINT64_C(3249405952), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_X2_IMM_vi
    UINT64_C(4121755648), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3249487872), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4121690112), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_X2_SGPR_IMM_gfx10
    UINT64_C(3249422336), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_X2_SGPR_IMM_gfx9
    UINT64_C(3249356800), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4121755648), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_X2_SGPR_RTN_gfx10
    UINT64_C(3249340416), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_X2_SGPR_RTN_vi
    UINT64_C(3249291264), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_X2_SGPR_alt_gfx9
    UINT64_C(4121690112), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_X2_SGPR_gfx10
    UINT64_C(3249274880), UINT64_C(0),	// S_BUFFER_ATOMIC_INC_X2_SGPR_vi
    UINT64_C(18014398513594826752), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_IMM_RTN_gfx10
    UINT64_C(3240558592), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_IMM_RTN_vi
    UINT64_C(18014398513594761216), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_IMM_gfx10
    UINT64_C(3240493056), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_IMM_vi
    UINT64_C(4112842752), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_SGPR_IMM_RTN_gfx10
    UINT64_C(3240574976), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_SGPR_IMM_RTN_gfx9
    UINT64_C(4112777216), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_SGPR_IMM_gfx10
    UINT64_C(3240509440), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_SGPR_IMM_gfx9
    UINT64_C(3240443904), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_SGPR_RTN_alt_gfx9
    UINT64_C(4112842752), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_SGPR_RTN_gfx10
    UINT64_C(3240427520), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_SGPR_RTN_vi
    UINT64_C(3240378368), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_SGPR_alt_gfx9
    UINT64_C(4112777216), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_SGPR_gfx10
    UINT64_C(3240361984), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_SGPR_vi
    UINT64_C(18014398513603215360), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_X2_IMM_RTN_gfx10
    UINT64_C(3248947200), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_X2_IMM_RTN_vi
    UINT64_C(18014398513603149824), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_X2_IMM_gfx10
    UINT64_C(3248881664), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_X2_IMM_vi
    UINT64_C(4121231360), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3248963584), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4121165824), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_X2_SGPR_IMM_gfx10
    UINT64_C(3248898048), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_X2_SGPR_IMM_gfx9
    UINT64_C(3248832512), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4121231360), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_X2_SGPR_RTN_gfx10
    UINT64_C(3248816128), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_X2_SGPR_RTN_vi
    UINT64_C(3248766976), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_X2_SGPR_alt_gfx9
    UINT64_C(4121165824), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_X2_SGPR_gfx10
    UINT64_C(3248750592), UINT64_C(0),	// S_BUFFER_ATOMIC_OR_X2_SGPR_vi
    UINT64_C(18014398513594040320), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_IMM_RTN_gfx10
    UINT64_C(3239772160), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_IMM_RTN_vi
    UINT64_C(18014398513593974784), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_IMM_gfx10
    UINT64_C(3239706624), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_IMM_vi
    UINT64_C(4112056320), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_SGPR_IMM_RTN_gfx10
    UINT64_C(3239788544), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_SGPR_IMM_RTN_gfx9
    UINT64_C(4111990784), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_SGPR_IMM_gfx10
    UINT64_C(3239723008), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_SGPR_IMM_gfx9
    UINT64_C(3239657472), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_SGPR_RTN_alt_gfx9
    UINT64_C(4112056320), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_SGPR_RTN_gfx10
    UINT64_C(3239641088), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_SGPR_RTN_vi
    UINT64_C(3239591936), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_SGPR_alt_gfx9
    UINT64_C(4111990784), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_SGPR_gfx10
    UINT64_C(3239575552), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_SGPR_vi
    UINT64_C(18014398513602428928), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_X2_IMM_RTN_gfx10
    UINT64_C(3248160768), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_X2_IMM_RTN_vi
    UINT64_C(18014398513602363392), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_X2_IMM_gfx10
    UINT64_C(3248095232), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_X2_IMM_vi
    UINT64_C(4120444928), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3248177152), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4120379392), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_X2_SGPR_IMM_gfx10
    UINT64_C(3248111616), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_X2_SGPR_IMM_gfx9
    UINT64_C(3248046080), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4120444928), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_X2_SGPR_RTN_gfx10
    UINT64_C(3248029696), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_X2_SGPR_RTN_vi
    UINT64_C(3247980544), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_X2_SGPR_alt_gfx9
    UINT64_C(4120379392), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_X2_SGPR_gfx10
    UINT64_C(3247964160), UINT64_C(0),	// S_BUFFER_ATOMIC_SMAX_X2_SGPR_vi
    UINT64_C(18014398513593516032), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_IMM_RTN_gfx10
    UINT64_C(3239247872), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_IMM_RTN_vi
    UINT64_C(18014398513593450496), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_IMM_gfx10
    UINT64_C(3239182336), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_IMM_vi
    UINT64_C(4111532032), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_SGPR_IMM_RTN_gfx10
    UINT64_C(3239264256), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_SGPR_IMM_RTN_gfx9
    UINT64_C(4111466496), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_SGPR_IMM_gfx10
    UINT64_C(3239198720), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_SGPR_IMM_gfx9
    UINT64_C(3239133184), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_SGPR_RTN_alt_gfx9
    UINT64_C(4111532032), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_SGPR_RTN_gfx10
    UINT64_C(3239116800), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_SGPR_RTN_vi
    UINT64_C(3239067648), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_SGPR_alt_gfx9
    UINT64_C(4111466496), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_SGPR_gfx10
    UINT64_C(3239051264), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_SGPR_vi
    UINT64_C(18014398513601904640), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_X2_IMM_RTN_gfx10
    UINT64_C(3247636480), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_X2_IMM_RTN_vi
    UINT64_C(18014398513601839104), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_X2_IMM_gfx10
    UINT64_C(3247570944), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_X2_IMM_vi
    UINT64_C(4119920640), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3247652864), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4119855104), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_X2_SGPR_IMM_gfx10
    UINT64_C(3247587328), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_X2_SGPR_IMM_gfx9
    UINT64_C(3247521792), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4119920640), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_X2_SGPR_RTN_gfx10
    UINT64_C(3247505408), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_X2_SGPR_RTN_vi
    UINT64_C(3247456256), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_X2_SGPR_alt_gfx9
    UINT64_C(4119855104), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_X2_SGPR_gfx10
    UINT64_C(3247439872), UINT64_C(0),	// S_BUFFER_ATOMIC_SMIN_X2_SGPR_vi
    UINT64_C(18014398513593253888), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_IMM_RTN_gfx10
    UINT64_C(3238985728), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_IMM_RTN_vi
    UINT64_C(18014398513593188352), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_IMM_gfx10
    UINT64_C(3238920192), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_IMM_vi
    UINT64_C(4111269888), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_SGPR_IMM_RTN_gfx10
    UINT64_C(3239002112), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_SGPR_IMM_RTN_gfx9
    UINT64_C(4111204352), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_SGPR_IMM_gfx10
    UINT64_C(3238936576), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_SGPR_IMM_gfx9
    UINT64_C(3238871040), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_SGPR_RTN_alt_gfx9
    UINT64_C(4111269888), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_SGPR_RTN_gfx10
    UINT64_C(3238854656), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_SGPR_RTN_vi
    UINT64_C(3238805504), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_SGPR_alt_gfx9
    UINT64_C(4111204352), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_SGPR_gfx10
    UINT64_C(3238789120), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_SGPR_vi
    UINT64_C(18014398513601642496), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_X2_IMM_RTN_gfx10
    UINT64_C(3247374336), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_X2_IMM_RTN_vi
    UINT64_C(18014398513601576960), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_X2_IMM_gfx10
    UINT64_C(3247308800), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_X2_IMM_vi
    UINT64_C(4119658496), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3247390720), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4119592960), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_X2_SGPR_IMM_gfx10
    UINT64_C(3247325184), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_X2_SGPR_IMM_gfx9
    UINT64_C(3247259648), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4119658496), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_X2_SGPR_RTN_gfx10
    UINT64_C(3247243264), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_X2_SGPR_RTN_vi
    UINT64_C(3247194112), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_X2_SGPR_alt_gfx9
    UINT64_C(4119592960), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_X2_SGPR_gfx10
    UINT64_C(3247177728), UINT64_C(0),	// S_BUFFER_ATOMIC_SUB_X2_SGPR_vi
    UINT64_C(18014398513592467456), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_IMM_RTN_gfx10
    UINT64_C(3238199296), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_IMM_RTN_vi
    UINT64_C(18014398513592401920), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_IMM_gfx10
    UINT64_C(3238133760), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_IMM_vi
    UINT64_C(4110483456), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_SGPR_IMM_RTN_gfx10
    UINT64_C(3238215680), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_SGPR_IMM_RTN_gfx9
    UINT64_C(4110417920), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_SGPR_IMM_gfx10
    UINT64_C(3238150144), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_SGPR_IMM_gfx9
    UINT64_C(3238084608), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_SGPR_RTN_alt_gfx9
    UINT64_C(4110483456), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_SGPR_RTN_gfx10
    UINT64_C(3238068224), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_SGPR_RTN_vi
    UINT64_C(3238019072), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_SGPR_alt_gfx9
    UINT64_C(4110417920), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_SGPR_gfx10
    UINT64_C(3238002688), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_SGPR_vi
    UINT64_C(18014398513600856064), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_X2_IMM_RTN_gfx10
    UINT64_C(3246587904), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_X2_IMM_RTN_vi
    UINT64_C(18014398513600790528), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_X2_IMM_gfx10
    UINT64_C(3246522368), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_X2_IMM_vi
    UINT64_C(4118872064), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3246604288), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4118806528), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_X2_SGPR_IMM_gfx10
    UINT64_C(3246538752), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_X2_SGPR_IMM_gfx9
    UINT64_C(3246473216), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4118872064), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_X2_SGPR_RTN_gfx10
    UINT64_C(3246456832), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_X2_SGPR_RTN_vi
    UINT64_C(3246407680), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_X2_SGPR_alt_gfx9
    UINT64_C(4118806528), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_X2_SGPR_gfx10
    UINT64_C(3246391296), UINT64_C(0),	// S_BUFFER_ATOMIC_SWAP_X2_SGPR_vi
    UINT64_C(18014398513594302464), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_IMM_RTN_gfx10
    UINT64_C(3240034304), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_IMM_RTN_vi
    UINT64_C(18014398513594236928), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_IMM_gfx10
    UINT64_C(3239968768), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_IMM_vi
    UINT64_C(4112318464), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_SGPR_IMM_RTN_gfx10
    UINT64_C(3240050688), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_SGPR_IMM_RTN_gfx9
    UINT64_C(4112252928), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_SGPR_IMM_gfx10
    UINT64_C(3239985152), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_SGPR_IMM_gfx9
    UINT64_C(3239919616), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_SGPR_RTN_alt_gfx9
    UINT64_C(4112318464), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_SGPR_RTN_gfx10
    UINT64_C(3239903232), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_SGPR_RTN_vi
    UINT64_C(3239854080), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_SGPR_alt_gfx9
    UINT64_C(4112252928), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_SGPR_gfx10
    UINT64_C(3239837696), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_SGPR_vi
    UINT64_C(18014398513602691072), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_X2_IMM_RTN_gfx10
    UINT64_C(3248422912), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_X2_IMM_RTN_vi
    UINT64_C(18014398513602625536), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_X2_IMM_gfx10
    UINT64_C(3248357376), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_X2_IMM_vi
    UINT64_C(4120707072), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3248439296), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4120641536), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_X2_SGPR_IMM_gfx10
    UINT64_C(3248373760), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_X2_SGPR_IMM_gfx9
    UINT64_C(3248308224), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4120707072), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_X2_SGPR_RTN_gfx10
    UINT64_C(3248291840), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_X2_SGPR_RTN_vi
    UINT64_C(3248242688), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_X2_SGPR_alt_gfx9
    UINT64_C(4120641536), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_X2_SGPR_gfx10
    UINT64_C(3248226304), UINT64_C(0),	// S_BUFFER_ATOMIC_UMAX_X2_SGPR_vi
    UINT64_C(18014398513593778176), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_IMM_RTN_gfx10
    UINT64_C(3239510016), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_IMM_RTN_vi
    UINT64_C(18014398513593712640), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_IMM_gfx10
    UINT64_C(3239444480), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_IMM_vi
    UINT64_C(4111794176), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_SGPR_IMM_RTN_gfx10
    UINT64_C(3239526400), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_SGPR_IMM_RTN_gfx9
    UINT64_C(4111728640), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_SGPR_IMM_gfx10
    UINT64_C(3239460864), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_SGPR_IMM_gfx9
    UINT64_C(3239395328), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_SGPR_RTN_alt_gfx9
    UINT64_C(4111794176), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_SGPR_RTN_gfx10
    UINT64_C(3239378944), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_SGPR_RTN_vi
    UINT64_C(3239329792), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_SGPR_alt_gfx9
    UINT64_C(4111728640), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_SGPR_gfx10
    UINT64_C(3239313408), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_SGPR_vi
    UINT64_C(18014398513602166784), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_X2_IMM_RTN_gfx10
    UINT64_C(3247898624), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_X2_IMM_RTN_vi
    UINT64_C(18014398513602101248), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_X2_IMM_gfx10
    UINT64_C(3247833088), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_X2_IMM_vi
    UINT64_C(4120182784), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3247915008), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4120117248), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_X2_SGPR_IMM_gfx10
    UINT64_C(3247849472), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_X2_SGPR_IMM_gfx9
    UINT64_C(3247783936), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4120182784), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_X2_SGPR_RTN_gfx10
    UINT64_C(3247767552), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_X2_SGPR_RTN_vi
    UINT64_C(3247718400), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_X2_SGPR_alt_gfx9
    UINT64_C(4120117248), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_X2_SGPR_gfx10
    UINT64_C(3247702016), UINT64_C(0),	// S_BUFFER_ATOMIC_UMIN_X2_SGPR_vi
    UINT64_C(18014398513595088896), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_IMM_RTN_gfx10
    UINT64_C(3240820736), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_IMM_RTN_vi
    UINT64_C(18014398513595023360), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_IMM_gfx10
    UINT64_C(3240755200), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_IMM_vi
    UINT64_C(4113104896), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_SGPR_IMM_RTN_gfx10
    UINT64_C(3240837120), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_SGPR_IMM_RTN_gfx9
    UINT64_C(4113039360), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_SGPR_IMM_gfx10
    UINT64_C(3240771584), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_SGPR_IMM_gfx9
    UINT64_C(3240706048), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_SGPR_RTN_alt_gfx9
    UINT64_C(4113104896), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_SGPR_RTN_gfx10
    UINT64_C(3240689664), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_SGPR_RTN_vi
    UINT64_C(3240640512), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_SGPR_alt_gfx9
    UINT64_C(4113039360), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_SGPR_gfx10
    UINT64_C(3240624128), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_SGPR_vi
    UINT64_C(18014398513603477504), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_X2_IMM_RTN_gfx10
    UINT64_C(3249209344), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_X2_IMM_RTN_vi
    UINT64_C(18014398513603411968), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_X2_IMM_gfx10
    UINT64_C(3249143808), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_X2_IMM_vi
    UINT64_C(4121493504), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_X2_SGPR_IMM_RTN_gfx10
    UINT64_C(3249225728), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_X2_SGPR_IMM_RTN_gfx9
    UINT64_C(4121427968), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_X2_SGPR_IMM_gfx10
    UINT64_C(3249160192), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_X2_SGPR_IMM_gfx9
    UINT64_C(3249094656), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_X2_SGPR_RTN_alt_gfx9
    UINT64_C(4121493504), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_X2_SGPR_RTN_gfx10
    UINT64_C(3249078272), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_X2_SGPR_RTN_vi
    UINT64_C(3249029120), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_X2_SGPR_alt_gfx9
    UINT64_C(4121427968), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_X2_SGPR_gfx10
    UINT64_C(3249012736), UINT64_C(0),	// S_BUFFER_ATOMIC_XOR_X2_SGPR_vi
    UINT64_C(17870283325502390272), UINT64_C(0),	// S_BUFFER_LOAD_B128_IMM_gfx11
    UINT64_C(17870283325499916288), UINT64_C(0),	// S_BUFFER_LOAD_B128_IMM_gfx12
    UINT64_C(4096262144), UINT64_C(0),	// S_BUFFER_LOAD_B128_SGPR_IMM_gfx11
    UINT64_C(4093788160), UINT64_C(0),	// S_BUFFER_LOAD_B128_SGPR_IMM_gfx12
    UINT64_C(4096262144), UINT64_C(0),	// S_BUFFER_LOAD_B128_SGPR_gfx11
    UINT64_C(17870283325502652416), UINT64_C(0),	// S_BUFFER_LOAD_B256_IMM_gfx11
    UINT64_C(17870283325499924480), UINT64_C(0),	// S_BUFFER_LOAD_B256_IMM_gfx12
    UINT64_C(4096524288), UINT64_C(0),	// S_BUFFER_LOAD_B256_SGPR_IMM_gfx11
    UINT64_C(4093796352), UINT64_C(0),	// S_BUFFER_LOAD_B256_SGPR_IMM_gfx12
    UINT64_C(4096524288), UINT64_C(0),	// S_BUFFER_LOAD_B256_SGPR_gfx11
    UINT64_C(17870283325501865984), UINT64_C(0),	// S_BUFFER_LOAD_B32_IMM_gfx11
    UINT64_C(17870283325499899904), UINT64_C(0),	// S_BUFFER_LOAD_B32_IMM_gfx12
    UINT64_C(4095737856), UINT64_C(0),	// S_BUFFER_LOAD_B32_SGPR_IMM_gfx11
    UINT64_C(4093771776), UINT64_C(0),	// S_BUFFER_LOAD_B32_SGPR_IMM_gfx12
    UINT64_C(4095737856), UINT64_C(0),	// S_BUFFER_LOAD_B32_SGPR_gfx11
    UINT64_C(17870283325502914560), UINT64_C(0),	// S_BUFFER_LOAD_B512_IMM_gfx11
    UINT64_C(17870283325499932672), UINT64_C(0),	// S_BUFFER_LOAD_B512_IMM_gfx12
    UINT64_C(4096786432), UINT64_C(0),	// S_BUFFER_LOAD_B512_SGPR_IMM_gfx11
    UINT64_C(4093804544), UINT64_C(0),	// S_BUFFER_LOAD_B512_SGPR_IMM_gfx12
    UINT64_C(4096786432), UINT64_C(0),	// S_BUFFER_LOAD_B512_SGPR_gfx11
    UINT64_C(17870283325502128128), UINT64_C(0),	// S_BUFFER_LOAD_B64_IMM_gfx11
    UINT64_C(17870283325499908096), UINT64_C(0),	// S_BUFFER_LOAD_B64_IMM_gfx12
    UINT64_C(4096000000), UINT64_C(0),	// S_BUFFER_LOAD_B64_SGPR_IMM_gfx11
    UINT64_C(4093779968), UINT64_C(0),	// S_BUFFER_LOAD_B64_SGPR_IMM_gfx12
    UINT64_C(4096000000), UINT64_C(0),	// S_BUFFER_LOAD_B64_SGPR_gfx11
    UINT64_C(17870283325499940864), UINT64_C(0),	// S_BUFFER_LOAD_B96_IMM_gfx12
    UINT64_C(4093812736), UINT64_C(0),	// S_BUFFER_LOAD_B96_SGPR_IMM_gfx12
    UINT64_C(3271557375), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX16_IMM_ci
    UINT64_C(18014398513578770432), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX16_IMM_gfx10
    UINT64_C(3271557376), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX16_IMM_si
    UINT64_C(3224502272), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX16_IMM_vi
    UINT64_C(4096786432), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX16_SGPR_IMM_gfx10
    UINT64_C(3224518656), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX16_SGPR_IMM_gfx9
    UINT64_C(3224387584), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX16_SGPR_alt_gfx9
    UINT64_C(4096786432), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX16_SGPR_gfx10
    UINT64_C(3271557120), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX16_SGPR_si
    UINT64_C(3224371200), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX16_SGPR_vi
    UINT64_C(3258974463), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX2_IMM_ci
    UINT64_C(18014398513577984000), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX2_IMM_gfx10
    UINT64_C(3258974464), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX2_IMM_si
    UINT64_C(3223715840), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX2_IMM_vi
    UINT64_C(4096000000), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX2_SGPR_IMM_gfx10
    UINT64_C(3223732224), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX2_SGPR_IMM_gfx9
    UINT64_C(3223601152), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX2_SGPR_alt_gfx9
    UINT64_C(4096000000), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX2_SGPR_gfx10
    UINT64_C(3258974208), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX2_SGPR_si
    UINT64_C(3223584768), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX2_SGPR_vi
    UINT64_C(3263168767), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX4_IMM_ci
    UINT64_C(18014398513578246144), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX4_IMM_gfx10
    UINT64_C(3263168768), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX4_IMM_si
    UINT64_C(3223977984), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX4_IMM_vi
    UINT64_C(4096262144), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX4_SGPR_IMM_gfx10
    UINT64_C(3223994368), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX4_SGPR_IMM_gfx9
    UINT64_C(3223863296), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX4_SGPR_alt_gfx9
    UINT64_C(4096262144), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX4_SGPR_gfx10
    UINT64_C(3263168512), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX4_SGPR_si
    UINT64_C(3223846912), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX4_SGPR_vi
    UINT64_C(3267363071), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX8_IMM_ci
    UINT64_C(18014398513578508288), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX8_IMM_gfx10
    UINT64_C(3267363072), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX8_IMM_si
    UINT64_C(3224240128), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX8_IMM_vi
    UINT64_C(4096524288), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX8_SGPR_IMM_gfx10
    UINT64_C(3224256512), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX8_SGPR_IMM_gfx9
    UINT64_C(3224125440), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX8_SGPR_alt_gfx9
    UINT64_C(4096524288), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX8_SGPR_gfx10
    UINT64_C(3267362816), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX8_SGPR_si
    UINT64_C(3224109056), UINT64_C(0),	// S_BUFFER_LOAD_DWORDX8_SGPR_vi
    UINT64_C(3254780159), UINT64_C(0),	// S_BUFFER_LOAD_DWORD_IMM_ci
    UINT64_C(18014398513577721856), UINT64_C(0),	// S_BUFFER_LOAD_DWORD_IMM_gfx10
    UINT64_C(3254780160), UINT64_C(0),	// S_BUFFER_LOAD_DWORD_IMM_si
    UINT64_C(3223453696), UINT64_C(0),	// S_BUFFER_LOAD_DWORD_IMM_vi
    UINT64_C(4095737856), UINT64_C(0),	// S_BUFFER_LOAD_DWORD_SGPR_IMM_gfx10
    UINT64_C(3223470080), UINT64_C(0),	// S_BUFFER_LOAD_DWORD_SGPR_IMM_gfx9
    UINT64_C(3223339008), UINT64_C(0),	// S_BUFFER_LOAD_DWORD_SGPR_alt_gfx9
    UINT64_C(4095737856), UINT64_C(0),	// S_BUFFER_LOAD_DWORD_SGPR_gfx10
    UINT64_C(3254779904), UINT64_C(0),	// S_BUFFER_LOAD_DWORD_SGPR_si
    UINT64_C(3223322624), UINT64_C(0),	// S_BUFFER_LOAD_DWORD_SGPR_vi
    UINT64_C(17870283325499981824), UINT64_C(0),	// S_BUFFER_LOAD_I16_IMM_gfx12
    UINT64_C(4093853696), UINT64_C(0),	// S_BUFFER_LOAD_I16_SGPR_IMM_gfx12
    UINT64_C(17870283325499965440), UINT64_C(0),	// S_BUFFER_LOAD_I8_IMM_gfx12
    UINT64_C(4093837312), UINT64_C(0),	// S_BUFFER_LOAD_I8_SGPR_IMM_gfx12
    UINT64_C(17870283325499990016), UINT64_C(0),	// S_BUFFER_LOAD_U16_IMM_gfx12
    UINT64_C(4093861888), UINT64_C(0),	// S_BUFFER_LOAD_U16_SGPR_IMM_gfx12
    UINT64_C(17870283325499973632), UINT64_C(0),	// S_BUFFER_LOAD_U8_IMM_gfx12
    UINT64_C(4093845504), UINT64_C(0),	// S_BUFFER_LOAD_U8_SGPR_IMM_gfx12
    UINT64_C(4093960192), UINT64_C(0),	// S_BUFFER_PREFETCH_DATA_gfx12
    UINT64_C(18014398513582178304), UINT64_C(0),	// S_BUFFER_STORE_DWORDX2_IMM_gfx10
    UINT64_C(3227910144), UINT64_C(0),	// S_BUFFER_STORE_DWORDX2_IMM_vi
    UINT64_C(4100194304), UINT64_C(0),	// S_BUFFER_STORE_DWORDX2_SGPR_IMM_gfx10
    UINT64_C(3227926528), UINT64_C(0),	// S_BUFFER_STORE_DWORDX2_SGPR_IMM_gfx9
    UINT64_C(3227795456), UINT64_C(0),	// S_BUFFER_STORE_DWORDX2_SGPR_alt_gfx9
    UINT64_C(4100194304), UINT64_C(0),	// S_BUFFER_STORE_DWORDX2_SGPR_gfx10
    UINT64_C(3227779072), UINT64_C(0),	// S_BUFFER_STORE_DWORDX2_SGPR_vi
    UINT64_C(18014398513582440448), UINT64_C(0),	// S_BUFFER_STORE_DWORDX4_IMM_gfx10
    UINT64_C(3228172288), UINT64_C(0),	// S_BUFFER_STORE_DWORDX4_IMM_vi
    UINT64_C(4100456448), UINT64_C(0),	// S_BUFFER_STORE_DWORDX4_SGPR_IMM_gfx10
    UINT64_C(3228188672), UINT64_C(0),	// S_BUFFER_STORE_DWORDX4_SGPR_IMM_gfx9
    UINT64_C(3228057600), UINT64_C(0),	// S_BUFFER_STORE_DWORDX4_SGPR_alt_gfx9
    UINT64_C(4100456448), UINT64_C(0),	// S_BUFFER_STORE_DWORDX4_SGPR_gfx10
    UINT64_C(3228041216), UINT64_C(0),	// S_BUFFER_STORE_DWORDX4_SGPR_vi
    UINT64_C(18014398513581916160), UINT64_C(0),	// S_BUFFER_STORE_DWORD_IMM_gfx10
    UINT64_C(3227648000), UINT64_C(0),	// S_BUFFER_STORE_DWORD_IMM_vi
    UINT64_C(4099932160), UINT64_C(0),	// S_BUFFER_STORE_DWORD_SGPR_IMM_gfx10
    UINT64_C(3227664384), UINT64_C(0),	// S_BUFFER_STORE_DWORD_SGPR_IMM_gfx9
    UINT64_C(3227533312), UINT64_C(0),	// S_BUFFER_STORE_DWORD_SGPR_alt_gfx9
    UINT64_C(4099932160), UINT64_C(0),	// S_BUFFER_STORE_DWORD_SGPR_gfx10
    UINT64_C(3227516928), UINT64_C(0),	// S_BUFFER_STORE_DWORD_SGPR_vi
    UINT64_C(3137339392), UINT64_C(0),	// S_CALL_B64_gfx10
    UINT64_C(3120562176), UINT64_C(0),	// S_CALL_B64_gfx11
    UINT64_C(3120562176), UINT64_C(0),	// S_CALL_B64_gfx12
    UINT64_C(3120562176), UINT64_C(0),	// S_CALL_B64_gfx1250
    UINT64_C(3128950784), UINT64_C(0),	// S_CALL_B64_vi
    UINT64_C(3214540800), UINT64_C(0),	// S_CBRANCH_CDBGSYS_AND_USER_gfx10
    UINT64_C(3215589376), UINT64_C(0),	// S_CBRANCH_CDBGSYS_AND_USER_gfx11
    UINT64_C(3214540800), UINT64_C(0),	// S_CBRANCH_CDBGSYS_AND_USER_gfx6_gfx7
    UINT64_C(13799029261477740544), UINT64_C(0),	// S_CBRANCH_CDBGSYS_AND_USER_pad_s_nop_gfx10
    UINT64_C(13799029261478789120), UINT64_C(0),	// S_CBRANCH_CDBGSYS_AND_USER_pad_s_nop_gfx11
    UINT64_C(13799029261477740544), UINT64_C(0),	// S_CBRANCH_CDBGSYS_AND_USER_pad_s_nop_gfx6_gfx7
    UINT64_C(13799029261477740544), UINT64_C(0),	// S_CBRANCH_CDBGSYS_AND_USER_pad_s_nop_vi
    UINT64_C(3214540800), UINT64_C(0),	// S_CBRANCH_CDBGSYS_AND_USER_vi
    UINT64_C(3214475264), UINT64_C(0),	// S_CBRANCH_CDBGSYS_OR_USER_gfx10
    UINT64_C(3215523840), UINT64_C(0),	// S_CBRANCH_CDBGSYS_OR_USER_gfx11
    UINT64_C(3214475264), UINT64_C(0),	// S_CBRANCH_CDBGSYS_OR_USER_gfx6_gfx7
    UINT64_C(13799029261477675008), UINT64_C(0),	// S_CBRANCH_CDBGSYS_OR_USER_pad_s_nop_gfx10
    UINT64_C(13799029261478723584), UINT64_C(0),	// S_CBRANCH_CDBGSYS_OR_USER_pad_s_nop_gfx11
    UINT64_C(13799029261477675008), UINT64_C(0),	// S_CBRANCH_CDBGSYS_OR_USER_pad_s_nop_gfx6_gfx7
    UINT64_C(13799029261477675008), UINT64_C(0),	// S_CBRANCH_CDBGSYS_OR_USER_pad_s_nop_vi
    UINT64_C(3214475264), UINT64_C(0),	// S_CBRANCH_CDBGSYS_OR_USER_vi
    UINT64_C(3214344192), UINT64_C(0),	// S_CBRANCH_CDBGSYS_gfx10
    UINT64_C(3215392768), UINT64_C(0),	// S_CBRANCH_CDBGSYS_gfx11
    UINT64_C(3214344192), UINT64_C(0),	// S_CBRANCH_CDBGSYS_gfx6_gfx7
    UINT64_C(13799029261477543936), UINT64_C(0),	// S_CBRANCH_CDBGSYS_pad_s_nop_gfx10
    UINT64_C(13799029261478592512), UINT64_C(0),	// S_CBRANCH_CDBGSYS_pad_s_nop_gfx11
    UINT64_C(13799029261477543936), UINT64_C(0),	// S_CBRANCH_CDBGSYS_pad_s_nop_gfx6_gfx7
    UINT64_C(13799029261477543936), UINT64_C(0),	// S_CBRANCH_CDBGSYS_pad_s_nop_vi
    UINT64_C(3214344192), UINT64_C(0),	// S_CBRANCH_CDBGSYS_vi
    UINT64_C(3214409728), UINT64_C(0),	// S_CBRANCH_CDBGUSER_gfx10
    UINT64_C(3215458304), UINT64_C(0),	// S_CBRANCH_CDBGUSER_gfx11
    UINT64_C(3214409728), UINT64_C(0),	// S_CBRANCH_CDBGUSER_gfx6_gfx7
    UINT64_C(13799029261477609472), UINT64_C(0),	// S_CBRANCH_CDBGUSER_pad_s_nop_gfx10
    UINT64_C(13799029261478658048), UINT64_C(0),	// S_CBRANCH_CDBGUSER_pad_s_nop_gfx11
    UINT64_C(13799029261477609472), UINT64_C(0),	// S_CBRANCH_CDBGUSER_pad_s_nop_gfx6_gfx7
    UINT64_C(13799029261477609472), UINT64_C(0),	// S_CBRANCH_CDBGUSER_pad_s_nop_vi
    UINT64_C(3214409728), UINT64_C(0),	// S_CBRANCH_CDBGUSER_vi
    UINT64_C(3213426688), UINT64_C(0),	// S_CBRANCH_EXECNZ_gfx10
    UINT64_C(3215327232), UINT64_C(0),	// S_CBRANCH_EXECNZ_gfx11
    UINT64_C(3215327232), UINT64_C(0),	// S_CBRANCH_EXECNZ_gfx12
    UINT64_C(3213426688), UINT64_C(0),	// S_CBRANCH_EXECNZ_gfx6_gfx7
    UINT64_C(13799029261476626432), UINT64_C(0),	// S_CBRANCH_EXECNZ_pad_s_nop_gfx10
    UINT64_C(13799029261478526976), UINT64_C(0),	// S_CBRANCH_EXECNZ_pad_s_nop_gfx11
    UINT64_C(13799029261478526976), UINT64_C(0),	// S_CBRANCH_EXECNZ_pad_s_nop_gfx12
    UINT64_C(13799029261476626432), UINT64_C(0),	// S_CBRANCH_EXECNZ_pad_s_nop_gfx6_gfx7
    UINT64_C(13799029261476626432), UINT64_C(0),	// S_CBRANCH_EXECNZ_pad_s_nop_vi
    UINT64_C(3213426688), UINT64_C(0),	// S_CBRANCH_EXECNZ_vi
    UINT64_C(3213361152), UINT64_C(0),	// S_CBRANCH_EXECZ_gfx10
    UINT64_C(3215261696), UINT64_C(0),	// S_CBRANCH_EXECZ_gfx11
    UINT64_C(3215261696), UINT64_C(0),	// S_CBRANCH_EXECZ_gfx12
    UINT64_C(3213361152), UINT64_C(0),	// S_CBRANCH_EXECZ_gfx6_gfx7
    UINT64_C(13799029261476560896), UINT64_C(0),	// S_CBRANCH_EXECZ_pad_s_nop_gfx10
    UINT64_C(13799029261478461440), UINT64_C(0),	// S_CBRANCH_EXECZ_pad_s_nop_gfx11
    UINT64_C(13799029261478461440), UINT64_C(0),	// S_CBRANCH_EXECZ_pad_s_nop_gfx12
    UINT64_C(13799029261476560896), UINT64_C(0),	// S_CBRANCH_EXECZ_pad_s_nop_gfx6_gfx7
    UINT64_C(13799029261476560896), UINT64_C(0),	// S_CBRANCH_EXECZ_pad_s_nop_vi
    UINT64_C(3213361152), UINT64_C(0),	// S_CBRANCH_EXECZ_vi
    UINT64_C(2508193792), UINT64_C(0),	// S_CBRANCH_G_FORK_gfx6_gfx7
    UINT64_C(2491416576), UINT64_C(0),	// S_CBRANCH_G_FORK_vi
    UINT64_C(3095396352), UINT64_C(0),	// S_CBRANCH_I_FORK_gfx6_gfx7
    UINT64_C(3087007744), UINT64_C(0),	// S_CBRANCH_I_FORK_vi
    UINT64_C(3196072448), UINT64_C(0),	// S_CBRANCH_JOIN_gfx6_gfx7
    UINT64_C(3196071424), UINT64_C(0),	// S_CBRANCH_JOIN_vi
    UINT64_C(3213099008), UINT64_C(0),	// S_CBRANCH_SCC0_gfx10
    UINT64_C(3214999552), UINT64_C(0),	// S_CBRANCH_SCC0_gfx11
    UINT64_C(3214999552), UINT64_C(0),	// S_CBRANCH_SCC0_gfx12
    UINT64_C(3213099008), UINT64_C(0),	// S_CBRANCH_SCC0_gfx6_gfx7
    UINT64_C(13799029261476298752), UINT64_C(0),	// S_CBRANCH_SCC0_pad_s_nop_gfx10
    UINT64_C(13799029261478199296), UINT64_C(0),	// S_CBRANCH_SCC0_pad_s_nop_gfx11
    UINT64_C(13799029261478199296), UINT64_C(0),	// S_CBRANCH_SCC0_pad_s_nop_gfx12
    UINT64_C(13799029261476298752), UINT64_C(0),	// S_CBRANCH_SCC0_pad_s_nop_gfx6_gfx7
    UINT64_C(13799029261476298752), UINT64_C(0),	// S_CBRANCH_SCC0_pad_s_nop_vi
    UINT64_C(3213099008), UINT64_C(0),	// S_CBRANCH_SCC0_vi
    UINT64_C(3213164544), UINT64_C(0),	// S_CBRANCH_SCC1_gfx10
    UINT64_C(3215065088), UINT64_C(0),	// S_CBRANCH_SCC1_gfx11
    UINT64_C(3215065088), UINT64_C(0),	// S_CBRANCH_SCC1_gfx12
    UINT64_C(3213164544), UINT64_C(0),	// S_CBRANCH_SCC1_gfx6_gfx7
    UINT64_C(13799029261476364288), UINT64_C(0),	// S_CBRANCH_SCC1_pad_s_nop_gfx10
    UINT64_C(13799029261478264832), UINT64_C(0),	// S_CBRANCH_SCC1_pad_s_nop_gfx11
    UINT64_C(13799029261478264832), UINT64_C(0),	// S_CBRANCH_SCC1_pad_s_nop_gfx12
    UINT64_C(13799029261476364288), UINT64_C(0),	// S_CBRANCH_SCC1_pad_s_nop_gfx6_gfx7
    UINT64_C(13799029261476364288), UINT64_C(0),	// S_CBRANCH_SCC1_pad_s_nop_vi
    UINT64_C(3213164544), UINT64_C(0),	// S_CBRANCH_SCC1_vi
    UINT64_C(3213295616), UINT64_C(0),	// S_CBRANCH_VCCNZ_gfx10
    UINT64_C(3215196160), UINT64_C(0),	// S_CBRANCH_VCCNZ_gfx11
    UINT64_C(3215196160), UINT64_C(0),	// S_CBRANCH_VCCNZ_gfx12
    UINT64_C(3213295616), UINT64_C(0),	// S_CBRANCH_VCCNZ_gfx6_gfx7
    UINT64_C(13799029261476495360), UINT64_C(0),	// S_CBRANCH_VCCNZ_pad_s_nop_gfx10
    UINT64_C(13799029261478395904), UINT64_C(0),	// S_CBRANCH_VCCNZ_pad_s_nop_gfx11
    UINT64_C(13799029261478395904), UINT64_C(0),	// S_CBRANCH_VCCNZ_pad_s_nop_gfx12
    UINT64_C(13799029261476495360), UINT64_C(0),	// S_CBRANCH_VCCNZ_pad_s_nop_gfx6_gfx7
    UINT64_C(13799029261476495360), UINT64_C(0),	// S_CBRANCH_VCCNZ_pad_s_nop_vi
    UINT64_C(3213295616), UINT64_C(0),	// S_CBRANCH_VCCNZ_vi
    UINT64_C(3213230080), UINT64_C(0),	// S_CBRANCH_VCCZ_gfx10
    UINT64_C(3215130624), UINT64_C(0),	// S_CBRANCH_VCCZ_gfx11
    UINT64_C(3215130624), UINT64_C(0),	// S_CBRANCH_VCCZ_gfx12
    UINT64_C(3213230080), UINT64_C(0),	// S_CBRANCH_VCCZ_gfx6_gfx7
    UINT64_C(13799029261476429824), UINT64_C(0),	// S_CBRANCH_VCCZ_pad_s_nop_gfx10
    UINT64_C(13799029261478330368), UINT64_C(0),	// S_CBRANCH_VCCZ_pad_s_nop_gfx11
    UINT64_C(13799029261478330368), UINT64_C(0),	// S_CBRANCH_VCCZ_pad_s_nop_gfx12
    UINT64_C(13799029261476429824), UINT64_C(0),	// S_CBRANCH_VCCZ_pad_s_nop_gfx6_gfx7
    UINT64_C(13799029261476429824), UINT64_C(0),	// S_CBRANCH_VCCZ_pad_s_nop_vi
    UINT64_C(3213230080), UINT64_C(0),	// S_CBRANCH_VCCZ_vi
    UINT64_C(3196087040), UINT64_C(0),	// S_CEIL_F16_gfx11
    UINT64_C(3196087040), UINT64_C(0),	// S_CEIL_F16_gfx12
    UINT64_C(3196084224), UINT64_C(0),	// S_CEIL_F32_gfx11
    UINT64_C(3196084224), UINT64_C(0),	// S_CEIL_F32_gfx12
    UINT64_C(3214999552), UINT64_C(0),	// S_CLAUSE_gfx10
    UINT64_C(3213164544), UINT64_C(0),	// S_CLAUSE_gfx11
    UINT64_C(3213164544), UINT64_C(0),	// S_CLAUSE_gfx12
    UINT64_C(2969567232), UINT64_C(0),	// S_CMOVK_I32_gfx10
    UINT64_C(2969567232), UINT64_C(0),	// S_CMOVK_I32_gfx11
    UINT64_C(2969567232), UINT64_C(0),	// S_CMOVK_I32_gfx12
    UINT64_C(2969567232), UINT64_C(0),	// S_CMOVK_I32_gfx6_gfx7
    UINT64_C(2961178624), UINT64_C(0),	// S_CMOVK_I32_vi
    UINT64_C(3196060928), UINT64_C(0),	// S_CMOV_B32_gfx10
    UINT64_C(3196060160), UINT64_C(0),	// S_CMOV_B32_gfx11
    UINT64_C(3196060160), UINT64_C(0),	// S_CMOV_B32_gfx12
    UINT64_C(3196060928), UINT64_C(0),	// S_CMOV_B32_gfx6_gfx7
    UINT64_C(3196060160), UINT64_C(0),	// S_CMOV_B32_vi
    UINT64_C(3196061184), UINT64_C(0),	// S_CMOV_B64_gfx10
    UINT64_C(3196060416), UINT64_C(0),	// S_CMOV_B64_gfx11
    UINT64_C(3196060416), UINT64_C(0),	// S_CMOV_B64_gfx12
    UINT64_C(3196061184), UINT64_C(0),	// S_CMOV_B64_gfx6_gfx7
    UINT64_C(3196060416), UINT64_C(0),	// S_CMOV_B64_vi
    UINT64_C(2977955840), UINT64_C(0),	// S_CMPK_EQ_I32_gfx10
    UINT64_C(2977955840), UINT64_C(0),	// S_CMPK_EQ_I32_gfx11
    UINT64_C(2977955840), UINT64_C(0),	// S_CMPK_EQ_I32_gfx6_gfx7
    UINT64_C(2969567232), UINT64_C(0),	// S_CMPK_EQ_I32_vi
    UINT64_C(3028287488), UINT64_C(0),	// S_CMPK_EQ_U32_gfx10
    UINT64_C(3028287488), UINT64_C(0),	// S_CMPK_EQ_U32_gfx11
    UINT64_C(3028287488), UINT64_C(0),	// S_CMPK_EQ_U32_gfx6_gfx7
    UINT64_C(3019898880), UINT64_C(0),	// S_CMPK_EQ_U32_vi
    UINT64_C(3003121664), UINT64_C(0),	// S_CMPK_GE_I32_gfx10
    UINT64_C(3003121664), UINT64_C(0),	// S_CMPK_GE_I32_gfx11
    UINT64_C(3003121664), UINT64_C(0),	// S_CMPK_GE_I32_gfx6_gfx7
    UINT64_C(2994733056), UINT64_C(0),	// S_CMPK_GE_I32_vi
    UINT64_C(3053453312), UINT64_C(0),	// S_CMPK_GE_U32_gfx10
    UINT64_C(3053453312), UINT64_C(0),	// S_CMPK_GE_U32_gfx11
    UINT64_C(3053453312), UINT64_C(0),	// S_CMPK_GE_U32_gfx6_gfx7
    UINT64_C(3045064704), UINT64_C(0),	// S_CMPK_GE_U32_vi
    UINT64_C(2994733056), UINT64_C(0),	// S_CMPK_GT_I32_gfx10
    UINT64_C(2994733056), UINT64_C(0),	// S_CMPK_GT_I32_gfx11
    UINT64_C(2994733056), UINT64_C(0),	// S_CMPK_GT_I32_gfx6_gfx7
    UINT64_C(2986344448), UINT64_C(0),	// S_CMPK_GT_I32_vi
    UINT64_C(3045064704), UINT64_C(0),	// S_CMPK_GT_U32_gfx10
    UINT64_C(3045064704), UINT64_C(0),	// S_CMPK_GT_U32_gfx11
    UINT64_C(3045064704), UINT64_C(0),	// S_CMPK_GT_U32_gfx6_gfx7
    UINT64_C(3036676096), UINT64_C(0),	// S_CMPK_GT_U32_vi
    UINT64_C(3019898880), UINT64_C(0),	// S_CMPK_LE_I32_gfx10
    UINT64_C(3019898880), UINT64_C(0),	// S_CMPK_LE_I32_gfx11
    UINT64_C(3019898880), UINT64_C(0),	// S_CMPK_LE_I32_gfx6_gfx7
    UINT64_C(3011510272), UINT64_C(0),	// S_CMPK_LE_I32_vi
    UINT64_C(3070230528), UINT64_C(0),	// S_CMPK_LE_U32_gfx10
    UINT64_C(3070230528), UINT64_C(0),	// S_CMPK_LE_U32_gfx11
    UINT64_C(3070230528), UINT64_C(0),	// S_CMPK_LE_U32_gfx6_gfx7
    UINT64_C(3061841920), UINT64_C(0),	// S_CMPK_LE_U32_vi
    UINT64_C(2986344448), UINT64_C(0),	// S_CMPK_LG_I32_gfx10
    UINT64_C(2986344448), UINT64_C(0),	// S_CMPK_LG_I32_gfx11
    UINT64_C(2986344448), UINT64_C(0),	// S_CMPK_LG_I32_gfx6_gfx7
    UINT64_C(2977955840), UINT64_C(0),	// S_CMPK_LG_I32_vi
    UINT64_C(3036676096), UINT64_C(0),	// S_CMPK_LG_U32_gfx10
    UINT64_C(3036676096), UINT64_C(0),	// S_CMPK_LG_U32_gfx11
    UINT64_C(3036676096), UINT64_C(0),	// S_CMPK_LG_U32_gfx6_gfx7
    UINT64_C(3028287488), UINT64_C(0),	// S_CMPK_LG_U32_vi
    UINT64_C(3011510272), UINT64_C(0),	// S_CMPK_LT_I32_gfx10
    UINT64_C(3011510272), UINT64_C(0),	// S_CMPK_LT_I32_gfx11
    UINT64_C(3011510272), UINT64_C(0),	// S_CMPK_LT_I32_gfx6_gfx7
    UINT64_C(3003121664), UINT64_C(0),	// S_CMPK_LT_I32_vi
    UINT64_C(3061841920), UINT64_C(0),	// S_CMPK_LT_U32_gfx10
    UINT64_C(3061841920), UINT64_C(0),	// S_CMPK_LT_U32_gfx11
    UINT64_C(3061841920), UINT64_C(0),	// S_CMPK_LT_U32_gfx6_gfx7
    UINT64_C(3053453312), UINT64_C(0),	// S_CMPK_LT_U32_vi
    UINT64_C(3209822208), UINT64_C(0),	// S_CMP_EQ_F16_gfx11
    UINT64_C(3209822208), UINT64_C(0),	// S_CMP_EQ_F16_gfx12
    UINT64_C(3208773632), UINT64_C(0),	// S_CMP_EQ_F32_gfx11
    UINT64_C(3208773632), UINT64_C(0),	// S_CMP_EQ_F32_gfx12
    UINT64_C(3204448256), UINT64_C(0),	// S_CMP_EQ_I32_gfx10
    UINT64_C(3204448256), UINT64_C(0),	// S_CMP_EQ_I32_gfx11
    UINT64_C(3204448256), UINT64_C(0),	// S_CMP_EQ_I32_gfx12
    UINT64_C(3204448256), UINT64_C(0),	// S_CMP_EQ_I32_gfx6_gfx7
    UINT64_C(3204448256), UINT64_C(0),	// S_CMP_EQ_I32_vi
    UINT64_C(3204841472), UINT64_C(0),	// S_CMP_EQ_U32_gfx10
    UINT64_C(3204841472), UINT64_C(0),	// S_CMP_EQ_U32_gfx11
    UINT64_C(3204841472), UINT64_C(0),	// S_CMP_EQ_U32_gfx12
    UINT64_C(3204841472), UINT64_C(0),	// S_CMP_EQ_U32_gfx6_gfx7
    UINT64_C(3204841472), UINT64_C(0),	// S_CMP_EQ_U32_vi
    UINT64_C(3205627904), UINT64_C(0),	// S_CMP_EQ_U64_gfx10
    UINT64_C(3205496832), UINT64_C(0),	// S_CMP_EQ_U64_gfx11
    UINT64_C(3205496832), UINT64_C(0),	// S_CMP_EQ_U64_gfx12
    UINT64_C(3205627904), UINT64_C(0),	// S_CMP_EQ_U64_vi
    UINT64_C(3210084352), UINT64_C(0),	// S_CMP_GE_F16_gfx11
    UINT64_C(3210084352), UINT64_C(0),	// S_CMP_GE_F16_gfx12
    UINT64_C(3209035776), UINT64_C(0),	// S_CMP_GE_F32_gfx11
    UINT64_C(3209035776), UINT64_C(0),	// S_CMP_GE_F32_gfx12
    UINT64_C(3204644864), UINT64_C(0),	// S_CMP_GE_I32_gfx10
    UINT64_C(3204644864), UINT64_C(0),	// S_CMP_GE_I32_gfx11
    UINT64_C(3204644864), UINT64_C(0),	// S_CMP_GE_I32_gfx12
    UINT64_C(3204644864), UINT64_C(0),	// S_CMP_GE_I32_gfx6_gfx7
    UINT64_C(3204644864), UINT64_C(0),	// S_CMP_GE_I32_vi
    UINT64_C(3205038080), UINT64_C(0),	// S_CMP_GE_U32_gfx10
    UINT64_C(3205038080), UINT64_C(0),	// S_CMP_GE_U32_gfx11
    UINT64_C(3205038080), UINT64_C(0),	// S_CMP_GE_U32_gfx12
    UINT64_C(3205038080), UINT64_C(0),	// S_CMP_GE_U32_gfx6_gfx7
    UINT64_C(3205038080), UINT64_C(0),	// S_CMP_GE_U32_vi
    UINT64_C(3209953280), UINT64_C(0),	// S_CMP_GT_F16_gfx11
    UINT64_C(3209953280), UINT64_C(0),	// S_CMP_GT_F16_gfx12
    UINT64_C(3208904704), UINT64_C(0),	// S_CMP_GT_F32_gfx11
    UINT64_C(3208904704), UINT64_C(0),	// S_CMP_GT_F32_gfx12
    UINT64_C(3204579328), UINT64_C(0),	// S_CMP_GT_I32_gfx10
    UINT64_C(3204579328), UINT64_C(0),	// S_CMP_GT_I32_gfx11
    UINT64_C(3204579328), UINT64_C(0),	// S_CMP_GT_I32_gfx12
    UINT64_C(3204579328), UINT64_C(0),	// S_CMP_GT_I32_gfx6_gfx7
    UINT64_C(3204579328), UINT64_C(0),	// S_CMP_GT_I32_vi
    UINT64_C(3204972544), UINT64_C(0),	// S_CMP_GT_U32_gfx10
    UINT64_C(3204972544), UINT64_C(0),	// S_CMP_GT_U32_gfx11
    UINT64_C(3204972544), UINT64_C(0),	// S_CMP_GT_U32_gfx12
    UINT64_C(3204972544), UINT64_C(0),	// S_CMP_GT_U32_gfx6_gfx7
    UINT64_C(3204972544), UINT64_C(0),	// S_CMP_GT_U32_vi
    UINT64_C(3209887744), UINT64_C(0),	// S_CMP_LE_F16_gfx11
    UINT64_C(3209887744), UINT64_C(0),	// S_CMP_LE_F16_gfx12
    UINT64_C(3208839168), UINT64_C(0),	// S_CMP_LE_F32_gfx11
    UINT64_C(3208839168), UINT64_C(0),	// S_CMP_LE_F32_gfx12
    UINT64_C(3204775936), UINT64_C(0),	// S_CMP_LE_I32_gfx10
    UINT64_C(3204775936), UINT64_C(0),	// S_CMP_LE_I32_gfx11
    UINT64_C(3204775936), UINT64_C(0),	// S_CMP_LE_I32_gfx12
    UINT64_C(3204775936), UINT64_C(0),	// S_CMP_LE_I32_gfx6_gfx7
    UINT64_C(3204775936), UINT64_C(0),	// S_CMP_LE_I32_vi
    UINT64_C(3205169152), UINT64_C(0),	// S_CMP_LE_U32_gfx10
    UINT64_C(3205169152), UINT64_C(0),	// S_CMP_LE_U32_gfx11
    UINT64_C(3205169152), UINT64_C(0),	// S_CMP_LE_U32_gfx12
    UINT64_C(3205169152), UINT64_C(0),	// S_CMP_LE_U32_gfx6_gfx7
    UINT64_C(3205169152), UINT64_C(0),	// S_CMP_LE_U32_vi
    UINT64_C(3210018816), UINT64_C(0),	// S_CMP_LG_F16_gfx11
    UINT64_C(3210018816), UINT64_C(0),	// S_CMP_LG_F16_gfx12
    UINT64_C(3208970240), UINT64_C(0),	// S_CMP_LG_F32_gfx11
    UINT64_C(3208970240), UINT64_C(0),	// S_CMP_LG_F32_gfx12
    UINT64_C(3204513792), UINT64_C(0),	// S_CMP_LG_I32_gfx10
    UINT64_C(3204513792), UINT64_C(0),	// S_CMP_LG_I32_gfx11
    UINT64_C(3204513792), UINT64_C(0),	// S_CMP_LG_I32_gfx12
    UINT64_C(3204513792), UINT64_C(0),	// S_CMP_LG_I32_gfx6_gfx7
    UINT64_C(3204513792), UINT64_C(0),	// S_CMP_LG_I32_vi
    UINT64_C(3204907008), UINT64_C(0),	// S_CMP_LG_U32_gfx10
    UINT64_C(3204907008), UINT64_C(0),	// S_CMP_LG_U32_gfx11
    UINT64_C(3204907008), UINT64_C(0),	// S_CMP_LG_U32_gfx12
    UINT64_C(3204907008), UINT64_C(0),	// S_CMP_LG_U32_gfx6_gfx7
    UINT64_C(3204907008), UINT64_C(0),	// S_CMP_LG_U32_vi
    UINT64_C(3205693440), UINT64_C(0),	// S_CMP_LG_U64_gfx10
    UINT64_C(3205562368), UINT64_C(0),	// S_CMP_LG_U64_gfx11
    UINT64_C(3205562368), UINT64_C(0),	// S_CMP_LG_U64_gfx12
    UINT64_C(3205693440), UINT64_C(0),	// S_CMP_LG_U64_vi
    UINT64_C(3209756672), UINT64_C(0),	// S_CMP_LT_F16_gfx11
    UINT64_C(3209756672), UINT64_C(0),	// S_CMP_LT_F16_gfx12
    UINT64_C(3208708096), UINT64_C(0),	// S_CMP_LT_F32_gfx11
    UINT64_C(3208708096), UINT64_C(0),	// S_CMP_LT_F32_gfx12
    UINT64_C(3204710400), UINT64_C(0),	// S_CMP_LT_I32_gfx10
    UINT64_C(3204710400), UINT64_C(0),	// S_CMP_LT_I32_gfx11
    UINT64_C(3204710400), UINT64_C(0),	// S_CMP_LT_I32_gfx12
    UINT64_C(3204710400), UINT64_C(0),	// S_CMP_LT_I32_gfx6_gfx7
    UINT64_C(3204710400), UINT64_C(0),	// S_CMP_LT_I32_vi
    UINT64_C(3205103616), UINT64_C(0),	// S_CMP_LT_U32_gfx10
    UINT64_C(3205103616), UINT64_C(0),	// S_CMP_LT_U32_gfx11
    UINT64_C(3205103616), UINT64_C(0),	// S_CMP_LT_U32_gfx12
    UINT64_C(3205103616), UINT64_C(0),	// S_CMP_LT_U32_gfx6_gfx7
    UINT64_C(3205103616), UINT64_C(0),	// S_CMP_LT_U32_vi
    UINT64_C(3210543104), UINT64_C(0),	// S_CMP_NEQ_F16_gfx11
    UINT64_C(3210543104), UINT64_C(0),	// S_CMP_NEQ_F16_gfx12
    UINT64_C(3209494528), UINT64_C(0),	// S_CMP_NEQ_F32_gfx11
    UINT64_C(3209494528), UINT64_C(0),	// S_CMP_NEQ_F32_gfx12
    UINT64_C(3210280960), UINT64_C(0),	// S_CMP_NGE_F16_gfx11
    UINT64_C(3210280960), UINT64_C(0),	// S_CMP_NGE_F16_gfx12
    UINT64_C(3209232384), UINT64_C(0),	// S_CMP_NGE_F32_gfx11
    UINT64_C(3209232384), UINT64_C(0),	// S_CMP_NGE_F32_gfx12
    UINT64_C(3210412032), UINT64_C(0),	// S_CMP_NGT_F16_gfx11
    UINT64_C(3210412032), UINT64_C(0),	// S_CMP_NGT_F16_gfx12
    UINT64_C(3209363456), UINT64_C(0),	// S_CMP_NGT_F32_gfx11
    UINT64_C(3209363456), UINT64_C(0),	// S_CMP_NGT_F32_gfx12
    UINT64_C(3210477568), UINT64_C(0),	// S_CMP_NLE_F16_gfx11
    UINT64_C(3210477568), UINT64_C(0),	// S_CMP_NLE_F16_gfx12
    UINT64_C(3209428992), UINT64_C(0),	// S_CMP_NLE_F32_gfx11
    UINT64_C(3209428992), UINT64_C(0),	// S_CMP_NLE_F32_gfx12
    UINT64_C(3210346496), UINT64_C(0),	// S_CMP_NLG_F16_gfx11
    UINT64_C(3210346496), UINT64_C(0),	// S_CMP_NLG_F16_gfx12
    UINT64_C(3209297920), UINT64_C(0),	// S_CMP_NLG_F32_gfx11
    UINT64_C(3209297920), UINT64_C(0),	// S_CMP_NLG_F32_gfx12
    UINT64_C(3210608640), UINT64_C(0),	// S_CMP_NLT_F16_gfx11
    UINT64_C(3210608640), UINT64_C(0),	// S_CMP_NLT_F16_gfx12
    UINT64_C(3209560064), UINT64_C(0),	// S_CMP_NLT_F32_gfx11
    UINT64_C(3209560064), UINT64_C(0),	// S_CMP_NLT_F32_gfx12
    UINT64_C(3210149888), UINT64_C(0),	// S_CMP_O_F16_gfx11
    UINT64_C(3210149888), UINT64_C(0),	// S_CMP_O_F16_gfx12
    UINT64_C(3209101312), UINT64_C(0),	// S_CMP_O_F32_gfx11
    UINT64_C(3209101312), UINT64_C(0),	// S_CMP_O_F32_gfx12
    UINT64_C(3210215424), UINT64_C(0),	// S_CMP_U_F16_gfx11
    UINT64_C(3210215424), UINT64_C(0),	// S_CMP_U_F16_gfx12
    UINT64_C(3209166848), UINT64_C(0),	// S_CMP_U_F32_gfx11
    UINT64_C(3209166848), UINT64_C(0),	// S_CMP_U_F32_gfx12
    UINT64_C(3214868480), UINT64_C(0),	// S_CODE_END_gfx10
    UINT64_C(3214868480), UINT64_C(0),	// S_CODE_END_gfx11
    UINT64_C(3214868480), UINT64_C(0),	// S_CODE_END_gfx12
    UINT64_C(2231369728), UINT64_C(0),	// S_CSELECT_B32_gfx10
    UINT64_C(2550136832), UINT64_C(0),	// S_CSELECT_B32_gfx11
    UINT64_C(2550136832), UINT64_C(0),	// S_CSELECT_B32_gfx12
    UINT64_C(2231369728), UINT64_C(0),	// S_CSELECT_B32_gfx6_gfx7
    UINT64_C(2231369728), UINT64_C(0),	// S_CSELECT_B32_vi
    UINT64_C(2239758336), UINT64_C(0),	// S_CSELECT_B64_gfx10
    UINT64_C(2558525440), UINT64_C(0),	// S_CSELECT_B64_gfx11
    UINT64_C(2558525440), UINT64_C(0),	// S_CSELECT_B64_gfx12
    UINT64_C(2239758336), UINT64_C(0),	// S_CSELECT_B64_gfx6_gfx7
    UINT64_C(2239758336), UINT64_C(0),	// S_CSELECT_B64_vi
    UINT64_C(3196086272), UINT64_C(0),	// S_CVT_F16_F32_gfx11
    UINT64_C(3196086272), UINT64_C(0),	// S_CVT_F16_F32_gfx12
    UINT64_C(3196086528), UINT64_C(0),	// S_CVT_F32_F16_gfx11
    UINT64_C(3196086528), UINT64_C(0),	// S_CVT_F32_F16_gfx12
    UINT64_C(3196085248), UINT64_C(0),	// S_CVT_F32_I32_gfx11
    UINT64_C(3196085248), UINT64_C(0),	// S_CVT_F32_I32_gfx12
    UINT64_C(3196085504), UINT64_C(0),	// S_CVT_F32_U32_gfx11
    UINT64_C(3196085504), UINT64_C(0),	// S_CVT_F32_U32_gfx12
    UINT64_C(3196086784), UINT64_C(0),	// S_CVT_HI_F32_F16_gfx11
    UINT64_C(3196086784), UINT64_C(0),	// S_CVT_HI_F32_F16_gfx12
    UINT64_C(3196085760), UINT64_C(0),	// S_CVT_I32_F32_gfx11
    UINT64_C(3196085760), UINT64_C(0),	// S_CVT_I32_F32_gfx12
    UINT64_C(2751463424), UINT64_C(0),	// S_CVT_PK_RTZ_F16_F32_gfx11
    UINT64_C(2751463424), UINT64_C(0),	// S_CVT_PK_RTZ_F16_F32_gfx12
    UINT64_C(3196086016), UINT64_C(0),	// S_CVT_U32_F32_gfx11
    UINT64_C(3196086016), UINT64_C(0),	// S_CVT_U32_F32_gfx12
    UINT64_C(18014398513586110464), UINT64_C(0),	// S_DCACHE_DISCARD_IMM_gfx10
    UINT64_C(3231842304), UINT64_C(0),	// S_DCACHE_DISCARD_IMM_vi
    UINT64_C(4104126464), UINT64_C(0),	// S_DCACHE_DISCARD_SGPR_IMM_gfx10
    UINT64_C(3231858688), UINT64_C(0),	// S_DCACHE_DISCARD_SGPR_IMM_gfx9
    UINT64_C(3231727616), UINT64_C(0),	// S_DCACHE_DISCARD_SGPR_alt_gfx9
    UINT64_C(4104126464), UINT64_C(0),	// S_DCACHE_DISCARD_SGPR_gfx10
    UINT64_C(3231711232), UINT64_C(0),	// S_DCACHE_DISCARD_SGPR_vi
    UINT64_C(18014398513586372608), UINT64_C(0),	// S_DCACHE_DISCARD_X2_IMM_gfx10
    UINT64_C(3232104448), UINT64_C(0),	// S_DCACHE_DISCARD_X2_IMM_vi
    UINT64_C(4104388608), UINT64_C(0),	// S_DCACHE_DISCARD_X2_SGPR_IMM_gfx10
    UINT64_C(3232120832), UINT64_C(0),	// S_DCACHE_DISCARD_X2_SGPR_IMM_gfx9
    UINT64_C(3231989760), UINT64_C(0),	// S_DCACHE_DISCARD_X2_SGPR_alt_gfx9
    UINT64_C(4104388608), UINT64_C(0),	// S_DCACHE_DISCARD_X2_SGPR_gfx10
    UINT64_C(3231973376), UINT64_C(0),	// S_DCACHE_DISCARD_X2_SGPR_vi
    UINT64_C(3342860288), UINT64_C(0),	// S_DCACHE_INV_VOL_ci
    UINT64_C(3230138368), UINT64_C(0),	// S_DCACHE_INV_VOL_vi
    UINT64_C(4102029312), UINT64_C(0),	// S_DCACHE_INV_gfx10
    UINT64_C(4102291456), UINT64_C(0),	// S_DCACHE_INV_gfx11
    UINT64_C(4093911040), UINT64_C(0),	// S_DCACHE_INV_gfx12
    UINT64_C(3351248896), UINT64_C(0),	// S_DCACHE_INV_si
    UINT64_C(3229614080), UINT64_C(0),	// S_DCACHE_INV_vi
    UINT64_C(3230400512), UINT64_C(0),	// S_DCACHE_WB_VOL_vi
    UINT64_C(4102291456), UINT64_C(0),	// S_DCACHE_WB_gfx10
    UINT64_C(3229876224), UINT64_C(0),	// S_DCACHE_WB_vi
    UINT64_C(3214213120), UINT64_C(0),	// S_DECPERFLEVEL_gfx10
    UINT64_C(3216572416), UINT64_C(0),	// S_DECPERFLEVEL_gfx11
    UINT64_C(3216572416), UINT64_C(0),	// S_DECPERFLEVEL_gfx12
    UINT64_C(3214213120), UINT64_C(0),	// S_DECPERFLEVEL_gfx6_gfx7
    UINT64_C(3214213120), UINT64_C(0),	// S_DECPERFLEVEL_vi
    UINT64_C(3213295616), UINT64_C(0),	// S_DELAY_ALU_gfx11
    UINT64_C(3213295616), UINT64_C(0),	// S_DELAY_ALU_gfx12
    UINT64_C(3215261696), UINT64_C(0),	// S_DENORM_MODE_gfx10
    UINT64_C(3214016512), UINT64_C(0),	// S_DENORM_MODE_gfx11
    UINT64_C(3214016512), UINT64_C(0),	// S_DENORM_MODE_gfx12
    UINT64_C(3214802944), UINT64_C(0),	// S_ENDPGM_ORDERED_PS_DONE_gfx10
    UINT64_C(3216113664), UINT64_C(0),	// S_ENDPGM_ORDERED_PS_DONE_gfx11
    UINT64_C(3214802944), UINT64_C(0),	// S_ENDPGM_ORDERED_PS_DONE_vi
    UINT64_C(3214606336), UINT64_C(0),	// S_ENDPGM_SAVED_gfx10
    UINT64_C(3216048128), UINT64_C(0),	// S_ENDPGM_SAVED_gfx11
    UINT64_C(3216048128), UINT64_C(0),	// S_ENDPGM_SAVED_gfx12
    UINT64_C(3214606336), UINT64_C(0),	// S_ENDPGM_SAVED_gfx6_gfx7
    UINT64_C(3214606336), UINT64_C(0),	// S_ENDPGM_SAVED_vi
    UINT64_C(3212902400), UINT64_C(0),	// S_ENDPGM_gfx10
    UINT64_C(3215982592), UINT64_C(0),	// S_ENDPGM_gfx11
    UINT64_C(3215982592), UINT64_C(0),	// S_ENDPGM_gfx12
    UINT64_C(3212902400), UINT64_C(0),	// S_ENDPGM_gfx6_gfx7
    UINT64_C(3212902400), UINT64_C(0),	// S_ENDPGM_vi
    UINT64_C(3196064000), UINT64_C(0),	// S_FF0_I32_B32_gfx10
    UINT64_C(3196064000), UINT64_C(0),	// S_FF0_I32_B32_gfx6_gfx7
    UINT64_C(3196063232), UINT64_C(0),	// S_FF0_I32_B32_vi
    UINT64_C(3196064256), UINT64_C(0),	// S_FF0_I32_B64_gfx10
    UINT64_C(3196064256), UINT64_C(0),	// S_FF0_I32_B64_gfx6_gfx7
    UINT64_C(3196063488), UINT64_C(0),	// S_FF0_I32_B64_vi
    UINT64_C(3196064512), UINT64_C(0),	// S_FF1_I32_B32_gfx10
    UINT64_C(3196061696), UINT64_C(0),	// S_FF1_I32_B32_gfx11
    UINT64_C(3196061696), UINT64_C(0),	// S_FF1_I32_B32_gfx12
    UINT64_C(3196064512), UINT64_C(0),	// S_FF1_I32_B32_gfx6_gfx7
    UINT64_C(3196063744), UINT64_C(0),	// S_FF1_I32_B32_vi
    UINT64_C(3196064768), UINT64_C(0),	// S_FF1_I32_B64_gfx10
    UINT64_C(3196061952), UINT64_C(0),	// S_FF1_I32_B64_gfx11
    UINT64_C(3196061952), UINT64_C(0),	// S_FF1_I32_B64_gfx12
    UINT64_C(3196064768), UINT64_C(0),	// S_FF1_I32_B64_gfx6_gfx7
    UINT64_C(3196064000), UINT64_C(0),	// S_FF1_I32_B64_vi
    UINT64_C(3196065024), UINT64_C(0),	// S_FLBIT_I32_B32_gfx10
    UINT64_C(3196062208), UINT64_C(0),	// S_FLBIT_I32_B32_gfx11
    UINT64_C(3196062208), UINT64_C(0),	// S_FLBIT_I32_B32_gfx12
    UINT64_C(3196065024), UINT64_C(0),	// S_FLBIT_I32_B32_gfx6_gfx7
    UINT64_C(3196064256), UINT64_C(0),	// S_FLBIT_I32_B32_vi
    UINT64_C(3196065280), UINT64_C(0),	// S_FLBIT_I32_B64_gfx10
    UINT64_C(3196062464), UINT64_C(0),	// S_FLBIT_I32_B64_gfx11
    UINT64_C(3196062464), UINT64_C(0),	// S_FLBIT_I32_B64_gfx12
    UINT64_C(3196065280), UINT64_C(0),	// S_FLBIT_I32_B64_gfx6_gfx7
    UINT64_C(3196064512), UINT64_C(0),	// S_FLBIT_I32_B64_vi
    UINT64_C(3196065792), UINT64_C(0),	// S_FLBIT_I32_I64_gfx10
    UINT64_C(3196062976), UINT64_C(0),	// S_FLBIT_I32_I64_gfx11
    UINT64_C(3196062976), UINT64_C(0),	// S_FLBIT_I32_I64_gfx12
    UINT64_C(3196065792), UINT64_C(0),	// S_FLBIT_I32_I64_gfx6_gfx7
    UINT64_C(3196065024), UINT64_C(0),	// S_FLBIT_I32_I64_vi
    UINT64_C(3196065536), UINT64_C(0),	// S_FLBIT_I32_gfx10
    UINT64_C(3196062720), UINT64_C(0),	// S_FLBIT_I32_gfx11
    UINT64_C(3196062720), UINT64_C(0),	// S_FLBIT_I32_gfx12
    UINT64_C(3196065536), UINT64_C(0),	// S_FLBIT_I32_gfx6_gfx7
    UINT64_C(3196064768), UINT64_C(0),	// S_FLBIT_I32_vi
    UINT64_C(3196087296), UINT64_C(0),	// S_FLOOR_F16_gfx11
    UINT64_C(3196087296), UINT64_C(0),	// S_FLOOR_F16_gfx12
    UINT64_C(3196084480), UINT64_C(0),	// S_FLOOR_F32_gfx11
    UINT64_C(3196084480), UINT64_C(0),	// S_FLOOR_F32_gfx12
    UINT64_C(2726297600), UINT64_C(0),	// S_FMAAK_F32_gfx11
    UINT64_C(2726297600), UINT64_C(0),	// S_FMAAK_F32_gfx12
    UINT64_C(2801795072), UINT64_C(0),	// S_FMAC_F16_gfx11
    UINT64_C(2801795072), UINT64_C(0),	// S_FMAC_F16_gfx12
    UINT64_C(2743074816), UINT64_C(0),	// S_FMAC_F32_gfx11
    UINT64_C(2743074816), UINT64_C(0),	// S_FMAC_F32_gfx12
    UINT64_C(2734686208), UINT64_C(0),	// S_FMAMK_F32_gfx11
    UINT64_C(2734686208), UINT64_C(0),	// S_FMAMK_F32_gfx12
    UINT64_C(3196067584), UINT64_C(0),	// S_GETPC_B64_gfx10
    UINT64_C(3196077824), UINT64_C(0),	// S_GETPC_B64_gfx11
    UINT64_C(3196077824), UINT64_C(0),	// S_GETPC_B64_gfx12
    UINT64_C(3196077824), UINT64_C(0),	// S_GETPC_B64_gfx1250
    UINT64_C(3196067584), UINT64_C(0),	// S_GETPC_B64_gfx6_gfx7
    UINT64_C(3196066816), UINT64_C(0),	// S_GETPC_B64_vi
    UINT64_C(3103784960), UINT64_C(0),	// S_GETREG_B32_gfx10
    UINT64_C(3095396352), UINT64_C(0),	// S_GETREG_B32_gfx11
    UINT64_C(3095396352), UINT64_C(0),	// S_GETREG_B32_gfx12
    UINT64_C(3103784960), UINT64_C(0),	// S_GETREG_B32_gfx6_gfx7
    UINT64_C(3095396352), UINT64_C(0),	// S_GETREG_B32_vi
    UINT64_C(3196080128), UINT64_C(0),	// S_GET_BARRIER_STATE_IMM_gfx12
    UINT64_C(3196080253), UINT64_C(0),	// S_GET_BARRIER_STATE_M0_gfx12
    UINT64_C(3196061184), UINT64_C(0),	// S_GET_SHADER_CYCLES_U64_gfx12
    UINT64_C(4104650752), UINT64_C(0),	// S_GET_WAVEID_IN_WORKGROUP_gfx10
    UINT64_C(4101767168), UINT64_C(0),	// S_GL1_INV_gfx10
    UINT64_C(4102029312), UINT64_C(0),	// S_GL1_INV_gfx11
    UINT64_C(3214082048), UINT64_C(0),	// S_ICACHE_INV_gfx10
    UINT64_C(3216769024), UINT64_C(0),	// S_ICACHE_INV_gfx11
    UINT64_C(3216769024), UINT64_C(0),	// S_ICACHE_INV_gfx12
    UINT64_C(3214082048), UINT64_C(0),	// S_ICACHE_INV_gfx6_gfx7
    UINT64_C(3214082048), UINT64_C(0),	// S_ICACHE_INV_vi
    UINT64_C(3214147584), UINT64_C(0),	// S_INCPERFLEVEL_gfx10
    UINT64_C(3216506880), UINT64_C(0),	// S_INCPERFLEVEL_gfx11
    UINT64_C(3216506880), UINT64_C(0),	// S_INCPERFLEVEL_gfx12
    UINT64_C(3214147584), UINT64_C(0),	// S_INCPERFLEVEL_gfx6_gfx7
    UINT64_C(3214147584), UINT64_C(0),	// S_INCPERFLEVEL_vi
    UINT64_C(3214934016), UINT64_C(0),	// S_INST_PREFETCH_gfx10
    UINT64_C(3213099008), UINT64_C(0),	// S_INST_PREFETCH_gfx11
    UINT64_C(17870283325500293120), UINT64_C(0),	// S_LOAD_B128_IMM_gfx11
    UINT64_C(17870283325499785216), UINT64_C(0),	// S_LOAD_B128_IMM_gfx12
    UINT64_C(4094164992), UINT64_C(0),	// S_LOAD_B128_SGPR_IMM_gfx11
    UINT64_C(4093657088), UINT64_C(0),	// S_LOAD_B128_SGPR_IMM_gfx12
    UINT64_C(4094164992), UINT64_C(0),	// S_LOAD_B128_SGPR_gfx11
    UINT64_C(17870283325500555264), UINT64_C(0),	// S_LOAD_B256_IMM_gfx11
    UINT64_C(17870283325499793408), UINT64_C(0),	// S_LOAD_B256_IMM_gfx12
    UINT64_C(4094427136), UINT64_C(0),	// S_LOAD_B256_SGPR_IMM_gfx11
    UINT64_C(4093665280), UINT64_C(0),	// S_LOAD_B256_SGPR_IMM_gfx12
    UINT64_C(4094427136), UINT64_C(0),	// S_LOAD_B256_SGPR_gfx11
    UINT64_C(17870283325499768832), UINT64_C(0),	// S_LOAD_B32_IMM_gfx11
    UINT64_C(17870283325499768832), UINT64_C(0),	// S_LOAD_B32_IMM_gfx12
    UINT64_C(4093640704), UINT64_C(0),	// S_LOAD_B32_SGPR_IMM_gfx11
    UINT64_C(4093640704), UINT64_C(0),	// S_LOAD_B32_SGPR_IMM_gfx12
    UINT64_C(4093640704), UINT64_C(0),	// S_LOAD_B32_SGPR_gfx11
    UINT64_C(17870283325500817408), UINT64_C(0),	// S_LOAD_B512_IMM_gfx11
    UINT64_C(17870283325499801600), UINT64_C(0),	// S_LOAD_B512_IMM_gfx12
    UINT64_C(4094689280), UINT64_C(0),	// S_LOAD_B512_SGPR_IMM_gfx11
    UINT64_C(4093673472), UINT64_C(0),	// S_LOAD_B512_SGPR_IMM_gfx12
    UINT64_C(4094689280), UINT64_C(0),	// S_LOAD_B512_SGPR_gfx11
    UINT64_C(17870283325500030976), UINT64_C(0),	// S_LOAD_B64_IMM_gfx11
    UINT64_C(17870283325499777024), UINT64_C(0),	// S_LOAD_B64_IMM_gfx12
    UINT64_C(4093902848), UINT64_C(0),	// S_LOAD_B64_SGPR_IMM_gfx11
    UINT64_C(4093648896), UINT64_C(0),	// S_LOAD_B64_SGPR_IMM_gfx12
    UINT64_C(4093902848), UINT64_C(0),	// S_LOAD_B64_SGPR_gfx11
    UINT64_C(17870283325499809792), UINT64_C(0),	// S_LOAD_B96_IMM_gfx12
    UINT64_C(4093681664), UINT64_C(0),	// S_LOAD_B96_SGPR_IMM_gfx12
    UINT64_C(3238002943), UINT64_C(0),	// S_LOAD_DWORDX16_IMM_ci
    UINT64_C(18014398513576673280), UINT64_C(0),	// S_LOAD_DWORDX16_IMM_gfx10
    UINT64_C(3238002944), UINT64_C(0),	// S_LOAD_DWORDX16_IMM_si
    UINT64_C(3222405120), UINT64_C(0),	// S_LOAD_DWORDX16_IMM_vi
    UINT64_C(4094689280), UINT64_C(0),	// S_LOAD_DWORDX16_SGPR_IMM_gfx10
    UINT64_C(3222421504), UINT64_C(0),	// S_LOAD_DWORDX16_SGPR_IMM_gfx9
    UINT64_C(3222290432), UINT64_C(0),	// S_LOAD_DWORDX16_SGPR_alt_gfx9
    UINT64_C(4094689280), UINT64_C(0),	// S_LOAD_DWORDX16_SGPR_gfx10
    UINT64_C(3238002688), UINT64_C(0),	// S_LOAD_DWORDX16_SGPR_si
    UINT64_C(3222274048), UINT64_C(0),	// S_LOAD_DWORDX16_SGPR_vi
    UINT64_C(3225420031), UINT64_C(0),	// S_LOAD_DWORDX2_IMM_ci
    UINT64_C(18014398513575886848), UINT64_C(0),	// S_LOAD_DWORDX2_IMM_gfx10
    UINT64_C(3225420032), UINT64_C(0),	// S_LOAD_DWORDX2_IMM_si
    UINT64_C(3221618688), UINT64_C(0),	// S_LOAD_DWORDX2_IMM_vi
    UINT64_C(4093902848), UINT64_C(0),	// S_LOAD_DWORDX2_SGPR_IMM_gfx10
    UINT64_C(3221635072), UINT64_C(0),	// S_LOAD_DWORDX2_SGPR_IMM_gfx9
    UINT64_C(3221504000), UINT64_C(0),	// S_LOAD_DWORDX2_SGPR_alt_gfx9
    UINT64_C(4093902848), UINT64_C(0),	// S_LOAD_DWORDX2_SGPR_gfx10
    UINT64_C(3225419776), UINT64_C(0),	// S_LOAD_DWORDX2_SGPR_si
    UINT64_C(3221487616), UINT64_C(0),	// S_LOAD_DWORDX2_SGPR_vi
    UINT64_C(3229614335), UINT64_C(0),	// S_LOAD_DWORDX4_IMM_ci
    UINT64_C(18014398513576148992), UINT64_C(0),	// S_LOAD_DWORDX4_IMM_gfx10
    UINT64_C(3229614336), UINT64_C(0),	// S_LOAD_DWORDX4_IMM_si
    UINT64_C(3221880832), UINT64_C(0),	// S_LOAD_DWORDX4_IMM_vi
    UINT64_C(4094164992), UINT64_C(0),	// S_LOAD_DWORDX4_SGPR_IMM_gfx10
    UINT64_C(3221897216), UINT64_C(0),	// S_LOAD_DWORDX4_SGPR_IMM_gfx9
    UINT64_C(3221766144), UINT64_C(0),	// S_LOAD_DWORDX4_SGPR_alt_gfx9
    UINT64_C(4094164992), UINT64_C(0),	// S_LOAD_DWORDX4_SGPR_gfx10
    UINT64_C(3229614080), UINT64_C(0),	// S_LOAD_DWORDX4_SGPR_si
    UINT64_C(3221749760), UINT64_C(0),	// S_LOAD_DWORDX4_SGPR_vi
    UINT64_C(3233808639), UINT64_C(0),	// S_LOAD_DWORDX8_IMM_ci
    UINT64_C(18014398513576411136), UINT64_C(0),	// S_LOAD_DWORDX8_IMM_gfx10
    UINT64_C(3233808640), UINT64_C(0),	// S_LOAD_DWORDX8_IMM_si
    UINT64_C(3222142976), UINT64_C(0),	// S_LOAD_DWORDX8_IMM_vi
    UINT64_C(4094427136), UINT64_C(0),	// S_LOAD_DWORDX8_SGPR_IMM_gfx10
    UINT64_C(3222159360), UINT64_C(0),	// S_LOAD_DWORDX8_SGPR_IMM_gfx9
    UINT64_C(3222028288), UINT64_C(0),	// S_LOAD_DWORDX8_SGPR_alt_gfx9
    UINT64_C(4094427136), UINT64_C(0),	// S_LOAD_DWORDX8_SGPR_gfx10
    UINT64_C(3233808384), UINT64_C(0),	// S_LOAD_DWORDX8_SGPR_si
    UINT64_C(3222011904), UINT64_C(0),	// S_LOAD_DWORDX8_SGPR_vi
    UINT64_C(3221225727), UINT64_C(0),	// S_LOAD_DWORD_IMM_ci
    UINT64_C(18014398513575624704), UINT64_C(0),	// S_LOAD_DWORD_IMM_gfx10
    UINT64_C(3221225728), UINT64_C(0),	// S_LOAD_DWORD_IMM_si
    UINT64_C(3221356544), UINT64_C(0),	// S_LOAD_DWORD_IMM_vi
    UINT64_C(4093640704), UINT64_C(0),	// S_LOAD_DWORD_SGPR_IMM_gfx10
    UINT64_C(3221372928), UINT64_C(0),	// S_LOAD_DWORD_SGPR_IMM_gfx9
    UINT64_C(3221241856), UINT64_C(0),	// S_LOAD_DWORD_SGPR_alt_gfx9
    UINT64_C(4093640704), UINT64_C(0),	// S_LOAD_DWORD_SGPR_gfx10
    UINT64_C(3221225472), UINT64_C(0),	// S_LOAD_DWORD_SGPR_si
    UINT64_C(3221225472), UINT64_C(0),	// S_LOAD_DWORD_SGPR_vi
    UINT64_C(17870283325499850752), UINT64_C(0),	// S_LOAD_I16_IMM_gfx12
    UINT64_C(4093722624), UINT64_C(0),	// S_LOAD_I16_SGPR_IMM_gfx12
    UINT64_C(17870283325499834368), UINT64_C(0),	// S_LOAD_I8_IMM_gfx12
    UINT64_C(4093706240), UINT64_C(0),	// S_LOAD_I8_SGPR_IMM_gfx12
    UINT64_C(17870283325499858944), UINT64_C(0),	// S_LOAD_U16_IMM_gfx12
    UINT64_C(4093730816), UINT64_C(0),	// S_LOAD_U16_SGPR_IMM_gfx12
    UINT64_C(17870283325499842560), UINT64_C(0),	// S_LOAD_U8_IMM_gfx12
    UINT64_C(4093714432), UINT64_C(0),	// S_LOAD_U8_SGPR_IMM_gfx12
    UINT64_C(2533359616), UINT64_C(0),	// S_LSHL1_ADD_U32_gfx10
    UINT64_C(2264924160), UINT64_C(0),	// S_LSHL1_ADD_U32_gfx11
    UINT64_C(2264924160), UINT64_C(0),	// S_LSHL1_ADD_U32_gfx12
    UINT64_C(2533359616), UINT64_C(0),	// S_LSHL1_ADD_U32_vi
    UINT64_C(2541748224), UINT64_C(0),	// S_LSHL2_ADD_U32_gfx10
    UINT64_C(2273312768), UINT64_C(0),	// S_LSHL2_ADD_U32_gfx11
    UINT64_C(2273312768), UINT64_C(0),	// S_LSHL2_ADD_U32_gfx12
    UINT64_C(2541748224), UINT64_C(0),	// S_LSHL2_ADD_U32_vi
    UINT64_C(2550136832), UINT64_C(0),	// S_LSHL3_ADD_U32_gfx10
    UINT64_C(2281701376), UINT64_C(0),	// S_LSHL3_ADD_U32_gfx11
    UINT64_C(2281701376), UINT64_C(0),	// S_LSHL3_ADD_U32_gfx12
    UINT64_C(2550136832), UINT64_C(0),	// S_LSHL3_ADD_U32_vi
    UINT64_C(2558525440), UINT64_C(0),	// S_LSHL4_ADD_U32_gfx10
    UINT64_C(2290089984), UINT64_C(0),	// S_LSHL4_ADD_U32_gfx11
    UINT64_C(2290089984), UINT64_C(0),	// S_LSHL4_ADD_U32_gfx12
    UINT64_C(2558525440), UINT64_C(0),	// S_LSHL4_ADD_U32_vi
    UINT64_C(2399141888), UINT64_C(0),	// S_LSHL_B32_gfx10
    UINT64_C(2214592512), UINT64_C(0),	// S_LSHL_B32_gfx11
    UINT64_C(2214592512), UINT64_C(0),	// S_LSHL_B32_gfx12
    UINT64_C(2399141888), UINT64_C(0),	// S_LSHL_B32_gfx6_gfx7
    UINT64_C(2382364672), UINT64_C(0),	// S_LSHL_B32_vi
    UINT64_C(2407530496), UINT64_C(0),	// S_LSHL_B64_gfx10
    UINT64_C(2222981120), UINT64_C(0),	// S_LSHL_B64_gfx11
    UINT64_C(2222981120), UINT64_C(0),	// S_LSHL_B64_gfx12
    UINT64_C(2407530496), UINT64_C(0),	// S_LSHL_B64_gfx6_gfx7
    UINT64_C(2390753280), UINT64_C(0),	// S_LSHL_B64_vi
    UINT64_C(2415919104), UINT64_C(0),	// S_LSHR_B32_gfx10
    UINT64_C(2231369728), UINT64_C(0),	// S_LSHR_B32_gfx11
    UINT64_C(2231369728), UINT64_C(0),	// S_LSHR_B32_gfx12
    UINT64_C(2415919104), UINT64_C(0),	// S_LSHR_B32_gfx6_gfx7
    UINT64_C(2399141888), UINT64_C(0),	// S_LSHR_B32_vi
    UINT64_C(2424307712), UINT64_C(0),	// S_LSHR_B64_gfx10
    UINT64_C(2239758336), UINT64_C(0),	// S_LSHR_B64_gfx11
    UINT64_C(2239758336), UINT64_C(0),	// S_LSHR_B64_gfx12
    UINT64_C(2424307712), UINT64_C(0),	// S_LSHR_B64_gfx6_gfx7
    UINT64_C(2407530496), UINT64_C(0),	// S_LSHR_B64_vi
    UINT64_C(2835349504), UINT64_C(0),	// S_MAXIMUM_F16_gfx12
    UINT64_C(2818572288), UINT64_C(0),	// S_MAXIMUM_F32_gfx12
    UINT64_C(2785017856), UINT64_C(0),	// S_MAX_F16_gfx11
    UINT64_C(2785017856), UINT64_C(0),	// S_MAX_F16_gfx12
    UINT64_C(2709520384), UINT64_C(0),	// S_MAX_F32_gfx11
    UINT64_C(2709520384), UINT64_C(0),	// S_MAX_F32_gfx12
    UINT64_C(2214592512), UINT64_C(0),	// S_MAX_I32_gfx10
    UINT64_C(2315255808), UINT64_C(0),	// S_MAX_I32_gfx11
    UINT64_C(2315255808), UINT64_C(0),	// S_MAX_I32_gfx12
    UINT64_C(2214592512), UINT64_C(0),	// S_MAX_I32_gfx6_gfx7
    UINT64_C(2214592512), UINT64_C(0),	// S_MAX_I32_vi
    UINT64_C(2222981120), UINT64_C(0),	// S_MAX_U32_gfx10
    UINT64_C(2323644416), UINT64_C(0),	// S_MAX_U32_gfx11
    UINT64_C(2323644416), UINT64_C(0),	// S_MAX_U32_gfx12
    UINT64_C(2222981120), UINT64_C(0),	// S_MAX_U32_gfx6_gfx7
    UINT64_C(2222981120), UINT64_C(0),	// S_MAX_U32_vi
    UINT64_C(4103340032), UINT64_C(0),	// S_MEMREALTIME_gfx10
    UINT64_C(3230924800), UINT64_C(0),	// S_MEMREALTIME_vi
    UINT64_C(4103077888), UINT64_C(0),	// S_MEMTIME_gfx10
    UINT64_C(3347054592), UINT64_C(0),	// S_MEMTIME_si
    UINT64_C(3230662656), UINT64_C(0),	// S_MEMTIME_vi
    UINT64_C(2826960896), UINT64_C(0),	// S_MINIMUM_F16_gfx12
    UINT64_C(2810183680), UINT64_C(0),	// S_MINIMUM_F32_gfx12
    UINT64_C(2776629248), UINT64_C(0),	// S_MIN_F16_gfx11
    UINT64_C(2776629248), UINT64_C(0),	// S_MIN_F16_gfx12
    UINT64_C(2701131776), UINT64_C(0),	// S_MIN_F32_gfx11
    UINT64_C(2701131776), UINT64_C(0),	// S_MIN_F32_gfx12
    UINT64_C(2197815296), UINT64_C(0),	// S_MIN_I32_gfx10
    UINT64_C(2298478592), UINT64_C(0),	// S_MIN_I32_gfx11
    UINT64_C(2298478592), UINT64_C(0),	// S_MIN_I32_gfx12
    UINT64_C(2197815296), UINT64_C(0),	// S_MIN_I32_gfx6_gfx7
    UINT64_C(2197815296), UINT64_C(0),	// S_MIN_I32_vi
    UINT64_C(2206203904), UINT64_C(0),	// S_MIN_U32_gfx10
    UINT64_C(2306867200), UINT64_C(0),	// S_MIN_U32_gfx11
    UINT64_C(2306867200), UINT64_C(0),	// S_MIN_U32_gfx12
    UINT64_C(2206203904), UINT64_C(0),	// S_MIN_U32_gfx6_gfx7
    UINT64_C(2206203904), UINT64_C(0),	// S_MIN_U32_vi
    UINT64_C(3213099008), UINT64_C(0),	// S_MONITOR_SLEEP_gfx12
    UINT64_C(2952790016), UINT64_C(0),	// S_MOVK_I32_gfx10
    UINT64_C(2952790016), UINT64_C(0),	// S_MOVK_I32_gfx11
    UINT64_C(2952790016), UINT64_C(0),	// S_MOVK_I32_gfx12
    UINT64_C(2952790016), UINT64_C(0),	// S_MOVK_I32_gfx6_gfx7
    UINT64_C(2952790016), UINT64_C(0),	// S_MOVK_I32_vi
    UINT64_C(3196071936), UINT64_C(0),	// S_MOVRELD_B32_gfx10
    UINT64_C(3196076544), UINT64_C(0),	// S_MOVRELD_B32_gfx11
    UINT64_C(3196076544), UINT64_C(0),	// S_MOVRELD_B32_gfx12
    UINT64_C(3196071936), UINT64_C(0),	// S_MOVRELD_B32_gfx6_gfx7
    UINT64_C(3196070912), UINT64_C(0),	// S_MOVRELD_B32_vi
    UINT64_C(3196072192), UINT64_C(0),	// S_MOVRELD_B64_gfx10
    UINT64_C(3196076800), UINT64_C(0),	// S_MOVRELD_B64_gfx11
    UINT64_C(3196076800), UINT64_C(0),	// S_MOVRELD_B64_gfx12
    UINT64_C(3196072192), UINT64_C(0),	// S_MOVRELD_B64_gfx6_gfx7
    UINT64_C(3196071168), UINT64_C(0),	// S_MOVRELD_B64_vi
    UINT64_C(3196078336), UINT64_C(0),	// S_MOVRELSD_2_B32_gfx10
    UINT64_C(3196077056), UINT64_C(0),	// S_MOVRELSD_2_B32_gfx11
    UINT64_C(3196077056), UINT64_C(0),	// S_MOVRELSD_2_B32_gfx12
    UINT64_C(3196071424), UINT64_C(0),	// S_MOVRELS_B32_gfx10
    UINT64_C(3196076032), UINT64_C(0),	// S_MOVRELS_B32_gfx11
    UINT64_C(3196076032), UINT64_C(0),	// S_MOVRELS_B32_gfx12
    UINT64_C(3196071424), UINT64_C(0),	// S_MOVRELS_B32_gfx6_gfx7
    UINT64_C(3196070400), UINT64_C(0),	// S_MOVRELS_B32_vi
    UINT64_C(3196071680), UINT64_C(0),	// S_MOVRELS_B64_gfx10
    UINT64_C(3196076288), UINT64_C(0),	// S_MOVRELS_B64_gfx11
    UINT64_C(3196076288), UINT64_C(0),	// S_MOVRELS_B64_gfx12
    UINT64_C(3196071680), UINT64_C(0),	// S_MOVRELS_B64_gfx6_gfx7
    UINT64_C(3196070656), UINT64_C(0),	// S_MOVRELS_B64_vi
    UINT64_C(3196060416), UINT64_C(0),	// S_MOV_B32_gfx10
    UINT64_C(3196059648), UINT64_C(0),	// S_MOV_B32_gfx11
    UINT64_C(3196059648), UINT64_C(0),	// S_MOV_B32_gfx12
    UINT64_C(3196060416), UINT64_C(0),	// S_MOV_B32_gfx6_gfx7
    UINT64_C(3196059648), UINT64_C(0),	// S_MOV_B32_vi
    UINT64_C(3196060672), UINT64_C(0),	// S_MOV_B64_gfx10
    UINT64_C(3196059904), UINT64_C(0),	// S_MOV_B64_gfx11
    UINT64_C(3196059904), UINT64_C(0),	// S_MOV_B64_gfx12
    UINT64_C(3196060672), UINT64_C(0),	// S_MOV_B64_gfx6_gfx7
    UINT64_C(3196059904), UINT64_C(0),	// S_MOV_B64_vi
    UINT64_C(3087007744), UINT64_C(0),	// S_MULK_I32_gfx10
    UINT64_C(3087007744), UINT64_C(0),	// S_MULK_I32_gfx11
    UINT64_C(3087007744), UINT64_C(0),	// S_MULK_I32_gfx12
    UINT64_C(3087007744), UINT64_C(0),	// S_MULK_I32_gfx6_gfx7
    UINT64_C(3078619136), UINT64_C(0),	// S_MULK_I32_vi
    UINT64_C(2793406464), UINT64_C(0),	// S_MUL_F16_gfx11
    UINT64_C(2793406464), UINT64_C(0),	// S_MUL_F16_gfx12
    UINT64_C(2717908992), UINT64_C(0),	// S_MUL_F32_gfx11
    UINT64_C(2717908992), UINT64_C(0),	// S_MUL_F32_gfx12
    UINT64_C(2600468480), UINT64_C(0),	// S_MUL_HI_I32_gfx10
    UINT64_C(2533359616), UINT64_C(0),	// S_MUL_HI_I32_gfx11
    UINT64_C(2533359616), UINT64_C(0),	// S_MUL_HI_I32_gfx12
    UINT64_C(2524971008), UINT64_C(0),	// S_MUL_HI_I32_vi
    UINT64_C(2592079872), UINT64_C(0),	// S_MUL_HI_U32_gfx10
    UINT64_C(2524971008), UINT64_C(0),	// S_MUL_HI_U32_gfx11
    UINT64_C(2524971008), UINT64_C(0),	// S_MUL_HI_U32_gfx12
    UINT64_C(2516582400), UINT64_C(0),	// S_MUL_HI_U32_vi
    UINT64_C(2466250752), UINT64_C(0),	// S_MUL_I32_gfx10
    UINT64_C(2516582400), UINT64_C(0),	// S_MUL_I32_gfx11
    UINT64_C(2516582400), UINT64_C(0),	// S_MUL_I32_gfx12
    UINT64_C(2466250752), UINT64_C(0),	// S_MUL_I32_gfx6_gfx7
    UINT64_C(2449473536), UINT64_C(0),	// S_MUL_I32_vi
    UINT64_C(2860515328), UINT64_C(0),	// S_MUL_U64_gfx12
    UINT64_C(2348810240), UINT64_C(0),	// S_NAND_B32_gfx10
    UINT64_C(2382364672), UINT64_C(0),	// S_NAND_B32_gfx11
    UINT64_C(2382364672), UINT64_C(0),	// S_NAND_B32_gfx12
    UINT64_C(2348810240), UINT64_C(0),	// S_NAND_B32_gfx6_gfx7
    UINT64_C(2332033024), UINT64_C(0),	// S_NAND_B32_vi
    UINT64_C(2357198848), UINT64_C(0),	// S_NAND_B64_gfx10
    UINT64_C(2390753280), UINT64_C(0),	// S_NAND_B64_gfx11
    UINT64_C(2390753280), UINT64_C(0),	// S_NAND_B64_gfx12
    UINT64_C(2357198848), UINT64_C(0),	// S_NAND_B64_gfx6_gfx7
    UINT64_C(2340421632), UINT64_C(0),	// S_NAND_B64_vi
    UINT64_C(3196076288), UINT64_C(0),	// S_NAND_SAVEEXEC_B32_gfx10
    UINT64_C(3196069376), UINT64_C(0),	// S_NAND_SAVEEXEC_B32_gfx11
    UINT64_C(3196069376), UINT64_C(0),	// S_NAND_SAVEEXEC_B32_gfx12
    UINT64_C(3196070144), UINT64_C(0),	// S_NAND_SAVEEXEC_B64_gfx10
    UINT64_C(3196069632), UINT64_C(0),	// S_NAND_SAVEEXEC_B64_gfx11
    UINT64_C(3196069632), UINT64_C(0),	// S_NAND_SAVEEXEC_B64_gfx12
    UINT64_C(3196070144), UINT64_C(0),	// S_NAND_SAVEEXEC_B64_gfx6_gfx7
    UINT64_C(3196069120), UINT64_C(0),	// S_NAND_SAVEEXEC_B64_vi
    UINT64_C(3212836864), UINT64_C(0),	// S_NOP_gfx10
    UINT64_C(3212836864), UINT64_C(0),	// S_NOP_gfx11
    UINT64_C(3212836864), UINT64_C(0),	// S_NOP_gfx12
    UINT64_C(3212836864), UINT64_C(0),	// S_NOP_gfx6_gfx7
    UINT64_C(3212836864), UINT64_C(0),	// S_NOP_vi
    UINT64_C(2365587456), UINT64_C(0),	// S_NOR_B32_gfx10
    UINT64_C(2399141888), UINT64_C(0),	// S_NOR_B32_gfx11
    UINT64_C(2399141888), UINT64_C(0),	// S_NOR_B32_gfx12
    UINT64_C(2365587456), UINT64_C(0),	// S_NOR_B32_gfx6_gfx7
    UINT64_C(2348810240), UINT64_C(0),	// S_NOR_B32_vi
    UINT64_C(2373976064), UINT64_C(0),	// S_NOR_B64_gfx10
    UINT64_C(2407530496), UINT64_C(0),	// S_NOR_B64_gfx11
    UINT64_C(2407530496), UINT64_C(0),	// S_NOR_B64_gfx12
    UINT64_C(2373976064), UINT64_C(0),	// S_NOR_B64_gfx6_gfx7
    UINT64_C(2357198848), UINT64_C(0),	// S_NOR_B64_vi
    UINT64_C(3196076544), UINT64_C(0),	// S_NOR_SAVEEXEC_B32_gfx10
    UINT64_C(3196069888), UINT64_C(0),	// S_NOR_SAVEEXEC_B32_gfx11
    UINT64_C(3196069888), UINT64_C(0),	// S_NOR_SAVEEXEC_B32_gfx12
    UINT64_C(3196070400), UINT64_C(0),	// S_NOR_SAVEEXEC_B64_gfx10
    UINT64_C(3196070144), UINT64_C(0),	// S_NOR_SAVEEXEC_B64_gfx11
    UINT64_C(3196070144), UINT64_C(0),	// S_NOR_SAVEEXEC_B64_gfx12
    UINT64_C(3196070400), UINT64_C(0),	// S_NOR_SAVEEXEC_B64_gfx6_gfx7
    UINT64_C(3196069376), UINT64_C(0),	// S_NOR_SAVEEXEC_B64_vi
    UINT64_C(3196061440), UINT64_C(0),	// S_NOT_B32_gfx10
    UINT64_C(3196067328), UINT64_C(0),	// S_NOT_B32_gfx11
    UINT64_C(3196067328), UINT64_C(0),	// S_NOT_B32_gfx12
    UINT64_C(3196061440), UINT64_C(0),	// S_NOT_B32_gfx6_gfx7
    UINT64_C(3196060672), UINT64_C(0),	// S_NOT_B32_vi
    UINT64_C(3196061696), UINT64_C(0),	// S_NOT_B64_gfx10
    UINT64_C(3196067584), UINT64_C(0),	// S_NOT_B64_gfx11
    UINT64_C(3196067584), UINT64_C(0),	// S_NOT_B64_gfx12
    UINT64_C(3196061696), UINT64_C(0),	// S_NOT_B64_gfx6_gfx7
    UINT64_C(3196060928), UINT64_C(0),	// S_NOT_B64_vi
    UINT64_C(3196077312), UINT64_C(0),	// S_ORN1_SAVEEXEC_B32_gfx10
    UINT64_C(3196071424), UINT64_C(0),	// S_ORN1_SAVEEXEC_B32_gfx11
    UINT64_C(3196071424), UINT64_C(0),	// S_ORN1_SAVEEXEC_B32_gfx12
    UINT64_C(3196073984), UINT64_C(0),	// S_ORN1_SAVEEXEC_B64_gfx10
    UINT64_C(3196071680), UINT64_C(0),	// S_ORN1_SAVEEXEC_B64_gfx11
    UINT64_C(3196071680), UINT64_C(0),	// S_ORN1_SAVEEXEC_B64_gfx12
    UINT64_C(3196072960), UINT64_C(0),	// S_ORN1_SAVEEXEC_B64_vi
    UINT64_C(2332033024), UINT64_C(0),	// S_ORN2_B32_gfx10
    UINT64_C(2449473536), UINT64_C(0),	// S_ORN2_B32_gfx11
    UINT64_C(2449473536), UINT64_C(0),	// S_ORN2_B32_gfx12
    UINT64_C(2332033024), UINT64_C(0),	// S_ORN2_B32_gfx6_gfx7
    UINT64_C(2315255808), UINT64_C(0),	// S_ORN2_B32_vi
    UINT64_C(2340421632), UINT64_C(0),	// S_ORN2_B64_gfx10
    UINT64_C(2457862144), UINT64_C(0),	// S_ORN2_B64_gfx11
    UINT64_C(2457862144), UINT64_C(0),	// S_ORN2_B64_gfx12
    UINT64_C(2340421632), UINT64_C(0),	// S_ORN2_B64_gfx6_gfx7
    UINT64_C(2323644416), UINT64_C(0),	// S_ORN2_B64_vi
    UINT64_C(3196076032), UINT64_C(0),	// S_ORN2_SAVEEXEC_B32_gfx10
    UINT64_C(3196072448), UINT64_C(0),	// S_ORN2_SAVEEXEC_B32_gfx11
    UINT64_C(3196072448), UINT64_C(0),	// S_ORN2_SAVEEXEC_B32_gfx12
    UINT64_C(3196069888), UINT64_C(0),	// S_ORN2_SAVEEXEC_B64_gfx10
    UINT64_C(3196072704), UINT64_C(0),	// S_ORN2_SAVEEXEC_B64_gfx11
    UINT64_C(3196072704), UINT64_C(0),	// S_ORN2_SAVEEXEC_B64_gfx12
    UINT64_C(3196069888), UINT64_C(0),	// S_ORN2_SAVEEXEC_B64_gfx6_gfx7
    UINT64_C(3196068864), UINT64_C(0),	// S_ORN2_SAVEEXEC_B64_vi
    UINT64_C(2281701376), UINT64_C(0),	// S_OR_B32_gfx10
    UINT64_C(2348810240), UINT64_C(0),	// S_OR_B32_gfx11
    UINT64_C(2348810240), UINT64_C(0),	// S_OR_B32_gfx12
    UINT64_C(2281701376), UINT64_C(0),	// S_OR_B32_gfx6_gfx7
    UINT64_C(2264924160), UINT64_C(0),	// S_OR_B32_vi
    UINT64_C(2290089984), UINT64_C(0),	// S_OR_B64_gfx10
    UINT64_C(2357198848), UINT64_C(0),	// S_OR_B64_gfx11
    UINT64_C(2357198848), UINT64_C(0),	// S_OR_B64_gfx12
    UINT64_C(2290089984), UINT64_C(0),	// S_OR_B64_gfx6_gfx7
    UINT64_C(2273312768), UINT64_C(0),	// S_OR_B64_vi
    UINT64_C(3196075264), UINT64_C(0),	// S_OR_SAVEEXEC_B32_gfx10
    UINT64_C(3196068352), UINT64_C(0),	// S_OR_SAVEEXEC_B32_gfx11
    UINT64_C(3196068352), UINT64_C(0),	// S_OR_SAVEEXEC_B32_gfx12
    UINT64_C(3196069120), UINT64_C(0),	// S_OR_SAVEEXEC_B64_gfx10
    UINT64_C(3196068608), UINT64_C(0),	// S_OR_SAVEEXEC_B64_gfx11
    UINT64_C(3196068608), UINT64_C(0),	// S_OR_SAVEEXEC_B64_gfx12
    UINT64_C(3196069120), UINT64_C(0),	// S_OR_SAVEEXEC_B64_gfx6_gfx7
    UINT64_C(3196068096), UINT64_C(0),	// S_OR_SAVEEXEC_B64_vi
    UINT64_C(2583691264), UINT64_C(0),	// S_PACK_HH_B32_B16_gfx10
    UINT64_C(2583691264), UINT64_C(0),	// S_PACK_HH_B32_B16_gfx11
    UINT64_C(2583691264), UINT64_C(0),	// S_PACK_HH_B32_B16_gfx12
    UINT64_C(2583691264), UINT64_C(0),	// S_PACK_HH_B32_B16_vi
    UINT64_C(2592079872), UINT64_C(0),	// S_PACK_HL_B32_B16_gfx11
    UINT64_C(2592079872), UINT64_C(0),	// S_PACK_HL_B32_B16_gfx12
    UINT64_C(2575302656), UINT64_C(0),	// S_PACK_LH_B32_B16_gfx10
    UINT64_C(2575302656), UINT64_C(0),	// S_PACK_LH_B32_B16_gfx11
    UINT64_C(2575302656), UINT64_C(0),	// S_PACK_LH_B32_B16_gfx12
    UINT64_C(2575302656), UINT64_C(0),	// S_PACK_LH_B32_B16_vi
    UINT64_C(2566914048), UINT64_C(0),	// S_PACK_LL_B32_B16_gfx10
    UINT64_C(2566914048), UINT64_C(0),	// S_PACK_LL_B32_B16_gfx11
    UINT64_C(2566914048), UINT64_C(0),	// S_PACK_LL_B32_B16_gfx12
    UINT64_C(2566914048), UINT64_C(0),	// S_PACK_LL_B32_B16_vi
    UINT64_C(4093968384), UINT64_C(0),	// S_PREFETCH_DATA_PC_REL_gfx12
    UINT64_C(4093952000), UINT64_C(0),	// S_PREFETCH_DATA_gfx12
    UINT64_C(4093943808), UINT64_C(0),	// S_PREFETCH_INST_PC_REL_gfx12
    UINT64_C(4093935616), UINT64_C(0),	// S_PREFETCH_INST_gfx12
    UINT64_C(3196070912), UINT64_C(0),	// S_QUADMASK_B32_gfx10
    UINT64_C(3196066304), UINT64_C(0),	// S_QUADMASK_B32_gfx11
    UINT64_C(3196066304), UINT64_C(0),	// S_QUADMASK_B32_gfx12
    UINT64_C(3196070912), UINT64_C(0),	// S_QUADMASK_B32_gfx6_gfx7
    UINT64_C(3196069888), UINT64_C(0),	// S_QUADMASK_B32_vi
    UINT64_C(3196071168), UINT64_C(0),	// S_QUADMASK_B64_gfx10
    UINT64_C(3196066560), UINT64_C(0),	// S_QUADMASK_B64_gfx11
    UINT64_C(3196066560), UINT64_C(0),	// S_QUADMASK_B64_gfx12
    UINT64_C(3196071168), UINT64_C(0),	// S_QUADMASK_B64_gfx6_gfx7
    UINT64_C(3196070144), UINT64_C(0),	// S_QUADMASK_B64_vi
    UINT64_C(3196068352), UINT64_C(0),	// S_RFE_B64_gfx10
    UINT64_C(3196078592), UINT64_C(0),	// S_RFE_B64_gfx11
    UINT64_C(3196078592), UINT64_C(0),	// S_RFE_B64_gfx12
    UINT64_C(3196078592), UINT64_C(0),	// S_RFE_B64_gfx1250
    UINT64_C(3196068352), UINT64_C(0),	// S_RFE_B64_gfx6_gfx7
    UINT64_C(3196067584), UINT64_C(0),	// S_RFE_B64_vi
    UINT64_C(2508193792), UINT64_C(0),	// S_RFE_RESTORE_B64_vi
    UINT64_C(3196087808), UINT64_C(0),	// S_RNDNE_F16_gfx11
    UINT64_C(3196087808), UINT64_C(0),	// S_RNDNE_F16_gfx12
    UINT64_C(3196084992), UINT64_C(0),	// S_RNDNE_F32_gfx11
    UINT64_C(3196084992), UINT64_C(0),	// S_RNDNE_F32_gfx12
    UINT64_C(3215196160), UINT64_C(0),	// S_ROUND_MODE_gfx10
    UINT64_C(3213950976), UINT64_C(0),	// S_ROUND_MODE_gfx11
    UINT64_C(3213950976), UINT64_C(0),	// S_ROUND_MODE_gfx12
    UINT64_C(18014398513577197568), UINT64_C(0),	// S_SCRATCH_LOAD_DWORDX2_IMM_gfx10
    UINT64_C(3222929408), UINT64_C(0),	// S_SCRATCH_LOAD_DWORDX2_IMM_vi
    UINT64_C(4095213568), UINT64_C(0),	// S_SCRATCH_LOAD_DWORDX2_SGPR_IMM_gfx10
    UINT64_C(3222945792), UINT64_C(0),	// S_SCRATCH_LOAD_DWORDX2_SGPR_IMM_gfx9
    UINT64_C(3222814720), UINT64_C(0),	// S_SCRATCH_LOAD_DWORDX2_SGPR_alt_gfx9
    UINT64_C(4095213568), UINT64_C(0),	// S_SCRATCH_LOAD_DWORDX2_SGPR_gfx10
    UINT64_C(3222798336), UINT64_C(0),	// S_SCRATCH_LOAD_DWORDX2_SGPR_vi
    UINT64_C(18014398513577459712), UINT64_C(0),	// S_SCRATCH_LOAD_DWORDX4_IMM_gfx10
    UINT64_C(3223191552), UINT64_C(0),	// S_SCRATCH_LOAD_DWORDX4_IMM_vi
    UINT64_C(4095475712), UINT64_C(0),	// S_SCRATCH_LOAD_DWORDX4_SGPR_IMM_gfx10
    UINT64_C(3223207936), UINT64_C(0),	// S_SCRATCH_LOAD_DWORDX4_SGPR_IMM_gfx9
    UINT64_C(3223076864), UINT64_C(0),	// S_SCRATCH_LOAD_DWORDX4_SGPR_alt_gfx9
    UINT64_C(4095475712), UINT64_C(0),	// S_SCRATCH_LOAD_DWORDX4_SGPR_gfx10
    UINT64_C(3223060480), UINT64_C(0),	// S_SCRATCH_LOAD_DWORDX4_SGPR_vi
    UINT64_C(18014398513576935424), UINT64_C(0),	// S_SCRATCH_LOAD_DWORD_IMM_gfx10
    UINT64_C(3222667264), UINT64_C(0),	// S_SCRATCH_LOAD_DWORD_IMM_vi
    UINT64_C(4094951424), UINT64_C(0),	// S_SCRATCH_LOAD_DWORD_SGPR_IMM_gfx10
    UINT64_C(3222683648), UINT64_C(0),	// S_SCRATCH_LOAD_DWORD_SGPR_IMM_gfx9
    UINT64_C(3222552576), UINT64_C(0),	// S_SCRATCH_LOAD_DWORD_SGPR_alt_gfx9
    UINT64_C(4094951424), UINT64_C(0),	// S_SCRATCH_LOAD_DWORD_SGPR_gfx10
    UINT64_C(3222536192), UINT64_C(0),	// S_SCRATCH_LOAD_DWORD_SGPR_vi
    UINT64_C(18014398513581391872), UINT64_C(0),	// S_SCRATCH_STORE_DWORDX2_IMM_gfx10
    UINT64_C(3227123712), UINT64_C(0),	// S_SCRATCH_STORE_DWORDX2_IMM_vi
    UINT64_C(4099407872), UINT64_C(0),	// S_SCRATCH_STORE_DWORDX2_SGPR_IMM_gfx10
    UINT64_C(3227140096), UINT64_C(0),	// S_SCRATCH_STORE_DWORDX2_SGPR_IMM_gfx9
    UINT64_C(3227009024), UINT64_C(0),	// S_SCRATCH_STORE_DWORDX2_SGPR_alt_gfx9
    UINT64_C(4099407872), UINT64_C(0),	// S_SCRATCH_STORE_DWORDX2_SGPR_gfx10
    UINT64_C(3226992640), UINT64_C(0),	// S_SCRATCH_STORE_DWORDX2_SGPR_vi
    UINT64_C(18014398513581654016), UINT64_C(0),	// S_SCRATCH_STORE_DWORDX4_IMM_gfx10
    UINT64_C(3227385856), UINT64_C(0),	// S_SCRATCH_STORE_DWORDX4_IMM_vi
    UINT64_C(4099670016), UINT64_C(0),	// S_SCRATCH_STORE_DWORDX4_SGPR_IMM_gfx10
    UINT64_C(3227402240), UINT64_C(0),	// S_SCRATCH_STORE_DWORDX4_SGPR_IMM_gfx9
    UINT64_C(3227271168), UINT64_C(0),	// S_SCRATCH_STORE_DWORDX4_SGPR_alt_gfx9
    UINT64_C(4099670016), UINT64_C(0),	// S_SCRATCH_STORE_DWORDX4_SGPR_gfx10
    UINT64_C(3227254784), UINT64_C(0),	// S_SCRATCH_STORE_DWORDX4_SGPR_vi
    UINT64_C(18014398513581129728), UINT64_C(0),	// S_SCRATCH_STORE_DWORD_IMM_gfx10
    UINT64_C(3226861568), UINT64_C(0),	// S_SCRATCH_STORE_DWORD_IMM_vi
    UINT64_C(4099145728), UINT64_C(0),	// S_SCRATCH_STORE_DWORD_SGPR_IMM_gfx10
    UINT64_C(3226877952), UINT64_C(0),	// S_SCRATCH_STORE_DWORD_SGPR_IMM_gfx9
    UINT64_C(3226746880), UINT64_C(0),	// S_SCRATCH_STORE_DWORD_SGPR_alt_gfx9
    UINT64_C(4099145728), UINT64_C(0),	// S_SCRATCH_STORE_DWORD_SGPR_gfx10
    UINT64_C(3226730496), UINT64_C(0),	// S_SCRATCH_STORE_DWORD_SGPR_vi
    UINT64_C(3213950976), UINT64_C(0),	// S_SENDMSGHALT_gfx10
    UINT64_C(3216441344), UINT64_C(0),	// S_SENDMSGHALT_gfx11
    UINT64_C(3216441344), UINT64_C(0),	// S_SENDMSGHALT_gfx12
    UINT64_C(3213950976), UINT64_C(0),	// S_SENDMSGHALT_gfx6_gfx7
    UINT64_C(3213950976), UINT64_C(0),	// S_SENDMSGHALT_vi
    UINT64_C(3196079104), UINT64_C(0),	// S_SENDMSG_RTN_B32_gfx11
    UINT64_C(3196079104), UINT64_C(0),	// S_SENDMSG_RTN_B32_gfx12
    UINT64_C(3196079360), UINT64_C(0),	// S_SENDMSG_RTN_B64_gfx11
    UINT64_C(3196079360), UINT64_C(0),	// S_SENDMSG_RTN_B64_gfx12
    UINT64_C(3213885440), UINT64_C(0),	// S_SENDMSG_gfx10
    UINT64_C(3216375808), UINT64_C(0),	// S_SENDMSG_gfx11
    UINT64_C(3216375808), UINT64_C(0),	// S_SENDMSG_gfx12
    UINT64_C(3213885440), UINT64_C(0),	// S_SENDMSG_gfx6_gfx7
    UINT64_C(3213885440), UINT64_C(0),	// S_SENDMSG_vi
    UINT64_C(3213688832), UINT64_C(0),	// S_SETHALT_gfx10
    UINT64_C(3212967936), UINT64_C(0),	// S_SETHALT_gfx11
    UINT64_C(3212967936), UINT64_C(0),	// S_SETHALT_gfx12
    UINT64_C(3213688832), UINT64_C(0),	// S_SETHALT_gfx6_gfx7
    UINT64_C(3213688832), UINT64_C(0),	// S_SETHALT_vi
    UINT64_C(3213557760), UINT64_C(0),	// S_SETKILL_gfx10
    UINT64_C(3212902400), UINT64_C(0),	// S_SETKILL_gfx11
    UINT64_C(3212902400), UINT64_C(0),	// S_SETKILL_gfx12
    UINT64_C(3213557760), UINT64_C(0),	// S_SETKILL_gfx6_gfx7
    UINT64_C(3213557760), UINT64_C(0),	// S_SETKILL_vi
    UINT64_C(3196067840), UINT64_C(0),	// S_SETPC_B64_gfx10
    UINT64_C(3196078080), UINT64_C(0),	// S_SETPC_B64_gfx11
    UINT64_C(3196078080), UINT64_C(0),	// S_SETPC_B64_gfx12
    UINT64_C(3196078080), UINT64_C(0),	// S_SETPC_B64_gfx1250
    UINT64_C(3196067840), UINT64_C(0),	// S_SETPC_B64_gfx6_gfx7
    UINT64_C(3196067072), UINT64_C(0),	// S_SETPC_B64_vi
    UINT64_C(3216900096), UINT64_C(0),	// S_SETPRIO_INC_WG_gfx12
    UINT64_C(3213819904), UINT64_C(0),	// S_SETPRIO_gfx10
    UINT64_C(3216310272), UINT64_C(0),	// S_SETPRIO_gfx11
    UINT64_C(3216310272), UINT64_C(0),	// S_SETPRIO_gfx12
    UINT64_C(3213819904), UINT64_C(0),	// S_SETPRIO_gfx6_gfx7
    UINT64_C(3213819904), UINT64_C(0),	// S_SETPRIO_vi
    UINT64_C(3112173568), UINT64_C(0),	// S_SETREG_B32_gfx10
    UINT64_C(3103784960), UINT64_C(0),	// S_SETREG_B32_gfx11
    UINT64_C(3103784960), UINT64_C(0),	// S_SETREG_B32_gfx12
    UINT64_C(3112173568), UINT64_C(0),	// S_SETREG_B32_gfx6_gfx7
    UINT64_C(3103784960), UINT64_C(0),	// S_SETREG_B32_vi
    UINT64_C(3128950784), UINT64_C(0),	// S_SETREG_IMM32_B32_gfx10
    UINT64_C(3112173568), UINT64_C(0),	// S_SETREG_IMM32_B32_gfx11
    UINT64_C(3112173568), UINT64_C(0),	// S_SETREG_IMM32_B32_gfx12
    UINT64_C(3128950784), UINT64_C(0),	// S_SETREG_IMM32_B32_gfx6_gfx7
    UINT64_C(3120562176), UINT64_C(0),	// S_SETREG_IMM32_B32_vi
    UINT64_C(3205496832), UINT64_C(0),	// S_SETVSKIP_gfx6_gfx7
    UINT64_C(3205496832), UINT64_C(0),	// S_SETVSKIP_vi
    UINT64_C(3196072448), UINT64_C(0),	// S_SET_GPR_IDX_IDX_vi
    UINT64_C(3214737408), UINT64_C(0),	// S_SET_GPR_IDX_MODE_vi
    UINT64_C(3214671872), UINT64_C(0),	// S_SET_GPR_IDX_OFF_vi
    UINT64_C(3205562368), UINT64_C(0),	// S_SET_GPR_IDX_ON_vi
    UINT64_C(3213230080), UINT64_C(0),	// S_SET_VGPR_MSB_gfx12
    UINT64_C(3196066304), UINT64_C(0),	// S_SEXT_I32_I16_gfx10
    UINT64_C(3196063488), UINT64_C(0),	// S_SEXT_I32_I16_gfx11
    UINT64_C(3196063488), UINT64_C(0),	// S_SEXT_I32_I16_gfx12
    UINT64_C(3196066304), UINT64_C(0),	// S_SEXT_I32_I16_gfx6_gfx7
    UINT64_C(3196065536), UINT64_C(0),	// S_SEXT_I32_I16_vi
    UINT64_C(3196066048), UINT64_C(0),	// S_SEXT_I32_I8_gfx10
    UINT64_C(3196063232), UINT64_C(0),	// S_SEXT_I32_I8_gfx11
    UINT64_C(3196063232), UINT64_C(0),	// S_SEXT_I32_I8_gfx12
    UINT64_C(3196066048), UINT64_C(0),	// S_SEXT_I32_I8_gfx6_gfx7
    UINT64_C(3196065280), UINT64_C(0),	// S_SEXT_I32_I8_vi
    UINT64_C(3196082176), UINT64_C(0),	// S_SLEEP_VAR_gfx12
    UINT64_C(3213754368), UINT64_C(0),	// S_SLEEP_gfx10
    UINT64_C(3213033472), UINT64_C(0),	// S_SLEEP_gfx11
    UINT64_C(3213033472), UINT64_C(0),	// S_SLEEP_gfx12
    UINT64_C(3213754368), UINT64_C(0),	// S_SLEEP_gfx6_gfx7
    UINT64_C(3213754368), UINT64_C(0),	// S_SLEEP_vi
    UINT64_C(18014398513580081152), UINT64_C(0),	// S_STORE_DWORDX2_IMM_gfx10
    UINT64_C(3225812992), UINT64_C(0),	// S_STORE_DWORDX2_IMM_vi
    UINT64_C(4098097152), UINT64_C(0),	// S_STORE_DWORDX2_SGPR_IMM_gfx10
    UINT64_C(3225829376), UINT64_C(0),	// S_STORE_DWORDX2_SGPR_IMM_gfx9
    UINT64_C(3225698304), UINT64_C(0),	// S_STORE_DWORDX2_SGPR_alt_gfx9
    UINT64_C(4098097152), UINT64_C(0),	// S_STORE_DWORDX2_SGPR_gfx10
    UINT64_C(3225681920), UINT64_C(0),	// S_STORE_DWORDX2_SGPR_vi
    UINT64_C(18014398513580343296), UINT64_C(0),	// S_STORE_DWORDX4_IMM_gfx10
    UINT64_C(3226075136), UINT64_C(0),	// S_STORE_DWORDX4_IMM_vi
    UINT64_C(4098359296), UINT64_C(0),	// S_STORE_DWORDX4_SGPR_IMM_gfx10
    UINT64_C(3226091520), UINT64_C(0),	// S_STORE_DWORDX4_SGPR_IMM_gfx9
    UINT64_C(3225960448), UINT64_C(0),	// S_STORE_DWORDX4_SGPR_alt_gfx9
    UINT64_C(4098359296), UINT64_C(0),	// S_STORE_DWORDX4_SGPR_gfx10
    UINT64_C(3225944064), UINT64_C(0),	// S_STORE_DWORDX4_SGPR_vi
    UINT64_C(18014398513579819008), UINT64_C(0),	// S_STORE_DWORD_IMM_gfx10
    UINT64_C(3225550848), UINT64_C(0),	// S_STORE_DWORD_IMM_vi
    UINT64_C(4097835008), UINT64_C(0),	// S_STORE_DWORD_SGPR_IMM_gfx10
    UINT64_C(3225567232), UINT64_C(0),	// S_STORE_DWORD_SGPR_IMM_gfx9
    UINT64_C(3225436160), UINT64_C(0),	// S_STORE_DWORD_SGPR_alt_gfx9
    UINT64_C(4097835008), UINT64_C(0),	// S_STORE_DWORD_SGPR_gfx10
    UINT64_C(3225419776), UINT64_C(0),	// S_STORE_DWORD_SGPR_vi
    UINT64_C(2189426688), UINT64_C(0),	// S_SUBB_U32_gfx10
    UINT64_C(2189426688), UINT64_C(0),	// S_SUBB_U32_gfx11
    UINT64_C(2189426688), UINT64_C(0),	// S_SUBB_U32_gfx12
    UINT64_C(2189426688), UINT64_C(0),	// S_SUBB_U32_gfx6_gfx7
    UINT64_C(2189426688), UINT64_C(0),	// S_SUBB_U32_vi
    UINT64_C(3179282432), UINT64_C(0),	// S_SUBVECTOR_LOOP_BEGIN_gfx10
    UINT64_C(3137339392), UINT64_C(0),	// S_SUBVECTOR_LOOP_BEGIN_gfx11
    UINT64_C(3187671040), UINT64_C(0),	// S_SUBVECTOR_LOOP_END_gfx10
    UINT64_C(3145728000), UINT64_C(0),	// S_SUBVECTOR_LOOP_END_gfx11
    UINT64_C(2768240640), UINT64_C(0),	// S_SUB_F16_gfx11
    UINT64_C(2768240640), UINT64_C(0),	// S_SUB_F16_gfx12
    UINT64_C(2692743168), UINT64_C(0),	// S_SUB_F32_gfx11
    UINT64_C(2692743168), UINT64_C(0),	// S_SUB_F32_gfx12
    UINT64_C(2172649472), UINT64_C(0),	// S_SUB_I32_gfx10
    UINT64_C(2172649472), UINT64_C(0),	// S_SUB_I32_gfx11
    UINT64_C(2172649472), UINT64_C(0),	// S_SUB_I32_gfx12
    UINT64_C(2172649472), UINT64_C(0),	// S_SUB_I32_gfx6_gfx7
    UINT64_C(2172649472), UINT64_C(0),	// S_SUB_I32_vi
    UINT64_C(2155872256), UINT64_C(0),	// S_SUB_U32_gfx10
    UINT64_C(2155872256), UINT64_C(0),	// S_SUB_U32_gfx11
    UINT64_C(2155872256), UINT64_C(0),	// S_SUB_U32_gfx12
    UINT64_C(2155872256), UINT64_C(0),	// S_SUB_U32_gfx6_gfx7
    UINT64_C(2155872256), UINT64_C(0),	// S_SUB_U32_vi
    UINT64_C(2852126720), UINT64_C(0),	// S_SUB_U64_gfx12
    UINT64_C(3196068096), UINT64_C(0),	// S_SWAPPC_B64_gfx10
    UINT64_C(3196078336), UINT64_C(0),	// S_SWAPPC_B64_gfx11
    UINT64_C(3196078336), UINT64_C(0),	// S_SWAPPC_B64_gfx12
    UINT64_C(3196078336), UINT64_C(0),	// S_SWAPPC_B64_gfx1250
    UINT64_C(3196068096), UINT64_C(0),	// S_SWAPPC_B64_gfx6_gfx7
    UINT64_C(3196067328), UINT64_C(0),	// S_SWAPPC_B64_vi
    UINT64_C(3214016512), UINT64_C(0),	// S_TRAP_gfx10
    UINT64_C(3213885440), UINT64_C(0),	// S_TRAP_gfx11
    UINT64_C(3213885440), UINT64_C(0),	// S_TRAP_gfx12
    UINT64_C(3214016512), UINT64_C(0),	// S_TRAP_gfx6_gfx7
    UINT64_C(3214016512), UINT64_C(0),	// S_TRAP_vi
    UINT64_C(3196087552), UINT64_C(0),	// S_TRUNC_F16_gfx11
    UINT64_C(3196087552), UINT64_C(0),	// S_TRUNC_F16_gfx12
    UINT64_C(3196084736), UINT64_C(0),	// S_TRUNC_F32_gfx11
    UINT64_C(3196084736), UINT64_C(0),	// S_TRUNC_F32_gfx12
    UINT64_C(3215458304), UINT64_C(0),	// S_TTRACEDATA_IMM_gfx10
    UINT64_C(3216703488), UINT64_C(0),	// S_TTRACEDATA_IMM_gfx11
    UINT64_C(3216703488), UINT64_C(0),	// S_TTRACEDATA_IMM_gfx12
    UINT64_C(3214278656), UINT64_C(0),	// S_TTRACEDATA_gfx10
    UINT64_C(3216637952), UINT64_C(0),	// S_TTRACEDATA_gfx11
    UINT64_C(3216637952), UINT64_C(0),	// S_TTRACEDATA_gfx12
    UINT64_C(3214278656), UINT64_C(0),	// S_TTRACEDATA_gfx6_gfx7
    UINT64_C(3214278656), UINT64_C(0),	// S_TTRACEDATA_vi
    UINT64_C(2961178624), UINT64_C(0),	// S_VERSION_gfx10
    UINT64_C(2961178624), UINT64_C(0),	// S_VERSION_gfx11
    UINT64_C(2961178624), UINT64_C(0),	// S_VERSION_gfx12
    UINT64_C(3215130624), UINT64_C(0),	// S_WAITCNT_DEPCTR_gfx10
    UINT64_C(3213361152), UINT64_C(0),	// S_WAITCNT_DEPCTR_gfx11
    UINT64_C(3213361152), UINT64_C(0),	// S_WAITCNT_DEPCTR_gfx12
    UINT64_C(3162505216), UINT64_C(0),	// S_WAITCNT_EXPCNT_gfx10
    UINT64_C(3170893824), UINT64_C(0),	// S_WAITCNT_EXPCNT_gfx11
    UINT64_C(3170893824), UINT64_C(0),	// S_WAITCNT_LGKMCNT_gfx10
    UINT64_C(3179282432), UINT64_C(0),	// S_WAITCNT_LGKMCNT_gfx11
    UINT64_C(3154116608), UINT64_C(0),	// S_WAITCNT_VMCNT_gfx10
    UINT64_C(3162505216), UINT64_C(0),	// S_WAITCNT_VMCNT_gfx11
    UINT64_C(3145728000), UINT64_C(0),	// S_WAITCNT_VSCNT_gfx10
    UINT64_C(3154116608), UINT64_C(0),	// S_WAITCNT_VSCNT_gfx11
    UINT64_C(3213623296), UINT64_C(0),	// S_WAITCNT_gfx10
    UINT64_C(3213426688), UINT64_C(0),	// S_WAITCNT_gfx11
    UINT64_C(3213426688), UINT64_C(0),	// S_WAITCNT_gfx12
    UINT64_C(3213623296), UINT64_C(0),	// S_WAITCNT_gfx6_gfx7
    UINT64_C(3213623296), UINT64_C(0),	// S_WAITCNT_vi
    UINT64_C(3217686528), UINT64_C(0),	// S_WAIT_ASYNCCNT_gfx12
    UINT64_C(3217227776), UINT64_C(0),	// S_WAIT_BVHCNT_gfx12
    UINT64_C(3217424384), UINT64_C(0),	// S_WAIT_DSCNT_gfx12
    UINT64_C(3213557760), UINT64_C(0),	// S_WAIT_EVENT_gfx11
    UINT64_C(3213557760), UINT64_C(0),	// S_WAIT_EVENT_gfx12
    UINT64_C(3217293312), UINT64_C(0),	// S_WAIT_EXPCNT_gfx12
    UINT64_C(3215065088), UINT64_C(0),	// S_WAIT_IDLE_gfx10
    UINT64_C(3213492224), UINT64_C(0),	// S_WAIT_IDLE_gfx11
    UINT64_C(3213492224), UINT64_C(0),	// S_WAIT_IDLE_gfx12
    UINT64_C(3217489920), UINT64_C(0),	// S_WAIT_KMCNT_gfx12
    UINT64_C(3217555456), UINT64_C(0),	// S_WAIT_LOADCNT_DSCNT_gfx12
    UINT64_C(3217031168), UINT64_C(0),	// S_WAIT_LOADCNT_gfx12
    UINT64_C(3217162240), UINT64_C(0),	// S_WAIT_SAMPLECNT_gfx12
    UINT64_C(3217620992), UINT64_C(0),	// S_WAIT_STORECNT_DSCNT_gfx12
    UINT64_C(3217096704), UINT64_C(0),	// S_WAIT_STORECNT_gfx12
    UINT64_C(3217752064), UINT64_C(0),	// S_WAIT_TENSORCNT_gfx12
    UINT64_C(3217358848), UINT64_C(0),	// S_WAIT_XCNT_gfx12
    UINT64_C(3196081920), UINT64_C(0),	// S_WAKEUP_BARRIER_IMM_gfx12
    UINT64_C(3196082045), UINT64_C(0),	// S_WAKEUP_BARRIER_M0_gfx12
    UINT64_C(3213033472), UINT64_C(0),	// S_WAKEUP_gfx10
    UINT64_C(3216244736), UINT64_C(0),	// S_WAKEUP_gfx11
    UINT64_C(3216244736), UINT64_C(0),	// S_WAKEUP_gfx12
    UINT64_C(3213033472), UINT64_C(0),	// S_WAKEUP_vi
    UINT64_C(3196061952), UINT64_C(0),	// S_WQM_B32_gfx10
    UINT64_C(3196066816), UINT64_C(0),	// S_WQM_B32_gfx11
    UINT64_C(3196066816), UINT64_C(0),	// S_WQM_B32_gfx12
    UINT64_C(3196061952), UINT64_C(0),	// S_WQM_B32_gfx6_gfx7
    UINT64_C(3196061184), UINT64_C(0),	// S_WQM_B32_vi
    UINT64_C(3196062208), UINT64_C(0),	// S_WQM_B64_gfx10
    UINT64_C(3196067072), UINT64_C(0),	// S_WQM_B64_gfx11
    UINT64_C(3196067072), UINT64_C(0),	// S_WQM_B64_gfx12
    UINT64_C(3196062208), UINT64_C(0),	// S_WQM_B64_gfx6_gfx7
    UINT64_C(3196061440), UINT64_C(0),	// S_WQM_B64_vi
    UINT64_C(2382364672), UINT64_C(0),	// S_XNOR_B32_gfx10
    UINT64_C(2415919104), UINT64_C(0),	// S_XNOR_B32_gfx11
    UINT64_C(2415919104), UINT64_C(0),	// S_XNOR_B32_gfx12
    UINT64_C(2382364672), UINT64_C(0),	// S_XNOR_B32_gfx6_gfx7
    UINT64_C(2365587456), UINT64_C(0),	// S_XNOR_B32_vi
    UINT64_C(2390753280), UINT64_C(0),	// S_XNOR_B64_gfx10
    UINT64_C(2424307712), UINT64_C(0),	// S_XNOR_B64_gfx11
    UINT64_C(2424307712), UINT64_C(0),	// S_XNOR_B64_gfx12
    UINT64_C(2390753280), UINT64_C(0),	// S_XNOR_B64_gfx6_gfx7
    UINT64_C(2373976064), UINT64_C(0),	// S_XNOR_B64_vi
    UINT64_C(3196076800), UINT64_C(0),	// S_XNOR_SAVEEXEC_B32_gfx10
    UINT64_C(3196070400), UINT64_C(0),	// S_XNOR_SAVEEXEC_B32_gfx11
    UINT64_C(3196070400), UINT64_C(0),	// S_XNOR_SAVEEXEC_B32_gfx12
    UINT64_C(3196070656), UINT64_C(0),	// S_XNOR_SAVEEXEC_B64_gfx10
    UINT64_C(3196070656), UINT64_C(0),	// S_XNOR_SAVEEXEC_B64_gfx11
    UINT64_C(3196070656), UINT64_C(0),	// S_XNOR_SAVEEXEC_B64_gfx12
    UINT64_C(3196070656), UINT64_C(0),	// S_XNOR_SAVEEXEC_B64_gfx6_gfx7
    UINT64_C(3196069632), UINT64_C(0),	// S_XNOR_SAVEEXEC_B64_vi
    UINT64_C(2298478592), UINT64_C(0),	// S_XOR_B32_gfx10
    UINT64_C(2365587456), UINT64_C(0),	// S_XOR_B32_gfx11
    UINT64_C(2365587456), UINT64_C(0),	// S_XOR_B32_gfx12
    UINT64_C(2298478592), UINT64_C(0),	// S_XOR_B32_gfx6_gfx7
    UINT64_C(2281701376), UINT64_C(0),	// S_XOR_B32_vi
    UINT64_C(2306867200), UINT64_C(0),	// S_XOR_B64_gfx10
    UINT64_C(2373976064), UINT64_C(0),	// S_XOR_B64_gfx11
    UINT64_C(2373976064), UINT64_C(0),	// S_XOR_B64_gfx12
    UINT64_C(2306867200), UINT64_C(0),	// S_XOR_B64_gfx6_gfx7
    UINT64_C(2290089984), UINT64_C(0),	// S_XOR_B64_vi
    UINT64_C(3196075520), UINT64_C(0),	// S_XOR_SAVEEXEC_B32_gfx10
    UINT64_C(3196068864), UINT64_C(0),	// S_XOR_SAVEEXEC_B32_gfx11
    UINT64_C(3196068864), UINT64_C(0),	// S_XOR_SAVEEXEC_B32_gfx12
    UINT64_C(3196069376), UINT64_C(0),	// S_XOR_SAVEEXEC_B64_gfx10
    UINT64_C(3196069120), UINT64_C(0),	// S_XOR_SAVEEXEC_B64_gfx11
    UINT64_C(3196069120), UINT64_C(0),	// S_XOR_SAVEEXEC_B64_gfx12
    UINT64_C(3196069376), UINT64_C(0),	// S_XOR_SAVEEXEC_B64_gfx6_gfx7
    UINT64_C(3196068352), UINT64_C(0),	// S_XOR_SAVEEXEC_B64_vi
    UINT64_C(9007203147264000), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx10
    UINT64_C(54043199421120512), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx11
    UINT64_C(3892686848), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx90a
    UINT64_C(3892686848), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_vi
    UINT64_C(9007203147259904), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx10
    UINT64_C(36028800911638528), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx11
    UINT64_C(3892682752), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx90a
    UINT64_C(3892682752), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_vi
    UINT64_C(9007203147255808), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx10
    UINT64_C(18014402402156544), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx11
    UINT64_C(3892678656), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx90a
    UINT64_C(3892678656), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_vi
    UINT64_C(9007203147251712), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx10
    UINT64_C(3892674560), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx11
    UINT64_C(3892674560), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx90a
    UINT64_C(3892674560), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_vi
    UINT64_C(13835058058572775424), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN_gfx12
    UINT64_C(9223372040145387520), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN_gfx12
    UINT64_C(4611686021717999616), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN_gfx12
    UINT64_C(3290611712), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET_gfx12
    UINT64_C(3892686848), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80
    UINT64_C(3892682752), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80
    UINT64_C(3892678656), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80
    UINT64_C(3892674560), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80
    UINT64_C(9007203147198464), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx10
    UINT64_C(54043199421087744), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx11
    UINT64_C(3892654080), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx90a
    UINT64_C(3892654080), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_vi
    UINT64_C(9007203147194368), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx10
    UINT64_C(36028800911605760), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx11
    UINT64_C(3892649984), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx90a
    UINT64_C(3892649984), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_vi
    UINT64_C(9007203147190272), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx10
    UINT64_C(18014402402123776), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx11
    UINT64_C(3892645888), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx90a
    UINT64_C(3892645888), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_vi
    UINT64_C(9007203147186176), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx10
    UINT64_C(3892641792), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx11
    UINT64_C(3892641792), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx90a
    UINT64_C(3892641792), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_vi
    UINT64_C(13835058058572759040), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN_gfx12
    UINT64_C(9223372040145371136), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN_gfx12
    UINT64_C(4611686021717983232), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN_gfx12
    UINT64_C(3290595328), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET_gfx12
    UINT64_C(3892654080), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80
    UINT64_C(3892649984), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80
    UINT64_C(3892645888), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80
    UINT64_C(3892641792), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80
    UINT64_C(9007203147132928), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx10
    UINT64_C(54043199421054976), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx11
    UINT64_C(3892621312), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx90a
    UINT64_C(3892621312), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_vi
    UINT64_C(9007203147128832), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx10
    UINT64_C(36028800911572992), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx11
    UINT64_C(3892617216), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx90a
    UINT64_C(3892617216), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_vi
    UINT64_C(9007203147124736), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx10
    UINT64_C(18014402402091008), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx11
    UINT64_C(3892613120), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx90a
    UINT64_C(3892613120), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_vi
    UINT64_C(9007203147120640), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx10
    UINT64_C(3892609024), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx11
    UINT64_C(3892609024), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx90a
    UINT64_C(3892609024), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_vi
    UINT64_C(13835058058572742656), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN_gfx12
    UINT64_C(9223372040145354752), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN_gfx12
    UINT64_C(4611686021717966848), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN_gfx12
    UINT64_C(3290578944), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET_gfx12
    UINT64_C(3892621312), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_gfx80
    UINT64_C(3892617216), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_gfx80
    UINT64_C(3892613120), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_gfx80
    UINT64_C(3892609024), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_gfx80
    UINT64_C(9007203147067392), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx10
    UINT64_C(54043199421022208), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx11
    UINT64_C(3892588544), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx90a
    UINT64_C(3892588544), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_vi
    UINT64_C(9007203147063296), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx10
    UINT64_C(36028800911540224), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx11
    UINT64_C(3892584448), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx90a
    UINT64_C(3892584448), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_IDXEN_vi
    UINT64_C(9007203147059200), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx10
    UINT64_C(18014402402058240), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx11
    UINT64_C(3892580352), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx90a
    UINT64_C(3892580352), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_OFFEN_vi
    UINT64_C(9007203147055104), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx10
    UINT64_C(3892576256), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx11
    UINT64_C(3892576256), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx90a
    UINT64_C(3892576256), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_OFFSET_vi
    UINT64_C(13835058058572726272), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN_gfx12
    UINT64_C(9223372040145338368), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN_gfx12
    UINT64_C(4611686021717950464), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN_gfx12
    UINT64_C(3290562560), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET_gfx12
    UINT64_C(3892588544), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_gfx80
    UINT64_C(3892584448), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_gfx80
    UINT64_C(3892580352), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_gfx80
    UINT64_C(3892576256), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_gfx80
    UINT64_C(3892543488), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_ADDR64_gfx6_gfx7
    UINT64_C(3892523008), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx10
    UINT64_C(54043199420858368), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx11
    UINT64_C(3892523008), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx6_gfx7
    UINT64_C(3892424704), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx90a
    UINT64_C(3892424704), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi
    UINT64_C(3892518912), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx10
    UINT64_C(36028800911376384), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx11
    UINT64_C(3892518912), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx6_gfx7
    UINT64_C(3892420608), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx90a
    UINT64_C(3892420608), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_IDXEN_vi
    UINT64_C(3892514816), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx10
    UINT64_C(18014402401894400), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx11
    UINT64_C(3892514816), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx6_gfx7
    UINT64_C(3892416512), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx90a
    UINT64_C(3892416512), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_OFFEN_vi
    UINT64_C(3892510720), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx10
    UINT64_C(3892412416), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx11
    UINT64_C(3892510720), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx6_gfx7
    UINT64_C(3892412416), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx90a
    UINT64_C(3892412416), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_OFFSET_vi
    UINT64_C(13835058058572644352), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN_gfx12
    UINT64_C(9223372040145256448), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN_gfx12
    UINT64_C(4611686021717868544), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN_gfx12
    UINT64_C(3290480640), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET_gfx12
    UINT64_C(3892477952), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_ADDR64_gfx6_gfx7
    UINT64_C(3892457472), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx10
    UINT64_C(54043199420825600), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx11
    UINT64_C(3892457472), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx6_gfx7
    UINT64_C(3892391936), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx90a
    UINT64_C(3892391936), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi
    UINT64_C(3892453376), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx10
    UINT64_C(36028800911343616), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx11
    UINT64_C(3892453376), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx6_gfx7
    UINT64_C(3892387840), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx90a
    UINT64_C(3892387840), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_IDXEN_vi
    UINT64_C(3892449280), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx10
    UINT64_C(18014402401861632), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx11
    UINT64_C(3892449280), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx6_gfx7
    UINT64_C(3892383744), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx90a
    UINT64_C(3892383744), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_OFFEN_vi
    UINT64_C(3892445184), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx10
    UINT64_C(3892379648), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx11
    UINT64_C(3892445184), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx6_gfx7
    UINT64_C(3892379648), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx90a
    UINT64_C(3892379648), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_OFFSET_vi
    UINT64_C(13835058058572627968), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN_gfx12
    UINT64_C(9223372040145240064), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN_gfx12
    UINT64_C(4611686021717852160), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN_gfx12
    UINT64_C(3290464256), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET_gfx12
    UINT64_C(3892412416), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_ADDR64_gfx6_gfx7
    UINT64_C(3892391936), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx10
    UINT64_C(54043199420792832), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx11
    UINT64_C(3892391936), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx6_gfx7
    UINT64_C(3892359168), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx90a
    UINT64_C(3892359168), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_BOTHEN_vi
    UINT64_C(3892387840), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx10
    UINT64_C(36028800911310848), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx11
    UINT64_C(3892387840), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx6_gfx7
    UINT64_C(3892355072), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx90a
    UINT64_C(3892355072), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_IDXEN_vi
    UINT64_C(3892383744), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx10
    UINT64_C(18014402401828864), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx11
    UINT64_C(3892383744), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx6_gfx7
    UINT64_C(3892350976), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx90a
    UINT64_C(3892350976), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_OFFEN_vi
    UINT64_C(3892379648), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx10
    UINT64_C(3892346880), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx11
    UINT64_C(3892379648), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx6_gfx7
    UINT64_C(3892346880), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx90a
    UINT64_C(3892346880), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_OFFSET_vi
    UINT64_C(13835058058572611584), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN_gfx12
    UINT64_C(9223372040145223680), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN_gfx12
    UINT64_C(4611686021717835776), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN_gfx12
    UINT64_C(3290447872), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET_gfx12
    UINT64_C(3892346880), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_ADDR64_gfx6_gfx7
    UINT64_C(3892326400), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx10
    UINT64_C(54043199420760064), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx11
    UINT64_C(3892326400), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx6_gfx7
    UINT64_C(3892326400), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx90a
    UINT64_C(3892326400), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_BOTHEN_vi
    UINT64_C(3892322304), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_IDXEN_gfx10
    UINT64_C(36028800911278080), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_IDXEN_gfx11
    UINT64_C(3892322304), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_IDXEN_gfx6_gfx7
    UINT64_C(3892322304), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_IDXEN_gfx90a
    UINT64_C(3892322304), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_IDXEN_vi
    UINT64_C(3892318208), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_OFFEN_gfx10
    UINT64_C(18014402401796096), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_OFFEN_gfx11
    UINT64_C(3892318208), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_OFFEN_gfx6_gfx7
    UINT64_C(3892318208), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_OFFEN_gfx90a
    UINT64_C(3892318208), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_OFFEN_vi
    UINT64_C(3892314112), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_OFFSET_gfx10
    UINT64_C(3892314112), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_OFFSET_gfx11
    UINT64_C(3892314112), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_OFFSET_gfx6_gfx7
    UINT64_C(3892314112), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_OFFSET_gfx90a
    UINT64_C(3892314112), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_OFFSET_vi
    UINT64_C(13835058058572595200), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN_gfx12
    UINT64_C(9223372040145207296), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN_gfx12
    UINT64_C(4611686021717819392), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN_gfx12
    UINT64_C(3290431488), UINT64_C(0),	// TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET_gfx12
    UINT64_C(9007203147526144), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx10
    UINT64_C(54043199421251584), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx11
    UINT64_C(3892817920), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx90a
    UINT64_C(3892817920), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_vi
    UINT64_C(9007203147522048), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx10
    UINT64_C(36028800911769600), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx11
    UINT64_C(3892813824), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx90a
    UINT64_C(3892813824), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_vi
    UINT64_C(9007203147517952), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx10
    UINT64_C(18014402402287616), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx11
    UINT64_C(3892809728), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx90a
    UINT64_C(3892809728), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_vi
    UINT64_C(9007203147513856), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx10
    UINT64_C(3892805632), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx11
    UINT64_C(3892805632), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx90a
    UINT64_C(3892805632), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_vi
    UINT64_C(13835058058572840960), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_gfx12
    UINT64_C(9223372040145453056), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_gfx12
    UINT64_C(4611686021718065152), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_gfx12
    UINT64_C(3290677248), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_gfx12
    UINT64_C(3892817920), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80
    UINT64_C(3892813824), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80
    UINT64_C(3892809728), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80
    UINT64_C(3892805632), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80
    UINT64_C(9007203147460608), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx10
    UINT64_C(54043199421218816), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx11
    UINT64_C(3892785152), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx90a
    UINT64_C(3892785152), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_vi
    UINT64_C(9007203147456512), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx10
    UINT64_C(36028800911736832), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx11
    UINT64_C(3892781056), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx90a
    UINT64_C(3892781056), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_vi
    UINT64_C(9007203147452416), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx10
    UINT64_C(18014402402254848), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx11
    UINT64_C(3892776960), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx90a
    UINT64_C(3892776960), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_vi
    UINT64_C(9007203147448320), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx10
    UINT64_C(3892772864), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx11
    UINT64_C(3892772864), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx90a
    UINT64_C(3892772864), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_vi
    UINT64_C(13835058058572824576), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_BOTHEN_gfx12
    UINT64_C(9223372040145436672), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_IDXEN_gfx12
    UINT64_C(4611686021718048768), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_OFFEN_gfx12
    UINT64_C(3290660864), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_OFFSET_gfx12
    UINT64_C(3892785152), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80
    UINT64_C(3892781056), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80
    UINT64_C(3892776960), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80
    UINT64_C(3892772864), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80
    UINT64_C(9007203147395072), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx10
    UINT64_C(54043199421186048), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx11
    UINT64_C(3892752384), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx90a
    UINT64_C(3892752384), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_vi
    UINT64_C(9007203147390976), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx10
    UINT64_C(36028800911704064), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx11
    UINT64_C(3892748288), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx90a
    UINT64_C(3892748288), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_IDXEN_vi
    UINT64_C(9007203147386880), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx10
    UINT64_C(18014402402222080), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx11
    UINT64_C(3892744192), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx90a
    UINT64_C(3892744192), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_OFFEN_vi
    UINT64_C(9007203147382784), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx10
    UINT64_C(3892740096), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx11
    UINT64_C(3892740096), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx90a
    UINT64_C(3892740096), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_OFFSET_vi
    UINT64_C(13835058058572808192), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_gfx12
    UINT64_C(9223372040145420288), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_gfx12
    UINT64_C(4611686021718032384), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_gfx12
    UINT64_C(3290644480), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_gfx12
    UINT64_C(3892752384), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_gfx80
    UINT64_C(3892748288), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_gfx80
    UINT64_C(3892744192), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_gfx80
    UINT64_C(3892740096), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_gfx80
    UINT64_C(9007203147329536), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx10
    UINT64_C(54043199421153280), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx11
    UINT64_C(3892719616), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx90a
    UINT64_C(3892719616), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_BOTHEN_vi
    UINT64_C(9007203147325440), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_IDXEN_gfx10
    UINT64_C(36028800911671296), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_IDXEN_gfx11
    UINT64_C(3892715520), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_IDXEN_gfx90a
    UINT64_C(3892715520), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_IDXEN_vi
    UINT64_C(9007203147321344), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_OFFEN_gfx10
    UINT64_C(18014402402189312), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_OFFEN_gfx11
    UINT64_C(3892711424), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_OFFEN_gfx90a
    UINT64_C(3892711424), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_OFFEN_vi
    UINT64_C(9007203147317248), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_OFFSET_gfx10
    UINT64_C(3892707328), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_OFFSET_gfx11
    UINT64_C(3892707328), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_OFFSET_gfx90a
    UINT64_C(3892707328), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_OFFSET_vi
    UINT64_C(13835058058572791808), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_gfx12
    UINT64_C(9223372040145403904), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_gfx12
    UINT64_C(4611686021718016000), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_gfx12
    UINT64_C(3290628096), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_gfx12
    UINT64_C(3892719616), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_gfx80
    UINT64_C(3892715520), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_gfx80
    UINT64_C(3892711424), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_gfx80
    UINT64_C(3892707328), UINT64_C(0),	// TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_gfx80
    UINT64_C(3892805632), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_ADDR64_gfx6_gfx7
    UINT64_C(3892785152), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx10
    UINT64_C(54043199420989440), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx11
    UINT64_C(3892785152), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx6_gfx7
    UINT64_C(3892555776), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx90a
    UINT64_C(3892555776), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_BOTHEN_vi
    UINT64_C(3892781056), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx10
    UINT64_C(36028800911507456), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx11
    UINT64_C(3892781056), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx6_gfx7
    UINT64_C(3892551680), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx90a
    UINT64_C(3892551680), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_IDXEN_vi
    UINT64_C(3892776960), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx10
    UINT64_C(18014402402025472), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx11
    UINT64_C(3892776960), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx6_gfx7
    UINT64_C(3892547584), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx90a
    UINT64_C(3892547584), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_OFFEN_vi
    UINT64_C(3892772864), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx10
    UINT64_C(3892543488), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx11
    UINT64_C(3892772864), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx6_gfx7
    UINT64_C(3892543488), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx90a
    UINT64_C(3892543488), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_OFFSET_vi
    UINT64_C(13835058058572709888), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_gfx12
    UINT64_C(9223372040145321984), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_gfx12
    UINT64_C(4611686021717934080), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_gfx12
    UINT64_C(3290546176), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_gfx12
    UINT64_C(3892740096), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_ADDR64_gfx6_gfx7
    UINT64_C(3892719616), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx10
    UINT64_C(54043199420956672), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx11
    UINT64_C(3892719616), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx6_gfx7
    UINT64_C(3892523008), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx90a
    UINT64_C(3892523008), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_BOTHEN_vi
    UINT64_C(3892715520), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx10
    UINT64_C(36028800911474688), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx11
    UINT64_C(3892715520), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx6_gfx7
    UINT64_C(3892518912), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx90a
    UINT64_C(3892518912), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_IDXEN_vi
    UINT64_C(3892711424), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx10
    UINT64_C(18014402401992704), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx11
    UINT64_C(3892711424), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx6_gfx7
    UINT64_C(3892514816), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx90a
    UINT64_C(3892514816), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_OFFEN_vi
    UINT64_C(3892707328), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx10
    UINT64_C(3892510720), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx11
    UINT64_C(3892707328), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx6_gfx7
    UINT64_C(3892510720), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx90a
    UINT64_C(3892510720), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_OFFSET_vi
    UINT64_C(13835058058572693504), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_gfx12
    UINT64_C(9223372040145305600), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_gfx12
    UINT64_C(4611686021717917696), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_gfx12
    UINT64_C(3290529792), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_gfx12
    UINT64_C(3892674560), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_ADDR64_gfx6_gfx7
    UINT64_C(3892654080), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx10
    UINT64_C(54043199420923904), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx11
    UINT64_C(3892654080), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx6_gfx7
    UINT64_C(3892490240), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx90a
    UINT64_C(3892490240), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_BOTHEN_vi
    UINT64_C(3892649984), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_IDXEN_gfx10
    UINT64_C(36028800911441920), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_IDXEN_gfx11
    UINT64_C(3892649984), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_IDXEN_gfx6_gfx7
    UINT64_C(3892486144), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_IDXEN_gfx90a
    UINT64_C(3892486144), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_IDXEN_vi
    UINT64_C(3892645888), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_OFFEN_gfx10
    UINT64_C(18014402401959936), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_OFFEN_gfx11
    UINT64_C(3892645888), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_OFFEN_gfx6_gfx7
    UINT64_C(3892482048), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_OFFEN_gfx90a
    UINT64_C(3892482048), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_OFFEN_vi
    UINT64_C(3892641792), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_OFFSET_gfx10
    UINT64_C(3892477952), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_OFFSET_gfx11
    UINT64_C(3892641792), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_OFFSET_gfx6_gfx7
    UINT64_C(3892477952), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_OFFSET_gfx90a
    UINT64_C(3892477952), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_OFFSET_vi
    UINT64_C(13835058058572677120), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_gfx12
    UINT64_C(9223372040145289216), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_gfx12
    UINT64_C(4611686021717901312), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_gfx12
    UINT64_C(3290513408), UINT64_C(0),	// TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_gfx12
    UINT64_C(3892609024), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_ADDR64_gfx6_gfx7
    UINT64_C(3892588544), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_BOTHEN_gfx10
    UINT64_C(54043199420891136), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_BOTHEN_gfx11
    UINT64_C(3892588544), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_BOTHEN_gfx6_gfx7
    UINT64_C(3892457472), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_BOTHEN_gfx90a
    UINT64_C(3892457472), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_BOTHEN_vi
    UINT64_C(3892584448), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_IDXEN_gfx10
    UINT64_C(36028800911409152), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_IDXEN_gfx11
    UINT64_C(3892584448), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_IDXEN_gfx6_gfx7
    UINT64_C(3892453376), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_IDXEN_gfx90a
    UINT64_C(3892453376), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_IDXEN_vi
    UINT64_C(3892580352), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_OFFEN_gfx10
    UINT64_C(18014402401927168), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_OFFEN_gfx11
    UINT64_C(3892580352), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_OFFEN_gfx6_gfx7
    UINT64_C(3892449280), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_OFFEN_gfx90a
    UINT64_C(3892449280), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_OFFEN_vi
    UINT64_C(3892576256), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_OFFSET_gfx10
    UINT64_C(3892445184), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_OFFSET_gfx11
    UINT64_C(3892576256), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_OFFSET_gfx6_gfx7
    UINT64_C(3892445184), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_OFFSET_gfx90a
    UINT64_C(3892445184), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_OFFSET_vi
    UINT64_C(13835058058572660736), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_gfx12
    UINT64_C(9223372040145272832), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_gfx12
    UINT64_C(4611686021717884928), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_gfx12
    UINT64_C(3290497024), UINT64_C(0),	// TBUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_gfx12
    UINT64_C(8935141664200130561), UINT64_C(2088501248),	// TENSOR_LOAD_TO_LDS_D2_gfx1250
    UINT64_C(8935141664200130561), UINT64_C(0),	// TENSOR_LOAD_TO_LDS_gfx1250
    UINT64_C(3994779648), UINT64_C(0),	// TENSOR_SAVE_gfx1250
    UINT64_C(3994796156), UINT64_C(0),	// TENSOR_STOP_gfx1250
    UINT64_C(8935141664200146945), UINT64_C(2088501248),	// TENSOR_STORE_FROM_LDS_D2_gfx1250
    UINT64_C(8935141664200146945), UINT64_C(0),	// TENSOR_STORE_FROM_LDS_gfx1250
    UINT64_C(2113971200), UINT64_C(0),	// V_ACCVGPR_MOV_B32_vi
    UINT64_C(3554148352), UINT64_C(0),	// V_ACCVGPR_READ_B32_vi
    UINT64_C(3554213888), UINT64_C(0),	// V_ACCVGPR_WRITE_B32_vi
    UINT64_C(3595894784), UINT64_C(0),	// V_ADD3_U32_e64_dpp8_gfx11
    UINT64_C(3595894784), UINT64_C(0),	// V_ADD3_U32_e64_dpp8_gfx12
    UINT64_C(1077337718784), UINT64_C(0),	// V_ADD3_U32_e64_dpp_gfx11
    UINT64_C(1077337718784), UINT64_C(0),	// V_ADD3_U32_e64_dpp_gfx12
    UINT64_C(3595894784), UINT64_C(0),	// V_ADD3_U32_e64_gfx11
    UINT64_C(3595894784), UINT64_C(0),	// V_ADD3_U32_e64_gfx12
    UINT64_C(3614244864), UINT64_C(0),	// V_ADD3_U32_gfx10
    UINT64_C(3523149824), UINT64_C(0),	// V_ADD3_U32_vi
    UINT64_C(939524346), UINT64_C(0),	// V_ADDC_CO_U32_dpp_gfx9
    UINT64_C(939524096), UINT64_C(0),	// V_ADDC_CO_U32_e32_gfx9
    UINT64_C(3508273152), UINT64_C(0),	// V_ADDC_CO_U32_e64_gfx9
    UINT64_C(939524345), UINT64_C(0),	// V_ADDC_CO_U32_sdwa_gfx9
    UINT64_C(939524346), UINT64_C(0),	// V_ADDC_U32_dpp_vi
    UINT64_C(1342177280), UINT64_C(0),	// V_ADDC_U32_e32_gfx6_gfx7
    UINT64_C(939524096), UINT64_C(0),	// V_ADDC_U32_e32_vi
    UINT64_C(3528458240), UINT64_C(0),	// V_ADDC_U32_e64_gfx6_gfx7
    UINT64_C(3508273152), UINT64_C(0),	// V_ADDC_U32_e64_vi
    UINT64_C(939524345), UINT64_C(0),	// V_ADDC_U32_sdwa_vi
    UINT64_C(1342177280), UINT64_C(0),	// V_ADD_CO_CI_U32_dpp8_gfx10
    UINT64_C(1073741824), UINT64_C(0),	// V_ADD_CO_CI_U32_dpp8_gfx11
    UINT64_C(1073741824), UINT64_C(0),	// V_ADD_CO_CI_U32_dpp8_gfx12
    UINT64_C(1342177280), UINT64_C(0),	// V_ADD_CO_CI_U32_dpp8_w32_gfx10
    UINT64_C(1073741824), UINT64_C(0),	// V_ADD_CO_CI_U32_dpp8_w32_gfx11
    UINT64_C(1073741824), UINT64_C(0),	// V_ADD_CO_CI_U32_dpp8_w32_gfx12
    UINT64_C(1342177280), UINT64_C(0),	// V_ADD_CO_CI_U32_dpp8_w64_gfx10
    UINT64_C(1073741824), UINT64_C(0),	// V_ADD_CO_CI_U32_dpp8_w64_gfx11
    UINT64_C(1073741824), UINT64_C(0),	// V_ADD_CO_CI_U32_dpp8_w64_gfx12
    UINT64_C(1342177530), UINT64_C(0),	// V_ADD_CO_CI_U32_dpp_gfx10
    UINT64_C(1073742074), UINT64_C(0),	// V_ADD_CO_CI_U32_dpp_gfx11
    UINT64_C(1073742074), UINT64_C(0),	// V_ADD_CO_CI_U32_dpp_gfx12
    UINT64_C(1342177530), UINT64_C(0),	// V_ADD_CO_CI_U32_dpp_w32_gfx10
    UINT64_C(1073742074), UINT64_C(0),	// V_ADD_CO_CI_U32_dpp_w32_gfx11
    UINT64_C(1073742074), UINT64_C(0),	// V_ADD_CO_CI_U32_dpp_w32_gfx12
    UINT64_C(1342177530), UINT64_C(0),	// V_ADD_CO_CI_U32_dpp_w64_gfx10
    UINT64_C(1073742074), UINT64_C(0),	// V_ADD_CO_CI_U32_dpp_w64_gfx11
    UINT64_C(1073742074), UINT64_C(0),	// V_ADD_CO_CI_U32_dpp_w64_gfx12
    UINT64_C(1342177280), UINT64_C(0),	// V_ADD_CO_CI_U32_e32_gfx10
    UINT64_C(1073741824), UINT64_C(0),	// V_ADD_CO_CI_U32_e32_gfx11
    UINT64_C(1073741824), UINT64_C(0),	// V_ADD_CO_CI_U32_e32_gfx12
    UINT64_C(3575644160), UINT64_C(0),	// V_ADD_CO_CI_U32_e64_dpp8_gfx11
    UINT64_C(3575644160), UINT64_C(0),	// V_ADD_CO_CI_U32_e64_dpp8_gfx12
    UINT64_C(1077317468160), UINT64_C(0),	// V_ADD_CO_CI_U32_e64_dpp_gfx11
    UINT64_C(1077317468160), UINT64_C(0),	// V_ADD_CO_CI_U32_e64_dpp_gfx12
    UINT64_C(3576168448), UINT64_C(0),	// V_ADD_CO_CI_U32_e64_gfx10
    UINT64_C(3575644160), UINT64_C(0),	// V_ADD_CO_CI_U32_e64_gfx11
    UINT64_C(3575644160), UINT64_C(0),	// V_ADD_CO_CI_U32_e64_gfx12
    UINT64_C(1342177529), UINT64_C(0),	// V_ADD_CO_CI_U32_sdwa_gfx10
    UINT64_C(1342177529), UINT64_C(0),	// V_ADD_CO_CI_U32_sdwa_w32_gfx10
    UINT64_C(1342177529), UINT64_C(0),	// V_ADD_CO_CI_U32_sdwa_w64_gfx10
    UINT64_C(838861050), UINT64_C(0),	// V_ADD_CO_U32_dpp_gfx9
    UINT64_C(838860800), UINT64_C(0),	// V_ADD_CO_U32_e32_gfx9
    UINT64_C(3607101440), UINT64_C(0),	// V_ADD_CO_U32_e64_dpp8_gfx11
    UINT64_C(3607101440), UINT64_C(0),	// V_ADD_CO_U32_e64_dpp8_gfx12
    UINT64_C(1077348925440), UINT64_C(0),	// V_ADD_CO_U32_e64_dpp_gfx11
    UINT64_C(1077348925440), UINT64_C(0),	// V_ADD_CO_U32_e64_dpp_gfx12
    UINT64_C(3608084480), UINT64_C(0),	// V_ADD_CO_U32_e64_gfx10
    UINT64_C(3607101440), UINT64_C(0),	// V_ADD_CO_U32_e64_gfx11
    UINT64_C(3607101440), UINT64_C(0),	// V_ADD_CO_U32_e64_gfx12
    UINT64_C(3508076544), UINT64_C(0),	// V_ADD_CO_U32_e64_gfx9
    UINT64_C(838861049), UINT64_C(0),	// V_ADD_CO_U32_sdwa_gfx9
    UINT64_C(1677721600), UINT64_C(0),	// V_ADD_F16_dpp8_gfx10
    UINT64_C(1677721850), UINT64_C(0),	// V_ADD_F16_dpp_gfx10
    UINT64_C(1040187642), UINT64_C(0),	// V_ADD_F16_dpp_vi
    UINT64_C(1677721600), UINT64_C(0),	// V_ADD_F16_e32_gfx10
    UINT64_C(1040187392), UINT64_C(0),	// V_ADD_F16_e32_vi
    UINT64_C(3576823808), UINT64_C(0),	// V_ADD_F16_e64_gfx10
    UINT64_C(3508469760), UINT64_C(0),	// V_ADD_F16_e64_vi
    UINT64_C(1677721600), UINT64_C(0),	// V_ADD_F16_fake16_dpp8_gfx11
    UINT64_C(1677721600), UINT64_C(0),	// V_ADD_F16_fake16_dpp8_gfx12
    UINT64_C(1677721850), UINT64_C(0),	// V_ADD_F16_fake16_dpp_gfx11
    UINT64_C(1677721850), UINT64_C(0),	// V_ADD_F16_fake16_dpp_gfx12
    UINT64_C(1677721600), UINT64_C(0),	// V_ADD_F16_fake16_e32_gfx11
    UINT64_C(1677721600), UINT64_C(0),	// V_ADD_F16_fake16_e32_gfx12
    UINT64_C(3576823808), UINT64_C(0),	// V_ADD_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3576823808), UINT64_C(0),	// V_ADD_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077318647808), UINT64_C(0),	// V_ADD_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077318647808), UINT64_C(0),	// V_ADD_F16_fake16_e64_dpp_gfx12
    UINT64_C(3576823808), UINT64_C(0),	// V_ADD_F16_fake16_e64_gfx11
    UINT64_C(3576823808), UINT64_C(0),	// V_ADD_F16_fake16_e64_gfx12
    UINT64_C(1677721849), UINT64_C(0),	// V_ADD_F16_sdwa_gfx10
    UINT64_C(1040187641), UINT64_C(0),	// V_ADD_F16_sdwa_gfx9
    UINT64_C(1040187641), UINT64_C(0),	// V_ADD_F16_sdwa_vi
    UINT64_C(1677721600), UINT64_C(0),	// V_ADD_F16_t16_dpp8_gfx11
    UINT64_C(1677721600), UINT64_C(0),	// V_ADD_F16_t16_dpp8_gfx12
    UINT64_C(1677721850), UINT64_C(0),	// V_ADD_F16_t16_dpp_gfx11
    UINT64_C(1677721850), UINT64_C(0),	// V_ADD_F16_t16_dpp_gfx12
    UINT64_C(1677721600), UINT64_C(0),	// V_ADD_F16_t16_e32_gfx11
    UINT64_C(1677721600), UINT64_C(0),	// V_ADD_F16_t16_e32_gfx12
    UINT64_C(3576823808), UINT64_C(0),	// V_ADD_F16_t16_e64_dpp8_gfx11
    UINT64_C(3576823808), UINT64_C(0),	// V_ADD_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077318647808), UINT64_C(0),	// V_ADD_F16_t16_e64_dpp_gfx11
    UINT64_C(1077318647808), UINT64_C(0),	// V_ADD_F16_t16_e64_dpp_gfx12
    UINT64_C(3576823808), UINT64_C(0),	// V_ADD_F16_t16_e64_gfx11
    UINT64_C(3576823808), UINT64_C(0),	// V_ADD_F16_t16_e64_gfx12
    UINT64_C(100663296), UINT64_C(0),	// V_ADD_F32_dpp8_gfx10
    UINT64_C(100663296), UINT64_C(0),	// V_ADD_F32_dpp8_gfx11
    UINT64_C(100663296), UINT64_C(0),	// V_ADD_F32_dpp8_gfx12
    UINT64_C(100663546), UINT64_C(0),	// V_ADD_F32_dpp_gfx10
    UINT64_C(100663546), UINT64_C(0),	// V_ADD_F32_dpp_gfx11
    UINT64_C(100663546), UINT64_C(0),	// V_ADD_F32_dpp_gfx12
    UINT64_C(33554682), UINT64_C(0),	// V_ADD_F32_dpp_vi
    UINT64_C(100663296), UINT64_C(0),	// V_ADD_F32_e32_gfx10
    UINT64_C(100663296), UINT64_C(0),	// V_ADD_F32_e32_gfx11
    UINT64_C(100663296), UINT64_C(0),	// V_ADD_F32_e32_gfx12
    UINT64_C(100663296), UINT64_C(0),	// V_ADD_F32_e32_gfx6_gfx7
    UINT64_C(33554432), UINT64_C(0),	// V_ADD_F32_e32_vi
    UINT64_C(3573743616), UINT64_C(0),	// V_ADD_F32_e64_dpp8_gfx11
    UINT64_C(3573743616), UINT64_C(0),	// V_ADD_F32_e64_dpp8_gfx12
    UINT64_C(1077315567616), UINT64_C(0),	// V_ADD_F32_e64_dpp_gfx11
    UINT64_C(1077315567616), UINT64_C(0),	// V_ADD_F32_e64_dpp_gfx12
    UINT64_C(3573743616), UINT64_C(0),	// V_ADD_F32_e64_gfx10
    UINT64_C(3573743616), UINT64_C(0),	// V_ADD_F32_e64_gfx11
    UINT64_C(3573743616), UINT64_C(0),	// V_ADD_F32_e64_gfx12
    UINT64_C(3523608576), UINT64_C(0),	// V_ADD_F32_e64_gfx6_gfx7
    UINT64_C(3506503680), UINT64_C(0),	// V_ADD_F32_e64_vi
    UINT64_C(100663545), UINT64_C(0),	// V_ADD_F32_sdwa_gfx10
    UINT64_C(33554681), UINT64_C(0),	// V_ADD_F32_sdwa_gfx9
    UINT64_C(33554681), UINT64_C(0),	// V_ADD_F32_sdwa_vi
    UINT64_C(67109114), UINT64_C(0),	// V_ADD_F64_dpp_gfx12
    UINT64_C(67108864), UINT64_C(0),	// V_ADD_F64_e32_gfx12
    UINT64_C(1077315502080), UINT64_C(0),	// V_ADD_F64_e64_dpp_gfx12
    UINT64_C(3609657344), UINT64_C(0),	// V_ADD_F64_e64_gfx11
    UINT64_C(3573678080), UINT64_C(0),	// V_ADD_F64_e64_gfx12
    UINT64_C(3580100608), UINT64_C(0),	// V_ADD_F64_gfx10
    UINT64_C(3536322560), UINT64_C(0),	// V_ADD_F64_gfx6_gfx7
    UINT64_C(3531603968), UINT64_C(0),	// V_ADD_F64_vi
    UINT64_C(3533570048), UINT64_C(0),	// V_ADD_I16_vi
    UINT64_C(1241513984), UINT64_C(0),	// V_ADD_I32_e32_gfx6_gfx7
    UINT64_C(3528065024), UINT64_C(0),	// V_ADD_I32_e64_gfx6_gfx7
    UINT64_C(3533438976), UINT64_C(0),	// V_ADD_I32_vi
    UINT64_C(3594977280), UINT64_C(0),	// V_ADD_LSHL_U32_e64_dpp8_gfx11
    UINT64_C(3594977280), UINT64_C(0),	// V_ADD_LSHL_U32_e64_dpp8_gfx12
    UINT64_C(1077336801280), UINT64_C(0),	// V_ADD_LSHL_U32_e64_dpp_gfx11
    UINT64_C(1077336801280), UINT64_C(0),	// V_ADD_LSHL_U32_e64_dpp_gfx12
    UINT64_C(3594977280), UINT64_C(0),	// V_ADD_LSHL_U32_e64_gfx11
    UINT64_C(3594977280), UINT64_C(0),	// V_ADD_LSHL_U32_e64_gfx12
    UINT64_C(3611754496), UINT64_C(0),	// V_ADD_LSHL_U32_gfx10
    UINT64_C(3523084288), UINT64_C(0),	// V_ADD_LSHL_U32_vi
    UINT64_C(3596484608), UINT64_C(0),	// V_ADD_MAX_I32_e64_dpp8_gfx1250
    UINT64_C(1077338308608), UINT64_C(0),	// V_ADD_MAX_I32_e64_dpp_gfx1250
    UINT64_C(3596484608), UINT64_C(0),	// V_ADD_MAX_I32_e64_gfx1250
    UINT64_C(3596550144), UINT64_C(0),	// V_ADD_MAX_U32_e64_dpp8_gfx1250
    UINT64_C(1077338374144), UINT64_C(0),	// V_ADD_MAX_U32_e64_dpp_gfx1250
    UINT64_C(3596550144), UINT64_C(0),	// V_ADD_MAX_U32_e64_gfx1250
    UINT64_C(3596615680), UINT64_C(0),	// V_ADD_MIN_I32_e64_dpp8_gfx1250
    UINT64_C(1077338439680), UINT64_C(0),	// V_ADD_MIN_I32_e64_dpp_gfx1250
    UINT64_C(3596615680), UINT64_C(0),	// V_ADD_MIN_I32_e64_gfx1250
    UINT64_C(3596681216), UINT64_C(0),	// V_ADD_MIN_U32_e64_dpp8_gfx1250
    UINT64_C(1077338505216), UINT64_C(0),	// V_ADD_MIN_U32_e64_dpp_gfx1250
    UINT64_C(3596681216), UINT64_C(0),	// V_ADD_MIN_U32_e64_gfx1250
    UINT64_C(3607953408), UINT64_C(0),	// V_ADD_NC_I16V_ADD_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3607953408), UINT64_C(0),	// V_ADD_NC_I16V_ADD_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077349777408), UINT64_C(0),	// V_ADD_NC_I16V_ADD_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077349777408), UINT64_C(0),	// V_ADD_NC_I16V_ADD_I16_fake16_e64_dpp_gfx12
    UINT64_C(3607953408), UINT64_C(0),	// V_ADD_NC_I16V_ADD_I16_fake16_e64_gfx11
    UINT64_C(3607953408), UINT64_C(0),	// V_ADD_NC_I16V_ADD_I16_fake16_e64_gfx12
    UINT64_C(3607953408), UINT64_C(0),	// V_ADD_NC_I16V_ADD_I16_t16_e64_dpp8_gfx11
    UINT64_C(3607953408), UINT64_C(0),	// V_ADD_NC_I16V_ADD_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077349777408), UINT64_C(0),	// V_ADD_NC_I16V_ADD_I16_t16_e64_dpp_gfx11
    UINT64_C(1077349777408), UINT64_C(0),	// V_ADD_NC_I16V_ADD_I16_t16_e64_dpp_gfx12
    UINT64_C(3607953408), UINT64_C(0),	// V_ADD_NC_I16V_ADD_I16_t16_e64_gfx11
    UINT64_C(3607953408), UINT64_C(0),	// V_ADD_NC_I16V_ADD_I16_t16_e64_gfx12
    UINT64_C(3607953408), UINT64_C(0),	// V_ADD_NC_I16_gfx10
    UINT64_C(3609591808), UINT64_C(0),	// V_ADD_NC_I32_e64_dpp8_gfx11
    UINT64_C(3609591808), UINT64_C(0),	// V_ADD_NC_I32_e64_dpp8_gfx12
    UINT64_C(1077351415808), UINT64_C(0),	// V_ADD_NC_I32_e64_dpp_gfx11
    UINT64_C(1077351415808), UINT64_C(0),	// V_ADD_NC_I32_e64_dpp_gfx12
    UINT64_C(3609591808), UINT64_C(0),	// V_ADD_NC_I32_e64_gfx11
    UINT64_C(3609591808), UINT64_C(0),	// V_ADD_NC_I32_e64_gfx12
    UINT64_C(3615424512), UINT64_C(0),	// V_ADD_NC_I32_gfx10
    UINT64_C(3607298048), UINT64_C(0),	// V_ADD_NC_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3607298048), UINT64_C(0),	// V_ADD_NC_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077349122048), UINT64_C(0),	// V_ADD_NC_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077349122048), UINT64_C(0),	// V_ADD_NC_U16_fake16_e64_dpp_gfx12
    UINT64_C(3607298048), UINT64_C(0),	// V_ADD_NC_U16_fake16_e64_gfx11
    UINT64_C(3607298048), UINT64_C(0),	// V_ADD_NC_U16_fake16_e64_gfx12
    UINT64_C(3607298048), UINT64_C(0),	// V_ADD_NC_U16_gfx10
    UINT64_C(3607298048), UINT64_C(0),	// V_ADD_NC_U16_t16_e64_dpp8_gfx11
    UINT64_C(3607298048), UINT64_C(0),	// V_ADD_NC_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077349122048), UINT64_C(0),	// V_ADD_NC_U16_t16_e64_dpp_gfx11
    UINT64_C(1077349122048), UINT64_C(0),	// V_ADD_NC_U16_t16_e64_dpp_gfx12
    UINT64_C(3607298048), UINT64_C(0),	// V_ADD_NC_U16_t16_e64_gfx11
    UINT64_C(3607298048), UINT64_C(0),	// V_ADD_NC_U16_t16_e64_gfx12
    UINT64_C(1241513984), UINT64_C(0),	// V_ADD_NC_U32_dpp8_gfx10
    UINT64_C(1241513984), UINT64_C(0),	// V_ADD_NC_U32_dpp8_gfx11
    UINT64_C(1241513984), UINT64_C(0),	// V_ADD_NC_U32_dpp8_gfx12
    UINT64_C(1241514234), UINT64_C(0),	// V_ADD_NC_U32_dpp_gfx10
    UINT64_C(1241514234), UINT64_C(0),	// V_ADD_NC_U32_dpp_gfx11
    UINT64_C(1241514234), UINT64_C(0),	// V_ADD_NC_U32_dpp_gfx12
    UINT64_C(1241513984), UINT64_C(0),	// V_ADD_NC_U32_e32_gfx10
    UINT64_C(1241513984), UINT64_C(0),	// V_ADD_NC_U32_e32_gfx11
    UINT64_C(1241513984), UINT64_C(0),	// V_ADD_NC_U32_e32_gfx12
    UINT64_C(3575971840), UINT64_C(0),	// V_ADD_NC_U32_e64_dpp8_gfx11
    UINT64_C(3575971840), UINT64_C(0),	// V_ADD_NC_U32_e64_dpp8_gfx12
    UINT64_C(1077317795840), UINT64_C(0),	// V_ADD_NC_U32_e64_dpp_gfx11
    UINT64_C(1077317795840), UINT64_C(0),	// V_ADD_NC_U32_e64_dpp_gfx12
    UINT64_C(3575971840), UINT64_C(0),	// V_ADD_NC_U32_e64_gfx10
    UINT64_C(3575971840), UINT64_C(0),	// V_ADD_NC_U32_e64_gfx11
    UINT64_C(3575971840), UINT64_C(0),	// V_ADD_NC_U32_e64_gfx12
    UINT64_C(1241514233), UINT64_C(0),	// V_ADD_NC_U32_sdwa_gfx10
    UINT64_C(1275068666), UINT64_C(0),	// V_ADD_U16_dpp_vi
    UINT64_C(1275068416), UINT64_C(0),	// V_ADD_U16_e32_vi
    UINT64_C(3508928512), UINT64_C(0),	// V_ADD_U16_e64_vi
    UINT64_C(1275068665), UINT64_C(0),	// V_ADD_U16_sdwa_gfx9
    UINT64_C(1275068665), UINT64_C(0),	// V_ADD_U16_sdwa_vi
    UINT64_C(1744830714), UINT64_C(0),	// V_ADD_U32_dpp_gfx9
    UINT64_C(838861050), UINT64_C(0),	// V_ADD_U32_dpp_vi
    UINT64_C(1744830464), UINT64_C(0),	// V_ADD_U32_e32_gfx9
    UINT64_C(838860800), UINT64_C(0),	// V_ADD_U32_e32_vi
    UINT64_C(3509846016), UINT64_C(0),	// V_ADD_U32_e64_gfx9
    UINT64_C(3508076544), UINT64_C(0),	// V_ADD_U32_e64_vi
    UINT64_C(1744830713), UINT64_C(0),	// V_ADD_U32_sdwa_gfx9
    UINT64_C(838861049), UINT64_C(0),	// V_ADD_U32_sdwa_vi
    UINT64_C(1342177530), UINT64_C(0),	// V_ADD_U64_dpp_gfx1250
    UINT64_C(1342177280), UINT64_C(0),	// V_ADD_U64_e32_gfx1250
    UINT64_C(1077317992448), UINT64_C(0),	// V_ADD_U64_e64_dpp_gfx1250
    UINT64_C(3576168448), UINT64_C(0),	// V_ADD_U64_e64_gfx1250
    UINT64_C(3591766016), UINT64_C(0),	// V_ALIGNBIT_B32V_ALIGNBIT_B32_fake16_e64_dpp8_gfx11
    UINT64_C(3591766016), UINT64_C(0),	// V_ALIGNBIT_B32V_ALIGNBIT_B32_fake16_e64_dpp8_gfx12
    UINT64_C(1077333590016), UINT64_C(0),	// V_ALIGNBIT_B32V_ALIGNBIT_B32_fake16_e64_dpp_gfx11
    UINT64_C(1077333590016), UINT64_C(0),	// V_ALIGNBIT_B32V_ALIGNBIT_B32_fake16_e64_dpp_gfx12
    UINT64_C(3591766016), UINT64_C(0),	// V_ALIGNBIT_B32V_ALIGNBIT_B32_fake16_e64_gfx11
    UINT64_C(3591766016), UINT64_C(0),	// V_ALIGNBIT_B32V_ALIGNBIT_B32_fake16_e64_gfx12
    UINT64_C(3591766016), UINT64_C(0),	// V_ALIGNBIT_B32V_ALIGNBIT_B32_t16_e64_dpp8_gfx11
    UINT64_C(3591766016), UINT64_C(0),	// V_ALIGNBIT_B32V_ALIGNBIT_B32_t16_e64_dpp8_gfx12
    UINT64_C(1077333590016), UINT64_C(0),	// V_ALIGNBIT_B32V_ALIGNBIT_B32_t16_e64_dpp_gfx11
    UINT64_C(1077333590016), UINT64_C(0),	// V_ALIGNBIT_B32V_ALIGNBIT_B32_t16_e64_dpp_gfx12
    UINT64_C(3591766016), UINT64_C(0),	// V_ALIGNBIT_B32V_ALIGNBIT_B32_t16_e64_gfx11
    UINT64_C(3591766016), UINT64_C(0),	// V_ALIGNBIT_B32V_ALIGNBIT_B32_t16_e64_gfx12
    UINT64_C(3533438976), UINT64_C(0),	// V_ALIGNBIT_B32_gfx6_gfx7
    UINT64_C(3578658816), UINT64_C(0),	// V_ALIGNBIT_B32_opsel_gfx10
    UINT64_C(3519938560), UINT64_C(0),	// V_ALIGNBIT_B32_opsel_gfx9
    UINT64_C(3519938560), UINT64_C(0),	// V_ALIGNBIT_B32_vi
    UINT64_C(3591831552), UINT64_C(0),	// V_ALIGNBYTE_B32V_ALIGNBYTE_B32_fake16_e64_dpp8_gfx11
    UINT64_C(3591831552), UINT64_C(0),	// V_ALIGNBYTE_B32V_ALIGNBYTE_B32_fake16_e64_dpp8_gfx12
    UINT64_C(1077333655552), UINT64_C(0),	// V_ALIGNBYTE_B32V_ALIGNBYTE_B32_fake16_e64_dpp_gfx11
    UINT64_C(1077333655552), UINT64_C(0),	// V_ALIGNBYTE_B32V_ALIGNBYTE_B32_fake16_e64_dpp_gfx12
    UINT64_C(3591831552), UINT64_C(0),	// V_ALIGNBYTE_B32V_ALIGNBYTE_B32_fake16_e64_gfx11
    UINT64_C(3591831552), UINT64_C(0),	// V_ALIGNBYTE_B32V_ALIGNBYTE_B32_fake16_e64_gfx12
    UINT64_C(3591831552), UINT64_C(0),	// V_ALIGNBYTE_B32V_ALIGNBYTE_B32_t16_e64_dpp8_gfx11
    UINT64_C(3591831552), UINT64_C(0),	// V_ALIGNBYTE_B32V_ALIGNBYTE_B32_t16_e64_dpp8_gfx12
    UINT64_C(1077333655552), UINT64_C(0),	// V_ALIGNBYTE_B32V_ALIGNBYTE_B32_t16_e64_dpp_gfx11
    UINT64_C(1077333655552), UINT64_C(0),	// V_ALIGNBYTE_B32V_ALIGNBYTE_B32_t16_e64_dpp_gfx12
    UINT64_C(3591831552), UINT64_C(0),	// V_ALIGNBYTE_B32V_ALIGNBYTE_B32_t16_e64_gfx11
    UINT64_C(3591831552), UINT64_C(0),	// V_ALIGNBYTE_B32V_ALIGNBYTE_B32_t16_e64_gfx12
    UINT64_C(3533570048), UINT64_C(0),	// V_ALIGNBYTE_B32_gfx6_gfx7
    UINT64_C(3578724352), UINT64_C(0),	// V_ALIGNBYTE_B32_opsel_gfx10
    UINT64_C(3520004096), UINT64_C(0),	// V_ALIGNBYTE_B32_opsel_gfx9
    UINT64_C(3520004096), UINT64_C(0),	// V_ALIGNBYTE_B32_vi
    UINT64_C(3613523968), UINT64_C(0),	// V_AND_B16_fake16_e64_dpp8_gfx11
    UINT64_C(3613523968), UINT64_C(0),	// V_AND_B16_fake16_e64_dpp8_gfx12
    UINT64_C(1077355347968), UINT64_C(0),	// V_AND_B16_fake16_e64_dpp_gfx11
    UINT64_C(1077355347968), UINT64_C(0),	// V_AND_B16_fake16_e64_dpp_gfx12
    UINT64_C(3613523968), UINT64_C(0),	// V_AND_B16_fake16_e64_gfx11
    UINT64_C(3613523968), UINT64_C(0),	// V_AND_B16_fake16_e64_gfx12
    UINT64_C(3613523968), UINT64_C(0),	// V_AND_B16_t16_e64_dpp8_gfx11
    UINT64_C(3613523968), UINT64_C(0),	// V_AND_B16_t16_e64_dpp8_gfx12
    UINT64_C(1077355347968), UINT64_C(0),	// V_AND_B16_t16_e64_dpp_gfx11
    UINT64_C(1077355347968), UINT64_C(0),	// V_AND_B16_t16_e64_dpp_gfx12
    UINT64_C(3613523968), UINT64_C(0),	// V_AND_B16_t16_e64_gfx11
    UINT64_C(3613523968), UINT64_C(0),	// V_AND_B16_t16_e64_gfx12
    UINT64_C(905969664), UINT64_C(0),	// V_AND_B32_dpp8_gfx10
    UINT64_C(905969664), UINT64_C(0),	// V_AND_B32_dpp8_gfx11
    UINT64_C(905969664), UINT64_C(0),	// V_AND_B32_dpp8_gfx12
    UINT64_C(905969914), UINT64_C(0),	// V_AND_B32_dpp_gfx10
    UINT64_C(905969914), UINT64_C(0),	// V_AND_B32_dpp_gfx11
    UINT64_C(905969914), UINT64_C(0),	// V_AND_B32_dpp_gfx12
    UINT64_C(637534458), UINT64_C(0),	// V_AND_B32_dpp_vi
    UINT64_C(905969664), UINT64_C(0),	// V_AND_B32_e32_gfx10
    UINT64_C(905969664), UINT64_C(0),	// V_AND_B32_e32_gfx11
    UINT64_C(905969664), UINT64_C(0),	// V_AND_B32_e32_gfx12
    UINT64_C(905969664), UINT64_C(0),	// V_AND_B32_e32_gfx6_gfx7
    UINT64_C(637534208), UINT64_C(0),	// V_AND_B32_e32_vi
    UINT64_C(3575316480), UINT64_C(0),	// V_AND_B32_e64_dpp8_gfx11
    UINT64_C(3575316480), UINT64_C(0),	// V_AND_B32_e64_dpp8_gfx12
    UINT64_C(1077317140480), UINT64_C(0),	// V_AND_B32_e64_dpp_gfx11
    UINT64_C(1077317140480), UINT64_C(0),	// V_AND_B32_e64_dpp_gfx12
    UINT64_C(3575316480), UINT64_C(0),	// V_AND_B32_e64_gfx10
    UINT64_C(3575316480), UINT64_C(0),	// V_AND_B32_e64_gfx11
    UINT64_C(3575316480), UINT64_C(0),	// V_AND_B32_e64_gfx12
    UINT64_C(3526754304), UINT64_C(0),	// V_AND_B32_e64_gfx6_gfx7
    UINT64_C(3507683328), UINT64_C(0),	// V_AND_B32_e64_vi
    UINT64_C(905969913), UINT64_C(0),	// V_AND_B32_sdwa_gfx10
    UINT64_C(637534457), UINT64_C(0),	// V_AND_B32_sdwa_gfx9
    UINT64_C(637534457), UINT64_C(0),	// V_AND_B32_sdwa_vi
    UINT64_C(3596025856), UINT64_C(0),	// V_AND_OR_B32_e64_dpp8_gfx11
    UINT64_C(3596025856), UINT64_C(0),	// V_AND_OR_B32_e64_dpp8_gfx12
    UINT64_C(1077337849856), UINT64_C(0),	// V_AND_OR_B32_e64_dpp_gfx11
    UINT64_C(1077337849856), UINT64_C(0),	// V_AND_OR_B32_e64_dpp_gfx12
    UINT64_C(3596025856), UINT64_C(0),	// V_AND_OR_B32_e64_gfx11
    UINT64_C(3596025856), UINT64_C(0),	// V_AND_OR_B32_e64_gfx12
    UINT64_C(3614507008), UINT64_C(0),	// V_AND_OR_B32_gfx10
    UINT64_C(3523280896), UINT64_C(0),	// V_AND_OR_B32_vi
    UINT64_C(1476395258), UINT64_C(0),	// V_ASHRREV_I16_dpp_vi
    UINT64_C(1476395008), UINT64_C(0),	// V_ASHRREV_I16_e32_vi
    UINT64_C(3509321728), UINT64_C(0),	// V_ASHRREV_I16_e64_vi
    UINT64_C(3610902528), UINT64_C(0),	// V_ASHRREV_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3610902528), UINT64_C(0),	// V_ASHRREV_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077352726528), UINT64_C(0),	// V_ASHRREV_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077352726528), UINT64_C(0),	// V_ASHRREV_I16_fake16_e64_dpp_gfx12
    UINT64_C(3610902528), UINT64_C(0),	// V_ASHRREV_I16_fake16_e64_gfx11
    UINT64_C(3610902528), UINT64_C(0),	// V_ASHRREV_I16_fake16_e64_gfx12
    UINT64_C(3607625728), UINT64_C(0),	// V_ASHRREV_I16_gfx10
    UINT64_C(1476395257), UINT64_C(0),	// V_ASHRREV_I16_sdwa_gfx9
    UINT64_C(1476395257), UINT64_C(0),	// V_ASHRREV_I16_sdwa_vi
    UINT64_C(3610902528), UINT64_C(0),	// V_ASHRREV_I16_t16_e64_dpp8_gfx11
    UINT64_C(3610902528), UINT64_C(0),	// V_ASHRREV_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077352726528), UINT64_C(0),	// V_ASHRREV_I16_t16_e64_dpp_gfx11
    UINT64_C(1077352726528), UINT64_C(0),	// V_ASHRREV_I16_t16_e64_dpp_gfx12
    UINT64_C(3610902528), UINT64_C(0),	// V_ASHRREV_I16_t16_e64_gfx11
    UINT64_C(3610902528), UINT64_C(0),	// V_ASHRREV_I16_t16_e64_gfx12
    UINT64_C(805306368), UINT64_C(0),	// V_ASHRREV_I32_dpp8_gfx10
    UINT64_C(872415232), UINT64_C(0),	// V_ASHRREV_I32_dpp8_gfx11
    UINT64_C(872415232), UINT64_C(0),	// V_ASHRREV_I32_dpp8_gfx12
    UINT64_C(805306618), UINT64_C(0),	// V_ASHRREV_I32_dpp_gfx10
    UINT64_C(872415482), UINT64_C(0),	// V_ASHRREV_I32_dpp_gfx11
    UINT64_C(872415482), UINT64_C(0),	// V_ASHRREV_I32_dpp_gfx12
    UINT64_C(570425594), UINT64_C(0),	// V_ASHRREV_I32_dpp_vi
    UINT64_C(805306368), UINT64_C(0),	// V_ASHRREV_I32_e32_gfx10
    UINT64_C(872415232), UINT64_C(0),	// V_ASHRREV_I32_e32_gfx11
    UINT64_C(872415232), UINT64_C(0),	// V_ASHRREV_I32_e32_gfx12
    UINT64_C(805306368), UINT64_C(0),	// V_ASHRREV_I32_e32_gfx6_gfx7
    UINT64_C(570425344), UINT64_C(0),	// V_ASHRREV_I32_e32_vi
    UINT64_C(3575250944), UINT64_C(0),	// V_ASHRREV_I32_e64_dpp8_gfx11
    UINT64_C(3575250944), UINT64_C(0),	// V_ASHRREV_I32_e64_dpp8_gfx12
    UINT64_C(1077317074944), UINT64_C(0),	// V_ASHRREV_I32_e64_dpp_gfx11
    UINT64_C(1077317074944), UINT64_C(0),	// V_ASHRREV_I32_e64_dpp_gfx12
    UINT64_C(3575119872), UINT64_C(0),	// V_ASHRREV_I32_e64_gfx10
    UINT64_C(3575250944), UINT64_C(0),	// V_ASHRREV_I32_e64_gfx11
    UINT64_C(3575250944), UINT64_C(0),	// V_ASHRREV_I32_e64_gfx12
    UINT64_C(3526361088), UINT64_C(0),	// V_ASHRREV_I32_e64_gfx6_gfx7
    UINT64_C(3507552256), UINT64_C(0),	// V_ASHRREV_I32_e64_vi
    UINT64_C(805306617), UINT64_C(0),	// V_ASHRREV_I32_sdwa_gfx10
    UINT64_C(570425593), UINT64_C(0),	// V_ASHRREV_I32_sdwa_gfx9
    UINT64_C(570425593), UINT64_C(0),	// V_ASHRREV_I32_sdwa_vi
    UINT64_C(1077352988672), UINT64_C(0),	// V_ASHRREV_I64_e64_dpp_gfx1250
    UINT64_C(3611164672), UINT64_C(0),	// V_ASHRREV_I64_e64_gfx11
    UINT64_C(3611164672), UINT64_C(0),	// V_ASHRREV_I64_e64_gfx12
    UINT64_C(3611164672), UINT64_C(0),	// V_ASHRREV_I64_e64_gfx1250
    UINT64_C(3607166976), UINT64_C(0),	// V_ASHRREV_I64_gfx10
    UINT64_C(3532718080), UINT64_C(0),	// V_ASHRREV_I64_vi
    UINT64_C(771751936), UINT64_C(0),	// V_ASHR_I32_e32_gfx6_gfx7
    UINT64_C(3526230016), UINT64_C(0),	// V_ASHR_I32_e64_gfx6_gfx7
    UINT64_C(3536191488), UINT64_C(0),	// V_ASHR_I64_gfx6_gfx7
    UINT64_C(3599761408), UINT64_C(0),	// V_ASHR_PK_I8_I32_e64_dpp8_gfx1250
    UINT64_C(1077341585408), UINT64_C(0),	// V_ASHR_PK_I8_I32_e64_dpp_gfx1250
    UINT64_C(3599761408), UINT64_C(0),	// V_ASHR_PK_I8_I32_e64_gfx1250
    UINT64_C(3529834496), UINT64_C(0),	// V_ASHR_PK_I8_I32_vi
    UINT64_C(3599826944), UINT64_C(0),	// V_ASHR_PK_U8_I32_e64_dpp8_gfx1250
    UINT64_C(1077341650944), UINT64_C(0),	// V_ASHR_PK_U8_I32_e64_dpp_gfx1250
    UINT64_C(3599826944), UINT64_C(0),	// V_ASHR_PK_U8_I32_e64_gfx1250
    UINT64_C(3529900032), UINT64_C(0),	// V_ASHR_PK_U8_I32_vi
    UINT64_C(1140850688), UINT64_C(0),	// V_BCNT_U32_B32_e32_gfx6_gfx7
    UINT64_C(3609067520), UINT64_C(0),	// V_BCNT_U32_B32_e64_dpp8_gfx11
    UINT64_C(3609067520), UINT64_C(0),	// V_BCNT_U32_B32_e64_dpp8_gfx12
    UINT64_C(1077350891520), UINT64_C(0),	// V_BCNT_U32_B32_e64_dpp_gfx11
    UINT64_C(1077350891520), UINT64_C(0),	// V_BCNT_U32_B32_e64_dpp_gfx12
    UINT64_C(3613655040), UINT64_C(0),	// V_BCNT_U32_B32_e64_gfx10
    UINT64_C(3609067520), UINT64_C(0),	// V_BCNT_U32_B32_e64_gfx11
    UINT64_C(3609067520), UINT64_C(0),	// V_BCNT_U32_B32_e64_gfx12
    UINT64_C(3527671808), UINT64_C(0),	// V_BCNT_U32_B32_e64_gfx6_gfx7
    UINT64_C(3532324864), UINT64_C(0),	// V_BCNT_U32_B32_e64_vi
    UINT64_C(3591438336), UINT64_C(0),	// V_BFE_I32_e64_dpp8_gfx11
    UINT64_C(3591438336), UINT64_C(0),	// V_BFE_I32_e64_dpp8_gfx12
    UINT64_C(1077333262336), UINT64_C(0),	// V_BFE_I32_e64_dpp_gfx11
    UINT64_C(1077333262336), UINT64_C(0),	// V_BFE_I32_e64_dpp_gfx12
    UINT64_C(3591438336), UINT64_C(0),	// V_BFE_I32_e64_gfx11
    UINT64_C(3591438336), UINT64_C(0),	// V_BFE_I32_e64_gfx12
    UINT64_C(3578331136), UINT64_C(0),	// V_BFE_I32_gfx10
    UINT64_C(3532783616), UINT64_C(0),	// V_BFE_I32_gfx6_gfx7
    UINT64_C(3519610880), UINT64_C(0),	// V_BFE_I32_vi
    UINT64_C(3591372800), UINT64_C(0),	// V_BFE_U32_e64_dpp8_gfx11
    UINT64_C(3591372800), UINT64_C(0),	// V_BFE_U32_e64_dpp8_gfx12
    UINT64_C(1077333196800), UINT64_C(0),	// V_BFE_U32_e64_dpp_gfx11
    UINT64_C(1077333196800), UINT64_C(0),	// V_BFE_U32_e64_dpp_gfx12
    UINT64_C(3591372800), UINT64_C(0),	// V_BFE_U32_e64_gfx11
    UINT64_C(3591372800), UINT64_C(0),	// V_BFE_U32_e64_gfx12
    UINT64_C(3578265600), UINT64_C(0),	// V_BFE_U32_gfx10
    UINT64_C(3532652544), UINT64_C(0),	// V_BFE_U32_gfx6_gfx7
    UINT64_C(3519545344), UINT64_C(0),	// V_BFE_U32_vi
    UINT64_C(3591503872), UINT64_C(0),	// V_BFI_B32_e64_dpp8_gfx11
    UINT64_C(3591503872), UINT64_C(0),	// V_BFI_B32_e64_dpp8_gfx12
    UINT64_C(1077333327872), UINT64_C(0),	// V_BFI_B32_e64_dpp_gfx11
    UINT64_C(1077333327872), UINT64_C(0),	// V_BFI_B32_e64_dpp_gfx12
    UINT64_C(3591503872), UINT64_C(0),	// V_BFI_B32_e64_gfx11
    UINT64_C(3591503872), UINT64_C(0),	// V_BFI_B32_e64_gfx12
    UINT64_C(3578396672), UINT64_C(0),	// V_BFI_B32_gfx10
    UINT64_C(3532914688), UINT64_C(0),	// V_BFI_B32_gfx6_gfx7
    UINT64_C(3519676416), UINT64_C(0),	// V_BFI_B32_vi
    UINT64_C(1006632960), UINT64_C(0),	// V_BFM_B32_e32_gfx6_gfx7
    UINT64_C(3609001984), UINT64_C(0),	// V_BFM_B32_e64_dpp8_gfx11
    UINT64_C(3609001984), UINT64_C(0),	// V_BFM_B32_e64_dpp8_gfx12
    UINT64_C(1077350825984), UINT64_C(0),	// V_BFM_B32_e64_dpp_gfx11
    UINT64_C(1077350825984), UINT64_C(0),	// V_BFM_B32_e64_dpp_gfx12
    UINT64_C(3613589504), UINT64_C(0),	// V_BFM_B32_e64_gfx10
    UINT64_C(3609001984), UINT64_C(0),	// V_BFM_B32_e64_gfx11
    UINT64_C(3609001984), UINT64_C(0),	// V_BFM_B32_e64_gfx12
    UINT64_C(3527147520), UINT64_C(0),	// V_BFM_B32_e64_gfx6_gfx7
    UINT64_C(3532849152), UINT64_C(0),	// V_BFM_B32_e64_vi
    UINT64_C(2113957888), UINT64_C(0),	// V_BFREV_B32_dpp8_gfx10
    UINT64_C(2113957888), UINT64_C(0),	// V_BFREV_B32_dpp8_gfx11
    UINT64_C(2113957888), UINT64_C(0),	// V_BFREV_B32_dpp8_gfx12
    UINT64_C(2113958138), UINT64_C(0),	// V_BFREV_B32_dpp_gfx10
    UINT64_C(2113958138), UINT64_C(0),	// V_BFREV_B32_dpp_gfx11
    UINT64_C(2113958138), UINT64_C(0),	// V_BFREV_B32_dpp_gfx12
    UINT64_C(2113951994), UINT64_C(0),	// V_BFREV_B32_dpp_vi
    UINT64_C(2113957888), UINT64_C(0),	// V_BFREV_B32_e32_gfx10
    UINT64_C(2113957888), UINT64_C(0),	// V_BFREV_B32_e32_gfx11
    UINT64_C(2113957888), UINT64_C(0),	// V_BFREV_B32_e32_gfx12
    UINT64_C(2113957888), UINT64_C(0),	// V_BFREV_B32_e32_gfx6_gfx7
    UINT64_C(2113951744), UINT64_C(0),	// V_BFREV_B32_e32_vi
    UINT64_C(3585605632), UINT64_C(0),	// V_BFREV_B32_e64_dpp8_gfx11
    UINT64_C(3585605632), UINT64_C(0),	// V_BFREV_B32_e64_dpp8_gfx12
    UINT64_C(1077327429632), UINT64_C(0),	// V_BFREV_B32_e64_dpp_gfx11
    UINT64_C(1077327429632), UINT64_C(0),	// V_BFREV_B32_e64_dpp_gfx12
    UINT64_C(3585605632), UINT64_C(0),	// V_BFREV_B32_e64_gfx10
    UINT64_C(3585605632), UINT64_C(0),	// V_BFREV_B32_e64_gfx11
    UINT64_C(3585605632), UINT64_C(0),	// V_BFREV_B32_e64_gfx12
    UINT64_C(3547332608), UINT64_C(0),	// V_BFREV_B32_e64_gfx6_gfx7
    UINT64_C(3513516032), UINT64_C(0),	// V_BFREV_B32_e64_vi
    UINT64_C(2113958137), UINT64_C(0),	// V_BFREV_B32_sdwa_gfx10
    UINT64_C(2113951993), UINT64_C(0),	// V_BFREV_B32_sdwa_gfx9
    UINT64_C(2113951993), UINT64_C(0),	// V_BFREV_B32_sdwa_vi
    UINT64_C(3593666560), UINT64_C(0),	// V_BITOP3_B16_gfx1250_fake16_e64_dpp8_gfx1250
    UINT64_C(1077335490560), UINT64_C(0),	// V_BITOP3_B16_gfx1250_fake16_e64_dpp_gfx1250
    UINT64_C(3593666560), UINT64_C(0),	// V_BITOP3_B16_gfx1250_fake16_e64_gfx1250
    UINT64_C(3593666560), UINT64_C(0),	// V_BITOP3_B16_gfx1250_t16_e64_dpp8_gfx1250
    UINT64_C(1077335490560), UINT64_C(0),	// V_BITOP3_B16_gfx1250_t16_e64_dpp_gfx1250
    UINT64_C(3593666560), UINT64_C(0),	// V_BITOP3_B16_gfx1250_t16_e64_gfx1250
    UINT64_C(3526557696), UINT64_C(0),	// V_BITOP3_B16_gfx9
    UINT64_C(3593732096), UINT64_C(0),	// V_BITOP3_B32_e64_dpp8_gfx1250
    UINT64_C(1077335556096), UINT64_C(0),	// V_BITOP3_B32_e64_dpp_gfx1250
    UINT64_C(3593732096), UINT64_C(0),	// V_BITOP3_B32_e64_gfx1250
    UINT64_C(3526623232), UINT64_C(0),	// V_BITOP3_B32_gfx9
    UINT64_C(2113976320), UINT64_C(0),	// V_CEIL_F16_dpp8_gfx10
    UINT64_C(2113976570), UINT64_C(0),	// V_CEIL_F16_dpp_gfx10
    UINT64_C(2113964794), UINT64_C(0),	// V_CEIL_F16_dpp_vi
    UINT64_C(2113976320), UINT64_C(0),	// V_CEIL_F16_e32_gfx10
    UINT64_C(2113964544), UINT64_C(0),	// V_CEIL_F16_e32_vi
    UINT64_C(3587964928), UINT64_C(0),	// V_CEIL_F16_e64_gfx10
    UINT64_C(3515154432), UINT64_C(0),	// V_CEIL_F16_e64_vi
    UINT64_C(2113976320), UINT64_C(0),	// V_CEIL_F16_fake16_dpp8_gfx11
    UINT64_C(2113976320), UINT64_C(0),	// V_CEIL_F16_fake16_dpp8_gfx12
    UINT64_C(2113976570), UINT64_C(0),	// V_CEIL_F16_fake16_dpp_gfx11
    UINT64_C(2113976570), UINT64_C(0),	// V_CEIL_F16_fake16_dpp_gfx12
    UINT64_C(2113976320), UINT64_C(0),	// V_CEIL_F16_fake16_e32_gfx11
    UINT64_C(2113976320), UINT64_C(0),	// V_CEIL_F16_fake16_e32_gfx12
    UINT64_C(3587964928), UINT64_C(0),	// V_CEIL_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3587964928), UINT64_C(0),	// V_CEIL_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077329788928), UINT64_C(0),	// V_CEIL_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077329788928), UINT64_C(0),	// V_CEIL_F16_fake16_e64_dpp_gfx12
    UINT64_C(3587964928), UINT64_C(0),	// V_CEIL_F16_fake16_e64_gfx11
    UINT64_C(3587964928), UINT64_C(0),	// V_CEIL_F16_fake16_e64_gfx12
    UINT64_C(2113976569), UINT64_C(0),	// V_CEIL_F16_sdwa_gfx10
    UINT64_C(2113964793), UINT64_C(0),	// V_CEIL_F16_sdwa_gfx9
    UINT64_C(2113964793), UINT64_C(0),	// V_CEIL_F16_sdwa_vi
    UINT64_C(2113976320), UINT64_C(0),	// V_CEIL_F16_t16_dpp8_gfx11
    UINT64_C(2113976320), UINT64_C(0),	// V_CEIL_F16_t16_dpp8_gfx12
    UINT64_C(2113976570), UINT64_C(0),	// V_CEIL_F16_t16_dpp_gfx11
    UINT64_C(2113976570), UINT64_C(0),	// V_CEIL_F16_t16_dpp_gfx12
    UINT64_C(2113976320), UINT64_C(0),	// V_CEIL_F16_t16_e32_gfx11
    UINT64_C(2113976320), UINT64_C(0),	// V_CEIL_F16_t16_e32_gfx12
    UINT64_C(3587964928), UINT64_C(0),	// V_CEIL_F16_t16_e64_dpp8_gfx11
    UINT64_C(3587964928), UINT64_C(0),	// V_CEIL_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077329788928), UINT64_C(0),	// V_CEIL_F16_t16_e64_dpp_gfx11
    UINT64_C(1077329788928), UINT64_C(0),	// V_CEIL_F16_t16_e64_dpp_gfx12
    UINT64_C(3587964928), UINT64_C(0),	// V_CEIL_F16_t16_e64_gfx11
    UINT64_C(3587964928), UINT64_C(0),	// V_CEIL_F16_t16_e64_gfx12
    UINT64_C(2113946624), UINT64_C(0),	// V_CEIL_F32_dpp8_gfx10
    UINT64_C(2113946624), UINT64_C(0),	// V_CEIL_F32_dpp8_gfx11
    UINT64_C(2113946624), UINT64_C(0),	// V_CEIL_F32_dpp8_gfx12
    UINT64_C(2113946874), UINT64_C(0),	// V_CEIL_F32_dpp_gfx10
    UINT64_C(2113946874), UINT64_C(0),	// V_CEIL_F32_dpp_gfx11
    UINT64_C(2113946874), UINT64_C(0),	// V_CEIL_F32_dpp_gfx12
    UINT64_C(2113944314), UINT64_C(0),	// V_CEIL_F32_dpp_vi
    UINT64_C(2113946624), UINT64_C(0),	// V_CEIL_F32_e32_gfx10
    UINT64_C(2113946624), UINT64_C(0),	// V_CEIL_F32_e32_gfx11
    UINT64_C(2113946624), UINT64_C(0),	// V_CEIL_F32_e32_gfx12
    UINT64_C(2113946624), UINT64_C(0),	// V_CEIL_F32_e32_gfx6_gfx7
    UINT64_C(2113944064), UINT64_C(0),	// V_CEIL_F32_e32_vi
    UINT64_C(3584163840), UINT64_C(0),	// V_CEIL_F32_e64_dpp8_gfx11
    UINT64_C(3584163840), UINT64_C(0),	// V_CEIL_F32_e64_dpp8_gfx12
    UINT64_C(1077325987840), UINT64_C(0),	// V_CEIL_F32_e64_dpp_gfx11
    UINT64_C(1077325987840), UINT64_C(0),	// V_CEIL_F32_e64_dpp_gfx12
    UINT64_C(3584163840), UINT64_C(0),	// V_CEIL_F32_e64_gfx10
    UINT64_C(3584163840), UINT64_C(0),	// V_CEIL_F32_e64_gfx11
    UINT64_C(3584163840), UINT64_C(0),	// V_CEIL_F32_e64_gfx12
    UINT64_C(3544449024), UINT64_C(0),	// V_CEIL_F32_e64_gfx6_gfx7
    UINT64_C(3512532992), UINT64_C(0),	// V_CEIL_F32_e64_vi
    UINT64_C(2113946873), UINT64_C(0),	// V_CEIL_F32_sdwa_gfx10
    UINT64_C(2113944313), UINT64_C(0),	// V_CEIL_F32_sdwa_gfx9
    UINT64_C(2113944313), UINT64_C(0),	// V_CEIL_F32_sdwa_vi
    UINT64_C(2113941754), UINT64_C(0),	// V_CEIL_F64_dpp_gfx12
    UINT64_C(2113941754), UINT64_C(0),	// V_CEIL_F64_dpp_vi
    UINT64_C(2113941504), UINT64_C(0),	// V_CEIL_F64_e32_gfx10
    UINT64_C(2113941504), UINT64_C(0),	// V_CEIL_F64_e32_gfx11
    UINT64_C(2113941504), UINT64_C(0),	// V_CEIL_F64_e32_gfx12
    UINT64_C(2113941504), UINT64_C(0),	// V_CEIL_F64_e32_gfx7
    UINT64_C(2113941504), UINT64_C(0),	// V_CEIL_F64_e32_vi
    UINT64_C(1077325332480), UINT64_C(0),	// V_CEIL_F64_e64_dpp_gfx12
    UINT64_C(3583508480), UINT64_C(0),	// V_CEIL_F64_e64_gfx10
    UINT64_C(3583508480), UINT64_C(0),	// V_CEIL_F64_e64_gfx11
    UINT64_C(3583508480), UINT64_C(0),	// V_CEIL_F64_e64_gfx12
    UINT64_C(3543138304), UINT64_C(0),	// V_CEIL_F64_e64_gfx7
    UINT64_C(3512205312), UINT64_C(0),	// V_CEIL_F64_e64_vi
    UINT64_C(2113962496), UINT64_C(0),	// V_CLREXCP_e32_gfx10
    UINT64_C(2113962496), UINT64_C(0),	// V_CLREXCP_e32_gfx6_gfx7
    UINT64_C(2113956352), UINT64_C(0),	// V_CLREXCP_e32_vi
    UINT64_C(3586195456), UINT64_C(0),	// V_CLREXCP_e64_gfx10
    UINT64_C(3548512256), UINT64_C(0),	// V_CLREXCP_e64_gfx6_gfx7
    UINT64_C(3514105856), UINT64_C(0),	// V_CLREXCP_e64_vi
    UINT64_C(2113959424), UINT64_C(0),	// V_CLS_I32_dpp8_gfx11
    UINT64_C(2113959424), UINT64_C(0),	// V_CLS_I32_dpp8_gfx12
    UINT64_C(2113959674), UINT64_C(0),	// V_CLS_I32_dpp_gfx11
    UINT64_C(2113959674), UINT64_C(0),	// V_CLS_I32_dpp_gfx12
    UINT64_C(2113959424), UINT64_C(0),	// V_CLS_I32_e32_gfx11
    UINT64_C(2113959424), UINT64_C(0),	// V_CLS_I32_e32_gfx12
    UINT64_C(3585802240), UINT64_C(0),	// V_CLS_I32_e64_dpp8_gfx11
    UINT64_C(3585802240), UINT64_C(0),	// V_CLS_I32_e64_dpp8_gfx12
    UINT64_C(1077327626240), UINT64_C(0),	// V_CLS_I32_e64_dpp_gfx11
    UINT64_C(1077327626240), UINT64_C(0),	// V_CLS_I32_e64_dpp_gfx12
    UINT64_C(3585802240), UINT64_C(0),	// V_CLS_I32_e64_gfx11
    UINT64_C(3585802240), UINT64_C(0),	// V_CLS_I32_e64_gfx12
    UINT64_C(2113958400), UINT64_C(0),	// V_CLZ_I32_U32_dpp8_gfx11
    UINT64_C(2113958400), UINT64_C(0),	// V_CLZ_I32_U32_dpp8_gfx12
    UINT64_C(2113958650), UINT64_C(0),	// V_CLZ_I32_U32_dpp_gfx11
    UINT64_C(2113958650), UINT64_C(0),	// V_CLZ_I32_U32_dpp_gfx12
    UINT64_C(2113958400), UINT64_C(0),	// V_CLZ_I32_U32_e32_gfx11
    UINT64_C(2113958400), UINT64_C(0),	// V_CLZ_I32_U32_e32_gfx12
    UINT64_C(3585671168), UINT64_C(0),	// V_CLZ_I32_U32_e64_dpp8_gfx11
    UINT64_C(3585671168), UINT64_C(0),	// V_CLZ_I32_U32_e64_dpp8_gfx12
    UINT64_C(1077327495168), UINT64_C(0),	// V_CLZ_I32_U32_e64_dpp_gfx11
    UINT64_C(1077327495168), UINT64_C(0),	// V_CLZ_I32_U32_e64_dpp_gfx12
    UINT64_C(3585671168), UINT64_C(0),	// V_CLZ_I32_U32_e64_gfx11
    UINT64_C(3585671168), UINT64_C(0),	// V_CLZ_I32_U32_e64_gfx12
    UINT64_C(2091122688), UINT64_C(0),	// V_CMPSX_EQ_F32_e32_gfx6_gfx7
    UINT64_C(3500408832), UINT64_C(0),	// V_CMPSX_EQ_F32_e64_gfx6_gfx7
    UINT64_C(2095316992), UINT64_C(0),	// V_CMPSX_EQ_F64_e32_gfx6_gfx7
    UINT64_C(3504603136), UINT64_C(0),	// V_CMPSX_EQ_F64_e64_gfx6_gfx7
    UINT64_C(2090860544), UINT64_C(0),	// V_CMPSX_F_F32_e32_gfx6_gfx7
    UINT64_C(3500146688), UINT64_C(0),	// V_CMPSX_F_F32_e64_gfx6_gfx7
    UINT64_C(2095054848), UINT64_C(0),	// V_CMPSX_F_F64_e32_gfx6_gfx7
    UINT64_C(3504340992), UINT64_C(0),	// V_CMPSX_F_F64_e64_gfx6_gfx7
    UINT64_C(2091646976), UINT64_C(0),	// V_CMPSX_GE_F32_e32_gfx6_gfx7
    UINT64_C(3500933120), UINT64_C(0),	// V_CMPSX_GE_F32_e64_gfx6_gfx7
    UINT64_C(2095841280), UINT64_C(0),	// V_CMPSX_GE_F64_e32_gfx6_gfx7
    UINT64_C(3505127424), UINT64_C(0),	// V_CMPSX_GE_F64_e64_gfx6_gfx7
    UINT64_C(2091384832), UINT64_C(0),	// V_CMPSX_GT_F32_e32_gfx6_gfx7
    UINT64_C(3500670976), UINT64_C(0),	// V_CMPSX_GT_F32_e64_gfx6_gfx7
    UINT64_C(2095579136), UINT64_C(0),	// V_CMPSX_GT_F64_e32_gfx6_gfx7
    UINT64_C(3504865280), UINT64_C(0),	// V_CMPSX_GT_F64_e64_gfx6_gfx7
    UINT64_C(2091253760), UINT64_C(0),	// V_CMPSX_LE_F32_e32_gfx6_gfx7
    UINT64_C(3500539904), UINT64_C(0),	// V_CMPSX_LE_F32_e64_gfx6_gfx7
    UINT64_C(2095448064), UINT64_C(0),	// V_CMPSX_LE_F64_e32_gfx6_gfx7
    UINT64_C(3504734208), UINT64_C(0),	// V_CMPSX_LE_F64_e64_gfx6_gfx7
    UINT64_C(2091515904), UINT64_C(0),	// V_CMPSX_LG_F32_e32_gfx6_gfx7
    UINT64_C(3500802048), UINT64_C(0),	// V_CMPSX_LG_F32_e64_gfx6_gfx7
    UINT64_C(2095710208), UINT64_C(0),	// V_CMPSX_LG_F64_e32_gfx6_gfx7
    UINT64_C(3504996352), UINT64_C(0),	// V_CMPSX_LG_F64_e64_gfx6_gfx7
    UINT64_C(2090991616), UINT64_C(0),	// V_CMPSX_LT_F32_e32_gfx6_gfx7
    UINT64_C(3500277760), UINT64_C(0),	// V_CMPSX_LT_F32_e64_gfx6_gfx7
    UINT64_C(2095185920), UINT64_C(0),	// V_CMPSX_LT_F64_e32_gfx6_gfx7
    UINT64_C(3504472064), UINT64_C(0),	// V_CMPSX_LT_F64_e64_gfx6_gfx7
    UINT64_C(2092564480), UINT64_C(0),	// V_CMPSX_NEQ_F32_e32_gfx6_gfx7
    UINT64_C(3501850624), UINT64_C(0),	// V_CMPSX_NEQ_F32_e64_gfx6_gfx7
    UINT64_C(2096758784), UINT64_C(0),	// V_CMPSX_NEQ_F64_e32_gfx6_gfx7
    UINT64_C(3506044928), UINT64_C(0),	// V_CMPSX_NEQ_F64_e64_gfx6_gfx7
    UINT64_C(2092040192), UINT64_C(0),	// V_CMPSX_NGE_F32_e32_gfx6_gfx7
    UINT64_C(3501326336), UINT64_C(0),	// V_CMPSX_NGE_F32_e64_gfx6_gfx7
    UINT64_C(2096234496), UINT64_C(0),	// V_CMPSX_NGE_F64_e32_gfx6_gfx7
    UINT64_C(3505520640), UINT64_C(0),	// V_CMPSX_NGE_F64_e64_gfx6_gfx7
    UINT64_C(2092302336), UINT64_C(0),	// V_CMPSX_NGT_F32_e32_gfx6_gfx7
    UINT64_C(3501588480), UINT64_C(0),	// V_CMPSX_NGT_F32_e64_gfx6_gfx7
    UINT64_C(2096496640), UINT64_C(0),	// V_CMPSX_NGT_F64_e32_gfx6_gfx7
    UINT64_C(3505782784), UINT64_C(0),	// V_CMPSX_NGT_F64_e64_gfx6_gfx7
    UINT64_C(2092433408), UINT64_C(0),	// V_CMPSX_NLE_F32_e32_gfx6_gfx7
    UINT64_C(3501719552), UINT64_C(0),	// V_CMPSX_NLE_F32_e64_gfx6_gfx7
    UINT64_C(2096627712), UINT64_C(0),	// V_CMPSX_NLE_F64_e32_gfx6_gfx7
    UINT64_C(3505913856), UINT64_C(0),	// V_CMPSX_NLE_F64_e64_gfx6_gfx7
    UINT64_C(2092171264), UINT64_C(0),	// V_CMPSX_NLG_F32_e32_gfx6_gfx7
    UINT64_C(3501457408), UINT64_C(0),	// V_CMPSX_NLG_F32_e64_gfx6_gfx7
    UINT64_C(2096365568), UINT64_C(0),	// V_CMPSX_NLG_F64_e32_gfx6_gfx7
    UINT64_C(3505651712), UINT64_C(0),	// V_CMPSX_NLG_F64_e64_gfx6_gfx7
    UINT64_C(2092695552), UINT64_C(0),	// V_CMPSX_NLT_F32_e32_gfx6_gfx7
    UINT64_C(3501981696), UINT64_C(0),	// V_CMPSX_NLT_F32_e64_gfx6_gfx7
    UINT64_C(2096889856), UINT64_C(0),	// V_CMPSX_NLT_F64_e32_gfx6_gfx7
    UINT64_C(3506176000), UINT64_C(0),	// V_CMPSX_NLT_F64_e64_gfx6_gfx7
    UINT64_C(2091778048), UINT64_C(0),	// V_CMPSX_O_F32_e32_gfx6_gfx7
    UINT64_C(3501064192), UINT64_C(0),	// V_CMPSX_O_F32_e64_gfx6_gfx7
    UINT64_C(2095972352), UINT64_C(0),	// V_CMPSX_O_F64_e32_gfx6_gfx7
    UINT64_C(3505258496), UINT64_C(0),	// V_CMPSX_O_F64_e64_gfx6_gfx7
    UINT64_C(2092826624), UINT64_C(0),	// V_CMPSX_TRU_F32_e32_gfx6_gfx7
    UINT64_C(3502112768), UINT64_C(0),	// V_CMPSX_TRU_F32_e64_gfx6_gfx7
    UINT64_C(2097020928), UINT64_C(0),	// V_CMPSX_TRU_F64_e32_gfx6_gfx7
    UINT64_C(3506307072), UINT64_C(0),	// V_CMPSX_TRU_F64_e64_gfx6_gfx7
    UINT64_C(2091909120), UINT64_C(0),	// V_CMPSX_U_F32_e32_gfx6_gfx7
    UINT64_C(3501195264), UINT64_C(0),	// V_CMPSX_U_F32_e64_gfx6_gfx7
    UINT64_C(2096103424), UINT64_C(0),	// V_CMPSX_U_F64_e32_gfx6_gfx7
    UINT64_C(3505389568), UINT64_C(0),	// V_CMPSX_U_F64_e64_gfx6_gfx7
    UINT64_C(2089025536), UINT64_C(0),	// V_CMPS_EQ_F32_e32_gfx6_gfx7
    UINT64_C(3498311680), UINT64_C(0),	// V_CMPS_EQ_F32_e64_gfx6_gfx7
    UINT64_C(2093219840), UINT64_C(0),	// V_CMPS_EQ_F64_e32_gfx6_gfx7
    UINT64_C(3502505984), UINT64_C(0),	// V_CMPS_EQ_F64_e64_gfx6_gfx7
    UINT64_C(2088763392), UINT64_C(0),	// V_CMPS_F_F32_e32_gfx6_gfx7
    UINT64_C(3498049536), UINT64_C(0),	// V_CMPS_F_F32_e64_gfx6_gfx7
    UINT64_C(2092957696), UINT64_C(0),	// V_CMPS_F_F64_e32_gfx6_gfx7
    UINT64_C(3502243840), UINT64_C(0),	// V_CMPS_F_F64_e64_gfx6_gfx7
    UINT64_C(2089549824), UINT64_C(0),	// V_CMPS_GE_F32_e32_gfx6_gfx7
    UINT64_C(3498835968), UINT64_C(0),	// V_CMPS_GE_F32_e64_gfx6_gfx7
    UINT64_C(2093744128), UINT64_C(0),	// V_CMPS_GE_F64_e32_gfx6_gfx7
    UINT64_C(3503030272), UINT64_C(0),	// V_CMPS_GE_F64_e64_gfx6_gfx7
    UINT64_C(2089287680), UINT64_C(0),	// V_CMPS_GT_F32_e32_gfx6_gfx7
    UINT64_C(3498573824), UINT64_C(0),	// V_CMPS_GT_F32_e64_gfx6_gfx7
    UINT64_C(2093481984), UINT64_C(0),	// V_CMPS_GT_F64_e32_gfx6_gfx7
    UINT64_C(3502768128), UINT64_C(0),	// V_CMPS_GT_F64_e64_gfx6_gfx7
    UINT64_C(2089156608), UINT64_C(0),	// V_CMPS_LE_F32_e32_gfx6_gfx7
    UINT64_C(3498442752), UINT64_C(0),	// V_CMPS_LE_F32_e64_gfx6_gfx7
    UINT64_C(2093350912), UINT64_C(0),	// V_CMPS_LE_F64_e32_gfx6_gfx7
    UINT64_C(3502637056), UINT64_C(0),	// V_CMPS_LE_F64_e64_gfx6_gfx7
    UINT64_C(2089418752), UINT64_C(0),	// V_CMPS_LG_F32_e32_gfx6_gfx7
    UINT64_C(3498704896), UINT64_C(0),	// V_CMPS_LG_F32_e64_gfx6_gfx7
    UINT64_C(2093613056), UINT64_C(0),	// V_CMPS_LG_F64_e32_gfx6_gfx7
    UINT64_C(3502899200), UINT64_C(0),	// V_CMPS_LG_F64_e64_gfx6_gfx7
    UINT64_C(2088894464), UINT64_C(0),	// V_CMPS_LT_F32_e32_gfx6_gfx7
    UINT64_C(3498180608), UINT64_C(0),	// V_CMPS_LT_F32_e64_gfx6_gfx7
    UINT64_C(2093088768), UINT64_C(0),	// V_CMPS_LT_F64_e32_gfx6_gfx7
    UINT64_C(3502374912), UINT64_C(0),	// V_CMPS_LT_F64_e64_gfx6_gfx7
    UINT64_C(2090467328), UINT64_C(0),	// V_CMPS_NEQ_F32_e32_gfx6_gfx7
    UINT64_C(3499753472), UINT64_C(0),	// V_CMPS_NEQ_F32_e64_gfx6_gfx7
    UINT64_C(2094661632), UINT64_C(0),	// V_CMPS_NEQ_F64_e32_gfx6_gfx7
    UINT64_C(3503947776), UINT64_C(0),	// V_CMPS_NEQ_F64_e64_gfx6_gfx7
    UINT64_C(2089943040), UINT64_C(0),	// V_CMPS_NGE_F32_e32_gfx6_gfx7
    UINT64_C(3499229184), UINT64_C(0),	// V_CMPS_NGE_F32_e64_gfx6_gfx7
    UINT64_C(2094137344), UINT64_C(0),	// V_CMPS_NGE_F64_e32_gfx6_gfx7
    UINT64_C(3503423488), UINT64_C(0),	// V_CMPS_NGE_F64_e64_gfx6_gfx7
    UINT64_C(2090205184), UINT64_C(0),	// V_CMPS_NGT_F32_e32_gfx6_gfx7
    UINT64_C(3499491328), UINT64_C(0),	// V_CMPS_NGT_F32_e64_gfx6_gfx7
    UINT64_C(2094399488), UINT64_C(0),	// V_CMPS_NGT_F64_e32_gfx6_gfx7
    UINT64_C(3503685632), UINT64_C(0),	// V_CMPS_NGT_F64_e64_gfx6_gfx7
    UINT64_C(2090336256), UINT64_C(0),	// V_CMPS_NLE_F32_e32_gfx6_gfx7
    UINT64_C(3499622400), UINT64_C(0),	// V_CMPS_NLE_F32_e64_gfx6_gfx7
    UINT64_C(2094530560), UINT64_C(0),	// V_CMPS_NLE_F64_e32_gfx6_gfx7
    UINT64_C(3503816704), UINT64_C(0),	// V_CMPS_NLE_F64_e64_gfx6_gfx7
    UINT64_C(2090074112), UINT64_C(0),	// V_CMPS_NLG_F32_e32_gfx6_gfx7
    UINT64_C(3499360256), UINT64_C(0),	// V_CMPS_NLG_F32_e64_gfx6_gfx7
    UINT64_C(2094268416), UINT64_C(0),	// V_CMPS_NLG_F64_e32_gfx6_gfx7
    UINT64_C(3503554560), UINT64_C(0),	// V_CMPS_NLG_F64_e64_gfx6_gfx7
    UINT64_C(2090598400), UINT64_C(0),	// V_CMPS_NLT_F32_e32_gfx6_gfx7
    UINT64_C(3499884544), UINT64_C(0),	// V_CMPS_NLT_F32_e64_gfx6_gfx7
    UINT64_C(2094792704), UINT64_C(0),	// V_CMPS_NLT_F64_e32_gfx6_gfx7
    UINT64_C(3504078848), UINT64_C(0),	// V_CMPS_NLT_F64_e64_gfx6_gfx7
    UINT64_C(2089680896), UINT64_C(0),	// V_CMPS_O_F32_e32_gfx6_gfx7
    UINT64_C(3498967040), UINT64_C(0),	// V_CMPS_O_F32_e64_gfx6_gfx7
    UINT64_C(2093875200), UINT64_C(0),	// V_CMPS_O_F64_e32_gfx6_gfx7
    UINT64_C(3503161344), UINT64_C(0),	// V_CMPS_O_F64_e64_gfx6_gfx7
    UINT64_C(2090729472), UINT64_C(0),	// V_CMPS_TRU_F32_e32_gfx6_gfx7
    UINT64_C(3500015616), UINT64_C(0),	// V_CMPS_TRU_F32_e64_gfx6_gfx7
    UINT64_C(2094923776), UINT64_C(0),	// V_CMPS_TRU_F64_e32_gfx6_gfx7
    UINT64_C(3504209920), UINT64_C(0),	// V_CMPS_TRU_F64_e64_gfx6_gfx7
    UINT64_C(2089811968), UINT64_C(0),	// V_CMPS_U_F32_e32_gfx6_gfx7
    UINT64_C(3499098112), UINT64_C(0),	// V_CMPS_U_F32_e64_gfx6_gfx7
    UINT64_C(2094006272), UINT64_C(0),	// V_CMPS_U_F64_e32_gfx6_gfx7
    UINT64_C(3503292416), UINT64_C(0),	// V_CMPS_U_F64_e64_gfx6_gfx7
    UINT64_C(2101215232), UINT64_C(0),	// V_CMPX_CLASS_F16_e32_gfx10
    UINT64_C(2083127296), UINT64_C(0),	// V_CMPX_CLASS_F16_e32_vi
    UINT64_C(3567190016), UINT64_C(0),	// V_CMPX_CLASS_F16_e64_gfx10
    UINT64_C(3491037184), UINT64_C(0),	// V_CMPX_CLASS_F16_e64_vi
    UINT64_C(2113536000), UINT64_C(0),	// V_CMPX_CLASS_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2113536000), UINT64_C(0),	// V_CMPX_CLASS_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2113536250), UINT64_C(0),	// V_CMPX_CLASS_F16_fake16_e32_dpp_gfx11
    UINT64_C(2113536250), UINT64_C(0),	// V_CMPX_CLASS_F16_fake16_e32_dpp_gfx12
    UINT64_C(2113536000), UINT64_C(0),	// V_CMPX_CLASS_F16_fake16_e32_gfx11
    UINT64_C(2113536000), UINT64_C(0),	// V_CMPX_CLASS_F16_fake16_e32_gfx12
    UINT64_C(3573350400), UINT64_C(0),	// V_CMPX_CLASS_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3573350400), UINT64_C(0),	// V_CMPX_CLASS_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077315174400), UINT64_C(0),	// V_CMPX_CLASS_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077315174400), UINT64_C(0),	// V_CMPX_CLASS_F16_fake16_e64_dpp_gfx12
    UINT64_C(3573350400), UINT64_C(0),	// V_CMPX_CLASS_F16_fake16_e64_gfx11
    UINT64_C(3573350400), UINT64_C(0),	// V_CMPX_CLASS_F16_fake16_e64_gfx12
    UINT64_C(2101215481), UINT64_C(0),	// V_CMPX_CLASS_F16_sdwa_gfx10
    UINT64_C(2083127545), UINT64_C(0),	// V_CMPX_CLASS_F16_sdwa_gfx9
    UINT64_C(2083127545), UINT64_C(0),	// V_CMPX_CLASS_F16_sdwa_vi
    UINT64_C(2113536000), UINT64_C(0),	// V_CMPX_CLASS_F16_t16_e32_dpp8_gfx11
    UINT64_C(2113536000), UINT64_C(0),	// V_CMPX_CLASS_F16_t16_e32_dpp8_gfx12
    UINT64_C(2113536250), UINT64_C(0),	// V_CMPX_CLASS_F16_t16_e32_dpp_gfx11
    UINT64_C(2113536250), UINT64_C(0),	// V_CMPX_CLASS_F16_t16_e32_dpp_gfx12
    UINT64_C(2113536000), UINT64_C(0),	// V_CMPX_CLASS_F16_t16_e32_gfx11
    UINT64_C(2113536000), UINT64_C(0),	// V_CMPX_CLASS_F16_t16_e32_gfx12
    UINT64_C(3573350400), UINT64_C(0),	// V_CMPX_CLASS_F16_t16_e64_dpp8_gfx11
    UINT64_C(3573350400), UINT64_C(0),	// V_CMPX_CLASS_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077315174400), UINT64_C(0),	// V_CMPX_CLASS_F16_t16_e64_dpp_gfx11
    UINT64_C(1077315174400), UINT64_C(0),	// V_CMPX_CLASS_F16_t16_e64_dpp_gfx12
    UINT64_C(3573350400), UINT64_C(0),	// V_CMPX_CLASS_F16_t16_e64_gfx11
    UINT64_C(3573350400), UINT64_C(0),	// V_CMPX_CLASS_F16_t16_e64_gfx12
    UINT64_C(2113667072), UINT64_C(0),	// V_CMPX_CLASS_F32_e32_dpp8_gfx11
    UINT64_C(2113667072), UINT64_C(0),	// V_CMPX_CLASS_F32_e32_dpp8_gfx12
    UINT64_C(2113667322), UINT64_C(0),	// V_CMPX_CLASS_F32_e32_dpp_gfx11
    UINT64_C(2113667322), UINT64_C(0),	// V_CMPX_CLASS_F32_e32_dpp_gfx12
    UINT64_C(2100297728), UINT64_C(0),	// V_CMPX_CLASS_F32_e32_gfx10
    UINT64_C(2113667072), UINT64_C(0),	// V_CMPX_CLASS_F32_e32_gfx11
    UINT64_C(2113667072), UINT64_C(0),	// V_CMPX_CLASS_F32_e32_gfx12
    UINT64_C(2100297728), UINT64_C(0),	// V_CMPX_CLASS_F32_e32_gfx6_gfx7
    UINT64_C(2082603008), UINT64_C(0),	// V_CMPX_CLASS_F32_e32_vi
    UINT64_C(3573415936), UINT64_C(0),	// V_CMPX_CLASS_F32_e64_dpp8_gfx11
    UINT64_C(3573415936), UINT64_C(0),	// V_CMPX_CLASS_F32_e64_dpp8_gfx12
    UINT64_C(1077315239936), UINT64_C(0),	// V_CMPX_CLASS_F32_e64_dpp_gfx11
    UINT64_C(1077315239936), UINT64_C(0),	// V_CMPX_CLASS_F32_e64_dpp_gfx12
    UINT64_C(3566731264), UINT64_C(0),	// V_CMPX_CLASS_F32_e64_gfx10
    UINT64_C(3573415936), UINT64_C(0),	// V_CMPX_CLASS_F32_e64_gfx11
    UINT64_C(3573415936), UINT64_C(0),	// V_CMPX_CLASS_F32_e64_gfx12
    UINT64_C(3509583872), UINT64_C(0),	// V_CMPX_CLASS_F32_e64_gfx6_gfx7
    UINT64_C(3490775040), UINT64_C(0),	// V_CMPX_CLASS_F32_e64_vi
    UINT64_C(2100297977), UINT64_C(0),	// V_CMPX_CLASS_F32_sdwa_gfx10
    UINT64_C(2082603257), UINT64_C(0),	// V_CMPX_CLASS_F32_sdwa_gfx9
    UINT64_C(2082603257), UINT64_C(0),	// V_CMPX_CLASS_F32_sdwa_vi
    UINT64_C(2104492032), UINT64_C(0),	// V_CMPX_CLASS_F64_e32_gfx10
    UINT64_C(2113798144), UINT64_C(0),	// V_CMPX_CLASS_F64_e32_gfx11
    UINT64_C(2113798144), UINT64_C(0),	// V_CMPX_CLASS_F64_e32_gfx12
    UINT64_C(2104492032), UINT64_C(0),	// V_CMPX_CLASS_F64_e32_gfx6_gfx7
    UINT64_C(2082865152), UINT64_C(0),	// V_CMPX_CLASS_F64_e32_vi
    UINT64_C(3568828416), UINT64_C(0),	// V_CMPX_CLASS_F64_e64_gfx10
    UINT64_C(3573481472), UINT64_C(0),	// V_CMPX_CLASS_F64_e64_gfx11
    UINT64_C(3573481472), UINT64_C(0),	// V_CMPX_CLASS_F64_e64_gfx12
    UINT64_C(3513778176), UINT64_C(0),	// V_CMPX_CLASS_F64_e64_gfx6_gfx7
    UINT64_C(3490906112), UINT64_C(0),	// V_CMPX_CLASS_F64_e64_vi
    UINT64_C(2108948480), UINT64_C(0),	// V_CMPX_EQ_F16_e32_gfx10
    UINT64_C(2086928384), UINT64_C(0),	// V_CMPX_EQ_F16_e32_vi
    UINT64_C(3571056640), UINT64_C(0),	// V_CMPX_EQ_F16_e64_gfx10
    UINT64_C(3492937728), UINT64_C(0),	// V_CMPX_EQ_F16_e64_vi
    UINT64_C(2097414144), UINT64_C(0),	// V_CMPX_EQ_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2097414144), UINT64_C(0),	// V_CMPX_EQ_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2097414394), UINT64_C(0),	// V_CMPX_EQ_F16_fake16_e32_dpp_gfx11
    UINT64_C(2097414394), UINT64_C(0),	// V_CMPX_EQ_F16_fake16_e32_dpp_gfx12
    UINT64_C(2097414144), UINT64_C(0),	// V_CMPX_EQ_F16_fake16_e32_gfx11
    UINT64_C(2097414144), UINT64_C(0),	// V_CMPX_EQ_F16_fake16_e32_gfx12
    UINT64_C(3565289472), UINT64_C(0),	// V_CMPX_EQ_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3565289472), UINT64_C(0),	// V_CMPX_EQ_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077307113472), UINT64_C(0),	// V_CMPX_EQ_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077307113472), UINT64_C(0),	// V_CMPX_EQ_F16_fake16_e64_dpp_gfx12
    UINT64_C(3565289472), UINT64_C(0),	// V_CMPX_EQ_F16_fake16_e64_gfx11
    UINT64_C(3565289472), UINT64_C(0),	// V_CMPX_EQ_F16_fake16_e64_gfx12
    UINT64_C(2108948729), UINT64_C(0),	// V_CMPX_EQ_F16_sdwa_gfx10
    UINT64_C(2086928633), UINT64_C(0),	// V_CMPX_EQ_F16_sdwa_gfx9
    UINT64_C(2086928633), UINT64_C(0),	// V_CMPX_EQ_F16_sdwa_vi
    UINT64_C(2097414144), UINT64_C(0),	// V_CMPX_EQ_F16_t16_e32_dpp8_gfx11
    UINT64_C(2097414144), UINT64_C(0),	// V_CMPX_EQ_F16_t16_e32_dpp8_gfx12
    UINT64_C(2097414394), UINT64_C(0),	// V_CMPX_EQ_F16_t16_e32_dpp_gfx11
    UINT64_C(2097414394), UINT64_C(0),	// V_CMPX_EQ_F16_t16_e32_dpp_gfx12
    UINT64_C(2097414144), UINT64_C(0),	// V_CMPX_EQ_F16_t16_e32_gfx11
    UINT64_C(2097414144), UINT64_C(0),	// V_CMPX_EQ_F16_t16_e32_gfx12
    UINT64_C(3565289472), UINT64_C(0),	// V_CMPX_EQ_F16_t16_e64_dpp8_gfx11
    UINT64_C(3565289472), UINT64_C(0),	// V_CMPX_EQ_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077307113472), UINT64_C(0),	// V_CMPX_EQ_F16_t16_e64_dpp_gfx11
    UINT64_C(1077307113472), UINT64_C(0),	// V_CMPX_EQ_F16_t16_e64_dpp_gfx12
    UINT64_C(3565289472), UINT64_C(0),	// V_CMPX_EQ_F16_t16_e64_gfx11
    UINT64_C(3565289472), UINT64_C(0),	// V_CMPX_EQ_F16_t16_e64_gfx12
    UINT64_C(2099511296), UINT64_C(0),	// V_CMPX_EQ_F32_e32_dpp8_gfx11
    UINT64_C(2099511296), UINT64_C(0),	// V_CMPX_EQ_F32_e32_dpp8_gfx12
    UINT64_C(2099511546), UINT64_C(0),	// V_CMPX_EQ_F32_e32_dpp_gfx11
    UINT64_C(2099511546), UINT64_C(0),	// V_CMPX_EQ_F32_e32_dpp_gfx12
    UINT64_C(2082734080), UINT64_C(0),	// V_CMPX_EQ_F32_e32_gfx10
    UINT64_C(2099511296), UINT64_C(0),	// V_CMPX_EQ_F32_e32_gfx11
    UINT64_C(2099511296), UINT64_C(0),	// V_CMPX_EQ_F32_e32_gfx12
    UINT64_C(2082734080), UINT64_C(0),	// V_CMPX_EQ_F32_e32_gfx6_gfx7
    UINT64_C(2091122688), UINT64_C(0),	// V_CMPX_EQ_F32_e32_vi
    UINT64_C(3566338048), UINT64_C(0),	// V_CMPX_EQ_F32_e64_dpp8_gfx11
    UINT64_C(3566338048), UINT64_C(0),	// V_CMPX_EQ_F32_e64_dpp8_gfx12
    UINT64_C(1077308162048), UINT64_C(0),	// V_CMPX_EQ_F32_e64_dpp_gfx11
    UINT64_C(1077308162048), UINT64_C(0),	// V_CMPX_EQ_F32_e64_dpp_gfx12
    UINT64_C(3557949440), UINT64_C(0),	// V_CMPX_EQ_F32_e64_gfx10
    UINT64_C(3566338048), UINT64_C(0),	// V_CMPX_EQ_F32_e64_gfx11
    UINT64_C(3566338048), UINT64_C(0),	// V_CMPX_EQ_F32_e64_gfx12
    UINT64_C(3492020224), UINT64_C(0),	// V_CMPX_EQ_F32_e64_gfx6_gfx7
    UINT64_C(3495034880), UINT64_C(0),	// V_CMPX_EQ_F32_e64_vi
    UINT64_C(2082734329), UINT64_C(0),	// V_CMPX_EQ_F32_sdwa_gfx10
    UINT64_C(2091122937), UINT64_C(0),	// V_CMPX_EQ_F32_sdwa_gfx9
    UINT64_C(2091122937), UINT64_C(0),	// V_CMPX_EQ_F32_sdwa_vi
    UINT64_C(2086928384), UINT64_C(0),	// V_CMPX_EQ_F64_e32_gfx10
    UINT64_C(2101608448), UINT64_C(0),	// V_CMPX_EQ_F64_e32_gfx11
    UINT64_C(2101608448), UINT64_C(0),	// V_CMPX_EQ_F64_e32_gfx12
    UINT64_C(2086928384), UINT64_C(0),	// V_CMPX_EQ_F64_e32_gfx6_gfx7
    UINT64_C(2095316992), UINT64_C(0),	// V_CMPX_EQ_F64_e32_vi
    UINT64_C(3560046592), UINT64_C(0),	// V_CMPX_EQ_F64_e64_gfx10
    UINT64_C(3567386624), UINT64_C(0),	// V_CMPX_EQ_F64_e64_gfx11
    UINT64_C(3567386624), UINT64_C(0),	// V_CMPX_EQ_F64_e64_gfx12
    UINT64_C(3496214528), UINT64_C(0),	// V_CMPX_EQ_F64_e64_gfx6_gfx7
    UINT64_C(3497132032), UINT64_C(0),	// V_CMPX_EQ_F64_e64_vi
    UINT64_C(2100559872), UINT64_C(0),	// V_CMPX_EQ_I16_e32_gfx10
    UINT64_C(2103705600), UINT64_C(0),	// V_CMPX_EQ_I16_e32_vi
    UINT64_C(3566862336), UINT64_C(0),	// V_CMPX_EQ_I16_e64_gfx10
    UINT64_C(3501326336), UINT64_C(0),	// V_CMPX_EQ_I16_e64_vi
    UINT64_C(2103705600), UINT64_C(0),	// V_CMPX_EQ_I16_fake16_e32_dpp8_gfx11
    UINT64_C(2103705600), UINT64_C(0),	// V_CMPX_EQ_I16_fake16_e32_dpp8_gfx12
    UINT64_C(2103705850), UINT64_C(0),	// V_CMPX_EQ_I16_fake16_e32_dpp_gfx11
    UINT64_C(2103705850), UINT64_C(0),	// V_CMPX_EQ_I16_fake16_e32_dpp_gfx12
    UINT64_C(2103705600), UINT64_C(0),	// V_CMPX_EQ_I16_fake16_e32_gfx11
    UINT64_C(2103705600), UINT64_C(0),	// V_CMPX_EQ_I16_fake16_e32_gfx12
    UINT64_C(3568435200), UINT64_C(0),	// V_CMPX_EQ_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3568435200), UINT64_C(0),	// V_CMPX_EQ_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077310259200), UINT64_C(0),	// V_CMPX_EQ_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077310259200), UINT64_C(0),	// V_CMPX_EQ_I16_fake16_e64_dpp_gfx12
    UINT64_C(3568435200), UINT64_C(0),	// V_CMPX_EQ_I16_fake16_e64_gfx11
    UINT64_C(3568435200), UINT64_C(0),	// V_CMPX_EQ_I16_fake16_e64_gfx12
    UINT64_C(2100560121), UINT64_C(0),	// V_CMPX_EQ_I16_sdwa_gfx10
    UINT64_C(2103705849), UINT64_C(0),	// V_CMPX_EQ_I16_sdwa_gfx9
    UINT64_C(2103705849), UINT64_C(0),	// V_CMPX_EQ_I16_sdwa_vi
    UINT64_C(2103705600), UINT64_C(0),	// V_CMPX_EQ_I16_t16_e32_dpp8_gfx11
    UINT64_C(2103705600), UINT64_C(0),	// V_CMPX_EQ_I16_t16_e32_dpp8_gfx12
    UINT64_C(2103705850), UINT64_C(0),	// V_CMPX_EQ_I16_t16_e32_dpp_gfx11
    UINT64_C(2103705850), UINT64_C(0),	// V_CMPX_EQ_I16_t16_e32_dpp_gfx12
    UINT64_C(2103705600), UINT64_C(0),	// V_CMPX_EQ_I16_t16_e32_gfx11
    UINT64_C(2103705600), UINT64_C(0),	// V_CMPX_EQ_I16_t16_e32_gfx12
    UINT64_C(3568435200), UINT64_C(0),	// V_CMPX_EQ_I16_t16_e64_dpp8_gfx11
    UINT64_C(3568435200), UINT64_C(0),	// V_CMPX_EQ_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077310259200), UINT64_C(0),	// V_CMPX_EQ_I16_t16_e64_dpp_gfx11
    UINT64_C(1077310259200), UINT64_C(0),	// V_CMPX_EQ_I16_t16_e64_dpp_gfx12
    UINT64_C(3568435200), UINT64_C(0),	// V_CMPX_EQ_I16_t16_e64_gfx11
    UINT64_C(3568435200), UINT64_C(0),	// V_CMPX_EQ_I16_t16_e64_gfx12
    UINT64_C(2105802752), UINT64_C(0),	// V_CMPX_EQ_I32_e32_dpp8_gfx11
    UINT64_C(2105802752), UINT64_C(0),	// V_CMPX_EQ_I32_e32_dpp8_gfx12
    UINT64_C(2105803002), UINT64_C(0),	// V_CMPX_EQ_I32_e32_dpp_gfx11
    UINT64_C(2105803002), UINT64_C(0),	// V_CMPX_EQ_I32_e32_dpp_gfx12
    UINT64_C(2099511296), UINT64_C(0),	// V_CMPX_EQ_I32_e32_gfx10
    UINT64_C(2105802752), UINT64_C(0),	// V_CMPX_EQ_I32_e32_gfx11
    UINT64_C(2105802752), UINT64_C(0),	// V_CMPX_EQ_I32_e32_gfx12
    UINT64_C(2099511296), UINT64_C(0),	// V_CMPX_EQ_I32_e32_gfx6_gfx7
    UINT64_C(2107899904), UINT64_C(0),	// V_CMPX_EQ_I32_e32_vi
    UINT64_C(3569483776), UINT64_C(0),	// V_CMPX_EQ_I32_e64_dpp8_gfx11
    UINT64_C(3569483776), UINT64_C(0),	// V_CMPX_EQ_I32_e64_dpp8_gfx12
    UINT64_C(1077311307776), UINT64_C(0),	// V_CMPX_EQ_I32_e64_dpp_gfx11
    UINT64_C(1077311307776), UINT64_C(0),	// V_CMPX_EQ_I32_e64_dpp_gfx12
    UINT64_C(3566338048), UINT64_C(0),	// V_CMPX_EQ_I32_e64_gfx10
    UINT64_C(3569483776), UINT64_C(0),	// V_CMPX_EQ_I32_e64_gfx11
    UINT64_C(3569483776), UINT64_C(0),	// V_CMPX_EQ_I32_e64_gfx12
    UINT64_C(3508797440), UINT64_C(0),	// V_CMPX_EQ_I32_e64_gfx6_gfx7
    UINT64_C(3503423488), UINT64_C(0),	// V_CMPX_EQ_I32_e64_vi
    UINT64_C(2099511545), UINT64_C(0),	// V_CMPX_EQ_I32_sdwa_gfx10
    UINT64_C(2107900153), UINT64_C(0),	// V_CMPX_EQ_I32_sdwa_gfx9
    UINT64_C(2107900153), UINT64_C(0),	// V_CMPX_EQ_I32_sdwa_vi
    UINT64_C(2103705600), UINT64_C(0),	// V_CMPX_EQ_I64_e32_gfx10
    UINT64_C(2107899904), UINT64_C(0),	// V_CMPX_EQ_I64_e32_gfx11
    UINT64_C(2107899904), UINT64_C(0),	// V_CMPX_EQ_I64_e32_gfx12
    UINT64_C(2103705600), UINT64_C(0),	// V_CMPX_EQ_I64_e32_gfx6_gfx7
    UINT64_C(2112094208), UINT64_C(0),	// V_CMPX_EQ_I64_e32_vi
    UINT64_C(3568435200), UINT64_C(0),	// V_CMPX_EQ_I64_e64_gfx10
    UINT64_C(3570532352), UINT64_C(0),	// V_CMPX_EQ_I64_e64_gfx11
    UINT64_C(3570532352), UINT64_C(0),	// V_CMPX_EQ_I64_e64_gfx12
    UINT64_C(3512991744), UINT64_C(0),	// V_CMPX_EQ_I64_e64_gfx6_gfx7
    UINT64_C(3505520640), UINT64_C(0),	// V_CMPX_EQ_I64_e64_vi
    UINT64_C(2104754176), UINT64_C(0),	// V_CMPX_EQ_U16_e32_gfx10
    UINT64_C(2104754176), UINT64_C(0),	// V_CMPX_EQ_U16_e32_vi
    UINT64_C(3568959488), UINT64_C(0),	// V_CMPX_EQ_U16_e64_gfx10
    UINT64_C(3501850624), UINT64_C(0),	// V_CMPX_EQ_U16_e64_vi
    UINT64_C(2104754176), UINT64_C(0),	// V_CMPX_EQ_U16_fake16_e32_dpp8_gfx11
    UINT64_C(2104754176), UINT64_C(0),	// V_CMPX_EQ_U16_fake16_e32_dpp8_gfx12
    UINT64_C(2104754426), UINT64_C(0),	// V_CMPX_EQ_U16_fake16_e32_dpp_gfx11
    UINT64_C(2104754426), UINT64_C(0),	// V_CMPX_EQ_U16_fake16_e32_dpp_gfx12
    UINT64_C(2104754176), UINT64_C(0),	// V_CMPX_EQ_U16_fake16_e32_gfx11
    UINT64_C(2104754176), UINT64_C(0),	// V_CMPX_EQ_U16_fake16_e32_gfx12
    UINT64_C(3568959488), UINT64_C(0),	// V_CMPX_EQ_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3568959488), UINT64_C(0),	// V_CMPX_EQ_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077310783488), UINT64_C(0),	// V_CMPX_EQ_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077310783488), UINT64_C(0),	// V_CMPX_EQ_U16_fake16_e64_dpp_gfx12
    UINT64_C(3568959488), UINT64_C(0),	// V_CMPX_EQ_U16_fake16_e64_gfx11
    UINT64_C(3568959488), UINT64_C(0),	// V_CMPX_EQ_U16_fake16_e64_gfx12
    UINT64_C(2104754425), UINT64_C(0),	// V_CMPX_EQ_U16_sdwa_gfx10
    UINT64_C(2104754425), UINT64_C(0),	// V_CMPX_EQ_U16_sdwa_gfx9
    UINT64_C(2104754425), UINT64_C(0),	// V_CMPX_EQ_U16_sdwa_vi
    UINT64_C(2104754176), UINT64_C(0),	// V_CMPX_EQ_U16_t16_e32_dpp8_gfx11
    UINT64_C(2104754176), UINT64_C(0),	// V_CMPX_EQ_U16_t16_e32_dpp8_gfx12
    UINT64_C(2104754426), UINT64_C(0),	// V_CMPX_EQ_U16_t16_e32_dpp_gfx11
    UINT64_C(2104754426), UINT64_C(0),	// V_CMPX_EQ_U16_t16_e32_dpp_gfx12
    UINT64_C(2104754176), UINT64_C(0),	// V_CMPX_EQ_U16_t16_e32_gfx11
    UINT64_C(2104754176), UINT64_C(0),	// V_CMPX_EQ_U16_t16_e32_gfx12
    UINT64_C(3568959488), UINT64_C(0),	// V_CMPX_EQ_U16_t16_e64_dpp8_gfx11
    UINT64_C(3568959488), UINT64_C(0),	// V_CMPX_EQ_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077310783488), UINT64_C(0),	// V_CMPX_EQ_U16_t16_e64_dpp_gfx11
    UINT64_C(1077310783488), UINT64_C(0),	// V_CMPX_EQ_U16_t16_e64_dpp_gfx12
    UINT64_C(3568959488), UINT64_C(0),	// V_CMPX_EQ_U16_t16_e64_gfx11
    UINT64_C(3568959488), UINT64_C(0),	// V_CMPX_EQ_U16_t16_e64_gfx12
    UINT64_C(2106851328), UINT64_C(0),	// V_CMPX_EQ_U32_e32_dpp8_gfx11
    UINT64_C(2106851328), UINT64_C(0),	// V_CMPX_EQ_U32_e32_dpp8_gfx12
    UINT64_C(2106851578), UINT64_C(0),	// V_CMPX_EQ_U32_e32_dpp_gfx11
    UINT64_C(2106851578), UINT64_C(0),	// V_CMPX_EQ_U32_e32_dpp_gfx12
    UINT64_C(2107899904), UINT64_C(0),	// V_CMPX_EQ_U32_e32_gfx10
    UINT64_C(2106851328), UINT64_C(0),	// V_CMPX_EQ_U32_e32_gfx11
    UINT64_C(2106851328), UINT64_C(0),	// V_CMPX_EQ_U32_e32_gfx12
    UINT64_C(2107899904), UINT64_C(0),	// V_CMPX_EQ_U32_e32_gfx6_gfx7
    UINT64_C(2108948480), UINT64_C(0),	// V_CMPX_EQ_U32_e32_vi
    UINT64_C(3570008064), UINT64_C(0),	// V_CMPX_EQ_U32_e64_dpp8_gfx11
    UINT64_C(3570008064), UINT64_C(0),	// V_CMPX_EQ_U32_e64_dpp8_gfx12
    UINT64_C(1077311832064), UINT64_C(0),	// V_CMPX_EQ_U32_e64_dpp_gfx11
    UINT64_C(1077311832064), UINT64_C(0),	// V_CMPX_EQ_U32_e64_dpp_gfx12
    UINT64_C(3570532352), UINT64_C(0),	// V_CMPX_EQ_U32_e64_gfx10
    UINT64_C(3570008064), UINT64_C(0),	// V_CMPX_EQ_U32_e64_gfx11
    UINT64_C(3570008064), UINT64_C(0),	// V_CMPX_EQ_U32_e64_gfx12
    UINT64_C(3517186048), UINT64_C(0),	// V_CMPX_EQ_U32_e64_gfx6_gfx7
    UINT64_C(3503947776), UINT64_C(0),	// V_CMPX_EQ_U32_e64_vi
    UINT64_C(2107900153), UINT64_C(0),	// V_CMPX_EQ_U32_sdwa_gfx10
    UINT64_C(2108948729), UINT64_C(0),	// V_CMPX_EQ_U32_sdwa_gfx9
    UINT64_C(2108948729), UINT64_C(0),	// V_CMPX_EQ_U32_sdwa_vi
    UINT64_C(2112094208), UINT64_C(0),	// V_CMPX_EQ_U64_e32_gfx10
    UINT64_C(2108948480), UINT64_C(0),	// V_CMPX_EQ_U64_e32_gfx11
    UINT64_C(2108948480), UINT64_C(0),	// V_CMPX_EQ_U64_e32_gfx12
    UINT64_C(2112094208), UINT64_C(0),	// V_CMPX_EQ_U64_e32_gfx6_gfx7
    UINT64_C(2113142784), UINT64_C(0),	// V_CMPX_EQ_U64_e32_vi
    UINT64_C(3572629504), UINT64_C(0),	// V_CMPX_EQ_U64_e64_gfx10
    UINT64_C(3571056640), UINT64_C(0),	// V_CMPX_EQ_U64_e64_gfx11
    UINT64_C(3571056640), UINT64_C(0),	// V_CMPX_EQ_U64_e64_gfx12
    UINT64_C(3521380352), UINT64_C(0),	// V_CMPX_EQ_U64_e64_gfx6_gfx7
    UINT64_C(3506044928), UINT64_C(0),	// V_CMPX_EQ_U64_e64_vi
    UINT64_C(2108686336), UINT64_C(0),	// V_CMPX_F_F16_e32_gfx10
    UINT64_C(2086666240), UINT64_C(0),	// V_CMPX_F_F16_e32_vi
    UINT64_C(3570925568), UINT64_C(0),	// V_CMPX_F_F16_e64_gfx10
    UINT64_C(3492806656), UINT64_C(0),	// V_CMPX_F_F16_e64_vi
    UINT64_C(2097152000), UINT64_C(0),	// V_CMPX_F_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2097152250), UINT64_C(0),	// V_CMPX_F_F16_fake16_e32_dpp_gfx11
    UINT64_C(2097152000), UINT64_C(0),	// V_CMPX_F_F16_fake16_e32_gfx11
    UINT64_C(3565158400), UINT64_C(0),	// V_CMPX_F_F16_fake16_e64_dpp8_gfx11
    UINT64_C(1077306982400), UINT64_C(0),	// V_CMPX_F_F16_fake16_e64_dpp_gfx11
    UINT64_C(3565158400), UINT64_C(0),	// V_CMPX_F_F16_fake16_e64_gfx11
    UINT64_C(2108686585), UINT64_C(0),	// V_CMPX_F_F16_sdwa_gfx10
    UINT64_C(2086666489), UINT64_C(0),	// V_CMPX_F_F16_sdwa_gfx9
    UINT64_C(2086666489), UINT64_C(0),	// V_CMPX_F_F16_sdwa_vi
    UINT64_C(2097152000), UINT64_C(0),	// V_CMPX_F_F16_t16_e32_dpp8_gfx11
    UINT64_C(2097152250), UINT64_C(0),	// V_CMPX_F_F16_t16_e32_dpp_gfx11
    UINT64_C(2097152000), UINT64_C(0),	// V_CMPX_F_F16_t16_e32_gfx11
    UINT64_C(3565158400), UINT64_C(0),	// V_CMPX_F_F16_t16_e64_dpp8_gfx11
    UINT64_C(1077306982400), UINT64_C(0),	// V_CMPX_F_F16_t16_e64_dpp_gfx11
    UINT64_C(3565158400), UINT64_C(0),	// V_CMPX_F_F16_t16_e64_gfx11
    UINT64_C(2099249152), UINT64_C(0),	// V_CMPX_F_F32_e32_dpp8_gfx11
    UINT64_C(2099249402), UINT64_C(0),	// V_CMPX_F_F32_e32_dpp_gfx11
    UINT64_C(2082471936), UINT64_C(0),	// V_CMPX_F_F32_e32_gfx10
    UINT64_C(2099249152), UINT64_C(0),	// V_CMPX_F_F32_e32_gfx11
    UINT64_C(2082471936), UINT64_C(0),	// V_CMPX_F_F32_e32_gfx6_gfx7
    UINT64_C(2090860544), UINT64_C(0),	// V_CMPX_F_F32_e32_vi
    UINT64_C(3566206976), UINT64_C(0),	// V_CMPX_F_F32_e64_dpp8_gfx11
    UINT64_C(1077308030976), UINT64_C(0),	// V_CMPX_F_F32_e64_dpp_gfx11
    UINT64_C(3557818368), UINT64_C(0),	// V_CMPX_F_F32_e64_gfx10
    UINT64_C(3566206976), UINT64_C(0),	// V_CMPX_F_F32_e64_gfx11
    UINT64_C(3491758080), UINT64_C(0),	// V_CMPX_F_F32_e64_gfx6_gfx7
    UINT64_C(3494903808), UINT64_C(0),	// V_CMPX_F_F32_e64_vi
    UINT64_C(2082472185), UINT64_C(0),	// V_CMPX_F_F32_sdwa_gfx10
    UINT64_C(2090860793), UINT64_C(0),	// V_CMPX_F_F32_sdwa_gfx9
    UINT64_C(2090860793), UINT64_C(0),	// V_CMPX_F_F32_sdwa_vi
    UINT64_C(2086666240), UINT64_C(0),	// V_CMPX_F_F64_e32_gfx10
    UINT64_C(2101346304), UINT64_C(0),	// V_CMPX_F_F64_e32_gfx11
    UINT64_C(2086666240), UINT64_C(0),	// V_CMPX_F_F64_e32_gfx6_gfx7
    UINT64_C(2095054848), UINT64_C(0),	// V_CMPX_F_F64_e32_vi
    UINT64_C(3559915520), UINT64_C(0),	// V_CMPX_F_F64_e64_gfx10
    UINT64_C(3567255552), UINT64_C(0),	// V_CMPX_F_F64_e64_gfx11
    UINT64_C(3495952384), UINT64_C(0),	// V_CMPX_F_F64_e64_gfx6_gfx7
    UINT64_C(3497000960), UINT64_C(0),	// V_CMPX_F_F64_e64_vi
    UINT64_C(2103443456), UINT64_C(0),	// V_CMPX_F_I16_e32_vi
    UINT64_C(3501195264), UINT64_C(0),	// V_CMPX_F_I16_e64_vi
    UINT64_C(2103443705), UINT64_C(0),	// V_CMPX_F_I16_sdwa_gfx9
    UINT64_C(2103443705), UINT64_C(0),	// V_CMPX_F_I16_sdwa_vi
    UINT64_C(2105540608), UINT64_C(0),	// V_CMPX_F_I32_e32_dpp8_gfx11
    UINT64_C(2105540858), UINT64_C(0),	// V_CMPX_F_I32_e32_dpp_gfx11
    UINT64_C(2099249152), UINT64_C(0),	// V_CMPX_F_I32_e32_gfx10
    UINT64_C(2105540608), UINT64_C(0),	// V_CMPX_F_I32_e32_gfx11
    UINT64_C(2099249152), UINT64_C(0),	// V_CMPX_F_I32_e32_gfx6_gfx7
    UINT64_C(2107637760), UINT64_C(0),	// V_CMPX_F_I32_e32_vi
    UINT64_C(3569352704), UINT64_C(0),	// V_CMPX_F_I32_e64_dpp8_gfx11
    UINT64_C(1077311176704), UINT64_C(0),	// V_CMPX_F_I32_e64_dpp_gfx11
    UINT64_C(3566206976), UINT64_C(0),	// V_CMPX_F_I32_e64_gfx10
    UINT64_C(3569352704), UINT64_C(0),	// V_CMPX_F_I32_e64_gfx11
    UINT64_C(3508535296), UINT64_C(0),	// V_CMPX_F_I32_e64_gfx6_gfx7
    UINT64_C(3503292416), UINT64_C(0),	// V_CMPX_F_I32_e64_vi
    UINT64_C(2099249401), UINT64_C(0),	// V_CMPX_F_I32_sdwa_gfx10
    UINT64_C(2107638009), UINT64_C(0),	// V_CMPX_F_I32_sdwa_gfx9
    UINT64_C(2107638009), UINT64_C(0),	// V_CMPX_F_I32_sdwa_vi
    UINT64_C(2103443456), UINT64_C(0),	// V_CMPX_F_I64_e32_gfx10
    UINT64_C(2107637760), UINT64_C(0),	// V_CMPX_F_I64_e32_gfx11
    UINT64_C(2103443456), UINT64_C(0),	// V_CMPX_F_I64_e32_gfx6_gfx7
    UINT64_C(2111832064), UINT64_C(0),	// V_CMPX_F_I64_e32_vi
    UINT64_C(3568304128), UINT64_C(0),	// V_CMPX_F_I64_e64_gfx10
    UINT64_C(3570401280), UINT64_C(0),	// V_CMPX_F_I64_e64_gfx11
    UINT64_C(3512729600), UINT64_C(0),	// V_CMPX_F_I64_e64_gfx6_gfx7
    UINT64_C(3505389568), UINT64_C(0),	// V_CMPX_F_I64_e64_vi
    UINT64_C(2104492032), UINT64_C(0),	// V_CMPX_F_U16_e32_vi
    UINT64_C(3501719552), UINT64_C(0),	// V_CMPX_F_U16_e64_vi
    UINT64_C(2104492281), UINT64_C(0),	// V_CMPX_F_U16_sdwa_gfx9
    UINT64_C(2104492281), UINT64_C(0),	// V_CMPX_F_U16_sdwa_vi
    UINT64_C(2106589184), UINT64_C(0),	// V_CMPX_F_U32_e32_dpp8_gfx11
    UINT64_C(2106589434), UINT64_C(0),	// V_CMPX_F_U32_e32_dpp_gfx11
    UINT64_C(2107637760), UINT64_C(0),	// V_CMPX_F_U32_e32_gfx10
    UINT64_C(2106589184), UINT64_C(0),	// V_CMPX_F_U32_e32_gfx11
    UINT64_C(2107637760), UINT64_C(0),	// V_CMPX_F_U32_e32_gfx6_gfx7
    UINT64_C(2108686336), UINT64_C(0),	// V_CMPX_F_U32_e32_vi
    UINT64_C(3569876992), UINT64_C(0),	// V_CMPX_F_U32_e64_dpp8_gfx11
    UINT64_C(1077311700992), UINT64_C(0),	// V_CMPX_F_U32_e64_dpp_gfx11
    UINT64_C(3570401280), UINT64_C(0),	// V_CMPX_F_U32_e64_gfx10
    UINT64_C(3569876992), UINT64_C(0),	// V_CMPX_F_U32_e64_gfx11
    UINT64_C(3516923904), UINT64_C(0),	// V_CMPX_F_U32_e64_gfx6_gfx7
    UINT64_C(3503816704), UINT64_C(0),	// V_CMPX_F_U32_e64_vi
    UINT64_C(2107638009), UINT64_C(0),	// V_CMPX_F_U32_sdwa_gfx10
    UINT64_C(2108686585), UINT64_C(0),	// V_CMPX_F_U32_sdwa_gfx9
    UINT64_C(2108686585), UINT64_C(0),	// V_CMPX_F_U32_sdwa_vi
    UINT64_C(2111832064), UINT64_C(0),	// V_CMPX_F_U64_e32_gfx10
    UINT64_C(2108686336), UINT64_C(0),	// V_CMPX_F_U64_e32_gfx11
    UINT64_C(2111832064), UINT64_C(0),	// V_CMPX_F_U64_e32_gfx6_gfx7
    UINT64_C(2112880640), UINT64_C(0),	// V_CMPX_F_U64_e32_vi
    UINT64_C(3572498432), UINT64_C(0),	// V_CMPX_F_U64_e64_gfx10
    UINT64_C(3570925568), UINT64_C(0),	// V_CMPX_F_U64_e64_gfx11
    UINT64_C(3521118208), UINT64_C(0),	// V_CMPX_F_U64_e64_gfx6_gfx7
    UINT64_C(3505913856), UINT64_C(0),	// V_CMPX_F_U64_e64_vi
    UINT64_C(2109472768), UINT64_C(0),	// V_CMPX_GE_F16_e32_gfx10
    UINT64_C(2087452672), UINT64_C(0),	// V_CMPX_GE_F16_e32_vi
    UINT64_C(3571318784), UINT64_C(0),	// V_CMPX_GE_F16_e64_gfx10
    UINT64_C(3493199872), UINT64_C(0),	// V_CMPX_GE_F16_e64_vi
    UINT64_C(2097938432), UINT64_C(0),	// V_CMPX_GE_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2097938432), UINT64_C(0),	// V_CMPX_GE_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2097938682), UINT64_C(0),	// V_CMPX_GE_F16_fake16_e32_dpp_gfx11
    UINT64_C(2097938682), UINT64_C(0),	// V_CMPX_GE_F16_fake16_e32_dpp_gfx12
    UINT64_C(2097938432), UINT64_C(0),	// V_CMPX_GE_F16_fake16_e32_gfx11
    UINT64_C(2097938432), UINT64_C(0),	// V_CMPX_GE_F16_fake16_e32_gfx12
    UINT64_C(3565551616), UINT64_C(0),	// V_CMPX_GE_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3565551616), UINT64_C(0),	// V_CMPX_GE_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077307375616), UINT64_C(0),	// V_CMPX_GE_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077307375616), UINT64_C(0),	// V_CMPX_GE_F16_fake16_e64_dpp_gfx12
    UINT64_C(3565551616), UINT64_C(0),	// V_CMPX_GE_F16_fake16_e64_gfx11
    UINT64_C(3565551616), UINT64_C(0),	// V_CMPX_GE_F16_fake16_e64_gfx12
    UINT64_C(2109473017), UINT64_C(0),	// V_CMPX_GE_F16_sdwa_gfx10
    UINT64_C(2087452921), UINT64_C(0),	// V_CMPX_GE_F16_sdwa_gfx9
    UINT64_C(2087452921), UINT64_C(0),	// V_CMPX_GE_F16_sdwa_vi
    UINT64_C(2097938432), UINT64_C(0),	// V_CMPX_GE_F16_t16_e32_dpp8_gfx11
    UINT64_C(2097938432), UINT64_C(0),	// V_CMPX_GE_F16_t16_e32_dpp8_gfx12
    UINT64_C(2097938682), UINT64_C(0),	// V_CMPX_GE_F16_t16_e32_dpp_gfx11
    UINT64_C(2097938682), UINT64_C(0),	// V_CMPX_GE_F16_t16_e32_dpp_gfx12
    UINT64_C(2097938432), UINT64_C(0),	// V_CMPX_GE_F16_t16_e32_gfx11
    UINT64_C(2097938432), UINT64_C(0),	// V_CMPX_GE_F16_t16_e32_gfx12
    UINT64_C(3565551616), UINT64_C(0),	// V_CMPX_GE_F16_t16_e64_dpp8_gfx11
    UINT64_C(3565551616), UINT64_C(0),	// V_CMPX_GE_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077307375616), UINT64_C(0),	// V_CMPX_GE_F16_t16_e64_dpp_gfx11
    UINT64_C(1077307375616), UINT64_C(0),	// V_CMPX_GE_F16_t16_e64_dpp_gfx12
    UINT64_C(3565551616), UINT64_C(0),	// V_CMPX_GE_F16_t16_e64_gfx11
    UINT64_C(3565551616), UINT64_C(0),	// V_CMPX_GE_F16_t16_e64_gfx12
    UINT64_C(2100035584), UINT64_C(0),	// V_CMPX_GE_F32_e32_dpp8_gfx11
    UINT64_C(2100035584), UINT64_C(0),	// V_CMPX_GE_F32_e32_dpp8_gfx12
    UINT64_C(2100035834), UINT64_C(0),	// V_CMPX_GE_F32_e32_dpp_gfx11
    UINT64_C(2100035834), UINT64_C(0),	// V_CMPX_GE_F32_e32_dpp_gfx12
    UINT64_C(2083258368), UINT64_C(0),	// V_CMPX_GE_F32_e32_gfx10
    UINT64_C(2100035584), UINT64_C(0),	// V_CMPX_GE_F32_e32_gfx11
    UINT64_C(2100035584), UINT64_C(0),	// V_CMPX_GE_F32_e32_gfx12
    UINT64_C(2083258368), UINT64_C(0),	// V_CMPX_GE_F32_e32_gfx6_gfx7
    UINT64_C(2091646976), UINT64_C(0),	// V_CMPX_GE_F32_e32_vi
    UINT64_C(3566600192), UINT64_C(0),	// V_CMPX_GE_F32_e64_dpp8_gfx11
    UINT64_C(3566600192), UINT64_C(0),	// V_CMPX_GE_F32_e64_dpp8_gfx12
    UINT64_C(1077308424192), UINT64_C(0),	// V_CMPX_GE_F32_e64_dpp_gfx11
    UINT64_C(1077308424192), UINT64_C(0),	// V_CMPX_GE_F32_e64_dpp_gfx12
    UINT64_C(3558211584), UINT64_C(0),	// V_CMPX_GE_F32_e64_gfx10
    UINT64_C(3566600192), UINT64_C(0),	// V_CMPX_GE_F32_e64_gfx11
    UINT64_C(3566600192), UINT64_C(0),	// V_CMPX_GE_F32_e64_gfx12
    UINT64_C(3492544512), UINT64_C(0),	// V_CMPX_GE_F32_e64_gfx6_gfx7
    UINT64_C(3495297024), UINT64_C(0),	// V_CMPX_GE_F32_e64_vi
    UINT64_C(2083258617), UINT64_C(0),	// V_CMPX_GE_F32_sdwa_gfx10
    UINT64_C(2091647225), UINT64_C(0),	// V_CMPX_GE_F32_sdwa_gfx9
    UINT64_C(2091647225), UINT64_C(0),	// V_CMPX_GE_F32_sdwa_vi
    UINT64_C(2087452672), UINT64_C(0),	// V_CMPX_GE_F64_e32_gfx10
    UINT64_C(2102132736), UINT64_C(0),	// V_CMPX_GE_F64_e32_gfx11
    UINT64_C(2102132736), UINT64_C(0),	// V_CMPX_GE_F64_e32_gfx12
    UINT64_C(2087452672), UINT64_C(0),	// V_CMPX_GE_F64_e32_gfx6_gfx7
    UINT64_C(2095841280), UINT64_C(0),	// V_CMPX_GE_F64_e32_vi
    UINT64_C(3560308736), UINT64_C(0),	// V_CMPX_GE_F64_e64_gfx10
    UINT64_C(3567648768), UINT64_C(0),	// V_CMPX_GE_F64_e64_gfx11
    UINT64_C(3567648768), UINT64_C(0),	// V_CMPX_GE_F64_e64_gfx12
    UINT64_C(3496738816), UINT64_C(0),	// V_CMPX_GE_F64_e64_gfx6_gfx7
    UINT64_C(3497394176), UINT64_C(0),	// V_CMPX_GE_F64_e64_vi
    UINT64_C(2101084160), UINT64_C(0),	// V_CMPX_GE_I16_e32_gfx10
    UINT64_C(2104229888), UINT64_C(0),	// V_CMPX_GE_I16_e32_vi
    UINT64_C(3567124480), UINT64_C(0),	// V_CMPX_GE_I16_e64_gfx10
    UINT64_C(3501588480), UINT64_C(0),	// V_CMPX_GE_I16_e64_vi
    UINT64_C(2104229888), UINT64_C(0),	// V_CMPX_GE_I16_fake16_e32_dpp8_gfx11
    UINT64_C(2104229888), UINT64_C(0),	// V_CMPX_GE_I16_fake16_e32_dpp8_gfx12
    UINT64_C(2104230138), UINT64_C(0),	// V_CMPX_GE_I16_fake16_e32_dpp_gfx11
    UINT64_C(2104230138), UINT64_C(0),	// V_CMPX_GE_I16_fake16_e32_dpp_gfx12
    UINT64_C(2104229888), UINT64_C(0),	// V_CMPX_GE_I16_fake16_e32_gfx11
    UINT64_C(2104229888), UINT64_C(0),	// V_CMPX_GE_I16_fake16_e32_gfx12
    UINT64_C(3568697344), UINT64_C(0),	// V_CMPX_GE_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3568697344), UINT64_C(0),	// V_CMPX_GE_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077310521344), UINT64_C(0),	// V_CMPX_GE_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077310521344), UINT64_C(0),	// V_CMPX_GE_I16_fake16_e64_dpp_gfx12
    UINT64_C(3568697344), UINT64_C(0),	// V_CMPX_GE_I16_fake16_e64_gfx11
    UINT64_C(3568697344), UINT64_C(0),	// V_CMPX_GE_I16_fake16_e64_gfx12
    UINT64_C(2101084409), UINT64_C(0),	// V_CMPX_GE_I16_sdwa_gfx10
    UINT64_C(2104230137), UINT64_C(0),	// V_CMPX_GE_I16_sdwa_gfx9
    UINT64_C(2104230137), UINT64_C(0),	// V_CMPX_GE_I16_sdwa_vi
    UINT64_C(2104229888), UINT64_C(0),	// V_CMPX_GE_I16_t16_e32_dpp8_gfx11
    UINT64_C(2104229888), UINT64_C(0),	// V_CMPX_GE_I16_t16_e32_dpp8_gfx12
    UINT64_C(2104230138), UINT64_C(0),	// V_CMPX_GE_I16_t16_e32_dpp_gfx11
    UINT64_C(2104230138), UINT64_C(0),	// V_CMPX_GE_I16_t16_e32_dpp_gfx12
    UINT64_C(2104229888), UINT64_C(0),	// V_CMPX_GE_I16_t16_e32_gfx11
    UINT64_C(2104229888), UINT64_C(0),	// V_CMPX_GE_I16_t16_e32_gfx12
    UINT64_C(3568697344), UINT64_C(0),	// V_CMPX_GE_I16_t16_e64_dpp8_gfx11
    UINT64_C(3568697344), UINT64_C(0),	// V_CMPX_GE_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077310521344), UINT64_C(0),	// V_CMPX_GE_I16_t16_e64_dpp_gfx11
    UINT64_C(1077310521344), UINT64_C(0),	// V_CMPX_GE_I16_t16_e64_dpp_gfx12
    UINT64_C(3568697344), UINT64_C(0),	// V_CMPX_GE_I16_t16_e64_gfx11
    UINT64_C(3568697344), UINT64_C(0),	// V_CMPX_GE_I16_t16_e64_gfx12
    UINT64_C(2106327040), UINT64_C(0),	// V_CMPX_GE_I32_e32_dpp8_gfx11
    UINT64_C(2106327040), UINT64_C(0),	// V_CMPX_GE_I32_e32_dpp8_gfx12
    UINT64_C(2106327290), UINT64_C(0),	// V_CMPX_GE_I32_e32_dpp_gfx11
    UINT64_C(2106327290), UINT64_C(0),	// V_CMPX_GE_I32_e32_dpp_gfx12
    UINT64_C(2100035584), UINT64_C(0),	// V_CMPX_GE_I32_e32_gfx10
    UINT64_C(2106327040), UINT64_C(0),	// V_CMPX_GE_I32_e32_gfx11
    UINT64_C(2106327040), UINT64_C(0),	// V_CMPX_GE_I32_e32_gfx12
    UINT64_C(2100035584), UINT64_C(0),	// V_CMPX_GE_I32_e32_gfx6_gfx7
    UINT64_C(2108424192), UINT64_C(0),	// V_CMPX_GE_I32_e32_vi
    UINT64_C(3569745920), UINT64_C(0),	// V_CMPX_GE_I32_e64_dpp8_gfx11
    UINT64_C(3569745920), UINT64_C(0),	// V_CMPX_GE_I32_e64_dpp8_gfx12
    UINT64_C(1077311569920), UINT64_C(0),	// V_CMPX_GE_I32_e64_dpp_gfx11
    UINT64_C(1077311569920), UINT64_C(0),	// V_CMPX_GE_I32_e64_dpp_gfx12
    UINT64_C(3566600192), UINT64_C(0),	// V_CMPX_GE_I32_e64_gfx10
    UINT64_C(3569745920), UINT64_C(0),	// V_CMPX_GE_I32_e64_gfx11
    UINT64_C(3569745920), UINT64_C(0),	// V_CMPX_GE_I32_e64_gfx12
    UINT64_C(3509321728), UINT64_C(0),	// V_CMPX_GE_I32_e64_gfx6_gfx7
    UINT64_C(3503685632), UINT64_C(0),	// V_CMPX_GE_I32_e64_vi
    UINT64_C(2100035833), UINT64_C(0),	// V_CMPX_GE_I32_sdwa_gfx10
    UINT64_C(2108424441), UINT64_C(0),	// V_CMPX_GE_I32_sdwa_gfx9
    UINT64_C(2108424441), UINT64_C(0),	// V_CMPX_GE_I32_sdwa_vi
    UINT64_C(2104229888), UINT64_C(0),	// V_CMPX_GE_I64_e32_gfx10
    UINT64_C(2108424192), UINT64_C(0),	// V_CMPX_GE_I64_e32_gfx11
    UINT64_C(2108424192), UINT64_C(0),	// V_CMPX_GE_I64_e32_gfx12
    UINT64_C(2104229888), UINT64_C(0),	// V_CMPX_GE_I64_e32_gfx6_gfx7
    UINT64_C(2112618496), UINT64_C(0),	// V_CMPX_GE_I64_e32_vi
    UINT64_C(3568697344), UINT64_C(0),	// V_CMPX_GE_I64_e64_gfx10
    UINT64_C(3570794496), UINT64_C(0),	// V_CMPX_GE_I64_e64_gfx11
    UINT64_C(3570794496), UINT64_C(0),	// V_CMPX_GE_I64_e64_gfx12
    UINT64_C(3513516032), UINT64_C(0),	// V_CMPX_GE_I64_e64_gfx6_gfx7
    UINT64_C(3505782784), UINT64_C(0),	// V_CMPX_GE_I64_e64_vi
    UINT64_C(2105278464), UINT64_C(0),	// V_CMPX_GE_U16_e32_gfx10
    UINT64_C(2105278464), UINT64_C(0),	// V_CMPX_GE_U16_e32_vi
    UINT64_C(3569221632), UINT64_C(0),	// V_CMPX_GE_U16_e64_gfx10
    UINT64_C(3502112768), UINT64_C(0),	// V_CMPX_GE_U16_e64_vi
    UINT64_C(2105278464), UINT64_C(0),	// V_CMPX_GE_U16_fake16_e32_dpp8_gfx11
    UINT64_C(2105278464), UINT64_C(0),	// V_CMPX_GE_U16_fake16_e32_dpp8_gfx12
    UINT64_C(2105278714), UINT64_C(0),	// V_CMPX_GE_U16_fake16_e32_dpp_gfx11
    UINT64_C(2105278714), UINT64_C(0),	// V_CMPX_GE_U16_fake16_e32_dpp_gfx12
    UINT64_C(2105278464), UINT64_C(0),	// V_CMPX_GE_U16_fake16_e32_gfx11
    UINT64_C(2105278464), UINT64_C(0),	// V_CMPX_GE_U16_fake16_e32_gfx12
    UINT64_C(3569221632), UINT64_C(0),	// V_CMPX_GE_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3569221632), UINT64_C(0),	// V_CMPX_GE_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077311045632), UINT64_C(0),	// V_CMPX_GE_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077311045632), UINT64_C(0),	// V_CMPX_GE_U16_fake16_e64_dpp_gfx12
    UINT64_C(3569221632), UINT64_C(0),	// V_CMPX_GE_U16_fake16_e64_gfx11
    UINT64_C(3569221632), UINT64_C(0),	// V_CMPX_GE_U16_fake16_e64_gfx12
    UINT64_C(2105278713), UINT64_C(0),	// V_CMPX_GE_U16_sdwa_gfx10
    UINT64_C(2105278713), UINT64_C(0),	// V_CMPX_GE_U16_sdwa_gfx9
    UINT64_C(2105278713), UINT64_C(0),	// V_CMPX_GE_U16_sdwa_vi
    UINT64_C(2105278464), UINT64_C(0),	// V_CMPX_GE_U16_t16_e32_dpp8_gfx11
    UINT64_C(2105278464), UINT64_C(0),	// V_CMPX_GE_U16_t16_e32_dpp8_gfx12
    UINT64_C(2105278714), UINT64_C(0),	// V_CMPX_GE_U16_t16_e32_dpp_gfx11
    UINT64_C(2105278714), UINT64_C(0),	// V_CMPX_GE_U16_t16_e32_dpp_gfx12
    UINT64_C(2105278464), UINT64_C(0),	// V_CMPX_GE_U16_t16_e32_gfx11
    UINT64_C(2105278464), UINT64_C(0),	// V_CMPX_GE_U16_t16_e32_gfx12
    UINT64_C(3569221632), UINT64_C(0),	// V_CMPX_GE_U16_t16_e64_dpp8_gfx11
    UINT64_C(3569221632), UINT64_C(0),	// V_CMPX_GE_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077311045632), UINT64_C(0),	// V_CMPX_GE_U16_t16_e64_dpp_gfx11
    UINT64_C(1077311045632), UINT64_C(0),	// V_CMPX_GE_U16_t16_e64_dpp_gfx12
    UINT64_C(3569221632), UINT64_C(0),	// V_CMPX_GE_U16_t16_e64_gfx11
    UINT64_C(3569221632), UINT64_C(0),	// V_CMPX_GE_U16_t16_e64_gfx12
    UINT64_C(2107375616), UINT64_C(0),	// V_CMPX_GE_U32_e32_dpp8_gfx11
    UINT64_C(2107375616), UINT64_C(0),	// V_CMPX_GE_U32_e32_dpp8_gfx12
    UINT64_C(2107375866), UINT64_C(0),	// V_CMPX_GE_U32_e32_dpp_gfx11
    UINT64_C(2107375866), UINT64_C(0),	// V_CMPX_GE_U32_e32_dpp_gfx12
    UINT64_C(2108424192), UINT64_C(0),	// V_CMPX_GE_U32_e32_gfx10
    UINT64_C(2107375616), UINT64_C(0),	// V_CMPX_GE_U32_e32_gfx11
    UINT64_C(2107375616), UINT64_C(0),	// V_CMPX_GE_U32_e32_gfx12
    UINT64_C(2108424192), UINT64_C(0),	// V_CMPX_GE_U32_e32_gfx6_gfx7
    UINT64_C(2109472768), UINT64_C(0),	// V_CMPX_GE_U32_e32_vi
    UINT64_C(3570270208), UINT64_C(0),	// V_CMPX_GE_U32_e64_dpp8_gfx11
    UINT64_C(3570270208), UINT64_C(0),	// V_CMPX_GE_U32_e64_dpp8_gfx12
    UINT64_C(1077312094208), UINT64_C(0),	// V_CMPX_GE_U32_e64_dpp_gfx11
    UINT64_C(1077312094208), UINT64_C(0),	// V_CMPX_GE_U32_e64_dpp_gfx12
    UINT64_C(3570794496), UINT64_C(0),	// V_CMPX_GE_U32_e64_gfx10
    UINT64_C(3570270208), UINT64_C(0),	// V_CMPX_GE_U32_e64_gfx11
    UINT64_C(3570270208), UINT64_C(0),	// V_CMPX_GE_U32_e64_gfx12
    UINT64_C(3517710336), UINT64_C(0),	// V_CMPX_GE_U32_e64_gfx6_gfx7
    UINT64_C(3504209920), UINT64_C(0),	// V_CMPX_GE_U32_e64_vi
    UINT64_C(2108424441), UINT64_C(0),	// V_CMPX_GE_U32_sdwa_gfx10
    UINT64_C(2109473017), UINT64_C(0),	// V_CMPX_GE_U32_sdwa_gfx9
    UINT64_C(2109473017), UINT64_C(0),	// V_CMPX_GE_U32_sdwa_vi
    UINT64_C(2112618496), UINT64_C(0),	// V_CMPX_GE_U64_e32_gfx10
    UINT64_C(2109472768), UINT64_C(0),	// V_CMPX_GE_U64_e32_gfx11
    UINT64_C(2109472768), UINT64_C(0),	// V_CMPX_GE_U64_e32_gfx12
    UINT64_C(2112618496), UINT64_C(0),	// V_CMPX_GE_U64_e32_gfx6_gfx7
    UINT64_C(2113667072), UINT64_C(0),	// V_CMPX_GE_U64_e32_vi
    UINT64_C(3572891648), UINT64_C(0),	// V_CMPX_GE_U64_e64_gfx10
    UINT64_C(3571318784), UINT64_C(0),	// V_CMPX_GE_U64_e64_gfx11
    UINT64_C(3571318784), UINT64_C(0),	// V_CMPX_GE_U64_e64_gfx12
    UINT64_C(3521904640), UINT64_C(0),	// V_CMPX_GE_U64_e64_gfx6_gfx7
    UINT64_C(3506307072), UINT64_C(0),	// V_CMPX_GE_U64_e64_vi
    UINT64_C(2109210624), UINT64_C(0),	// V_CMPX_GT_F16_e32_gfx10
    UINT64_C(2087190528), UINT64_C(0),	// V_CMPX_GT_F16_e32_vi
    UINT64_C(3571187712), UINT64_C(0),	// V_CMPX_GT_F16_e64_gfx10
    UINT64_C(3493068800), UINT64_C(0),	// V_CMPX_GT_F16_e64_vi
    UINT64_C(2097676288), UINT64_C(0),	// V_CMPX_GT_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2097676288), UINT64_C(0),	// V_CMPX_GT_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2097676538), UINT64_C(0),	// V_CMPX_GT_F16_fake16_e32_dpp_gfx11
    UINT64_C(2097676538), UINT64_C(0),	// V_CMPX_GT_F16_fake16_e32_dpp_gfx12
    UINT64_C(2097676288), UINT64_C(0),	// V_CMPX_GT_F16_fake16_e32_gfx11
    UINT64_C(2097676288), UINT64_C(0),	// V_CMPX_GT_F16_fake16_e32_gfx12
    UINT64_C(3565420544), UINT64_C(0),	// V_CMPX_GT_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3565420544), UINT64_C(0),	// V_CMPX_GT_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077307244544), UINT64_C(0),	// V_CMPX_GT_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077307244544), UINT64_C(0),	// V_CMPX_GT_F16_fake16_e64_dpp_gfx12
    UINT64_C(3565420544), UINT64_C(0),	// V_CMPX_GT_F16_fake16_e64_gfx11
    UINT64_C(3565420544), UINT64_C(0),	// V_CMPX_GT_F16_fake16_e64_gfx12
    UINT64_C(2109210873), UINT64_C(0),	// V_CMPX_GT_F16_sdwa_gfx10
    UINT64_C(2087190777), UINT64_C(0),	// V_CMPX_GT_F16_sdwa_gfx9
    UINT64_C(2087190777), UINT64_C(0),	// V_CMPX_GT_F16_sdwa_vi
    UINT64_C(2097676288), UINT64_C(0),	// V_CMPX_GT_F16_t16_e32_dpp8_gfx11
    UINT64_C(2097676288), UINT64_C(0),	// V_CMPX_GT_F16_t16_e32_dpp8_gfx12
    UINT64_C(2097676538), UINT64_C(0),	// V_CMPX_GT_F16_t16_e32_dpp_gfx11
    UINT64_C(2097676538), UINT64_C(0),	// V_CMPX_GT_F16_t16_e32_dpp_gfx12
    UINT64_C(2097676288), UINT64_C(0),	// V_CMPX_GT_F16_t16_e32_gfx11
    UINT64_C(2097676288), UINT64_C(0),	// V_CMPX_GT_F16_t16_e32_gfx12
    UINT64_C(3565420544), UINT64_C(0),	// V_CMPX_GT_F16_t16_e64_dpp8_gfx11
    UINT64_C(3565420544), UINT64_C(0),	// V_CMPX_GT_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077307244544), UINT64_C(0),	// V_CMPX_GT_F16_t16_e64_dpp_gfx11
    UINT64_C(1077307244544), UINT64_C(0),	// V_CMPX_GT_F16_t16_e64_dpp_gfx12
    UINT64_C(3565420544), UINT64_C(0),	// V_CMPX_GT_F16_t16_e64_gfx11
    UINT64_C(3565420544), UINT64_C(0),	// V_CMPX_GT_F16_t16_e64_gfx12
    UINT64_C(2099773440), UINT64_C(0),	// V_CMPX_GT_F32_e32_dpp8_gfx11
    UINT64_C(2099773440), UINT64_C(0),	// V_CMPX_GT_F32_e32_dpp8_gfx12
    UINT64_C(2099773690), UINT64_C(0),	// V_CMPX_GT_F32_e32_dpp_gfx11
    UINT64_C(2099773690), UINT64_C(0),	// V_CMPX_GT_F32_e32_dpp_gfx12
    UINT64_C(2082996224), UINT64_C(0),	// V_CMPX_GT_F32_e32_gfx10
    UINT64_C(2099773440), UINT64_C(0),	// V_CMPX_GT_F32_e32_gfx11
    UINT64_C(2099773440), UINT64_C(0),	// V_CMPX_GT_F32_e32_gfx12
    UINT64_C(2082996224), UINT64_C(0),	// V_CMPX_GT_F32_e32_gfx6_gfx7
    UINT64_C(2091384832), UINT64_C(0),	// V_CMPX_GT_F32_e32_vi
    UINT64_C(3566469120), UINT64_C(0),	// V_CMPX_GT_F32_e64_dpp8_gfx11
    UINT64_C(3566469120), UINT64_C(0),	// V_CMPX_GT_F32_e64_dpp8_gfx12
    UINT64_C(1077308293120), UINT64_C(0),	// V_CMPX_GT_F32_e64_dpp_gfx11
    UINT64_C(1077308293120), UINT64_C(0),	// V_CMPX_GT_F32_e64_dpp_gfx12
    UINT64_C(3558080512), UINT64_C(0),	// V_CMPX_GT_F32_e64_gfx10
    UINT64_C(3566469120), UINT64_C(0),	// V_CMPX_GT_F32_e64_gfx11
    UINT64_C(3566469120), UINT64_C(0),	// V_CMPX_GT_F32_e64_gfx12
    UINT64_C(3492282368), UINT64_C(0),	// V_CMPX_GT_F32_e64_gfx6_gfx7
    UINT64_C(3495165952), UINT64_C(0),	// V_CMPX_GT_F32_e64_vi
    UINT64_C(2082996473), UINT64_C(0),	// V_CMPX_GT_F32_sdwa_gfx10
    UINT64_C(2091385081), UINT64_C(0),	// V_CMPX_GT_F32_sdwa_gfx9
    UINT64_C(2091385081), UINT64_C(0),	// V_CMPX_GT_F32_sdwa_vi
    UINT64_C(2087190528), UINT64_C(0),	// V_CMPX_GT_F64_e32_gfx10
    UINT64_C(2101870592), UINT64_C(0),	// V_CMPX_GT_F64_e32_gfx11
    UINT64_C(2101870592), UINT64_C(0),	// V_CMPX_GT_F64_e32_gfx12
    UINT64_C(2087190528), UINT64_C(0),	// V_CMPX_GT_F64_e32_gfx6_gfx7
    UINT64_C(2095579136), UINT64_C(0),	// V_CMPX_GT_F64_e32_vi
    UINT64_C(3560177664), UINT64_C(0),	// V_CMPX_GT_F64_e64_gfx10
    UINT64_C(3567517696), UINT64_C(0),	// V_CMPX_GT_F64_e64_gfx11
    UINT64_C(3567517696), UINT64_C(0),	// V_CMPX_GT_F64_e64_gfx12
    UINT64_C(3496476672), UINT64_C(0),	// V_CMPX_GT_F64_e64_gfx6_gfx7
    UINT64_C(3497263104), UINT64_C(0),	// V_CMPX_GT_F64_e64_vi
    UINT64_C(2100822016), UINT64_C(0),	// V_CMPX_GT_I16_e32_gfx10
    UINT64_C(2103967744), UINT64_C(0),	// V_CMPX_GT_I16_e32_vi
    UINT64_C(3566993408), UINT64_C(0),	// V_CMPX_GT_I16_e64_gfx10
    UINT64_C(3501457408), UINT64_C(0),	// V_CMPX_GT_I16_e64_vi
    UINT64_C(2103967744), UINT64_C(0),	// V_CMPX_GT_I16_fake16_e32_dpp8_gfx11
    UINT64_C(2103967744), UINT64_C(0),	// V_CMPX_GT_I16_fake16_e32_dpp8_gfx12
    UINT64_C(2103967994), UINT64_C(0),	// V_CMPX_GT_I16_fake16_e32_dpp_gfx11
    UINT64_C(2103967994), UINT64_C(0),	// V_CMPX_GT_I16_fake16_e32_dpp_gfx12
    UINT64_C(2103967744), UINT64_C(0),	// V_CMPX_GT_I16_fake16_e32_gfx11
    UINT64_C(2103967744), UINT64_C(0),	// V_CMPX_GT_I16_fake16_e32_gfx12
    UINT64_C(3568566272), UINT64_C(0),	// V_CMPX_GT_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3568566272), UINT64_C(0),	// V_CMPX_GT_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077310390272), UINT64_C(0),	// V_CMPX_GT_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077310390272), UINT64_C(0),	// V_CMPX_GT_I16_fake16_e64_dpp_gfx12
    UINT64_C(3568566272), UINT64_C(0),	// V_CMPX_GT_I16_fake16_e64_gfx11
    UINT64_C(3568566272), UINT64_C(0),	// V_CMPX_GT_I16_fake16_e64_gfx12
    UINT64_C(2100822265), UINT64_C(0),	// V_CMPX_GT_I16_sdwa_gfx10
    UINT64_C(2103967993), UINT64_C(0),	// V_CMPX_GT_I16_sdwa_gfx9
    UINT64_C(2103967993), UINT64_C(0),	// V_CMPX_GT_I16_sdwa_vi
    UINT64_C(2103967744), UINT64_C(0),	// V_CMPX_GT_I16_t16_e32_dpp8_gfx11
    UINT64_C(2103967744), UINT64_C(0),	// V_CMPX_GT_I16_t16_e32_dpp8_gfx12
    UINT64_C(2103967994), UINT64_C(0),	// V_CMPX_GT_I16_t16_e32_dpp_gfx11
    UINT64_C(2103967994), UINT64_C(0),	// V_CMPX_GT_I16_t16_e32_dpp_gfx12
    UINT64_C(2103967744), UINT64_C(0),	// V_CMPX_GT_I16_t16_e32_gfx11
    UINT64_C(2103967744), UINT64_C(0),	// V_CMPX_GT_I16_t16_e32_gfx12
    UINT64_C(3568566272), UINT64_C(0),	// V_CMPX_GT_I16_t16_e64_dpp8_gfx11
    UINT64_C(3568566272), UINT64_C(0),	// V_CMPX_GT_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077310390272), UINT64_C(0),	// V_CMPX_GT_I16_t16_e64_dpp_gfx11
    UINT64_C(1077310390272), UINT64_C(0),	// V_CMPX_GT_I16_t16_e64_dpp_gfx12
    UINT64_C(3568566272), UINT64_C(0),	// V_CMPX_GT_I16_t16_e64_gfx11
    UINT64_C(3568566272), UINT64_C(0),	// V_CMPX_GT_I16_t16_e64_gfx12
    UINT64_C(2106064896), UINT64_C(0),	// V_CMPX_GT_I32_e32_dpp8_gfx11
    UINT64_C(2106064896), UINT64_C(0),	// V_CMPX_GT_I32_e32_dpp8_gfx12
    UINT64_C(2106065146), UINT64_C(0),	// V_CMPX_GT_I32_e32_dpp_gfx11
    UINT64_C(2106065146), UINT64_C(0),	// V_CMPX_GT_I32_e32_dpp_gfx12
    UINT64_C(2099773440), UINT64_C(0),	// V_CMPX_GT_I32_e32_gfx10
    UINT64_C(2106064896), UINT64_C(0),	// V_CMPX_GT_I32_e32_gfx11
    UINT64_C(2106064896), UINT64_C(0),	// V_CMPX_GT_I32_e32_gfx12
    UINT64_C(2099773440), UINT64_C(0),	// V_CMPX_GT_I32_e32_gfx6_gfx7
    UINT64_C(2108162048), UINT64_C(0),	// V_CMPX_GT_I32_e32_vi
    UINT64_C(3569614848), UINT64_C(0),	// V_CMPX_GT_I32_e64_dpp8_gfx11
    UINT64_C(3569614848), UINT64_C(0),	// V_CMPX_GT_I32_e64_dpp8_gfx12
    UINT64_C(1077311438848), UINT64_C(0),	// V_CMPX_GT_I32_e64_dpp_gfx11
    UINT64_C(1077311438848), UINT64_C(0),	// V_CMPX_GT_I32_e64_dpp_gfx12
    UINT64_C(3566469120), UINT64_C(0),	// V_CMPX_GT_I32_e64_gfx10
    UINT64_C(3569614848), UINT64_C(0),	// V_CMPX_GT_I32_e64_gfx11
    UINT64_C(3569614848), UINT64_C(0),	// V_CMPX_GT_I32_e64_gfx12
    UINT64_C(3509059584), UINT64_C(0),	// V_CMPX_GT_I32_e64_gfx6_gfx7
    UINT64_C(3503554560), UINT64_C(0),	// V_CMPX_GT_I32_e64_vi
    UINT64_C(2099773689), UINT64_C(0),	// V_CMPX_GT_I32_sdwa_gfx10
    UINT64_C(2108162297), UINT64_C(0),	// V_CMPX_GT_I32_sdwa_gfx9
    UINT64_C(2108162297), UINT64_C(0),	// V_CMPX_GT_I32_sdwa_vi
    UINT64_C(2103967744), UINT64_C(0),	// V_CMPX_GT_I64_e32_gfx10
    UINT64_C(2108162048), UINT64_C(0),	// V_CMPX_GT_I64_e32_gfx11
    UINT64_C(2108162048), UINT64_C(0),	// V_CMPX_GT_I64_e32_gfx12
    UINT64_C(2103967744), UINT64_C(0),	// V_CMPX_GT_I64_e32_gfx6_gfx7
    UINT64_C(2112356352), UINT64_C(0),	// V_CMPX_GT_I64_e32_vi
    UINT64_C(3568566272), UINT64_C(0),	// V_CMPX_GT_I64_e64_gfx10
    UINT64_C(3570663424), UINT64_C(0),	// V_CMPX_GT_I64_e64_gfx11
    UINT64_C(3570663424), UINT64_C(0),	// V_CMPX_GT_I64_e64_gfx12
    UINT64_C(3513253888), UINT64_C(0),	// V_CMPX_GT_I64_e64_gfx6_gfx7
    UINT64_C(3505651712), UINT64_C(0),	// V_CMPX_GT_I64_e64_vi
    UINT64_C(2105016320), UINT64_C(0),	// V_CMPX_GT_U16_e32_gfx10
    UINT64_C(2105016320), UINT64_C(0),	// V_CMPX_GT_U16_e32_vi
    UINT64_C(3569090560), UINT64_C(0),	// V_CMPX_GT_U16_e64_gfx10
    UINT64_C(3501981696), UINT64_C(0),	// V_CMPX_GT_U16_e64_vi
    UINT64_C(2105016320), UINT64_C(0),	// V_CMPX_GT_U16_fake16_e32_dpp8_gfx11
    UINT64_C(2105016320), UINT64_C(0),	// V_CMPX_GT_U16_fake16_e32_dpp8_gfx12
    UINT64_C(2105016570), UINT64_C(0),	// V_CMPX_GT_U16_fake16_e32_dpp_gfx11
    UINT64_C(2105016570), UINT64_C(0),	// V_CMPX_GT_U16_fake16_e32_dpp_gfx12
    UINT64_C(2105016320), UINT64_C(0),	// V_CMPX_GT_U16_fake16_e32_gfx11
    UINT64_C(2105016320), UINT64_C(0),	// V_CMPX_GT_U16_fake16_e32_gfx12
    UINT64_C(3569090560), UINT64_C(0),	// V_CMPX_GT_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3569090560), UINT64_C(0),	// V_CMPX_GT_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077310914560), UINT64_C(0),	// V_CMPX_GT_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077310914560), UINT64_C(0),	// V_CMPX_GT_U16_fake16_e64_dpp_gfx12
    UINT64_C(3569090560), UINT64_C(0),	// V_CMPX_GT_U16_fake16_e64_gfx11
    UINT64_C(3569090560), UINT64_C(0),	// V_CMPX_GT_U16_fake16_e64_gfx12
    UINT64_C(2105016569), UINT64_C(0),	// V_CMPX_GT_U16_sdwa_gfx10
    UINT64_C(2105016569), UINT64_C(0),	// V_CMPX_GT_U16_sdwa_gfx9
    UINT64_C(2105016569), UINT64_C(0),	// V_CMPX_GT_U16_sdwa_vi
    UINT64_C(2105016320), UINT64_C(0),	// V_CMPX_GT_U16_t16_e32_dpp8_gfx11
    UINT64_C(2105016320), UINT64_C(0),	// V_CMPX_GT_U16_t16_e32_dpp8_gfx12
    UINT64_C(2105016570), UINT64_C(0),	// V_CMPX_GT_U16_t16_e32_dpp_gfx11
    UINT64_C(2105016570), UINT64_C(0),	// V_CMPX_GT_U16_t16_e32_dpp_gfx12
    UINT64_C(2105016320), UINT64_C(0),	// V_CMPX_GT_U16_t16_e32_gfx11
    UINT64_C(2105016320), UINT64_C(0),	// V_CMPX_GT_U16_t16_e32_gfx12
    UINT64_C(3569090560), UINT64_C(0),	// V_CMPX_GT_U16_t16_e64_dpp8_gfx11
    UINT64_C(3569090560), UINT64_C(0),	// V_CMPX_GT_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077310914560), UINT64_C(0),	// V_CMPX_GT_U16_t16_e64_dpp_gfx11
    UINT64_C(1077310914560), UINT64_C(0),	// V_CMPX_GT_U16_t16_e64_dpp_gfx12
    UINT64_C(3569090560), UINT64_C(0),	// V_CMPX_GT_U16_t16_e64_gfx11
    UINT64_C(3569090560), UINT64_C(0),	// V_CMPX_GT_U16_t16_e64_gfx12
    UINT64_C(2107113472), UINT64_C(0),	// V_CMPX_GT_U32_e32_dpp8_gfx11
    UINT64_C(2107113472), UINT64_C(0),	// V_CMPX_GT_U32_e32_dpp8_gfx12
    UINT64_C(2107113722), UINT64_C(0),	// V_CMPX_GT_U32_e32_dpp_gfx11
    UINT64_C(2107113722), UINT64_C(0),	// V_CMPX_GT_U32_e32_dpp_gfx12
    UINT64_C(2108162048), UINT64_C(0),	// V_CMPX_GT_U32_e32_gfx10
    UINT64_C(2107113472), UINT64_C(0),	// V_CMPX_GT_U32_e32_gfx11
    UINT64_C(2107113472), UINT64_C(0),	// V_CMPX_GT_U32_e32_gfx12
    UINT64_C(2108162048), UINT64_C(0),	// V_CMPX_GT_U32_e32_gfx6_gfx7
    UINT64_C(2109210624), UINT64_C(0),	// V_CMPX_GT_U32_e32_vi
    UINT64_C(3570139136), UINT64_C(0),	// V_CMPX_GT_U32_e64_dpp8_gfx11
    UINT64_C(3570139136), UINT64_C(0),	// V_CMPX_GT_U32_e64_dpp8_gfx12
    UINT64_C(1077311963136), UINT64_C(0),	// V_CMPX_GT_U32_e64_dpp_gfx11
    UINT64_C(1077311963136), UINT64_C(0),	// V_CMPX_GT_U32_e64_dpp_gfx12
    UINT64_C(3570663424), UINT64_C(0),	// V_CMPX_GT_U32_e64_gfx10
    UINT64_C(3570139136), UINT64_C(0),	// V_CMPX_GT_U32_e64_gfx11
    UINT64_C(3570139136), UINT64_C(0),	// V_CMPX_GT_U32_e64_gfx12
    UINT64_C(3517448192), UINT64_C(0),	// V_CMPX_GT_U32_e64_gfx6_gfx7
    UINT64_C(3504078848), UINT64_C(0),	// V_CMPX_GT_U32_e64_vi
    UINT64_C(2108162297), UINT64_C(0),	// V_CMPX_GT_U32_sdwa_gfx10
    UINT64_C(2109210873), UINT64_C(0),	// V_CMPX_GT_U32_sdwa_gfx9
    UINT64_C(2109210873), UINT64_C(0),	// V_CMPX_GT_U32_sdwa_vi
    UINT64_C(2112356352), UINT64_C(0),	// V_CMPX_GT_U64_e32_gfx10
    UINT64_C(2109210624), UINT64_C(0),	// V_CMPX_GT_U64_e32_gfx11
    UINT64_C(2109210624), UINT64_C(0),	// V_CMPX_GT_U64_e32_gfx12
    UINT64_C(2112356352), UINT64_C(0),	// V_CMPX_GT_U64_e32_gfx6_gfx7
    UINT64_C(2113404928), UINT64_C(0),	// V_CMPX_GT_U64_e32_vi
    UINT64_C(3572760576), UINT64_C(0),	// V_CMPX_GT_U64_e64_gfx10
    UINT64_C(3571187712), UINT64_C(0),	// V_CMPX_GT_U64_e64_gfx11
    UINT64_C(3571187712), UINT64_C(0),	// V_CMPX_GT_U64_e64_gfx12
    UINT64_C(3521642496), UINT64_C(0),	// V_CMPX_GT_U64_e64_gfx6_gfx7
    UINT64_C(3506176000), UINT64_C(0),	// V_CMPX_GT_U64_e64_vi
    UINT64_C(2109079552), UINT64_C(0),	// V_CMPX_LE_F16_e32_gfx10
    UINT64_C(2087059456), UINT64_C(0),	// V_CMPX_LE_F16_e32_vi
    UINT64_C(3571122176), UINT64_C(0),	// V_CMPX_LE_F16_e64_gfx10
    UINT64_C(3493003264), UINT64_C(0),	// V_CMPX_LE_F16_e64_vi
    UINT64_C(2097545216), UINT64_C(0),	// V_CMPX_LE_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2097545216), UINT64_C(0),	// V_CMPX_LE_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2097545466), UINT64_C(0),	// V_CMPX_LE_F16_fake16_e32_dpp_gfx11
    UINT64_C(2097545466), UINT64_C(0),	// V_CMPX_LE_F16_fake16_e32_dpp_gfx12
    UINT64_C(2097545216), UINT64_C(0),	// V_CMPX_LE_F16_fake16_e32_gfx11
    UINT64_C(2097545216), UINT64_C(0),	// V_CMPX_LE_F16_fake16_e32_gfx12
    UINT64_C(3565355008), UINT64_C(0),	// V_CMPX_LE_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3565355008), UINT64_C(0),	// V_CMPX_LE_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077307179008), UINT64_C(0),	// V_CMPX_LE_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077307179008), UINT64_C(0),	// V_CMPX_LE_F16_fake16_e64_dpp_gfx12
    UINT64_C(3565355008), UINT64_C(0),	// V_CMPX_LE_F16_fake16_e64_gfx11
    UINT64_C(3565355008), UINT64_C(0),	// V_CMPX_LE_F16_fake16_e64_gfx12
    UINT64_C(2109079801), UINT64_C(0),	// V_CMPX_LE_F16_sdwa_gfx10
    UINT64_C(2087059705), UINT64_C(0),	// V_CMPX_LE_F16_sdwa_gfx9
    UINT64_C(2087059705), UINT64_C(0),	// V_CMPX_LE_F16_sdwa_vi
    UINT64_C(2097545216), UINT64_C(0),	// V_CMPX_LE_F16_t16_e32_dpp8_gfx11
    UINT64_C(2097545216), UINT64_C(0),	// V_CMPX_LE_F16_t16_e32_dpp8_gfx12
    UINT64_C(2097545466), UINT64_C(0),	// V_CMPX_LE_F16_t16_e32_dpp_gfx11
    UINT64_C(2097545466), UINT64_C(0),	// V_CMPX_LE_F16_t16_e32_dpp_gfx12
    UINT64_C(2097545216), UINT64_C(0),	// V_CMPX_LE_F16_t16_e32_gfx11
    UINT64_C(2097545216), UINT64_C(0),	// V_CMPX_LE_F16_t16_e32_gfx12
    UINT64_C(3565355008), UINT64_C(0),	// V_CMPX_LE_F16_t16_e64_dpp8_gfx11
    UINT64_C(3565355008), UINT64_C(0),	// V_CMPX_LE_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077307179008), UINT64_C(0),	// V_CMPX_LE_F16_t16_e64_dpp_gfx11
    UINT64_C(1077307179008), UINT64_C(0),	// V_CMPX_LE_F16_t16_e64_dpp_gfx12
    UINT64_C(3565355008), UINT64_C(0),	// V_CMPX_LE_F16_t16_e64_gfx11
    UINT64_C(3565355008), UINT64_C(0),	// V_CMPX_LE_F16_t16_e64_gfx12
    UINT64_C(2099642368), UINT64_C(0),	// V_CMPX_LE_F32_e32_dpp8_gfx11
    UINT64_C(2099642368), UINT64_C(0),	// V_CMPX_LE_F32_e32_dpp8_gfx12
    UINT64_C(2099642618), UINT64_C(0),	// V_CMPX_LE_F32_e32_dpp_gfx11
    UINT64_C(2099642618), UINT64_C(0),	// V_CMPX_LE_F32_e32_dpp_gfx12
    UINT64_C(2082865152), UINT64_C(0),	// V_CMPX_LE_F32_e32_gfx10
    UINT64_C(2099642368), UINT64_C(0),	// V_CMPX_LE_F32_e32_gfx11
    UINT64_C(2099642368), UINT64_C(0),	// V_CMPX_LE_F32_e32_gfx12
    UINT64_C(2082865152), UINT64_C(0),	// V_CMPX_LE_F32_e32_gfx6_gfx7
    UINT64_C(2091253760), UINT64_C(0),	// V_CMPX_LE_F32_e32_vi
    UINT64_C(3566403584), UINT64_C(0),	// V_CMPX_LE_F32_e64_dpp8_gfx11
    UINT64_C(3566403584), UINT64_C(0),	// V_CMPX_LE_F32_e64_dpp8_gfx12
    UINT64_C(1077308227584), UINT64_C(0),	// V_CMPX_LE_F32_e64_dpp_gfx11
    UINT64_C(1077308227584), UINT64_C(0),	// V_CMPX_LE_F32_e64_dpp_gfx12
    UINT64_C(3558014976), UINT64_C(0),	// V_CMPX_LE_F32_e64_gfx10
    UINT64_C(3566403584), UINT64_C(0),	// V_CMPX_LE_F32_e64_gfx11
    UINT64_C(3566403584), UINT64_C(0),	// V_CMPX_LE_F32_e64_gfx12
    UINT64_C(3492151296), UINT64_C(0),	// V_CMPX_LE_F32_e64_gfx6_gfx7
    UINT64_C(3495100416), UINT64_C(0),	// V_CMPX_LE_F32_e64_vi
    UINT64_C(2082865401), UINT64_C(0),	// V_CMPX_LE_F32_sdwa_gfx10
    UINT64_C(2091254009), UINT64_C(0),	// V_CMPX_LE_F32_sdwa_gfx9
    UINT64_C(2091254009), UINT64_C(0),	// V_CMPX_LE_F32_sdwa_vi
    UINT64_C(2087059456), UINT64_C(0),	// V_CMPX_LE_F64_e32_gfx10
    UINT64_C(2101739520), UINT64_C(0),	// V_CMPX_LE_F64_e32_gfx11
    UINT64_C(2101739520), UINT64_C(0),	// V_CMPX_LE_F64_e32_gfx12
    UINT64_C(2087059456), UINT64_C(0),	// V_CMPX_LE_F64_e32_gfx6_gfx7
    UINT64_C(2095448064), UINT64_C(0),	// V_CMPX_LE_F64_e32_vi
    UINT64_C(3560112128), UINT64_C(0),	// V_CMPX_LE_F64_e64_gfx10
    UINT64_C(3567452160), UINT64_C(0),	// V_CMPX_LE_F64_e64_gfx11
    UINT64_C(3567452160), UINT64_C(0),	// V_CMPX_LE_F64_e64_gfx12
    UINT64_C(3496345600), UINT64_C(0),	// V_CMPX_LE_F64_e64_gfx6_gfx7
    UINT64_C(3497197568), UINT64_C(0),	// V_CMPX_LE_F64_e64_vi
    UINT64_C(2100690944), UINT64_C(0),	// V_CMPX_LE_I16_e32_gfx10
    UINT64_C(2103836672), UINT64_C(0),	// V_CMPX_LE_I16_e32_vi
    UINT64_C(3566927872), UINT64_C(0),	// V_CMPX_LE_I16_e64_gfx10
    UINT64_C(3501391872), UINT64_C(0),	// V_CMPX_LE_I16_e64_vi
    UINT64_C(2103836672), UINT64_C(0),	// V_CMPX_LE_I16_fake16_e32_dpp8_gfx11
    UINT64_C(2103836672), UINT64_C(0),	// V_CMPX_LE_I16_fake16_e32_dpp8_gfx12
    UINT64_C(2103836922), UINT64_C(0),	// V_CMPX_LE_I16_fake16_e32_dpp_gfx11
    UINT64_C(2103836922), UINT64_C(0),	// V_CMPX_LE_I16_fake16_e32_dpp_gfx12
    UINT64_C(2103836672), UINT64_C(0),	// V_CMPX_LE_I16_fake16_e32_gfx11
    UINT64_C(2103836672), UINT64_C(0),	// V_CMPX_LE_I16_fake16_e32_gfx12
    UINT64_C(3568500736), UINT64_C(0),	// V_CMPX_LE_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3568500736), UINT64_C(0),	// V_CMPX_LE_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077310324736), UINT64_C(0),	// V_CMPX_LE_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077310324736), UINT64_C(0),	// V_CMPX_LE_I16_fake16_e64_dpp_gfx12
    UINT64_C(3568500736), UINT64_C(0),	// V_CMPX_LE_I16_fake16_e64_gfx11
    UINT64_C(3568500736), UINT64_C(0),	// V_CMPX_LE_I16_fake16_e64_gfx12
    UINT64_C(2100691193), UINT64_C(0),	// V_CMPX_LE_I16_sdwa_gfx10
    UINT64_C(2103836921), UINT64_C(0),	// V_CMPX_LE_I16_sdwa_gfx9
    UINT64_C(2103836921), UINT64_C(0),	// V_CMPX_LE_I16_sdwa_vi
    UINT64_C(2103836672), UINT64_C(0),	// V_CMPX_LE_I16_t16_e32_dpp8_gfx11
    UINT64_C(2103836672), UINT64_C(0),	// V_CMPX_LE_I16_t16_e32_dpp8_gfx12
    UINT64_C(2103836922), UINT64_C(0),	// V_CMPX_LE_I16_t16_e32_dpp_gfx11
    UINT64_C(2103836922), UINT64_C(0),	// V_CMPX_LE_I16_t16_e32_dpp_gfx12
    UINT64_C(2103836672), UINT64_C(0),	// V_CMPX_LE_I16_t16_e32_gfx11
    UINT64_C(2103836672), UINT64_C(0),	// V_CMPX_LE_I16_t16_e32_gfx12
    UINT64_C(3568500736), UINT64_C(0),	// V_CMPX_LE_I16_t16_e64_dpp8_gfx11
    UINT64_C(3568500736), UINT64_C(0),	// V_CMPX_LE_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077310324736), UINT64_C(0),	// V_CMPX_LE_I16_t16_e64_dpp_gfx11
    UINT64_C(1077310324736), UINT64_C(0),	// V_CMPX_LE_I16_t16_e64_dpp_gfx12
    UINT64_C(3568500736), UINT64_C(0),	// V_CMPX_LE_I16_t16_e64_gfx11
    UINT64_C(3568500736), UINT64_C(0),	// V_CMPX_LE_I16_t16_e64_gfx12
    UINT64_C(2105933824), UINT64_C(0),	// V_CMPX_LE_I32_e32_dpp8_gfx11
    UINT64_C(2105933824), UINT64_C(0),	// V_CMPX_LE_I32_e32_dpp8_gfx12
    UINT64_C(2105934074), UINT64_C(0),	// V_CMPX_LE_I32_e32_dpp_gfx11
    UINT64_C(2105934074), UINT64_C(0),	// V_CMPX_LE_I32_e32_dpp_gfx12
    UINT64_C(2099642368), UINT64_C(0),	// V_CMPX_LE_I32_e32_gfx10
    UINT64_C(2105933824), UINT64_C(0),	// V_CMPX_LE_I32_e32_gfx11
    UINT64_C(2105933824), UINT64_C(0),	// V_CMPX_LE_I32_e32_gfx12
    UINT64_C(2099642368), UINT64_C(0),	// V_CMPX_LE_I32_e32_gfx6_gfx7
    UINT64_C(2108030976), UINT64_C(0),	// V_CMPX_LE_I32_e32_vi
    UINT64_C(3569549312), UINT64_C(0),	// V_CMPX_LE_I32_e64_dpp8_gfx11
    UINT64_C(3569549312), UINT64_C(0),	// V_CMPX_LE_I32_e64_dpp8_gfx12
    UINT64_C(1077311373312), UINT64_C(0),	// V_CMPX_LE_I32_e64_dpp_gfx11
    UINT64_C(1077311373312), UINT64_C(0),	// V_CMPX_LE_I32_e64_dpp_gfx12
    UINT64_C(3566403584), UINT64_C(0),	// V_CMPX_LE_I32_e64_gfx10
    UINT64_C(3569549312), UINT64_C(0),	// V_CMPX_LE_I32_e64_gfx11
    UINT64_C(3569549312), UINT64_C(0),	// V_CMPX_LE_I32_e64_gfx12
    UINT64_C(3508928512), UINT64_C(0),	// V_CMPX_LE_I32_e64_gfx6_gfx7
    UINT64_C(3503489024), UINT64_C(0),	// V_CMPX_LE_I32_e64_vi
    UINT64_C(2099642617), UINT64_C(0),	// V_CMPX_LE_I32_sdwa_gfx10
    UINT64_C(2108031225), UINT64_C(0),	// V_CMPX_LE_I32_sdwa_gfx9
    UINT64_C(2108031225), UINT64_C(0),	// V_CMPX_LE_I32_sdwa_vi
    UINT64_C(2103836672), UINT64_C(0),	// V_CMPX_LE_I64_e32_gfx10
    UINT64_C(2108030976), UINT64_C(0),	// V_CMPX_LE_I64_e32_gfx11
    UINT64_C(2108030976), UINT64_C(0),	// V_CMPX_LE_I64_e32_gfx12
    UINT64_C(2103836672), UINT64_C(0),	// V_CMPX_LE_I64_e32_gfx6_gfx7
    UINT64_C(2112225280), UINT64_C(0),	// V_CMPX_LE_I64_e32_vi
    UINT64_C(3568500736), UINT64_C(0),	// V_CMPX_LE_I64_e64_gfx10
    UINT64_C(3570597888), UINT64_C(0),	// V_CMPX_LE_I64_e64_gfx11
    UINT64_C(3570597888), UINT64_C(0),	// V_CMPX_LE_I64_e64_gfx12
    UINT64_C(3513122816), UINT64_C(0),	// V_CMPX_LE_I64_e64_gfx6_gfx7
    UINT64_C(3505586176), UINT64_C(0),	// V_CMPX_LE_I64_e64_vi
    UINT64_C(2104885248), UINT64_C(0),	// V_CMPX_LE_U16_e32_gfx10
    UINT64_C(2104885248), UINT64_C(0),	// V_CMPX_LE_U16_e32_vi
    UINT64_C(3569025024), UINT64_C(0),	// V_CMPX_LE_U16_e64_gfx10
    UINT64_C(3501916160), UINT64_C(0),	// V_CMPX_LE_U16_e64_vi
    UINT64_C(2104885248), UINT64_C(0),	// V_CMPX_LE_U16_fake16_e32_dpp8_gfx11
    UINT64_C(2104885248), UINT64_C(0),	// V_CMPX_LE_U16_fake16_e32_dpp8_gfx12
    UINT64_C(2104885498), UINT64_C(0),	// V_CMPX_LE_U16_fake16_e32_dpp_gfx11
    UINT64_C(2104885498), UINT64_C(0),	// V_CMPX_LE_U16_fake16_e32_dpp_gfx12
    UINT64_C(2104885248), UINT64_C(0),	// V_CMPX_LE_U16_fake16_e32_gfx11
    UINT64_C(2104885248), UINT64_C(0),	// V_CMPX_LE_U16_fake16_e32_gfx12
    UINT64_C(3569025024), UINT64_C(0),	// V_CMPX_LE_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3569025024), UINT64_C(0),	// V_CMPX_LE_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077310849024), UINT64_C(0),	// V_CMPX_LE_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077310849024), UINT64_C(0),	// V_CMPX_LE_U16_fake16_e64_dpp_gfx12
    UINT64_C(3569025024), UINT64_C(0),	// V_CMPX_LE_U16_fake16_e64_gfx11
    UINT64_C(3569025024), UINT64_C(0),	// V_CMPX_LE_U16_fake16_e64_gfx12
    UINT64_C(2104885497), UINT64_C(0),	// V_CMPX_LE_U16_sdwa_gfx10
    UINT64_C(2104885497), UINT64_C(0),	// V_CMPX_LE_U16_sdwa_gfx9
    UINT64_C(2104885497), UINT64_C(0),	// V_CMPX_LE_U16_sdwa_vi
    UINT64_C(2104885248), UINT64_C(0),	// V_CMPX_LE_U16_t16_e32_dpp8_gfx11
    UINT64_C(2104885248), UINT64_C(0),	// V_CMPX_LE_U16_t16_e32_dpp8_gfx12
    UINT64_C(2104885498), UINT64_C(0),	// V_CMPX_LE_U16_t16_e32_dpp_gfx11
    UINT64_C(2104885498), UINT64_C(0),	// V_CMPX_LE_U16_t16_e32_dpp_gfx12
    UINT64_C(2104885248), UINT64_C(0),	// V_CMPX_LE_U16_t16_e32_gfx11
    UINT64_C(2104885248), UINT64_C(0),	// V_CMPX_LE_U16_t16_e32_gfx12
    UINT64_C(3569025024), UINT64_C(0),	// V_CMPX_LE_U16_t16_e64_dpp8_gfx11
    UINT64_C(3569025024), UINT64_C(0),	// V_CMPX_LE_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077310849024), UINT64_C(0),	// V_CMPX_LE_U16_t16_e64_dpp_gfx11
    UINT64_C(1077310849024), UINT64_C(0),	// V_CMPX_LE_U16_t16_e64_dpp_gfx12
    UINT64_C(3569025024), UINT64_C(0),	// V_CMPX_LE_U16_t16_e64_gfx11
    UINT64_C(3569025024), UINT64_C(0),	// V_CMPX_LE_U16_t16_e64_gfx12
    UINT64_C(2106982400), UINT64_C(0),	// V_CMPX_LE_U32_e32_dpp8_gfx11
    UINT64_C(2106982400), UINT64_C(0),	// V_CMPX_LE_U32_e32_dpp8_gfx12
    UINT64_C(2106982650), UINT64_C(0),	// V_CMPX_LE_U32_e32_dpp_gfx11
    UINT64_C(2106982650), UINT64_C(0),	// V_CMPX_LE_U32_e32_dpp_gfx12
    UINT64_C(2108030976), UINT64_C(0),	// V_CMPX_LE_U32_e32_gfx10
    UINT64_C(2106982400), UINT64_C(0),	// V_CMPX_LE_U32_e32_gfx11
    UINT64_C(2106982400), UINT64_C(0),	// V_CMPX_LE_U32_e32_gfx12
    UINT64_C(2108030976), UINT64_C(0),	// V_CMPX_LE_U32_e32_gfx6_gfx7
    UINT64_C(2109079552), UINT64_C(0),	// V_CMPX_LE_U32_e32_vi
    UINT64_C(3570073600), UINT64_C(0),	// V_CMPX_LE_U32_e64_dpp8_gfx11
    UINT64_C(3570073600), UINT64_C(0),	// V_CMPX_LE_U32_e64_dpp8_gfx12
    UINT64_C(1077311897600), UINT64_C(0),	// V_CMPX_LE_U32_e64_dpp_gfx11
    UINT64_C(1077311897600), UINT64_C(0),	// V_CMPX_LE_U32_e64_dpp_gfx12
    UINT64_C(3570597888), UINT64_C(0),	// V_CMPX_LE_U32_e64_gfx10
    UINT64_C(3570073600), UINT64_C(0),	// V_CMPX_LE_U32_e64_gfx11
    UINT64_C(3570073600), UINT64_C(0),	// V_CMPX_LE_U32_e64_gfx12
    UINT64_C(3517317120), UINT64_C(0),	// V_CMPX_LE_U32_e64_gfx6_gfx7
    UINT64_C(3504013312), UINT64_C(0),	// V_CMPX_LE_U32_e64_vi
    UINT64_C(2108031225), UINT64_C(0),	// V_CMPX_LE_U32_sdwa_gfx10
    UINT64_C(2109079801), UINT64_C(0),	// V_CMPX_LE_U32_sdwa_gfx9
    UINT64_C(2109079801), UINT64_C(0),	// V_CMPX_LE_U32_sdwa_vi
    UINT64_C(2112225280), UINT64_C(0),	// V_CMPX_LE_U64_e32_gfx10
    UINT64_C(2109079552), UINT64_C(0),	// V_CMPX_LE_U64_e32_gfx11
    UINT64_C(2109079552), UINT64_C(0),	// V_CMPX_LE_U64_e32_gfx12
    UINT64_C(2112225280), UINT64_C(0),	// V_CMPX_LE_U64_e32_gfx6_gfx7
    UINT64_C(2113273856), UINT64_C(0),	// V_CMPX_LE_U64_e32_vi
    UINT64_C(3572695040), UINT64_C(0),	// V_CMPX_LE_U64_e64_gfx10
    UINT64_C(3571122176), UINT64_C(0),	// V_CMPX_LE_U64_e64_gfx11
    UINT64_C(3571122176), UINT64_C(0),	// V_CMPX_LE_U64_e64_gfx12
    UINT64_C(3521511424), UINT64_C(0),	// V_CMPX_LE_U64_e64_gfx6_gfx7
    UINT64_C(3506110464), UINT64_C(0),	// V_CMPX_LE_U64_e64_vi
    UINT64_C(2109341696), UINT64_C(0),	// V_CMPX_LG_F16_e32_gfx10
    UINT64_C(2087321600), UINT64_C(0),	// V_CMPX_LG_F16_e32_vi
    UINT64_C(3571253248), UINT64_C(0),	// V_CMPX_LG_F16_e64_gfx10
    UINT64_C(3493134336), UINT64_C(0),	// V_CMPX_LG_F16_e64_vi
    UINT64_C(2097807360), UINT64_C(0),	// V_CMPX_LG_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2097807360), UINT64_C(0),	// V_CMPX_LG_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2097807610), UINT64_C(0),	// V_CMPX_LG_F16_fake16_e32_dpp_gfx11
    UINT64_C(2097807610), UINT64_C(0),	// V_CMPX_LG_F16_fake16_e32_dpp_gfx12
    UINT64_C(2097807360), UINT64_C(0),	// V_CMPX_LG_F16_fake16_e32_gfx11
    UINT64_C(2097807360), UINT64_C(0),	// V_CMPX_LG_F16_fake16_e32_gfx12
    UINT64_C(3565486080), UINT64_C(0),	// V_CMPX_LG_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3565486080), UINT64_C(0),	// V_CMPX_LG_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077307310080), UINT64_C(0),	// V_CMPX_LG_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077307310080), UINT64_C(0),	// V_CMPX_LG_F16_fake16_e64_dpp_gfx12
    UINT64_C(3565486080), UINT64_C(0),	// V_CMPX_LG_F16_fake16_e64_gfx11
    UINT64_C(3565486080), UINT64_C(0),	// V_CMPX_LG_F16_fake16_e64_gfx12
    UINT64_C(2109341945), UINT64_C(0),	// V_CMPX_LG_F16_sdwa_gfx10
    UINT64_C(2087321849), UINT64_C(0),	// V_CMPX_LG_F16_sdwa_gfx9
    UINT64_C(2087321849), UINT64_C(0),	// V_CMPX_LG_F16_sdwa_vi
    UINT64_C(2097807360), UINT64_C(0),	// V_CMPX_LG_F16_t16_e32_dpp8_gfx11
    UINT64_C(2097807360), UINT64_C(0),	// V_CMPX_LG_F16_t16_e32_dpp8_gfx12
    UINT64_C(2097807610), UINT64_C(0),	// V_CMPX_LG_F16_t16_e32_dpp_gfx11
    UINT64_C(2097807610), UINT64_C(0),	// V_CMPX_LG_F16_t16_e32_dpp_gfx12
    UINT64_C(2097807360), UINT64_C(0),	// V_CMPX_LG_F16_t16_e32_gfx11
    UINT64_C(2097807360), UINT64_C(0),	// V_CMPX_LG_F16_t16_e32_gfx12
    UINT64_C(3565486080), UINT64_C(0),	// V_CMPX_LG_F16_t16_e64_dpp8_gfx11
    UINT64_C(3565486080), UINT64_C(0),	// V_CMPX_LG_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077307310080), UINT64_C(0),	// V_CMPX_LG_F16_t16_e64_dpp_gfx11
    UINT64_C(1077307310080), UINT64_C(0),	// V_CMPX_LG_F16_t16_e64_dpp_gfx12
    UINT64_C(3565486080), UINT64_C(0),	// V_CMPX_LG_F16_t16_e64_gfx11
    UINT64_C(3565486080), UINT64_C(0),	// V_CMPX_LG_F16_t16_e64_gfx12
    UINT64_C(2099904512), UINT64_C(0),	// V_CMPX_LG_F32_e32_dpp8_gfx11
    UINT64_C(2099904512), UINT64_C(0),	// V_CMPX_LG_F32_e32_dpp8_gfx12
    UINT64_C(2099904762), UINT64_C(0),	// V_CMPX_LG_F32_e32_dpp_gfx11
    UINT64_C(2099904762), UINT64_C(0),	// V_CMPX_LG_F32_e32_dpp_gfx12
    UINT64_C(2083127296), UINT64_C(0),	// V_CMPX_LG_F32_e32_gfx10
    UINT64_C(2099904512), UINT64_C(0),	// V_CMPX_LG_F32_e32_gfx11
    UINT64_C(2099904512), UINT64_C(0),	// V_CMPX_LG_F32_e32_gfx12
    UINT64_C(2083127296), UINT64_C(0),	// V_CMPX_LG_F32_e32_gfx6_gfx7
    UINT64_C(2091515904), UINT64_C(0),	// V_CMPX_LG_F32_e32_vi
    UINT64_C(3566534656), UINT64_C(0),	// V_CMPX_LG_F32_e64_dpp8_gfx11
    UINT64_C(3566534656), UINT64_C(0),	// V_CMPX_LG_F32_e64_dpp8_gfx12
    UINT64_C(1077308358656), UINT64_C(0),	// V_CMPX_LG_F32_e64_dpp_gfx11
    UINT64_C(1077308358656), UINT64_C(0),	// V_CMPX_LG_F32_e64_dpp_gfx12
    UINT64_C(3558146048), UINT64_C(0),	// V_CMPX_LG_F32_e64_gfx10
    UINT64_C(3566534656), UINT64_C(0),	// V_CMPX_LG_F32_e64_gfx11
    UINT64_C(3566534656), UINT64_C(0),	// V_CMPX_LG_F32_e64_gfx12
    UINT64_C(3492413440), UINT64_C(0),	// V_CMPX_LG_F32_e64_gfx6_gfx7
    UINT64_C(3495231488), UINT64_C(0),	// V_CMPX_LG_F32_e64_vi
    UINT64_C(2083127545), UINT64_C(0),	// V_CMPX_LG_F32_sdwa_gfx10
    UINT64_C(2091516153), UINT64_C(0),	// V_CMPX_LG_F32_sdwa_gfx9
    UINT64_C(2091516153), UINT64_C(0),	// V_CMPX_LG_F32_sdwa_vi
    UINT64_C(2087321600), UINT64_C(0),	// V_CMPX_LG_F64_e32_gfx10
    UINT64_C(2102001664), UINT64_C(0),	// V_CMPX_LG_F64_e32_gfx11
    UINT64_C(2102001664), UINT64_C(0),	// V_CMPX_LG_F64_e32_gfx12
    UINT64_C(2087321600), UINT64_C(0),	// V_CMPX_LG_F64_e32_gfx6_gfx7
    UINT64_C(2095710208), UINT64_C(0),	// V_CMPX_LG_F64_e32_vi
    UINT64_C(3560243200), UINT64_C(0),	// V_CMPX_LG_F64_e64_gfx10
    UINT64_C(3567583232), UINT64_C(0),	// V_CMPX_LG_F64_e64_gfx11
    UINT64_C(3567583232), UINT64_C(0),	// V_CMPX_LG_F64_e64_gfx12
    UINT64_C(3496607744), UINT64_C(0),	// V_CMPX_LG_F64_e64_gfx6_gfx7
    UINT64_C(3497328640), UINT64_C(0),	// V_CMPX_LG_F64_e64_vi
    UINT64_C(2108817408), UINT64_C(0),	// V_CMPX_LT_F16_e32_gfx10
    UINT64_C(2086797312), UINT64_C(0),	// V_CMPX_LT_F16_e32_vi
    UINT64_C(3570991104), UINT64_C(0),	// V_CMPX_LT_F16_e64_gfx10
    UINT64_C(3492872192), UINT64_C(0),	// V_CMPX_LT_F16_e64_vi
    UINT64_C(2097283072), UINT64_C(0),	// V_CMPX_LT_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2097283072), UINT64_C(0),	// V_CMPX_LT_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2097283322), UINT64_C(0),	// V_CMPX_LT_F16_fake16_e32_dpp_gfx11
    UINT64_C(2097283322), UINT64_C(0),	// V_CMPX_LT_F16_fake16_e32_dpp_gfx12
    UINT64_C(2097283072), UINT64_C(0),	// V_CMPX_LT_F16_fake16_e32_gfx11
    UINT64_C(2097283072), UINT64_C(0),	// V_CMPX_LT_F16_fake16_e32_gfx12
    UINT64_C(3565223936), UINT64_C(0),	// V_CMPX_LT_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3565223936), UINT64_C(0),	// V_CMPX_LT_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077307047936), UINT64_C(0),	// V_CMPX_LT_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077307047936), UINT64_C(0),	// V_CMPX_LT_F16_fake16_e64_dpp_gfx12
    UINT64_C(3565223936), UINT64_C(0),	// V_CMPX_LT_F16_fake16_e64_gfx11
    UINT64_C(3565223936), UINT64_C(0),	// V_CMPX_LT_F16_fake16_e64_gfx12
    UINT64_C(2108817657), UINT64_C(0),	// V_CMPX_LT_F16_sdwa_gfx10
    UINT64_C(2086797561), UINT64_C(0),	// V_CMPX_LT_F16_sdwa_gfx9
    UINT64_C(2086797561), UINT64_C(0),	// V_CMPX_LT_F16_sdwa_vi
    UINT64_C(2097283072), UINT64_C(0),	// V_CMPX_LT_F16_t16_e32_dpp8_gfx11
    UINT64_C(2097283072), UINT64_C(0),	// V_CMPX_LT_F16_t16_e32_dpp8_gfx12
    UINT64_C(2097283322), UINT64_C(0),	// V_CMPX_LT_F16_t16_e32_dpp_gfx11
    UINT64_C(2097283322), UINT64_C(0),	// V_CMPX_LT_F16_t16_e32_dpp_gfx12
    UINT64_C(2097283072), UINT64_C(0),	// V_CMPX_LT_F16_t16_e32_gfx11
    UINT64_C(2097283072), UINT64_C(0),	// V_CMPX_LT_F16_t16_e32_gfx12
    UINT64_C(3565223936), UINT64_C(0),	// V_CMPX_LT_F16_t16_e64_dpp8_gfx11
    UINT64_C(3565223936), UINT64_C(0),	// V_CMPX_LT_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077307047936), UINT64_C(0),	// V_CMPX_LT_F16_t16_e64_dpp_gfx11
    UINT64_C(1077307047936), UINT64_C(0),	// V_CMPX_LT_F16_t16_e64_dpp_gfx12
    UINT64_C(3565223936), UINT64_C(0),	// V_CMPX_LT_F16_t16_e64_gfx11
    UINT64_C(3565223936), UINT64_C(0),	// V_CMPX_LT_F16_t16_e64_gfx12
    UINT64_C(2099380224), UINT64_C(0),	// V_CMPX_LT_F32_e32_dpp8_gfx11
    UINT64_C(2099380224), UINT64_C(0),	// V_CMPX_LT_F32_e32_dpp8_gfx12
    UINT64_C(2099380474), UINT64_C(0),	// V_CMPX_LT_F32_e32_dpp_gfx11
    UINT64_C(2099380474), UINT64_C(0),	// V_CMPX_LT_F32_e32_dpp_gfx12
    UINT64_C(2082603008), UINT64_C(0),	// V_CMPX_LT_F32_e32_gfx10
    UINT64_C(2099380224), UINT64_C(0),	// V_CMPX_LT_F32_e32_gfx11
    UINT64_C(2099380224), UINT64_C(0),	// V_CMPX_LT_F32_e32_gfx12
    UINT64_C(2082603008), UINT64_C(0),	// V_CMPX_LT_F32_e32_gfx6_gfx7
    UINT64_C(2090991616), UINT64_C(0),	// V_CMPX_LT_F32_e32_vi
    UINT64_C(3566272512), UINT64_C(0),	// V_CMPX_LT_F32_e64_dpp8_gfx11
    UINT64_C(3566272512), UINT64_C(0),	// V_CMPX_LT_F32_e64_dpp8_gfx12
    UINT64_C(1077308096512), UINT64_C(0),	// V_CMPX_LT_F32_e64_dpp_gfx11
    UINT64_C(1077308096512), UINT64_C(0),	// V_CMPX_LT_F32_e64_dpp_gfx12
    UINT64_C(3557883904), UINT64_C(0),	// V_CMPX_LT_F32_e64_gfx10
    UINT64_C(3566272512), UINT64_C(0),	// V_CMPX_LT_F32_e64_gfx11
    UINT64_C(3566272512), UINT64_C(0),	// V_CMPX_LT_F32_e64_gfx12
    UINT64_C(3491889152), UINT64_C(0),	// V_CMPX_LT_F32_e64_gfx6_gfx7
    UINT64_C(3494969344), UINT64_C(0),	// V_CMPX_LT_F32_e64_vi
    UINT64_C(2082603257), UINT64_C(0),	// V_CMPX_LT_F32_sdwa_gfx10
    UINT64_C(2090991865), UINT64_C(0),	// V_CMPX_LT_F32_sdwa_gfx9
    UINT64_C(2090991865), UINT64_C(0),	// V_CMPX_LT_F32_sdwa_vi
    UINT64_C(2086797312), UINT64_C(0),	// V_CMPX_LT_F64_e32_gfx10
    UINT64_C(2101477376), UINT64_C(0),	// V_CMPX_LT_F64_e32_gfx11
    UINT64_C(2101477376), UINT64_C(0),	// V_CMPX_LT_F64_e32_gfx12
    UINT64_C(2086797312), UINT64_C(0),	// V_CMPX_LT_F64_e32_gfx6_gfx7
    UINT64_C(2095185920), UINT64_C(0),	// V_CMPX_LT_F64_e32_vi
    UINT64_C(3559981056), UINT64_C(0),	// V_CMPX_LT_F64_e64_gfx10
    UINT64_C(3567321088), UINT64_C(0),	// V_CMPX_LT_F64_e64_gfx11
    UINT64_C(3567321088), UINT64_C(0),	// V_CMPX_LT_F64_e64_gfx12
    UINT64_C(3496083456), UINT64_C(0),	// V_CMPX_LT_F64_e64_gfx6_gfx7
    UINT64_C(3497066496), UINT64_C(0),	// V_CMPX_LT_F64_e64_vi
    UINT64_C(2100428800), UINT64_C(0),	// V_CMPX_LT_I16_e32_gfx10
    UINT64_C(2103574528), UINT64_C(0),	// V_CMPX_LT_I16_e32_vi
    UINT64_C(3566796800), UINT64_C(0),	// V_CMPX_LT_I16_e64_gfx10
    UINT64_C(3501260800), UINT64_C(0),	// V_CMPX_LT_I16_e64_vi
    UINT64_C(2103574528), UINT64_C(0),	// V_CMPX_LT_I16_fake16_e32_dpp8_gfx11
    UINT64_C(2103574528), UINT64_C(0),	// V_CMPX_LT_I16_fake16_e32_dpp8_gfx12
    UINT64_C(2103574778), UINT64_C(0),	// V_CMPX_LT_I16_fake16_e32_dpp_gfx11
    UINT64_C(2103574778), UINT64_C(0),	// V_CMPX_LT_I16_fake16_e32_dpp_gfx12
    UINT64_C(2103574528), UINT64_C(0),	// V_CMPX_LT_I16_fake16_e32_gfx11
    UINT64_C(2103574528), UINT64_C(0),	// V_CMPX_LT_I16_fake16_e32_gfx12
    UINT64_C(3568369664), UINT64_C(0),	// V_CMPX_LT_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3568369664), UINT64_C(0),	// V_CMPX_LT_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077310193664), UINT64_C(0),	// V_CMPX_LT_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077310193664), UINT64_C(0),	// V_CMPX_LT_I16_fake16_e64_dpp_gfx12
    UINT64_C(3568369664), UINT64_C(0),	// V_CMPX_LT_I16_fake16_e64_gfx11
    UINT64_C(3568369664), UINT64_C(0),	// V_CMPX_LT_I16_fake16_e64_gfx12
    UINT64_C(2100429049), UINT64_C(0),	// V_CMPX_LT_I16_sdwa_gfx10
    UINT64_C(2103574777), UINT64_C(0),	// V_CMPX_LT_I16_sdwa_gfx9
    UINT64_C(2103574777), UINT64_C(0),	// V_CMPX_LT_I16_sdwa_vi
    UINT64_C(2103574528), UINT64_C(0),	// V_CMPX_LT_I16_t16_e32_dpp8_gfx11
    UINT64_C(2103574528), UINT64_C(0),	// V_CMPX_LT_I16_t16_e32_dpp8_gfx12
    UINT64_C(2103574778), UINT64_C(0),	// V_CMPX_LT_I16_t16_e32_dpp_gfx11
    UINT64_C(2103574778), UINT64_C(0),	// V_CMPX_LT_I16_t16_e32_dpp_gfx12
    UINT64_C(2103574528), UINT64_C(0),	// V_CMPX_LT_I16_t16_e32_gfx11
    UINT64_C(2103574528), UINT64_C(0),	// V_CMPX_LT_I16_t16_e32_gfx12
    UINT64_C(3568369664), UINT64_C(0),	// V_CMPX_LT_I16_t16_e64_dpp8_gfx11
    UINT64_C(3568369664), UINT64_C(0),	// V_CMPX_LT_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077310193664), UINT64_C(0),	// V_CMPX_LT_I16_t16_e64_dpp_gfx11
    UINT64_C(1077310193664), UINT64_C(0),	// V_CMPX_LT_I16_t16_e64_dpp_gfx12
    UINT64_C(3568369664), UINT64_C(0),	// V_CMPX_LT_I16_t16_e64_gfx11
    UINT64_C(3568369664), UINT64_C(0),	// V_CMPX_LT_I16_t16_e64_gfx12
    UINT64_C(2105671680), UINT64_C(0),	// V_CMPX_LT_I32_e32_dpp8_gfx11
    UINT64_C(2105671680), UINT64_C(0),	// V_CMPX_LT_I32_e32_dpp8_gfx12
    UINT64_C(2105671930), UINT64_C(0),	// V_CMPX_LT_I32_e32_dpp_gfx11
    UINT64_C(2105671930), UINT64_C(0),	// V_CMPX_LT_I32_e32_dpp_gfx12
    UINT64_C(2099380224), UINT64_C(0),	// V_CMPX_LT_I32_e32_gfx10
    UINT64_C(2105671680), UINT64_C(0),	// V_CMPX_LT_I32_e32_gfx11
    UINT64_C(2105671680), UINT64_C(0),	// V_CMPX_LT_I32_e32_gfx12
    UINT64_C(2099380224), UINT64_C(0),	// V_CMPX_LT_I32_e32_gfx6_gfx7
    UINT64_C(2107768832), UINT64_C(0),	// V_CMPX_LT_I32_e32_vi
    UINT64_C(3569418240), UINT64_C(0),	// V_CMPX_LT_I32_e64_dpp8_gfx11
    UINT64_C(3569418240), UINT64_C(0),	// V_CMPX_LT_I32_e64_dpp8_gfx12
    UINT64_C(1077311242240), UINT64_C(0),	// V_CMPX_LT_I32_e64_dpp_gfx11
    UINT64_C(1077311242240), UINT64_C(0),	// V_CMPX_LT_I32_e64_dpp_gfx12
    UINT64_C(3566272512), UINT64_C(0),	// V_CMPX_LT_I32_e64_gfx10
    UINT64_C(3569418240), UINT64_C(0),	// V_CMPX_LT_I32_e64_gfx11
    UINT64_C(3569418240), UINT64_C(0),	// V_CMPX_LT_I32_e64_gfx12
    UINT64_C(3508666368), UINT64_C(0),	// V_CMPX_LT_I32_e64_gfx6_gfx7
    UINT64_C(3503357952), UINT64_C(0),	// V_CMPX_LT_I32_e64_vi
    UINT64_C(2099380473), UINT64_C(0),	// V_CMPX_LT_I32_sdwa_gfx10
    UINT64_C(2107769081), UINT64_C(0),	// V_CMPX_LT_I32_sdwa_gfx9
    UINT64_C(2107769081), UINT64_C(0),	// V_CMPX_LT_I32_sdwa_vi
    UINT64_C(2103574528), UINT64_C(0),	// V_CMPX_LT_I64_e32_gfx10
    UINT64_C(2107768832), UINT64_C(0),	// V_CMPX_LT_I64_e32_gfx11
    UINT64_C(2107768832), UINT64_C(0),	// V_CMPX_LT_I64_e32_gfx12
    UINT64_C(2103574528), UINT64_C(0),	// V_CMPX_LT_I64_e32_gfx6_gfx7
    UINT64_C(2111963136), UINT64_C(0),	// V_CMPX_LT_I64_e32_vi
    UINT64_C(3568369664), UINT64_C(0),	// V_CMPX_LT_I64_e64_gfx10
    UINT64_C(3570466816), UINT64_C(0),	// V_CMPX_LT_I64_e64_gfx11
    UINT64_C(3570466816), UINT64_C(0),	// V_CMPX_LT_I64_e64_gfx12
    UINT64_C(3512860672), UINT64_C(0),	// V_CMPX_LT_I64_e64_gfx6_gfx7
    UINT64_C(3505455104), UINT64_C(0),	// V_CMPX_LT_I64_e64_vi
    UINT64_C(2104623104), UINT64_C(0),	// V_CMPX_LT_U16_e32_gfx10
    UINT64_C(2104623104), UINT64_C(0),	// V_CMPX_LT_U16_e32_vi
    UINT64_C(3568893952), UINT64_C(0),	// V_CMPX_LT_U16_e64_gfx10
    UINT64_C(3501785088), UINT64_C(0),	// V_CMPX_LT_U16_e64_vi
    UINT64_C(2104623104), UINT64_C(0),	// V_CMPX_LT_U16_fake16_e32_dpp8_gfx11
    UINT64_C(2104623104), UINT64_C(0),	// V_CMPX_LT_U16_fake16_e32_dpp8_gfx12
    UINT64_C(2104623354), UINT64_C(0),	// V_CMPX_LT_U16_fake16_e32_dpp_gfx11
    UINT64_C(2104623354), UINT64_C(0),	// V_CMPX_LT_U16_fake16_e32_dpp_gfx12
    UINT64_C(2104623104), UINT64_C(0),	// V_CMPX_LT_U16_fake16_e32_gfx11
    UINT64_C(2104623104), UINT64_C(0),	// V_CMPX_LT_U16_fake16_e32_gfx12
    UINT64_C(3568893952), UINT64_C(0),	// V_CMPX_LT_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3568893952), UINT64_C(0),	// V_CMPX_LT_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077310717952), UINT64_C(0),	// V_CMPX_LT_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077310717952), UINT64_C(0),	// V_CMPX_LT_U16_fake16_e64_dpp_gfx12
    UINT64_C(3568893952), UINT64_C(0),	// V_CMPX_LT_U16_fake16_e64_gfx11
    UINT64_C(3568893952), UINT64_C(0),	// V_CMPX_LT_U16_fake16_e64_gfx12
    UINT64_C(2104623353), UINT64_C(0),	// V_CMPX_LT_U16_sdwa_gfx10
    UINT64_C(2104623353), UINT64_C(0),	// V_CMPX_LT_U16_sdwa_gfx9
    UINT64_C(2104623353), UINT64_C(0),	// V_CMPX_LT_U16_sdwa_vi
    UINT64_C(2104623104), UINT64_C(0),	// V_CMPX_LT_U16_t16_e32_dpp8_gfx11
    UINT64_C(2104623104), UINT64_C(0),	// V_CMPX_LT_U16_t16_e32_dpp8_gfx12
    UINT64_C(2104623354), UINT64_C(0),	// V_CMPX_LT_U16_t16_e32_dpp_gfx11
    UINT64_C(2104623354), UINT64_C(0),	// V_CMPX_LT_U16_t16_e32_dpp_gfx12
    UINT64_C(2104623104), UINT64_C(0),	// V_CMPX_LT_U16_t16_e32_gfx11
    UINT64_C(2104623104), UINT64_C(0),	// V_CMPX_LT_U16_t16_e32_gfx12
    UINT64_C(3568893952), UINT64_C(0),	// V_CMPX_LT_U16_t16_e64_dpp8_gfx11
    UINT64_C(3568893952), UINT64_C(0),	// V_CMPX_LT_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077310717952), UINT64_C(0),	// V_CMPX_LT_U16_t16_e64_dpp_gfx11
    UINT64_C(1077310717952), UINT64_C(0),	// V_CMPX_LT_U16_t16_e64_dpp_gfx12
    UINT64_C(3568893952), UINT64_C(0),	// V_CMPX_LT_U16_t16_e64_gfx11
    UINT64_C(3568893952), UINT64_C(0),	// V_CMPX_LT_U16_t16_e64_gfx12
    UINT64_C(2106720256), UINT64_C(0),	// V_CMPX_LT_U32_e32_dpp8_gfx11
    UINT64_C(2106720256), UINT64_C(0),	// V_CMPX_LT_U32_e32_dpp8_gfx12
    UINT64_C(2106720506), UINT64_C(0),	// V_CMPX_LT_U32_e32_dpp_gfx11
    UINT64_C(2106720506), UINT64_C(0),	// V_CMPX_LT_U32_e32_dpp_gfx12
    UINT64_C(2107768832), UINT64_C(0),	// V_CMPX_LT_U32_e32_gfx10
    UINT64_C(2106720256), UINT64_C(0),	// V_CMPX_LT_U32_e32_gfx11
    UINT64_C(2106720256), UINT64_C(0),	// V_CMPX_LT_U32_e32_gfx12
    UINT64_C(2107768832), UINT64_C(0),	// V_CMPX_LT_U32_e32_gfx6_gfx7
    UINT64_C(2108817408), UINT64_C(0),	// V_CMPX_LT_U32_e32_vi
    UINT64_C(3569942528), UINT64_C(0),	// V_CMPX_LT_U32_e64_dpp8_gfx11
    UINT64_C(3569942528), UINT64_C(0),	// V_CMPX_LT_U32_e64_dpp8_gfx12
    UINT64_C(1077311766528), UINT64_C(0),	// V_CMPX_LT_U32_e64_dpp_gfx11
    UINT64_C(1077311766528), UINT64_C(0),	// V_CMPX_LT_U32_e64_dpp_gfx12
    UINT64_C(3570466816), UINT64_C(0),	// V_CMPX_LT_U32_e64_gfx10
    UINT64_C(3569942528), UINT64_C(0),	// V_CMPX_LT_U32_e64_gfx11
    UINT64_C(3569942528), UINT64_C(0),	// V_CMPX_LT_U32_e64_gfx12
    UINT64_C(3517054976), UINT64_C(0),	// V_CMPX_LT_U32_e64_gfx6_gfx7
    UINT64_C(3503882240), UINT64_C(0),	// V_CMPX_LT_U32_e64_vi
    UINT64_C(2107769081), UINT64_C(0),	// V_CMPX_LT_U32_sdwa_gfx10
    UINT64_C(2108817657), UINT64_C(0),	// V_CMPX_LT_U32_sdwa_gfx9
    UINT64_C(2108817657), UINT64_C(0),	// V_CMPX_LT_U32_sdwa_vi
    UINT64_C(2111963136), UINT64_C(0),	// V_CMPX_LT_U64_e32_gfx10
    UINT64_C(2108817408), UINT64_C(0),	// V_CMPX_LT_U64_e32_gfx11
    UINT64_C(2108817408), UINT64_C(0),	// V_CMPX_LT_U64_e32_gfx12
    UINT64_C(2111963136), UINT64_C(0),	// V_CMPX_LT_U64_e32_gfx6_gfx7
    UINT64_C(2113011712), UINT64_C(0),	// V_CMPX_LT_U64_e32_vi
    UINT64_C(3572563968), UINT64_C(0),	// V_CMPX_LT_U64_e64_gfx10
    UINT64_C(3570991104), UINT64_C(0),	// V_CMPX_LT_U64_e64_gfx11
    UINT64_C(3570991104), UINT64_C(0),	// V_CMPX_LT_U64_e64_gfx12
    UINT64_C(3521249280), UINT64_C(0),	// V_CMPX_LT_U64_e64_gfx6_gfx7
    UINT64_C(3505979392), UINT64_C(0),	// V_CMPX_LT_U64_e64_vi
    UINT64_C(2113536000), UINT64_C(0),	// V_CMPX_NEQ_F16_e32_gfx10
    UINT64_C(2088370176), UINT64_C(0),	// V_CMPX_NEQ_F16_e32_vi
    UINT64_C(3573350400), UINT64_C(0),	// V_CMPX_NEQ_F16_e64_gfx10
    UINT64_C(3493658624), UINT64_C(0),	// V_CMPX_NEQ_F16_e64_vi
    UINT64_C(2098855936), UINT64_C(0),	// V_CMPX_NEQ_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2098855936), UINT64_C(0),	// V_CMPX_NEQ_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2098856186), UINT64_C(0),	// V_CMPX_NEQ_F16_fake16_e32_dpp_gfx11
    UINT64_C(2098856186), UINT64_C(0),	// V_CMPX_NEQ_F16_fake16_e32_dpp_gfx12
    UINT64_C(2098855936), UINT64_C(0),	// V_CMPX_NEQ_F16_fake16_e32_gfx11
    UINT64_C(2098855936), UINT64_C(0),	// V_CMPX_NEQ_F16_fake16_e32_gfx12
    UINT64_C(3566010368), UINT64_C(0),	// V_CMPX_NEQ_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3566010368), UINT64_C(0),	// V_CMPX_NEQ_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077307834368), UINT64_C(0),	// V_CMPX_NEQ_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077307834368), UINT64_C(0),	// V_CMPX_NEQ_F16_fake16_e64_dpp_gfx12
    UINT64_C(3566010368), UINT64_C(0),	// V_CMPX_NEQ_F16_fake16_e64_gfx11
    UINT64_C(3566010368), UINT64_C(0),	// V_CMPX_NEQ_F16_fake16_e64_gfx12
    UINT64_C(2113536249), UINT64_C(0),	// V_CMPX_NEQ_F16_sdwa_gfx10
    UINT64_C(2088370425), UINT64_C(0),	// V_CMPX_NEQ_F16_sdwa_gfx9
    UINT64_C(2088370425), UINT64_C(0),	// V_CMPX_NEQ_F16_sdwa_vi
    UINT64_C(2098855936), UINT64_C(0),	// V_CMPX_NEQ_F16_t16_e32_dpp8_gfx11
    UINT64_C(2098855936), UINT64_C(0),	// V_CMPX_NEQ_F16_t16_e32_dpp8_gfx12
    UINT64_C(2098856186), UINT64_C(0),	// V_CMPX_NEQ_F16_t16_e32_dpp_gfx11
    UINT64_C(2098856186), UINT64_C(0),	// V_CMPX_NEQ_F16_t16_e32_dpp_gfx12
    UINT64_C(2098855936), UINT64_C(0),	// V_CMPX_NEQ_F16_t16_e32_gfx11
    UINT64_C(2098855936), UINT64_C(0),	// V_CMPX_NEQ_F16_t16_e32_gfx12
    UINT64_C(3566010368), UINT64_C(0),	// V_CMPX_NEQ_F16_t16_e64_dpp8_gfx11
    UINT64_C(3566010368), UINT64_C(0),	// V_CMPX_NEQ_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077307834368), UINT64_C(0),	// V_CMPX_NEQ_F16_t16_e64_dpp_gfx11
    UINT64_C(1077307834368), UINT64_C(0),	// V_CMPX_NEQ_F16_t16_e64_dpp_gfx12
    UINT64_C(3566010368), UINT64_C(0),	// V_CMPX_NEQ_F16_t16_e64_gfx11
    UINT64_C(3566010368), UINT64_C(0),	// V_CMPX_NEQ_F16_t16_e64_gfx12
    UINT64_C(2100953088), UINT64_C(0),	// V_CMPX_NEQ_F32_e32_dpp8_gfx11
    UINT64_C(2100953088), UINT64_C(0),	// V_CMPX_NEQ_F32_e32_dpp8_gfx12
    UINT64_C(2100953338), UINT64_C(0),	// V_CMPX_NEQ_F32_e32_dpp_gfx11
    UINT64_C(2100953338), UINT64_C(0),	// V_CMPX_NEQ_F32_e32_dpp_gfx12
    UINT64_C(2084175872), UINT64_C(0),	// V_CMPX_NEQ_F32_e32_gfx10
    UINT64_C(2100953088), UINT64_C(0),	// V_CMPX_NEQ_F32_e32_gfx11
    UINT64_C(2100953088), UINT64_C(0),	// V_CMPX_NEQ_F32_e32_gfx12
    UINT64_C(2084175872), UINT64_C(0),	// V_CMPX_NEQ_F32_e32_gfx6_gfx7
    UINT64_C(2092564480), UINT64_C(0),	// V_CMPX_NEQ_F32_e32_vi
    UINT64_C(3567058944), UINT64_C(0),	// V_CMPX_NEQ_F32_e64_dpp8_gfx11
    UINT64_C(3567058944), UINT64_C(0),	// V_CMPX_NEQ_F32_e64_dpp8_gfx12
    UINT64_C(1077308882944), UINT64_C(0),	// V_CMPX_NEQ_F32_e64_dpp_gfx11
    UINT64_C(1077308882944), UINT64_C(0),	// V_CMPX_NEQ_F32_e64_dpp_gfx12
    UINT64_C(3558670336), UINT64_C(0),	// V_CMPX_NEQ_F32_e64_gfx10
    UINT64_C(3567058944), UINT64_C(0),	// V_CMPX_NEQ_F32_e64_gfx11
    UINT64_C(3567058944), UINT64_C(0),	// V_CMPX_NEQ_F32_e64_gfx12
    UINT64_C(3493462016), UINT64_C(0),	// V_CMPX_NEQ_F32_e64_gfx6_gfx7
    UINT64_C(3495755776), UINT64_C(0),	// V_CMPX_NEQ_F32_e64_vi
    UINT64_C(2084176121), UINT64_C(0),	// V_CMPX_NEQ_F32_sdwa_gfx10
    UINT64_C(2092564729), UINT64_C(0),	// V_CMPX_NEQ_F32_sdwa_gfx9
    UINT64_C(2092564729), UINT64_C(0),	// V_CMPX_NEQ_F32_sdwa_vi
    UINT64_C(2088370176), UINT64_C(0),	// V_CMPX_NEQ_F64_e32_gfx10
    UINT64_C(2103050240), UINT64_C(0),	// V_CMPX_NEQ_F64_e32_gfx11
    UINT64_C(2103050240), UINT64_C(0),	// V_CMPX_NEQ_F64_e32_gfx12
    UINT64_C(2088370176), UINT64_C(0),	// V_CMPX_NEQ_F64_e32_gfx6_gfx7
    UINT64_C(2096758784), UINT64_C(0),	// V_CMPX_NEQ_F64_e32_vi
    UINT64_C(3560767488), UINT64_C(0),	// V_CMPX_NEQ_F64_e64_gfx10
    UINT64_C(3568107520), UINT64_C(0),	// V_CMPX_NEQ_F64_e64_gfx11
    UINT64_C(3568107520), UINT64_C(0),	// V_CMPX_NEQ_F64_e64_gfx12
    UINT64_C(3497656320), UINT64_C(0),	// V_CMPX_NEQ_F64_e64_gfx6_gfx7
    UINT64_C(3497852928), UINT64_C(0),	// V_CMPX_NEQ_F64_e64_vi
    UINT64_C(2100953088), UINT64_C(0),	// V_CMPX_NE_I16_e32_gfx10
    UINT64_C(2104098816), UINT64_C(0),	// V_CMPX_NE_I16_e32_vi
    UINT64_C(3567058944), UINT64_C(0),	// V_CMPX_NE_I16_e64_gfx10
    UINT64_C(3501522944), UINT64_C(0),	// V_CMPX_NE_I16_e64_vi
    UINT64_C(2104098816), UINT64_C(0),	// V_CMPX_NE_I16_fake16_e32_dpp8_gfx11
    UINT64_C(2104098816), UINT64_C(0),	// V_CMPX_NE_I16_fake16_e32_dpp8_gfx12
    UINT64_C(2104099066), UINT64_C(0),	// V_CMPX_NE_I16_fake16_e32_dpp_gfx11
    UINT64_C(2104099066), UINT64_C(0),	// V_CMPX_NE_I16_fake16_e32_dpp_gfx12
    UINT64_C(2104098816), UINT64_C(0),	// V_CMPX_NE_I16_fake16_e32_gfx11
    UINT64_C(2104098816), UINT64_C(0),	// V_CMPX_NE_I16_fake16_e32_gfx12
    UINT64_C(3568631808), UINT64_C(0),	// V_CMPX_NE_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3568631808), UINT64_C(0),	// V_CMPX_NE_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077310455808), UINT64_C(0),	// V_CMPX_NE_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077310455808), UINT64_C(0),	// V_CMPX_NE_I16_fake16_e64_dpp_gfx12
    UINT64_C(3568631808), UINT64_C(0),	// V_CMPX_NE_I16_fake16_e64_gfx11
    UINT64_C(3568631808), UINT64_C(0),	// V_CMPX_NE_I16_fake16_e64_gfx12
    UINT64_C(2100953337), UINT64_C(0),	// V_CMPX_NE_I16_sdwa_gfx10
    UINT64_C(2104099065), UINT64_C(0),	// V_CMPX_NE_I16_sdwa_gfx9
    UINT64_C(2104099065), UINT64_C(0),	// V_CMPX_NE_I16_sdwa_vi
    UINT64_C(2104098816), UINT64_C(0),	// V_CMPX_NE_I16_t16_e32_dpp8_gfx11
    UINT64_C(2104098816), UINT64_C(0),	// V_CMPX_NE_I16_t16_e32_dpp8_gfx12
    UINT64_C(2104099066), UINT64_C(0),	// V_CMPX_NE_I16_t16_e32_dpp_gfx11
    UINT64_C(2104099066), UINT64_C(0),	// V_CMPX_NE_I16_t16_e32_dpp_gfx12
    UINT64_C(2104098816), UINT64_C(0),	// V_CMPX_NE_I16_t16_e32_gfx11
    UINT64_C(2104098816), UINT64_C(0),	// V_CMPX_NE_I16_t16_e32_gfx12
    UINT64_C(3568631808), UINT64_C(0),	// V_CMPX_NE_I16_t16_e64_dpp8_gfx11
    UINT64_C(3568631808), UINT64_C(0),	// V_CMPX_NE_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077310455808), UINT64_C(0),	// V_CMPX_NE_I16_t16_e64_dpp_gfx11
    UINT64_C(1077310455808), UINT64_C(0),	// V_CMPX_NE_I16_t16_e64_dpp_gfx12
    UINT64_C(3568631808), UINT64_C(0),	// V_CMPX_NE_I16_t16_e64_gfx11
    UINT64_C(3568631808), UINT64_C(0),	// V_CMPX_NE_I16_t16_e64_gfx12
    UINT64_C(2106195968), UINT64_C(0),	// V_CMPX_NE_I32_e32_dpp8_gfx11
    UINT64_C(2106195968), UINT64_C(0),	// V_CMPX_NE_I32_e32_dpp8_gfx12
    UINT64_C(2106196218), UINT64_C(0),	// V_CMPX_NE_I32_e32_dpp_gfx11
    UINT64_C(2106196218), UINT64_C(0),	// V_CMPX_NE_I32_e32_dpp_gfx12
    UINT64_C(2099904512), UINT64_C(0),	// V_CMPX_NE_I32_e32_gfx10
    UINT64_C(2106195968), UINT64_C(0),	// V_CMPX_NE_I32_e32_gfx11
    UINT64_C(2106195968), UINT64_C(0),	// V_CMPX_NE_I32_e32_gfx12
    UINT64_C(2099904512), UINT64_C(0),	// V_CMPX_NE_I32_e32_gfx6_gfx7
    UINT64_C(2108293120), UINT64_C(0),	// V_CMPX_NE_I32_e32_vi
    UINT64_C(3569680384), UINT64_C(0),	// V_CMPX_NE_I32_e64_dpp8_gfx11
    UINT64_C(3569680384), UINT64_C(0),	// V_CMPX_NE_I32_e64_dpp8_gfx12
    UINT64_C(1077311504384), UINT64_C(0),	// V_CMPX_NE_I32_e64_dpp_gfx11
    UINT64_C(1077311504384), UINT64_C(0),	// V_CMPX_NE_I32_e64_dpp_gfx12
    UINT64_C(3566534656), UINT64_C(0),	// V_CMPX_NE_I32_e64_gfx10
    UINT64_C(3569680384), UINT64_C(0),	// V_CMPX_NE_I32_e64_gfx11
    UINT64_C(3569680384), UINT64_C(0),	// V_CMPX_NE_I32_e64_gfx12
    UINT64_C(3509190656), UINT64_C(0),	// V_CMPX_NE_I32_e64_gfx6_gfx7
    UINT64_C(3503620096), UINT64_C(0),	// V_CMPX_NE_I32_e64_vi
    UINT64_C(2099904761), UINT64_C(0),	// V_CMPX_NE_I32_sdwa_gfx10
    UINT64_C(2108293369), UINT64_C(0),	// V_CMPX_NE_I32_sdwa_gfx9
    UINT64_C(2108293369), UINT64_C(0),	// V_CMPX_NE_I32_sdwa_vi
    UINT64_C(2104098816), UINT64_C(0),	// V_CMPX_NE_I64_e32_gfx10
    UINT64_C(2108293120), UINT64_C(0),	// V_CMPX_NE_I64_e32_gfx11
    UINT64_C(2108293120), UINT64_C(0),	// V_CMPX_NE_I64_e32_gfx12
    UINT64_C(2104098816), UINT64_C(0),	// V_CMPX_NE_I64_e32_gfx6_gfx7
    UINT64_C(2112487424), UINT64_C(0),	// V_CMPX_NE_I64_e32_vi
    UINT64_C(3568631808), UINT64_C(0),	// V_CMPX_NE_I64_e64_gfx10
    UINT64_C(3570728960), UINT64_C(0),	// V_CMPX_NE_I64_e64_gfx11
    UINT64_C(3570728960), UINT64_C(0),	// V_CMPX_NE_I64_e64_gfx12
    UINT64_C(3513384960), UINT64_C(0),	// V_CMPX_NE_I64_e64_gfx6_gfx7
    UINT64_C(3505717248), UINT64_C(0),	// V_CMPX_NE_I64_e64_vi
    UINT64_C(2105147392), UINT64_C(0),	// V_CMPX_NE_U16_e32_gfx10
    UINT64_C(2105147392), UINT64_C(0),	// V_CMPX_NE_U16_e32_vi
    UINT64_C(3569156096), UINT64_C(0),	// V_CMPX_NE_U16_e64_gfx10
    UINT64_C(3502047232), UINT64_C(0),	// V_CMPX_NE_U16_e64_vi
    UINT64_C(2105147392), UINT64_C(0),	// V_CMPX_NE_U16_fake16_e32_dpp8_gfx11
    UINT64_C(2105147392), UINT64_C(0),	// V_CMPX_NE_U16_fake16_e32_dpp8_gfx12
    UINT64_C(2105147642), UINT64_C(0),	// V_CMPX_NE_U16_fake16_e32_dpp_gfx11
    UINT64_C(2105147642), UINT64_C(0),	// V_CMPX_NE_U16_fake16_e32_dpp_gfx12
    UINT64_C(2105147392), UINT64_C(0),	// V_CMPX_NE_U16_fake16_e32_gfx11
    UINT64_C(2105147392), UINT64_C(0),	// V_CMPX_NE_U16_fake16_e32_gfx12
    UINT64_C(3569156096), UINT64_C(0),	// V_CMPX_NE_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3569156096), UINT64_C(0),	// V_CMPX_NE_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077310980096), UINT64_C(0),	// V_CMPX_NE_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077310980096), UINT64_C(0),	// V_CMPX_NE_U16_fake16_e64_dpp_gfx12
    UINT64_C(3569156096), UINT64_C(0),	// V_CMPX_NE_U16_fake16_e64_gfx11
    UINT64_C(3569156096), UINT64_C(0),	// V_CMPX_NE_U16_fake16_e64_gfx12
    UINT64_C(2105147641), UINT64_C(0),	// V_CMPX_NE_U16_sdwa_gfx10
    UINT64_C(2105147641), UINT64_C(0),	// V_CMPX_NE_U16_sdwa_gfx9
    UINT64_C(2105147641), UINT64_C(0),	// V_CMPX_NE_U16_sdwa_vi
    UINT64_C(2105147392), UINT64_C(0),	// V_CMPX_NE_U16_t16_e32_dpp8_gfx11
    UINT64_C(2105147392), UINT64_C(0),	// V_CMPX_NE_U16_t16_e32_dpp8_gfx12
    UINT64_C(2105147642), UINT64_C(0),	// V_CMPX_NE_U16_t16_e32_dpp_gfx11
    UINT64_C(2105147642), UINT64_C(0),	// V_CMPX_NE_U16_t16_e32_dpp_gfx12
    UINT64_C(2105147392), UINT64_C(0),	// V_CMPX_NE_U16_t16_e32_gfx11
    UINT64_C(2105147392), UINT64_C(0),	// V_CMPX_NE_U16_t16_e32_gfx12
    UINT64_C(3569156096), UINT64_C(0),	// V_CMPX_NE_U16_t16_e64_dpp8_gfx11
    UINT64_C(3569156096), UINT64_C(0),	// V_CMPX_NE_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077310980096), UINT64_C(0),	// V_CMPX_NE_U16_t16_e64_dpp_gfx11
    UINT64_C(1077310980096), UINT64_C(0),	// V_CMPX_NE_U16_t16_e64_dpp_gfx12
    UINT64_C(3569156096), UINT64_C(0),	// V_CMPX_NE_U16_t16_e64_gfx11
    UINT64_C(3569156096), UINT64_C(0),	// V_CMPX_NE_U16_t16_e64_gfx12
    UINT64_C(2107244544), UINT64_C(0),	// V_CMPX_NE_U32_e32_dpp8_gfx11
    UINT64_C(2107244544), UINT64_C(0),	// V_CMPX_NE_U32_e32_dpp8_gfx12
    UINT64_C(2107244794), UINT64_C(0),	// V_CMPX_NE_U32_e32_dpp_gfx11
    UINT64_C(2107244794), UINT64_C(0),	// V_CMPX_NE_U32_e32_dpp_gfx12
    UINT64_C(2108293120), UINT64_C(0),	// V_CMPX_NE_U32_e32_gfx10
    UINT64_C(2107244544), UINT64_C(0),	// V_CMPX_NE_U32_e32_gfx11
    UINT64_C(2107244544), UINT64_C(0),	// V_CMPX_NE_U32_e32_gfx12
    UINT64_C(2108293120), UINT64_C(0),	// V_CMPX_NE_U32_e32_gfx6_gfx7
    UINT64_C(2109341696), UINT64_C(0),	// V_CMPX_NE_U32_e32_vi
    UINT64_C(3570204672), UINT64_C(0),	// V_CMPX_NE_U32_e64_dpp8_gfx11
    UINT64_C(3570204672), UINT64_C(0),	// V_CMPX_NE_U32_e64_dpp8_gfx12
    UINT64_C(1077312028672), UINT64_C(0),	// V_CMPX_NE_U32_e64_dpp_gfx11
    UINT64_C(1077312028672), UINT64_C(0),	// V_CMPX_NE_U32_e64_dpp_gfx12
    UINT64_C(3570728960), UINT64_C(0),	// V_CMPX_NE_U32_e64_gfx10
    UINT64_C(3570204672), UINT64_C(0),	// V_CMPX_NE_U32_e64_gfx11
    UINT64_C(3570204672), UINT64_C(0),	// V_CMPX_NE_U32_e64_gfx12
    UINT64_C(3517579264), UINT64_C(0),	// V_CMPX_NE_U32_e64_gfx6_gfx7
    UINT64_C(3504144384), UINT64_C(0),	// V_CMPX_NE_U32_e64_vi
    UINT64_C(2108293369), UINT64_C(0),	// V_CMPX_NE_U32_sdwa_gfx10
    UINT64_C(2109341945), UINT64_C(0),	// V_CMPX_NE_U32_sdwa_gfx9
    UINT64_C(2109341945), UINT64_C(0),	// V_CMPX_NE_U32_sdwa_vi
    UINT64_C(2112487424), UINT64_C(0),	// V_CMPX_NE_U64_e32_gfx10
    UINT64_C(2109341696), UINT64_C(0),	// V_CMPX_NE_U64_e32_gfx11
    UINT64_C(2109341696), UINT64_C(0),	// V_CMPX_NE_U64_e32_gfx12
    UINT64_C(2112487424), UINT64_C(0),	// V_CMPX_NE_U64_e32_gfx6_gfx7
    UINT64_C(2113536000), UINT64_C(0),	// V_CMPX_NE_U64_e32_vi
    UINT64_C(3572826112), UINT64_C(0),	// V_CMPX_NE_U64_e64_gfx10
    UINT64_C(3571253248), UINT64_C(0),	// V_CMPX_NE_U64_e64_gfx11
    UINT64_C(3571253248), UINT64_C(0),	// V_CMPX_NE_U64_e64_gfx12
    UINT64_C(3521773568), UINT64_C(0),	// V_CMPX_NE_U64_e64_gfx6_gfx7
    UINT64_C(3506241536), UINT64_C(0),	// V_CMPX_NE_U64_e64_vi
    UINT64_C(2113011712), UINT64_C(0),	// V_CMPX_NGE_F16_e32_gfx10
    UINT64_C(2087845888), UINT64_C(0),	// V_CMPX_NGE_F16_e32_vi
    UINT64_C(3573088256), UINT64_C(0),	// V_CMPX_NGE_F16_e64_gfx10
    UINT64_C(3493396480), UINT64_C(0),	// V_CMPX_NGE_F16_e64_vi
    UINT64_C(2098331648), UINT64_C(0),	// V_CMPX_NGE_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2098331648), UINT64_C(0),	// V_CMPX_NGE_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2098331898), UINT64_C(0),	// V_CMPX_NGE_F16_fake16_e32_dpp_gfx11
    UINT64_C(2098331898), UINT64_C(0),	// V_CMPX_NGE_F16_fake16_e32_dpp_gfx12
    UINT64_C(2098331648), UINT64_C(0),	// V_CMPX_NGE_F16_fake16_e32_gfx11
    UINT64_C(2098331648), UINT64_C(0),	// V_CMPX_NGE_F16_fake16_e32_gfx12
    UINT64_C(3565748224), UINT64_C(0),	// V_CMPX_NGE_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3565748224), UINT64_C(0),	// V_CMPX_NGE_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077307572224), UINT64_C(0),	// V_CMPX_NGE_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077307572224), UINT64_C(0),	// V_CMPX_NGE_F16_fake16_e64_dpp_gfx12
    UINT64_C(3565748224), UINT64_C(0),	// V_CMPX_NGE_F16_fake16_e64_gfx11
    UINT64_C(3565748224), UINT64_C(0),	// V_CMPX_NGE_F16_fake16_e64_gfx12
    UINT64_C(2113011961), UINT64_C(0),	// V_CMPX_NGE_F16_sdwa_gfx10
    UINT64_C(2087846137), UINT64_C(0),	// V_CMPX_NGE_F16_sdwa_gfx9
    UINT64_C(2087846137), UINT64_C(0),	// V_CMPX_NGE_F16_sdwa_vi
    UINT64_C(2098331648), UINT64_C(0),	// V_CMPX_NGE_F16_t16_e32_dpp8_gfx11
    UINT64_C(2098331648), UINT64_C(0),	// V_CMPX_NGE_F16_t16_e32_dpp8_gfx12
    UINT64_C(2098331898), UINT64_C(0),	// V_CMPX_NGE_F16_t16_e32_dpp_gfx11
    UINT64_C(2098331898), UINT64_C(0),	// V_CMPX_NGE_F16_t16_e32_dpp_gfx12
    UINT64_C(2098331648), UINT64_C(0),	// V_CMPX_NGE_F16_t16_e32_gfx11
    UINT64_C(2098331648), UINT64_C(0),	// V_CMPX_NGE_F16_t16_e32_gfx12
    UINT64_C(3565748224), UINT64_C(0),	// V_CMPX_NGE_F16_t16_e64_dpp8_gfx11
    UINT64_C(3565748224), UINT64_C(0),	// V_CMPX_NGE_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077307572224), UINT64_C(0),	// V_CMPX_NGE_F16_t16_e64_dpp_gfx11
    UINT64_C(1077307572224), UINT64_C(0),	// V_CMPX_NGE_F16_t16_e64_dpp_gfx12
    UINT64_C(3565748224), UINT64_C(0),	// V_CMPX_NGE_F16_t16_e64_gfx11
    UINT64_C(3565748224), UINT64_C(0),	// V_CMPX_NGE_F16_t16_e64_gfx12
    UINT64_C(2100428800), UINT64_C(0),	// V_CMPX_NGE_F32_e32_dpp8_gfx11
    UINT64_C(2100428800), UINT64_C(0),	// V_CMPX_NGE_F32_e32_dpp8_gfx12
    UINT64_C(2100429050), UINT64_C(0),	// V_CMPX_NGE_F32_e32_dpp_gfx11
    UINT64_C(2100429050), UINT64_C(0),	// V_CMPX_NGE_F32_e32_dpp_gfx12
    UINT64_C(2083651584), UINT64_C(0),	// V_CMPX_NGE_F32_e32_gfx10
    UINT64_C(2100428800), UINT64_C(0),	// V_CMPX_NGE_F32_e32_gfx11
    UINT64_C(2100428800), UINT64_C(0),	// V_CMPX_NGE_F32_e32_gfx12
    UINT64_C(2083651584), UINT64_C(0),	// V_CMPX_NGE_F32_e32_gfx6_gfx7
    UINT64_C(2092040192), UINT64_C(0),	// V_CMPX_NGE_F32_e32_vi
    UINT64_C(3566796800), UINT64_C(0),	// V_CMPX_NGE_F32_e64_dpp8_gfx11
    UINT64_C(3566796800), UINT64_C(0),	// V_CMPX_NGE_F32_e64_dpp8_gfx12
    UINT64_C(1077308620800), UINT64_C(0),	// V_CMPX_NGE_F32_e64_dpp_gfx11
    UINT64_C(1077308620800), UINT64_C(0),	// V_CMPX_NGE_F32_e64_dpp_gfx12
    UINT64_C(3558408192), UINT64_C(0),	// V_CMPX_NGE_F32_e64_gfx10
    UINT64_C(3566796800), UINT64_C(0),	// V_CMPX_NGE_F32_e64_gfx11
    UINT64_C(3566796800), UINT64_C(0),	// V_CMPX_NGE_F32_e64_gfx12
    UINT64_C(3492937728), UINT64_C(0),	// V_CMPX_NGE_F32_e64_gfx6_gfx7
    UINT64_C(3495493632), UINT64_C(0),	// V_CMPX_NGE_F32_e64_vi
    UINT64_C(2083651833), UINT64_C(0),	// V_CMPX_NGE_F32_sdwa_gfx10
    UINT64_C(2092040441), UINT64_C(0),	// V_CMPX_NGE_F32_sdwa_gfx9
    UINT64_C(2092040441), UINT64_C(0),	// V_CMPX_NGE_F32_sdwa_vi
    UINT64_C(2087845888), UINT64_C(0),	// V_CMPX_NGE_F64_e32_gfx10
    UINT64_C(2102525952), UINT64_C(0),	// V_CMPX_NGE_F64_e32_gfx11
    UINT64_C(2102525952), UINT64_C(0),	// V_CMPX_NGE_F64_e32_gfx12
    UINT64_C(2087845888), UINT64_C(0),	// V_CMPX_NGE_F64_e32_gfx6_gfx7
    UINT64_C(2096234496), UINT64_C(0),	// V_CMPX_NGE_F64_e32_vi
    UINT64_C(3560505344), UINT64_C(0),	// V_CMPX_NGE_F64_e64_gfx10
    UINT64_C(3567845376), UINT64_C(0),	// V_CMPX_NGE_F64_e64_gfx11
    UINT64_C(3567845376), UINT64_C(0),	// V_CMPX_NGE_F64_e64_gfx12
    UINT64_C(3497132032), UINT64_C(0),	// V_CMPX_NGE_F64_e64_gfx6_gfx7
    UINT64_C(3497590784), UINT64_C(0),	// V_CMPX_NGE_F64_e64_vi
    UINT64_C(2113273856), UINT64_C(0),	// V_CMPX_NGT_F16_e32_gfx10
    UINT64_C(2088108032), UINT64_C(0),	// V_CMPX_NGT_F16_e32_vi
    UINT64_C(3573219328), UINT64_C(0),	// V_CMPX_NGT_F16_e64_gfx10
    UINT64_C(3493527552), UINT64_C(0),	// V_CMPX_NGT_F16_e64_vi
    UINT64_C(2098593792), UINT64_C(0),	// V_CMPX_NGT_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2098593792), UINT64_C(0),	// V_CMPX_NGT_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2098594042), UINT64_C(0),	// V_CMPX_NGT_F16_fake16_e32_dpp_gfx11
    UINT64_C(2098594042), UINT64_C(0),	// V_CMPX_NGT_F16_fake16_e32_dpp_gfx12
    UINT64_C(2098593792), UINT64_C(0),	// V_CMPX_NGT_F16_fake16_e32_gfx11
    UINT64_C(2098593792), UINT64_C(0),	// V_CMPX_NGT_F16_fake16_e32_gfx12
    UINT64_C(3565879296), UINT64_C(0),	// V_CMPX_NGT_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3565879296), UINT64_C(0),	// V_CMPX_NGT_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077307703296), UINT64_C(0),	// V_CMPX_NGT_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077307703296), UINT64_C(0),	// V_CMPX_NGT_F16_fake16_e64_dpp_gfx12
    UINT64_C(3565879296), UINT64_C(0),	// V_CMPX_NGT_F16_fake16_e64_gfx11
    UINT64_C(3565879296), UINT64_C(0),	// V_CMPX_NGT_F16_fake16_e64_gfx12
    UINT64_C(2113274105), UINT64_C(0),	// V_CMPX_NGT_F16_sdwa_gfx10
    UINT64_C(2088108281), UINT64_C(0),	// V_CMPX_NGT_F16_sdwa_gfx9
    UINT64_C(2088108281), UINT64_C(0),	// V_CMPX_NGT_F16_sdwa_vi
    UINT64_C(2098593792), UINT64_C(0),	// V_CMPX_NGT_F16_t16_e32_dpp8_gfx11
    UINT64_C(2098593792), UINT64_C(0),	// V_CMPX_NGT_F16_t16_e32_dpp8_gfx12
    UINT64_C(2098594042), UINT64_C(0),	// V_CMPX_NGT_F16_t16_e32_dpp_gfx11
    UINT64_C(2098594042), UINT64_C(0),	// V_CMPX_NGT_F16_t16_e32_dpp_gfx12
    UINT64_C(2098593792), UINT64_C(0),	// V_CMPX_NGT_F16_t16_e32_gfx11
    UINT64_C(2098593792), UINT64_C(0),	// V_CMPX_NGT_F16_t16_e32_gfx12
    UINT64_C(3565879296), UINT64_C(0),	// V_CMPX_NGT_F16_t16_e64_dpp8_gfx11
    UINT64_C(3565879296), UINT64_C(0),	// V_CMPX_NGT_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077307703296), UINT64_C(0),	// V_CMPX_NGT_F16_t16_e64_dpp_gfx11
    UINT64_C(1077307703296), UINT64_C(0),	// V_CMPX_NGT_F16_t16_e64_dpp_gfx12
    UINT64_C(3565879296), UINT64_C(0),	// V_CMPX_NGT_F16_t16_e64_gfx11
    UINT64_C(3565879296), UINT64_C(0),	// V_CMPX_NGT_F16_t16_e64_gfx12
    UINT64_C(2100690944), UINT64_C(0),	// V_CMPX_NGT_F32_e32_dpp8_gfx11
    UINT64_C(2100690944), UINT64_C(0),	// V_CMPX_NGT_F32_e32_dpp8_gfx12
    UINT64_C(2100691194), UINT64_C(0),	// V_CMPX_NGT_F32_e32_dpp_gfx11
    UINT64_C(2100691194), UINT64_C(0),	// V_CMPX_NGT_F32_e32_dpp_gfx12
    UINT64_C(2083913728), UINT64_C(0),	// V_CMPX_NGT_F32_e32_gfx10
    UINT64_C(2100690944), UINT64_C(0),	// V_CMPX_NGT_F32_e32_gfx11
    UINT64_C(2100690944), UINT64_C(0),	// V_CMPX_NGT_F32_e32_gfx12
    UINT64_C(2083913728), UINT64_C(0),	// V_CMPX_NGT_F32_e32_gfx6_gfx7
    UINT64_C(2092302336), UINT64_C(0),	// V_CMPX_NGT_F32_e32_vi
    UINT64_C(3566927872), UINT64_C(0),	// V_CMPX_NGT_F32_e64_dpp8_gfx11
    UINT64_C(3566927872), UINT64_C(0),	// V_CMPX_NGT_F32_e64_dpp8_gfx12
    UINT64_C(1077308751872), UINT64_C(0),	// V_CMPX_NGT_F32_e64_dpp_gfx11
    UINT64_C(1077308751872), UINT64_C(0),	// V_CMPX_NGT_F32_e64_dpp_gfx12
    UINT64_C(3558539264), UINT64_C(0),	// V_CMPX_NGT_F32_e64_gfx10
    UINT64_C(3566927872), UINT64_C(0),	// V_CMPX_NGT_F32_e64_gfx11
    UINT64_C(3566927872), UINT64_C(0),	// V_CMPX_NGT_F32_e64_gfx12
    UINT64_C(3493199872), UINT64_C(0),	// V_CMPX_NGT_F32_e64_gfx6_gfx7
    UINT64_C(3495624704), UINT64_C(0),	// V_CMPX_NGT_F32_e64_vi
    UINT64_C(2083913977), UINT64_C(0),	// V_CMPX_NGT_F32_sdwa_gfx10
    UINT64_C(2092302585), UINT64_C(0),	// V_CMPX_NGT_F32_sdwa_gfx9
    UINT64_C(2092302585), UINT64_C(0),	// V_CMPX_NGT_F32_sdwa_vi
    UINT64_C(2088108032), UINT64_C(0),	// V_CMPX_NGT_F64_e32_gfx10
    UINT64_C(2102788096), UINT64_C(0),	// V_CMPX_NGT_F64_e32_gfx11
    UINT64_C(2102788096), UINT64_C(0),	// V_CMPX_NGT_F64_e32_gfx12
    UINT64_C(2088108032), UINT64_C(0),	// V_CMPX_NGT_F64_e32_gfx6_gfx7
    UINT64_C(2096496640), UINT64_C(0),	// V_CMPX_NGT_F64_e32_vi
    UINT64_C(3560636416), UINT64_C(0),	// V_CMPX_NGT_F64_e64_gfx10
    UINT64_C(3567976448), UINT64_C(0),	// V_CMPX_NGT_F64_e64_gfx11
    UINT64_C(3567976448), UINT64_C(0),	// V_CMPX_NGT_F64_e64_gfx12
    UINT64_C(3497394176), UINT64_C(0),	// V_CMPX_NGT_F64_e64_gfx6_gfx7
    UINT64_C(3497721856), UINT64_C(0),	// V_CMPX_NGT_F64_e64_vi
    UINT64_C(2113404928), UINT64_C(0),	// V_CMPX_NLE_F16_e32_gfx10
    UINT64_C(2088239104), UINT64_C(0),	// V_CMPX_NLE_F16_e32_vi
    UINT64_C(3573284864), UINT64_C(0),	// V_CMPX_NLE_F16_e64_gfx10
    UINT64_C(3493593088), UINT64_C(0),	// V_CMPX_NLE_F16_e64_vi
    UINT64_C(2098724864), UINT64_C(0),	// V_CMPX_NLE_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2098724864), UINT64_C(0),	// V_CMPX_NLE_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2098725114), UINT64_C(0),	// V_CMPX_NLE_F16_fake16_e32_dpp_gfx11
    UINT64_C(2098725114), UINT64_C(0),	// V_CMPX_NLE_F16_fake16_e32_dpp_gfx12
    UINT64_C(2098724864), UINT64_C(0),	// V_CMPX_NLE_F16_fake16_e32_gfx11
    UINT64_C(2098724864), UINT64_C(0),	// V_CMPX_NLE_F16_fake16_e32_gfx12
    UINT64_C(3565944832), UINT64_C(0),	// V_CMPX_NLE_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3565944832), UINT64_C(0),	// V_CMPX_NLE_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077307768832), UINT64_C(0),	// V_CMPX_NLE_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077307768832), UINT64_C(0),	// V_CMPX_NLE_F16_fake16_e64_dpp_gfx12
    UINT64_C(3565944832), UINT64_C(0),	// V_CMPX_NLE_F16_fake16_e64_gfx11
    UINT64_C(3565944832), UINT64_C(0),	// V_CMPX_NLE_F16_fake16_e64_gfx12
    UINT64_C(2113405177), UINT64_C(0),	// V_CMPX_NLE_F16_sdwa_gfx10
    UINT64_C(2088239353), UINT64_C(0),	// V_CMPX_NLE_F16_sdwa_gfx9
    UINT64_C(2088239353), UINT64_C(0),	// V_CMPX_NLE_F16_sdwa_vi
    UINT64_C(2098724864), UINT64_C(0),	// V_CMPX_NLE_F16_t16_e32_dpp8_gfx11
    UINT64_C(2098724864), UINT64_C(0),	// V_CMPX_NLE_F16_t16_e32_dpp8_gfx12
    UINT64_C(2098725114), UINT64_C(0),	// V_CMPX_NLE_F16_t16_e32_dpp_gfx11
    UINT64_C(2098725114), UINT64_C(0),	// V_CMPX_NLE_F16_t16_e32_dpp_gfx12
    UINT64_C(2098724864), UINT64_C(0),	// V_CMPX_NLE_F16_t16_e32_gfx11
    UINT64_C(2098724864), UINT64_C(0),	// V_CMPX_NLE_F16_t16_e32_gfx12
    UINT64_C(3565944832), UINT64_C(0),	// V_CMPX_NLE_F16_t16_e64_dpp8_gfx11
    UINT64_C(3565944832), UINT64_C(0),	// V_CMPX_NLE_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077307768832), UINT64_C(0),	// V_CMPX_NLE_F16_t16_e64_dpp_gfx11
    UINT64_C(1077307768832), UINT64_C(0),	// V_CMPX_NLE_F16_t16_e64_dpp_gfx12
    UINT64_C(3565944832), UINT64_C(0),	// V_CMPX_NLE_F16_t16_e64_gfx11
    UINT64_C(3565944832), UINT64_C(0),	// V_CMPX_NLE_F16_t16_e64_gfx12
    UINT64_C(2100822016), UINT64_C(0),	// V_CMPX_NLE_F32_e32_dpp8_gfx11
    UINT64_C(2100822016), UINT64_C(0),	// V_CMPX_NLE_F32_e32_dpp8_gfx12
    UINT64_C(2100822266), UINT64_C(0),	// V_CMPX_NLE_F32_e32_dpp_gfx11
    UINT64_C(2100822266), UINT64_C(0),	// V_CMPX_NLE_F32_e32_dpp_gfx12
    UINT64_C(2084044800), UINT64_C(0),	// V_CMPX_NLE_F32_e32_gfx10
    UINT64_C(2100822016), UINT64_C(0),	// V_CMPX_NLE_F32_e32_gfx11
    UINT64_C(2100822016), UINT64_C(0),	// V_CMPX_NLE_F32_e32_gfx12
    UINT64_C(2084044800), UINT64_C(0),	// V_CMPX_NLE_F32_e32_gfx6_gfx7
    UINT64_C(2092433408), UINT64_C(0),	// V_CMPX_NLE_F32_e32_vi
    UINT64_C(3566993408), UINT64_C(0),	// V_CMPX_NLE_F32_e64_dpp8_gfx11
    UINT64_C(3566993408), UINT64_C(0),	// V_CMPX_NLE_F32_e64_dpp8_gfx12
    UINT64_C(1077308817408), UINT64_C(0),	// V_CMPX_NLE_F32_e64_dpp_gfx11
    UINT64_C(1077308817408), UINT64_C(0),	// V_CMPX_NLE_F32_e64_dpp_gfx12
    UINT64_C(3558604800), UINT64_C(0),	// V_CMPX_NLE_F32_e64_gfx10
    UINT64_C(3566993408), UINT64_C(0),	// V_CMPX_NLE_F32_e64_gfx11
    UINT64_C(3566993408), UINT64_C(0),	// V_CMPX_NLE_F32_e64_gfx12
    UINT64_C(3493330944), UINT64_C(0),	// V_CMPX_NLE_F32_e64_gfx6_gfx7
    UINT64_C(3495690240), UINT64_C(0),	// V_CMPX_NLE_F32_e64_vi
    UINT64_C(2084045049), UINT64_C(0),	// V_CMPX_NLE_F32_sdwa_gfx10
    UINT64_C(2092433657), UINT64_C(0),	// V_CMPX_NLE_F32_sdwa_gfx9
    UINT64_C(2092433657), UINT64_C(0),	// V_CMPX_NLE_F32_sdwa_vi
    UINT64_C(2088239104), UINT64_C(0),	// V_CMPX_NLE_F64_e32_gfx10
    UINT64_C(2102919168), UINT64_C(0),	// V_CMPX_NLE_F64_e32_gfx11
    UINT64_C(2102919168), UINT64_C(0),	// V_CMPX_NLE_F64_e32_gfx12
    UINT64_C(2088239104), UINT64_C(0),	// V_CMPX_NLE_F64_e32_gfx6_gfx7
    UINT64_C(2096627712), UINT64_C(0),	// V_CMPX_NLE_F64_e32_vi
    UINT64_C(3560701952), UINT64_C(0),	// V_CMPX_NLE_F64_e64_gfx10
    UINT64_C(3568041984), UINT64_C(0),	// V_CMPX_NLE_F64_e64_gfx11
    UINT64_C(3568041984), UINT64_C(0),	// V_CMPX_NLE_F64_e64_gfx12
    UINT64_C(3497525248), UINT64_C(0),	// V_CMPX_NLE_F64_e64_gfx6_gfx7
    UINT64_C(3497787392), UINT64_C(0),	// V_CMPX_NLE_F64_e64_vi
    UINT64_C(2113142784), UINT64_C(0),	// V_CMPX_NLG_F16_e32_gfx10
    UINT64_C(2087976960), UINT64_C(0),	// V_CMPX_NLG_F16_e32_vi
    UINT64_C(3573153792), UINT64_C(0),	// V_CMPX_NLG_F16_e64_gfx10
    UINT64_C(3493462016), UINT64_C(0),	// V_CMPX_NLG_F16_e64_vi
    UINT64_C(2098462720), UINT64_C(0),	// V_CMPX_NLG_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2098462720), UINT64_C(0),	// V_CMPX_NLG_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2098462970), UINT64_C(0),	// V_CMPX_NLG_F16_fake16_e32_dpp_gfx11
    UINT64_C(2098462970), UINT64_C(0),	// V_CMPX_NLG_F16_fake16_e32_dpp_gfx12
    UINT64_C(2098462720), UINT64_C(0),	// V_CMPX_NLG_F16_fake16_e32_gfx11
    UINT64_C(2098462720), UINT64_C(0),	// V_CMPX_NLG_F16_fake16_e32_gfx12
    UINT64_C(3565813760), UINT64_C(0),	// V_CMPX_NLG_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3565813760), UINT64_C(0),	// V_CMPX_NLG_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077307637760), UINT64_C(0),	// V_CMPX_NLG_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077307637760), UINT64_C(0),	// V_CMPX_NLG_F16_fake16_e64_dpp_gfx12
    UINT64_C(3565813760), UINT64_C(0),	// V_CMPX_NLG_F16_fake16_e64_gfx11
    UINT64_C(3565813760), UINT64_C(0),	// V_CMPX_NLG_F16_fake16_e64_gfx12
    UINT64_C(2113143033), UINT64_C(0),	// V_CMPX_NLG_F16_sdwa_gfx10
    UINT64_C(2087977209), UINT64_C(0),	// V_CMPX_NLG_F16_sdwa_gfx9
    UINT64_C(2087977209), UINT64_C(0),	// V_CMPX_NLG_F16_sdwa_vi
    UINT64_C(2098462720), UINT64_C(0),	// V_CMPX_NLG_F16_t16_e32_dpp8_gfx11
    UINT64_C(2098462720), UINT64_C(0),	// V_CMPX_NLG_F16_t16_e32_dpp8_gfx12
    UINT64_C(2098462970), UINT64_C(0),	// V_CMPX_NLG_F16_t16_e32_dpp_gfx11
    UINT64_C(2098462970), UINT64_C(0),	// V_CMPX_NLG_F16_t16_e32_dpp_gfx12
    UINT64_C(2098462720), UINT64_C(0),	// V_CMPX_NLG_F16_t16_e32_gfx11
    UINT64_C(2098462720), UINT64_C(0),	// V_CMPX_NLG_F16_t16_e32_gfx12
    UINT64_C(3565813760), UINT64_C(0),	// V_CMPX_NLG_F16_t16_e64_dpp8_gfx11
    UINT64_C(3565813760), UINT64_C(0),	// V_CMPX_NLG_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077307637760), UINT64_C(0),	// V_CMPX_NLG_F16_t16_e64_dpp_gfx11
    UINT64_C(1077307637760), UINT64_C(0),	// V_CMPX_NLG_F16_t16_e64_dpp_gfx12
    UINT64_C(3565813760), UINT64_C(0),	// V_CMPX_NLG_F16_t16_e64_gfx11
    UINT64_C(3565813760), UINT64_C(0),	// V_CMPX_NLG_F16_t16_e64_gfx12
    UINT64_C(2100559872), UINT64_C(0),	// V_CMPX_NLG_F32_e32_dpp8_gfx11
    UINT64_C(2100559872), UINT64_C(0),	// V_CMPX_NLG_F32_e32_dpp8_gfx12
    UINT64_C(2100560122), UINT64_C(0),	// V_CMPX_NLG_F32_e32_dpp_gfx11
    UINT64_C(2100560122), UINT64_C(0),	// V_CMPX_NLG_F32_e32_dpp_gfx12
    UINT64_C(2083782656), UINT64_C(0),	// V_CMPX_NLG_F32_e32_gfx10
    UINT64_C(2100559872), UINT64_C(0),	// V_CMPX_NLG_F32_e32_gfx11
    UINT64_C(2100559872), UINT64_C(0),	// V_CMPX_NLG_F32_e32_gfx12
    UINT64_C(2083782656), UINT64_C(0),	// V_CMPX_NLG_F32_e32_gfx6_gfx7
    UINT64_C(2092171264), UINT64_C(0),	// V_CMPX_NLG_F32_e32_vi
    UINT64_C(3566862336), UINT64_C(0),	// V_CMPX_NLG_F32_e64_dpp8_gfx11
    UINT64_C(3566862336), UINT64_C(0),	// V_CMPX_NLG_F32_e64_dpp8_gfx12
    UINT64_C(1077308686336), UINT64_C(0),	// V_CMPX_NLG_F32_e64_dpp_gfx11
    UINT64_C(1077308686336), UINT64_C(0),	// V_CMPX_NLG_F32_e64_dpp_gfx12
    UINT64_C(3558473728), UINT64_C(0),	// V_CMPX_NLG_F32_e64_gfx10
    UINT64_C(3566862336), UINT64_C(0),	// V_CMPX_NLG_F32_e64_gfx11
    UINT64_C(3566862336), UINT64_C(0),	// V_CMPX_NLG_F32_e64_gfx12
    UINT64_C(3493068800), UINT64_C(0),	// V_CMPX_NLG_F32_e64_gfx6_gfx7
    UINT64_C(3495559168), UINT64_C(0),	// V_CMPX_NLG_F32_e64_vi
    UINT64_C(2083782905), UINT64_C(0),	// V_CMPX_NLG_F32_sdwa_gfx10
    UINT64_C(2092171513), UINT64_C(0),	// V_CMPX_NLG_F32_sdwa_gfx9
    UINT64_C(2092171513), UINT64_C(0),	// V_CMPX_NLG_F32_sdwa_vi
    UINT64_C(2087976960), UINT64_C(0),	// V_CMPX_NLG_F64_e32_gfx10
    UINT64_C(2102657024), UINT64_C(0),	// V_CMPX_NLG_F64_e32_gfx11
    UINT64_C(2102657024), UINT64_C(0),	// V_CMPX_NLG_F64_e32_gfx12
    UINT64_C(2087976960), UINT64_C(0),	// V_CMPX_NLG_F64_e32_gfx6_gfx7
    UINT64_C(2096365568), UINT64_C(0),	// V_CMPX_NLG_F64_e32_vi
    UINT64_C(3560570880), UINT64_C(0),	// V_CMPX_NLG_F64_e64_gfx10
    UINT64_C(3567910912), UINT64_C(0),	// V_CMPX_NLG_F64_e64_gfx11
    UINT64_C(3567910912), UINT64_C(0),	// V_CMPX_NLG_F64_e64_gfx12
    UINT64_C(3497263104), UINT64_C(0),	// V_CMPX_NLG_F64_e64_gfx6_gfx7
    UINT64_C(3497656320), UINT64_C(0),	// V_CMPX_NLG_F64_e64_vi
    UINT64_C(2113667072), UINT64_C(0),	// V_CMPX_NLT_F16_e32_gfx10
    UINT64_C(2088501248), UINT64_C(0),	// V_CMPX_NLT_F16_e32_vi
    UINT64_C(3573415936), UINT64_C(0),	// V_CMPX_NLT_F16_e64_gfx10
    UINT64_C(3493724160), UINT64_C(0),	// V_CMPX_NLT_F16_e64_vi
    UINT64_C(2098987008), UINT64_C(0),	// V_CMPX_NLT_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2098987008), UINT64_C(0),	// V_CMPX_NLT_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2098987258), UINT64_C(0),	// V_CMPX_NLT_F16_fake16_e32_dpp_gfx11
    UINT64_C(2098987258), UINT64_C(0),	// V_CMPX_NLT_F16_fake16_e32_dpp_gfx12
    UINT64_C(2098987008), UINT64_C(0),	// V_CMPX_NLT_F16_fake16_e32_gfx11
    UINT64_C(2098987008), UINT64_C(0),	// V_CMPX_NLT_F16_fake16_e32_gfx12
    UINT64_C(3566075904), UINT64_C(0),	// V_CMPX_NLT_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3566075904), UINT64_C(0),	// V_CMPX_NLT_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077307899904), UINT64_C(0),	// V_CMPX_NLT_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077307899904), UINT64_C(0),	// V_CMPX_NLT_F16_fake16_e64_dpp_gfx12
    UINT64_C(3566075904), UINT64_C(0),	// V_CMPX_NLT_F16_fake16_e64_gfx11
    UINT64_C(3566075904), UINT64_C(0),	// V_CMPX_NLT_F16_fake16_e64_gfx12
    UINT64_C(2113667321), UINT64_C(0),	// V_CMPX_NLT_F16_sdwa_gfx10
    UINT64_C(2088501497), UINT64_C(0),	// V_CMPX_NLT_F16_sdwa_gfx9
    UINT64_C(2088501497), UINT64_C(0),	// V_CMPX_NLT_F16_sdwa_vi
    UINT64_C(2098987008), UINT64_C(0),	// V_CMPX_NLT_F16_t16_e32_dpp8_gfx11
    UINT64_C(2098987008), UINT64_C(0),	// V_CMPX_NLT_F16_t16_e32_dpp8_gfx12
    UINT64_C(2098987258), UINT64_C(0),	// V_CMPX_NLT_F16_t16_e32_dpp_gfx11
    UINT64_C(2098987258), UINT64_C(0),	// V_CMPX_NLT_F16_t16_e32_dpp_gfx12
    UINT64_C(2098987008), UINT64_C(0),	// V_CMPX_NLT_F16_t16_e32_gfx11
    UINT64_C(2098987008), UINT64_C(0),	// V_CMPX_NLT_F16_t16_e32_gfx12
    UINT64_C(3566075904), UINT64_C(0),	// V_CMPX_NLT_F16_t16_e64_dpp8_gfx11
    UINT64_C(3566075904), UINT64_C(0),	// V_CMPX_NLT_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077307899904), UINT64_C(0),	// V_CMPX_NLT_F16_t16_e64_dpp_gfx11
    UINT64_C(1077307899904), UINT64_C(0),	// V_CMPX_NLT_F16_t16_e64_dpp_gfx12
    UINT64_C(3566075904), UINT64_C(0),	// V_CMPX_NLT_F16_t16_e64_gfx11
    UINT64_C(3566075904), UINT64_C(0),	// V_CMPX_NLT_F16_t16_e64_gfx12
    UINT64_C(2101084160), UINT64_C(0),	// V_CMPX_NLT_F32_e32_dpp8_gfx11
    UINT64_C(2101084160), UINT64_C(0),	// V_CMPX_NLT_F32_e32_dpp8_gfx12
    UINT64_C(2101084410), UINT64_C(0),	// V_CMPX_NLT_F32_e32_dpp_gfx11
    UINT64_C(2101084410), UINT64_C(0),	// V_CMPX_NLT_F32_e32_dpp_gfx12
    UINT64_C(2084306944), UINT64_C(0),	// V_CMPX_NLT_F32_e32_gfx10
    UINT64_C(2101084160), UINT64_C(0),	// V_CMPX_NLT_F32_e32_gfx11
    UINT64_C(2101084160), UINT64_C(0),	// V_CMPX_NLT_F32_e32_gfx12
    UINT64_C(2084306944), UINT64_C(0),	// V_CMPX_NLT_F32_e32_gfx6_gfx7
    UINT64_C(2092695552), UINT64_C(0),	// V_CMPX_NLT_F32_e32_vi
    UINT64_C(3567124480), UINT64_C(0),	// V_CMPX_NLT_F32_e64_dpp8_gfx11
    UINT64_C(3567124480), UINT64_C(0),	// V_CMPX_NLT_F32_e64_dpp8_gfx12
    UINT64_C(1077308948480), UINT64_C(0),	// V_CMPX_NLT_F32_e64_dpp_gfx11
    UINT64_C(1077308948480), UINT64_C(0),	// V_CMPX_NLT_F32_e64_dpp_gfx12
    UINT64_C(3558735872), UINT64_C(0),	// V_CMPX_NLT_F32_e64_gfx10
    UINT64_C(3567124480), UINT64_C(0),	// V_CMPX_NLT_F32_e64_gfx11
    UINT64_C(3567124480), UINT64_C(0),	// V_CMPX_NLT_F32_e64_gfx12
    UINT64_C(3493593088), UINT64_C(0),	// V_CMPX_NLT_F32_e64_gfx6_gfx7
    UINT64_C(3495821312), UINT64_C(0),	// V_CMPX_NLT_F32_e64_vi
    UINT64_C(2084307193), UINT64_C(0),	// V_CMPX_NLT_F32_sdwa_gfx10
    UINT64_C(2092695801), UINT64_C(0),	// V_CMPX_NLT_F32_sdwa_gfx9
    UINT64_C(2092695801), UINT64_C(0),	// V_CMPX_NLT_F32_sdwa_vi
    UINT64_C(2088501248), UINT64_C(0),	// V_CMPX_NLT_F64_e32_gfx10
    UINT64_C(2103181312), UINT64_C(0),	// V_CMPX_NLT_F64_e32_gfx11
    UINT64_C(2103181312), UINT64_C(0),	// V_CMPX_NLT_F64_e32_gfx12
    UINT64_C(2088501248), UINT64_C(0),	// V_CMPX_NLT_F64_e32_gfx6_gfx7
    UINT64_C(2096889856), UINT64_C(0),	// V_CMPX_NLT_F64_e32_vi
    UINT64_C(3560833024), UINT64_C(0),	// V_CMPX_NLT_F64_e64_gfx10
    UINT64_C(3568173056), UINT64_C(0),	// V_CMPX_NLT_F64_e64_gfx11
    UINT64_C(3568173056), UINT64_C(0),	// V_CMPX_NLT_F64_e64_gfx12
    UINT64_C(3497787392), UINT64_C(0),	// V_CMPX_NLT_F64_e64_gfx6_gfx7
    UINT64_C(3497918464), UINT64_C(0),	// V_CMPX_NLT_F64_e64_vi
    UINT64_C(2109603840), UINT64_C(0),	// V_CMPX_O_F16_e32_gfx10
    UINT64_C(2087583744), UINT64_C(0),	// V_CMPX_O_F16_e32_vi
    UINT64_C(3571384320), UINT64_C(0),	// V_CMPX_O_F16_e64_gfx10
    UINT64_C(3493265408), UINT64_C(0),	// V_CMPX_O_F16_e64_vi
    UINT64_C(2098069504), UINT64_C(0),	// V_CMPX_O_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2098069504), UINT64_C(0),	// V_CMPX_O_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2098069754), UINT64_C(0),	// V_CMPX_O_F16_fake16_e32_dpp_gfx11
    UINT64_C(2098069754), UINT64_C(0),	// V_CMPX_O_F16_fake16_e32_dpp_gfx12
    UINT64_C(2098069504), UINT64_C(0),	// V_CMPX_O_F16_fake16_e32_gfx11
    UINT64_C(2098069504), UINT64_C(0),	// V_CMPX_O_F16_fake16_e32_gfx12
    UINT64_C(3565617152), UINT64_C(0),	// V_CMPX_O_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3565617152), UINT64_C(0),	// V_CMPX_O_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077307441152), UINT64_C(0),	// V_CMPX_O_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077307441152), UINT64_C(0),	// V_CMPX_O_F16_fake16_e64_dpp_gfx12
    UINT64_C(3565617152), UINT64_C(0),	// V_CMPX_O_F16_fake16_e64_gfx11
    UINT64_C(3565617152), UINT64_C(0),	// V_CMPX_O_F16_fake16_e64_gfx12
    UINT64_C(2109604089), UINT64_C(0),	// V_CMPX_O_F16_sdwa_gfx10
    UINT64_C(2087583993), UINT64_C(0),	// V_CMPX_O_F16_sdwa_gfx9
    UINT64_C(2087583993), UINT64_C(0),	// V_CMPX_O_F16_sdwa_vi
    UINT64_C(2098069504), UINT64_C(0),	// V_CMPX_O_F16_t16_e32_dpp8_gfx11
    UINT64_C(2098069504), UINT64_C(0),	// V_CMPX_O_F16_t16_e32_dpp8_gfx12
    UINT64_C(2098069754), UINT64_C(0),	// V_CMPX_O_F16_t16_e32_dpp_gfx11
    UINT64_C(2098069754), UINT64_C(0),	// V_CMPX_O_F16_t16_e32_dpp_gfx12
    UINT64_C(2098069504), UINT64_C(0),	// V_CMPX_O_F16_t16_e32_gfx11
    UINT64_C(2098069504), UINT64_C(0),	// V_CMPX_O_F16_t16_e32_gfx12
    UINT64_C(3565617152), UINT64_C(0),	// V_CMPX_O_F16_t16_e64_dpp8_gfx11
    UINT64_C(3565617152), UINT64_C(0),	// V_CMPX_O_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077307441152), UINT64_C(0),	// V_CMPX_O_F16_t16_e64_dpp_gfx11
    UINT64_C(1077307441152), UINT64_C(0),	// V_CMPX_O_F16_t16_e64_dpp_gfx12
    UINT64_C(3565617152), UINT64_C(0),	// V_CMPX_O_F16_t16_e64_gfx11
    UINT64_C(3565617152), UINT64_C(0),	// V_CMPX_O_F16_t16_e64_gfx12
    UINT64_C(2100166656), UINT64_C(0),	// V_CMPX_O_F32_e32_dpp8_gfx11
    UINT64_C(2100166656), UINT64_C(0),	// V_CMPX_O_F32_e32_dpp8_gfx12
    UINT64_C(2100166906), UINT64_C(0),	// V_CMPX_O_F32_e32_dpp_gfx11
    UINT64_C(2100166906), UINT64_C(0),	// V_CMPX_O_F32_e32_dpp_gfx12
    UINT64_C(2083389440), UINT64_C(0),	// V_CMPX_O_F32_e32_gfx10
    UINT64_C(2100166656), UINT64_C(0),	// V_CMPX_O_F32_e32_gfx11
    UINT64_C(2100166656), UINT64_C(0),	// V_CMPX_O_F32_e32_gfx12
    UINT64_C(2083389440), UINT64_C(0),	// V_CMPX_O_F32_e32_gfx6_gfx7
    UINT64_C(2091778048), UINT64_C(0),	// V_CMPX_O_F32_e32_vi
    UINT64_C(3566665728), UINT64_C(0),	// V_CMPX_O_F32_e64_dpp8_gfx11
    UINT64_C(3566665728), UINT64_C(0),	// V_CMPX_O_F32_e64_dpp8_gfx12
    UINT64_C(1077308489728), UINT64_C(0),	// V_CMPX_O_F32_e64_dpp_gfx11
    UINT64_C(1077308489728), UINT64_C(0),	// V_CMPX_O_F32_e64_dpp_gfx12
    UINT64_C(3558277120), UINT64_C(0),	// V_CMPX_O_F32_e64_gfx10
    UINT64_C(3566665728), UINT64_C(0),	// V_CMPX_O_F32_e64_gfx11
    UINT64_C(3566665728), UINT64_C(0),	// V_CMPX_O_F32_e64_gfx12
    UINT64_C(3492675584), UINT64_C(0),	// V_CMPX_O_F32_e64_gfx6_gfx7
    UINT64_C(3495362560), UINT64_C(0),	// V_CMPX_O_F32_e64_vi
    UINT64_C(2083389689), UINT64_C(0),	// V_CMPX_O_F32_sdwa_gfx10
    UINT64_C(2091778297), UINT64_C(0),	// V_CMPX_O_F32_sdwa_gfx9
    UINT64_C(2091778297), UINT64_C(0),	// V_CMPX_O_F32_sdwa_vi
    UINT64_C(2087583744), UINT64_C(0),	// V_CMPX_O_F64_e32_gfx10
    UINT64_C(2102263808), UINT64_C(0),	// V_CMPX_O_F64_e32_gfx11
    UINT64_C(2102263808), UINT64_C(0),	// V_CMPX_O_F64_e32_gfx12
    UINT64_C(2087583744), UINT64_C(0),	// V_CMPX_O_F64_e32_gfx6_gfx7
    UINT64_C(2095972352), UINT64_C(0),	// V_CMPX_O_F64_e32_vi
    UINT64_C(3560374272), UINT64_C(0),	// V_CMPX_O_F64_e64_gfx10
    UINT64_C(3567714304), UINT64_C(0),	// V_CMPX_O_F64_e64_gfx11
    UINT64_C(3567714304), UINT64_C(0),	// V_CMPX_O_F64_e64_gfx12
    UINT64_C(3496869888), UINT64_C(0),	// V_CMPX_O_F64_e64_gfx6_gfx7
    UINT64_C(3497459712), UINT64_C(0),	// V_CMPX_O_F64_e64_vi
    UINT64_C(2113798144), UINT64_C(0),	// V_CMPX_TRU_F16_e32_gfx10
    UINT64_C(2088632320), UINT64_C(0),	// V_CMPX_TRU_F16_e32_vi
    UINT64_C(3573481472), UINT64_C(0),	// V_CMPX_TRU_F16_e64_gfx10
    UINT64_C(3493789696), UINT64_C(0),	// V_CMPX_TRU_F16_e64_vi
    UINT64_C(2113798393), UINT64_C(0),	// V_CMPX_TRU_F16_sdwa_gfx10
    UINT64_C(2088632569), UINT64_C(0),	// V_CMPX_TRU_F16_sdwa_gfx9
    UINT64_C(2088632569), UINT64_C(0),	// V_CMPX_TRU_F16_sdwa_vi
    UINT64_C(2084438016), UINT64_C(0),	// V_CMPX_TRU_F32_e32_gfx10
    UINT64_C(2084438016), UINT64_C(0),	// V_CMPX_TRU_F32_e32_gfx6_gfx7
    UINT64_C(2092826624), UINT64_C(0),	// V_CMPX_TRU_F32_e32_vi
    UINT64_C(3558801408), UINT64_C(0),	// V_CMPX_TRU_F32_e64_gfx10
    UINT64_C(3493724160), UINT64_C(0),	// V_CMPX_TRU_F32_e64_gfx6_gfx7
    UINT64_C(3495886848), UINT64_C(0),	// V_CMPX_TRU_F32_e64_vi
    UINT64_C(2084438265), UINT64_C(0),	// V_CMPX_TRU_F32_sdwa_gfx10
    UINT64_C(2092826873), UINT64_C(0),	// V_CMPX_TRU_F32_sdwa_gfx9
    UINT64_C(2092826873), UINT64_C(0),	// V_CMPX_TRU_F32_sdwa_vi
    UINT64_C(2088632320), UINT64_C(0),	// V_CMPX_TRU_F64_e32_gfx10
    UINT64_C(2088632320), UINT64_C(0),	// V_CMPX_TRU_F64_e32_gfx6_gfx7
    UINT64_C(2097020928), UINT64_C(0),	// V_CMPX_TRU_F64_e32_vi
    UINT64_C(3560898560), UINT64_C(0),	// V_CMPX_TRU_F64_e64_gfx10
    UINT64_C(3497918464), UINT64_C(0),	// V_CMPX_TRU_F64_e64_gfx6_gfx7
    UINT64_C(3497984000), UINT64_C(0),	// V_CMPX_TRU_F64_e64_vi
    UINT64_C(2099118080), UINT64_C(0),	// V_CMPX_T_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2099118330), UINT64_C(0),	// V_CMPX_T_F16_fake16_e32_dpp_gfx11
    UINT64_C(2099118080), UINT64_C(0),	// V_CMPX_T_F16_fake16_e32_gfx11
    UINT64_C(3566141440), UINT64_C(0),	// V_CMPX_T_F16_fake16_e64_dpp8_gfx11
    UINT64_C(1077307965440), UINT64_C(0),	// V_CMPX_T_F16_fake16_e64_dpp_gfx11
    UINT64_C(3566141440), UINT64_C(0),	// V_CMPX_T_F16_fake16_e64_gfx11
    UINT64_C(2099118080), UINT64_C(0),	// V_CMPX_T_F16_t16_e32_dpp8_gfx11
    UINT64_C(2099118330), UINT64_C(0),	// V_CMPX_T_F16_t16_e32_dpp_gfx11
    UINT64_C(2099118080), UINT64_C(0),	// V_CMPX_T_F16_t16_e32_gfx11
    UINT64_C(3566141440), UINT64_C(0),	// V_CMPX_T_F16_t16_e64_dpp8_gfx11
    UINT64_C(1077307965440), UINT64_C(0),	// V_CMPX_T_F16_t16_e64_dpp_gfx11
    UINT64_C(3566141440), UINT64_C(0),	// V_CMPX_T_F16_t16_e64_gfx11
    UINT64_C(2101215232), UINT64_C(0),	// V_CMPX_T_F32_e32_dpp8_gfx11
    UINT64_C(2101215482), UINT64_C(0),	// V_CMPX_T_F32_e32_dpp_gfx11
    UINT64_C(2101215232), UINT64_C(0),	// V_CMPX_T_F32_e32_gfx11
    UINT64_C(3567190016), UINT64_C(0),	// V_CMPX_T_F32_e64_dpp8_gfx11
    UINT64_C(1077309014016), UINT64_C(0),	// V_CMPX_T_F32_e64_dpp_gfx11
    UINT64_C(3567190016), UINT64_C(0),	// V_CMPX_T_F32_e64_gfx11
    UINT64_C(2103312384), UINT64_C(0),	// V_CMPX_T_F64_e32_gfx11
    UINT64_C(3568238592), UINT64_C(0),	// V_CMPX_T_F64_e64_gfx11
    UINT64_C(2104360960), UINT64_C(0),	// V_CMPX_T_I16_e32_vi
    UINT64_C(3501654016), UINT64_C(0),	// V_CMPX_T_I16_e64_vi
    UINT64_C(2104361209), UINT64_C(0),	// V_CMPX_T_I16_sdwa_gfx9
    UINT64_C(2104361209), UINT64_C(0),	// V_CMPX_T_I16_sdwa_vi
    UINT64_C(2106458112), UINT64_C(0),	// V_CMPX_T_I32_e32_dpp8_gfx11
    UINT64_C(2106458362), UINT64_C(0),	// V_CMPX_T_I32_e32_dpp_gfx11
    UINT64_C(2100166656), UINT64_C(0),	// V_CMPX_T_I32_e32_gfx10
    UINT64_C(2106458112), UINT64_C(0),	// V_CMPX_T_I32_e32_gfx11
    UINT64_C(2100166656), UINT64_C(0),	// V_CMPX_T_I32_e32_gfx6_gfx7
    UINT64_C(2108555264), UINT64_C(0),	// V_CMPX_T_I32_e32_vi
    UINT64_C(3569811456), UINT64_C(0),	// V_CMPX_T_I32_e64_dpp8_gfx11
    UINT64_C(1077311635456), UINT64_C(0),	// V_CMPX_T_I32_e64_dpp_gfx11
    UINT64_C(3566665728), UINT64_C(0),	// V_CMPX_T_I32_e64_gfx10
    UINT64_C(3569811456), UINT64_C(0),	// V_CMPX_T_I32_e64_gfx11
    UINT64_C(3509452800), UINT64_C(0),	// V_CMPX_T_I32_e64_gfx6_gfx7
    UINT64_C(3503751168), UINT64_C(0),	// V_CMPX_T_I32_e64_vi
    UINT64_C(2100166905), UINT64_C(0),	// V_CMPX_T_I32_sdwa_gfx10
    UINT64_C(2108555513), UINT64_C(0),	// V_CMPX_T_I32_sdwa_gfx9
    UINT64_C(2108555513), UINT64_C(0),	// V_CMPX_T_I32_sdwa_vi
    UINT64_C(2104360960), UINT64_C(0),	// V_CMPX_T_I64_e32_gfx10
    UINT64_C(2108555264), UINT64_C(0),	// V_CMPX_T_I64_e32_gfx11
    UINT64_C(2104360960), UINT64_C(0),	// V_CMPX_T_I64_e32_gfx6_gfx7
    UINT64_C(2112749568), UINT64_C(0),	// V_CMPX_T_I64_e32_vi
    UINT64_C(3568762880), UINT64_C(0),	// V_CMPX_T_I64_e64_gfx10
    UINT64_C(3570860032), UINT64_C(0),	// V_CMPX_T_I64_e64_gfx11
    UINT64_C(3513647104), UINT64_C(0),	// V_CMPX_T_I64_e64_gfx6_gfx7
    UINT64_C(3505848320), UINT64_C(0),	// V_CMPX_T_I64_e64_vi
    UINT64_C(2105409536), UINT64_C(0),	// V_CMPX_T_U16_e32_vi
    UINT64_C(3502178304), UINT64_C(0),	// V_CMPX_T_U16_e64_vi
    UINT64_C(2105409785), UINT64_C(0),	// V_CMPX_T_U16_sdwa_gfx9
    UINT64_C(2105409785), UINT64_C(0),	// V_CMPX_T_U16_sdwa_vi
    UINT64_C(2107506688), UINT64_C(0),	// V_CMPX_T_U32_e32_dpp8_gfx11
    UINT64_C(2107506938), UINT64_C(0),	// V_CMPX_T_U32_e32_dpp_gfx11
    UINT64_C(2108555264), UINT64_C(0),	// V_CMPX_T_U32_e32_gfx10
    UINT64_C(2107506688), UINT64_C(0),	// V_CMPX_T_U32_e32_gfx11
    UINT64_C(2108555264), UINT64_C(0),	// V_CMPX_T_U32_e32_gfx6_gfx7
    UINT64_C(2109603840), UINT64_C(0),	// V_CMPX_T_U32_e32_vi
    UINT64_C(3570335744), UINT64_C(0),	// V_CMPX_T_U32_e64_dpp8_gfx11
    UINT64_C(1077312159744), UINT64_C(0),	// V_CMPX_T_U32_e64_dpp_gfx11
    UINT64_C(3570860032), UINT64_C(0),	// V_CMPX_T_U32_e64_gfx10
    UINT64_C(3570335744), UINT64_C(0),	// V_CMPX_T_U32_e64_gfx11
    UINT64_C(3517841408), UINT64_C(0),	// V_CMPX_T_U32_e64_gfx6_gfx7
    UINT64_C(3504275456), UINT64_C(0),	// V_CMPX_T_U32_e64_vi
    UINT64_C(2108555513), UINT64_C(0),	// V_CMPX_T_U32_sdwa_gfx10
    UINT64_C(2109604089), UINT64_C(0),	// V_CMPX_T_U32_sdwa_gfx9
    UINT64_C(2109604089), UINT64_C(0),	// V_CMPX_T_U32_sdwa_vi
    UINT64_C(2112749568), UINT64_C(0),	// V_CMPX_T_U64_e32_gfx10
    UINT64_C(2109603840), UINT64_C(0),	// V_CMPX_T_U64_e32_gfx11
    UINT64_C(2112749568), UINT64_C(0),	// V_CMPX_T_U64_e32_gfx6_gfx7
    UINT64_C(2113798144), UINT64_C(0),	// V_CMPX_T_U64_e32_vi
    UINT64_C(3572957184), UINT64_C(0),	// V_CMPX_T_U64_e64_gfx10
    UINT64_C(3571384320), UINT64_C(0),	// V_CMPX_T_U64_e64_gfx11
    UINT64_C(3522035712), UINT64_C(0),	// V_CMPX_T_U64_e64_gfx6_gfx7
    UINT64_C(3506372608), UINT64_C(0),	// V_CMPX_T_U64_e64_vi
    UINT64_C(2112880640), UINT64_C(0),	// V_CMPX_U_F16_e32_gfx10
    UINT64_C(2087714816), UINT64_C(0),	// V_CMPX_U_F16_e32_vi
    UINT64_C(3573022720), UINT64_C(0),	// V_CMPX_U_F16_e64_gfx10
    UINT64_C(3493330944), UINT64_C(0),	// V_CMPX_U_F16_e64_vi
    UINT64_C(2098200576), UINT64_C(0),	// V_CMPX_U_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2098200576), UINT64_C(0),	// V_CMPX_U_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2098200826), UINT64_C(0),	// V_CMPX_U_F16_fake16_e32_dpp_gfx11
    UINT64_C(2098200826), UINT64_C(0),	// V_CMPX_U_F16_fake16_e32_dpp_gfx12
    UINT64_C(2098200576), UINT64_C(0),	// V_CMPX_U_F16_fake16_e32_gfx11
    UINT64_C(2098200576), UINT64_C(0),	// V_CMPX_U_F16_fake16_e32_gfx12
    UINT64_C(3565682688), UINT64_C(0),	// V_CMPX_U_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3565682688), UINT64_C(0),	// V_CMPX_U_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077307506688), UINT64_C(0),	// V_CMPX_U_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077307506688), UINT64_C(0),	// V_CMPX_U_F16_fake16_e64_dpp_gfx12
    UINT64_C(3565682688), UINT64_C(0),	// V_CMPX_U_F16_fake16_e64_gfx11
    UINT64_C(3565682688), UINT64_C(0),	// V_CMPX_U_F16_fake16_e64_gfx12
    UINT64_C(2112880889), UINT64_C(0),	// V_CMPX_U_F16_sdwa_gfx10
    UINT64_C(2087715065), UINT64_C(0),	// V_CMPX_U_F16_sdwa_gfx9
    UINT64_C(2087715065), UINT64_C(0),	// V_CMPX_U_F16_sdwa_vi
    UINT64_C(2098200576), UINT64_C(0),	// V_CMPX_U_F16_t16_e32_dpp8_gfx11
    UINT64_C(2098200576), UINT64_C(0),	// V_CMPX_U_F16_t16_e32_dpp8_gfx12
    UINT64_C(2098200826), UINT64_C(0),	// V_CMPX_U_F16_t16_e32_dpp_gfx11
    UINT64_C(2098200826), UINT64_C(0),	// V_CMPX_U_F16_t16_e32_dpp_gfx12
    UINT64_C(2098200576), UINT64_C(0),	// V_CMPX_U_F16_t16_e32_gfx11
    UINT64_C(2098200576), UINT64_C(0),	// V_CMPX_U_F16_t16_e32_gfx12
    UINT64_C(3565682688), UINT64_C(0),	// V_CMPX_U_F16_t16_e64_dpp8_gfx11
    UINT64_C(3565682688), UINT64_C(0),	// V_CMPX_U_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077307506688), UINT64_C(0),	// V_CMPX_U_F16_t16_e64_dpp_gfx11
    UINT64_C(1077307506688), UINT64_C(0),	// V_CMPX_U_F16_t16_e64_dpp_gfx12
    UINT64_C(3565682688), UINT64_C(0),	// V_CMPX_U_F16_t16_e64_gfx11
    UINT64_C(3565682688), UINT64_C(0),	// V_CMPX_U_F16_t16_e64_gfx12
    UINT64_C(2100297728), UINT64_C(0),	// V_CMPX_U_F32_e32_dpp8_gfx11
    UINT64_C(2100297728), UINT64_C(0),	// V_CMPX_U_F32_e32_dpp8_gfx12
    UINT64_C(2100297978), UINT64_C(0),	// V_CMPX_U_F32_e32_dpp_gfx11
    UINT64_C(2100297978), UINT64_C(0),	// V_CMPX_U_F32_e32_dpp_gfx12
    UINT64_C(2083520512), UINT64_C(0),	// V_CMPX_U_F32_e32_gfx10
    UINT64_C(2100297728), UINT64_C(0),	// V_CMPX_U_F32_e32_gfx11
    UINT64_C(2100297728), UINT64_C(0),	// V_CMPX_U_F32_e32_gfx12
    UINT64_C(2083520512), UINT64_C(0),	// V_CMPX_U_F32_e32_gfx6_gfx7
    UINT64_C(2091909120), UINT64_C(0),	// V_CMPX_U_F32_e32_vi
    UINT64_C(3566731264), UINT64_C(0),	// V_CMPX_U_F32_e64_dpp8_gfx11
    UINT64_C(3566731264), UINT64_C(0),	// V_CMPX_U_F32_e64_dpp8_gfx12
    UINT64_C(1077308555264), UINT64_C(0),	// V_CMPX_U_F32_e64_dpp_gfx11
    UINT64_C(1077308555264), UINT64_C(0),	// V_CMPX_U_F32_e64_dpp_gfx12
    UINT64_C(3558342656), UINT64_C(0),	// V_CMPX_U_F32_e64_gfx10
    UINT64_C(3566731264), UINT64_C(0),	// V_CMPX_U_F32_e64_gfx11
    UINT64_C(3566731264), UINT64_C(0),	// V_CMPX_U_F32_e64_gfx12
    UINT64_C(3492806656), UINT64_C(0),	// V_CMPX_U_F32_e64_gfx6_gfx7
    UINT64_C(3495428096), UINT64_C(0),	// V_CMPX_U_F32_e64_vi
    UINT64_C(2083520761), UINT64_C(0),	// V_CMPX_U_F32_sdwa_gfx10
    UINT64_C(2091909369), UINT64_C(0),	// V_CMPX_U_F32_sdwa_gfx9
    UINT64_C(2091909369), UINT64_C(0),	// V_CMPX_U_F32_sdwa_vi
    UINT64_C(2087714816), UINT64_C(0),	// V_CMPX_U_F64_e32_gfx10
    UINT64_C(2102394880), UINT64_C(0),	// V_CMPX_U_F64_e32_gfx11
    UINT64_C(2102394880), UINT64_C(0),	// V_CMPX_U_F64_e32_gfx12
    UINT64_C(2087714816), UINT64_C(0),	// V_CMPX_U_F64_e32_gfx6_gfx7
    UINT64_C(2096103424), UINT64_C(0),	// V_CMPX_U_F64_e32_vi
    UINT64_C(3560439808), UINT64_C(0),	// V_CMPX_U_F64_e64_gfx10
    UINT64_C(3567779840), UINT64_C(0),	// V_CMPX_U_F64_e64_gfx11
    UINT64_C(3567779840), UINT64_C(0),	// V_CMPX_U_F64_e64_gfx12
    UINT64_C(3497000960), UINT64_C(0),	// V_CMPX_U_F64_e64_gfx6_gfx7
    UINT64_C(3497525248), UINT64_C(0),	// V_CMPX_U_F64_e64_vi
    UINT64_C(2099118080), UINT64_C(0),	// V_CMP_CLASS_F16_e32_gfx10
    UINT64_C(2082996224), UINT64_C(0),	// V_CMP_CLASS_F16_e32_vi
    UINT64_C(3566141440), UINT64_C(0),	// V_CMP_CLASS_F16_e64_gfx10
    UINT64_C(3490971648), UINT64_C(0),	// V_CMP_CLASS_F16_e64_vi
    UINT64_C(2096758784), UINT64_C(0),	// V_CMP_CLASS_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2096758784), UINT64_C(0),	// V_CMP_CLASS_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2096758784), UINT64_C(0),	// V_CMP_CLASS_F16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2096758784), UINT64_C(0),	// V_CMP_CLASS_F16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2096758784), UINT64_C(0),	// V_CMP_CLASS_F16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2096758784), UINT64_C(0),	// V_CMP_CLASS_F16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2096759034), UINT64_C(0),	// V_CMP_CLASS_F16_fake16_e32_dpp_gfx11
    UINT64_C(2096759034), UINT64_C(0),	// V_CMP_CLASS_F16_fake16_e32_dpp_gfx12
    UINT64_C(2096759034), UINT64_C(0),	// V_CMP_CLASS_F16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2096759034), UINT64_C(0),	// V_CMP_CLASS_F16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2096759034), UINT64_C(0),	// V_CMP_CLASS_F16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2096759034), UINT64_C(0),	// V_CMP_CLASS_F16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2096758784), UINT64_C(0),	// V_CMP_CLASS_F16_fake16_e32_gfx11
    UINT64_C(2096758784), UINT64_C(0),	// V_CMP_CLASS_F16_fake16_e32_gfx12
    UINT64_C(3564961792), UINT64_C(0),	// V_CMP_CLASS_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3564961792), UINT64_C(0),	// V_CMP_CLASS_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077306785792), UINT64_C(0),	// V_CMP_CLASS_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077306785792), UINT64_C(0),	// V_CMP_CLASS_F16_fake16_e64_dpp_gfx12
    UINT64_C(3564961792), UINT64_C(0),	// V_CMP_CLASS_F16_fake16_e64_gfx11
    UINT64_C(3564961792), UINT64_C(0),	// V_CMP_CLASS_F16_fake16_e64_gfx12
    UINT64_C(2099118329), UINT64_C(0),	// V_CMP_CLASS_F16_sdwa_gfx10
    UINT64_C(2082996473), UINT64_C(0),	// V_CMP_CLASS_F16_sdwa_gfx9
    UINT64_C(2082996473), UINT64_C(0),	// V_CMP_CLASS_F16_sdwa_vi
    UINT64_C(2096758784), UINT64_C(0),	// V_CMP_CLASS_F16_t16_e32_dpp8_gfx11
    UINT64_C(2096758784), UINT64_C(0),	// V_CMP_CLASS_F16_t16_e32_dpp8_gfx12
    UINT64_C(2096758784), UINT64_C(0),	// V_CMP_CLASS_F16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2096758784), UINT64_C(0),	// V_CMP_CLASS_F16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2096758784), UINT64_C(0),	// V_CMP_CLASS_F16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2096758784), UINT64_C(0),	// V_CMP_CLASS_F16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2096759034), UINT64_C(0),	// V_CMP_CLASS_F16_t16_e32_dpp_gfx11
    UINT64_C(2096759034), UINT64_C(0),	// V_CMP_CLASS_F16_t16_e32_dpp_gfx12
    UINT64_C(2096759034), UINT64_C(0),	// V_CMP_CLASS_F16_t16_e32_dpp_w32_gfx11
    UINT64_C(2096759034), UINT64_C(0),	// V_CMP_CLASS_F16_t16_e32_dpp_w32_gfx12
    UINT64_C(2096759034), UINT64_C(0),	// V_CMP_CLASS_F16_t16_e32_dpp_w64_gfx11
    UINT64_C(2096759034), UINT64_C(0),	// V_CMP_CLASS_F16_t16_e32_dpp_w64_gfx12
    UINT64_C(2096758784), UINT64_C(0),	// V_CMP_CLASS_F16_t16_e32_gfx11
    UINT64_C(2096758784), UINT64_C(0),	// V_CMP_CLASS_F16_t16_e32_gfx12
    UINT64_C(3564961792), UINT64_C(0),	// V_CMP_CLASS_F16_t16_e64_dpp8_gfx11
    UINT64_C(3564961792), UINT64_C(0),	// V_CMP_CLASS_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077306785792), UINT64_C(0),	// V_CMP_CLASS_F16_t16_e64_dpp_gfx11
    UINT64_C(1077306785792), UINT64_C(0),	// V_CMP_CLASS_F16_t16_e64_dpp_gfx12
    UINT64_C(3564961792), UINT64_C(0),	// V_CMP_CLASS_F16_t16_e64_gfx11
    UINT64_C(3564961792), UINT64_C(0),	// V_CMP_CLASS_F16_t16_e64_gfx12
    UINT64_C(2096889856), UINT64_C(0),	// V_CMP_CLASS_F32_e32_dpp8_gfx11
    UINT64_C(2096889856), UINT64_C(0),	// V_CMP_CLASS_F32_e32_dpp8_gfx12
    UINT64_C(2096889856), UINT64_C(0),	// V_CMP_CLASS_F32_e32_dpp8_w32_gfx11
    UINT64_C(2096889856), UINT64_C(0),	// V_CMP_CLASS_F32_e32_dpp8_w32_gfx12
    UINT64_C(2096889856), UINT64_C(0),	// V_CMP_CLASS_F32_e32_dpp8_w64_gfx11
    UINT64_C(2096889856), UINT64_C(0),	// V_CMP_CLASS_F32_e32_dpp8_w64_gfx12
    UINT64_C(2096890106), UINT64_C(0),	// V_CMP_CLASS_F32_e32_dpp_gfx11
    UINT64_C(2096890106), UINT64_C(0),	// V_CMP_CLASS_F32_e32_dpp_gfx12
    UINT64_C(2096890106), UINT64_C(0),	// V_CMP_CLASS_F32_e32_dpp_w32_gfx11
    UINT64_C(2096890106), UINT64_C(0),	// V_CMP_CLASS_F32_e32_dpp_w32_gfx12
    UINT64_C(2096890106), UINT64_C(0),	// V_CMP_CLASS_F32_e32_dpp_w64_gfx11
    UINT64_C(2096890106), UINT64_C(0),	// V_CMP_CLASS_F32_e32_dpp_w64_gfx12
    UINT64_C(2098200576), UINT64_C(0),	// V_CMP_CLASS_F32_e32_gfx10
    UINT64_C(2096889856), UINT64_C(0),	// V_CMP_CLASS_F32_e32_gfx11
    UINT64_C(2096889856), UINT64_C(0),	// V_CMP_CLASS_F32_e32_gfx12
    UINT64_C(2098200576), UINT64_C(0),	// V_CMP_CLASS_F32_e32_gfx6_gfx7
    UINT64_C(2082471936), UINT64_C(0),	// V_CMP_CLASS_F32_e32_vi
    UINT64_C(3565027328), UINT64_C(0),	// V_CMP_CLASS_F32_e64_dpp8_gfx11
    UINT64_C(3565027328), UINT64_C(0),	// V_CMP_CLASS_F32_e64_dpp8_gfx12
    UINT64_C(1077306851328), UINT64_C(0),	// V_CMP_CLASS_F32_e64_dpp_gfx11
    UINT64_C(1077306851328), UINT64_C(0),	// V_CMP_CLASS_F32_e64_dpp_gfx12
    UINT64_C(3565682688), UINT64_C(0),	// V_CMP_CLASS_F32_e64_gfx10
    UINT64_C(3565027328), UINT64_C(0),	// V_CMP_CLASS_F32_e64_gfx11
    UINT64_C(3565027328), UINT64_C(0),	// V_CMP_CLASS_F32_e64_gfx12
    UINT64_C(3507486720), UINT64_C(0),	// V_CMP_CLASS_F32_e64_gfx6_gfx7
    UINT64_C(3490709504), UINT64_C(0),	// V_CMP_CLASS_F32_e64_vi
    UINT64_C(2098200825), UINT64_C(0),	// V_CMP_CLASS_F32_sdwa_gfx10
    UINT64_C(2082472185), UINT64_C(0),	// V_CMP_CLASS_F32_sdwa_gfx9
    UINT64_C(2082472185), UINT64_C(0),	// V_CMP_CLASS_F32_sdwa_vi
    UINT64_C(2102394880), UINT64_C(0),	// V_CMP_CLASS_F64_e32_gfx10
    UINT64_C(2097020928), UINT64_C(0),	// V_CMP_CLASS_F64_e32_gfx11
    UINT64_C(2097020928), UINT64_C(0),	// V_CMP_CLASS_F64_e32_gfx12
    UINT64_C(2102394880), UINT64_C(0),	// V_CMP_CLASS_F64_e32_gfx6_gfx7
    UINT64_C(2082734080), UINT64_C(0),	// V_CMP_CLASS_F64_e32_vi
    UINT64_C(3567779840), UINT64_C(0),	// V_CMP_CLASS_F64_e64_gfx10
    UINT64_C(3565092864), UINT64_C(0),	// V_CMP_CLASS_F64_e64_gfx11
    UINT64_C(3565092864), UINT64_C(0),	// V_CMP_CLASS_F64_e64_gfx12
    UINT64_C(3511681024), UINT64_C(0),	// V_CMP_CLASS_F64_e64_gfx6_gfx7
    UINT64_C(3490840576), UINT64_C(0),	// V_CMP_CLASS_F64_e64_vi
    UINT64_C(2106851328), UINT64_C(0),	// V_CMP_EQ_F16_e32_gfx10
    UINT64_C(2084831232), UINT64_C(0),	// V_CMP_EQ_F16_e32_vi
    UINT64_C(3570008064), UINT64_C(0),	// V_CMP_EQ_F16_e64_gfx10
    UINT64_C(3491889152), UINT64_C(0),	// V_CMP_EQ_F16_e64_vi
    UINT64_C(2080636928), UINT64_C(0),	// V_CMP_EQ_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2080636928), UINT64_C(0),	// V_CMP_EQ_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2080636928), UINT64_C(0),	// V_CMP_EQ_F16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2080636928), UINT64_C(0),	// V_CMP_EQ_F16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2080636928), UINT64_C(0),	// V_CMP_EQ_F16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2080636928), UINT64_C(0),	// V_CMP_EQ_F16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2080637178), UINT64_C(0),	// V_CMP_EQ_F16_fake16_e32_dpp_gfx11
    UINT64_C(2080637178), UINT64_C(0),	// V_CMP_EQ_F16_fake16_e32_dpp_gfx12
    UINT64_C(2080637178), UINT64_C(0),	// V_CMP_EQ_F16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2080637178), UINT64_C(0),	// V_CMP_EQ_F16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2080637178), UINT64_C(0),	// V_CMP_EQ_F16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2080637178), UINT64_C(0),	// V_CMP_EQ_F16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2080636928), UINT64_C(0),	// V_CMP_EQ_F16_fake16_e32_gfx11
    UINT64_C(2080636928), UINT64_C(0),	// V_CMP_EQ_F16_fake16_e32_gfx12
    UINT64_C(3556900864), UINT64_C(0),	// V_CMP_EQ_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3556900864), UINT64_C(0),	// V_CMP_EQ_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077298724864), UINT64_C(0),	// V_CMP_EQ_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077298724864), UINT64_C(0),	// V_CMP_EQ_F16_fake16_e64_dpp_gfx12
    UINT64_C(3556900864), UINT64_C(0),	// V_CMP_EQ_F16_fake16_e64_gfx11
    UINT64_C(3556900864), UINT64_C(0),	// V_CMP_EQ_F16_fake16_e64_gfx12
    UINT64_C(2106851577), UINT64_C(0),	// V_CMP_EQ_F16_sdwa_gfx10
    UINT64_C(2084831481), UINT64_C(0),	// V_CMP_EQ_F16_sdwa_gfx9
    UINT64_C(2084831481), UINT64_C(0),	// V_CMP_EQ_F16_sdwa_vi
    UINT64_C(2080636928), UINT64_C(0),	// V_CMP_EQ_F16_t16_e32_dpp8_gfx11
    UINT64_C(2080636928), UINT64_C(0),	// V_CMP_EQ_F16_t16_e32_dpp8_gfx12
    UINT64_C(2080636928), UINT64_C(0),	// V_CMP_EQ_F16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2080636928), UINT64_C(0),	// V_CMP_EQ_F16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2080636928), UINT64_C(0),	// V_CMP_EQ_F16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2080636928), UINT64_C(0),	// V_CMP_EQ_F16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2080637178), UINT64_C(0),	// V_CMP_EQ_F16_t16_e32_dpp_gfx11
    UINT64_C(2080637178), UINT64_C(0),	// V_CMP_EQ_F16_t16_e32_dpp_gfx12
    UINT64_C(2080637178), UINT64_C(0),	// V_CMP_EQ_F16_t16_e32_dpp_w32_gfx11
    UINT64_C(2080637178), UINT64_C(0),	// V_CMP_EQ_F16_t16_e32_dpp_w32_gfx12
    UINT64_C(2080637178), UINT64_C(0),	// V_CMP_EQ_F16_t16_e32_dpp_w64_gfx11
    UINT64_C(2080637178), UINT64_C(0),	// V_CMP_EQ_F16_t16_e32_dpp_w64_gfx12
    UINT64_C(2080636928), UINT64_C(0),	// V_CMP_EQ_F16_t16_e32_gfx11
    UINT64_C(2080636928), UINT64_C(0),	// V_CMP_EQ_F16_t16_e32_gfx12
    UINT64_C(3556900864), UINT64_C(0),	// V_CMP_EQ_F16_t16_e64_dpp8_gfx11
    UINT64_C(3556900864), UINT64_C(0),	// V_CMP_EQ_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077298724864), UINT64_C(0),	// V_CMP_EQ_F16_t16_e64_dpp_gfx11
    UINT64_C(1077298724864), UINT64_C(0),	// V_CMP_EQ_F16_t16_e64_dpp_gfx12
    UINT64_C(3556900864), UINT64_C(0),	// V_CMP_EQ_F16_t16_e64_gfx11
    UINT64_C(3556900864), UINT64_C(0),	// V_CMP_EQ_F16_t16_e64_gfx12
    UINT64_C(2082734080), UINT64_C(0),	// V_CMP_EQ_F32_e32_dpp8_gfx11
    UINT64_C(2082734080), UINT64_C(0),	// V_CMP_EQ_F32_e32_dpp8_gfx12
    UINT64_C(2082734080), UINT64_C(0),	// V_CMP_EQ_F32_e32_dpp8_w32_gfx11
    UINT64_C(2082734080), UINT64_C(0),	// V_CMP_EQ_F32_e32_dpp8_w32_gfx12
    UINT64_C(2082734080), UINT64_C(0),	// V_CMP_EQ_F32_e32_dpp8_w64_gfx11
    UINT64_C(2082734080), UINT64_C(0),	// V_CMP_EQ_F32_e32_dpp8_w64_gfx12
    UINT64_C(2082734330), UINT64_C(0),	// V_CMP_EQ_F32_e32_dpp_gfx11
    UINT64_C(2082734330), UINT64_C(0),	// V_CMP_EQ_F32_e32_dpp_gfx12
    UINT64_C(2082734330), UINT64_C(0),	// V_CMP_EQ_F32_e32_dpp_w32_gfx11
    UINT64_C(2082734330), UINT64_C(0),	// V_CMP_EQ_F32_e32_dpp_w32_gfx12
    UINT64_C(2082734330), UINT64_C(0),	// V_CMP_EQ_F32_e32_dpp_w64_gfx11
    UINT64_C(2082734330), UINT64_C(0),	// V_CMP_EQ_F32_e32_dpp_w64_gfx12
    UINT64_C(2080636928), UINT64_C(0),	// V_CMP_EQ_F32_e32_gfx10
    UINT64_C(2082734080), UINT64_C(0),	// V_CMP_EQ_F32_e32_gfx11
    UINT64_C(2082734080), UINT64_C(0),	// V_CMP_EQ_F32_e32_gfx12
    UINT64_C(2080636928), UINT64_C(0),	// V_CMP_EQ_F32_e32_gfx6_gfx7
    UINT64_C(2089025536), UINT64_C(0),	// V_CMP_EQ_F32_e32_vi
    UINT64_C(3557949440), UINT64_C(0),	// V_CMP_EQ_F32_e64_dpp8_gfx11
    UINT64_C(3557949440), UINT64_C(0),	// V_CMP_EQ_F32_e64_dpp8_gfx12
    UINT64_C(1077299773440), UINT64_C(0),	// V_CMP_EQ_F32_e64_dpp_gfx11
    UINT64_C(1077299773440), UINT64_C(0),	// V_CMP_EQ_F32_e64_dpp_gfx12
    UINT64_C(3556900864), UINT64_C(0),	// V_CMP_EQ_F32_e64_gfx10
    UINT64_C(3557949440), UINT64_C(0),	// V_CMP_EQ_F32_e64_gfx11
    UINT64_C(3557949440), UINT64_C(0),	// V_CMP_EQ_F32_e64_gfx12
    UINT64_C(3489923072), UINT64_C(0),	// V_CMP_EQ_F32_e64_gfx6_gfx7
    UINT64_C(3493986304), UINT64_C(0),	// V_CMP_EQ_F32_e64_vi
    UINT64_C(2080637177), UINT64_C(0),	// V_CMP_EQ_F32_sdwa_gfx10
    UINT64_C(2089025785), UINT64_C(0),	// V_CMP_EQ_F32_sdwa_gfx9
    UINT64_C(2089025785), UINT64_C(0),	// V_CMP_EQ_F32_sdwa_vi
    UINT64_C(2084831232), UINT64_C(0),	// V_CMP_EQ_F64_e32_gfx10
    UINT64_C(2084831232), UINT64_C(0),	// V_CMP_EQ_F64_e32_gfx11
    UINT64_C(2084831232), UINT64_C(0),	// V_CMP_EQ_F64_e32_gfx12
    UINT64_C(2084831232), UINT64_C(0),	// V_CMP_EQ_F64_e32_gfx6_gfx7
    UINT64_C(2093219840), UINT64_C(0),	// V_CMP_EQ_F64_e32_vi
    UINT64_C(3558998016), UINT64_C(0),	// V_CMP_EQ_F64_e64_gfx10
    UINT64_C(3558998016), UINT64_C(0),	// V_CMP_EQ_F64_e64_gfx11
    UINT64_C(3558998016), UINT64_C(0),	// V_CMP_EQ_F64_e64_gfx12
    UINT64_C(3494117376), UINT64_C(0),	// V_CMP_EQ_F64_e64_gfx6_gfx7
    UINT64_C(3496083456), UINT64_C(0),	// V_CMP_EQ_F64_e64_vi
    UINT64_C(2098462720), UINT64_C(0),	// V_CMP_EQ_I16_e32_gfx10
    UINT64_C(2101608448), UINT64_C(0),	// V_CMP_EQ_I16_e32_vi
    UINT64_C(3565813760), UINT64_C(0),	// V_CMP_EQ_I16_e64_gfx10
    UINT64_C(3500277760), UINT64_C(0),	// V_CMP_EQ_I16_e64_vi
    UINT64_C(2086928384), UINT64_C(0),	// V_CMP_EQ_I16_fake16_e32_dpp8_gfx11
    UINT64_C(2086928384), UINT64_C(0),	// V_CMP_EQ_I16_fake16_e32_dpp8_gfx12
    UINT64_C(2086928384), UINT64_C(0),	// V_CMP_EQ_I16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2086928384), UINT64_C(0),	// V_CMP_EQ_I16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2086928384), UINT64_C(0),	// V_CMP_EQ_I16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2086928384), UINT64_C(0),	// V_CMP_EQ_I16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2086928634), UINT64_C(0),	// V_CMP_EQ_I16_fake16_e32_dpp_gfx11
    UINT64_C(2086928634), UINT64_C(0),	// V_CMP_EQ_I16_fake16_e32_dpp_gfx12
    UINT64_C(2086928634), UINT64_C(0),	// V_CMP_EQ_I16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2086928634), UINT64_C(0),	// V_CMP_EQ_I16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2086928634), UINT64_C(0),	// V_CMP_EQ_I16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2086928634), UINT64_C(0),	// V_CMP_EQ_I16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2086928384), UINT64_C(0),	// V_CMP_EQ_I16_fake16_e32_gfx11
    UINT64_C(2086928384), UINT64_C(0),	// V_CMP_EQ_I16_fake16_e32_gfx12
    UINT64_C(3560046592), UINT64_C(0),	// V_CMP_EQ_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3560046592), UINT64_C(0),	// V_CMP_EQ_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077301870592), UINT64_C(0),	// V_CMP_EQ_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077301870592), UINT64_C(0),	// V_CMP_EQ_I16_fake16_e64_dpp_gfx12
    UINT64_C(3560046592), UINT64_C(0),	// V_CMP_EQ_I16_fake16_e64_gfx11
    UINT64_C(3560046592), UINT64_C(0),	// V_CMP_EQ_I16_fake16_e64_gfx12
    UINT64_C(2098462969), UINT64_C(0),	// V_CMP_EQ_I16_sdwa_gfx10
    UINT64_C(2101608697), UINT64_C(0),	// V_CMP_EQ_I16_sdwa_gfx9
    UINT64_C(2101608697), UINT64_C(0),	// V_CMP_EQ_I16_sdwa_vi
    UINT64_C(2086928384), UINT64_C(0),	// V_CMP_EQ_I16_t16_e32_dpp8_gfx11
    UINT64_C(2086928384), UINT64_C(0),	// V_CMP_EQ_I16_t16_e32_dpp8_gfx12
    UINT64_C(2086928384), UINT64_C(0),	// V_CMP_EQ_I16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2086928384), UINT64_C(0),	// V_CMP_EQ_I16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2086928384), UINT64_C(0),	// V_CMP_EQ_I16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2086928384), UINT64_C(0),	// V_CMP_EQ_I16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2086928634), UINT64_C(0),	// V_CMP_EQ_I16_t16_e32_dpp_gfx11
    UINT64_C(2086928634), UINT64_C(0),	// V_CMP_EQ_I16_t16_e32_dpp_gfx12
    UINT64_C(2086928634), UINT64_C(0),	// V_CMP_EQ_I16_t16_e32_dpp_w32_gfx11
    UINT64_C(2086928634), UINT64_C(0),	// V_CMP_EQ_I16_t16_e32_dpp_w32_gfx12
    UINT64_C(2086928634), UINT64_C(0),	// V_CMP_EQ_I16_t16_e32_dpp_w64_gfx11
    UINT64_C(2086928634), UINT64_C(0),	// V_CMP_EQ_I16_t16_e32_dpp_w64_gfx12
    UINT64_C(2086928384), UINT64_C(0),	// V_CMP_EQ_I16_t16_e32_gfx11
    UINT64_C(2086928384), UINT64_C(0),	// V_CMP_EQ_I16_t16_e32_gfx12
    UINT64_C(3560046592), UINT64_C(0),	// V_CMP_EQ_I16_t16_e64_dpp8_gfx11
    UINT64_C(3560046592), UINT64_C(0),	// V_CMP_EQ_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077301870592), UINT64_C(0),	// V_CMP_EQ_I16_t16_e64_dpp_gfx11
    UINT64_C(1077301870592), UINT64_C(0),	// V_CMP_EQ_I16_t16_e64_dpp_gfx12
    UINT64_C(3560046592), UINT64_C(0),	// V_CMP_EQ_I16_t16_e64_gfx11
    UINT64_C(3560046592), UINT64_C(0),	// V_CMP_EQ_I16_t16_e64_gfx12
    UINT64_C(2089025536), UINT64_C(0),	// V_CMP_EQ_I32_e32_dpp8_gfx11
    UINT64_C(2089025536), UINT64_C(0),	// V_CMP_EQ_I32_e32_dpp8_gfx12
    UINT64_C(2089025536), UINT64_C(0),	// V_CMP_EQ_I32_e32_dpp8_w32_gfx11
    UINT64_C(2089025536), UINT64_C(0),	// V_CMP_EQ_I32_e32_dpp8_w32_gfx12
    UINT64_C(2089025536), UINT64_C(0),	// V_CMP_EQ_I32_e32_dpp8_w64_gfx11
    UINT64_C(2089025536), UINT64_C(0),	// V_CMP_EQ_I32_e32_dpp8_w64_gfx12
    UINT64_C(2089025786), UINT64_C(0),	// V_CMP_EQ_I32_e32_dpp_gfx11
    UINT64_C(2089025786), UINT64_C(0),	// V_CMP_EQ_I32_e32_dpp_gfx12
    UINT64_C(2089025786), UINT64_C(0),	// V_CMP_EQ_I32_e32_dpp_w32_gfx11
    UINT64_C(2089025786), UINT64_C(0),	// V_CMP_EQ_I32_e32_dpp_w32_gfx12
    UINT64_C(2089025786), UINT64_C(0),	// V_CMP_EQ_I32_e32_dpp_w64_gfx11
    UINT64_C(2089025786), UINT64_C(0),	// V_CMP_EQ_I32_e32_dpp_w64_gfx12
    UINT64_C(2097414144), UINT64_C(0),	// V_CMP_EQ_I32_e32_gfx10
    UINT64_C(2089025536), UINT64_C(0),	// V_CMP_EQ_I32_e32_gfx11
    UINT64_C(2089025536), UINT64_C(0),	// V_CMP_EQ_I32_e32_gfx12
    UINT64_C(2097414144), UINT64_C(0),	// V_CMP_EQ_I32_e32_gfx6_gfx7
    UINT64_C(2105802752), UINT64_C(0),	// V_CMP_EQ_I32_e32_vi
    UINT64_C(3561095168), UINT64_C(0),	// V_CMP_EQ_I32_e64_dpp8_gfx11
    UINT64_C(3561095168), UINT64_C(0),	// V_CMP_EQ_I32_e64_dpp8_gfx12
    UINT64_C(1077302919168), UINT64_C(0),	// V_CMP_EQ_I32_e64_dpp_gfx11
    UINT64_C(1077302919168), UINT64_C(0),	// V_CMP_EQ_I32_e64_dpp_gfx12
    UINT64_C(3565289472), UINT64_C(0),	// V_CMP_EQ_I32_e64_gfx10
    UINT64_C(3561095168), UINT64_C(0),	// V_CMP_EQ_I32_e64_gfx11
    UINT64_C(3561095168), UINT64_C(0),	// V_CMP_EQ_I32_e64_gfx12
    UINT64_C(3506700288), UINT64_C(0),	// V_CMP_EQ_I32_e64_gfx6_gfx7
    UINT64_C(3502374912), UINT64_C(0),	// V_CMP_EQ_I32_e64_vi
    UINT64_C(2097414393), UINT64_C(0),	// V_CMP_EQ_I32_sdwa_gfx10
    UINT64_C(2105803001), UINT64_C(0),	// V_CMP_EQ_I32_sdwa_gfx9
    UINT64_C(2105803001), UINT64_C(0),	// V_CMP_EQ_I32_sdwa_vi
    UINT64_C(2101608448), UINT64_C(0),	// V_CMP_EQ_I64_e32_gfx10
    UINT64_C(2091122688), UINT64_C(0),	// V_CMP_EQ_I64_e32_gfx11
    UINT64_C(2091122688), UINT64_C(0),	// V_CMP_EQ_I64_e32_gfx12
    UINT64_C(2101608448), UINT64_C(0),	// V_CMP_EQ_I64_e32_gfx6_gfx7
    UINT64_C(2109997056), UINT64_C(0),	// V_CMP_EQ_I64_e32_vi
    UINT64_C(3567386624), UINT64_C(0),	// V_CMP_EQ_I64_e64_gfx10
    UINT64_C(3562143744), UINT64_C(0),	// V_CMP_EQ_I64_e64_gfx11
    UINT64_C(3562143744), UINT64_C(0),	// V_CMP_EQ_I64_e64_gfx12
    UINT64_C(3510894592), UINT64_C(0),	// V_CMP_EQ_I64_e64_gfx6_gfx7
    UINT64_C(3504472064), UINT64_C(0),	// V_CMP_EQ_I64_e64_vi
    UINT64_C(2102657024), UINT64_C(0),	// V_CMP_EQ_U16_e32_gfx10
    UINT64_C(2102657024), UINT64_C(0),	// V_CMP_EQ_U16_e32_vi
    UINT64_C(3567910912), UINT64_C(0),	// V_CMP_EQ_U16_e64_gfx10
    UINT64_C(3500802048), UINT64_C(0),	// V_CMP_EQ_U16_e64_vi
    UINT64_C(2087976960), UINT64_C(0),	// V_CMP_EQ_U16_fake16_e32_dpp8_gfx11
    UINT64_C(2087976960), UINT64_C(0),	// V_CMP_EQ_U16_fake16_e32_dpp8_gfx12
    UINT64_C(2087976960), UINT64_C(0),	// V_CMP_EQ_U16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2087976960), UINT64_C(0),	// V_CMP_EQ_U16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2087976960), UINT64_C(0),	// V_CMP_EQ_U16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2087976960), UINT64_C(0),	// V_CMP_EQ_U16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2087977210), UINT64_C(0),	// V_CMP_EQ_U16_fake16_e32_dpp_gfx11
    UINT64_C(2087977210), UINT64_C(0),	// V_CMP_EQ_U16_fake16_e32_dpp_gfx12
    UINT64_C(2087977210), UINT64_C(0),	// V_CMP_EQ_U16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2087977210), UINT64_C(0),	// V_CMP_EQ_U16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2087977210), UINT64_C(0),	// V_CMP_EQ_U16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2087977210), UINT64_C(0),	// V_CMP_EQ_U16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2087976960), UINT64_C(0),	// V_CMP_EQ_U16_fake16_e32_gfx11
    UINT64_C(2087976960), UINT64_C(0),	// V_CMP_EQ_U16_fake16_e32_gfx12
    UINT64_C(3560570880), UINT64_C(0),	// V_CMP_EQ_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3560570880), UINT64_C(0),	// V_CMP_EQ_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077302394880), UINT64_C(0),	// V_CMP_EQ_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077302394880), UINT64_C(0),	// V_CMP_EQ_U16_fake16_e64_dpp_gfx12
    UINT64_C(3560570880), UINT64_C(0),	// V_CMP_EQ_U16_fake16_e64_gfx11
    UINT64_C(3560570880), UINT64_C(0),	// V_CMP_EQ_U16_fake16_e64_gfx12
    UINT64_C(2102657273), UINT64_C(0),	// V_CMP_EQ_U16_sdwa_gfx10
    UINT64_C(2102657273), UINT64_C(0),	// V_CMP_EQ_U16_sdwa_gfx9
    UINT64_C(2102657273), UINT64_C(0),	// V_CMP_EQ_U16_sdwa_vi
    UINT64_C(2087976960), UINT64_C(0),	// V_CMP_EQ_U16_t16_e32_dpp8_gfx11
    UINT64_C(2087976960), UINT64_C(0),	// V_CMP_EQ_U16_t16_e32_dpp8_gfx12
    UINT64_C(2087976960), UINT64_C(0),	// V_CMP_EQ_U16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2087976960), UINT64_C(0),	// V_CMP_EQ_U16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2087976960), UINT64_C(0),	// V_CMP_EQ_U16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2087976960), UINT64_C(0),	// V_CMP_EQ_U16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2087977210), UINT64_C(0),	// V_CMP_EQ_U16_t16_e32_dpp_gfx11
    UINT64_C(2087977210), UINT64_C(0),	// V_CMP_EQ_U16_t16_e32_dpp_gfx12
    UINT64_C(2087977210), UINT64_C(0),	// V_CMP_EQ_U16_t16_e32_dpp_w32_gfx11
    UINT64_C(2087977210), UINT64_C(0),	// V_CMP_EQ_U16_t16_e32_dpp_w32_gfx12
    UINT64_C(2087977210), UINT64_C(0),	// V_CMP_EQ_U16_t16_e32_dpp_w64_gfx11
    UINT64_C(2087977210), UINT64_C(0),	// V_CMP_EQ_U16_t16_e32_dpp_w64_gfx12
    UINT64_C(2087976960), UINT64_C(0),	// V_CMP_EQ_U16_t16_e32_gfx11
    UINT64_C(2087976960), UINT64_C(0),	// V_CMP_EQ_U16_t16_e32_gfx12
    UINT64_C(3560570880), UINT64_C(0),	// V_CMP_EQ_U16_t16_e64_dpp8_gfx11
    UINT64_C(3560570880), UINT64_C(0),	// V_CMP_EQ_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077302394880), UINT64_C(0),	// V_CMP_EQ_U16_t16_e64_dpp_gfx11
    UINT64_C(1077302394880), UINT64_C(0),	// V_CMP_EQ_U16_t16_e64_dpp_gfx12
    UINT64_C(3560570880), UINT64_C(0),	// V_CMP_EQ_U16_t16_e64_gfx11
    UINT64_C(3560570880), UINT64_C(0),	// V_CMP_EQ_U16_t16_e64_gfx12
    UINT64_C(2090074112), UINT64_C(0),	// V_CMP_EQ_U32_e32_dpp8_gfx11
    UINT64_C(2090074112), UINT64_C(0),	// V_CMP_EQ_U32_e32_dpp8_gfx12
    UINT64_C(2090074112), UINT64_C(0),	// V_CMP_EQ_U32_e32_dpp8_w32_gfx11
    UINT64_C(2090074112), UINT64_C(0),	// V_CMP_EQ_U32_e32_dpp8_w32_gfx12
    UINT64_C(2090074112), UINT64_C(0),	// V_CMP_EQ_U32_e32_dpp8_w64_gfx11
    UINT64_C(2090074112), UINT64_C(0),	// V_CMP_EQ_U32_e32_dpp8_w64_gfx12
    UINT64_C(2090074362), UINT64_C(0),	// V_CMP_EQ_U32_e32_dpp_gfx11
    UINT64_C(2090074362), UINT64_C(0),	// V_CMP_EQ_U32_e32_dpp_gfx12
    UINT64_C(2090074362), UINT64_C(0),	// V_CMP_EQ_U32_e32_dpp_w32_gfx11
    UINT64_C(2090074362), UINT64_C(0),	// V_CMP_EQ_U32_e32_dpp_w32_gfx12
    UINT64_C(2090074362), UINT64_C(0),	// V_CMP_EQ_U32_e32_dpp_w64_gfx11
    UINT64_C(2090074362), UINT64_C(0),	// V_CMP_EQ_U32_e32_dpp_w64_gfx12
    UINT64_C(2105802752), UINT64_C(0),	// V_CMP_EQ_U32_e32_gfx10
    UINT64_C(2090074112), UINT64_C(0),	// V_CMP_EQ_U32_e32_gfx11
    UINT64_C(2090074112), UINT64_C(0),	// V_CMP_EQ_U32_e32_gfx12
    UINT64_C(2105802752), UINT64_C(0),	// V_CMP_EQ_U32_e32_gfx6_gfx7
    UINT64_C(2106851328), UINT64_C(0),	// V_CMP_EQ_U32_e32_vi
    UINT64_C(3561619456), UINT64_C(0),	// V_CMP_EQ_U32_e64_dpp8_gfx11
    UINT64_C(3561619456), UINT64_C(0),	// V_CMP_EQ_U32_e64_dpp8_gfx12
    UINT64_C(1077303443456), UINT64_C(0),	// V_CMP_EQ_U32_e64_dpp_gfx11
    UINT64_C(1077303443456), UINT64_C(0),	// V_CMP_EQ_U32_e64_dpp_gfx12
    UINT64_C(3569483776), UINT64_C(0),	// V_CMP_EQ_U32_e64_gfx10
    UINT64_C(3561619456), UINT64_C(0),	// V_CMP_EQ_U32_e64_gfx11
    UINT64_C(3561619456), UINT64_C(0),	// V_CMP_EQ_U32_e64_gfx12
    UINT64_C(3515088896), UINT64_C(0),	// V_CMP_EQ_U32_e64_gfx6_gfx7
    UINT64_C(3502899200), UINT64_C(0),	// V_CMP_EQ_U32_e64_vi
    UINT64_C(2105803001), UINT64_C(0),	// V_CMP_EQ_U32_sdwa_gfx10
    UINT64_C(2106851577), UINT64_C(0),	// V_CMP_EQ_U32_sdwa_gfx9
    UINT64_C(2106851577), UINT64_C(0),	// V_CMP_EQ_U32_sdwa_vi
    UINT64_C(2109997056), UINT64_C(0),	// V_CMP_EQ_U64_e32_gfx10
    UINT64_C(2092171264), UINT64_C(0),	// V_CMP_EQ_U64_e32_gfx11
    UINT64_C(2092171264), UINT64_C(0),	// V_CMP_EQ_U64_e32_gfx12
    UINT64_C(2109997056), UINT64_C(0),	// V_CMP_EQ_U64_e32_gfx6_gfx7
    UINT64_C(2111045632), UINT64_C(0),	// V_CMP_EQ_U64_e32_vi
    UINT64_C(3571580928), UINT64_C(0),	// V_CMP_EQ_U64_e64_gfx10
    UINT64_C(3562668032), UINT64_C(0),	// V_CMP_EQ_U64_e64_gfx11
    UINT64_C(3562668032), UINT64_C(0),	// V_CMP_EQ_U64_e64_gfx12
    UINT64_C(3519283200), UINT64_C(0),	// V_CMP_EQ_U64_e64_gfx6_gfx7
    UINT64_C(3504996352), UINT64_C(0),	// V_CMP_EQ_U64_e64_vi
    UINT64_C(2106589184), UINT64_C(0),	// V_CMP_F_F16_e32_gfx10
    UINT64_C(2084569088), UINT64_C(0),	// V_CMP_F_F16_e32_vi
    UINT64_C(3569876992), UINT64_C(0),	// V_CMP_F_F16_e64_gfx10
    UINT64_C(3491758080), UINT64_C(0),	// V_CMP_F_F16_e64_vi
    UINT64_C(2080374784), UINT64_C(0),	// V_CMP_F_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2080374784), UINT64_C(0),	// V_CMP_F_F16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2080374784), UINT64_C(0),	// V_CMP_F_F16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2080375034), UINT64_C(0),	// V_CMP_F_F16_fake16_e32_dpp_gfx11
    UINT64_C(2080375034), UINT64_C(0),	// V_CMP_F_F16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2080375034), UINT64_C(0),	// V_CMP_F_F16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2080374784), UINT64_C(0),	// V_CMP_F_F16_fake16_e32_gfx11
    UINT64_C(3556769792), UINT64_C(0),	// V_CMP_F_F16_fake16_e64_dpp8_gfx11
    UINT64_C(1077298593792), UINT64_C(0),	// V_CMP_F_F16_fake16_e64_dpp_gfx11
    UINT64_C(3556769792), UINT64_C(0),	// V_CMP_F_F16_fake16_e64_gfx11
    UINT64_C(2106589433), UINT64_C(0),	// V_CMP_F_F16_sdwa_gfx10
    UINT64_C(2084569337), UINT64_C(0),	// V_CMP_F_F16_sdwa_gfx9
    UINT64_C(2084569337), UINT64_C(0),	// V_CMP_F_F16_sdwa_vi
    UINT64_C(2080374784), UINT64_C(0),	// V_CMP_F_F16_t16_e32_dpp8_gfx11
    UINT64_C(2080374784), UINT64_C(0),	// V_CMP_F_F16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2080374784), UINT64_C(0),	// V_CMP_F_F16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2080375034), UINT64_C(0),	// V_CMP_F_F16_t16_e32_dpp_gfx11
    UINT64_C(2080375034), UINT64_C(0),	// V_CMP_F_F16_t16_e32_dpp_w32_gfx11
    UINT64_C(2080375034), UINT64_C(0),	// V_CMP_F_F16_t16_e32_dpp_w64_gfx11
    UINT64_C(2080374784), UINT64_C(0),	// V_CMP_F_F16_t16_e32_gfx11
    UINT64_C(3556769792), UINT64_C(0),	// V_CMP_F_F16_t16_e64_dpp8_gfx11
    UINT64_C(1077298593792), UINT64_C(0),	// V_CMP_F_F16_t16_e64_dpp_gfx11
    UINT64_C(3556769792), UINT64_C(0),	// V_CMP_F_F16_t16_e64_gfx11
    UINT64_C(2082471936), UINT64_C(0),	// V_CMP_F_F32_e32_dpp8_gfx11
    UINT64_C(2082471936), UINT64_C(0),	// V_CMP_F_F32_e32_dpp8_w32_gfx11
    UINT64_C(2082471936), UINT64_C(0),	// V_CMP_F_F32_e32_dpp8_w64_gfx11
    UINT64_C(2082472186), UINT64_C(0),	// V_CMP_F_F32_e32_dpp_gfx11
    UINT64_C(2082472186), UINT64_C(0),	// V_CMP_F_F32_e32_dpp_w32_gfx11
    UINT64_C(2082472186), UINT64_C(0),	// V_CMP_F_F32_e32_dpp_w64_gfx11
    UINT64_C(2080374784), UINT64_C(0),	// V_CMP_F_F32_e32_gfx10
    UINT64_C(2082471936), UINT64_C(0),	// V_CMP_F_F32_e32_gfx11
    UINT64_C(2080374784), UINT64_C(0),	// V_CMP_F_F32_e32_gfx6_gfx7
    UINT64_C(2088763392), UINT64_C(0),	// V_CMP_F_F32_e32_vi
    UINT64_C(3557818368), UINT64_C(0),	// V_CMP_F_F32_e64_dpp8_gfx11
    UINT64_C(1077299642368), UINT64_C(0),	// V_CMP_F_F32_e64_dpp_gfx11
    UINT64_C(3556769792), UINT64_C(0),	// V_CMP_F_F32_e64_gfx10
    UINT64_C(3557818368), UINT64_C(0),	// V_CMP_F_F32_e64_gfx11
    UINT64_C(3489660928), UINT64_C(0),	// V_CMP_F_F32_e64_gfx6_gfx7
    UINT64_C(3493855232), UINT64_C(0),	// V_CMP_F_F32_e64_vi
    UINT64_C(2080375033), UINT64_C(0),	// V_CMP_F_F32_sdwa_gfx10
    UINT64_C(2088763641), UINT64_C(0),	// V_CMP_F_F32_sdwa_gfx9
    UINT64_C(2088763641), UINT64_C(0),	// V_CMP_F_F32_sdwa_vi
    UINT64_C(2084569088), UINT64_C(0),	// V_CMP_F_F64_e32_gfx10
    UINT64_C(2084569088), UINT64_C(0),	// V_CMP_F_F64_e32_gfx11
    UINT64_C(2084569088), UINT64_C(0),	// V_CMP_F_F64_e32_gfx6_gfx7
    UINT64_C(2092957696), UINT64_C(0),	// V_CMP_F_F64_e32_vi
    UINT64_C(3558866944), UINT64_C(0),	// V_CMP_F_F64_e64_gfx10
    UINT64_C(3558866944), UINT64_C(0),	// V_CMP_F_F64_e64_gfx11
    UINT64_C(3493855232), UINT64_C(0),	// V_CMP_F_F64_e64_gfx6_gfx7
    UINT64_C(3495952384), UINT64_C(0),	// V_CMP_F_F64_e64_vi
    UINT64_C(2101346304), UINT64_C(0),	// V_CMP_F_I16_e32_vi
    UINT64_C(3500146688), UINT64_C(0),	// V_CMP_F_I16_e64_vi
    UINT64_C(2101346553), UINT64_C(0),	// V_CMP_F_I16_sdwa_gfx9
    UINT64_C(2101346553), UINT64_C(0),	// V_CMP_F_I16_sdwa_vi
    UINT64_C(2088763392), UINT64_C(0),	// V_CMP_F_I32_e32_dpp8_gfx11
    UINT64_C(2088763392), UINT64_C(0),	// V_CMP_F_I32_e32_dpp8_w32_gfx11
    UINT64_C(2088763392), UINT64_C(0),	// V_CMP_F_I32_e32_dpp8_w64_gfx11
    UINT64_C(2088763642), UINT64_C(0),	// V_CMP_F_I32_e32_dpp_gfx11
    UINT64_C(2088763642), UINT64_C(0),	// V_CMP_F_I32_e32_dpp_w32_gfx11
    UINT64_C(2088763642), UINT64_C(0),	// V_CMP_F_I32_e32_dpp_w64_gfx11
    UINT64_C(2097152000), UINT64_C(0),	// V_CMP_F_I32_e32_gfx10
    UINT64_C(2088763392), UINT64_C(0),	// V_CMP_F_I32_e32_gfx11
    UINT64_C(2097152000), UINT64_C(0),	// V_CMP_F_I32_e32_gfx6_gfx7
    UINT64_C(2105540608), UINT64_C(0),	// V_CMP_F_I32_e32_vi
    UINT64_C(3560964096), UINT64_C(0),	// V_CMP_F_I32_e64_dpp8_gfx11
    UINT64_C(1077302788096), UINT64_C(0),	// V_CMP_F_I32_e64_dpp_gfx11
    UINT64_C(3565158400), UINT64_C(0),	// V_CMP_F_I32_e64_gfx10
    UINT64_C(3560964096), UINT64_C(0),	// V_CMP_F_I32_e64_gfx11
    UINT64_C(3506438144), UINT64_C(0),	// V_CMP_F_I32_e64_gfx6_gfx7
    UINT64_C(3502243840), UINT64_C(0),	// V_CMP_F_I32_e64_vi
    UINT64_C(2097152249), UINT64_C(0),	// V_CMP_F_I32_sdwa_gfx10
    UINT64_C(2105540857), UINT64_C(0),	// V_CMP_F_I32_sdwa_gfx9
    UINT64_C(2105540857), UINT64_C(0),	// V_CMP_F_I32_sdwa_vi
    UINT64_C(2101346304), UINT64_C(0),	// V_CMP_F_I64_e32_gfx10
    UINT64_C(2090860544), UINT64_C(0),	// V_CMP_F_I64_e32_gfx11
    UINT64_C(2101346304), UINT64_C(0),	// V_CMP_F_I64_e32_gfx6_gfx7
    UINT64_C(2109734912), UINT64_C(0),	// V_CMP_F_I64_e32_vi
    UINT64_C(3567255552), UINT64_C(0),	// V_CMP_F_I64_e64_gfx10
    UINT64_C(3562012672), UINT64_C(0),	// V_CMP_F_I64_e64_gfx11
    UINT64_C(3510632448), UINT64_C(0),	// V_CMP_F_I64_e64_gfx6_gfx7
    UINT64_C(3504340992), UINT64_C(0),	// V_CMP_F_I64_e64_vi
    UINT64_C(2102394880), UINT64_C(0),	// V_CMP_F_U16_e32_vi
    UINT64_C(3500670976), UINT64_C(0),	// V_CMP_F_U16_e64_vi
    UINT64_C(2102395129), UINT64_C(0),	// V_CMP_F_U16_sdwa_gfx9
    UINT64_C(2102395129), UINT64_C(0),	// V_CMP_F_U16_sdwa_vi
    UINT64_C(2089811968), UINT64_C(0),	// V_CMP_F_U32_e32_dpp8_gfx11
    UINT64_C(2089811968), UINT64_C(0),	// V_CMP_F_U32_e32_dpp8_w32_gfx11
    UINT64_C(2089811968), UINT64_C(0),	// V_CMP_F_U32_e32_dpp8_w64_gfx11
    UINT64_C(2089812218), UINT64_C(0),	// V_CMP_F_U32_e32_dpp_gfx11
    UINT64_C(2089812218), UINT64_C(0),	// V_CMP_F_U32_e32_dpp_w32_gfx11
    UINT64_C(2089812218), UINT64_C(0),	// V_CMP_F_U32_e32_dpp_w64_gfx11
    UINT64_C(2105540608), UINT64_C(0),	// V_CMP_F_U32_e32_gfx10
    UINT64_C(2089811968), UINT64_C(0),	// V_CMP_F_U32_e32_gfx11
    UINT64_C(2105540608), UINT64_C(0),	// V_CMP_F_U32_e32_gfx6_gfx7
    UINT64_C(2106589184), UINT64_C(0),	// V_CMP_F_U32_e32_vi
    UINT64_C(3561488384), UINT64_C(0),	// V_CMP_F_U32_e64_dpp8_gfx11
    UINT64_C(1077303312384), UINT64_C(0),	// V_CMP_F_U32_e64_dpp_gfx11
    UINT64_C(3569352704), UINT64_C(0),	// V_CMP_F_U32_e64_gfx10
    UINT64_C(3561488384), UINT64_C(0),	// V_CMP_F_U32_e64_gfx11
    UINT64_C(3514826752), UINT64_C(0),	// V_CMP_F_U32_e64_gfx6_gfx7
    UINT64_C(3502768128), UINT64_C(0),	// V_CMP_F_U32_e64_vi
    UINT64_C(2105540857), UINT64_C(0),	// V_CMP_F_U32_sdwa_gfx10
    UINT64_C(2106589433), UINT64_C(0),	// V_CMP_F_U32_sdwa_gfx9
    UINT64_C(2106589433), UINT64_C(0),	// V_CMP_F_U32_sdwa_vi
    UINT64_C(2109734912), UINT64_C(0),	// V_CMP_F_U64_e32_gfx10
    UINT64_C(2091909120), UINT64_C(0),	// V_CMP_F_U64_e32_gfx11
    UINT64_C(2109734912), UINT64_C(0),	// V_CMP_F_U64_e32_gfx6_gfx7
    UINT64_C(2110783488), UINT64_C(0),	// V_CMP_F_U64_e32_vi
    UINT64_C(3571449856), UINT64_C(0),	// V_CMP_F_U64_e64_gfx10
    UINT64_C(3562536960), UINT64_C(0),	// V_CMP_F_U64_e64_gfx11
    UINT64_C(3519021056), UINT64_C(0),	// V_CMP_F_U64_e64_gfx6_gfx7
    UINT64_C(3504865280), UINT64_C(0),	// V_CMP_F_U64_e64_vi
    UINT64_C(2107375616), UINT64_C(0),	// V_CMP_GE_F16_e32_gfx10
    UINT64_C(2085355520), UINT64_C(0),	// V_CMP_GE_F16_e32_vi
    UINT64_C(3570270208), UINT64_C(0),	// V_CMP_GE_F16_e64_gfx10
    UINT64_C(3492151296), UINT64_C(0),	// V_CMP_GE_F16_e64_vi
    UINT64_C(2081161216), UINT64_C(0),	// V_CMP_GE_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2081161216), UINT64_C(0),	// V_CMP_GE_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2081161216), UINT64_C(0),	// V_CMP_GE_F16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2081161216), UINT64_C(0),	// V_CMP_GE_F16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2081161216), UINT64_C(0),	// V_CMP_GE_F16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2081161216), UINT64_C(0),	// V_CMP_GE_F16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2081161466), UINT64_C(0),	// V_CMP_GE_F16_fake16_e32_dpp_gfx11
    UINT64_C(2081161466), UINT64_C(0),	// V_CMP_GE_F16_fake16_e32_dpp_gfx12
    UINT64_C(2081161466), UINT64_C(0),	// V_CMP_GE_F16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2081161466), UINT64_C(0),	// V_CMP_GE_F16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2081161466), UINT64_C(0),	// V_CMP_GE_F16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2081161466), UINT64_C(0),	// V_CMP_GE_F16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2081161216), UINT64_C(0),	// V_CMP_GE_F16_fake16_e32_gfx11
    UINT64_C(2081161216), UINT64_C(0),	// V_CMP_GE_F16_fake16_e32_gfx12
    UINT64_C(3557163008), UINT64_C(0),	// V_CMP_GE_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3557163008), UINT64_C(0),	// V_CMP_GE_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077298987008), UINT64_C(0),	// V_CMP_GE_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077298987008), UINT64_C(0),	// V_CMP_GE_F16_fake16_e64_dpp_gfx12
    UINT64_C(3557163008), UINT64_C(0),	// V_CMP_GE_F16_fake16_e64_gfx11
    UINT64_C(3557163008), UINT64_C(0),	// V_CMP_GE_F16_fake16_e64_gfx12
    UINT64_C(2107375865), UINT64_C(0),	// V_CMP_GE_F16_sdwa_gfx10
    UINT64_C(2085355769), UINT64_C(0),	// V_CMP_GE_F16_sdwa_gfx9
    UINT64_C(2085355769), UINT64_C(0),	// V_CMP_GE_F16_sdwa_vi
    UINT64_C(2081161216), UINT64_C(0),	// V_CMP_GE_F16_t16_e32_dpp8_gfx11
    UINT64_C(2081161216), UINT64_C(0),	// V_CMP_GE_F16_t16_e32_dpp8_gfx12
    UINT64_C(2081161216), UINT64_C(0),	// V_CMP_GE_F16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2081161216), UINT64_C(0),	// V_CMP_GE_F16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2081161216), UINT64_C(0),	// V_CMP_GE_F16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2081161216), UINT64_C(0),	// V_CMP_GE_F16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2081161466), UINT64_C(0),	// V_CMP_GE_F16_t16_e32_dpp_gfx11
    UINT64_C(2081161466), UINT64_C(0),	// V_CMP_GE_F16_t16_e32_dpp_gfx12
    UINT64_C(2081161466), UINT64_C(0),	// V_CMP_GE_F16_t16_e32_dpp_w32_gfx11
    UINT64_C(2081161466), UINT64_C(0),	// V_CMP_GE_F16_t16_e32_dpp_w32_gfx12
    UINT64_C(2081161466), UINT64_C(0),	// V_CMP_GE_F16_t16_e32_dpp_w64_gfx11
    UINT64_C(2081161466), UINT64_C(0),	// V_CMP_GE_F16_t16_e32_dpp_w64_gfx12
    UINT64_C(2081161216), UINT64_C(0),	// V_CMP_GE_F16_t16_e32_gfx11
    UINT64_C(2081161216), UINT64_C(0),	// V_CMP_GE_F16_t16_e32_gfx12
    UINT64_C(3557163008), UINT64_C(0),	// V_CMP_GE_F16_t16_e64_dpp8_gfx11
    UINT64_C(3557163008), UINT64_C(0),	// V_CMP_GE_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077298987008), UINT64_C(0),	// V_CMP_GE_F16_t16_e64_dpp_gfx11
    UINT64_C(1077298987008), UINT64_C(0),	// V_CMP_GE_F16_t16_e64_dpp_gfx12
    UINT64_C(3557163008), UINT64_C(0),	// V_CMP_GE_F16_t16_e64_gfx11
    UINT64_C(3557163008), UINT64_C(0),	// V_CMP_GE_F16_t16_e64_gfx12
    UINT64_C(2083258368), UINT64_C(0),	// V_CMP_GE_F32_e32_dpp8_gfx11
    UINT64_C(2083258368), UINT64_C(0),	// V_CMP_GE_F32_e32_dpp8_gfx12
    UINT64_C(2083258368), UINT64_C(0),	// V_CMP_GE_F32_e32_dpp8_w32_gfx11
    UINT64_C(2083258368), UINT64_C(0),	// V_CMP_GE_F32_e32_dpp8_w32_gfx12
    UINT64_C(2083258368), UINT64_C(0),	// V_CMP_GE_F32_e32_dpp8_w64_gfx11
    UINT64_C(2083258368), UINT64_C(0),	// V_CMP_GE_F32_e32_dpp8_w64_gfx12
    UINT64_C(2083258618), UINT64_C(0),	// V_CMP_GE_F32_e32_dpp_gfx11
    UINT64_C(2083258618), UINT64_C(0),	// V_CMP_GE_F32_e32_dpp_gfx12
    UINT64_C(2083258618), UINT64_C(0),	// V_CMP_GE_F32_e32_dpp_w32_gfx11
    UINT64_C(2083258618), UINT64_C(0),	// V_CMP_GE_F32_e32_dpp_w32_gfx12
    UINT64_C(2083258618), UINT64_C(0),	// V_CMP_GE_F32_e32_dpp_w64_gfx11
    UINT64_C(2083258618), UINT64_C(0),	// V_CMP_GE_F32_e32_dpp_w64_gfx12
    UINT64_C(2081161216), UINT64_C(0),	// V_CMP_GE_F32_e32_gfx10
    UINT64_C(2083258368), UINT64_C(0),	// V_CMP_GE_F32_e32_gfx11
    UINT64_C(2083258368), UINT64_C(0),	// V_CMP_GE_F32_e32_gfx12
    UINT64_C(2081161216), UINT64_C(0),	// V_CMP_GE_F32_e32_gfx6_gfx7
    UINT64_C(2089549824), UINT64_C(0),	// V_CMP_GE_F32_e32_vi
    UINT64_C(3558211584), UINT64_C(0),	// V_CMP_GE_F32_e64_dpp8_gfx11
    UINT64_C(3558211584), UINT64_C(0),	// V_CMP_GE_F32_e64_dpp8_gfx12
    UINT64_C(1077300035584), UINT64_C(0),	// V_CMP_GE_F32_e64_dpp_gfx11
    UINT64_C(1077300035584), UINT64_C(0),	// V_CMP_GE_F32_e64_dpp_gfx12
    UINT64_C(3557163008), UINT64_C(0),	// V_CMP_GE_F32_e64_gfx10
    UINT64_C(3558211584), UINT64_C(0),	// V_CMP_GE_F32_e64_gfx11
    UINT64_C(3558211584), UINT64_C(0),	// V_CMP_GE_F32_e64_gfx12
    UINT64_C(3490447360), UINT64_C(0),	// V_CMP_GE_F32_e64_gfx6_gfx7
    UINT64_C(3494248448), UINT64_C(0),	// V_CMP_GE_F32_e64_vi
    UINT64_C(2081161465), UINT64_C(0),	// V_CMP_GE_F32_sdwa_gfx10
    UINT64_C(2089550073), UINT64_C(0),	// V_CMP_GE_F32_sdwa_gfx9
    UINT64_C(2089550073), UINT64_C(0),	// V_CMP_GE_F32_sdwa_vi
    UINT64_C(2085355520), UINT64_C(0),	// V_CMP_GE_F64_e32_gfx10
    UINT64_C(2085355520), UINT64_C(0),	// V_CMP_GE_F64_e32_gfx11
    UINT64_C(2085355520), UINT64_C(0),	// V_CMP_GE_F64_e32_gfx12
    UINT64_C(2085355520), UINT64_C(0),	// V_CMP_GE_F64_e32_gfx6_gfx7
    UINT64_C(2093744128), UINT64_C(0),	// V_CMP_GE_F64_e32_vi
    UINT64_C(3559260160), UINT64_C(0),	// V_CMP_GE_F64_e64_gfx10
    UINT64_C(3559260160), UINT64_C(0),	// V_CMP_GE_F64_e64_gfx11
    UINT64_C(3559260160), UINT64_C(0),	// V_CMP_GE_F64_e64_gfx12
    UINT64_C(3494641664), UINT64_C(0),	// V_CMP_GE_F64_e64_gfx6_gfx7
    UINT64_C(3496345600), UINT64_C(0),	// V_CMP_GE_F64_e64_vi
    UINT64_C(2098987008), UINT64_C(0),	// V_CMP_GE_I16_e32_gfx10
    UINT64_C(2102132736), UINT64_C(0),	// V_CMP_GE_I16_e32_vi
    UINT64_C(3566075904), UINT64_C(0),	// V_CMP_GE_I16_e64_gfx10
    UINT64_C(3500539904), UINT64_C(0),	// V_CMP_GE_I16_e64_vi
    UINT64_C(2087452672), UINT64_C(0),	// V_CMP_GE_I16_fake16_e32_dpp8_gfx11
    UINT64_C(2087452672), UINT64_C(0),	// V_CMP_GE_I16_fake16_e32_dpp8_gfx12
    UINT64_C(2087452672), UINT64_C(0),	// V_CMP_GE_I16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2087452672), UINT64_C(0),	// V_CMP_GE_I16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2087452672), UINT64_C(0),	// V_CMP_GE_I16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2087452672), UINT64_C(0),	// V_CMP_GE_I16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2087452922), UINT64_C(0),	// V_CMP_GE_I16_fake16_e32_dpp_gfx11
    UINT64_C(2087452922), UINT64_C(0),	// V_CMP_GE_I16_fake16_e32_dpp_gfx12
    UINT64_C(2087452922), UINT64_C(0),	// V_CMP_GE_I16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2087452922), UINT64_C(0),	// V_CMP_GE_I16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2087452922), UINT64_C(0),	// V_CMP_GE_I16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2087452922), UINT64_C(0),	// V_CMP_GE_I16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2087452672), UINT64_C(0),	// V_CMP_GE_I16_fake16_e32_gfx11
    UINT64_C(2087452672), UINT64_C(0),	// V_CMP_GE_I16_fake16_e32_gfx12
    UINT64_C(3560308736), UINT64_C(0),	// V_CMP_GE_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3560308736), UINT64_C(0),	// V_CMP_GE_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077302132736), UINT64_C(0),	// V_CMP_GE_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077302132736), UINT64_C(0),	// V_CMP_GE_I16_fake16_e64_dpp_gfx12
    UINT64_C(3560308736), UINT64_C(0),	// V_CMP_GE_I16_fake16_e64_gfx11
    UINT64_C(3560308736), UINT64_C(0),	// V_CMP_GE_I16_fake16_e64_gfx12
    UINT64_C(2098987257), UINT64_C(0),	// V_CMP_GE_I16_sdwa_gfx10
    UINT64_C(2102132985), UINT64_C(0),	// V_CMP_GE_I16_sdwa_gfx9
    UINT64_C(2102132985), UINT64_C(0),	// V_CMP_GE_I16_sdwa_vi
    UINT64_C(2087452672), UINT64_C(0),	// V_CMP_GE_I16_t16_e32_dpp8_gfx11
    UINT64_C(2087452672), UINT64_C(0),	// V_CMP_GE_I16_t16_e32_dpp8_gfx12
    UINT64_C(2087452672), UINT64_C(0),	// V_CMP_GE_I16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2087452672), UINT64_C(0),	// V_CMP_GE_I16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2087452672), UINT64_C(0),	// V_CMP_GE_I16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2087452672), UINT64_C(0),	// V_CMP_GE_I16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2087452922), UINT64_C(0),	// V_CMP_GE_I16_t16_e32_dpp_gfx11
    UINT64_C(2087452922), UINT64_C(0),	// V_CMP_GE_I16_t16_e32_dpp_gfx12
    UINT64_C(2087452922), UINT64_C(0),	// V_CMP_GE_I16_t16_e32_dpp_w32_gfx11
    UINT64_C(2087452922), UINT64_C(0),	// V_CMP_GE_I16_t16_e32_dpp_w32_gfx12
    UINT64_C(2087452922), UINT64_C(0),	// V_CMP_GE_I16_t16_e32_dpp_w64_gfx11
    UINT64_C(2087452922), UINT64_C(0),	// V_CMP_GE_I16_t16_e32_dpp_w64_gfx12
    UINT64_C(2087452672), UINT64_C(0),	// V_CMP_GE_I16_t16_e32_gfx11
    UINT64_C(2087452672), UINT64_C(0),	// V_CMP_GE_I16_t16_e32_gfx12
    UINT64_C(3560308736), UINT64_C(0),	// V_CMP_GE_I16_t16_e64_dpp8_gfx11
    UINT64_C(3560308736), UINT64_C(0),	// V_CMP_GE_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077302132736), UINT64_C(0),	// V_CMP_GE_I16_t16_e64_dpp_gfx11
    UINT64_C(1077302132736), UINT64_C(0),	// V_CMP_GE_I16_t16_e64_dpp_gfx12
    UINT64_C(3560308736), UINT64_C(0),	// V_CMP_GE_I16_t16_e64_gfx11
    UINT64_C(3560308736), UINT64_C(0),	// V_CMP_GE_I16_t16_e64_gfx12
    UINT64_C(2089549824), UINT64_C(0),	// V_CMP_GE_I32_e32_dpp8_gfx11
    UINT64_C(2089549824), UINT64_C(0),	// V_CMP_GE_I32_e32_dpp8_gfx12
    UINT64_C(2089549824), UINT64_C(0),	// V_CMP_GE_I32_e32_dpp8_w32_gfx11
    UINT64_C(2089549824), UINT64_C(0),	// V_CMP_GE_I32_e32_dpp8_w32_gfx12
    UINT64_C(2089549824), UINT64_C(0),	// V_CMP_GE_I32_e32_dpp8_w64_gfx11
    UINT64_C(2089549824), UINT64_C(0),	// V_CMP_GE_I32_e32_dpp8_w64_gfx12
    UINT64_C(2089550074), UINT64_C(0),	// V_CMP_GE_I32_e32_dpp_gfx11
    UINT64_C(2089550074), UINT64_C(0),	// V_CMP_GE_I32_e32_dpp_gfx12
    UINT64_C(2089550074), UINT64_C(0),	// V_CMP_GE_I32_e32_dpp_w32_gfx11
    UINT64_C(2089550074), UINT64_C(0),	// V_CMP_GE_I32_e32_dpp_w32_gfx12
    UINT64_C(2089550074), UINT64_C(0),	// V_CMP_GE_I32_e32_dpp_w64_gfx11
    UINT64_C(2089550074), UINT64_C(0),	// V_CMP_GE_I32_e32_dpp_w64_gfx12
    UINT64_C(2097938432), UINT64_C(0),	// V_CMP_GE_I32_e32_gfx10
    UINT64_C(2089549824), UINT64_C(0),	// V_CMP_GE_I32_e32_gfx11
    UINT64_C(2089549824), UINT64_C(0),	// V_CMP_GE_I32_e32_gfx12
    UINT64_C(2097938432), UINT64_C(0),	// V_CMP_GE_I32_e32_gfx6_gfx7
    UINT64_C(2106327040), UINT64_C(0),	// V_CMP_GE_I32_e32_vi
    UINT64_C(3561357312), UINT64_C(0),	// V_CMP_GE_I32_e64_dpp8_gfx11
    UINT64_C(3561357312), UINT64_C(0),	// V_CMP_GE_I32_e64_dpp8_gfx12
    UINT64_C(1077303181312), UINT64_C(0),	// V_CMP_GE_I32_e64_dpp_gfx11
    UINT64_C(1077303181312), UINT64_C(0),	// V_CMP_GE_I32_e64_dpp_gfx12
    UINT64_C(3565551616), UINT64_C(0),	// V_CMP_GE_I32_e64_gfx10
    UINT64_C(3561357312), UINT64_C(0),	// V_CMP_GE_I32_e64_gfx11
    UINT64_C(3561357312), UINT64_C(0),	// V_CMP_GE_I32_e64_gfx12
    UINT64_C(3507224576), UINT64_C(0),	// V_CMP_GE_I32_e64_gfx6_gfx7
    UINT64_C(3502637056), UINT64_C(0),	// V_CMP_GE_I32_e64_vi
    UINT64_C(2097938681), UINT64_C(0),	// V_CMP_GE_I32_sdwa_gfx10
    UINT64_C(2106327289), UINT64_C(0),	// V_CMP_GE_I32_sdwa_gfx9
    UINT64_C(2106327289), UINT64_C(0),	// V_CMP_GE_I32_sdwa_vi
    UINT64_C(2102132736), UINT64_C(0),	// V_CMP_GE_I64_e32_gfx10
    UINT64_C(2091646976), UINT64_C(0),	// V_CMP_GE_I64_e32_gfx11
    UINT64_C(2091646976), UINT64_C(0),	// V_CMP_GE_I64_e32_gfx12
    UINT64_C(2102132736), UINT64_C(0),	// V_CMP_GE_I64_e32_gfx6_gfx7
    UINT64_C(2110521344), UINT64_C(0),	// V_CMP_GE_I64_e32_vi
    UINT64_C(3567648768), UINT64_C(0),	// V_CMP_GE_I64_e64_gfx10
    UINT64_C(3562405888), UINT64_C(0),	// V_CMP_GE_I64_e64_gfx11
    UINT64_C(3562405888), UINT64_C(0),	// V_CMP_GE_I64_e64_gfx12
    UINT64_C(3511418880), UINT64_C(0),	// V_CMP_GE_I64_e64_gfx6_gfx7
    UINT64_C(3504734208), UINT64_C(0),	// V_CMP_GE_I64_e64_vi
    UINT64_C(2103181312), UINT64_C(0),	// V_CMP_GE_U16_e32_gfx10
    UINT64_C(2103181312), UINT64_C(0),	// V_CMP_GE_U16_e32_vi
    UINT64_C(3568173056), UINT64_C(0),	// V_CMP_GE_U16_e64_gfx10
    UINT64_C(3501064192), UINT64_C(0),	// V_CMP_GE_U16_e64_vi
    UINT64_C(2088501248), UINT64_C(0),	// V_CMP_GE_U16_fake16_e32_dpp8_gfx11
    UINT64_C(2088501248), UINT64_C(0),	// V_CMP_GE_U16_fake16_e32_dpp8_gfx12
    UINT64_C(2088501248), UINT64_C(0),	// V_CMP_GE_U16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2088501248), UINT64_C(0),	// V_CMP_GE_U16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2088501248), UINT64_C(0),	// V_CMP_GE_U16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2088501248), UINT64_C(0),	// V_CMP_GE_U16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2088501498), UINT64_C(0),	// V_CMP_GE_U16_fake16_e32_dpp_gfx11
    UINT64_C(2088501498), UINT64_C(0),	// V_CMP_GE_U16_fake16_e32_dpp_gfx12
    UINT64_C(2088501498), UINT64_C(0),	// V_CMP_GE_U16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2088501498), UINT64_C(0),	// V_CMP_GE_U16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2088501498), UINT64_C(0),	// V_CMP_GE_U16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2088501498), UINT64_C(0),	// V_CMP_GE_U16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2088501248), UINT64_C(0),	// V_CMP_GE_U16_fake16_e32_gfx11
    UINT64_C(2088501248), UINT64_C(0),	// V_CMP_GE_U16_fake16_e32_gfx12
    UINT64_C(3560833024), UINT64_C(0),	// V_CMP_GE_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3560833024), UINT64_C(0),	// V_CMP_GE_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077302657024), UINT64_C(0),	// V_CMP_GE_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077302657024), UINT64_C(0),	// V_CMP_GE_U16_fake16_e64_dpp_gfx12
    UINT64_C(3560833024), UINT64_C(0),	// V_CMP_GE_U16_fake16_e64_gfx11
    UINT64_C(3560833024), UINT64_C(0),	// V_CMP_GE_U16_fake16_e64_gfx12
    UINT64_C(2103181561), UINT64_C(0),	// V_CMP_GE_U16_sdwa_gfx10
    UINT64_C(2103181561), UINT64_C(0),	// V_CMP_GE_U16_sdwa_gfx9
    UINT64_C(2103181561), UINT64_C(0),	// V_CMP_GE_U16_sdwa_vi
    UINT64_C(2088501248), UINT64_C(0),	// V_CMP_GE_U16_t16_e32_dpp8_gfx11
    UINT64_C(2088501248), UINT64_C(0),	// V_CMP_GE_U16_t16_e32_dpp8_gfx12
    UINT64_C(2088501248), UINT64_C(0),	// V_CMP_GE_U16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2088501248), UINT64_C(0),	// V_CMP_GE_U16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2088501248), UINT64_C(0),	// V_CMP_GE_U16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2088501248), UINT64_C(0),	// V_CMP_GE_U16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2088501498), UINT64_C(0),	// V_CMP_GE_U16_t16_e32_dpp_gfx11
    UINT64_C(2088501498), UINT64_C(0),	// V_CMP_GE_U16_t16_e32_dpp_gfx12
    UINT64_C(2088501498), UINT64_C(0),	// V_CMP_GE_U16_t16_e32_dpp_w32_gfx11
    UINT64_C(2088501498), UINT64_C(0),	// V_CMP_GE_U16_t16_e32_dpp_w32_gfx12
    UINT64_C(2088501498), UINT64_C(0),	// V_CMP_GE_U16_t16_e32_dpp_w64_gfx11
    UINT64_C(2088501498), UINT64_C(0),	// V_CMP_GE_U16_t16_e32_dpp_w64_gfx12
    UINT64_C(2088501248), UINT64_C(0),	// V_CMP_GE_U16_t16_e32_gfx11
    UINT64_C(2088501248), UINT64_C(0),	// V_CMP_GE_U16_t16_e32_gfx12
    UINT64_C(3560833024), UINT64_C(0),	// V_CMP_GE_U16_t16_e64_dpp8_gfx11
    UINT64_C(3560833024), UINT64_C(0),	// V_CMP_GE_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077302657024), UINT64_C(0),	// V_CMP_GE_U16_t16_e64_dpp_gfx11
    UINT64_C(1077302657024), UINT64_C(0),	// V_CMP_GE_U16_t16_e64_dpp_gfx12
    UINT64_C(3560833024), UINT64_C(0),	// V_CMP_GE_U16_t16_e64_gfx11
    UINT64_C(3560833024), UINT64_C(0),	// V_CMP_GE_U16_t16_e64_gfx12
    UINT64_C(2090598400), UINT64_C(0),	// V_CMP_GE_U32_e32_dpp8_gfx11
    UINT64_C(2090598400), UINT64_C(0),	// V_CMP_GE_U32_e32_dpp8_gfx12
    UINT64_C(2090598400), UINT64_C(0),	// V_CMP_GE_U32_e32_dpp8_w32_gfx11
    UINT64_C(2090598400), UINT64_C(0),	// V_CMP_GE_U32_e32_dpp8_w32_gfx12
    UINT64_C(2090598400), UINT64_C(0),	// V_CMP_GE_U32_e32_dpp8_w64_gfx11
    UINT64_C(2090598400), UINT64_C(0),	// V_CMP_GE_U32_e32_dpp8_w64_gfx12
    UINT64_C(2090598650), UINT64_C(0),	// V_CMP_GE_U32_e32_dpp_gfx11
    UINT64_C(2090598650), UINT64_C(0),	// V_CMP_GE_U32_e32_dpp_gfx12
    UINT64_C(2090598650), UINT64_C(0),	// V_CMP_GE_U32_e32_dpp_w32_gfx11
    UINT64_C(2090598650), UINT64_C(0),	// V_CMP_GE_U32_e32_dpp_w32_gfx12
    UINT64_C(2090598650), UINT64_C(0),	// V_CMP_GE_U32_e32_dpp_w64_gfx11
    UINT64_C(2090598650), UINT64_C(0),	// V_CMP_GE_U32_e32_dpp_w64_gfx12
    UINT64_C(2106327040), UINT64_C(0),	// V_CMP_GE_U32_e32_gfx10
    UINT64_C(2090598400), UINT64_C(0),	// V_CMP_GE_U32_e32_gfx11
    UINT64_C(2090598400), UINT64_C(0),	// V_CMP_GE_U32_e32_gfx12
    UINT64_C(2106327040), UINT64_C(0),	// V_CMP_GE_U32_e32_gfx6_gfx7
    UINT64_C(2107375616), UINT64_C(0),	// V_CMP_GE_U32_e32_vi
    UINT64_C(3561881600), UINT64_C(0),	// V_CMP_GE_U32_e64_dpp8_gfx11
    UINT64_C(3561881600), UINT64_C(0),	// V_CMP_GE_U32_e64_dpp8_gfx12
    UINT64_C(1077303705600), UINT64_C(0),	// V_CMP_GE_U32_e64_dpp_gfx11
    UINT64_C(1077303705600), UINT64_C(0),	// V_CMP_GE_U32_e64_dpp_gfx12
    UINT64_C(3569745920), UINT64_C(0),	// V_CMP_GE_U32_e64_gfx10
    UINT64_C(3561881600), UINT64_C(0),	// V_CMP_GE_U32_e64_gfx11
    UINT64_C(3561881600), UINT64_C(0),	// V_CMP_GE_U32_e64_gfx12
    UINT64_C(3515613184), UINT64_C(0),	// V_CMP_GE_U32_e64_gfx6_gfx7
    UINT64_C(3503161344), UINT64_C(0),	// V_CMP_GE_U32_e64_vi
    UINT64_C(2106327289), UINT64_C(0),	// V_CMP_GE_U32_sdwa_gfx10
    UINT64_C(2107375865), UINT64_C(0),	// V_CMP_GE_U32_sdwa_gfx9
    UINT64_C(2107375865), UINT64_C(0),	// V_CMP_GE_U32_sdwa_vi
    UINT64_C(2110521344), UINT64_C(0),	// V_CMP_GE_U64_e32_gfx10
    UINT64_C(2092695552), UINT64_C(0),	// V_CMP_GE_U64_e32_gfx11
    UINT64_C(2092695552), UINT64_C(0),	// V_CMP_GE_U64_e32_gfx12
    UINT64_C(2110521344), UINT64_C(0),	// V_CMP_GE_U64_e32_gfx6_gfx7
    UINT64_C(2111569920), UINT64_C(0),	// V_CMP_GE_U64_e32_vi
    UINT64_C(3571843072), UINT64_C(0),	// V_CMP_GE_U64_e64_gfx10
    UINT64_C(3562930176), UINT64_C(0),	// V_CMP_GE_U64_e64_gfx11
    UINT64_C(3562930176), UINT64_C(0),	// V_CMP_GE_U64_e64_gfx12
    UINT64_C(3519807488), UINT64_C(0),	// V_CMP_GE_U64_e64_gfx6_gfx7
    UINT64_C(3505258496), UINT64_C(0),	// V_CMP_GE_U64_e64_vi
    UINT64_C(2107113472), UINT64_C(0),	// V_CMP_GT_F16_e32_gfx10
    UINT64_C(2085093376), UINT64_C(0),	// V_CMP_GT_F16_e32_vi
    UINT64_C(3570139136), UINT64_C(0),	// V_CMP_GT_F16_e64_gfx10
    UINT64_C(3492020224), UINT64_C(0),	// V_CMP_GT_F16_e64_vi
    UINT64_C(2080899072), UINT64_C(0),	// V_CMP_GT_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2080899072), UINT64_C(0),	// V_CMP_GT_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2080899072), UINT64_C(0),	// V_CMP_GT_F16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2080899072), UINT64_C(0),	// V_CMP_GT_F16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2080899072), UINT64_C(0),	// V_CMP_GT_F16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2080899072), UINT64_C(0),	// V_CMP_GT_F16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2080899322), UINT64_C(0),	// V_CMP_GT_F16_fake16_e32_dpp_gfx11
    UINT64_C(2080899322), UINT64_C(0),	// V_CMP_GT_F16_fake16_e32_dpp_gfx12
    UINT64_C(2080899322), UINT64_C(0),	// V_CMP_GT_F16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2080899322), UINT64_C(0),	// V_CMP_GT_F16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2080899322), UINT64_C(0),	// V_CMP_GT_F16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2080899322), UINT64_C(0),	// V_CMP_GT_F16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2080899072), UINT64_C(0),	// V_CMP_GT_F16_fake16_e32_gfx11
    UINT64_C(2080899072), UINT64_C(0),	// V_CMP_GT_F16_fake16_e32_gfx12
    UINT64_C(3557031936), UINT64_C(0),	// V_CMP_GT_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3557031936), UINT64_C(0),	// V_CMP_GT_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077298855936), UINT64_C(0),	// V_CMP_GT_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077298855936), UINT64_C(0),	// V_CMP_GT_F16_fake16_e64_dpp_gfx12
    UINT64_C(3557031936), UINT64_C(0),	// V_CMP_GT_F16_fake16_e64_gfx11
    UINT64_C(3557031936), UINT64_C(0),	// V_CMP_GT_F16_fake16_e64_gfx12
    UINT64_C(2107113721), UINT64_C(0),	// V_CMP_GT_F16_sdwa_gfx10
    UINT64_C(2085093625), UINT64_C(0),	// V_CMP_GT_F16_sdwa_gfx9
    UINT64_C(2085093625), UINT64_C(0),	// V_CMP_GT_F16_sdwa_vi
    UINT64_C(2080899072), UINT64_C(0),	// V_CMP_GT_F16_t16_e32_dpp8_gfx11
    UINT64_C(2080899072), UINT64_C(0),	// V_CMP_GT_F16_t16_e32_dpp8_gfx12
    UINT64_C(2080899072), UINT64_C(0),	// V_CMP_GT_F16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2080899072), UINT64_C(0),	// V_CMP_GT_F16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2080899072), UINT64_C(0),	// V_CMP_GT_F16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2080899072), UINT64_C(0),	// V_CMP_GT_F16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2080899322), UINT64_C(0),	// V_CMP_GT_F16_t16_e32_dpp_gfx11
    UINT64_C(2080899322), UINT64_C(0),	// V_CMP_GT_F16_t16_e32_dpp_gfx12
    UINT64_C(2080899322), UINT64_C(0),	// V_CMP_GT_F16_t16_e32_dpp_w32_gfx11
    UINT64_C(2080899322), UINT64_C(0),	// V_CMP_GT_F16_t16_e32_dpp_w32_gfx12
    UINT64_C(2080899322), UINT64_C(0),	// V_CMP_GT_F16_t16_e32_dpp_w64_gfx11
    UINT64_C(2080899322), UINT64_C(0),	// V_CMP_GT_F16_t16_e32_dpp_w64_gfx12
    UINT64_C(2080899072), UINT64_C(0),	// V_CMP_GT_F16_t16_e32_gfx11
    UINT64_C(2080899072), UINT64_C(0),	// V_CMP_GT_F16_t16_e32_gfx12
    UINT64_C(3557031936), UINT64_C(0),	// V_CMP_GT_F16_t16_e64_dpp8_gfx11
    UINT64_C(3557031936), UINT64_C(0),	// V_CMP_GT_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077298855936), UINT64_C(0),	// V_CMP_GT_F16_t16_e64_dpp_gfx11
    UINT64_C(1077298855936), UINT64_C(0),	// V_CMP_GT_F16_t16_e64_dpp_gfx12
    UINT64_C(3557031936), UINT64_C(0),	// V_CMP_GT_F16_t16_e64_gfx11
    UINT64_C(3557031936), UINT64_C(0),	// V_CMP_GT_F16_t16_e64_gfx12
    UINT64_C(2082996224), UINT64_C(0),	// V_CMP_GT_F32_e32_dpp8_gfx11
    UINT64_C(2082996224), UINT64_C(0),	// V_CMP_GT_F32_e32_dpp8_gfx12
    UINT64_C(2082996224), UINT64_C(0),	// V_CMP_GT_F32_e32_dpp8_w32_gfx11
    UINT64_C(2082996224), UINT64_C(0),	// V_CMP_GT_F32_e32_dpp8_w32_gfx12
    UINT64_C(2082996224), UINT64_C(0),	// V_CMP_GT_F32_e32_dpp8_w64_gfx11
    UINT64_C(2082996224), UINT64_C(0),	// V_CMP_GT_F32_e32_dpp8_w64_gfx12
    UINT64_C(2082996474), UINT64_C(0),	// V_CMP_GT_F32_e32_dpp_gfx11
    UINT64_C(2082996474), UINT64_C(0),	// V_CMP_GT_F32_e32_dpp_gfx12
    UINT64_C(2082996474), UINT64_C(0),	// V_CMP_GT_F32_e32_dpp_w32_gfx11
    UINT64_C(2082996474), UINT64_C(0),	// V_CMP_GT_F32_e32_dpp_w32_gfx12
    UINT64_C(2082996474), UINT64_C(0),	// V_CMP_GT_F32_e32_dpp_w64_gfx11
    UINT64_C(2082996474), UINT64_C(0),	// V_CMP_GT_F32_e32_dpp_w64_gfx12
    UINT64_C(2080899072), UINT64_C(0),	// V_CMP_GT_F32_e32_gfx10
    UINT64_C(2082996224), UINT64_C(0),	// V_CMP_GT_F32_e32_gfx11
    UINT64_C(2082996224), UINT64_C(0),	// V_CMP_GT_F32_e32_gfx12
    UINT64_C(2080899072), UINT64_C(0),	// V_CMP_GT_F32_e32_gfx6_gfx7
    UINT64_C(2089287680), UINT64_C(0),	// V_CMP_GT_F32_e32_vi
    UINT64_C(3558080512), UINT64_C(0),	// V_CMP_GT_F32_e64_dpp8_gfx11
    UINT64_C(3558080512), UINT64_C(0),	// V_CMP_GT_F32_e64_dpp8_gfx12
    UINT64_C(1077299904512), UINT64_C(0),	// V_CMP_GT_F32_e64_dpp_gfx11
    UINT64_C(1077299904512), UINT64_C(0),	// V_CMP_GT_F32_e64_dpp_gfx12
    UINT64_C(3557031936), UINT64_C(0),	// V_CMP_GT_F32_e64_gfx10
    UINT64_C(3558080512), UINT64_C(0),	// V_CMP_GT_F32_e64_gfx11
    UINT64_C(3558080512), UINT64_C(0),	// V_CMP_GT_F32_e64_gfx12
    UINT64_C(3490185216), UINT64_C(0),	// V_CMP_GT_F32_e64_gfx6_gfx7
    UINT64_C(3494117376), UINT64_C(0),	// V_CMP_GT_F32_e64_vi
    UINT64_C(2080899321), UINT64_C(0),	// V_CMP_GT_F32_sdwa_gfx10
    UINT64_C(2089287929), UINT64_C(0),	// V_CMP_GT_F32_sdwa_gfx9
    UINT64_C(2089287929), UINT64_C(0),	// V_CMP_GT_F32_sdwa_vi
    UINT64_C(2085093376), UINT64_C(0),	// V_CMP_GT_F64_e32_gfx10
    UINT64_C(2085093376), UINT64_C(0),	// V_CMP_GT_F64_e32_gfx11
    UINT64_C(2085093376), UINT64_C(0),	// V_CMP_GT_F64_e32_gfx12
    UINT64_C(2085093376), UINT64_C(0),	// V_CMP_GT_F64_e32_gfx6_gfx7
    UINT64_C(2093481984), UINT64_C(0),	// V_CMP_GT_F64_e32_vi
    UINT64_C(3559129088), UINT64_C(0),	// V_CMP_GT_F64_e64_gfx10
    UINT64_C(3559129088), UINT64_C(0),	// V_CMP_GT_F64_e64_gfx11
    UINT64_C(3559129088), UINT64_C(0),	// V_CMP_GT_F64_e64_gfx12
    UINT64_C(3494379520), UINT64_C(0),	// V_CMP_GT_F64_e64_gfx6_gfx7
    UINT64_C(3496214528), UINT64_C(0),	// V_CMP_GT_F64_e64_vi
    UINT64_C(2098724864), UINT64_C(0),	// V_CMP_GT_I16_e32_gfx10
    UINT64_C(2101870592), UINT64_C(0),	// V_CMP_GT_I16_e32_vi
    UINT64_C(3565944832), UINT64_C(0),	// V_CMP_GT_I16_e64_gfx10
    UINT64_C(3500408832), UINT64_C(0),	// V_CMP_GT_I16_e64_vi
    UINT64_C(2087190528), UINT64_C(0),	// V_CMP_GT_I16_fake16_e32_dpp8_gfx11
    UINT64_C(2087190528), UINT64_C(0),	// V_CMP_GT_I16_fake16_e32_dpp8_gfx12
    UINT64_C(2087190528), UINT64_C(0),	// V_CMP_GT_I16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2087190528), UINT64_C(0),	// V_CMP_GT_I16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2087190528), UINT64_C(0),	// V_CMP_GT_I16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2087190528), UINT64_C(0),	// V_CMP_GT_I16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2087190778), UINT64_C(0),	// V_CMP_GT_I16_fake16_e32_dpp_gfx11
    UINT64_C(2087190778), UINT64_C(0),	// V_CMP_GT_I16_fake16_e32_dpp_gfx12
    UINT64_C(2087190778), UINT64_C(0),	// V_CMP_GT_I16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2087190778), UINT64_C(0),	// V_CMP_GT_I16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2087190778), UINT64_C(0),	// V_CMP_GT_I16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2087190778), UINT64_C(0),	// V_CMP_GT_I16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2087190528), UINT64_C(0),	// V_CMP_GT_I16_fake16_e32_gfx11
    UINT64_C(2087190528), UINT64_C(0),	// V_CMP_GT_I16_fake16_e32_gfx12
    UINT64_C(3560177664), UINT64_C(0),	// V_CMP_GT_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3560177664), UINT64_C(0),	// V_CMP_GT_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077302001664), UINT64_C(0),	// V_CMP_GT_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077302001664), UINT64_C(0),	// V_CMP_GT_I16_fake16_e64_dpp_gfx12
    UINT64_C(3560177664), UINT64_C(0),	// V_CMP_GT_I16_fake16_e64_gfx11
    UINT64_C(3560177664), UINT64_C(0),	// V_CMP_GT_I16_fake16_e64_gfx12
    UINT64_C(2098725113), UINT64_C(0),	// V_CMP_GT_I16_sdwa_gfx10
    UINT64_C(2101870841), UINT64_C(0),	// V_CMP_GT_I16_sdwa_gfx9
    UINT64_C(2101870841), UINT64_C(0),	// V_CMP_GT_I16_sdwa_vi
    UINT64_C(2087190528), UINT64_C(0),	// V_CMP_GT_I16_t16_e32_dpp8_gfx11
    UINT64_C(2087190528), UINT64_C(0),	// V_CMP_GT_I16_t16_e32_dpp8_gfx12
    UINT64_C(2087190528), UINT64_C(0),	// V_CMP_GT_I16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2087190528), UINT64_C(0),	// V_CMP_GT_I16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2087190528), UINT64_C(0),	// V_CMP_GT_I16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2087190528), UINT64_C(0),	// V_CMP_GT_I16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2087190778), UINT64_C(0),	// V_CMP_GT_I16_t16_e32_dpp_gfx11
    UINT64_C(2087190778), UINT64_C(0),	// V_CMP_GT_I16_t16_e32_dpp_gfx12
    UINT64_C(2087190778), UINT64_C(0),	// V_CMP_GT_I16_t16_e32_dpp_w32_gfx11
    UINT64_C(2087190778), UINT64_C(0),	// V_CMP_GT_I16_t16_e32_dpp_w32_gfx12
    UINT64_C(2087190778), UINT64_C(0),	// V_CMP_GT_I16_t16_e32_dpp_w64_gfx11
    UINT64_C(2087190778), UINT64_C(0),	// V_CMP_GT_I16_t16_e32_dpp_w64_gfx12
    UINT64_C(2087190528), UINT64_C(0),	// V_CMP_GT_I16_t16_e32_gfx11
    UINT64_C(2087190528), UINT64_C(0),	// V_CMP_GT_I16_t16_e32_gfx12
    UINT64_C(3560177664), UINT64_C(0),	// V_CMP_GT_I16_t16_e64_dpp8_gfx11
    UINT64_C(3560177664), UINT64_C(0),	// V_CMP_GT_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077302001664), UINT64_C(0),	// V_CMP_GT_I16_t16_e64_dpp_gfx11
    UINT64_C(1077302001664), UINT64_C(0),	// V_CMP_GT_I16_t16_e64_dpp_gfx12
    UINT64_C(3560177664), UINT64_C(0),	// V_CMP_GT_I16_t16_e64_gfx11
    UINT64_C(3560177664), UINT64_C(0),	// V_CMP_GT_I16_t16_e64_gfx12
    UINT64_C(2089287680), UINT64_C(0),	// V_CMP_GT_I32_e32_dpp8_gfx11
    UINT64_C(2089287680), UINT64_C(0),	// V_CMP_GT_I32_e32_dpp8_gfx12
    UINT64_C(2089287680), UINT64_C(0),	// V_CMP_GT_I32_e32_dpp8_w32_gfx11
    UINT64_C(2089287680), UINT64_C(0),	// V_CMP_GT_I32_e32_dpp8_w32_gfx12
    UINT64_C(2089287680), UINT64_C(0),	// V_CMP_GT_I32_e32_dpp8_w64_gfx11
    UINT64_C(2089287680), UINT64_C(0),	// V_CMP_GT_I32_e32_dpp8_w64_gfx12
    UINT64_C(2089287930), UINT64_C(0),	// V_CMP_GT_I32_e32_dpp_gfx11
    UINT64_C(2089287930), UINT64_C(0),	// V_CMP_GT_I32_e32_dpp_gfx12
    UINT64_C(2089287930), UINT64_C(0),	// V_CMP_GT_I32_e32_dpp_w32_gfx11
    UINT64_C(2089287930), UINT64_C(0),	// V_CMP_GT_I32_e32_dpp_w32_gfx12
    UINT64_C(2089287930), UINT64_C(0),	// V_CMP_GT_I32_e32_dpp_w64_gfx11
    UINT64_C(2089287930), UINT64_C(0),	// V_CMP_GT_I32_e32_dpp_w64_gfx12
    UINT64_C(2097676288), UINT64_C(0),	// V_CMP_GT_I32_e32_gfx10
    UINT64_C(2089287680), UINT64_C(0),	// V_CMP_GT_I32_e32_gfx11
    UINT64_C(2089287680), UINT64_C(0),	// V_CMP_GT_I32_e32_gfx12
    UINT64_C(2097676288), UINT64_C(0),	// V_CMP_GT_I32_e32_gfx6_gfx7
    UINT64_C(2106064896), UINT64_C(0),	// V_CMP_GT_I32_e32_vi
    UINT64_C(3561226240), UINT64_C(0),	// V_CMP_GT_I32_e64_dpp8_gfx11
    UINT64_C(3561226240), UINT64_C(0),	// V_CMP_GT_I32_e64_dpp8_gfx12
    UINT64_C(1077303050240), UINT64_C(0),	// V_CMP_GT_I32_e64_dpp_gfx11
    UINT64_C(1077303050240), UINT64_C(0),	// V_CMP_GT_I32_e64_dpp_gfx12
    UINT64_C(3565420544), UINT64_C(0),	// V_CMP_GT_I32_e64_gfx10
    UINT64_C(3561226240), UINT64_C(0),	// V_CMP_GT_I32_e64_gfx11
    UINT64_C(3561226240), UINT64_C(0),	// V_CMP_GT_I32_e64_gfx12
    UINT64_C(3506962432), UINT64_C(0),	// V_CMP_GT_I32_e64_gfx6_gfx7
    UINT64_C(3502505984), UINT64_C(0),	// V_CMP_GT_I32_e64_vi
    UINT64_C(2097676537), UINT64_C(0),	// V_CMP_GT_I32_sdwa_gfx10
    UINT64_C(2106065145), UINT64_C(0),	// V_CMP_GT_I32_sdwa_gfx9
    UINT64_C(2106065145), UINT64_C(0),	// V_CMP_GT_I32_sdwa_vi
    UINT64_C(2101870592), UINT64_C(0),	// V_CMP_GT_I64_e32_gfx10
    UINT64_C(2091384832), UINT64_C(0),	// V_CMP_GT_I64_e32_gfx11
    UINT64_C(2091384832), UINT64_C(0),	// V_CMP_GT_I64_e32_gfx12
    UINT64_C(2101870592), UINT64_C(0),	// V_CMP_GT_I64_e32_gfx6_gfx7
    UINT64_C(2110259200), UINT64_C(0),	// V_CMP_GT_I64_e32_vi
    UINT64_C(3567517696), UINT64_C(0),	// V_CMP_GT_I64_e64_gfx10
    UINT64_C(3562274816), UINT64_C(0),	// V_CMP_GT_I64_e64_gfx11
    UINT64_C(3562274816), UINT64_C(0),	// V_CMP_GT_I64_e64_gfx12
    UINT64_C(3511156736), UINT64_C(0),	// V_CMP_GT_I64_e64_gfx6_gfx7
    UINT64_C(3504603136), UINT64_C(0),	// V_CMP_GT_I64_e64_vi
    UINT64_C(2102919168), UINT64_C(0),	// V_CMP_GT_U16_e32_gfx10
    UINT64_C(2102919168), UINT64_C(0),	// V_CMP_GT_U16_e32_vi
    UINT64_C(3568041984), UINT64_C(0),	// V_CMP_GT_U16_e64_gfx10
    UINT64_C(3500933120), UINT64_C(0),	// V_CMP_GT_U16_e64_vi
    UINT64_C(2088239104), UINT64_C(0),	// V_CMP_GT_U16_fake16_e32_dpp8_gfx11
    UINT64_C(2088239104), UINT64_C(0),	// V_CMP_GT_U16_fake16_e32_dpp8_gfx12
    UINT64_C(2088239104), UINT64_C(0),	// V_CMP_GT_U16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2088239104), UINT64_C(0),	// V_CMP_GT_U16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2088239104), UINT64_C(0),	// V_CMP_GT_U16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2088239104), UINT64_C(0),	// V_CMP_GT_U16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2088239354), UINT64_C(0),	// V_CMP_GT_U16_fake16_e32_dpp_gfx11
    UINT64_C(2088239354), UINT64_C(0),	// V_CMP_GT_U16_fake16_e32_dpp_gfx12
    UINT64_C(2088239354), UINT64_C(0),	// V_CMP_GT_U16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2088239354), UINT64_C(0),	// V_CMP_GT_U16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2088239354), UINT64_C(0),	// V_CMP_GT_U16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2088239354), UINT64_C(0),	// V_CMP_GT_U16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2088239104), UINT64_C(0),	// V_CMP_GT_U16_fake16_e32_gfx11
    UINT64_C(2088239104), UINT64_C(0),	// V_CMP_GT_U16_fake16_e32_gfx12
    UINT64_C(3560701952), UINT64_C(0),	// V_CMP_GT_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3560701952), UINT64_C(0),	// V_CMP_GT_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077302525952), UINT64_C(0),	// V_CMP_GT_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077302525952), UINT64_C(0),	// V_CMP_GT_U16_fake16_e64_dpp_gfx12
    UINT64_C(3560701952), UINT64_C(0),	// V_CMP_GT_U16_fake16_e64_gfx11
    UINT64_C(3560701952), UINT64_C(0),	// V_CMP_GT_U16_fake16_e64_gfx12
    UINT64_C(2102919417), UINT64_C(0),	// V_CMP_GT_U16_sdwa_gfx10
    UINT64_C(2102919417), UINT64_C(0),	// V_CMP_GT_U16_sdwa_gfx9
    UINT64_C(2102919417), UINT64_C(0),	// V_CMP_GT_U16_sdwa_vi
    UINT64_C(2088239104), UINT64_C(0),	// V_CMP_GT_U16_t16_e32_dpp8_gfx11
    UINT64_C(2088239104), UINT64_C(0),	// V_CMP_GT_U16_t16_e32_dpp8_gfx12
    UINT64_C(2088239104), UINT64_C(0),	// V_CMP_GT_U16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2088239104), UINT64_C(0),	// V_CMP_GT_U16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2088239104), UINT64_C(0),	// V_CMP_GT_U16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2088239104), UINT64_C(0),	// V_CMP_GT_U16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2088239354), UINT64_C(0),	// V_CMP_GT_U16_t16_e32_dpp_gfx11
    UINT64_C(2088239354), UINT64_C(0),	// V_CMP_GT_U16_t16_e32_dpp_gfx12
    UINT64_C(2088239354), UINT64_C(0),	// V_CMP_GT_U16_t16_e32_dpp_w32_gfx11
    UINT64_C(2088239354), UINT64_C(0),	// V_CMP_GT_U16_t16_e32_dpp_w32_gfx12
    UINT64_C(2088239354), UINT64_C(0),	// V_CMP_GT_U16_t16_e32_dpp_w64_gfx11
    UINT64_C(2088239354), UINT64_C(0),	// V_CMP_GT_U16_t16_e32_dpp_w64_gfx12
    UINT64_C(2088239104), UINT64_C(0),	// V_CMP_GT_U16_t16_e32_gfx11
    UINT64_C(2088239104), UINT64_C(0),	// V_CMP_GT_U16_t16_e32_gfx12
    UINT64_C(3560701952), UINT64_C(0),	// V_CMP_GT_U16_t16_e64_dpp8_gfx11
    UINT64_C(3560701952), UINT64_C(0),	// V_CMP_GT_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077302525952), UINT64_C(0),	// V_CMP_GT_U16_t16_e64_dpp_gfx11
    UINT64_C(1077302525952), UINT64_C(0),	// V_CMP_GT_U16_t16_e64_dpp_gfx12
    UINT64_C(3560701952), UINT64_C(0),	// V_CMP_GT_U16_t16_e64_gfx11
    UINT64_C(3560701952), UINT64_C(0),	// V_CMP_GT_U16_t16_e64_gfx12
    UINT64_C(2090336256), UINT64_C(0),	// V_CMP_GT_U32_e32_dpp8_gfx11
    UINT64_C(2090336256), UINT64_C(0),	// V_CMP_GT_U32_e32_dpp8_gfx12
    UINT64_C(2090336256), UINT64_C(0),	// V_CMP_GT_U32_e32_dpp8_w32_gfx11
    UINT64_C(2090336256), UINT64_C(0),	// V_CMP_GT_U32_e32_dpp8_w32_gfx12
    UINT64_C(2090336256), UINT64_C(0),	// V_CMP_GT_U32_e32_dpp8_w64_gfx11
    UINT64_C(2090336256), UINT64_C(0),	// V_CMP_GT_U32_e32_dpp8_w64_gfx12
    UINT64_C(2090336506), UINT64_C(0),	// V_CMP_GT_U32_e32_dpp_gfx11
    UINT64_C(2090336506), UINT64_C(0),	// V_CMP_GT_U32_e32_dpp_gfx12
    UINT64_C(2090336506), UINT64_C(0),	// V_CMP_GT_U32_e32_dpp_w32_gfx11
    UINT64_C(2090336506), UINT64_C(0),	// V_CMP_GT_U32_e32_dpp_w32_gfx12
    UINT64_C(2090336506), UINT64_C(0),	// V_CMP_GT_U32_e32_dpp_w64_gfx11
    UINT64_C(2090336506), UINT64_C(0),	// V_CMP_GT_U32_e32_dpp_w64_gfx12
    UINT64_C(2106064896), UINT64_C(0),	// V_CMP_GT_U32_e32_gfx10
    UINT64_C(2090336256), UINT64_C(0),	// V_CMP_GT_U32_e32_gfx11
    UINT64_C(2090336256), UINT64_C(0),	// V_CMP_GT_U32_e32_gfx12
    UINT64_C(2106064896), UINT64_C(0),	// V_CMP_GT_U32_e32_gfx6_gfx7
    UINT64_C(2107113472), UINT64_C(0),	// V_CMP_GT_U32_e32_vi
    UINT64_C(3561750528), UINT64_C(0),	// V_CMP_GT_U32_e64_dpp8_gfx11
    UINT64_C(3561750528), UINT64_C(0),	// V_CMP_GT_U32_e64_dpp8_gfx12
    UINT64_C(1077303574528), UINT64_C(0),	// V_CMP_GT_U32_e64_dpp_gfx11
    UINT64_C(1077303574528), UINT64_C(0),	// V_CMP_GT_U32_e64_dpp_gfx12
    UINT64_C(3569614848), UINT64_C(0),	// V_CMP_GT_U32_e64_gfx10
    UINT64_C(3561750528), UINT64_C(0),	// V_CMP_GT_U32_e64_gfx11
    UINT64_C(3561750528), UINT64_C(0),	// V_CMP_GT_U32_e64_gfx12
    UINT64_C(3515351040), UINT64_C(0),	// V_CMP_GT_U32_e64_gfx6_gfx7
    UINT64_C(3503030272), UINT64_C(0),	// V_CMP_GT_U32_e64_vi
    UINT64_C(2106065145), UINT64_C(0),	// V_CMP_GT_U32_sdwa_gfx10
    UINT64_C(2107113721), UINT64_C(0),	// V_CMP_GT_U32_sdwa_gfx9
    UINT64_C(2107113721), UINT64_C(0),	// V_CMP_GT_U32_sdwa_vi
    UINT64_C(2110259200), UINT64_C(0),	// V_CMP_GT_U64_e32_gfx10
    UINT64_C(2092433408), UINT64_C(0),	// V_CMP_GT_U64_e32_gfx11
    UINT64_C(2092433408), UINT64_C(0),	// V_CMP_GT_U64_e32_gfx12
    UINT64_C(2110259200), UINT64_C(0),	// V_CMP_GT_U64_e32_gfx6_gfx7
    UINT64_C(2111307776), UINT64_C(0),	// V_CMP_GT_U64_e32_vi
    UINT64_C(3571712000), UINT64_C(0),	// V_CMP_GT_U64_e64_gfx10
    UINT64_C(3562799104), UINT64_C(0),	// V_CMP_GT_U64_e64_gfx11
    UINT64_C(3562799104), UINT64_C(0),	// V_CMP_GT_U64_e64_gfx12
    UINT64_C(3519545344), UINT64_C(0),	// V_CMP_GT_U64_e64_gfx6_gfx7
    UINT64_C(3505127424), UINT64_C(0),	// V_CMP_GT_U64_e64_vi
    UINT64_C(2106982400), UINT64_C(0),	// V_CMP_LE_F16_e32_gfx10
    UINT64_C(2084962304), UINT64_C(0),	// V_CMP_LE_F16_e32_vi
    UINT64_C(3570073600), UINT64_C(0),	// V_CMP_LE_F16_e64_gfx10
    UINT64_C(3491954688), UINT64_C(0),	// V_CMP_LE_F16_e64_vi
    UINT64_C(2080768000), UINT64_C(0),	// V_CMP_LE_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2080768000), UINT64_C(0),	// V_CMP_LE_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2080768000), UINT64_C(0),	// V_CMP_LE_F16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2080768000), UINT64_C(0),	// V_CMP_LE_F16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2080768000), UINT64_C(0),	// V_CMP_LE_F16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2080768000), UINT64_C(0),	// V_CMP_LE_F16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2080768250), UINT64_C(0),	// V_CMP_LE_F16_fake16_e32_dpp_gfx11
    UINT64_C(2080768250), UINT64_C(0),	// V_CMP_LE_F16_fake16_e32_dpp_gfx12
    UINT64_C(2080768250), UINT64_C(0),	// V_CMP_LE_F16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2080768250), UINT64_C(0),	// V_CMP_LE_F16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2080768250), UINT64_C(0),	// V_CMP_LE_F16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2080768250), UINT64_C(0),	// V_CMP_LE_F16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2080768000), UINT64_C(0),	// V_CMP_LE_F16_fake16_e32_gfx11
    UINT64_C(2080768000), UINT64_C(0),	// V_CMP_LE_F16_fake16_e32_gfx12
    UINT64_C(3556966400), UINT64_C(0),	// V_CMP_LE_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3556966400), UINT64_C(0),	// V_CMP_LE_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077298790400), UINT64_C(0),	// V_CMP_LE_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077298790400), UINT64_C(0),	// V_CMP_LE_F16_fake16_e64_dpp_gfx12
    UINT64_C(3556966400), UINT64_C(0),	// V_CMP_LE_F16_fake16_e64_gfx11
    UINT64_C(3556966400), UINT64_C(0),	// V_CMP_LE_F16_fake16_e64_gfx12
    UINT64_C(2106982649), UINT64_C(0),	// V_CMP_LE_F16_sdwa_gfx10
    UINT64_C(2084962553), UINT64_C(0),	// V_CMP_LE_F16_sdwa_gfx9
    UINT64_C(2084962553), UINT64_C(0),	// V_CMP_LE_F16_sdwa_vi
    UINT64_C(2080768000), UINT64_C(0),	// V_CMP_LE_F16_t16_e32_dpp8_gfx11
    UINT64_C(2080768000), UINT64_C(0),	// V_CMP_LE_F16_t16_e32_dpp8_gfx12
    UINT64_C(2080768000), UINT64_C(0),	// V_CMP_LE_F16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2080768000), UINT64_C(0),	// V_CMP_LE_F16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2080768000), UINT64_C(0),	// V_CMP_LE_F16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2080768000), UINT64_C(0),	// V_CMP_LE_F16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2080768250), UINT64_C(0),	// V_CMP_LE_F16_t16_e32_dpp_gfx11
    UINT64_C(2080768250), UINT64_C(0),	// V_CMP_LE_F16_t16_e32_dpp_gfx12
    UINT64_C(2080768250), UINT64_C(0),	// V_CMP_LE_F16_t16_e32_dpp_w32_gfx11
    UINT64_C(2080768250), UINT64_C(0),	// V_CMP_LE_F16_t16_e32_dpp_w32_gfx12
    UINT64_C(2080768250), UINT64_C(0),	// V_CMP_LE_F16_t16_e32_dpp_w64_gfx11
    UINT64_C(2080768250), UINT64_C(0),	// V_CMP_LE_F16_t16_e32_dpp_w64_gfx12
    UINT64_C(2080768000), UINT64_C(0),	// V_CMP_LE_F16_t16_e32_gfx11
    UINT64_C(2080768000), UINT64_C(0),	// V_CMP_LE_F16_t16_e32_gfx12
    UINT64_C(3556966400), UINT64_C(0),	// V_CMP_LE_F16_t16_e64_dpp8_gfx11
    UINT64_C(3556966400), UINT64_C(0),	// V_CMP_LE_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077298790400), UINT64_C(0),	// V_CMP_LE_F16_t16_e64_dpp_gfx11
    UINT64_C(1077298790400), UINT64_C(0),	// V_CMP_LE_F16_t16_e64_dpp_gfx12
    UINT64_C(3556966400), UINT64_C(0),	// V_CMP_LE_F16_t16_e64_gfx11
    UINT64_C(3556966400), UINT64_C(0),	// V_CMP_LE_F16_t16_e64_gfx12
    UINT64_C(2082865152), UINT64_C(0),	// V_CMP_LE_F32_e32_dpp8_gfx11
    UINT64_C(2082865152), UINT64_C(0),	// V_CMP_LE_F32_e32_dpp8_gfx12
    UINT64_C(2082865152), UINT64_C(0),	// V_CMP_LE_F32_e32_dpp8_w32_gfx11
    UINT64_C(2082865152), UINT64_C(0),	// V_CMP_LE_F32_e32_dpp8_w32_gfx12
    UINT64_C(2082865152), UINT64_C(0),	// V_CMP_LE_F32_e32_dpp8_w64_gfx11
    UINT64_C(2082865152), UINT64_C(0),	// V_CMP_LE_F32_e32_dpp8_w64_gfx12
    UINT64_C(2082865402), UINT64_C(0),	// V_CMP_LE_F32_e32_dpp_gfx11
    UINT64_C(2082865402), UINT64_C(0),	// V_CMP_LE_F32_e32_dpp_gfx12
    UINT64_C(2082865402), UINT64_C(0),	// V_CMP_LE_F32_e32_dpp_w32_gfx11
    UINT64_C(2082865402), UINT64_C(0),	// V_CMP_LE_F32_e32_dpp_w32_gfx12
    UINT64_C(2082865402), UINT64_C(0),	// V_CMP_LE_F32_e32_dpp_w64_gfx11
    UINT64_C(2082865402), UINT64_C(0),	// V_CMP_LE_F32_e32_dpp_w64_gfx12
    UINT64_C(2080768000), UINT64_C(0),	// V_CMP_LE_F32_e32_gfx10
    UINT64_C(2082865152), UINT64_C(0),	// V_CMP_LE_F32_e32_gfx11
    UINT64_C(2082865152), UINT64_C(0),	// V_CMP_LE_F32_e32_gfx12
    UINT64_C(2080768000), UINT64_C(0),	// V_CMP_LE_F32_e32_gfx6_gfx7
    UINT64_C(2089156608), UINT64_C(0),	// V_CMP_LE_F32_e32_vi
    UINT64_C(3558014976), UINT64_C(0),	// V_CMP_LE_F32_e64_dpp8_gfx11
    UINT64_C(3558014976), UINT64_C(0),	// V_CMP_LE_F32_e64_dpp8_gfx12
    UINT64_C(1077299838976), UINT64_C(0),	// V_CMP_LE_F32_e64_dpp_gfx11
    UINT64_C(1077299838976), UINT64_C(0),	// V_CMP_LE_F32_e64_dpp_gfx12
    UINT64_C(3556966400), UINT64_C(0),	// V_CMP_LE_F32_e64_gfx10
    UINT64_C(3558014976), UINT64_C(0),	// V_CMP_LE_F32_e64_gfx11
    UINT64_C(3558014976), UINT64_C(0),	// V_CMP_LE_F32_e64_gfx12
    UINT64_C(3490054144), UINT64_C(0),	// V_CMP_LE_F32_e64_gfx6_gfx7
    UINT64_C(3494051840), UINT64_C(0),	// V_CMP_LE_F32_e64_vi
    UINT64_C(2080768249), UINT64_C(0),	// V_CMP_LE_F32_sdwa_gfx10
    UINT64_C(2089156857), UINT64_C(0),	// V_CMP_LE_F32_sdwa_gfx9
    UINT64_C(2089156857), UINT64_C(0),	// V_CMP_LE_F32_sdwa_vi
    UINT64_C(2084962304), UINT64_C(0),	// V_CMP_LE_F64_e32_gfx10
    UINT64_C(2084962304), UINT64_C(0),	// V_CMP_LE_F64_e32_gfx11
    UINT64_C(2084962304), UINT64_C(0),	// V_CMP_LE_F64_e32_gfx12
    UINT64_C(2084962304), UINT64_C(0),	// V_CMP_LE_F64_e32_gfx6_gfx7
    UINT64_C(2093350912), UINT64_C(0),	// V_CMP_LE_F64_e32_vi
    UINT64_C(3559063552), UINT64_C(0),	// V_CMP_LE_F64_e64_gfx10
    UINT64_C(3559063552), UINT64_C(0),	// V_CMP_LE_F64_e64_gfx11
    UINT64_C(3559063552), UINT64_C(0),	// V_CMP_LE_F64_e64_gfx12
    UINT64_C(3494248448), UINT64_C(0),	// V_CMP_LE_F64_e64_gfx6_gfx7
    UINT64_C(3496148992), UINT64_C(0),	// V_CMP_LE_F64_e64_vi
    UINT64_C(2098593792), UINT64_C(0),	// V_CMP_LE_I16_e32_gfx10
    UINT64_C(2101739520), UINT64_C(0),	// V_CMP_LE_I16_e32_vi
    UINT64_C(3565879296), UINT64_C(0),	// V_CMP_LE_I16_e64_gfx10
    UINT64_C(3500343296), UINT64_C(0),	// V_CMP_LE_I16_e64_vi
    UINT64_C(2087059456), UINT64_C(0),	// V_CMP_LE_I16_fake16_e32_dpp8_gfx11
    UINT64_C(2087059456), UINT64_C(0),	// V_CMP_LE_I16_fake16_e32_dpp8_gfx12
    UINT64_C(2087059456), UINT64_C(0),	// V_CMP_LE_I16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2087059456), UINT64_C(0),	// V_CMP_LE_I16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2087059456), UINT64_C(0),	// V_CMP_LE_I16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2087059456), UINT64_C(0),	// V_CMP_LE_I16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2087059706), UINT64_C(0),	// V_CMP_LE_I16_fake16_e32_dpp_gfx11
    UINT64_C(2087059706), UINT64_C(0),	// V_CMP_LE_I16_fake16_e32_dpp_gfx12
    UINT64_C(2087059706), UINT64_C(0),	// V_CMP_LE_I16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2087059706), UINT64_C(0),	// V_CMP_LE_I16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2087059706), UINT64_C(0),	// V_CMP_LE_I16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2087059706), UINT64_C(0),	// V_CMP_LE_I16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2087059456), UINT64_C(0),	// V_CMP_LE_I16_fake16_e32_gfx11
    UINT64_C(2087059456), UINT64_C(0),	// V_CMP_LE_I16_fake16_e32_gfx12
    UINT64_C(3560112128), UINT64_C(0),	// V_CMP_LE_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3560112128), UINT64_C(0),	// V_CMP_LE_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077301936128), UINT64_C(0),	// V_CMP_LE_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077301936128), UINT64_C(0),	// V_CMP_LE_I16_fake16_e64_dpp_gfx12
    UINT64_C(3560112128), UINT64_C(0),	// V_CMP_LE_I16_fake16_e64_gfx11
    UINT64_C(3560112128), UINT64_C(0),	// V_CMP_LE_I16_fake16_e64_gfx12
    UINT64_C(2098594041), UINT64_C(0),	// V_CMP_LE_I16_sdwa_gfx10
    UINT64_C(2101739769), UINT64_C(0),	// V_CMP_LE_I16_sdwa_gfx9
    UINT64_C(2101739769), UINT64_C(0),	// V_CMP_LE_I16_sdwa_vi
    UINT64_C(2087059456), UINT64_C(0),	// V_CMP_LE_I16_t16_e32_dpp8_gfx11
    UINT64_C(2087059456), UINT64_C(0),	// V_CMP_LE_I16_t16_e32_dpp8_gfx12
    UINT64_C(2087059456), UINT64_C(0),	// V_CMP_LE_I16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2087059456), UINT64_C(0),	// V_CMP_LE_I16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2087059456), UINT64_C(0),	// V_CMP_LE_I16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2087059456), UINT64_C(0),	// V_CMP_LE_I16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2087059706), UINT64_C(0),	// V_CMP_LE_I16_t16_e32_dpp_gfx11
    UINT64_C(2087059706), UINT64_C(0),	// V_CMP_LE_I16_t16_e32_dpp_gfx12
    UINT64_C(2087059706), UINT64_C(0),	// V_CMP_LE_I16_t16_e32_dpp_w32_gfx11
    UINT64_C(2087059706), UINT64_C(0),	// V_CMP_LE_I16_t16_e32_dpp_w32_gfx12
    UINT64_C(2087059706), UINT64_C(0),	// V_CMP_LE_I16_t16_e32_dpp_w64_gfx11
    UINT64_C(2087059706), UINT64_C(0),	// V_CMP_LE_I16_t16_e32_dpp_w64_gfx12
    UINT64_C(2087059456), UINT64_C(0),	// V_CMP_LE_I16_t16_e32_gfx11
    UINT64_C(2087059456), UINT64_C(0),	// V_CMP_LE_I16_t16_e32_gfx12
    UINT64_C(3560112128), UINT64_C(0),	// V_CMP_LE_I16_t16_e64_dpp8_gfx11
    UINT64_C(3560112128), UINT64_C(0),	// V_CMP_LE_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077301936128), UINT64_C(0),	// V_CMP_LE_I16_t16_e64_dpp_gfx11
    UINT64_C(1077301936128), UINT64_C(0),	// V_CMP_LE_I16_t16_e64_dpp_gfx12
    UINT64_C(3560112128), UINT64_C(0),	// V_CMP_LE_I16_t16_e64_gfx11
    UINT64_C(3560112128), UINT64_C(0),	// V_CMP_LE_I16_t16_e64_gfx12
    UINT64_C(2089156608), UINT64_C(0),	// V_CMP_LE_I32_e32_dpp8_gfx11
    UINT64_C(2089156608), UINT64_C(0),	// V_CMP_LE_I32_e32_dpp8_gfx12
    UINT64_C(2089156608), UINT64_C(0),	// V_CMP_LE_I32_e32_dpp8_w32_gfx11
    UINT64_C(2089156608), UINT64_C(0),	// V_CMP_LE_I32_e32_dpp8_w32_gfx12
    UINT64_C(2089156608), UINT64_C(0),	// V_CMP_LE_I32_e32_dpp8_w64_gfx11
    UINT64_C(2089156608), UINT64_C(0),	// V_CMP_LE_I32_e32_dpp8_w64_gfx12
    UINT64_C(2089156858), UINT64_C(0),	// V_CMP_LE_I32_e32_dpp_gfx11
    UINT64_C(2089156858), UINT64_C(0),	// V_CMP_LE_I32_e32_dpp_gfx12
    UINT64_C(2089156858), UINT64_C(0),	// V_CMP_LE_I32_e32_dpp_w32_gfx11
    UINT64_C(2089156858), UINT64_C(0),	// V_CMP_LE_I32_e32_dpp_w32_gfx12
    UINT64_C(2089156858), UINT64_C(0),	// V_CMP_LE_I32_e32_dpp_w64_gfx11
    UINT64_C(2089156858), UINT64_C(0),	// V_CMP_LE_I32_e32_dpp_w64_gfx12
    UINT64_C(2097545216), UINT64_C(0),	// V_CMP_LE_I32_e32_gfx10
    UINT64_C(2089156608), UINT64_C(0),	// V_CMP_LE_I32_e32_gfx11
    UINT64_C(2089156608), UINT64_C(0),	// V_CMP_LE_I32_e32_gfx12
    UINT64_C(2097545216), UINT64_C(0),	// V_CMP_LE_I32_e32_gfx6_gfx7
    UINT64_C(2105933824), UINT64_C(0),	// V_CMP_LE_I32_e32_vi
    UINT64_C(3561160704), UINT64_C(0),	// V_CMP_LE_I32_e64_dpp8_gfx11
    UINT64_C(3561160704), UINT64_C(0),	// V_CMP_LE_I32_e64_dpp8_gfx12
    UINT64_C(1077302984704), UINT64_C(0),	// V_CMP_LE_I32_e64_dpp_gfx11
    UINT64_C(1077302984704), UINT64_C(0),	// V_CMP_LE_I32_e64_dpp_gfx12
    UINT64_C(3565355008), UINT64_C(0),	// V_CMP_LE_I32_e64_gfx10
    UINT64_C(3561160704), UINT64_C(0),	// V_CMP_LE_I32_e64_gfx11
    UINT64_C(3561160704), UINT64_C(0),	// V_CMP_LE_I32_e64_gfx12
    UINT64_C(3506831360), UINT64_C(0),	// V_CMP_LE_I32_e64_gfx6_gfx7
    UINT64_C(3502440448), UINT64_C(0),	// V_CMP_LE_I32_e64_vi
    UINT64_C(2097545465), UINT64_C(0),	// V_CMP_LE_I32_sdwa_gfx10
    UINT64_C(2105934073), UINT64_C(0),	// V_CMP_LE_I32_sdwa_gfx9
    UINT64_C(2105934073), UINT64_C(0),	// V_CMP_LE_I32_sdwa_vi
    UINT64_C(2101739520), UINT64_C(0),	// V_CMP_LE_I64_e32_gfx10
    UINT64_C(2091253760), UINT64_C(0),	// V_CMP_LE_I64_e32_gfx11
    UINT64_C(2091253760), UINT64_C(0),	// V_CMP_LE_I64_e32_gfx12
    UINT64_C(2101739520), UINT64_C(0),	// V_CMP_LE_I64_e32_gfx6_gfx7
    UINT64_C(2110128128), UINT64_C(0),	// V_CMP_LE_I64_e32_vi
    UINT64_C(3567452160), UINT64_C(0),	// V_CMP_LE_I64_e64_gfx10
    UINT64_C(3562209280), UINT64_C(0),	// V_CMP_LE_I64_e64_gfx11
    UINT64_C(3562209280), UINT64_C(0),	// V_CMP_LE_I64_e64_gfx12
    UINT64_C(3511025664), UINT64_C(0),	// V_CMP_LE_I64_e64_gfx6_gfx7
    UINT64_C(3504537600), UINT64_C(0),	// V_CMP_LE_I64_e64_vi
    UINT64_C(2102788096), UINT64_C(0),	// V_CMP_LE_U16_e32_gfx10
    UINT64_C(2102788096), UINT64_C(0),	// V_CMP_LE_U16_e32_vi
    UINT64_C(3567976448), UINT64_C(0),	// V_CMP_LE_U16_e64_gfx10
    UINT64_C(3500867584), UINT64_C(0),	// V_CMP_LE_U16_e64_vi
    UINT64_C(2088108032), UINT64_C(0),	// V_CMP_LE_U16_fake16_e32_dpp8_gfx11
    UINT64_C(2088108032), UINT64_C(0),	// V_CMP_LE_U16_fake16_e32_dpp8_gfx12
    UINT64_C(2088108032), UINT64_C(0),	// V_CMP_LE_U16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2088108032), UINT64_C(0),	// V_CMP_LE_U16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2088108032), UINT64_C(0),	// V_CMP_LE_U16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2088108032), UINT64_C(0),	// V_CMP_LE_U16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2088108282), UINT64_C(0),	// V_CMP_LE_U16_fake16_e32_dpp_gfx11
    UINT64_C(2088108282), UINT64_C(0),	// V_CMP_LE_U16_fake16_e32_dpp_gfx12
    UINT64_C(2088108282), UINT64_C(0),	// V_CMP_LE_U16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2088108282), UINT64_C(0),	// V_CMP_LE_U16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2088108282), UINT64_C(0),	// V_CMP_LE_U16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2088108282), UINT64_C(0),	// V_CMP_LE_U16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2088108032), UINT64_C(0),	// V_CMP_LE_U16_fake16_e32_gfx11
    UINT64_C(2088108032), UINT64_C(0),	// V_CMP_LE_U16_fake16_e32_gfx12
    UINT64_C(3560636416), UINT64_C(0),	// V_CMP_LE_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3560636416), UINT64_C(0),	// V_CMP_LE_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077302460416), UINT64_C(0),	// V_CMP_LE_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077302460416), UINT64_C(0),	// V_CMP_LE_U16_fake16_e64_dpp_gfx12
    UINT64_C(3560636416), UINT64_C(0),	// V_CMP_LE_U16_fake16_e64_gfx11
    UINT64_C(3560636416), UINT64_C(0),	// V_CMP_LE_U16_fake16_e64_gfx12
    UINT64_C(2102788345), UINT64_C(0),	// V_CMP_LE_U16_sdwa_gfx10
    UINT64_C(2102788345), UINT64_C(0),	// V_CMP_LE_U16_sdwa_gfx9
    UINT64_C(2102788345), UINT64_C(0),	// V_CMP_LE_U16_sdwa_vi
    UINT64_C(2088108032), UINT64_C(0),	// V_CMP_LE_U16_t16_e32_dpp8_gfx11
    UINT64_C(2088108032), UINT64_C(0),	// V_CMP_LE_U16_t16_e32_dpp8_gfx12
    UINT64_C(2088108032), UINT64_C(0),	// V_CMP_LE_U16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2088108032), UINT64_C(0),	// V_CMP_LE_U16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2088108032), UINT64_C(0),	// V_CMP_LE_U16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2088108032), UINT64_C(0),	// V_CMP_LE_U16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2088108282), UINT64_C(0),	// V_CMP_LE_U16_t16_e32_dpp_gfx11
    UINT64_C(2088108282), UINT64_C(0),	// V_CMP_LE_U16_t16_e32_dpp_gfx12
    UINT64_C(2088108282), UINT64_C(0),	// V_CMP_LE_U16_t16_e32_dpp_w32_gfx11
    UINT64_C(2088108282), UINT64_C(0),	// V_CMP_LE_U16_t16_e32_dpp_w32_gfx12
    UINT64_C(2088108282), UINT64_C(0),	// V_CMP_LE_U16_t16_e32_dpp_w64_gfx11
    UINT64_C(2088108282), UINT64_C(0),	// V_CMP_LE_U16_t16_e32_dpp_w64_gfx12
    UINT64_C(2088108032), UINT64_C(0),	// V_CMP_LE_U16_t16_e32_gfx11
    UINT64_C(2088108032), UINT64_C(0),	// V_CMP_LE_U16_t16_e32_gfx12
    UINT64_C(3560636416), UINT64_C(0),	// V_CMP_LE_U16_t16_e64_dpp8_gfx11
    UINT64_C(3560636416), UINT64_C(0),	// V_CMP_LE_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077302460416), UINT64_C(0),	// V_CMP_LE_U16_t16_e64_dpp_gfx11
    UINT64_C(1077302460416), UINT64_C(0),	// V_CMP_LE_U16_t16_e64_dpp_gfx12
    UINT64_C(3560636416), UINT64_C(0),	// V_CMP_LE_U16_t16_e64_gfx11
    UINT64_C(3560636416), UINT64_C(0),	// V_CMP_LE_U16_t16_e64_gfx12
    UINT64_C(2090205184), UINT64_C(0),	// V_CMP_LE_U32_e32_dpp8_gfx11
    UINT64_C(2090205184), UINT64_C(0),	// V_CMP_LE_U32_e32_dpp8_gfx12
    UINT64_C(2090205184), UINT64_C(0),	// V_CMP_LE_U32_e32_dpp8_w32_gfx11
    UINT64_C(2090205184), UINT64_C(0),	// V_CMP_LE_U32_e32_dpp8_w32_gfx12
    UINT64_C(2090205184), UINT64_C(0),	// V_CMP_LE_U32_e32_dpp8_w64_gfx11
    UINT64_C(2090205184), UINT64_C(0),	// V_CMP_LE_U32_e32_dpp8_w64_gfx12
    UINT64_C(2090205434), UINT64_C(0),	// V_CMP_LE_U32_e32_dpp_gfx11
    UINT64_C(2090205434), UINT64_C(0),	// V_CMP_LE_U32_e32_dpp_gfx12
    UINT64_C(2090205434), UINT64_C(0),	// V_CMP_LE_U32_e32_dpp_w32_gfx11
    UINT64_C(2090205434), UINT64_C(0),	// V_CMP_LE_U32_e32_dpp_w32_gfx12
    UINT64_C(2090205434), UINT64_C(0),	// V_CMP_LE_U32_e32_dpp_w64_gfx11
    UINT64_C(2090205434), UINT64_C(0),	// V_CMP_LE_U32_e32_dpp_w64_gfx12
    UINT64_C(2105933824), UINT64_C(0),	// V_CMP_LE_U32_e32_gfx10
    UINT64_C(2090205184), UINT64_C(0),	// V_CMP_LE_U32_e32_gfx11
    UINT64_C(2090205184), UINT64_C(0),	// V_CMP_LE_U32_e32_gfx12
    UINT64_C(2105933824), UINT64_C(0),	// V_CMP_LE_U32_e32_gfx6_gfx7
    UINT64_C(2106982400), UINT64_C(0),	// V_CMP_LE_U32_e32_vi
    UINT64_C(3561684992), UINT64_C(0),	// V_CMP_LE_U32_e64_dpp8_gfx11
    UINT64_C(3561684992), UINT64_C(0),	// V_CMP_LE_U32_e64_dpp8_gfx12
    UINT64_C(1077303508992), UINT64_C(0),	// V_CMP_LE_U32_e64_dpp_gfx11
    UINT64_C(1077303508992), UINT64_C(0),	// V_CMP_LE_U32_e64_dpp_gfx12
    UINT64_C(3569549312), UINT64_C(0),	// V_CMP_LE_U32_e64_gfx10
    UINT64_C(3561684992), UINT64_C(0),	// V_CMP_LE_U32_e64_gfx11
    UINT64_C(3561684992), UINT64_C(0),	// V_CMP_LE_U32_e64_gfx12
    UINT64_C(3515219968), UINT64_C(0),	// V_CMP_LE_U32_e64_gfx6_gfx7
    UINT64_C(3502964736), UINT64_C(0),	// V_CMP_LE_U32_e64_vi
    UINT64_C(2105934073), UINT64_C(0),	// V_CMP_LE_U32_sdwa_gfx10
    UINT64_C(2106982649), UINT64_C(0),	// V_CMP_LE_U32_sdwa_gfx9
    UINT64_C(2106982649), UINT64_C(0),	// V_CMP_LE_U32_sdwa_vi
    UINT64_C(2110128128), UINT64_C(0),	// V_CMP_LE_U64_e32_gfx10
    UINT64_C(2092302336), UINT64_C(0),	// V_CMP_LE_U64_e32_gfx11
    UINT64_C(2092302336), UINT64_C(0),	// V_CMP_LE_U64_e32_gfx12
    UINT64_C(2110128128), UINT64_C(0),	// V_CMP_LE_U64_e32_gfx6_gfx7
    UINT64_C(2111176704), UINT64_C(0),	// V_CMP_LE_U64_e32_vi
    UINT64_C(3571646464), UINT64_C(0),	// V_CMP_LE_U64_e64_gfx10
    UINT64_C(3562733568), UINT64_C(0),	// V_CMP_LE_U64_e64_gfx11
    UINT64_C(3562733568), UINT64_C(0),	// V_CMP_LE_U64_e64_gfx12
    UINT64_C(3519414272), UINT64_C(0),	// V_CMP_LE_U64_e64_gfx6_gfx7
    UINT64_C(3505061888), UINT64_C(0),	// V_CMP_LE_U64_e64_vi
    UINT64_C(2107244544), UINT64_C(0),	// V_CMP_LG_F16_e32_gfx10
    UINT64_C(2085224448), UINT64_C(0),	// V_CMP_LG_F16_e32_vi
    UINT64_C(3570204672), UINT64_C(0),	// V_CMP_LG_F16_e64_gfx10
    UINT64_C(3492085760), UINT64_C(0),	// V_CMP_LG_F16_e64_vi
    UINT64_C(2081030144), UINT64_C(0),	// V_CMP_LG_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2081030144), UINT64_C(0),	// V_CMP_LG_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2081030144), UINT64_C(0),	// V_CMP_LG_F16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2081030144), UINT64_C(0),	// V_CMP_LG_F16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2081030144), UINT64_C(0),	// V_CMP_LG_F16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2081030144), UINT64_C(0),	// V_CMP_LG_F16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2081030394), UINT64_C(0),	// V_CMP_LG_F16_fake16_e32_dpp_gfx11
    UINT64_C(2081030394), UINT64_C(0),	// V_CMP_LG_F16_fake16_e32_dpp_gfx12
    UINT64_C(2081030394), UINT64_C(0),	// V_CMP_LG_F16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2081030394), UINT64_C(0),	// V_CMP_LG_F16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2081030394), UINT64_C(0),	// V_CMP_LG_F16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2081030394), UINT64_C(0),	// V_CMP_LG_F16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2081030144), UINT64_C(0),	// V_CMP_LG_F16_fake16_e32_gfx11
    UINT64_C(2081030144), UINT64_C(0),	// V_CMP_LG_F16_fake16_e32_gfx12
    UINT64_C(3557097472), UINT64_C(0),	// V_CMP_LG_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3557097472), UINT64_C(0),	// V_CMP_LG_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077298921472), UINT64_C(0),	// V_CMP_LG_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077298921472), UINT64_C(0),	// V_CMP_LG_F16_fake16_e64_dpp_gfx12
    UINT64_C(3557097472), UINT64_C(0),	// V_CMP_LG_F16_fake16_e64_gfx11
    UINT64_C(3557097472), UINT64_C(0),	// V_CMP_LG_F16_fake16_e64_gfx12
    UINT64_C(2107244793), UINT64_C(0),	// V_CMP_LG_F16_sdwa_gfx10
    UINT64_C(2085224697), UINT64_C(0),	// V_CMP_LG_F16_sdwa_gfx9
    UINT64_C(2085224697), UINT64_C(0),	// V_CMP_LG_F16_sdwa_vi
    UINT64_C(2081030144), UINT64_C(0),	// V_CMP_LG_F16_t16_e32_dpp8_gfx11
    UINT64_C(2081030144), UINT64_C(0),	// V_CMP_LG_F16_t16_e32_dpp8_gfx12
    UINT64_C(2081030144), UINT64_C(0),	// V_CMP_LG_F16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2081030144), UINT64_C(0),	// V_CMP_LG_F16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2081030144), UINT64_C(0),	// V_CMP_LG_F16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2081030144), UINT64_C(0),	// V_CMP_LG_F16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2081030394), UINT64_C(0),	// V_CMP_LG_F16_t16_e32_dpp_gfx11
    UINT64_C(2081030394), UINT64_C(0),	// V_CMP_LG_F16_t16_e32_dpp_gfx12
    UINT64_C(2081030394), UINT64_C(0),	// V_CMP_LG_F16_t16_e32_dpp_w32_gfx11
    UINT64_C(2081030394), UINT64_C(0),	// V_CMP_LG_F16_t16_e32_dpp_w32_gfx12
    UINT64_C(2081030394), UINT64_C(0),	// V_CMP_LG_F16_t16_e32_dpp_w64_gfx11
    UINT64_C(2081030394), UINT64_C(0),	// V_CMP_LG_F16_t16_e32_dpp_w64_gfx12
    UINT64_C(2081030144), UINT64_C(0),	// V_CMP_LG_F16_t16_e32_gfx11
    UINT64_C(2081030144), UINT64_C(0),	// V_CMP_LG_F16_t16_e32_gfx12
    UINT64_C(3557097472), UINT64_C(0),	// V_CMP_LG_F16_t16_e64_dpp8_gfx11
    UINT64_C(3557097472), UINT64_C(0),	// V_CMP_LG_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077298921472), UINT64_C(0),	// V_CMP_LG_F16_t16_e64_dpp_gfx11
    UINT64_C(1077298921472), UINT64_C(0),	// V_CMP_LG_F16_t16_e64_dpp_gfx12
    UINT64_C(3557097472), UINT64_C(0),	// V_CMP_LG_F16_t16_e64_gfx11
    UINT64_C(3557097472), UINT64_C(0),	// V_CMP_LG_F16_t16_e64_gfx12
    UINT64_C(2083127296), UINT64_C(0),	// V_CMP_LG_F32_e32_dpp8_gfx11
    UINT64_C(2083127296), UINT64_C(0),	// V_CMP_LG_F32_e32_dpp8_gfx12
    UINT64_C(2083127296), UINT64_C(0),	// V_CMP_LG_F32_e32_dpp8_w32_gfx11
    UINT64_C(2083127296), UINT64_C(0),	// V_CMP_LG_F32_e32_dpp8_w32_gfx12
    UINT64_C(2083127296), UINT64_C(0),	// V_CMP_LG_F32_e32_dpp8_w64_gfx11
    UINT64_C(2083127296), UINT64_C(0),	// V_CMP_LG_F32_e32_dpp8_w64_gfx12
    UINT64_C(2083127546), UINT64_C(0),	// V_CMP_LG_F32_e32_dpp_gfx11
    UINT64_C(2083127546), UINT64_C(0),	// V_CMP_LG_F32_e32_dpp_gfx12
    UINT64_C(2083127546), UINT64_C(0),	// V_CMP_LG_F32_e32_dpp_w32_gfx11
    UINT64_C(2083127546), UINT64_C(0),	// V_CMP_LG_F32_e32_dpp_w32_gfx12
    UINT64_C(2083127546), UINT64_C(0),	// V_CMP_LG_F32_e32_dpp_w64_gfx11
    UINT64_C(2083127546), UINT64_C(0),	// V_CMP_LG_F32_e32_dpp_w64_gfx12
    UINT64_C(2081030144), UINT64_C(0),	// V_CMP_LG_F32_e32_gfx10
    UINT64_C(2083127296), UINT64_C(0),	// V_CMP_LG_F32_e32_gfx11
    UINT64_C(2083127296), UINT64_C(0),	// V_CMP_LG_F32_e32_gfx12
    UINT64_C(2081030144), UINT64_C(0),	// V_CMP_LG_F32_e32_gfx6_gfx7
    UINT64_C(2089418752), UINT64_C(0),	// V_CMP_LG_F32_e32_vi
    UINT64_C(3558146048), UINT64_C(0),	// V_CMP_LG_F32_e64_dpp8_gfx11
    UINT64_C(3558146048), UINT64_C(0),	// V_CMP_LG_F32_e64_dpp8_gfx12
    UINT64_C(1077299970048), UINT64_C(0),	// V_CMP_LG_F32_e64_dpp_gfx11
    UINT64_C(1077299970048), UINT64_C(0),	// V_CMP_LG_F32_e64_dpp_gfx12
    UINT64_C(3557097472), UINT64_C(0),	// V_CMP_LG_F32_e64_gfx10
    UINT64_C(3558146048), UINT64_C(0),	// V_CMP_LG_F32_e64_gfx11
    UINT64_C(3558146048), UINT64_C(0),	// V_CMP_LG_F32_e64_gfx12
    UINT64_C(3490316288), UINT64_C(0),	// V_CMP_LG_F32_e64_gfx6_gfx7
    UINT64_C(3494182912), UINT64_C(0),	// V_CMP_LG_F32_e64_vi
    UINT64_C(2081030393), UINT64_C(0),	// V_CMP_LG_F32_sdwa_gfx10
    UINT64_C(2089419001), UINT64_C(0),	// V_CMP_LG_F32_sdwa_gfx9
    UINT64_C(2089419001), UINT64_C(0),	// V_CMP_LG_F32_sdwa_vi
    UINT64_C(2085224448), UINT64_C(0),	// V_CMP_LG_F64_e32_gfx10
    UINT64_C(2085224448), UINT64_C(0),	// V_CMP_LG_F64_e32_gfx11
    UINT64_C(2085224448), UINT64_C(0),	// V_CMP_LG_F64_e32_gfx12
    UINT64_C(2085224448), UINT64_C(0),	// V_CMP_LG_F64_e32_gfx6_gfx7
    UINT64_C(2093613056), UINT64_C(0),	// V_CMP_LG_F64_e32_vi
    UINT64_C(3559194624), UINT64_C(0),	// V_CMP_LG_F64_e64_gfx10
    UINT64_C(3559194624), UINT64_C(0),	// V_CMP_LG_F64_e64_gfx11
    UINT64_C(3559194624), UINT64_C(0),	// V_CMP_LG_F64_e64_gfx12
    UINT64_C(3494510592), UINT64_C(0),	// V_CMP_LG_F64_e64_gfx6_gfx7
    UINT64_C(3496280064), UINT64_C(0),	// V_CMP_LG_F64_e64_vi
    UINT64_C(2106720256), UINT64_C(0),	// V_CMP_LT_F16_e32_gfx10
    UINT64_C(2084700160), UINT64_C(0),	// V_CMP_LT_F16_e32_vi
    UINT64_C(3569942528), UINT64_C(0),	// V_CMP_LT_F16_e64_gfx10
    UINT64_C(3491823616), UINT64_C(0),	// V_CMP_LT_F16_e64_vi
    UINT64_C(2080505856), UINT64_C(0),	// V_CMP_LT_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2080505856), UINT64_C(0),	// V_CMP_LT_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2080505856), UINT64_C(0),	// V_CMP_LT_F16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2080505856), UINT64_C(0),	// V_CMP_LT_F16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2080505856), UINT64_C(0),	// V_CMP_LT_F16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2080505856), UINT64_C(0),	// V_CMP_LT_F16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2080506106), UINT64_C(0),	// V_CMP_LT_F16_fake16_e32_dpp_gfx11
    UINT64_C(2080506106), UINT64_C(0),	// V_CMP_LT_F16_fake16_e32_dpp_gfx12
    UINT64_C(2080506106), UINT64_C(0),	// V_CMP_LT_F16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2080506106), UINT64_C(0),	// V_CMP_LT_F16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2080506106), UINT64_C(0),	// V_CMP_LT_F16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2080506106), UINT64_C(0),	// V_CMP_LT_F16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2080505856), UINT64_C(0),	// V_CMP_LT_F16_fake16_e32_gfx11
    UINT64_C(2080505856), UINT64_C(0),	// V_CMP_LT_F16_fake16_e32_gfx12
    UINT64_C(3556835328), UINT64_C(0),	// V_CMP_LT_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3556835328), UINT64_C(0),	// V_CMP_LT_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077298659328), UINT64_C(0),	// V_CMP_LT_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077298659328), UINT64_C(0),	// V_CMP_LT_F16_fake16_e64_dpp_gfx12
    UINT64_C(3556835328), UINT64_C(0),	// V_CMP_LT_F16_fake16_e64_gfx11
    UINT64_C(3556835328), UINT64_C(0),	// V_CMP_LT_F16_fake16_e64_gfx12
    UINT64_C(2106720505), UINT64_C(0),	// V_CMP_LT_F16_sdwa_gfx10
    UINT64_C(2084700409), UINT64_C(0),	// V_CMP_LT_F16_sdwa_gfx9
    UINT64_C(2084700409), UINT64_C(0),	// V_CMP_LT_F16_sdwa_vi
    UINT64_C(2080505856), UINT64_C(0),	// V_CMP_LT_F16_t16_e32_dpp8_gfx11
    UINT64_C(2080505856), UINT64_C(0),	// V_CMP_LT_F16_t16_e32_dpp8_gfx12
    UINT64_C(2080505856), UINT64_C(0),	// V_CMP_LT_F16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2080505856), UINT64_C(0),	// V_CMP_LT_F16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2080505856), UINT64_C(0),	// V_CMP_LT_F16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2080505856), UINT64_C(0),	// V_CMP_LT_F16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2080506106), UINT64_C(0),	// V_CMP_LT_F16_t16_e32_dpp_gfx11
    UINT64_C(2080506106), UINT64_C(0),	// V_CMP_LT_F16_t16_e32_dpp_gfx12
    UINT64_C(2080506106), UINT64_C(0),	// V_CMP_LT_F16_t16_e32_dpp_w32_gfx11
    UINT64_C(2080506106), UINT64_C(0),	// V_CMP_LT_F16_t16_e32_dpp_w32_gfx12
    UINT64_C(2080506106), UINT64_C(0),	// V_CMP_LT_F16_t16_e32_dpp_w64_gfx11
    UINT64_C(2080506106), UINT64_C(0),	// V_CMP_LT_F16_t16_e32_dpp_w64_gfx12
    UINT64_C(2080505856), UINT64_C(0),	// V_CMP_LT_F16_t16_e32_gfx11
    UINT64_C(2080505856), UINT64_C(0),	// V_CMP_LT_F16_t16_e32_gfx12
    UINT64_C(3556835328), UINT64_C(0),	// V_CMP_LT_F16_t16_e64_dpp8_gfx11
    UINT64_C(3556835328), UINT64_C(0),	// V_CMP_LT_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077298659328), UINT64_C(0),	// V_CMP_LT_F16_t16_e64_dpp_gfx11
    UINT64_C(1077298659328), UINT64_C(0),	// V_CMP_LT_F16_t16_e64_dpp_gfx12
    UINT64_C(3556835328), UINT64_C(0),	// V_CMP_LT_F16_t16_e64_gfx11
    UINT64_C(3556835328), UINT64_C(0),	// V_CMP_LT_F16_t16_e64_gfx12
    UINT64_C(2082603008), UINT64_C(0),	// V_CMP_LT_F32_e32_dpp8_gfx11
    UINT64_C(2082603008), UINT64_C(0),	// V_CMP_LT_F32_e32_dpp8_gfx12
    UINT64_C(2082603008), UINT64_C(0),	// V_CMP_LT_F32_e32_dpp8_w32_gfx11
    UINT64_C(2082603008), UINT64_C(0),	// V_CMP_LT_F32_e32_dpp8_w32_gfx12
    UINT64_C(2082603008), UINT64_C(0),	// V_CMP_LT_F32_e32_dpp8_w64_gfx11
    UINT64_C(2082603008), UINT64_C(0),	// V_CMP_LT_F32_e32_dpp8_w64_gfx12
    UINT64_C(2082603258), UINT64_C(0),	// V_CMP_LT_F32_e32_dpp_gfx11
    UINT64_C(2082603258), UINT64_C(0),	// V_CMP_LT_F32_e32_dpp_gfx12
    UINT64_C(2082603258), UINT64_C(0),	// V_CMP_LT_F32_e32_dpp_w32_gfx11
    UINT64_C(2082603258), UINT64_C(0),	// V_CMP_LT_F32_e32_dpp_w32_gfx12
    UINT64_C(2082603258), UINT64_C(0),	// V_CMP_LT_F32_e32_dpp_w64_gfx11
    UINT64_C(2082603258), UINT64_C(0),	// V_CMP_LT_F32_e32_dpp_w64_gfx12
    UINT64_C(2080505856), UINT64_C(0),	// V_CMP_LT_F32_e32_gfx10
    UINT64_C(2082603008), UINT64_C(0),	// V_CMP_LT_F32_e32_gfx11
    UINT64_C(2082603008), UINT64_C(0),	// V_CMP_LT_F32_e32_gfx12
    UINT64_C(2080505856), UINT64_C(0),	// V_CMP_LT_F32_e32_gfx6_gfx7
    UINT64_C(2088894464), UINT64_C(0),	// V_CMP_LT_F32_e32_vi
    UINT64_C(3557883904), UINT64_C(0),	// V_CMP_LT_F32_e64_dpp8_gfx11
    UINT64_C(3557883904), UINT64_C(0),	// V_CMP_LT_F32_e64_dpp8_gfx12
    UINT64_C(1077299707904), UINT64_C(0),	// V_CMP_LT_F32_e64_dpp_gfx11
    UINT64_C(1077299707904), UINT64_C(0),	// V_CMP_LT_F32_e64_dpp_gfx12
    UINT64_C(3556835328), UINT64_C(0),	// V_CMP_LT_F32_e64_gfx10
    UINT64_C(3557883904), UINT64_C(0),	// V_CMP_LT_F32_e64_gfx11
    UINT64_C(3557883904), UINT64_C(0),	// V_CMP_LT_F32_e64_gfx12
    UINT64_C(3489792000), UINT64_C(0),	// V_CMP_LT_F32_e64_gfx6_gfx7
    UINT64_C(3493920768), UINT64_C(0),	// V_CMP_LT_F32_e64_vi
    UINT64_C(2080506105), UINT64_C(0),	// V_CMP_LT_F32_sdwa_gfx10
    UINT64_C(2088894713), UINT64_C(0),	// V_CMP_LT_F32_sdwa_gfx9
    UINT64_C(2088894713), UINT64_C(0),	// V_CMP_LT_F32_sdwa_vi
    UINT64_C(2084700160), UINT64_C(0),	// V_CMP_LT_F64_e32_gfx10
    UINT64_C(2084700160), UINT64_C(0),	// V_CMP_LT_F64_e32_gfx11
    UINT64_C(2084700160), UINT64_C(0),	// V_CMP_LT_F64_e32_gfx12
    UINT64_C(2084700160), UINT64_C(0),	// V_CMP_LT_F64_e32_gfx6_gfx7
    UINT64_C(2093088768), UINT64_C(0),	// V_CMP_LT_F64_e32_vi
    UINT64_C(3558932480), UINT64_C(0),	// V_CMP_LT_F64_e64_gfx10
    UINT64_C(3558932480), UINT64_C(0),	// V_CMP_LT_F64_e64_gfx11
    UINT64_C(3558932480), UINT64_C(0),	// V_CMP_LT_F64_e64_gfx12
    UINT64_C(3493986304), UINT64_C(0),	// V_CMP_LT_F64_e64_gfx6_gfx7
    UINT64_C(3496017920), UINT64_C(0),	// V_CMP_LT_F64_e64_vi
    UINT64_C(2098331648), UINT64_C(0),	// V_CMP_LT_I16_e32_gfx10
    UINT64_C(2101477376), UINT64_C(0),	// V_CMP_LT_I16_e32_vi
    UINT64_C(3565748224), UINT64_C(0),	// V_CMP_LT_I16_e64_gfx10
    UINT64_C(3500212224), UINT64_C(0),	// V_CMP_LT_I16_e64_vi
    UINT64_C(2086797312), UINT64_C(0),	// V_CMP_LT_I16_fake16_e32_dpp8_gfx11
    UINT64_C(2086797312), UINT64_C(0),	// V_CMP_LT_I16_fake16_e32_dpp8_gfx12
    UINT64_C(2086797312), UINT64_C(0),	// V_CMP_LT_I16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2086797312), UINT64_C(0),	// V_CMP_LT_I16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2086797312), UINT64_C(0),	// V_CMP_LT_I16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2086797312), UINT64_C(0),	// V_CMP_LT_I16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2086797562), UINT64_C(0),	// V_CMP_LT_I16_fake16_e32_dpp_gfx11
    UINT64_C(2086797562), UINT64_C(0),	// V_CMP_LT_I16_fake16_e32_dpp_gfx12
    UINT64_C(2086797562), UINT64_C(0),	// V_CMP_LT_I16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2086797562), UINT64_C(0),	// V_CMP_LT_I16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2086797562), UINT64_C(0),	// V_CMP_LT_I16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2086797562), UINT64_C(0),	// V_CMP_LT_I16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2086797312), UINT64_C(0),	// V_CMP_LT_I16_fake16_e32_gfx11
    UINT64_C(2086797312), UINT64_C(0),	// V_CMP_LT_I16_fake16_e32_gfx12
    UINT64_C(3559981056), UINT64_C(0),	// V_CMP_LT_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3559981056), UINT64_C(0),	// V_CMP_LT_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077301805056), UINT64_C(0),	// V_CMP_LT_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077301805056), UINT64_C(0),	// V_CMP_LT_I16_fake16_e64_dpp_gfx12
    UINT64_C(3559981056), UINT64_C(0),	// V_CMP_LT_I16_fake16_e64_gfx11
    UINT64_C(3559981056), UINT64_C(0),	// V_CMP_LT_I16_fake16_e64_gfx12
    UINT64_C(2098331897), UINT64_C(0),	// V_CMP_LT_I16_sdwa_gfx10
    UINT64_C(2101477625), UINT64_C(0),	// V_CMP_LT_I16_sdwa_gfx9
    UINT64_C(2101477625), UINT64_C(0),	// V_CMP_LT_I16_sdwa_vi
    UINT64_C(2086797312), UINT64_C(0),	// V_CMP_LT_I16_t16_e32_dpp8_gfx11
    UINT64_C(2086797312), UINT64_C(0),	// V_CMP_LT_I16_t16_e32_dpp8_gfx12
    UINT64_C(2086797312), UINT64_C(0),	// V_CMP_LT_I16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2086797312), UINT64_C(0),	// V_CMP_LT_I16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2086797312), UINT64_C(0),	// V_CMP_LT_I16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2086797312), UINT64_C(0),	// V_CMP_LT_I16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2086797562), UINT64_C(0),	// V_CMP_LT_I16_t16_e32_dpp_gfx11
    UINT64_C(2086797562), UINT64_C(0),	// V_CMP_LT_I16_t16_e32_dpp_gfx12
    UINT64_C(2086797562), UINT64_C(0),	// V_CMP_LT_I16_t16_e32_dpp_w32_gfx11
    UINT64_C(2086797562), UINT64_C(0),	// V_CMP_LT_I16_t16_e32_dpp_w32_gfx12
    UINT64_C(2086797562), UINT64_C(0),	// V_CMP_LT_I16_t16_e32_dpp_w64_gfx11
    UINT64_C(2086797562), UINT64_C(0),	// V_CMP_LT_I16_t16_e32_dpp_w64_gfx12
    UINT64_C(2086797312), UINT64_C(0),	// V_CMP_LT_I16_t16_e32_gfx11
    UINT64_C(2086797312), UINT64_C(0),	// V_CMP_LT_I16_t16_e32_gfx12
    UINT64_C(3559981056), UINT64_C(0),	// V_CMP_LT_I16_t16_e64_dpp8_gfx11
    UINT64_C(3559981056), UINT64_C(0),	// V_CMP_LT_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077301805056), UINT64_C(0),	// V_CMP_LT_I16_t16_e64_dpp_gfx11
    UINT64_C(1077301805056), UINT64_C(0),	// V_CMP_LT_I16_t16_e64_dpp_gfx12
    UINT64_C(3559981056), UINT64_C(0),	// V_CMP_LT_I16_t16_e64_gfx11
    UINT64_C(3559981056), UINT64_C(0),	// V_CMP_LT_I16_t16_e64_gfx12
    UINT64_C(2088894464), UINT64_C(0),	// V_CMP_LT_I32_e32_dpp8_gfx11
    UINT64_C(2088894464), UINT64_C(0),	// V_CMP_LT_I32_e32_dpp8_gfx12
    UINT64_C(2088894464), UINT64_C(0),	// V_CMP_LT_I32_e32_dpp8_w32_gfx11
    UINT64_C(2088894464), UINT64_C(0),	// V_CMP_LT_I32_e32_dpp8_w32_gfx12
    UINT64_C(2088894464), UINT64_C(0),	// V_CMP_LT_I32_e32_dpp8_w64_gfx11
    UINT64_C(2088894464), UINT64_C(0),	// V_CMP_LT_I32_e32_dpp8_w64_gfx12
    UINT64_C(2088894714), UINT64_C(0),	// V_CMP_LT_I32_e32_dpp_gfx11
    UINT64_C(2088894714), UINT64_C(0),	// V_CMP_LT_I32_e32_dpp_gfx12
    UINT64_C(2088894714), UINT64_C(0),	// V_CMP_LT_I32_e32_dpp_w32_gfx11
    UINT64_C(2088894714), UINT64_C(0),	// V_CMP_LT_I32_e32_dpp_w32_gfx12
    UINT64_C(2088894714), UINT64_C(0),	// V_CMP_LT_I32_e32_dpp_w64_gfx11
    UINT64_C(2088894714), UINT64_C(0),	// V_CMP_LT_I32_e32_dpp_w64_gfx12
    UINT64_C(2097283072), UINT64_C(0),	// V_CMP_LT_I32_e32_gfx10
    UINT64_C(2088894464), UINT64_C(0),	// V_CMP_LT_I32_e32_gfx11
    UINT64_C(2088894464), UINT64_C(0),	// V_CMP_LT_I32_e32_gfx12
    UINT64_C(2097283072), UINT64_C(0),	// V_CMP_LT_I32_e32_gfx6_gfx7
    UINT64_C(2105671680), UINT64_C(0),	// V_CMP_LT_I32_e32_vi
    UINT64_C(3561029632), UINT64_C(0),	// V_CMP_LT_I32_e64_dpp8_gfx11
    UINT64_C(3561029632), UINT64_C(0),	// V_CMP_LT_I32_e64_dpp8_gfx12
    UINT64_C(1077302853632), UINT64_C(0),	// V_CMP_LT_I32_e64_dpp_gfx11
    UINT64_C(1077302853632), UINT64_C(0),	// V_CMP_LT_I32_e64_dpp_gfx12
    UINT64_C(3565223936), UINT64_C(0),	// V_CMP_LT_I32_e64_gfx10
    UINT64_C(3561029632), UINT64_C(0),	// V_CMP_LT_I32_e64_gfx11
    UINT64_C(3561029632), UINT64_C(0),	// V_CMP_LT_I32_e64_gfx12
    UINT64_C(3506569216), UINT64_C(0),	// V_CMP_LT_I32_e64_gfx6_gfx7
    UINT64_C(3502309376), UINT64_C(0),	// V_CMP_LT_I32_e64_vi
    UINT64_C(2097283321), UINT64_C(0),	// V_CMP_LT_I32_sdwa_gfx10
    UINT64_C(2105671929), UINT64_C(0),	// V_CMP_LT_I32_sdwa_gfx9
    UINT64_C(2105671929), UINT64_C(0),	// V_CMP_LT_I32_sdwa_vi
    UINT64_C(2101477376), UINT64_C(0),	// V_CMP_LT_I64_e32_gfx10
    UINT64_C(2090991616), UINT64_C(0),	// V_CMP_LT_I64_e32_gfx11
    UINT64_C(2090991616), UINT64_C(0),	// V_CMP_LT_I64_e32_gfx12
    UINT64_C(2101477376), UINT64_C(0),	// V_CMP_LT_I64_e32_gfx6_gfx7
    UINT64_C(2109865984), UINT64_C(0),	// V_CMP_LT_I64_e32_vi
    UINT64_C(3567321088), UINT64_C(0),	// V_CMP_LT_I64_e64_gfx10
    UINT64_C(3562078208), UINT64_C(0),	// V_CMP_LT_I64_e64_gfx11
    UINT64_C(3562078208), UINT64_C(0),	// V_CMP_LT_I64_e64_gfx12
    UINT64_C(3510763520), UINT64_C(0),	// V_CMP_LT_I64_e64_gfx6_gfx7
    UINT64_C(3504406528), UINT64_C(0),	// V_CMP_LT_I64_e64_vi
    UINT64_C(2102525952), UINT64_C(0),	// V_CMP_LT_U16_e32_gfx10
    UINT64_C(2102525952), UINT64_C(0),	// V_CMP_LT_U16_e32_vi
    UINT64_C(3567845376), UINT64_C(0),	// V_CMP_LT_U16_e64_gfx10
    UINT64_C(3500736512), UINT64_C(0),	// V_CMP_LT_U16_e64_vi
    UINT64_C(2087845888), UINT64_C(0),	// V_CMP_LT_U16_fake16_e32_dpp8_gfx11
    UINT64_C(2087845888), UINT64_C(0),	// V_CMP_LT_U16_fake16_e32_dpp8_gfx12
    UINT64_C(2087845888), UINT64_C(0),	// V_CMP_LT_U16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2087845888), UINT64_C(0),	// V_CMP_LT_U16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2087845888), UINT64_C(0),	// V_CMP_LT_U16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2087845888), UINT64_C(0),	// V_CMP_LT_U16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2087846138), UINT64_C(0),	// V_CMP_LT_U16_fake16_e32_dpp_gfx11
    UINT64_C(2087846138), UINT64_C(0),	// V_CMP_LT_U16_fake16_e32_dpp_gfx12
    UINT64_C(2087846138), UINT64_C(0),	// V_CMP_LT_U16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2087846138), UINT64_C(0),	// V_CMP_LT_U16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2087846138), UINT64_C(0),	// V_CMP_LT_U16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2087846138), UINT64_C(0),	// V_CMP_LT_U16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2087845888), UINT64_C(0),	// V_CMP_LT_U16_fake16_e32_gfx11
    UINT64_C(2087845888), UINT64_C(0),	// V_CMP_LT_U16_fake16_e32_gfx12
    UINT64_C(3560505344), UINT64_C(0),	// V_CMP_LT_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3560505344), UINT64_C(0),	// V_CMP_LT_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077302329344), UINT64_C(0),	// V_CMP_LT_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077302329344), UINT64_C(0),	// V_CMP_LT_U16_fake16_e64_dpp_gfx12
    UINT64_C(3560505344), UINT64_C(0),	// V_CMP_LT_U16_fake16_e64_gfx11
    UINT64_C(3560505344), UINT64_C(0),	// V_CMP_LT_U16_fake16_e64_gfx12
    UINT64_C(2102526201), UINT64_C(0),	// V_CMP_LT_U16_sdwa_gfx10
    UINT64_C(2102526201), UINT64_C(0),	// V_CMP_LT_U16_sdwa_gfx9
    UINT64_C(2102526201), UINT64_C(0),	// V_CMP_LT_U16_sdwa_vi
    UINT64_C(2087845888), UINT64_C(0),	// V_CMP_LT_U16_t16_e32_dpp8_gfx11
    UINT64_C(2087845888), UINT64_C(0),	// V_CMP_LT_U16_t16_e32_dpp8_gfx12
    UINT64_C(2087845888), UINT64_C(0),	// V_CMP_LT_U16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2087845888), UINT64_C(0),	// V_CMP_LT_U16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2087845888), UINT64_C(0),	// V_CMP_LT_U16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2087845888), UINT64_C(0),	// V_CMP_LT_U16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2087846138), UINT64_C(0),	// V_CMP_LT_U16_t16_e32_dpp_gfx11
    UINT64_C(2087846138), UINT64_C(0),	// V_CMP_LT_U16_t16_e32_dpp_gfx12
    UINT64_C(2087846138), UINT64_C(0),	// V_CMP_LT_U16_t16_e32_dpp_w32_gfx11
    UINT64_C(2087846138), UINT64_C(0),	// V_CMP_LT_U16_t16_e32_dpp_w32_gfx12
    UINT64_C(2087846138), UINT64_C(0),	// V_CMP_LT_U16_t16_e32_dpp_w64_gfx11
    UINT64_C(2087846138), UINT64_C(0),	// V_CMP_LT_U16_t16_e32_dpp_w64_gfx12
    UINT64_C(2087845888), UINT64_C(0),	// V_CMP_LT_U16_t16_e32_gfx11
    UINT64_C(2087845888), UINT64_C(0),	// V_CMP_LT_U16_t16_e32_gfx12
    UINT64_C(3560505344), UINT64_C(0),	// V_CMP_LT_U16_t16_e64_dpp8_gfx11
    UINT64_C(3560505344), UINT64_C(0),	// V_CMP_LT_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077302329344), UINT64_C(0),	// V_CMP_LT_U16_t16_e64_dpp_gfx11
    UINT64_C(1077302329344), UINT64_C(0),	// V_CMP_LT_U16_t16_e64_dpp_gfx12
    UINT64_C(3560505344), UINT64_C(0),	// V_CMP_LT_U16_t16_e64_gfx11
    UINT64_C(3560505344), UINT64_C(0),	// V_CMP_LT_U16_t16_e64_gfx12
    UINT64_C(2089943040), UINT64_C(0),	// V_CMP_LT_U32_e32_dpp8_gfx11
    UINT64_C(2089943040), UINT64_C(0),	// V_CMP_LT_U32_e32_dpp8_gfx12
    UINT64_C(2089943040), UINT64_C(0),	// V_CMP_LT_U32_e32_dpp8_w32_gfx11
    UINT64_C(2089943040), UINT64_C(0),	// V_CMP_LT_U32_e32_dpp8_w32_gfx12
    UINT64_C(2089943040), UINT64_C(0),	// V_CMP_LT_U32_e32_dpp8_w64_gfx11
    UINT64_C(2089943040), UINT64_C(0),	// V_CMP_LT_U32_e32_dpp8_w64_gfx12
    UINT64_C(2089943290), UINT64_C(0),	// V_CMP_LT_U32_e32_dpp_gfx11
    UINT64_C(2089943290), UINT64_C(0),	// V_CMP_LT_U32_e32_dpp_gfx12
    UINT64_C(2089943290), UINT64_C(0),	// V_CMP_LT_U32_e32_dpp_w32_gfx11
    UINT64_C(2089943290), UINT64_C(0),	// V_CMP_LT_U32_e32_dpp_w32_gfx12
    UINT64_C(2089943290), UINT64_C(0),	// V_CMP_LT_U32_e32_dpp_w64_gfx11
    UINT64_C(2089943290), UINT64_C(0),	// V_CMP_LT_U32_e32_dpp_w64_gfx12
    UINT64_C(2105671680), UINT64_C(0),	// V_CMP_LT_U32_e32_gfx10
    UINT64_C(2089943040), UINT64_C(0),	// V_CMP_LT_U32_e32_gfx11
    UINT64_C(2089943040), UINT64_C(0),	// V_CMP_LT_U32_e32_gfx12
    UINT64_C(2105671680), UINT64_C(0),	// V_CMP_LT_U32_e32_gfx6_gfx7
    UINT64_C(2106720256), UINT64_C(0),	// V_CMP_LT_U32_e32_vi
    UINT64_C(3561553920), UINT64_C(0),	// V_CMP_LT_U32_e64_dpp8_gfx11
    UINT64_C(3561553920), UINT64_C(0),	// V_CMP_LT_U32_e64_dpp8_gfx12
    UINT64_C(1077303377920), UINT64_C(0),	// V_CMP_LT_U32_e64_dpp_gfx11
    UINT64_C(1077303377920), UINT64_C(0),	// V_CMP_LT_U32_e64_dpp_gfx12
    UINT64_C(3569418240), UINT64_C(0),	// V_CMP_LT_U32_e64_gfx10
    UINT64_C(3561553920), UINT64_C(0),	// V_CMP_LT_U32_e64_gfx11
    UINT64_C(3561553920), UINT64_C(0),	// V_CMP_LT_U32_e64_gfx12
    UINT64_C(3514957824), UINT64_C(0),	// V_CMP_LT_U32_e64_gfx6_gfx7
    UINT64_C(3502833664), UINT64_C(0),	// V_CMP_LT_U32_e64_vi
    UINT64_C(2105671929), UINT64_C(0),	// V_CMP_LT_U32_sdwa_gfx10
    UINT64_C(2106720505), UINT64_C(0),	// V_CMP_LT_U32_sdwa_gfx9
    UINT64_C(2106720505), UINT64_C(0),	// V_CMP_LT_U32_sdwa_vi
    UINT64_C(2109865984), UINT64_C(0),	// V_CMP_LT_U64_e32_gfx10
    UINT64_C(2092040192), UINT64_C(0),	// V_CMP_LT_U64_e32_gfx11
    UINT64_C(2092040192), UINT64_C(0),	// V_CMP_LT_U64_e32_gfx12
    UINT64_C(2109865984), UINT64_C(0),	// V_CMP_LT_U64_e32_gfx6_gfx7
    UINT64_C(2110914560), UINT64_C(0),	// V_CMP_LT_U64_e32_vi
    UINT64_C(3571515392), UINT64_C(0),	// V_CMP_LT_U64_e64_gfx10
    UINT64_C(3562602496), UINT64_C(0),	// V_CMP_LT_U64_e64_gfx11
    UINT64_C(3562602496), UINT64_C(0),	// V_CMP_LT_U64_e64_gfx12
    UINT64_C(3519152128), UINT64_C(0),	// V_CMP_LT_U64_e64_gfx6_gfx7
    UINT64_C(3504930816), UINT64_C(0),	// V_CMP_LT_U64_e64_vi
    UINT64_C(2111438848), UINT64_C(0),	// V_CMP_NEQ_F16_e32_gfx10
    UINT64_C(2086273024), UINT64_C(0),	// V_CMP_NEQ_F16_e32_vi
    UINT64_C(3572301824), UINT64_C(0),	// V_CMP_NEQ_F16_e64_gfx10
    UINT64_C(3492610048), UINT64_C(0),	// V_CMP_NEQ_F16_e64_vi
    UINT64_C(2082078720), UINT64_C(0),	// V_CMP_NEQ_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2082078720), UINT64_C(0),	// V_CMP_NEQ_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2082078720), UINT64_C(0),	// V_CMP_NEQ_F16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2082078720), UINT64_C(0),	// V_CMP_NEQ_F16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2082078720), UINT64_C(0),	// V_CMP_NEQ_F16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2082078720), UINT64_C(0),	// V_CMP_NEQ_F16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2082078970), UINT64_C(0),	// V_CMP_NEQ_F16_fake16_e32_dpp_gfx11
    UINT64_C(2082078970), UINT64_C(0),	// V_CMP_NEQ_F16_fake16_e32_dpp_gfx12
    UINT64_C(2082078970), UINT64_C(0),	// V_CMP_NEQ_F16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2082078970), UINT64_C(0),	// V_CMP_NEQ_F16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2082078970), UINT64_C(0),	// V_CMP_NEQ_F16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2082078970), UINT64_C(0),	// V_CMP_NEQ_F16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2082078720), UINT64_C(0),	// V_CMP_NEQ_F16_fake16_e32_gfx11
    UINT64_C(2082078720), UINT64_C(0),	// V_CMP_NEQ_F16_fake16_e32_gfx12
    UINT64_C(3557621760), UINT64_C(0),	// V_CMP_NEQ_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3557621760), UINT64_C(0),	// V_CMP_NEQ_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077299445760), UINT64_C(0),	// V_CMP_NEQ_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077299445760), UINT64_C(0),	// V_CMP_NEQ_F16_fake16_e64_dpp_gfx12
    UINT64_C(3557621760), UINT64_C(0),	// V_CMP_NEQ_F16_fake16_e64_gfx11
    UINT64_C(3557621760), UINT64_C(0),	// V_CMP_NEQ_F16_fake16_e64_gfx12
    UINT64_C(2111439097), UINT64_C(0),	// V_CMP_NEQ_F16_sdwa_gfx10
    UINT64_C(2086273273), UINT64_C(0),	// V_CMP_NEQ_F16_sdwa_gfx9
    UINT64_C(2086273273), UINT64_C(0),	// V_CMP_NEQ_F16_sdwa_vi
    UINT64_C(2082078720), UINT64_C(0),	// V_CMP_NEQ_F16_t16_e32_dpp8_gfx11
    UINT64_C(2082078720), UINT64_C(0),	// V_CMP_NEQ_F16_t16_e32_dpp8_gfx12
    UINT64_C(2082078720), UINT64_C(0),	// V_CMP_NEQ_F16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2082078720), UINT64_C(0),	// V_CMP_NEQ_F16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2082078720), UINT64_C(0),	// V_CMP_NEQ_F16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2082078720), UINT64_C(0),	// V_CMP_NEQ_F16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2082078970), UINT64_C(0),	// V_CMP_NEQ_F16_t16_e32_dpp_gfx11
    UINT64_C(2082078970), UINT64_C(0),	// V_CMP_NEQ_F16_t16_e32_dpp_gfx12
    UINT64_C(2082078970), UINT64_C(0),	// V_CMP_NEQ_F16_t16_e32_dpp_w32_gfx11
    UINT64_C(2082078970), UINT64_C(0),	// V_CMP_NEQ_F16_t16_e32_dpp_w32_gfx12
    UINT64_C(2082078970), UINT64_C(0),	// V_CMP_NEQ_F16_t16_e32_dpp_w64_gfx11
    UINT64_C(2082078970), UINT64_C(0),	// V_CMP_NEQ_F16_t16_e32_dpp_w64_gfx12
    UINT64_C(2082078720), UINT64_C(0),	// V_CMP_NEQ_F16_t16_e32_gfx11
    UINT64_C(2082078720), UINT64_C(0),	// V_CMP_NEQ_F16_t16_e32_gfx12
    UINT64_C(3557621760), UINT64_C(0),	// V_CMP_NEQ_F16_t16_e64_dpp8_gfx11
    UINT64_C(3557621760), UINT64_C(0),	// V_CMP_NEQ_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077299445760), UINT64_C(0),	// V_CMP_NEQ_F16_t16_e64_dpp_gfx11
    UINT64_C(1077299445760), UINT64_C(0),	// V_CMP_NEQ_F16_t16_e64_dpp_gfx12
    UINT64_C(3557621760), UINT64_C(0),	// V_CMP_NEQ_F16_t16_e64_gfx11
    UINT64_C(3557621760), UINT64_C(0),	// V_CMP_NEQ_F16_t16_e64_gfx12
    UINT64_C(2084175872), UINT64_C(0),	// V_CMP_NEQ_F32_e32_dpp8_gfx11
    UINT64_C(2084175872), UINT64_C(0),	// V_CMP_NEQ_F32_e32_dpp8_gfx12
    UINT64_C(2084175872), UINT64_C(0),	// V_CMP_NEQ_F32_e32_dpp8_w32_gfx11
    UINT64_C(2084175872), UINT64_C(0),	// V_CMP_NEQ_F32_e32_dpp8_w32_gfx12
    UINT64_C(2084175872), UINT64_C(0),	// V_CMP_NEQ_F32_e32_dpp8_w64_gfx11
    UINT64_C(2084175872), UINT64_C(0),	// V_CMP_NEQ_F32_e32_dpp8_w64_gfx12
    UINT64_C(2084176122), UINT64_C(0),	// V_CMP_NEQ_F32_e32_dpp_gfx11
    UINT64_C(2084176122), UINT64_C(0),	// V_CMP_NEQ_F32_e32_dpp_gfx12
    UINT64_C(2084176122), UINT64_C(0),	// V_CMP_NEQ_F32_e32_dpp_w32_gfx11
    UINT64_C(2084176122), UINT64_C(0),	// V_CMP_NEQ_F32_e32_dpp_w32_gfx12
    UINT64_C(2084176122), UINT64_C(0),	// V_CMP_NEQ_F32_e32_dpp_w64_gfx11
    UINT64_C(2084176122), UINT64_C(0),	// V_CMP_NEQ_F32_e32_dpp_w64_gfx12
    UINT64_C(2082078720), UINT64_C(0),	// V_CMP_NEQ_F32_e32_gfx10
    UINT64_C(2084175872), UINT64_C(0),	// V_CMP_NEQ_F32_e32_gfx11
    UINT64_C(2084175872), UINT64_C(0),	// V_CMP_NEQ_F32_e32_gfx12
    UINT64_C(2082078720), UINT64_C(0),	// V_CMP_NEQ_F32_e32_gfx6_gfx7
    UINT64_C(2090467328), UINT64_C(0),	// V_CMP_NEQ_F32_e32_vi
    UINT64_C(3558670336), UINT64_C(0),	// V_CMP_NEQ_F32_e64_dpp8_gfx11
    UINT64_C(3558670336), UINT64_C(0),	// V_CMP_NEQ_F32_e64_dpp8_gfx12
    UINT64_C(1077300494336), UINT64_C(0),	// V_CMP_NEQ_F32_e64_dpp_gfx11
    UINT64_C(1077300494336), UINT64_C(0),	// V_CMP_NEQ_F32_e64_dpp_gfx12
    UINT64_C(3557621760), UINT64_C(0),	// V_CMP_NEQ_F32_e64_gfx10
    UINT64_C(3558670336), UINT64_C(0),	// V_CMP_NEQ_F32_e64_gfx11
    UINT64_C(3558670336), UINT64_C(0),	// V_CMP_NEQ_F32_e64_gfx12
    UINT64_C(3491364864), UINT64_C(0),	// V_CMP_NEQ_F32_e64_gfx6_gfx7
    UINT64_C(3494707200), UINT64_C(0),	// V_CMP_NEQ_F32_e64_vi
    UINT64_C(2082078969), UINT64_C(0),	// V_CMP_NEQ_F32_sdwa_gfx10
    UINT64_C(2090467577), UINT64_C(0),	// V_CMP_NEQ_F32_sdwa_gfx9
    UINT64_C(2090467577), UINT64_C(0),	// V_CMP_NEQ_F32_sdwa_vi
    UINT64_C(2086273024), UINT64_C(0),	// V_CMP_NEQ_F64_e32_gfx10
    UINT64_C(2086273024), UINT64_C(0),	// V_CMP_NEQ_F64_e32_gfx11
    UINT64_C(2086273024), UINT64_C(0),	// V_CMP_NEQ_F64_e32_gfx12
    UINT64_C(2086273024), UINT64_C(0),	// V_CMP_NEQ_F64_e32_gfx6_gfx7
    UINT64_C(2094661632), UINT64_C(0),	// V_CMP_NEQ_F64_e32_vi
    UINT64_C(3559718912), UINT64_C(0),	// V_CMP_NEQ_F64_e64_gfx10
    UINT64_C(3559718912), UINT64_C(0),	// V_CMP_NEQ_F64_e64_gfx11
    UINT64_C(3559718912), UINT64_C(0),	// V_CMP_NEQ_F64_e64_gfx12
    UINT64_C(3495559168), UINT64_C(0),	// V_CMP_NEQ_F64_e64_gfx6_gfx7
    UINT64_C(3496804352), UINT64_C(0),	// V_CMP_NEQ_F64_e64_vi
    UINT64_C(2098855936), UINT64_C(0),	// V_CMP_NE_I16_e32_gfx10
    UINT64_C(2102001664), UINT64_C(0),	// V_CMP_NE_I16_e32_vi
    UINT64_C(3566010368), UINT64_C(0),	// V_CMP_NE_I16_e64_gfx10
    UINT64_C(3500474368), UINT64_C(0),	// V_CMP_NE_I16_e64_vi
    UINT64_C(2087321600), UINT64_C(0),	// V_CMP_NE_I16_fake16_e32_dpp8_gfx11
    UINT64_C(2087321600), UINT64_C(0),	// V_CMP_NE_I16_fake16_e32_dpp8_gfx12
    UINT64_C(2087321600), UINT64_C(0),	// V_CMP_NE_I16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2087321600), UINT64_C(0),	// V_CMP_NE_I16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2087321600), UINT64_C(0),	// V_CMP_NE_I16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2087321600), UINT64_C(0),	// V_CMP_NE_I16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2087321850), UINT64_C(0),	// V_CMP_NE_I16_fake16_e32_dpp_gfx11
    UINT64_C(2087321850), UINT64_C(0),	// V_CMP_NE_I16_fake16_e32_dpp_gfx12
    UINT64_C(2087321850), UINT64_C(0),	// V_CMP_NE_I16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2087321850), UINT64_C(0),	// V_CMP_NE_I16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2087321850), UINT64_C(0),	// V_CMP_NE_I16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2087321850), UINT64_C(0),	// V_CMP_NE_I16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2087321600), UINT64_C(0),	// V_CMP_NE_I16_fake16_e32_gfx11
    UINT64_C(2087321600), UINT64_C(0),	// V_CMP_NE_I16_fake16_e32_gfx12
    UINT64_C(3560243200), UINT64_C(0),	// V_CMP_NE_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3560243200), UINT64_C(0),	// V_CMP_NE_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077302067200), UINT64_C(0),	// V_CMP_NE_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077302067200), UINT64_C(0),	// V_CMP_NE_I16_fake16_e64_dpp_gfx12
    UINT64_C(3560243200), UINT64_C(0),	// V_CMP_NE_I16_fake16_e64_gfx11
    UINT64_C(3560243200), UINT64_C(0),	// V_CMP_NE_I16_fake16_e64_gfx12
    UINT64_C(2098856185), UINT64_C(0),	// V_CMP_NE_I16_sdwa_gfx10
    UINT64_C(2102001913), UINT64_C(0),	// V_CMP_NE_I16_sdwa_gfx9
    UINT64_C(2102001913), UINT64_C(0),	// V_CMP_NE_I16_sdwa_vi
    UINT64_C(2087321600), UINT64_C(0),	// V_CMP_NE_I16_t16_e32_dpp8_gfx11
    UINT64_C(2087321600), UINT64_C(0),	// V_CMP_NE_I16_t16_e32_dpp8_gfx12
    UINT64_C(2087321600), UINT64_C(0),	// V_CMP_NE_I16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2087321600), UINT64_C(0),	// V_CMP_NE_I16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2087321600), UINT64_C(0),	// V_CMP_NE_I16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2087321600), UINT64_C(0),	// V_CMP_NE_I16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2087321850), UINT64_C(0),	// V_CMP_NE_I16_t16_e32_dpp_gfx11
    UINT64_C(2087321850), UINT64_C(0),	// V_CMP_NE_I16_t16_e32_dpp_gfx12
    UINT64_C(2087321850), UINT64_C(0),	// V_CMP_NE_I16_t16_e32_dpp_w32_gfx11
    UINT64_C(2087321850), UINT64_C(0),	// V_CMP_NE_I16_t16_e32_dpp_w32_gfx12
    UINT64_C(2087321850), UINT64_C(0),	// V_CMP_NE_I16_t16_e32_dpp_w64_gfx11
    UINT64_C(2087321850), UINT64_C(0),	// V_CMP_NE_I16_t16_e32_dpp_w64_gfx12
    UINT64_C(2087321600), UINT64_C(0),	// V_CMP_NE_I16_t16_e32_gfx11
    UINT64_C(2087321600), UINT64_C(0),	// V_CMP_NE_I16_t16_e32_gfx12
    UINT64_C(3560243200), UINT64_C(0),	// V_CMP_NE_I16_t16_e64_dpp8_gfx11
    UINT64_C(3560243200), UINT64_C(0),	// V_CMP_NE_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077302067200), UINT64_C(0),	// V_CMP_NE_I16_t16_e64_dpp_gfx11
    UINT64_C(1077302067200), UINT64_C(0),	// V_CMP_NE_I16_t16_e64_dpp_gfx12
    UINT64_C(3560243200), UINT64_C(0),	// V_CMP_NE_I16_t16_e64_gfx11
    UINT64_C(3560243200), UINT64_C(0),	// V_CMP_NE_I16_t16_e64_gfx12
    UINT64_C(2089418752), UINT64_C(0),	// V_CMP_NE_I32_e32_dpp8_gfx11
    UINT64_C(2089418752), UINT64_C(0),	// V_CMP_NE_I32_e32_dpp8_gfx12
    UINT64_C(2089418752), UINT64_C(0),	// V_CMP_NE_I32_e32_dpp8_w32_gfx11
    UINT64_C(2089418752), UINT64_C(0),	// V_CMP_NE_I32_e32_dpp8_w32_gfx12
    UINT64_C(2089418752), UINT64_C(0),	// V_CMP_NE_I32_e32_dpp8_w64_gfx11
    UINT64_C(2089418752), UINT64_C(0),	// V_CMP_NE_I32_e32_dpp8_w64_gfx12
    UINT64_C(2089419002), UINT64_C(0),	// V_CMP_NE_I32_e32_dpp_gfx11
    UINT64_C(2089419002), UINT64_C(0),	// V_CMP_NE_I32_e32_dpp_gfx12
    UINT64_C(2089419002), UINT64_C(0),	// V_CMP_NE_I32_e32_dpp_w32_gfx11
    UINT64_C(2089419002), UINT64_C(0),	// V_CMP_NE_I32_e32_dpp_w32_gfx12
    UINT64_C(2089419002), UINT64_C(0),	// V_CMP_NE_I32_e32_dpp_w64_gfx11
    UINT64_C(2089419002), UINT64_C(0),	// V_CMP_NE_I32_e32_dpp_w64_gfx12
    UINT64_C(2097807360), UINT64_C(0),	// V_CMP_NE_I32_e32_gfx10
    UINT64_C(2089418752), UINT64_C(0),	// V_CMP_NE_I32_e32_gfx11
    UINT64_C(2089418752), UINT64_C(0),	// V_CMP_NE_I32_e32_gfx12
    UINT64_C(2097807360), UINT64_C(0),	// V_CMP_NE_I32_e32_gfx6_gfx7
    UINT64_C(2106195968), UINT64_C(0),	// V_CMP_NE_I32_e32_vi
    UINT64_C(3561291776), UINT64_C(0),	// V_CMP_NE_I32_e64_dpp8_gfx11
    UINT64_C(3561291776), UINT64_C(0),	// V_CMP_NE_I32_e64_dpp8_gfx12
    UINT64_C(1077303115776), UINT64_C(0),	// V_CMP_NE_I32_e64_dpp_gfx11
    UINT64_C(1077303115776), UINT64_C(0),	// V_CMP_NE_I32_e64_dpp_gfx12
    UINT64_C(3565486080), UINT64_C(0),	// V_CMP_NE_I32_e64_gfx10
    UINT64_C(3561291776), UINT64_C(0),	// V_CMP_NE_I32_e64_gfx11
    UINT64_C(3561291776), UINT64_C(0),	// V_CMP_NE_I32_e64_gfx12
    UINT64_C(3507093504), UINT64_C(0),	// V_CMP_NE_I32_e64_gfx6_gfx7
    UINT64_C(3502571520), UINT64_C(0),	// V_CMP_NE_I32_e64_vi
    UINT64_C(2097807609), UINT64_C(0),	// V_CMP_NE_I32_sdwa_gfx10
    UINT64_C(2106196217), UINT64_C(0),	// V_CMP_NE_I32_sdwa_gfx9
    UINT64_C(2106196217), UINT64_C(0),	// V_CMP_NE_I32_sdwa_vi
    UINT64_C(2102001664), UINT64_C(0),	// V_CMP_NE_I64_e32_gfx10
    UINT64_C(2091515904), UINT64_C(0),	// V_CMP_NE_I64_e32_gfx11
    UINT64_C(2091515904), UINT64_C(0),	// V_CMP_NE_I64_e32_gfx12
    UINT64_C(2102001664), UINT64_C(0),	// V_CMP_NE_I64_e32_gfx6_gfx7
    UINT64_C(2110390272), UINT64_C(0),	// V_CMP_NE_I64_e32_vi
    UINT64_C(3567583232), UINT64_C(0),	// V_CMP_NE_I64_e64_gfx10
    UINT64_C(3562340352), UINT64_C(0),	// V_CMP_NE_I64_e64_gfx11
    UINT64_C(3562340352), UINT64_C(0),	// V_CMP_NE_I64_e64_gfx12
    UINT64_C(3511287808), UINT64_C(0),	// V_CMP_NE_I64_e64_gfx6_gfx7
    UINT64_C(3504668672), UINT64_C(0),	// V_CMP_NE_I64_e64_vi
    UINT64_C(2103050240), UINT64_C(0),	// V_CMP_NE_U16_e32_gfx10
    UINT64_C(2103050240), UINT64_C(0),	// V_CMP_NE_U16_e32_vi
    UINT64_C(3568107520), UINT64_C(0),	// V_CMP_NE_U16_e64_gfx10
    UINT64_C(3500998656), UINT64_C(0),	// V_CMP_NE_U16_e64_vi
    UINT64_C(2088370176), UINT64_C(0),	// V_CMP_NE_U16_fake16_e32_dpp8_gfx11
    UINT64_C(2088370176), UINT64_C(0),	// V_CMP_NE_U16_fake16_e32_dpp8_gfx12
    UINT64_C(2088370176), UINT64_C(0),	// V_CMP_NE_U16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2088370176), UINT64_C(0),	// V_CMP_NE_U16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2088370176), UINT64_C(0),	// V_CMP_NE_U16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2088370176), UINT64_C(0),	// V_CMP_NE_U16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2088370426), UINT64_C(0),	// V_CMP_NE_U16_fake16_e32_dpp_gfx11
    UINT64_C(2088370426), UINT64_C(0),	// V_CMP_NE_U16_fake16_e32_dpp_gfx12
    UINT64_C(2088370426), UINT64_C(0),	// V_CMP_NE_U16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2088370426), UINT64_C(0),	// V_CMP_NE_U16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2088370426), UINT64_C(0),	// V_CMP_NE_U16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2088370426), UINT64_C(0),	// V_CMP_NE_U16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2088370176), UINT64_C(0),	// V_CMP_NE_U16_fake16_e32_gfx11
    UINT64_C(2088370176), UINT64_C(0),	// V_CMP_NE_U16_fake16_e32_gfx12
    UINT64_C(3560767488), UINT64_C(0),	// V_CMP_NE_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3560767488), UINT64_C(0),	// V_CMP_NE_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077302591488), UINT64_C(0),	// V_CMP_NE_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077302591488), UINT64_C(0),	// V_CMP_NE_U16_fake16_e64_dpp_gfx12
    UINT64_C(3560767488), UINT64_C(0),	// V_CMP_NE_U16_fake16_e64_gfx11
    UINT64_C(3560767488), UINT64_C(0),	// V_CMP_NE_U16_fake16_e64_gfx12
    UINT64_C(2103050489), UINT64_C(0),	// V_CMP_NE_U16_sdwa_gfx10
    UINT64_C(2103050489), UINT64_C(0),	// V_CMP_NE_U16_sdwa_gfx9
    UINT64_C(2103050489), UINT64_C(0),	// V_CMP_NE_U16_sdwa_vi
    UINT64_C(2088370176), UINT64_C(0),	// V_CMP_NE_U16_t16_e32_dpp8_gfx11
    UINT64_C(2088370176), UINT64_C(0),	// V_CMP_NE_U16_t16_e32_dpp8_gfx12
    UINT64_C(2088370176), UINT64_C(0),	// V_CMP_NE_U16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2088370176), UINT64_C(0),	// V_CMP_NE_U16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2088370176), UINT64_C(0),	// V_CMP_NE_U16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2088370176), UINT64_C(0),	// V_CMP_NE_U16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2088370426), UINT64_C(0),	// V_CMP_NE_U16_t16_e32_dpp_gfx11
    UINT64_C(2088370426), UINT64_C(0),	// V_CMP_NE_U16_t16_e32_dpp_gfx12
    UINT64_C(2088370426), UINT64_C(0),	// V_CMP_NE_U16_t16_e32_dpp_w32_gfx11
    UINT64_C(2088370426), UINT64_C(0),	// V_CMP_NE_U16_t16_e32_dpp_w32_gfx12
    UINT64_C(2088370426), UINT64_C(0),	// V_CMP_NE_U16_t16_e32_dpp_w64_gfx11
    UINT64_C(2088370426), UINT64_C(0),	// V_CMP_NE_U16_t16_e32_dpp_w64_gfx12
    UINT64_C(2088370176), UINT64_C(0),	// V_CMP_NE_U16_t16_e32_gfx11
    UINT64_C(2088370176), UINT64_C(0),	// V_CMP_NE_U16_t16_e32_gfx12
    UINT64_C(3560767488), UINT64_C(0),	// V_CMP_NE_U16_t16_e64_dpp8_gfx11
    UINT64_C(3560767488), UINT64_C(0),	// V_CMP_NE_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077302591488), UINT64_C(0),	// V_CMP_NE_U16_t16_e64_dpp_gfx11
    UINT64_C(1077302591488), UINT64_C(0),	// V_CMP_NE_U16_t16_e64_dpp_gfx12
    UINT64_C(3560767488), UINT64_C(0),	// V_CMP_NE_U16_t16_e64_gfx11
    UINT64_C(3560767488), UINT64_C(0),	// V_CMP_NE_U16_t16_e64_gfx12
    UINT64_C(2090467328), UINT64_C(0),	// V_CMP_NE_U32_e32_dpp8_gfx11
    UINT64_C(2090467328), UINT64_C(0),	// V_CMP_NE_U32_e32_dpp8_gfx12
    UINT64_C(2090467328), UINT64_C(0),	// V_CMP_NE_U32_e32_dpp8_w32_gfx11
    UINT64_C(2090467328), UINT64_C(0),	// V_CMP_NE_U32_e32_dpp8_w32_gfx12
    UINT64_C(2090467328), UINT64_C(0),	// V_CMP_NE_U32_e32_dpp8_w64_gfx11
    UINT64_C(2090467328), UINT64_C(0),	// V_CMP_NE_U32_e32_dpp8_w64_gfx12
    UINT64_C(2090467578), UINT64_C(0),	// V_CMP_NE_U32_e32_dpp_gfx11
    UINT64_C(2090467578), UINT64_C(0),	// V_CMP_NE_U32_e32_dpp_gfx12
    UINT64_C(2090467578), UINT64_C(0),	// V_CMP_NE_U32_e32_dpp_w32_gfx11
    UINT64_C(2090467578), UINT64_C(0),	// V_CMP_NE_U32_e32_dpp_w32_gfx12
    UINT64_C(2090467578), UINT64_C(0),	// V_CMP_NE_U32_e32_dpp_w64_gfx11
    UINT64_C(2090467578), UINT64_C(0),	// V_CMP_NE_U32_e32_dpp_w64_gfx12
    UINT64_C(2106195968), UINT64_C(0),	// V_CMP_NE_U32_e32_gfx10
    UINT64_C(2090467328), UINT64_C(0),	// V_CMP_NE_U32_e32_gfx11
    UINT64_C(2090467328), UINT64_C(0),	// V_CMP_NE_U32_e32_gfx12
    UINT64_C(2106195968), UINT64_C(0),	// V_CMP_NE_U32_e32_gfx6_gfx7
    UINT64_C(2107244544), UINT64_C(0),	// V_CMP_NE_U32_e32_vi
    UINT64_C(3561816064), UINT64_C(0),	// V_CMP_NE_U32_e64_dpp8_gfx11
    UINT64_C(3561816064), UINT64_C(0),	// V_CMP_NE_U32_e64_dpp8_gfx12
    UINT64_C(1077303640064), UINT64_C(0),	// V_CMP_NE_U32_e64_dpp_gfx11
    UINT64_C(1077303640064), UINT64_C(0),	// V_CMP_NE_U32_e64_dpp_gfx12
    UINT64_C(3569680384), UINT64_C(0),	// V_CMP_NE_U32_e64_gfx10
    UINT64_C(3561816064), UINT64_C(0),	// V_CMP_NE_U32_e64_gfx11
    UINT64_C(3561816064), UINT64_C(0),	// V_CMP_NE_U32_e64_gfx12
    UINT64_C(3515482112), UINT64_C(0),	// V_CMP_NE_U32_e64_gfx6_gfx7
    UINT64_C(3503095808), UINT64_C(0),	// V_CMP_NE_U32_e64_vi
    UINT64_C(2106196217), UINT64_C(0),	// V_CMP_NE_U32_sdwa_gfx10
    UINT64_C(2107244793), UINT64_C(0),	// V_CMP_NE_U32_sdwa_gfx9
    UINT64_C(2107244793), UINT64_C(0),	// V_CMP_NE_U32_sdwa_vi
    UINT64_C(2110390272), UINT64_C(0),	// V_CMP_NE_U64_e32_gfx10
    UINT64_C(2092564480), UINT64_C(0),	// V_CMP_NE_U64_e32_gfx11
    UINT64_C(2092564480), UINT64_C(0),	// V_CMP_NE_U64_e32_gfx12
    UINT64_C(2110390272), UINT64_C(0),	// V_CMP_NE_U64_e32_gfx6_gfx7
    UINT64_C(2111438848), UINT64_C(0),	// V_CMP_NE_U64_e32_vi
    UINT64_C(3571777536), UINT64_C(0),	// V_CMP_NE_U64_e64_gfx10
    UINT64_C(3562864640), UINT64_C(0),	// V_CMP_NE_U64_e64_gfx11
    UINT64_C(3562864640), UINT64_C(0),	// V_CMP_NE_U64_e64_gfx12
    UINT64_C(3519676416), UINT64_C(0),	// V_CMP_NE_U64_e64_gfx6_gfx7
    UINT64_C(3505192960), UINT64_C(0),	// V_CMP_NE_U64_e64_vi
    UINT64_C(2110914560), UINT64_C(0),	// V_CMP_NGE_F16_e32_gfx10
    UINT64_C(2085748736), UINT64_C(0),	// V_CMP_NGE_F16_e32_vi
    UINT64_C(3572039680), UINT64_C(0),	// V_CMP_NGE_F16_e64_gfx10
    UINT64_C(3492347904), UINT64_C(0),	// V_CMP_NGE_F16_e64_vi
    UINT64_C(2081554432), UINT64_C(0),	// V_CMP_NGE_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2081554432), UINT64_C(0),	// V_CMP_NGE_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2081554432), UINT64_C(0),	// V_CMP_NGE_F16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2081554432), UINT64_C(0),	// V_CMP_NGE_F16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2081554432), UINT64_C(0),	// V_CMP_NGE_F16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2081554432), UINT64_C(0),	// V_CMP_NGE_F16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2081554682), UINT64_C(0),	// V_CMP_NGE_F16_fake16_e32_dpp_gfx11
    UINT64_C(2081554682), UINT64_C(0),	// V_CMP_NGE_F16_fake16_e32_dpp_gfx12
    UINT64_C(2081554682), UINT64_C(0),	// V_CMP_NGE_F16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2081554682), UINT64_C(0),	// V_CMP_NGE_F16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2081554682), UINT64_C(0),	// V_CMP_NGE_F16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2081554682), UINT64_C(0),	// V_CMP_NGE_F16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2081554432), UINT64_C(0),	// V_CMP_NGE_F16_fake16_e32_gfx11
    UINT64_C(2081554432), UINT64_C(0),	// V_CMP_NGE_F16_fake16_e32_gfx12
    UINT64_C(3557359616), UINT64_C(0),	// V_CMP_NGE_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3557359616), UINT64_C(0),	// V_CMP_NGE_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077299183616), UINT64_C(0),	// V_CMP_NGE_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077299183616), UINT64_C(0),	// V_CMP_NGE_F16_fake16_e64_dpp_gfx12
    UINT64_C(3557359616), UINT64_C(0),	// V_CMP_NGE_F16_fake16_e64_gfx11
    UINT64_C(3557359616), UINT64_C(0),	// V_CMP_NGE_F16_fake16_e64_gfx12
    UINT64_C(2110914809), UINT64_C(0),	// V_CMP_NGE_F16_sdwa_gfx10
    UINT64_C(2085748985), UINT64_C(0),	// V_CMP_NGE_F16_sdwa_gfx9
    UINT64_C(2085748985), UINT64_C(0),	// V_CMP_NGE_F16_sdwa_vi
    UINT64_C(2081554432), UINT64_C(0),	// V_CMP_NGE_F16_t16_e32_dpp8_gfx11
    UINT64_C(2081554432), UINT64_C(0),	// V_CMP_NGE_F16_t16_e32_dpp8_gfx12
    UINT64_C(2081554432), UINT64_C(0),	// V_CMP_NGE_F16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2081554432), UINT64_C(0),	// V_CMP_NGE_F16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2081554432), UINT64_C(0),	// V_CMP_NGE_F16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2081554432), UINT64_C(0),	// V_CMP_NGE_F16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2081554682), UINT64_C(0),	// V_CMP_NGE_F16_t16_e32_dpp_gfx11
    UINT64_C(2081554682), UINT64_C(0),	// V_CMP_NGE_F16_t16_e32_dpp_gfx12
    UINT64_C(2081554682), UINT64_C(0),	// V_CMP_NGE_F16_t16_e32_dpp_w32_gfx11
    UINT64_C(2081554682), UINT64_C(0),	// V_CMP_NGE_F16_t16_e32_dpp_w32_gfx12
    UINT64_C(2081554682), UINT64_C(0),	// V_CMP_NGE_F16_t16_e32_dpp_w64_gfx11
    UINT64_C(2081554682), UINT64_C(0),	// V_CMP_NGE_F16_t16_e32_dpp_w64_gfx12
    UINT64_C(2081554432), UINT64_C(0),	// V_CMP_NGE_F16_t16_e32_gfx11
    UINT64_C(2081554432), UINT64_C(0),	// V_CMP_NGE_F16_t16_e32_gfx12
    UINT64_C(3557359616), UINT64_C(0),	// V_CMP_NGE_F16_t16_e64_dpp8_gfx11
    UINT64_C(3557359616), UINT64_C(0),	// V_CMP_NGE_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077299183616), UINT64_C(0),	// V_CMP_NGE_F16_t16_e64_dpp_gfx11
    UINT64_C(1077299183616), UINT64_C(0),	// V_CMP_NGE_F16_t16_e64_dpp_gfx12
    UINT64_C(3557359616), UINT64_C(0),	// V_CMP_NGE_F16_t16_e64_gfx11
    UINT64_C(3557359616), UINT64_C(0),	// V_CMP_NGE_F16_t16_e64_gfx12
    UINT64_C(2083651584), UINT64_C(0),	// V_CMP_NGE_F32_e32_dpp8_gfx11
    UINT64_C(2083651584), UINT64_C(0),	// V_CMP_NGE_F32_e32_dpp8_gfx12
    UINT64_C(2083651584), UINT64_C(0),	// V_CMP_NGE_F32_e32_dpp8_w32_gfx11
    UINT64_C(2083651584), UINT64_C(0),	// V_CMP_NGE_F32_e32_dpp8_w32_gfx12
    UINT64_C(2083651584), UINT64_C(0),	// V_CMP_NGE_F32_e32_dpp8_w64_gfx11
    UINT64_C(2083651584), UINT64_C(0),	// V_CMP_NGE_F32_e32_dpp8_w64_gfx12
    UINT64_C(2083651834), UINT64_C(0),	// V_CMP_NGE_F32_e32_dpp_gfx11
    UINT64_C(2083651834), UINT64_C(0),	// V_CMP_NGE_F32_e32_dpp_gfx12
    UINT64_C(2083651834), UINT64_C(0),	// V_CMP_NGE_F32_e32_dpp_w32_gfx11
    UINT64_C(2083651834), UINT64_C(0),	// V_CMP_NGE_F32_e32_dpp_w32_gfx12
    UINT64_C(2083651834), UINT64_C(0),	// V_CMP_NGE_F32_e32_dpp_w64_gfx11
    UINT64_C(2083651834), UINT64_C(0),	// V_CMP_NGE_F32_e32_dpp_w64_gfx12
    UINT64_C(2081554432), UINT64_C(0),	// V_CMP_NGE_F32_e32_gfx10
    UINT64_C(2083651584), UINT64_C(0),	// V_CMP_NGE_F32_e32_gfx11
    UINT64_C(2083651584), UINT64_C(0),	// V_CMP_NGE_F32_e32_gfx12
    UINT64_C(2081554432), UINT64_C(0),	// V_CMP_NGE_F32_e32_gfx6_gfx7
    UINT64_C(2089943040), UINT64_C(0),	// V_CMP_NGE_F32_e32_vi
    UINT64_C(3558408192), UINT64_C(0),	// V_CMP_NGE_F32_e64_dpp8_gfx11
    UINT64_C(3558408192), UINT64_C(0),	// V_CMP_NGE_F32_e64_dpp8_gfx12
    UINT64_C(1077300232192), UINT64_C(0),	// V_CMP_NGE_F32_e64_dpp_gfx11
    UINT64_C(1077300232192), UINT64_C(0),	// V_CMP_NGE_F32_e64_dpp_gfx12
    UINT64_C(3557359616), UINT64_C(0),	// V_CMP_NGE_F32_e64_gfx10
    UINT64_C(3558408192), UINT64_C(0),	// V_CMP_NGE_F32_e64_gfx11
    UINT64_C(3558408192), UINT64_C(0),	// V_CMP_NGE_F32_e64_gfx12
    UINT64_C(3490840576), UINT64_C(0),	// V_CMP_NGE_F32_e64_gfx6_gfx7
    UINT64_C(3494445056), UINT64_C(0),	// V_CMP_NGE_F32_e64_vi
    UINT64_C(2081554681), UINT64_C(0),	// V_CMP_NGE_F32_sdwa_gfx10
    UINT64_C(2089943289), UINT64_C(0),	// V_CMP_NGE_F32_sdwa_gfx9
    UINT64_C(2089943289), UINT64_C(0),	// V_CMP_NGE_F32_sdwa_vi
    UINT64_C(2085748736), UINT64_C(0),	// V_CMP_NGE_F64_e32_gfx10
    UINT64_C(2085748736), UINT64_C(0),	// V_CMP_NGE_F64_e32_gfx11
    UINT64_C(2085748736), UINT64_C(0),	// V_CMP_NGE_F64_e32_gfx12
    UINT64_C(2085748736), UINT64_C(0),	// V_CMP_NGE_F64_e32_gfx6_gfx7
    UINT64_C(2094137344), UINT64_C(0),	// V_CMP_NGE_F64_e32_vi
    UINT64_C(3559456768), UINT64_C(0),	// V_CMP_NGE_F64_e64_gfx10
    UINT64_C(3559456768), UINT64_C(0),	// V_CMP_NGE_F64_e64_gfx11
    UINT64_C(3559456768), UINT64_C(0),	// V_CMP_NGE_F64_e64_gfx12
    UINT64_C(3495034880), UINT64_C(0),	// V_CMP_NGE_F64_e64_gfx6_gfx7
    UINT64_C(3496542208), UINT64_C(0),	// V_CMP_NGE_F64_e64_vi
    UINT64_C(2111176704), UINT64_C(0),	// V_CMP_NGT_F16_e32_gfx10
    UINT64_C(2086010880), UINT64_C(0),	// V_CMP_NGT_F16_e32_vi
    UINT64_C(3572170752), UINT64_C(0),	// V_CMP_NGT_F16_e64_gfx10
    UINT64_C(3492478976), UINT64_C(0),	// V_CMP_NGT_F16_e64_vi
    UINT64_C(2081816576), UINT64_C(0),	// V_CMP_NGT_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2081816576), UINT64_C(0),	// V_CMP_NGT_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2081816576), UINT64_C(0),	// V_CMP_NGT_F16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2081816576), UINT64_C(0),	// V_CMP_NGT_F16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2081816576), UINT64_C(0),	// V_CMP_NGT_F16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2081816576), UINT64_C(0),	// V_CMP_NGT_F16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2081816826), UINT64_C(0),	// V_CMP_NGT_F16_fake16_e32_dpp_gfx11
    UINT64_C(2081816826), UINT64_C(0),	// V_CMP_NGT_F16_fake16_e32_dpp_gfx12
    UINT64_C(2081816826), UINT64_C(0),	// V_CMP_NGT_F16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2081816826), UINT64_C(0),	// V_CMP_NGT_F16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2081816826), UINT64_C(0),	// V_CMP_NGT_F16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2081816826), UINT64_C(0),	// V_CMP_NGT_F16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2081816576), UINT64_C(0),	// V_CMP_NGT_F16_fake16_e32_gfx11
    UINT64_C(2081816576), UINT64_C(0),	// V_CMP_NGT_F16_fake16_e32_gfx12
    UINT64_C(3557490688), UINT64_C(0),	// V_CMP_NGT_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3557490688), UINT64_C(0),	// V_CMP_NGT_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077299314688), UINT64_C(0),	// V_CMP_NGT_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077299314688), UINT64_C(0),	// V_CMP_NGT_F16_fake16_e64_dpp_gfx12
    UINT64_C(3557490688), UINT64_C(0),	// V_CMP_NGT_F16_fake16_e64_gfx11
    UINT64_C(3557490688), UINT64_C(0),	// V_CMP_NGT_F16_fake16_e64_gfx12
    UINT64_C(2111176953), UINT64_C(0),	// V_CMP_NGT_F16_sdwa_gfx10
    UINT64_C(2086011129), UINT64_C(0),	// V_CMP_NGT_F16_sdwa_gfx9
    UINT64_C(2086011129), UINT64_C(0),	// V_CMP_NGT_F16_sdwa_vi
    UINT64_C(2081816576), UINT64_C(0),	// V_CMP_NGT_F16_t16_e32_dpp8_gfx11
    UINT64_C(2081816576), UINT64_C(0),	// V_CMP_NGT_F16_t16_e32_dpp8_gfx12
    UINT64_C(2081816576), UINT64_C(0),	// V_CMP_NGT_F16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2081816576), UINT64_C(0),	// V_CMP_NGT_F16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2081816576), UINT64_C(0),	// V_CMP_NGT_F16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2081816576), UINT64_C(0),	// V_CMP_NGT_F16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2081816826), UINT64_C(0),	// V_CMP_NGT_F16_t16_e32_dpp_gfx11
    UINT64_C(2081816826), UINT64_C(0),	// V_CMP_NGT_F16_t16_e32_dpp_gfx12
    UINT64_C(2081816826), UINT64_C(0),	// V_CMP_NGT_F16_t16_e32_dpp_w32_gfx11
    UINT64_C(2081816826), UINT64_C(0),	// V_CMP_NGT_F16_t16_e32_dpp_w32_gfx12
    UINT64_C(2081816826), UINT64_C(0),	// V_CMP_NGT_F16_t16_e32_dpp_w64_gfx11
    UINT64_C(2081816826), UINT64_C(0),	// V_CMP_NGT_F16_t16_e32_dpp_w64_gfx12
    UINT64_C(2081816576), UINT64_C(0),	// V_CMP_NGT_F16_t16_e32_gfx11
    UINT64_C(2081816576), UINT64_C(0),	// V_CMP_NGT_F16_t16_e32_gfx12
    UINT64_C(3557490688), UINT64_C(0),	// V_CMP_NGT_F16_t16_e64_dpp8_gfx11
    UINT64_C(3557490688), UINT64_C(0),	// V_CMP_NGT_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077299314688), UINT64_C(0),	// V_CMP_NGT_F16_t16_e64_dpp_gfx11
    UINT64_C(1077299314688), UINT64_C(0),	// V_CMP_NGT_F16_t16_e64_dpp_gfx12
    UINT64_C(3557490688), UINT64_C(0),	// V_CMP_NGT_F16_t16_e64_gfx11
    UINT64_C(3557490688), UINT64_C(0),	// V_CMP_NGT_F16_t16_e64_gfx12
    UINT64_C(2083913728), UINT64_C(0),	// V_CMP_NGT_F32_e32_dpp8_gfx11
    UINT64_C(2083913728), UINT64_C(0),	// V_CMP_NGT_F32_e32_dpp8_gfx12
    UINT64_C(2083913728), UINT64_C(0),	// V_CMP_NGT_F32_e32_dpp8_w32_gfx11
    UINT64_C(2083913728), UINT64_C(0),	// V_CMP_NGT_F32_e32_dpp8_w32_gfx12
    UINT64_C(2083913728), UINT64_C(0),	// V_CMP_NGT_F32_e32_dpp8_w64_gfx11
    UINT64_C(2083913728), UINT64_C(0),	// V_CMP_NGT_F32_e32_dpp8_w64_gfx12
    UINT64_C(2083913978), UINT64_C(0),	// V_CMP_NGT_F32_e32_dpp_gfx11
    UINT64_C(2083913978), UINT64_C(0),	// V_CMP_NGT_F32_e32_dpp_gfx12
    UINT64_C(2083913978), UINT64_C(0),	// V_CMP_NGT_F32_e32_dpp_w32_gfx11
    UINT64_C(2083913978), UINT64_C(0),	// V_CMP_NGT_F32_e32_dpp_w32_gfx12
    UINT64_C(2083913978), UINT64_C(0),	// V_CMP_NGT_F32_e32_dpp_w64_gfx11
    UINT64_C(2083913978), UINT64_C(0),	// V_CMP_NGT_F32_e32_dpp_w64_gfx12
    UINT64_C(2081816576), UINT64_C(0),	// V_CMP_NGT_F32_e32_gfx10
    UINT64_C(2083913728), UINT64_C(0),	// V_CMP_NGT_F32_e32_gfx11
    UINT64_C(2083913728), UINT64_C(0),	// V_CMP_NGT_F32_e32_gfx12
    UINT64_C(2081816576), UINT64_C(0),	// V_CMP_NGT_F32_e32_gfx6_gfx7
    UINT64_C(2090205184), UINT64_C(0),	// V_CMP_NGT_F32_e32_vi
    UINT64_C(3558539264), UINT64_C(0),	// V_CMP_NGT_F32_e64_dpp8_gfx11
    UINT64_C(3558539264), UINT64_C(0),	// V_CMP_NGT_F32_e64_dpp8_gfx12
    UINT64_C(1077300363264), UINT64_C(0),	// V_CMP_NGT_F32_e64_dpp_gfx11
    UINT64_C(1077300363264), UINT64_C(0),	// V_CMP_NGT_F32_e64_dpp_gfx12
    UINT64_C(3557490688), UINT64_C(0),	// V_CMP_NGT_F32_e64_gfx10
    UINT64_C(3558539264), UINT64_C(0),	// V_CMP_NGT_F32_e64_gfx11
    UINT64_C(3558539264), UINT64_C(0),	// V_CMP_NGT_F32_e64_gfx12
    UINT64_C(3491102720), UINT64_C(0),	// V_CMP_NGT_F32_e64_gfx6_gfx7
    UINT64_C(3494576128), UINT64_C(0),	// V_CMP_NGT_F32_e64_vi
    UINT64_C(2081816825), UINT64_C(0),	// V_CMP_NGT_F32_sdwa_gfx10
    UINT64_C(2090205433), UINT64_C(0),	// V_CMP_NGT_F32_sdwa_gfx9
    UINT64_C(2090205433), UINT64_C(0),	// V_CMP_NGT_F32_sdwa_vi
    UINT64_C(2086010880), UINT64_C(0),	// V_CMP_NGT_F64_e32_gfx10
    UINT64_C(2086010880), UINT64_C(0),	// V_CMP_NGT_F64_e32_gfx11
    UINT64_C(2086010880), UINT64_C(0),	// V_CMP_NGT_F64_e32_gfx12
    UINT64_C(2086010880), UINT64_C(0),	// V_CMP_NGT_F64_e32_gfx6_gfx7
    UINT64_C(2094399488), UINT64_C(0),	// V_CMP_NGT_F64_e32_vi
    UINT64_C(3559587840), UINT64_C(0),	// V_CMP_NGT_F64_e64_gfx10
    UINT64_C(3559587840), UINT64_C(0),	// V_CMP_NGT_F64_e64_gfx11
    UINT64_C(3559587840), UINT64_C(0),	// V_CMP_NGT_F64_e64_gfx12
    UINT64_C(3495297024), UINT64_C(0),	// V_CMP_NGT_F64_e64_gfx6_gfx7
    UINT64_C(3496673280), UINT64_C(0),	// V_CMP_NGT_F64_e64_vi
    UINT64_C(2111307776), UINT64_C(0),	// V_CMP_NLE_F16_e32_gfx10
    UINT64_C(2086141952), UINT64_C(0),	// V_CMP_NLE_F16_e32_vi
    UINT64_C(3572236288), UINT64_C(0),	// V_CMP_NLE_F16_e64_gfx10
    UINT64_C(3492544512), UINT64_C(0),	// V_CMP_NLE_F16_e64_vi
    UINT64_C(2081947648), UINT64_C(0),	// V_CMP_NLE_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2081947648), UINT64_C(0),	// V_CMP_NLE_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2081947648), UINT64_C(0),	// V_CMP_NLE_F16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2081947648), UINT64_C(0),	// V_CMP_NLE_F16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2081947648), UINT64_C(0),	// V_CMP_NLE_F16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2081947648), UINT64_C(0),	// V_CMP_NLE_F16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2081947898), UINT64_C(0),	// V_CMP_NLE_F16_fake16_e32_dpp_gfx11
    UINT64_C(2081947898), UINT64_C(0),	// V_CMP_NLE_F16_fake16_e32_dpp_gfx12
    UINT64_C(2081947898), UINT64_C(0),	// V_CMP_NLE_F16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2081947898), UINT64_C(0),	// V_CMP_NLE_F16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2081947898), UINT64_C(0),	// V_CMP_NLE_F16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2081947898), UINT64_C(0),	// V_CMP_NLE_F16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2081947648), UINT64_C(0),	// V_CMP_NLE_F16_fake16_e32_gfx11
    UINT64_C(2081947648), UINT64_C(0),	// V_CMP_NLE_F16_fake16_e32_gfx12
    UINT64_C(3557556224), UINT64_C(0),	// V_CMP_NLE_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3557556224), UINT64_C(0),	// V_CMP_NLE_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077299380224), UINT64_C(0),	// V_CMP_NLE_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077299380224), UINT64_C(0),	// V_CMP_NLE_F16_fake16_e64_dpp_gfx12
    UINT64_C(3557556224), UINT64_C(0),	// V_CMP_NLE_F16_fake16_e64_gfx11
    UINT64_C(3557556224), UINT64_C(0),	// V_CMP_NLE_F16_fake16_e64_gfx12
    UINT64_C(2111308025), UINT64_C(0),	// V_CMP_NLE_F16_sdwa_gfx10
    UINT64_C(2086142201), UINT64_C(0),	// V_CMP_NLE_F16_sdwa_gfx9
    UINT64_C(2086142201), UINT64_C(0),	// V_CMP_NLE_F16_sdwa_vi
    UINT64_C(2081947648), UINT64_C(0),	// V_CMP_NLE_F16_t16_e32_dpp8_gfx11
    UINT64_C(2081947648), UINT64_C(0),	// V_CMP_NLE_F16_t16_e32_dpp8_gfx12
    UINT64_C(2081947648), UINT64_C(0),	// V_CMP_NLE_F16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2081947648), UINT64_C(0),	// V_CMP_NLE_F16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2081947648), UINT64_C(0),	// V_CMP_NLE_F16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2081947648), UINT64_C(0),	// V_CMP_NLE_F16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2081947898), UINT64_C(0),	// V_CMP_NLE_F16_t16_e32_dpp_gfx11
    UINT64_C(2081947898), UINT64_C(0),	// V_CMP_NLE_F16_t16_e32_dpp_gfx12
    UINT64_C(2081947898), UINT64_C(0),	// V_CMP_NLE_F16_t16_e32_dpp_w32_gfx11
    UINT64_C(2081947898), UINT64_C(0),	// V_CMP_NLE_F16_t16_e32_dpp_w32_gfx12
    UINT64_C(2081947898), UINT64_C(0),	// V_CMP_NLE_F16_t16_e32_dpp_w64_gfx11
    UINT64_C(2081947898), UINT64_C(0),	// V_CMP_NLE_F16_t16_e32_dpp_w64_gfx12
    UINT64_C(2081947648), UINT64_C(0),	// V_CMP_NLE_F16_t16_e32_gfx11
    UINT64_C(2081947648), UINT64_C(0),	// V_CMP_NLE_F16_t16_e32_gfx12
    UINT64_C(3557556224), UINT64_C(0),	// V_CMP_NLE_F16_t16_e64_dpp8_gfx11
    UINT64_C(3557556224), UINT64_C(0),	// V_CMP_NLE_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077299380224), UINT64_C(0),	// V_CMP_NLE_F16_t16_e64_dpp_gfx11
    UINT64_C(1077299380224), UINT64_C(0),	// V_CMP_NLE_F16_t16_e64_dpp_gfx12
    UINT64_C(3557556224), UINT64_C(0),	// V_CMP_NLE_F16_t16_e64_gfx11
    UINT64_C(3557556224), UINT64_C(0),	// V_CMP_NLE_F16_t16_e64_gfx12
    UINT64_C(2084044800), UINT64_C(0),	// V_CMP_NLE_F32_e32_dpp8_gfx11
    UINT64_C(2084044800), UINT64_C(0),	// V_CMP_NLE_F32_e32_dpp8_gfx12
    UINT64_C(2084044800), UINT64_C(0),	// V_CMP_NLE_F32_e32_dpp8_w32_gfx11
    UINT64_C(2084044800), UINT64_C(0),	// V_CMP_NLE_F32_e32_dpp8_w32_gfx12
    UINT64_C(2084044800), UINT64_C(0),	// V_CMP_NLE_F32_e32_dpp8_w64_gfx11
    UINT64_C(2084044800), UINT64_C(0),	// V_CMP_NLE_F32_e32_dpp8_w64_gfx12
    UINT64_C(2084045050), UINT64_C(0),	// V_CMP_NLE_F32_e32_dpp_gfx11
    UINT64_C(2084045050), UINT64_C(0),	// V_CMP_NLE_F32_e32_dpp_gfx12
    UINT64_C(2084045050), UINT64_C(0),	// V_CMP_NLE_F32_e32_dpp_w32_gfx11
    UINT64_C(2084045050), UINT64_C(0),	// V_CMP_NLE_F32_e32_dpp_w32_gfx12
    UINT64_C(2084045050), UINT64_C(0),	// V_CMP_NLE_F32_e32_dpp_w64_gfx11
    UINT64_C(2084045050), UINT64_C(0),	// V_CMP_NLE_F32_e32_dpp_w64_gfx12
    UINT64_C(2081947648), UINT64_C(0),	// V_CMP_NLE_F32_e32_gfx10
    UINT64_C(2084044800), UINT64_C(0),	// V_CMP_NLE_F32_e32_gfx11
    UINT64_C(2084044800), UINT64_C(0),	// V_CMP_NLE_F32_e32_gfx12
    UINT64_C(2081947648), UINT64_C(0),	// V_CMP_NLE_F32_e32_gfx6_gfx7
    UINT64_C(2090336256), UINT64_C(0),	// V_CMP_NLE_F32_e32_vi
    UINT64_C(3558604800), UINT64_C(0),	// V_CMP_NLE_F32_e64_dpp8_gfx11
    UINT64_C(3558604800), UINT64_C(0),	// V_CMP_NLE_F32_e64_dpp8_gfx12
    UINT64_C(1077300428800), UINT64_C(0),	// V_CMP_NLE_F32_e64_dpp_gfx11
    UINT64_C(1077300428800), UINT64_C(0),	// V_CMP_NLE_F32_e64_dpp_gfx12
    UINT64_C(3557556224), UINT64_C(0),	// V_CMP_NLE_F32_e64_gfx10
    UINT64_C(3558604800), UINT64_C(0),	// V_CMP_NLE_F32_e64_gfx11
    UINT64_C(3558604800), UINT64_C(0),	// V_CMP_NLE_F32_e64_gfx12
    UINT64_C(3491233792), UINT64_C(0),	// V_CMP_NLE_F32_e64_gfx6_gfx7
    UINT64_C(3494641664), UINT64_C(0),	// V_CMP_NLE_F32_e64_vi
    UINT64_C(2081947897), UINT64_C(0),	// V_CMP_NLE_F32_sdwa_gfx10
    UINT64_C(2090336505), UINT64_C(0),	// V_CMP_NLE_F32_sdwa_gfx9
    UINT64_C(2090336505), UINT64_C(0),	// V_CMP_NLE_F32_sdwa_vi
    UINT64_C(2086141952), UINT64_C(0),	// V_CMP_NLE_F64_e32_gfx10
    UINT64_C(2086141952), UINT64_C(0),	// V_CMP_NLE_F64_e32_gfx11
    UINT64_C(2086141952), UINT64_C(0),	// V_CMP_NLE_F64_e32_gfx12
    UINT64_C(2086141952), UINT64_C(0),	// V_CMP_NLE_F64_e32_gfx6_gfx7
    UINT64_C(2094530560), UINT64_C(0),	// V_CMP_NLE_F64_e32_vi
    UINT64_C(3559653376), UINT64_C(0),	// V_CMP_NLE_F64_e64_gfx10
    UINT64_C(3559653376), UINT64_C(0),	// V_CMP_NLE_F64_e64_gfx11
    UINT64_C(3559653376), UINT64_C(0),	// V_CMP_NLE_F64_e64_gfx12
    UINT64_C(3495428096), UINT64_C(0),	// V_CMP_NLE_F64_e64_gfx6_gfx7
    UINT64_C(3496738816), UINT64_C(0),	// V_CMP_NLE_F64_e64_vi
    UINT64_C(2111045632), UINT64_C(0),	// V_CMP_NLG_F16_e32_gfx10
    UINT64_C(2085879808), UINT64_C(0),	// V_CMP_NLG_F16_e32_vi
    UINT64_C(3572105216), UINT64_C(0),	// V_CMP_NLG_F16_e64_gfx10
    UINT64_C(3492413440), UINT64_C(0),	// V_CMP_NLG_F16_e64_vi
    UINT64_C(2081685504), UINT64_C(0),	// V_CMP_NLG_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2081685504), UINT64_C(0),	// V_CMP_NLG_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2081685504), UINT64_C(0),	// V_CMP_NLG_F16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2081685504), UINT64_C(0),	// V_CMP_NLG_F16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2081685504), UINT64_C(0),	// V_CMP_NLG_F16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2081685504), UINT64_C(0),	// V_CMP_NLG_F16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2081685754), UINT64_C(0),	// V_CMP_NLG_F16_fake16_e32_dpp_gfx11
    UINT64_C(2081685754), UINT64_C(0),	// V_CMP_NLG_F16_fake16_e32_dpp_gfx12
    UINT64_C(2081685754), UINT64_C(0),	// V_CMP_NLG_F16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2081685754), UINT64_C(0),	// V_CMP_NLG_F16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2081685754), UINT64_C(0),	// V_CMP_NLG_F16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2081685754), UINT64_C(0),	// V_CMP_NLG_F16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2081685504), UINT64_C(0),	// V_CMP_NLG_F16_fake16_e32_gfx11
    UINT64_C(2081685504), UINT64_C(0),	// V_CMP_NLG_F16_fake16_e32_gfx12
    UINT64_C(3557425152), UINT64_C(0),	// V_CMP_NLG_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3557425152), UINT64_C(0),	// V_CMP_NLG_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077299249152), UINT64_C(0),	// V_CMP_NLG_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077299249152), UINT64_C(0),	// V_CMP_NLG_F16_fake16_e64_dpp_gfx12
    UINT64_C(3557425152), UINT64_C(0),	// V_CMP_NLG_F16_fake16_e64_gfx11
    UINT64_C(3557425152), UINT64_C(0),	// V_CMP_NLG_F16_fake16_e64_gfx12
    UINT64_C(2111045881), UINT64_C(0),	// V_CMP_NLG_F16_sdwa_gfx10
    UINT64_C(2085880057), UINT64_C(0),	// V_CMP_NLG_F16_sdwa_gfx9
    UINT64_C(2085880057), UINT64_C(0),	// V_CMP_NLG_F16_sdwa_vi
    UINT64_C(2081685504), UINT64_C(0),	// V_CMP_NLG_F16_t16_e32_dpp8_gfx11
    UINT64_C(2081685504), UINT64_C(0),	// V_CMP_NLG_F16_t16_e32_dpp8_gfx12
    UINT64_C(2081685504), UINT64_C(0),	// V_CMP_NLG_F16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2081685504), UINT64_C(0),	// V_CMP_NLG_F16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2081685504), UINT64_C(0),	// V_CMP_NLG_F16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2081685504), UINT64_C(0),	// V_CMP_NLG_F16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2081685754), UINT64_C(0),	// V_CMP_NLG_F16_t16_e32_dpp_gfx11
    UINT64_C(2081685754), UINT64_C(0),	// V_CMP_NLG_F16_t16_e32_dpp_gfx12
    UINT64_C(2081685754), UINT64_C(0),	// V_CMP_NLG_F16_t16_e32_dpp_w32_gfx11
    UINT64_C(2081685754), UINT64_C(0),	// V_CMP_NLG_F16_t16_e32_dpp_w32_gfx12
    UINT64_C(2081685754), UINT64_C(0),	// V_CMP_NLG_F16_t16_e32_dpp_w64_gfx11
    UINT64_C(2081685754), UINT64_C(0),	// V_CMP_NLG_F16_t16_e32_dpp_w64_gfx12
    UINT64_C(2081685504), UINT64_C(0),	// V_CMP_NLG_F16_t16_e32_gfx11
    UINT64_C(2081685504), UINT64_C(0),	// V_CMP_NLG_F16_t16_e32_gfx12
    UINT64_C(3557425152), UINT64_C(0),	// V_CMP_NLG_F16_t16_e64_dpp8_gfx11
    UINT64_C(3557425152), UINT64_C(0),	// V_CMP_NLG_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077299249152), UINT64_C(0),	// V_CMP_NLG_F16_t16_e64_dpp_gfx11
    UINT64_C(1077299249152), UINT64_C(0),	// V_CMP_NLG_F16_t16_e64_dpp_gfx12
    UINT64_C(3557425152), UINT64_C(0),	// V_CMP_NLG_F16_t16_e64_gfx11
    UINT64_C(3557425152), UINT64_C(0),	// V_CMP_NLG_F16_t16_e64_gfx12
    UINT64_C(2083782656), UINT64_C(0),	// V_CMP_NLG_F32_e32_dpp8_gfx11
    UINT64_C(2083782656), UINT64_C(0),	// V_CMP_NLG_F32_e32_dpp8_gfx12
    UINT64_C(2083782656), UINT64_C(0),	// V_CMP_NLG_F32_e32_dpp8_w32_gfx11
    UINT64_C(2083782656), UINT64_C(0),	// V_CMP_NLG_F32_e32_dpp8_w32_gfx12
    UINT64_C(2083782656), UINT64_C(0),	// V_CMP_NLG_F32_e32_dpp8_w64_gfx11
    UINT64_C(2083782656), UINT64_C(0),	// V_CMP_NLG_F32_e32_dpp8_w64_gfx12
    UINT64_C(2083782906), UINT64_C(0),	// V_CMP_NLG_F32_e32_dpp_gfx11
    UINT64_C(2083782906), UINT64_C(0),	// V_CMP_NLG_F32_e32_dpp_gfx12
    UINT64_C(2083782906), UINT64_C(0),	// V_CMP_NLG_F32_e32_dpp_w32_gfx11
    UINT64_C(2083782906), UINT64_C(0),	// V_CMP_NLG_F32_e32_dpp_w32_gfx12
    UINT64_C(2083782906), UINT64_C(0),	// V_CMP_NLG_F32_e32_dpp_w64_gfx11
    UINT64_C(2083782906), UINT64_C(0),	// V_CMP_NLG_F32_e32_dpp_w64_gfx12
    UINT64_C(2081685504), UINT64_C(0),	// V_CMP_NLG_F32_e32_gfx10
    UINT64_C(2083782656), UINT64_C(0),	// V_CMP_NLG_F32_e32_gfx11
    UINT64_C(2083782656), UINT64_C(0),	// V_CMP_NLG_F32_e32_gfx12
    UINT64_C(2081685504), UINT64_C(0),	// V_CMP_NLG_F32_e32_gfx6_gfx7
    UINT64_C(2090074112), UINT64_C(0),	// V_CMP_NLG_F32_e32_vi
    UINT64_C(3558473728), UINT64_C(0),	// V_CMP_NLG_F32_e64_dpp8_gfx11
    UINT64_C(3558473728), UINT64_C(0),	// V_CMP_NLG_F32_e64_dpp8_gfx12
    UINT64_C(1077300297728), UINT64_C(0),	// V_CMP_NLG_F32_e64_dpp_gfx11
    UINT64_C(1077300297728), UINT64_C(0),	// V_CMP_NLG_F32_e64_dpp_gfx12
    UINT64_C(3557425152), UINT64_C(0),	// V_CMP_NLG_F32_e64_gfx10
    UINT64_C(3558473728), UINT64_C(0),	// V_CMP_NLG_F32_e64_gfx11
    UINT64_C(3558473728), UINT64_C(0),	// V_CMP_NLG_F32_e64_gfx12
    UINT64_C(3490971648), UINT64_C(0),	// V_CMP_NLG_F32_e64_gfx6_gfx7
    UINT64_C(3494510592), UINT64_C(0),	// V_CMP_NLG_F32_e64_vi
    UINT64_C(2081685753), UINT64_C(0),	// V_CMP_NLG_F32_sdwa_gfx10
    UINT64_C(2090074361), UINT64_C(0),	// V_CMP_NLG_F32_sdwa_gfx9
    UINT64_C(2090074361), UINT64_C(0),	// V_CMP_NLG_F32_sdwa_vi
    UINT64_C(2085879808), UINT64_C(0),	// V_CMP_NLG_F64_e32_gfx10
    UINT64_C(2085879808), UINT64_C(0),	// V_CMP_NLG_F64_e32_gfx11
    UINT64_C(2085879808), UINT64_C(0),	// V_CMP_NLG_F64_e32_gfx12
    UINT64_C(2085879808), UINT64_C(0),	// V_CMP_NLG_F64_e32_gfx6_gfx7
    UINT64_C(2094268416), UINT64_C(0),	// V_CMP_NLG_F64_e32_vi
    UINT64_C(3559522304), UINT64_C(0),	// V_CMP_NLG_F64_e64_gfx10
    UINT64_C(3559522304), UINT64_C(0),	// V_CMP_NLG_F64_e64_gfx11
    UINT64_C(3559522304), UINT64_C(0),	// V_CMP_NLG_F64_e64_gfx12
    UINT64_C(3495165952), UINT64_C(0),	// V_CMP_NLG_F64_e64_gfx6_gfx7
    UINT64_C(3496607744), UINT64_C(0),	// V_CMP_NLG_F64_e64_vi
    UINT64_C(2111569920), UINT64_C(0),	// V_CMP_NLT_F16_e32_gfx10
    UINT64_C(2086404096), UINT64_C(0),	// V_CMP_NLT_F16_e32_vi
    UINT64_C(3572367360), UINT64_C(0),	// V_CMP_NLT_F16_e64_gfx10
    UINT64_C(3492675584), UINT64_C(0),	// V_CMP_NLT_F16_e64_vi
    UINT64_C(2082209792), UINT64_C(0),	// V_CMP_NLT_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2082209792), UINT64_C(0),	// V_CMP_NLT_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2082209792), UINT64_C(0),	// V_CMP_NLT_F16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2082209792), UINT64_C(0),	// V_CMP_NLT_F16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2082209792), UINT64_C(0),	// V_CMP_NLT_F16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2082209792), UINT64_C(0),	// V_CMP_NLT_F16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2082210042), UINT64_C(0),	// V_CMP_NLT_F16_fake16_e32_dpp_gfx11
    UINT64_C(2082210042), UINT64_C(0),	// V_CMP_NLT_F16_fake16_e32_dpp_gfx12
    UINT64_C(2082210042), UINT64_C(0),	// V_CMP_NLT_F16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2082210042), UINT64_C(0),	// V_CMP_NLT_F16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2082210042), UINT64_C(0),	// V_CMP_NLT_F16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2082210042), UINT64_C(0),	// V_CMP_NLT_F16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2082209792), UINT64_C(0),	// V_CMP_NLT_F16_fake16_e32_gfx11
    UINT64_C(2082209792), UINT64_C(0),	// V_CMP_NLT_F16_fake16_e32_gfx12
    UINT64_C(3557687296), UINT64_C(0),	// V_CMP_NLT_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3557687296), UINT64_C(0),	// V_CMP_NLT_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077299511296), UINT64_C(0),	// V_CMP_NLT_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077299511296), UINT64_C(0),	// V_CMP_NLT_F16_fake16_e64_dpp_gfx12
    UINT64_C(3557687296), UINT64_C(0),	// V_CMP_NLT_F16_fake16_e64_gfx11
    UINT64_C(3557687296), UINT64_C(0),	// V_CMP_NLT_F16_fake16_e64_gfx12
    UINT64_C(2111570169), UINT64_C(0),	// V_CMP_NLT_F16_sdwa_gfx10
    UINT64_C(2086404345), UINT64_C(0),	// V_CMP_NLT_F16_sdwa_gfx9
    UINT64_C(2086404345), UINT64_C(0),	// V_CMP_NLT_F16_sdwa_vi
    UINT64_C(2082209792), UINT64_C(0),	// V_CMP_NLT_F16_t16_e32_dpp8_gfx11
    UINT64_C(2082209792), UINT64_C(0),	// V_CMP_NLT_F16_t16_e32_dpp8_gfx12
    UINT64_C(2082209792), UINT64_C(0),	// V_CMP_NLT_F16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2082209792), UINT64_C(0),	// V_CMP_NLT_F16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2082209792), UINT64_C(0),	// V_CMP_NLT_F16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2082209792), UINT64_C(0),	// V_CMP_NLT_F16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2082210042), UINT64_C(0),	// V_CMP_NLT_F16_t16_e32_dpp_gfx11
    UINT64_C(2082210042), UINT64_C(0),	// V_CMP_NLT_F16_t16_e32_dpp_gfx12
    UINT64_C(2082210042), UINT64_C(0),	// V_CMP_NLT_F16_t16_e32_dpp_w32_gfx11
    UINT64_C(2082210042), UINT64_C(0),	// V_CMP_NLT_F16_t16_e32_dpp_w32_gfx12
    UINT64_C(2082210042), UINT64_C(0),	// V_CMP_NLT_F16_t16_e32_dpp_w64_gfx11
    UINT64_C(2082210042), UINT64_C(0),	// V_CMP_NLT_F16_t16_e32_dpp_w64_gfx12
    UINT64_C(2082209792), UINT64_C(0),	// V_CMP_NLT_F16_t16_e32_gfx11
    UINT64_C(2082209792), UINT64_C(0),	// V_CMP_NLT_F16_t16_e32_gfx12
    UINT64_C(3557687296), UINT64_C(0),	// V_CMP_NLT_F16_t16_e64_dpp8_gfx11
    UINT64_C(3557687296), UINT64_C(0),	// V_CMP_NLT_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077299511296), UINT64_C(0),	// V_CMP_NLT_F16_t16_e64_dpp_gfx11
    UINT64_C(1077299511296), UINT64_C(0),	// V_CMP_NLT_F16_t16_e64_dpp_gfx12
    UINT64_C(3557687296), UINT64_C(0),	// V_CMP_NLT_F16_t16_e64_gfx11
    UINT64_C(3557687296), UINT64_C(0),	// V_CMP_NLT_F16_t16_e64_gfx12
    UINT64_C(2084306944), UINT64_C(0),	// V_CMP_NLT_F32_e32_dpp8_gfx11
    UINT64_C(2084306944), UINT64_C(0),	// V_CMP_NLT_F32_e32_dpp8_gfx12
    UINT64_C(2084306944), UINT64_C(0),	// V_CMP_NLT_F32_e32_dpp8_w32_gfx11
    UINT64_C(2084306944), UINT64_C(0),	// V_CMP_NLT_F32_e32_dpp8_w32_gfx12
    UINT64_C(2084306944), UINT64_C(0),	// V_CMP_NLT_F32_e32_dpp8_w64_gfx11
    UINT64_C(2084306944), UINT64_C(0),	// V_CMP_NLT_F32_e32_dpp8_w64_gfx12
    UINT64_C(2084307194), UINT64_C(0),	// V_CMP_NLT_F32_e32_dpp_gfx11
    UINT64_C(2084307194), UINT64_C(0),	// V_CMP_NLT_F32_e32_dpp_gfx12
    UINT64_C(2084307194), UINT64_C(0),	// V_CMP_NLT_F32_e32_dpp_w32_gfx11
    UINT64_C(2084307194), UINT64_C(0),	// V_CMP_NLT_F32_e32_dpp_w32_gfx12
    UINT64_C(2084307194), UINT64_C(0),	// V_CMP_NLT_F32_e32_dpp_w64_gfx11
    UINT64_C(2084307194), UINT64_C(0),	// V_CMP_NLT_F32_e32_dpp_w64_gfx12
    UINT64_C(2082209792), UINT64_C(0),	// V_CMP_NLT_F32_e32_gfx10
    UINT64_C(2084306944), UINT64_C(0),	// V_CMP_NLT_F32_e32_gfx11
    UINT64_C(2084306944), UINT64_C(0),	// V_CMP_NLT_F32_e32_gfx12
    UINT64_C(2082209792), UINT64_C(0),	// V_CMP_NLT_F32_e32_gfx6_gfx7
    UINT64_C(2090598400), UINT64_C(0),	// V_CMP_NLT_F32_e32_vi
    UINT64_C(3558735872), UINT64_C(0),	// V_CMP_NLT_F32_e64_dpp8_gfx11
    UINT64_C(3558735872), UINT64_C(0),	// V_CMP_NLT_F32_e64_dpp8_gfx12
    UINT64_C(1077300559872), UINT64_C(0),	// V_CMP_NLT_F32_e64_dpp_gfx11
    UINT64_C(1077300559872), UINT64_C(0),	// V_CMP_NLT_F32_e64_dpp_gfx12
    UINT64_C(3557687296), UINT64_C(0),	// V_CMP_NLT_F32_e64_gfx10
    UINT64_C(3558735872), UINT64_C(0),	// V_CMP_NLT_F32_e64_gfx11
    UINT64_C(3558735872), UINT64_C(0),	// V_CMP_NLT_F32_e64_gfx12
    UINT64_C(3491495936), UINT64_C(0),	// V_CMP_NLT_F32_e64_gfx6_gfx7
    UINT64_C(3494772736), UINT64_C(0),	// V_CMP_NLT_F32_e64_vi
    UINT64_C(2082210041), UINT64_C(0),	// V_CMP_NLT_F32_sdwa_gfx10
    UINT64_C(2090598649), UINT64_C(0),	// V_CMP_NLT_F32_sdwa_gfx9
    UINT64_C(2090598649), UINT64_C(0),	// V_CMP_NLT_F32_sdwa_vi
    UINT64_C(2086404096), UINT64_C(0),	// V_CMP_NLT_F64_e32_gfx10
    UINT64_C(2086404096), UINT64_C(0),	// V_CMP_NLT_F64_e32_gfx11
    UINT64_C(2086404096), UINT64_C(0),	// V_CMP_NLT_F64_e32_gfx12
    UINT64_C(2086404096), UINT64_C(0),	// V_CMP_NLT_F64_e32_gfx6_gfx7
    UINT64_C(2094792704), UINT64_C(0),	// V_CMP_NLT_F64_e32_vi
    UINT64_C(3559784448), UINT64_C(0),	// V_CMP_NLT_F64_e64_gfx10
    UINT64_C(3559784448), UINT64_C(0),	// V_CMP_NLT_F64_e64_gfx11
    UINT64_C(3559784448), UINT64_C(0),	// V_CMP_NLT_F64_e64_gfx12
    UINT64_C(3495690240), UINT64_C(0),	// V_CMP_NLT_F64_e64_gfx6_gfx7
    UINT64_C(3496869888), UINT64_C(0),	// V_CMP_NLT_F64_e64_vi
    UINT64_C(2107506688), UINT64_C(0),	// V_CMP_O_F16_e32_gfx10
    UINT64_C(2085486592), UINT64_C(0),	// V_CMP_O_F16_e32_vi
    UINT64_C(3570335744), UINT64_C(0),	// V_CMP_O_F16_e64_gfx10
    UINT64_C(3492216832), UINT64_C(0),	// V_CMP_O_F16_e64_vi
    UINT64_C(2081292288), UINT64_C(0),	// V_CMP_O_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2081292288), UINT64_C(0),	// V_CMP_O_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2081292288), UINT64_C(0),	// V_CMP_O_F16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2081292288), UINT64_C(0),	// V_CMP_O_F16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2081292288), UINT64_C(0),	// V_CMP_O_F16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2081292288), UINT64_C(0),	// V_CMP_O_F16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2081292538), UINT64_C(0),	// V_CMP_O_F16_fake16_e32_dpp_gfx11
    UINT64_C(2081292538), UINT64_C(0),	// V_CMP_O_F16_fake16_e32_dpp_gfx12
    UINT64_C(2081292538), UINT64_C(0),	// V_CMP_O_F16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2081292538), UINT64_C(0),	// V_CMP_O_F16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2081292538), UINT64_C(0),	// V_CMP_O_F16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2081292538), UINT64_C(0),	// V_CMP_O_F16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2081292288), UINT64_C(0),	// V_CMP_O_F16_fake16_e32_gfx11
    UINT64_C(2081292288), UINT64_C(0),	// V_CMP_O_F16_fake16_e32_gfx12
    UINT64_C(3557228544), UINT64_C(0),	// V_CMP_O_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3557228544), UINT64_C(0),	// V_CMP_O_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077299052544), UINT64_C(0),	// V_CMP_O_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077299052544), UINT64_C(0),	// V_CMP_O_F16_fake16_e64_dpp_gfx12
    UINT64_C(3557228544), UINT64_C(0),	// V_CMP_O_F16_fake16_e64_gfx11
    UINT64_C(3557228544), UINT64_C(0),	// V_CMP_O_F16_fake16_e64_gfx12
    UINT64_C(2107506937), UINT64_C(0),	// V_CMP_O_F16_sdwa_gfx10
    UINT64_C(2085486841), UINT64_C(0),	// V_CMP_O_F16_sdwa_gfx9
    UINT64_C(2085486841), UINT64_C(0),	// V_CMP_O_F16_sdwa_vi
    UINT64_C(2081292288), UINT64_C(0),	// V_CMP_O_F16_t16_e32_dpp8_gfx11
    UINT64_C(2081292288), UINT64_C(0),	// V_CMP_O_F16_t16_e32_dpp8_gfx12
    UINT64_C(2081292288), UINT64_C(0),	// V_CMP_O_F16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2081292288), UINT64_C(0),	// V_CMP_O_F16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2081292288), UINT64_C(0),	// V_CMP_O_F16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2081292288), UINT64_C(0),	// V_CMP_O_F16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2081292538), UINT64_C(0),	// V_CMP_O_F16_t16_e32_dpp_gfx11
    UINT64_C(2081292538), UINT64_C(0),	// V_CMP_O_F16_t16_e32_dpp_gfx12
    UINT64_C(2081292538), UINT64_C(0),	// V_CMP_O_F16_t16_e32_dpp_w32_gfx11
    UINT64_C(2081292538), UINT64_C(0),	// V_CMP_O_F16_t16_e32_dpp_w32_gfx12
    UINT64_C(2081292538), UINT64_C(0),	// V_CMP_O_F16_t16_e32_dpp_w64_gfx11
    UINT64_C(2081292538), UINT64_C(0),	// V_CMP_O_F16_t16_e32_dpp_w64_gfx12
    UINT64_C(2081292288), UINT64_C(0),	// V_CMP_O_F16_t16_e32_gfx11
    UINT64_C(2081292288), UINT64_C(0),	// V_CMP_O_F16_t16_e32_gfx12
    UINT64_C(3557228544), UINT64_C(0),	// V_CMP_O_F16_t16_e64_dpp8_gfx11
    UINT64_C(3557228544), UINT64_C(0),	// V_CMP_O_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077299052544), UINT64_C(0),	// V_CMP_O_F16_t16_e64_dpp_gfx11
    UINT64_C(1077299052544), UINT64_C(0),	// V_CMP_O_F16_t16_e64_dpp_gfx12
    UINT64_C(3557228544), UINT64_C(0),	// V_CMP_O_F16_t16_e64_gfx11
    UINT64_C(3557228544), UINT64_C(0),	// V_CMP_O_F16_t16_e64_gfx12
    UINT64_C(2083389440), UINT64_C(0),	// V_CMP_O_F32_e32_dpp8_gfx11
    UINT64_C(2083389440), UINT64_C(0),	// V_CMP_O_F32_e32_dpp8_gfx12
    UINT64_C(2083389440), UINT64_C(0),	// V_CMP_O_F32_e32_dpp8_w32_gfx11
    UINT64_C(2083389440), UINT64_C(0),	// V_CMP_O_F32_e32_dpp8_w32_gfx12
    UINT64_C(2083389440), UINT64_C(0),	// V_CMP_O_F32_e32_dpp8_w64_gfx11
    UINT64_C(2083389440), UINT64_C(0),	// V_CMP_O_F32_e32_dpp8_w64_gfx12
    UINT64_C(2083389690), UINT64_C(0),	// V_CMP_O_F32_e32_dpp_gfx11
    UINT64_C(2083389690), UINT64_C(0),	// V_CMP_O_F32_e32_dpp_gfx12
    UINT64_C(2083389690), UINT64_C(0),	// V_CMP_O_F32_e32_dpp_w32_gfx11
    UINT64_C(2083389690), UINT64_C(0),	// V_CMP_O_F32_e32_dpp_w32_gfx12
    UINT64_C(2083389690), UINT64_C(0),	// V_CMP_O_F32_e32_dpp_w64_gfx11
    UINT64_C(2083389690), UINT64_C(0),	// V_CMP_O_F32_e32_dpp_w64_gfx12
    UINT64_C(2081292288), UINT64_C(0),	// V_CMP_O_F32_e32_gfx10
    UINT64_C(2083389440), UINT64_C(0),	// V_CMP_O_F32_e32_gfx11
    UINT64_C(2083389440), UINT64_C(0),	// V_CMP_O_F32_e32_gfx12
    UINT64_C(2081292288), UINT64_C(0),	// V_CMP_O_F32_e32_gfx6_gfx7
    UINT64_C(2089680896), UINT64_C(0),	// V_CMP_O_F32_e32_vi
    UINT64_C(3558277120), UINT64_C(0),	// V_CMP_O_F32_e64_dpp8_gfx11
    UINT64_C(3558277120), UINT64_C(0),	// V_CMP_O_F32_e64_dpp8_gfx12
    UINT64_C(1077300101120), UINT64_C(0),	// V_CMP_O_F32_e64_dpp_gfx11
    UINT64_C(1077300101120), UINT64_C(0),	// V_CMP_O_F32_e64_dpp_gfx12
    UINT64_C(3557228544), UINT64_C(0),	// V_CMP_O_F32_e64_gfx10
    UINT64_C(3558277120), UINT64_C(0),	// V_CMP_O_F32_e64_gfx11
    UINT64_C(3558277120), UINT64_C(0),	// V_CMP_O_F32_e64_gfx12
    UINT64_C(3490578432), UINT64_C(0),	// V_CMP_O_F32_e64_gfx6_gfx7
    UINT64_C(3494313984), UINT64_C(0),	// V_CMP_O_F32_e64_vi
    UINT64_C(2081292537), UINT64_C(0),	// V_CMP_O_F32_sdwa_gfx10
    UINT64_C(2089681145), UINT64_C(0),	// V_CMP_O_F32_sdwa_gfx9
    UINT64_C(2089681145), UINT64_C(0),	// V_CMP_O_F32_sdwa_vi
    UINT64_C(2085486592), UINT64_C(0),	// V_CMP_O_F64_e32_gfx10
    UINT64_C(2085486592), UINT64_C(0),	// V_CMP_O_F64_e32_gfx11
    UINT64_C(2085486592), UINT64_C(0),	// V_CMP_O_F64_e32_gfx12
    UINT64_C(2085486592), UINT64_C(0),	// V_CMP_O_F64_e32_gfx6_gfx7
    UINT64_C(2093875200), UINT64_C(0),	// V_CMP_O_F64_e32_vi
    UINT64_C(3559325696), UINT64_C(0),	// V_CMP_O_F64_e64_gfx10
    UINT64_C(3559325696), UINT64_C(0),	// V_CMP_O_F64_e64_gfx11
    UINT64_C(3559325696), UINT64_C(0),	// V_CMP_O_F64_e64_gfx12
    UINT64_C(3494772736), UINT64_C(0),	// V_CMP_O_F64_e64_gfx6_gfx7
    UINT64_C(3496411136), UINT64_C(0),	// V_CMP_O_F64_e64_vi
    UINT64_C(2111700992), UINT64_C(0),	// V_CMP_TRU_F16_e32_gfx10
    UINT64_C(2086535168), UINT64_C(0),	// V_CMP_TRU_F16_e32_vi
    UINT64_C(3572432896), UINT64_C(0),	// V_CMP_TRU_F16_e64_gfx10
    UINT64_C(3492741120), UINT64_C(0),	// V_CMP_TRU_F16_e64_vi
    UINT64_C(2111701241), UINT64_C(0),	// V_CMP_TRU_F16_sdwa_gfx10
    UINT64_C(2086535417), UINT64_C(0),	// V_CMP_TRU_F16_sdwa_gfx9
    UINT64_C(2086535417), UINT64_C(0),	// V_CMP_TRU_F16_sdwa_vi
    UINT64_C(2082340864), UINT64_C(0),	// V_CMP_TRU_F32_e32_gfx10
    UINT64_C(2082340864), UINT64_C(0),	// V_CMP_TRU_F32_e32_gfx6_gfx7
    UINT64_C(2090729472), UINT64_C(0),	// V_CMP_TRU_F32_e32_vi
    UINT64_C(3557752832), UINT64_C(0),	// V_CMP_TRU_F32_e64_gfx10
    UINT64_C(3491627008), UINT64_C(0),	// V_CMP_TRU_F32_e64_gfx6_gfx7
    UINT64_C(3494838272), UINT64_C(0),	// V_CMP_TRU_F32_e64_vi
    UINT64_C(2082341113), UINT64_C(0),	// V_CMP_TRU_F32_sdwa_gfx10
    UINT64_C(2090729721), UINT64_C(0),	// V_CMP_TRU_F32_sdwa_gfx9
    UINT64_C(2090729721), UINT64_C(0),	// V_CMP_TRU_F32_sdwa_vi
    UINT64_C(2086535168), UINT64_C(0),	// V_CMP_TRU_F64_e32_gfx10
    UINT64_C(2086535168), UINT64_C(0),	// V_CMP_TRU_F64_e32_gfx6_gfx7
    UINT64_C(2094923776), UINT64_C(0),	// V_CMP_TRU_F64_e32_vi
    UINT64_C(3559849984), UINT64_C(0),	// V_CMP_TRU_F64_e64_gfx10
    UINT64_C(3495821312), UINT64_C(0),	// V_CMP_TRU_F64_e64_gfx6_gfx7
    UINT64_C(3496935424), UINT64_C(0),	// V_CMP_TRU_F64_e64_vi
    UINT64_C(2082340864), UINT64_C(0),	// V_CMP_T_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2082340864), UINT64_C(0),	// V_CMP_T_F16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2082340864), UINT64_C(0),	// V_CMP_T_F16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2082341114), UINT64_C(0),	// V_CMP_T_F16_fake16_e32_dpp_gfx11
    UINT64_C(2082341114), UINT64_C(0),	// V_CMP_T_F16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2082341114), UINT64_C(0),	// V_CMP_T_F16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2082340864), UINT64_C(0),	// V_CMP_T_F16_fake16_e32_gfx11
    UINT64_C(3557752832), UINT64_C(0),	// V_CMP_T_F16_fake16_e64_dpp8_gfx11
    UINT64_C(1077299576832), UINT64_C(0),	// V_CMP_T_F16_fake16_e64_dpp_gfx11
    UINT64_C(3557752832), UINT64_C(0),	// V_CMP_T_F16_fake16_e64_gfx11
    UINT64_C(2082340864), UINT64_C(0),	// V_CMP_T_F16_t16_e32_dpp8_gfx11
    UINT64_C(2082340864), UINT64_C(0),	// V_CMP_T_F16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2082340864), UINT64_C(0),	// V_CMP_T_F16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2082341114), UINT64_C(0),	// V_CMP_T_F16_t16_e32_dpp_gfx11
    UINT64_C(2082341114), UINT64_C(0),	// V_CMP_T_F16_t16_e32_dpp_w32_gfx11
    UINT64_C(2082341114), UINT64_C(0),	// V_CMP_T_F16_t16_e32_dpp_w64_gfx11
    UINT64_C(2082340864), UINT64_C(0),	// V_CMP_T_F16_t16_e32_gfx11
    UINT64_C(3557752832), UINT64_C(0),	// V_CMP_T_F16_t16_e64_dpp8_gfx11
    UINT64_C(1077299576832), UINT64_C(0),	// V_CMP_T_F16_t16_e64_dpp_gfx11
    UINT64_C(3557752832), UINT64_C(0),	// V_CMP_T_F16_t16_e64_gfx11
    UINT64_C(2084438016), UINT64_C(0),	// V_CMP_T_F32_e32_dpp8_gfx11
    UINT64_C(2084438016), UINT64_C(0),	// V_CMP_T_F32_e32_dpp8_w32_gfx11
    UINT64_C(2084438016), UINT64_C(0),	// V_CMP_T_F32_e32_dpp8_w64_gfx11
    UINT64_C(2084438266), UINT64_C(0),	// V_CMP_T_F32_e32_dpp_gfx11
    UINT64_C(2084438266), UINT64_C(0),	// V_CMP_T_F32_e32_dpp_w32_gfx11
    UINT64_C(2084438266), UINT64_C(0),	// V_CMP_T_F32_e32_dpp_w64_gfx11
    UINT64_C(2084438016), UINT64_C(0),	// V_CMP_T_F32_e32_gfx11
    UINT64_C(3558801408), UINT64_C(0),	// V_CMP_T_F32_e64_dpp8_gfx11
    UINT64_C(1077300625408), UINT64_C(0),	// V_CMP_T_F32_e64_dpp_gfx11
    UINT64_C(3558801408), UINT64_C(0),	// V_CMP_T_F32_e64_gfx11
    UINT64_C(2086535168), UINT64_C(0),	// V_CMP_T_F64_e32_gfx11
    UINT64_C(3559849984), UINT64_C(0),	// V_CMP_T_F64_e64_gfx11
    UINT64_C(2102263808), UINT64_C(0),	// V_CMP_T_I16_e32_vi
    UINT64_C(3500605440), UINT64_C(0),	// V_CMP_T_I16_e64_vi
    UINT64_C(2102264057), UINT64_C(0),	// V_CMP_T_I16_sdwa_gfx9
    UINT64_C(2102264057), UINT64_C(0),	// V_CMP_T_I16_sdwa_vi
    UINT64_C(2089680896), UINT64_C(0),	// V_CMP_T_I32_e32_dpp8_gfx11
    UINT64_C(2089680896), UINT64_C(0),	// V_CMP_T_I32_e32_dpp8_w32_gfx11
    UINT64_C(2089680896), UINT64_C(0),	// V_CMP_T_I32_e32_dpp8_w64_gfx11
    UINT64_C(2089681146), UINT64_C(0),	// V_CMP_T_I32_e32_dpp_gfx11
    UINT64_C(2089681146), UINT64_C(0),	// V_CMP_T_I32_e32_dpp_w32_gfx11
    UINT64_C(2089681146), UINT64_C(0),	// V_CMP_T_I32_e32_dpp_w64_gfx11
    UINT64_C(2098069504), UINT64_C(0),	// V_CMP_T_I32_e32_gfx10
    UINT64_C(2089680896), UINT64_C(0),	// V_CMP_T_I32_e32_gfx11
    UINT64_C(2098069504), UINT64_C(0),	// V_CMP_T_I32_e32_gfx6_gfx7
    UINT64_C(2106458112), UINT64_C(0),	// V_CMP_T_I32_e32_vi
    UINT64_C(3561422848), UINT64_C(0),	// V_CMP_T_I32_e64_dpp8_gfx11
    UINT64_C(1077303246848), UINT64_C(0),	// V_CMP_T_I32_e64_dpp_gfx11
    UINT64_C(3565617152), UINT64_C(0),	// V_CMP_T_I32_e64_gfx10
    UINT64_C(3561422848), UINT64_C(0),	// V_CMP_T_I32_e64_gfx11
    UINT64_C(3507355648), UINT64_C(0),	// V_CMP_T_I32_e64_gfx6_gfx7
    UINT64_C(3502702592), UINT64_C(0),	// V_CMP_T_I32_e64_vi
    UINT64_C(2098069753), UINT64_C(0),	// V_CMP_T_I32_sdwa_gfx10
    UINT64_C(2106458361), UINT64_C(0),	// V_CMP_T_I32_sdwa_gfx9
    UINT64_C(2106458361), UINT64_C(0),	// V_CMP_T_I32_sdwa_vi
    UINT64_C(2102263808), UINT64_C(0),	// V_CMP_T_I64_e32_gfx10
    UINT64_C(2091778048), UINT64_C(0),	// V_CMP_T_I64_e32_gfx11
    UINT64_C(2102263808), UINT64_C(0),	// V_CMP_T_I64_e32_gfx6_gfx7
    UINT64_C(2110652416), UINT64_C(0),	// V_CMP_T_I64_e32_vi
    UINT64_C(3567714304), UINT64_C(0),	// V_CMP_T_I64_e64_gfx10
    UINT64_C(3562471424), UINT64_C(0),	// V_CMP_T_I64_e64_gfx11
    UINT64_C(3511549952), UINT64_C(0),	// V_CMP_T_I64_e64_gfx6_gfx7
    UINT64_C(3504799744), UINT64_C(0),	// V_CMP_T_I64_e64_vi
    UINT64_C(2103312384), UINT64_C(0),	// V_CMP_T_U16_e32_vi
    UINT64_C(3501129728), UINT64_C(0),	// V_CMP_T_U16_e64_vi
    UINT64_C(2103312633), UINT64_C(0),	// V_CMP_T_U16_sdwa_gfx9
    UINT64_C(2103312633), UINT64_C(0),	// V_CMP_T_U16_sdwa_vi
    UINT64_C(2090729472), UINT64_C(0),	// V_CMP_T_U32_e32_dpp8_gfx11
    UINT64_C(2090729472), UINT64_C(0),	// V_CMP_T_U32_e32_dpp8_w32_gfx11
    UINT64_C(2090729472), UINT64_C(0),	// V_CMP_T_U32_e32_dpp8_w64_gfx11
    UINT64_C(2090729722), UINT64_C(0),	// V_CMP_T_U32_e32_dpp_gfx11
    UINT64_C(2090729722), UINT64_C(0),	// V_CMP_T_U32_e32_dpp_w32_gfx11
    UINT64_C(2090729722), UINT64_C(0),	// V_CMP_T_U32_e32_dpp_w64_gfx11
    UINT64_C(2106458112), UINT64_C(0),	// V_CMP_T_U32_e32_gfx10
    UINT64_C(2090729472), UINT64_C(0),	// V_CMP_T_U32_e32_gfx11
    UINT64_C(2106458112), UINT64_C(0),	// V_CMP_T_U32_e32_gfx6_gfx7
    UINT64_C(2107506688), UINT64_C(0),	// V_CMP_T_U32_e32_vi
    UINT64_C(3561947136), UINT64_C(0),	// V_CMP_T_U32_e64_dpp8_gfx11
    UINT64_C(1077303771136), UINT64_C(0),	// V_CMP_T_U32_e64_dpp_gfx11
    UINT64_C(3569811456), UINT64_C(0),	// V_CMP_T_U32_e64_gfx10
    UINT64_C(3561947136), UINT64_C(0),	// V_CMP_T_U32_e64_gfx11
    UINT64_C(3515744256), UINT64_C(0),	// V_CMP_T_U32_e64_gfx6_gfx7
    UINT64_C(3503226880), UINT64_C(0),	// V_CMP_T_U32_e64_vi
    UINT64_C(2106458361), UINT64_C(0),	// V_CMP_T_U32_sdwa_gfx10
    UINT64_C(2107506937), UINT64_C(0),	// V_CMP_T_U32_sdwa_gfx9
    UINT64_C(2107506937), UINT64_C(0),	// V_CMP_T_U32_sdwa_vi
    UINT64_C(2110652416), UINT64_C(0),	// V_CMP_T_U64_e32_gfx10
    UINT64_C(2092826624), UINT64_C(0),	// V_CMP_T_U64_e32_gfx11
    UINT64_C(2110652416), UINT64_C(0),	// V_CMP_T_U64_e32_gfx6_gfx7
    UINT64_C(2111700992), UINT64_C(0),	// V_CMP_T_U64_e32_vi
    UINT64_C(3571908608), UINT64_C(0),	// V_CMP_T_U64_e64_gfx10
    UINT64_C(3562995712), UINT64_C(0),	// V_CMP_T_U64_e64_gfx11
    UINT64_C(3519938560), UINT64_C(0),	// V_CMP_T_U64_e64_gfx6_gfx7
    UINT64_C(3505324032), UINT64_C(0),	// V_CMP_T_U64_e64_vi
    UINT64_C(2110783488), UINT64_C(0),	// V_CMP_U_F16_e32_gfx10
    UINT64_C(2085617664), UINT64_C(0),	// V_CMP_U_F16_e32_vi
    UINT64_C(3571974144), UINT64_C(0),	// V_CMP_U_F16_e64_gfx10
    UINT64_C(3492282368), UINT64_C(0),	// V_CMP_U_F16_e64_vi
    UINT64_C(2081423360), UINT64_C(0),	// V_CMP_U_F16_fake16_e32_dpp8_gfx11
    UINT64_C(2081423360), UINT64_C(0),	// V_CMP_U_F16_fake16_e32_dpp8_gfx12
    UINT64_C(2081423360), UINT64_C(0),	// V_CMP_U_F16_fake16_e32_dpp8_w32_gfx11
    UINT64_C(2081423360), UINT64_C(0),	// V_CMP_U_F16_fake16_e32_dpp8_w32_gfx12
    UINT64_C(2081423360), UINT64_C(0),	// V_CMP_U_F16_fake16_e32_dpp8_w64_gfx11
    UINT64_C(2081423360), UINT64_C(0),	// V_CMP_U_F16_fake16_e32_dpp8_w64_gfx12
    UINT64_C(2081423610), UINT64_C(0),	// V_CMP_U_F16_fake16_e32_dpp_gfx11
    UINT64_C(2081423610), UINT64_C(0),	// V_CMP_U_F16_fake16_e32_dpp_gfx12
    UINT64_C(2081423610), UINT64_C(0),	// V_CMP_U_F16_fake16_e32_dpp_w32_gfx11
    UINT64_C(2081423610), UINT64_C(0),	// V_CMP_U_F16_fake16_e32_dpp_w32_gfx12
    UINT64_C(2081423610), UINT64_C(0),	// V_CMP_U_F16_fake16_e32_dpp_w64_gfx11
    UINT64_C(2081423610), UINT64_C(0),	// V_CMP_U_F16_fake16_e32_dpp_w64_gfx12
    UINT64_C(2081423360), UINT64_C(0),	// V_CMP_U_F16_fake16_e32_gfx11
    UINT64_C(2081423360), UINT64_C(0),	// V_CMP_U_F16_fake16_e32_gfx12
    UINT64_C(3557294080), UINT64_C(0),	// V_CMP_U_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3557294080), UINT64_C(0),	// V_CMP_U_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077299118080), UINT64_C(0),	// V_CMP_U_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077299118080), UINT64_C(0),	// V_CMP_U_F16_fake16_e64_dpp_gfx12
    UINT64_C(3557294080), UINT64_C(0),	// V_CMP_U_F16_fake16_e64_gfx11
    UINT64_C(3557294080), UINT64_C(0),	// V_CMP_U_F16_fake16_e64_gfx12
    UINT64_C(2110783737), UINT64_C(0),	// V_CMP_U_F16_sdwa_gfx10
    UINT64_C(2085617913), UINT64_C(0),	// V_CMP_U_F16_sdwa_gfx9
    UINT64_C(2085617913), UINT64_C(0),	// V_CMP_U_F16_sdwa_vi
    UINT64_C(2081423360), UINT64_C(0),	// V_CMP_U_F16_t16_e32_dpp8_gfx11
    UINT64_C(2081423360), UINT64_C(0),	// V_CMP_U_F16_t16_e32_dpp8_gfx12
    UINT64_C(2081423360), UINT64_C(0),	// V_CMP_U_F16_t16_e32_dpp8_w32_gfx11
    UINT64_C(2081423360), UINT64_C(0),	// V_CMP_U_F16_t16_e32_dpp8_w32_gfx12
    UINT64_C(2081423360), UINT64_C(0),	// V_CMP_U_F16_t16_e32_dpp8_w64_gfx11
    UINT64_C(2081423360), UINT64_C(0),	// V_CMP_U_F16_t16_e32_dpp8_w64_gfx12
    UINT64_C(2081423610), UINT64_C(0),	// V_CMP_U_F16_t16_e32_dpp_gfx11
    UINT64_C(2081423610), UINT64_C(0),	// V_CMP_U_F16_t16_e32_dpp_gfx12
    UINT64_C(2081423610), UINT64_C(0),	// V_CMP_U_F16_t16_e32_dpp_w32_gfx11
    UINT64_C(2081423610), UINT64_C(0),	// V_CMP_U_F16_t16_e32_dpp_w32_gfx12
    UINT64_C(2081423610), UINT64_C(0),	// V_CMP_U_F16_t16_e32_dpp_w64_gfx11
    UINT64_C(2081423610), UINT64_C(0),	// V_CMP_U_F16_t16_e32_dpp_w64_gfx12
    UINT64_C(2081423360), UINT64_C(0),	// V_CMP_U_F16_t16_e32_gfx11
    UINT64_C(2081423360), UINT64_C(0),	// V_CMP_U_F16_t16_e32_gfx12
    UINT64_C(3557294080), UINT64_C(0),	// V_CMP_U_F16_t16_e64_dpp8_gfx11
    UINT64_C(3557294080), UINT64_C(0),	// V_CMP_U_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077299118080), UINT64_C(0),	// V_CMP_U_F16_t16_e64_dpp_gfx11
    UINT64_C(1077299118080), UINT64_C(0),	// V_CMP_U_F16_t16_e64_dpp_gfx12
    UINT64_C(3557294080), UINT64_C(0),	// V_CMP_U_F16_t16_e64_gfx11
    UINT64_C(3557294080), UINT64_C(0),	// V_CMP_U_F16_t16_e64_gfx12
    UINT64_C(2083520512), UINT64_C(0),	// V_CMP_U_F32_e32_dpp8_gfx11
    UINT64_C(2083520512), UINT64_C(0),	// V_CMP_U_F32_e32_dpp8_gfx12
    UINT64_C(2083520512), UINT64_C(0),	// V_CMP_U_F32_e32_dpp8_w32_gfx11
    UINT64_C(2083520512), UINT64_C(0),	// V_CMP_U_F32_e32_dpp8_w32_gfx12
    UINT64_C(2083520512), UINT64_C(0),	// V_CMP_U_F32_e32_dpp8_w64_gfx11
    UINT64_C(2083520512), UINT64_C(0),	// V_CMP_U_F32_e32_dpp8_w64_gfx12
    UINT64_C(2083520762), UINT64_C(0),	// V_CMP_U_F32_e32_dpp_gfx11
    UINT64_C(2083520762), UINT64_C(0),	// V_CMP_U_F32_e32_dpp_gfx12
    UINT64_C(2083520762), UINT64_C(0),	// V_CMP_U_F32_e32_dpp_w32_gfx11
    UINT64_C(2083520762), UINT64_C(0),	// V_CMP_U_F32_e32_dpp_w32_gfx12
    UINT64_C(2083520762), UINT64_C(0),	// V_CMP_U_F32_e32_dpp_w64_gfx11
    UINT64_C(2083520762), UINT64_C(0),	// V_CMP_U_F32_e32_dpp_w64_gfx12
    UINT64_C(2081423360), UINT64_C(0),	// V_CMP_U_F32_e32_gfx10
    UINT64_C(2083520512), UINT64_C(0),	// V_CMP_U_F32_e32_gfx11
    UINT64_C(2083520512), UINT64_C(0),	// V_CMP_U_F32_e32_gfx12
    UINT64_C(2081423360), UINT64_C(0),	// V_CMP_U_F32_e32_gfx6_gfx7
    UINT64_C(2089811968), UINT64_C(0),	// V_CMP_U_F32_e32_vi
    UINT64_C(3558342656), UINT64_C(0),	// V_CMP_U_F32_e64_dpp8_gfx11
    UINT64_C(3558342656), UINT64_C(0),	// V_CMP_U_F32_e64_dpp8_gfx12
    UINT64_C(1077300166656), UINT64_C(0),	// V_CMP_U_F32_e64_dpp_gfx11
    UINT64_C(1077300166656), UINT64_C(0),	// V_CMP_U_F32_e64_dpp_gfx12
    UINT64_C(3557294080), UINT64_C(0),	// V_CMP_U_F32_e64_gfx10
    UINT64_C(3558342656), UINT64_C(0),	// V_CMP_U_F32_e64_gfx11
    UINT64_C(3558342656), UINT64_C(0),	// V_CMP_U_F32_e64_gfx12
    UINT64_C(3490709504), UINT64_C(0),	// V_CMP_U_F32_e64_gfx6_gfx7
    UINT64_C(3494379520), UINT64_C(0),	// V_CMP_U_F32_e64_vi
    UINT64_C(2081423609), UINT64_C(0),	// V_CMP_U_F32_sdwa_gfx10
    UINT64_C(2089812217), UINT64_C(0),	// V_CMP_U_F32_sdwa_gfx9
    UINT64_C(2089812217), UINT64_C(0),	// V_CMP_U_F32_sdwa_vi
    UINT64_C(2085617664), UINT64_C(0),	// V_CMP_U_F64_e32_gfx10
    UINT64_C(2085617664), UINT64_C(0),	// V_CMP_U_F64_e32_gfx11
    UINT64_C(2085617664), UINT64_C(0),	// V_CMP_U_F64_e32_gfx12
    UINT64_C(2085617664), UINT64_C(0),	// V_CMP_U_F64_e32_gfx6_gfx7
    UINT64_C(2094006272), UINT64_C(0),	// V_CMP_U_F64_e32_vi
    UINT64_C(3559391232), UINT64_C(0),	// V_CMP_U_F64_e64_gfx10
    UINT64_C(3559391232), UINT64_C(0),	// V_CMP_U_F64_e64_gfx11
    UINT64_C(3559391232), UINT64_C(0),	// V_CMP_U_F64_e64_gfx12
    UINT64_C(3494903808), UINT64_C(0),	// V_CMP_U_F64_e64_gfx6_gfx7
    UINT64_C(3496476672), UINT64_C(0),	// V_CMP_U_F64_e64_vi
    UINT64_C(3596419072), UINT64_C(0),	// V_CNDMASK_B16_fake16_e64_dpp8_gfx11
    UINT64_C(3596419072), UINT64_C(0),	// V_CNDMASK_B16_fake16_e64_dpp8_gfx12
    UINT64_C(1077338243072), UINT64_C(0),	// V_CNDMASK_B16_fake16_e64_dpp_gfx11
    UINT64_C(1077338243072), UINT64_C(0),	// V_CNDMASK_B16_fake16_e64_dpp_gfx12
    UINT64_C(3596419072), UINT64_C(0),	// V_CNDMASK_B16_fake16_e64_gfx11
    UINT64_C(3596419072), UINT64_C(0),	// V_CNDMASK_B16_fake16_e64_gfx12
    UINT64_C(3596419072), UINT64_C(0),	// V_CNDMASK_B16_t16_e64_dpp8_gfx11
    UINT64_C(3596419072), UINT64_C(0),	// V_CNDMASK_B16_t16_e64_dpp8_gfx12
    UINT64_C(1077338243072), UINT64_C(0),	// V_CNDMASK_B16_t16_e64_dpp_gfx11
    UINT64_C(1077338243072), UINT64_C(0),	// V_CNDMASK_B16_t16_e64_dpp_gfx12
    UINT64_C(3596419072), UINT64_C(0),	// V_CNDMASK_B16_t16_e64_gfx11
    UINT64_C(3596419072), UINT64_C(0),	// V_CNDMASK_B16_t16_e64_gfx12
    UINT64_C(33554432), UINT64_C(0),	// V_CNDMASK_B32_dpp8_gfx10
    UINT64_C(33554432), UINT64_C(0),	// V_CNDMASK_B32_dpp8_gfx11
    UINT64_C(33554432), UINT64_C(0),	// V_CNDMASK_B32_dpp8_gfx12
    UINT64_C(33554432), UINT64_C(0),	// V_CNDMASK_B32_dpp8_w32_gfx10
    UINT64_C(33554432), UINT64_C(0),	// V_CNDMASK_B32_dpp8_w32_gfx11
    UINT64_C(33554432), UINT64_C(0),	// V_CNDMASK_B32_dpp8_w32_gfx12
    UINT64_C(33554432), UINT64_C(0),	// V_CNDMASK_B32_dpp8_w64_gfx10
    UINT64_C(33554432), UINT64_C(0),	// V_CNDMASK_B32_dpp8_w64_gfx11
    UINT64_C(33554432), UINT64_C(0),	// V_CNDMASK_B32_dpp8_w64_gfx12
    UINT64_C(33554682), UINT64_C(0),	// V_CNDMASK_B32_dpp_gfx10
    UINT64_C(33554682), UINT64_C(0),	// V_CNDMASK_B32_dpp_gfx11
    UINT64_C(33554682), UINT64_C(0),	// V_CNDMASK_B32_dpp_gfx12
    UINT64_C(250), UINT64_C(0),	// V_CNDMASK_B32_dpp_vi
    UINT64_C(33554682), UINT64_C(0),	// V_CNDMASK_B32_dpp_w32_gfx10
    UINT64_C(33554682), UINT64_C(0),	// V_CNDMASK_B32_dpp_w32_gfx11
    UINT64_C(33554682), UINT64_C(0),	// V_CNDMASK_B32_dpp_w32_gfx12
    UINT64_C(33554682), UINT64_C(0),	// V_CNDMASK_B32_dpp_w64_gfx10
    UINT64_C(33554682), UINT64_C(0),	// V_CNDMASK_B32_dpp_w64_gfx11
    UINT64_C(33554682), UINT64_C(0),	// V_CNDMASK_B32_dpp_w64_gfx12
    UINT64_C(33554432), UINT64_C(0),	// V_CNDMASK_B32_e32_gfx10
    UINT64_C(33554432), UINT64_C(0),	// V_CNDMASK_B32_e32_gfx11
    UINT64_C(33554432), UINT64_C(0),	// V_CNDMASK_B32_e32_gfx12
    UINT64_C(0), UINT64_C(0),	// V_CNDMASK_B32_e32_gfx6_gfx7
    UINT64_C(0), UINT64_C(0),	// V_CNDMASK_B32_e32_vi
    UINT64_C(3573612544), UINT64_C(0),	// V_CNDMASK_B32_e64_dpp8_gfx11
    UINT64_C(3573612544), UINT64_C(0),	// V_CNDMASK_B32_e64_dpp8_gfx12
    UINT64_C(1077315436544), UINT64_C(0),	// V_CNDMASK_B32_e64_dpp_gfx11
    UINT64_C(1077315436544), UINT64_C(0),	// V_CNDMASK_B32_e64_dpp_gfx12
    UINT64_C(3573612544), UINT64_C(0),	// V_CNDMASK_B32_e64_gfx10
    UINT64_C(3573612544), UINT64_C(0),	// V_CNDMASK_B32_e64_gfx11
    UINT64_C(3573612544), UINT64_C(0),	// V_CNDMASK_B32_e64_gfx12
    UINT64_C(3523215360), UINT64_C(0),	// V_CNDMASK_B32_e64_gfx6_gfx7
    UINT64_C(3506438144), UINT64_C(0),	// V_CNDMASK_B32_e64_vi
    UINT64_C(33554681), UINT64_C(0),	// V_CNDMASK_B32_sdwa_gfx10
    UINT64_C(249), UINT64_C(0),	// V_CNDMASK_B32_sdwa_gfx9
    UINT64_C(249), UINT64_C(0),	// V_CNDMASK_B32_sdwa_vi
    UINT64_C(33554681), UINT64_C(0),	// V_CNDMASK_B32_sdwa_w32_gfx10
    UINT64_C(33554681), UINT64_C(0),	// V_CNDMASK_B32_sdwa_w64_gfx10
    UINT64_C(2113994240), UINT64_C(0),	// V_COS_BF16V_COS_BF16_fake16_dpp8_gfx1250
    UINT64_C(2113994490), UINT64_C(0),	// V_COS_BF16V_COS_BF16_fake16_dpp_gfx1250
    UINT64_C(2113994240), UINT64_C(0),	// V_COS_BF16V_COS_BF16_fake16_e32_gfx1250
    UINT64_C(3590258688), UINT64_C(0),	// V_COS_BF16V_COS_BF16_fake16_e64_dpp8_gfx1250
    UINT64_C(1077332082688), UINT64_C(0),	// V_COS_BF16V_COS_BF16_fake16_e64_dpp_gfx1250
    UINT64_C(3590258688), UINT64_C(0),	// V_COS_BF16V_COS_BF16_fake16_e64_gfx1250
    UINT64_C(2113994240), UINT64_C(0),	// V_COS_BF16V_COS_BF16_t16_dpp8_gfx1250
    UINT64_C(2113994490), UINT64_C(0),	// V_COS_BF16V_COS_BF16_t16_dpp_gfx1250
    UINT64_C(2113994240), UINT64_C(0),	// V_COS_BF16V_COS_BF16_t16_e32_gfx1250
    UINT64_C(3590258688), UINT64_C(0),	// V_COS_BF16V_COS_BF16_t16_e64_dpp8_gfx1250
    UINT64_C(1077332082688), UINT64_C(0),	// V_COS_BF16V_COS_BF16_t16_e64_dpp_gfx1250
    UINT64_C(3590258688), UINT64_C(0),	// V_COS_BF16V_COS_BF16_t16_e64_gfx1250
    UINT64_C(2113978880), UINT64_C(0),	// V_COS_F16V_COS_F16_fake16_dpp8_gfx11
    UINT64_C(2113978880), UINT64_C(0),	// V_COS_F16V_COS_F16_fake16_dpp8_gfx12
    UINT64_C(2113979130), UINT64_C(0),	// V_COS_F16V_COS_F16_fake16_dpp_gfx11
    UINT64_C(2113979130), UINT64_C(0),	// V_COS_F16V_COS_F16_fake16_dpp_gfx12
    UINT64_C(2113978880), UINT64_C(0),	// V_COS_F16V_COS_F16_fake16_e32_gfx11
    UINT64_C(2113978880), UINT64_C(0),	// V_COS_F16V_COS_F16_fake16_e32_gfx12
    UINT64_C(3588292608), UINT64_C(0),	// V_COS_F16V_COS_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3588292608), UINT64_C(0),	// V_COS_F16V_COS_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077330116608), UINT64_C(0),	// V_COS_F16V_COS_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077330116608), UINT64_C(0),	// V_COS_F16V_COS_F16_fake16_e64_dpp_gfx12
    UINT64_C(3588292608), UINT64_C(0),	// V_COS_F16V_COS_F16_fake16_e64_gfx11
    UINT64_C(3588292608), UINT64_C(0),	// V_COS_F16V_COS_F16_fake16_e64_gfx12
    UINT64_C(2113978880), UINT64_C(0),	// V_COS_F16V_COS_F16_t16_dpp8_gfx11
    UINT64_C(2113978880), UINT64_C(0),	// V_COS_F16V_COS_F16_t16_dpp8_gfx12
    UINT64_C(2113979130), UINT64_C(0),	// V_COS_F16V_COS_F16_t16_dpp_gfx11
    UINT64_C(2113979130), UINT64_C(0),	// V_COS_F16V_COS_F16_t16_dpp_gfx12
    UINT64_C(2113978880), UINT64_C(0),	// V_COS_F16V_COS_F16_t16_e32_gfx11
    UINT64_C(2113978880), UINT64_C(0),	// V_COS_F16V_COS_F16_t16_e32_gfx12
    UINT64_C(3588292608), UINT64_C(0),	// V_COS_F16V_COS_F16_t16_e64_dpp8_gfx11
    UINT64_C(3588292608), UINT64_C(0),	// V_COS_F16V_COS_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077330116608), UINT64_C(0),	// V_COS_F16V_COS_F16_t16_e64_dpp_gfx11
    UINT64_C(1077330116608), UINT64_C(0),	// V_COS_F16V_COS_F16_t16_e64_dpp_gfx12
    UINT64_C(3588292608), UINT64_C(0),	// V_COS_F16V_COS_F16_t16_e64_gfx11
    UINT64_C(3588292608), UINT64_C(0),	// V_COS_F16V_COS_F16_t16_e64_gfx12
    UINT64_C(2113978880), UINT64_C(0),	// V_COS_F16_dpp8_gfx10
    UINT64_C(2113979130), UINT64_C(0),	// V_COS_F16_dpp_gfx10
    UINT64_C(2113967354), UINT64_C(0),	// V_COS_F16_dpp_vi
    UINT64_C(2113978880), UINT64_C(0),	// V_COS_F16_e32_gfx10
    UINT64_C(2113967104), UINT64_C(0),	// V_COS_F16_e32_vi
    UINT64_C(3588292608), UINT64_C(0),	// V_COS_F16_e64_gfx10
    UINT64_C(3515482112), UINT64_C(0),	// V_COS_F16_e64_vi
    UINT64_C(2113979129), UINT64_C(0),	// V_COS_F16_sdwa_gfx10
    UINT64_C(2113967353), UINT64_C(0),	// V_COS_F16_sdwa_gfx9
    UINT64_C(2113967353), UINT64_C(0),	// V_COS_F16_sdwa_vi
    UINT64_C(2113956864), UINT64_C(0),	// V_COS_F32_dpp8_gfx10
    UINT64_C(2113956864), UINT64_C(0),	// V_COS_F32_dpp8_gfx11
    UINT64_C(2113956864), UINT64_C(0),	// V_COS_F32_dpp8_gfx12
    UINT64_C(2113957114), UINT64_C(0),	// V_COS_F32_dpp_gfx10
    UINT64_C(2113957114), UINT64_C(0),	// V_COS_F32_dpp_gfx11
    UINT64_C(2113957114), UINT64_C(0),	// V_COS_F32_dpp_gfx12
    UINT64_C(2113950970), UINT64_C(0),	// V_COS_F32_dpp_vi
    UINT64_C(2113956864), UINT64_C(0),	// V_COS_F32_e32_gfx10
    UINT64_C(2113956864), UINT64_C(0),	// V_COS_F32_e32_gfx11
    UINT64_C(2113956864), UINT64_C(0),	// V_COS_F32_e32_gfx12
    UINT64_C(2113956864), UINT64_C(0),	// V_COS_F32_e32_gfx6_gfx7
    UINT64_C(2113950720), UINT64_C(0),	// V_COS_F32_e32_vi
    UINT64_C(3585474560), UINT64_C(0),	// V_COS_F32_e64_dpp8_gfx11
    UINT64_C(3585474560), UINT64_C(0),	// V_COS_F32_e64_dpp8_gfx12
    UINT64_C(1077327298560), UINT64_C(0),	// V_COS_F32_e64_dpp_gfx11
    UINT64_C(1077327298560), UINT64_C(0),	// V_COS_F32_e64_dpp_gfx12
    UINT64_C(3585474560), UINT64_C(0),	// V_COS_F32_e64_gfx10
    UINT64_C(3585474560), UINT64_C(0),	// V_COS_F32_e64_gfx11
    UINT64_C(3585474560), UINT64_C(0),	// V_COS_F32_e64_gfx12
    UINT64_C(3547070464), UINT64_C(0),	// V_COS_F32_e64_gfx6_gfx7
    UINT64_C(3513384960), UINT64_C(0),	// V_COS_F32_e64_vi
    UINT64_C(2113957113), UINT64_C(0),	// V_COS_F32_sdwa_gfx10
    UINT64_C(2113950969), UINT64_C(0),	// V_COS_F32_sdwa_gfx9
    UINT64_C(2113950969), UINT64_C(0),	// V_COS_F32_sdwa_vi
    UINT64_C(2113958912), UINT64_C(0),	// V_CTZ_I32_B32_dpp8_gfx11
    UINT64_C(2113958912), UINT64_C(0),	// V_CTZ_I32_B32_dpp8_gfx12
    UINT64_C(2113959162), UINT64_C(0),	// V_CTZ_I32_B32_dpp_gfx11
    UINT64_C(2113959162), UINT64_C(0),	// V_CTZ_I32_B32_dpp_gfx12
    UINT64_C(2113958912), UINT64_C(0),	// V_CTZ_I32_B32_e32_gfx11
    UINT64_C(2113958912), UINT64_C(0),	// V_CTZ_I32_B32_e32_gfx12
    UINT64_C(3585736704), UINT64_C(0),	// V_CTZ_I32_B32_e64_dpp8_gfx11
    UINT64_C(3585736704), UINT64_C(0),	// V_CTZ_I32_B32_e64_dpp8_gfx12
    UINT64_C(1077327560704), UINT64_C(0),	// V_CTZ_I32_B32_e64_dpp_gfx11
    UINT64_C(1077327560704), UINT64_C(0),	// V_CTZ_I32_B32_e64_dpp_gfx12
    UINT64_C(3585736704), UINT64_C(0),	// V_CTZ_I32_B32_e64_gfx11
    UINT64_C(3585736704), UINT64_C(0),	// V_CTZ_I32_B32_e64_gfx12
    UINT64_C(3591110656), UINT64_C(0),	// V_CUBEID_F32_e64_dpp8_gfx11
    UINT64_C(3591110656), UINT64_C(0),	// V_CUBEID_F32_e64_dpp8_gfx12
    UINT64_C(1077332934656), UINT64_C(0),	// V_CUBEID_F32_e64_dpp_gfx11
    UINT64_C(1077332934656), UINT64_C(0),	// V_CUBEID_F32_e64_dpp_gfx12
    UINT64_C(3591110656), UINT64_C(0),	// V_CUBEID_F32_e64_gfx11
    UINT64_C(3591110656), UINT64_C(0),	// V_CUBEID_F32_e64_gfx12
    UINT64_C(3578003456), UINT64_C(0),	// V_CUBEID_F32_gfx10
    UINT64_C(3532128256), UINT64_C(0),	// V_CUBEID_F32_gfx6_gfx7
    UINT64_C(3519283200), UINT64_C(0),	// V_CUBEID_F32_vi
    UINT64_C(3591307264), UINT64_C(0),	// V_CUBEMA_F32_e64_dpp8_gfx11
    UINT64_C(3591307264), UINT64_C(0),	// V_CUBEMA_F32_e64_dpp8_gfx12
    UINT64_C(1077333131264), UINT64_C(0),	// V_CUBEMA_F32_e64_dpp_gfx11
    UINT64_C(1077333131264), UINT64_C(0),	// V_CUBEMA_F32_e64_dpp_gfx12
    UINT64_C(3591307264), UINT64_C(0),	// V_CUBEMA_F32_e64_gfx11
    UINT64_C(3591307264), UINT64_C(0),	// V_CUBEMA_F32_e64_gfx12
    UINT64_C(3578200064), UINT64_C(0),	// V_CUBEMA_F32_gfx10
    UINT64_C(3532521472), UINT64_C(0),	// V_CUBEMA_F32_gfx6_gfx7
    UINT64_C(3519479808), UINT64_C(0),	// V_CUBEMA_F32_vi
    UINT64_C(3591176192), UINT64_C(0),	// V_CUBESC_F32_e64_dpp8_gfx11
    UINT64_C(3591176192), UINT64_C(0),	// V_CUBESC_F32_e64_dpp8_gfx12
    UINT64_C(1077333000192), UINT64_C(0),	// V_CUBESC_F32_e64_dpp_gfx11
    UINT64_C(1077333000192), UINT64_C(0),	// V_CUBESC_F32_e64_dpp_gfx12
    UINT64_C(3591176192), UINT64_C(0),	// V_CUBESC_F32_e64_gfx11
    UINT64_C(3591176192), UINT64_C(0),	// V_CUBESC_F32_e64_gfx12
    UINT64_C(3578068992), UINT64_C(0),	// V_CUBESC_F32_gfx10
    UINT64_C(3532259328), UINT64_C(0),	// V_CUBESC_F32_gfx6_gfx7
    UINT64_C(3519348736), UINT64_C(0),	// V_CUBESC_F32_vi
    UINT64_C(3591241728), UINT64_C(0),	// V_CUBETC_F32_e64_dpp8_gfx11
    UINT64_C(3591241728), UINT64_C(0),	// V_CUBETC_F32_e64_dpp8_gfx12
    UINT64_C(1077333065728), UINT64_C(0),	// V_CUBETC_F32_e64_dpp_gfx11
    UINT64_C(1077333065728), UINT64_C(0),	// V_CUBETC_F32_e64_dpp_gfx12
    UINT64_C(3591241728), UINT64_C(0),	// V_CUBETC_F32_e64_gfx11
    UINT64_C(3591241728), UINT64_C(0),	// V_CUBETC_F32_e64_gfx12
    UINT64_C(3578134528), UINT64_C(0),	// V_CUBETC_F32_gfx10
    UINT64_C(3532390400), UINT64_C(0),	// V_CUBETC_F32_gfx6_gfx7
    UINT64_C(3519414272), UINT64_C(0),	// V_CUBETC_F32_vi
    UINT64_C(2113990656), UINT64_C(0),	// V_CVT_F16_BF8V_CVT_F16_BF8_fake16_dpp8_gfx1250
    UINT64_C(2113990906), UINT64_C(0),	// V_CVT_F16_BF8V_CVT_F16_BF8_fake16_dpp_gfx1250
    UINT64_C(2113990656), UINT64_C(0),	// V_CVT_F16_BF8V_CVT_F16_BF8_fake16_e32_gfx1250
    UINT64_C(3589799936), UINT64_C(0),	// V_CVT_F16_BF8V_CVT_F16_BF8_fake16_e64_dpp8_gfx1250
    UINT64_C(1077331623936), UINT64_C(0),	// V_CVT_F16_BF8V_CVT_F16_BF8_fake16_e64_dpp_gfx1250
    UINT64_C(3589799936), UINT64_C(0),	// V_CVT_F16_BF8V_CVT_F16_BF8_fake16_e64_gfx1250
    UINT64_C(2113990656), UINT64_C(0),	// V_CVT_F16_BF8V_CVT_F16_BF8_t16_dpp8_gfx1250
    UINT64_C(2113990906), UINT64_C(0),	// V_CVT_F16_BF8V_CVT_F16_BF8_t16_dpp_gfx1250
    UINT64_C(2113990656), UINT64_C(0),	// V_CVT_F16_BF8V_CVT_F16_BF8_t16_e32_gfx1250
    UINT64_C(3589799936), UINT64_C(0),	// V_CVT_F16_BF8V_CVT_F16_BF8_t16_e64_dpp8_gfx1250
    UINT64_C(1077331623936), UINT64_C(0),	// V_CVT_F16_BF8V_CVT_F16_BF8_t16_e64_dpp_gfx1250
    UINT64_C(3589799936), UINT64_C(0),	// V_CVT_F16_BF8V_CVT_F16_BF8_t16_e64_gfx1250
    UINT64_C(2113934336), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_fake16_dpp8_gfx11
    UINT64_C(2113934336), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_fake16_dpp8_gfx12
    UINT64_C(2113934586), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_fake16_dpp_gfx11
    UINT64_C(2113934586), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_fake16_dpp_gfx12
    UINT64_C(2113934336), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_fake16_e32_gfx11
    UINT64_C(2113934336), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_fake16_e32_gfx12
    UINT64_C(3582590976), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_fake16_e64_dpp8_gfx11
    UINT64_C(3582590976), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_fake16_e64_dpp8_gfx12
    UINT64_C(1077324414976), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_fake16_e64_dpp_gfx11
    UINT64_C(1077324414976), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_fake16_e64_dpp_gfx12
    UINT64_C(3582590976), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_fake16_e64_gfx11
    UINT64_C(3582590976), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_fake16_e64_gfx12
    UINT64_C(2113934336), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_t16_dpp8_gfx11
    UINT64_C(2113934336), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_t16_dpp8_gfx12
    UINT64_C(2113934586), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_t16_dpp_gfx11
    UINT64_C(2113934586), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_t16_dpp_gfx12
    UINT64_C(2113934336), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_t16_e32_gfx11
    UINT64_C(2113934336), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_t16_e32_gfx12
    UINT64_C(3582590976), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_t16_e64_dpp8_gfx11
    UINT64_C(3582590976), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_t16_e64_dpp8_gfx12
    UINT64_C(1077324414976), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_t16_e64_dpp_gfx11
    UINT64_C(1077324414976), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_t16_e64_dpp_gfx12
    UINT64_C(3582590976), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_t16_e64_gfx11
    UINT64_C(3582590976), UINT64_C(0),	// V_CVT_F16_F32V_CVT_F16_F32_t16_e64_gfx12
    UINT64_C(2113934336), UINT64_C(0),	// V_CVT_F16_F32_dpp8_gfx10
    UINT64_C(2113934586), UINT64_C(0),	// V_CVT_F16_F32_dpp_gfx10
    UINT64_C(2113934586), UINT64_C(0),	// V_CVT_F16_F32_dpp_vi
    UINT64_C(2113934336), UINT64_C(0),	// V_CVT_F16_F32_e32_gfx10
    UINT64_C(2113934336), UINT64_C(0),	// V_CVT_F16_F32_e32_gfx6_gfx7
    UINT64_C(2113934336), UINT64_C(0),	// V_CVT_F16_F32_e32_vi
    UINT64_C(3582590976), UINT64_C(0),	// V_CVT_F16_F32_e64_gfx10
    UINT64_C(3541303296), UINT64_C(0),	// V_CVT_F16_F32_e64_gfx6_gfx7
    UINT64_C(3511287808), UINT64_C(0),	// V_CVT_F16_F32_e64_vi
    UINT64_C(2113934585), UINT64_C(0),	// V_CVT_F16_F32_sdwa_gfx10
    UINT64_C(2113934585), UINT64_C(0),	// V_CVT_F16_F32_sdwa_gfx9
    UINT64_C(2113934585), UINT64_C(0),	// V_CVT_F16_F32_sdwa_vi
    UINT64_C(2113990144), UINT64_C(0),	// V_CVT_F16_FP8V_CVT_F16_FP8_fake16_dpp8_gfx1250
    UINT64_C(2113990394), UINT64_C(0),	// V_CVT_F16_FP8V_CVT_F16_FP8_fake16_dpp_gfx1250
    UINT64_C(2113990144), UINT64_C(0),	// V_CVT_F16_FP8V_CVT_F16_FP8_fake16_e32_gfx1250
    UINT64_C(3589734400), UINT64_C(0),	// V_CVT_F16_FP8V_CVT_F16_FP8_fake16_e64_dpp8_gfx1250
    UINT64_C(1077331558400), UINT64_C(0),	// V_CVT_F16_FP8V_CVT_F16_FP8_fake16_e64_dpp_gfx1250
    UINT64_C(3589734400), UINT64_C(0),	// V_CVT_F16_FP8V_CVT_F16_FP8_fake16_e64_gfx1250
    UINT64_C(2113990144), UINT64_C(0),	// V_CVT_F16_FP8V_CVT_F16_FP8_t16_dpp8_gfx1250
    UINT64_C(2113990394), UINT64_C(0),	// V_CVT_F16_FP8V_CVT_F16_FP8_t16_dpp_gfx1250
    UINT64_C(2113990144), UINT64_C(0),	// V_CVT_F16_FP8V_CVT_F16_FP8_t16_e32_gfx1250
    UINT64_C(3589734400), UINT64_C(0),	// V_CVT_F16_FP8V_CVT_F16_FP8_t16_e64_dpp8_gfx1250
    UINT64_C(1077331558400), UINT64_C(0),	// V_CVT_F16_FP8V_CVT_F16_FP8_t16_e64_dpp_gfx1250
    UINT64_C(3589734400), UINT64_C(0),	// V_CVT_F16_FP8V_CVT_F16_FP8_t16_e64_gfx1250
    UINT64_C(2113970688), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_fake16_dpp8_gfx11
    UINT64_C(2113970688), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_fake16_dpp8_gfx12
    UINT64_C(2113970938), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_fake16_dpp_gfx11
    UINT64_C(2113970938), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_fake16_dpp_gfx12
    UINT64_C(2113970688), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_fake16_e32_gfx11
    UINT64_C(2113970688), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_fake16_e32_gfx12
    UINT64_C(3587244032), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3587244032), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077329068032), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077329068032), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_fake16_e64_dpp_gfx12
    UINT64_C(3587244032), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_fake16_e64_gfx11
    UINT64_C(3587244032), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_fake16_e64_gfx12
    UINT64_C(2113970688), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_t16_dpp8_gfx11
    UINT64_C(2113970688), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_t16_dpp8_gfx12
    UINT64_C(2113970938), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_t16_dpp_gfx11
    UINT64_C(2113970938), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_t16_dpp_gfx12
    UINT64_C(2113970688), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_t16_e32_gfx11
    UINT64_C(2113970688), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_t16_e32_gfx12
    UINT64_C(3587244032), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_t16_e64_dpp8_gfx11
    UINT64_C(3587244032), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077329068032), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_t16_e64_dpp_gfx11
    UINT64_C(1077329068032), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_t16_e64_dpp_gfx12
    UINT64_C(3587244032), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_t16_e64_gfx11
    UINT64_C(3587244032), UINT64_C(0),	// V_CVT_F16_I16V_CVT_F16_I16_t16_e64_gfx12
    UINT64_C(2113970688), UINT64_C(0),	// V_CVT_F16_I16_dpp8_gfx10
    UINT64_C(2113970938), UINT64_C(0),	// V_CVT_F16_I16_dpp_gfx10
    UINT64_C(2113959162), UINT64_C(0),	// V_CVT_F16_I16_dpp_vi
    UINT64_C(2113970688), UINT64_C(0),	// V_CVT_F16_I16_e32_gfx10
    UINT64_C(2113958912), UINT64_C(0),	// V_CVT_F16_I16_e32_vi
    UINT64_C(3587244032), UINT64_C(0),	// V_CVT_F16_I16_e64_gfx10
    UINT64_C(3514433536), UINT64_C(0),	// V_CVT_F16_I16_e64_vi
    UINT64_C(2113970937), UINT64_C(0),	// V_CVT_F16_I16_sdwa_gfx10
    UINT64_C(2113959161), UINT64_C(0),	// V_CVT_F16_I16_sdwa_gfx9
    UINT64_C(2113959161), UINT64_C(0),	// V_CVT_F16_I16_sdwa_vi
    UINT64_C(2113970176), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_fake16_dpp8_gfx11
    UINT64_C(2113970176), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_fake16_dpp8_gfx12
    UINT64_C(2113970426), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_fake16_dpp_gfx11
    UINT64_C(2113970426), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_fake16_dpp_gfx12
    UINT64_C(2113970176), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_fake16_e32_gfx11
    UINT64_C(2113970176), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_fake16_e32_gfx12
    UINT64_C(3587178496), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3587178496), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077329002496), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077329002496), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_fake16_e64_dpp_gfx12
    UINT64_C(3587178496), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_fake16_e64_gfx11
    UINT64_C(3587178496), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_fake16_e64_gfx12
    UINT64_C(2113970176), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_t16_dpp8_gfx11
    UINT64_C(2113970176), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_t16_dpp8_gfx12
    UINT64_C(2113970426), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_t16_dpp_gfx11
    UINT64_C(2113970426), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_t16_dpp_gfx12
    UINT64_C(2113970176), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_t16_e32_gfx11
    UINT64_C(2113970176), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_t16_e32_gfx12
    UINT64_C(3587178496), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_t16_e64_dpp8_gfx11
    UINT64_C(3587178496), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077329002496), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_t16_e64_dpp_gfx11
    UINT64_C(1077329002496), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_t16_e64_dpp_gfx12
    UINT64_C(3587178496), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_t16_e64_gfx11
    UINT64_C(3587178496), UINT64_C(0),	// V_CVT_F16_U16V_CVT_F16_U16_t16_e64_gfx12
    UINT64_C(2113970176), UINT64_C(0),	// V_CVT_F16_U16_dpp8_gfx10
    UINT64_C(2113970426), UINT64_C(0),	// V_CVT_F16_U16_dpp_gfx10
    UINT64_C(2113958650), UINT64_C(0),	// V_CVT_F16_U16_dpp_vi
    UINT64_C(2113970176), UINT64_C(0),	// V_CVT_F16_U16_e32_gfx10
    UINT64_C(2113958400), UINT64_C(0),	// V_CVT_F16_U16_e32_vi
    UINT64_C(3587178496), UINT64_C(0),	// V_CVT_F16_U16_e64_gfx10
    UINT64_C(3514368000), UINT64_C(0),	// V_CVT_F16_U16_e64_vi
    UINT64_C(2113970425), UINT64_C(0),	// V_CVT_F16_U16_sdwa_gfx10
    UINT64_C(2113958649), UINT64_C(0),	// V_CVT_F16_U16_sdwa_gfx9
    UINT64_C(2113958649), UINT64_C(0),	// V_CVT_F16_U16_sdwa_vi
    UINT64_C(2113976058), UINT64_C(0),	// V_CVT_F32_BF16_dpp_gfx9
    UINT64_C(2113975808), UINT64_C(0),	// V_CVT_F32_BF16_e32_vi
    UINT64_C(3516596224), UINT64_C(0),	// V_CVT_F32_BF16_e64_vi
    UINT64_C(2113987584), UINT64_C(0),	// V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_fake16_dpp8_gfx1250
    UINT64_C(2113987834), UINT64_C(0),	// V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_fake16_dpp_gfx1250
    UINT64_C(2113987584), UINT64_C(0),	// V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_fake16_e32_gfx1250
    UINT64_C(3589406720), UINT64_C(0),	// V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_fake16_e64_dpp8_gfx1250
    UINT64_C(1077331230720), UINT64_C(0),	// V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_fake16_e64_dpp_gfx1250
    UINT64_C(3589406720), UINT64_C(0),	// V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_fake16_e64_gfx1250
    UINT64_C(2113987584), UINT64_C(0),	// V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_t16_dpp8_gfx1250
    UINT64_C(2113987834), UINT64_C(0),	// V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_t16_dpp_gfx1250
    UINT64_C(2113987584), UINT64_C(0),	// V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_t16_e32_gfx1250
    UINT64_C(3589406720), UINT64_C(0),	// V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_t16_e64_dpp8_gfx1250
    UINT64_C(1077331230720), UINT64_C(0),	// V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_t16_e64_dpp_gfx1250
    UINT64_C(3589406720), UINT64_C(0),	// V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_t16_e64_gfx1250
    UINT64_C(2113976057), UINT64_C(0),	// V_CVT_F32_BF16_sdwa_gfx9
    UINT64_C(2113985024), UINT64_C(0),	// V_CVT_F32_BF8_dpp8_gfx12
    UINT64_C(2113985274), UINT64_C(0),	// V_CVT_F32_BF8_dpp_gfx12
    UINT64_C(2113972986), UINT64_C(0),	// V_CVT_F32_BF8_dpp_gfx9
    UINT64_C(2113985024), UINT64_C(0),	// V_CVT_F32_BF8_e32_gfx12
    UINT64_C(2113972736), UINT64_C(0),	// V_CVT_F32_BF8_e32_vi
    UINT64_C(3589079040), UINT64_C(0),	// V_CVT_F32_BF8_e64_dpp8_gfx12
    UINT64_C(1077330903040), UINT64_C(0),	// V_CVT_F32_BF8_e64_dpp_gfx12
    UINT64_C(3589079040), UINT64_C(0),	// V_CVT_F32_BF8_e64_gfx12
    UINT64_C(3516203008), UINT64_C(0),	// V_CVT_F32_BF8_e64_vi
    UINT64_C(6599183739641), UINT64_C(0),	// V_CVT_F32_BF8_sdwa_gfx9
    UINT64_C(2113934848), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_fake16_dpp8_gfx11
    UINT64_C(2113934848), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_fake16_dpp8_gfx12
    UINT64_C(2113935098), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_fake16_dpp_gfx11
    UINT64_C(2113935098), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_fake16_dpp_gfx12
    UINT64_C(2113934848), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_fake16_e32_gfx11
    UINT64_C(2113934848), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_fake16_e32_gfx12
    UINT64_C(3582656512), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3582656512), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077324480512), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077324480512), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_fake16_e64_dpp_gfx12
    UINT64_C(3582656512), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_fake16_e64_gfx11
    UINT64_C(3582656512), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_fake16_e64_gfx12
    UINT64_C(2113934848), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_t16_dpp8_gfx11
    UINT64_C(2113934848), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_t16_dpp8_gfx12
    UINT64_C(2113935098), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_t16_dpp_gfx11
    UINT64_C(2113935098), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_t16_dpp_gfx12
    UINT64_C(2113934848), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_t16_e32_gfx11
    UINT64_C(2113934848), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_t16_e32_gfx12
    UINT64_C(3582656512), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_t16_e64_dpp8_gfx11
    UINT64_C(3582656512), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077324480512), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_t16_e64_dpp_gfx11
    UINT64_C(1077324480512), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_t16_e64_dpp_gfx12
    UINT64_C(3582656512), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_t16_e64_gfx11
    UINT64_C(3582656512), UINT64_C(0),	// V_CVT_F32_F16V_CVT_F32_F16_t16_e64_gfx12
    UINT64_C(2113934848), UINT64_C(0),	// V_CVT_F32_F16_dpp8_gfx10
    UINT64_C(2113935098), UINT64_C(0),	// V_CVT_F32_F16_dpp_gfx10
    UINT64_C(2113935098), UINT64_C(0),	// V_CVT_F32_F16_dpp_vi
    UINT64_C(2113934848), UINT64_C(0),	// V_CVT_F32_F16_e32_gfx10
    UINT64_C(2113934848), UINT64_C(0),	// V_CVT_F32_F16_e32_gfx6_gfx7
    UINT64_C(2113934848), UINT64_C(0),	// V_CVT_F32_F16_e32_vi
    UINT64_C(3582656512), UINT64_C(0),	// V_CVT_F32_F16_e64_gfx10
    UINT64_C(3541434368), UINT64_C(0),	// V_CVT_F32_F16_e64_gfx6_gfx7
    UINT64_C(3511353344), UINT64_C(0),	// V_CVT_F32_F16_e64_vi
    UINT64_C(2113935097), UINT64_C(0),	// V_CVT_F32_F16_sdwa_gfx10
    UINT64_C(2113935097), UINT64_C(0),	// V_CVT_F32_F16_sdwa_gfx9
    UINT64_C(2113935097), UINT64_C(0),	// V_CVT_F32_F16_sdwa_vi
    UINT64_C(2113937146), UINT64_C(0),	// V_CVT_F32_F64_dpp_gfx12
    UINT64_C(2113937146), UINT64_C(0),	// V_CVT_F32_F64_dpp_vi
    UINT64_C(2113936896), UINT64_C(0),	// V_CVT_F32_F64_e32_gfx10
    UINT64_C(2113936896), UINT64_C(0),	// V_CVT_F32_F64_e32_gfx11
    UINT64_C(2113936896), UINT64_C(0),	// V_CVT_F32_F64_e32_gfx12
    UINT64_C(2113936896), UINT64_C(0),	// V_CVT_F32_F64_e32_gfx6_gfx7
    UINT64_C(2113936896), UINT64_C(0),	// V_CVT_F32_F64_e32_vi
    UINT64_C(1077324742656), UINT64_C(0),	// V_CVT_F32_F64_e64_dpp_gfx12
    UINT64_C(3582918656), UINT64_C(0),	// V_CVT_F32_F64_e64_gfx10
    UINT64_C(3582918656), UINT64_C(0),	// V_CVT_F32_F64_e64_gfx11
    UINT64_C(3582918656), UINT64_C(0),	// V_CVT_F32_F64_e64_gfx12
    UINT64_C(3541958656), UINT64_C(0),	// V_CVT_F32_F64_e64_gfx6_gfx7
    UINT64_C(3511615488), UINT64_C(0),	// V_CVT_F32_F64_e64_vi
    UINT64_C(2113984512), UINT64_C(0),	// V_CVT_F32_FP8_dpp8_gfx11
    UINT64_C(2113984512), UINT64_C(0),	// V_CVT_F32_FP8_dpp8_gfx12
    UINT64_C(2113984512), UINT64_C(0),	// V_CVT_F32_FP8_dpp8_gfx1250
    UINT64_C(2113984762), UINT64_C(0),	// V_CVT_F32_FP8_dpp_gfx11
    UINT64_C(2113984762), UINT64_C(0),	// V_CVT_F32_FP8_dpp_gfx12
    UINT64_C(2113984762), UINT64_C(0),	// V_CVT_F32_FP8_dpp_gfx1250
    UINT64_C(2113972474), UINT64_C(0),	// V_CVT_F32_FP8_dpp_gfx9
    UINT64_C(2113984512), UINT64_C(0),	// V_CVT_F32_FP8_e32_gfx11
    UINT64_C(2113984512), UINT64_C(0),	// V_CVT_F32_FP8_e32_gfx12
    UINT64_C(2113984512), UINT64_C(0),	// V_CVT_F32_FP8_e32_gfx1250
    UINT64_C(2113972224), UINT64_C(0),	// V_CVT_F32_FP8_e32_vi
    UINT64_C(3589013504), UINT64_C(0),	// V_CVT_F32_FP8_e64_dpp8_gfx11
    UINT64_C(3589013504), UINT64_C(0),	// V_CVT_F32_FP8_e64_dpp8_gfx12
    UINT64_C(3589013504), UINT64_C(0),	// V_CVT_F32_FP8_e64_dpp8_gfx1250
    UINT64_C(1077330837504), UINT64_C(0),	// V_CVT_F32_FP8_e64_dpp_gfx11
    UINT64_C(1077330837504), UINT64_C(0),	// V_CVT_F32_FP8_e64_dpp_gfx12
    UINT64_C(1077330837504), UINT64_C(0),	// V_CVT_F32_FP8_e64_dpp_gfx1250
    UINT64_C(3589013504), UINT64_C(0),	// V_CVT_F32_FP8_e64_gfx11
    UINT64_C(3589013504), UINT64_C(0),	// V_CVT_F32_FP8_e64_gfx12
    UINT64_C(3589013504), UINT64_C(0),	// V_CVT_F32_FP8_e64_gfx1250
    UINT64_C(3516137472), UINT64_C(0),	// V_CVT_F32_FP8_e64_vi
    UINT64_C(6599183739129), UINT64_C(0),	// V_CVT_F32_FP8_sdwa_gfx9
    UINT64_C(2113931776), UINT64_C(0),	// V_CVT_F32_I32_dpp8_gfx10
    UINT64_C(2113931776), UINT64_C(0),	// V_CVT_F32_I32_dpp8_gfx11
    UINT64_C(2113931776), UINT64_C(0),	// V_CVT_F32_I32_dpp8_gfx12
    UINT64_C(2113932026), UINT64_C(0),	// V_CVT_F32_I32_dpp_gfx10
    UINT64_C(2113932026), UINT64_C(0),	// V_CVT_F32_I32_dpp_gfx11
    UINT64_C(2113932026), UINT64_C(0),	// V_CVT_F32_I32_dpp_gfx12
    UINT64_C(2113932026), UINT64_C(0),	// V_CVT_F32_I32_dpp_vi
    UINT64_C(2113931776), UINT64_C(0),	// V_CVT_F32_I32_e32_gfx10
    UINT64_C(2113931776), UINT64_C(0),	// V_CVT_F32_I32_e32_gfx11
    UINT64_C(2113931776), UINT64_C(0),	// V_CVT_F32_I32_e32_gfx12
    UINT64_C(2113931776), UINT64_C(0),	// V_CVT_F32_I32_e32_gfx6_gfx7
    UINT64_C(2113931776), UINT64_C(0),	// V_CVT_F32_I32_e32_vi
    UINT64_C(3582263296), UINT64_C(0),	// V_CVT_F32_I32_e64_dpp8_gfx11
    UINT64_C(3582263296), UINT64_C(0),	// V_CVT_F32_I32_e64_dpp8_gfx12
    UINT64_C(1077324087296), UINT64_C(0),	// V_CVT_F32_I32_e64_dpp_gfx11
    UINT64_C(1077324087296), UINT64_C(0),	// V_CVT_F32_I32_e64_dpp_gfx12
    UINT64_C(3582263296), UINT64_C(0),	// V_CVT_F32_I32_e64_gfx10
    UINT64_C(3582263296), UINT64_C(0),	// V_CVT_F32_I32_e64_gfx11
    UINT64_C(3582263296), UINT64_C(0),	// V_CVT_F32_I32_e64_gfx12
    UINT64_C(3540647936), UINT64_C(0),	// V_CVT_F32_I32_e64_gfx6_gfx7
    UINT64_C(3510960128), UINT64_C(0),	// V_CVT_F32_I32_e64_vi
    UINT64_C(2113932025), UINT64_C(0),	// V_CVT_F32_I32_sdwa_gfx10
    UINT64_C(2113932025), UINT64_C(0),	// V_CVT_F32_I32_sdwa_gfx9
    UINT64_C(2113932025), UINT64_C(0),	// V_CVT_F32_I32_sdwa_vi
    UINT64_C(2113932288), UINT64_C(0),	// V_CVT_F32_U32_dpp8_gfx10
    UINT64_C(2113932288), UINT64_C(0),	// V_CVT_F32_U32_dpp8_gfx11
    UINT64_C(2113932288), UINT64_C(0),	// V_CVT_F32_U32_dpp8_gfx12
    UINT64_C(2113932538), UINT64_C(0),	// V_CVT_F32_U32_dpp_gfx10
    UINT64_C(2113932538), UINT64_C(0),	// V_CVT_F32_U32_dpp_gfx11
    UINT64_C(2113932538), UINT64_C(0),	// V_CVT_F32_U32_dpp_gfx12
    UINT64_C(2113932538), UINT64_C(0),	// V_CVT_F32_U32_dpp_vi
    UINT64_C(2113932288), UINT64_C(0),	// V_CVT_F32_U32_e32_gfx10
    UINT64_C(2113932288), UINT64_C(0),	// V_CVT_F32_U32_e32_gfx11
    UINT64_C(2113932288), UINT64_C(0),	// V_CVT_F32_U32_e32_gfx12
    UINT64_C(2113932288), UINT64_C(0),	// V_CVT_F32_U32_e32_gfx6_gfx7
    UINT64_C(2113932288), UINT64_C(0),	// V_CVT_F32_U32_e32_vi
    UINT64_C(3582328832), UINT64_C(0),	// V_CVT_F32_U32_e64_dpp8_gfx11
    UINT64_C(3582328832), UINT64_C(0),	// V_CVT_F32_U32_e64_dpp8_gfx12
    UINT64_C(1077324152832), UINT64_C(0),	// V_CVT_F32_U32_e64_dpp_gfx11
    UINT64_C(1077324152832), UINT64_C(0),	// V_CVT_F32_U32_e64_dpp_gfx12
    UINT64_C(3582328832), UINT64_C(0),	// V_CVT_F32_U32_e64_gfx10
    UINT64_C(3582328832), UINT64_C(0),	// V_CVT_F32_U32_e64_gfx11
    UINT64_C(3582328832), UINT64_C(0),	// V_CVT_F32_U32_e64_gfx12
    UINT64_C(3540779008), UINT64_C(0),	// V_CVT_F32_U32_e64_gfx6_gfx7
    UINT64_C(3511025664), UINT64_C(0),	// V_CVT_F32_U32_e64_vi
    UINT64_C(2113932537), UINT64_C(0),	// V_CVT_F32_U32_sdwa_gfx10
    UINT64_C(2113932537), UINT64_C(0),	// V_CVT_F32_U32_sdwa_gfx9
    UINT64_C(2113932537), UINT64_C(0),	// V_CVT_F32_U32_sdwa_vi
    UINT64_C(2113937920), UINT64_C(0),	// V_CVT_F32_UBYTE0_dpp8_gfx10
    UINT64_C(2113937920), UINT64_C(0),	// V_CVT_F32_UBYTE0_dpp8_gfx11
    UINT64_C(2113937920), UINT64_C(0),	// V_CVT_F32_UBYTE0_dpp8_gfx12
    UINT64_C(2113938170), UINT64_C(0),	// V_CVT_F32_UBYTE0_dpp_gfx10
    UINT64_C(2113938170), UINT64_C(0),	// V_CVT_F32_UBYTE0_dpp_gfx11
    UINT64_C(2113938170), UINT64_C(0),	// V_CVT_F32_UBYTE0_dpp_gfx12
    UINT64_C(2113938170), UINT64_C(0),	// V_CVT_F32_UBYTE0_dpp_vi
    UINT64_C(2113937920), UINT64_C(0),	// V_CVT_F32_UBYTE0_e32_gfx10
    UINT64_C(2113937920), UINT64_C(0),	// V_CVT_F32_UBYTE0_e32_gfx11
    UINT64_C(2113937920), UINT64_C(0),	// V_CVT_F32_UBYTE0_e32_gfx12
    UINT64_C(2113937920), UINT64_C(0),	// V_CVT_F32_UBYTE0_e32_gfx6_gfx7
    UINT64_C(2113937920), UINT64_C(0),	// V_CVT_F32_UBYTE0_e32_vi
    UINT64_C(3583049728), UINT64_C(0),	// V_CVT_F32_UBYTE0_e64_dpp8_gfx11
    UINT64_C(3583049728), UINT64_C(0),	// V_CVT_F32_UBYTE0_e64_dpp8_gfx12
    UINT64_C(1077324873728), UINT64_C(0),	// V_CVT_F32_UBYTE0_e64_dpp_gfx11
    UINT64_C(1077324873728), UINT64_C(0),	// V_CVT_F32_UBYTE0_e64_dpp_gfx12
    UINT64_C(3583049728), UINT64_C(0),	// V_CVT_F32_UBYTE0_e64_gfx10
    UINT64_C(3583049728), UINT64_C(0),	// V_CVT_F32_UBYTE0_e64_gfx11
    UINT64_C(3583049728), UINT64_C(0),	// V_CVT_F32_UBYTE0_e64_gfx12
    UINT64_C(3542220800), UINT64_C(0),	// V_CVT_F32_UBYTE0_e64_gfx6_gfx7
    UINT64_C(3511746560), UINT64_C(0),	// V_CVT_F32_UBYTE0_e64_vi
    UINT64_C(2113938169), UINT64_C(0),	// V_CVT_F32_UBYTE0_sdwa_gfx10
    UINT64_C(2113938169), UINT64_C(0),	// V_CVT_F32_UBYTE0_sdwa_gfx9
    UINT64_C(2113938169), UINT64_C(0),	// V_CVT_F32_UBYTE0_sdwa_vi
    UINT64_C(2113938432), UINT64_C(0),	// V_CVT_F32_UBYTE1_dpp8_gfx10
    UINT64_C(2113938432), UINT64_C(0),	// V_CVT_F32_UBYTE1_dpp8_gfx11
    UINT64_C(2113938432), UINT64_C(0),	// V_CVT_F32_UBYTE1_dpp8_gfx12
    UINT64_C(2113938682), UINT64_C(0),	// V_CVT_F32_UBYTE1_dpp_gfx10
    UINT64_C(2113938682), UINT64_C(0),	// V_CVT_F32_UBYTE1_dpp_gfx11
    UINT64_C(2113938682), UINT64_C(0),	// V_CVT_F32_UBYTE1_dpp_gfx12
    UINT64_C(2113938682), UINT64_C(0),	// V_CVT_F32_UBYTE1_dpp_vi
    UINT64_C(2113938432), UINT64_C(0),	// V_CVT_F32_UBYTE1_e32_gfx10
    UINT64_C(2113938432), UINT64_C(0),	// V_CVT_F32_UBYTE1_e32_gfx11
    UINT64_C(2113938432), UINT64_C(0),	// V_CVT_F32_UBYTE1_e32_gfx12
    UINT64_C(2113938432), UINT64_C(0),	// V_CVT_F32_UBYTE1_e32_gfx6_gfx7
    UINT64_C(2113938432), UINT64_C(0),	// V_CVT_F32_UBYTE1_e32_vi
    UINT64_C(3583115264), UINT64_C(0),	// V_CVT_F32_UBYTE1_e64_dpp8_gfx11
    UINT64_C(3583115264), UINT64_C(0),	// V_CVT_F32_UBYTE1_e64_dpp8_gfx12
    UINT64_C(1077324939264), UINT64_C(0),	// V_CVT_F32_UBYTE1_e64_dpp_gfx11
    UINT64_C(1077324939264), UINT64_C(0),	// V_CVT_F32_UBYTE1_e64_dpp_gfx12
    UINT64_C(3583115264), UINT64_C(0),	// V_CVT_F32_UBYTE1_e64_gfx10
    UINT64_C(3583115264), UINT64_C(0),	// V_CVT_F32_UBYTE1_e64_gfx11
    UINT64_C(3583115264), UINT64_C(0),	// V_CVT_F32_UBYTE1_e64_gfx12
    UINT64_C(3542351872), UINT64_C(0),	// V_CVT_F32_UBYTE1_e64_gfx6_gfx7
    UINT64_C(3511812096), UINT64_C(0),	// V_CVT_F32_UBYTE1_e64_vi
    UINT64_C(2113938681), UINT64_C(0),	// V_CVT_F32_UBYTE1_sdwa_gfx10
    UINT64_C(2113938681), UINT64_C(0),	// V_CVT_F32_UBYTE1_sdwa_gfx9
    UINT64_C(2113938681), UINT64_C(0),	// V_CVT_F32_UBYTE1_sdwa_vi
    UINT64_C(2113938944), UINT64_C(0),	// V_CVT_F32_UBYTE2_dpp8_gfx10
    UINT64_C(2113938944), UINT64_C(0),	// V_CVT_F32_UBYTE2_dpp8_gfx11
    UINT64_C(2113938944), UINT64_C(0),	// V_CVT_F32_UBYTE2_dpp8_gfx12
    UINT64_C(2113939194), UINT64_C(0),	// V_CVT_F32_UBYTE2_dpp_gfx10
    UINT64_C(2113939194), UINT64_C(0),	// V_CVT_F32_UBYTE2_dpp_gfx11
    UINT64_C(2113939194), UINT64_C(0),	// V_CVT_F32_UBYTE2_dpp_gfx12
    UINT64_C(2113939194), UINT64_C(0),	// V_CVT_F32_UBYTE2_dpp_vi
    UINT64_C(2113938944), UINT64_C(0),	// V_CVT_F32_UBYTE2_e32_gfx10
    UINT64_C(2113938944), UINT64_C(0),	// V_CVT_F32_UBYTE2_e32_gfx11
    UINT64_C(2113938944), UINT64_C(0),	// V_CVT_F32_UBYTE2_e32_gfx12
    UINT64_C(2113938944), UINT64_C(0),	// V_CVT_F32_UBYTE2_e32_gfx6_gfx7
    UINT64_C(2113938944), UINT64_C(0),	// V_CVT_F32_UBYTE2_e32_vi
    UINT64_C(3583180800), UINT64_C(0),	// V_CVT_F32_UBYTE2_e64_dpp8_gfx11
    UINT64_C(3583180800), UINT64_C(0),	// V_CVT_F32_UBYTE2_e64_dpp8_gfx12
    UINT64_C(1077325004800), UINT64_C(0),	// V_CVT_F32_UBYTE2_e64_dpp_gfx11
    UINT64_C(1077325004800), UINT64_C(0),	// V_CVT_F32_UBYTE2_e64_dpp_gfx12
    UINT64_C(3583180800), UINT64_C(0),	// V_CVT_F32_UBYTE2_e64_gfx10
    UINT64_C(3583180800), UINT64_C(0),	// V_CVT_F32_UBYTE2_e64_gfx11
    UINT64_C(3583180800), UINT64_C(0),	// V_CVT_F32_UBYTE2_e64_gfx12
    UINT64_C(3542482944), UINT64_C(0),	// V_CVT_F32_UBYTE2_e64_gfx6_gfx7
    UINT64_C(3511877632), UINT64_C(0),	// V_CVT_F32_UBYTE2_e64_vi
    UINT64_C(2113939193), UINT64_C(0),	// V_CVT_F32_UBYTE2_sdwa_gfx10
    UINT64_C(2113939193), UINT64_C(0),	// V_CVT_F32_UBYTE2_sdwa_gfx9
    UINT64_C(2113939193), UINT64_C(0),	// V_CVT_F32_UBYTE2_sdwa_vi
    UINT64_C(2113939456), UINT64_C(0),	// V_CVT_F32_UBYTE3_dpp8_gfx10
    UINT64_C(2113939456), UINT64_C(0),	// V_CVT_F32_UBYTE3_dpp8_gfx11
    UINT64_C(2113939456), UINT64_C(0),	// V_CVT_F32_UBYTE3_dpp8_gfx12
    UINT64_C(2113939706), UINT64_C(0),	// V_CVT_F32_UBYTE3_dpp_gfx10
    UINT64_C(2113939706), UINT64_C(0),	// V_CVT_F32_UBYTE3_dpp_gfx11
    UINT64_C(2113939706), UINT64_C(0),	// V_CVT_F32_UBYTE3_dpp_gfx12
    UINT64_C(2113939706), UINT64_C(0),	// V_CVT_F32_UBYTE3_dpp_vi
    UINT64_C(2113939456), UINT64_C(0),	// V_CVT_F32_UBYTE3_e32_gfx10
    UINT64_C(2113939456), UINT64_C(0),	// V_CVT_F32_UBYTE3_e32_gfx11
    UINT64_C(2113939456), UINT64_C(0),	// V_CVT_F32_UBYTE3_e32_gfx12
    UINT64_C(2113939456), UINT64_C(0),	// V_CVT_F32_UBYTE3_e32_gfx6_gfx7
    UINT64_C(2113939456), UINT64_C(0),	// V_CVT_F32_UBYTE3_e32_vi
    UINT64_C(3583246336), UINT64_C(0),	// V_CVT_F32_UBYTE3_e64_dpp8_gfx11
    UINT64_C(3583246336), UINT64_C(0),	// V_CVT_F32_UBYTE3_e64_dpp8_gfx12
    UINT64_C(1077325070336), UINT64_C(0),	// V_CVT_F32_UBYTE3_e64_dpp_gfx11
    UINT64_C(1077325070336), UINT64_C(0),	// V_CVT_F32_UBYTE3_e64_dpp_gfx12
    UINT64_C(3583246336), UINT64_C(0),	// V_CVT_F32_UBYTE3_e64_gfx10
    UINT64_C(3583246336), UINT64_C(0),	// V_CVT_F32_UBYTE3_e64_gfx11
    UINT64_C(3583246336), UINT64_C(0),	// V_CVT_F32_UBYTE3_e64_gfx12
    UINT64_C(3542614016), UINT64_C(0),	// V_CVT_F32_UBYTE3_e64_gfx6_gfx7
    UINT64_C(3511943168), UINT64_C(0),	// V_CVT_F32_UBYTE3_e64_vi
    UINT64_C(2113939705), UINT64_C(0),	// V_CVT_F32_UBYTE3_sdwa_gfx10
    UINT64_C(2113939705), UINT64_C(0),	// V_CVT_F32_UBYTE3_sdwa_gfx9
    UINT64_C(2113939705), UINT64_C(0),	// V_CVT_F32_UBYTE3_sdwa_vi
    UINT64_C(2113937658), UINT64_C(0),	// V_CVT_F64_F32_dpp_gfx12
    UINT64_C(2113937658), UINT64_C(0),	// V_CVT_F64_F32_dpp_vi
    UINT64_C(2113937408), UINT64_C(0),	// V_CVT_F64_F32_e32_gfx10
    UINT64_C(2113937408), UINT64_C(0),	// V_CVT_F64_F32_e32_gfx11
    UINT64_C(2113937408), UINT64_C(0),	// V_CVT_F64_F32_e32_gfx12
    UINT64_C(2113937408), UINT64_C(0),	// V_CVT_F64_F32_e32_gfx6_gfx7
    UINT64_C(2113937408), UINT64_C(0),	// V_CVT_F64_F32_e32_vi
    UINT64_C(1077324808192), UINT64_C(0),	// V_CVT_F64_F32_e64_dpp_gfx12
    UINT64_C(3582984192), UINT64_C(0),	// V_CVT_F64_F32_e64_gfx10
    UINT64_C(3582984192), UINT64_C(0),	// V_CVT_F64_F32_e64_gfx11
    UINT64_C(3582984192), UINT64_C(0),	// V_CVT_F64_F32_e64_gfx12
    UINT64_C(3542089728), UINT64_C(0),	// V_CVT_F64_F32_e64_gfx6_gfx7
    UINT64_C(3511681024), UINT64_C(0),	// V_CVT_F64_F32_e64_vi
    UINT64_C(2113931514), UINT64_C(0),	// V_CVT_F64_I32_dpp_gfx12
    UINT64_C(2113931514), UINT64_C(0),	// V_CVT_F64_I32_dpp_vi
    UINT64_C(2113931264), UINT64_C(0),	// V_CVT_F64_I32_e32_gfx10
    UINT64_C(2113931264), UINT64_C(0),	// V_CVT_F64_I32_e32_gfx11
    UINT64_C(2113931264), UINT64_C(0),	// V_CVT_F64_I32_e32_gfx12
    UINT64_C(2113931264), UINT64_C(0),	// V_CVT_F64_I32_e32_gfx6_gfx7
    UINT64_C(2113931264), UINT64_C(0),	// V_CVT_F64_I32_e32_vi
    UINT64_C(1077324021760), UINT64_C(0),	// V_CVT_F64_I32_e64_dpp_gfx12
    UINT64_C(3582197760), UINT64_C(0),	// V_CVT_F64_I32_e64_gfx10
    UINT64_C(3582197760), UINT64_C(0),	// V_CVT_F64_I32_e64_gfx11
    UINT64_C(3582197760), UINT64_C(0),	// V_CVT_F64_I32_e64_gfx12
    UINT64_C(3540516864), UINT64_C(0),	// V_CVT_F64_I32_e64_gfx6_gfx7
    UINT64_C(3510894592), UINT64_C(0),	// V_CVT_F64_I32_e64_vi
    UINT64_C(2113940730), UINT64_C(0),	// V_CVT_F64_U32_dpp_gfx12
    UINT64_C(2113940730), UINT64_C(0),	// V_CVT_F64_U32_dpp_vi
    UINT64_C(2113940480), UINT64_C(0),	// V_CVT_F64_U32_e32_gfx10
    UINT64_C(2113940480), UINT64_C(0),	// V_CVT_F64_U32_e32_gfx11
    UINT64_C(2113940480), UINT64_C(0),	// V_CVT_F64_U32_e32_gfx12
    UINT64_C(2113940480), UINT64_C(0),	// V_CVT_F64_U32_e32_gfx6_gfx7
    UINT64_C(2113940480), UINT64_C(0),	// V_CVT_F64_U32_e32_vi
    UINT64_C(1077325201408), UINT64_C(0),	// V_CVT_F64_U32_e64_dpp_gfx12
    UINT64_C(3583377408), UINT64_C(0),	// V_CVT_F64_U32_e64_gfx10
    UINT64_C(3583377408), UINT64_C(0),	// V_CVT_F64_U32_e64_gfx11
    UINT64_C(3583377408), UINT64_C(0),	// V_CVT_F64_U32_e64_gfx12
    UINT64_C(3542876160), UINT64_C(0),	// V_CVT_F64_U32_e64_gfx6_gfx7
    UINT64_C(3512074240), UINT64_C(0),	// V_CVT_F64_U32_e64_vi
    UINT64_C(2113935872), UINT64_C(0),	// V_CVT_FLOOR_I32_F32_dpp8_gfx11
    UINT64_C(2113935872), UINT64_C(0),	// V_CVT_FLOOR_I32_F32_dpp8_gfx12
    UINT64_C(2113936122), UINT64_C(0),	// V_CVT_FLOOR_I32_F32_dpp_gfx11
    UINT64_C(2113936122), UINT64_C(0),	// V_CVT_FLOOR_I32_F32_dpp_gfx12
    UINT64_C(2113935872), UINT64_C(0),	// V_CVT_FLOOR_I32_F32_e32_gfx11
    UINT64_C(2113935872), UINT64_C(0),	// V_CVT_FLOOR_I32_F32_e32_gfx12
    UINT64_C(3582787584), UINT64_C(0),	// V_CVT_FLOOR_I32_F32_e64_dpp8_gfx11
    UINT64_C(3582787584), UINT64_C(0),	// V_CVT_FLOOR_I32_F32_e64_dpp8_gfx12
    UINT64_C(1077324611584), UINT64_C(0),	// V_CVT_FLOOR_I32_F32_e64_dpp_gfx11
    UINT64_C(1077324611584), UINT64_C(0),	// V_CVT_FLOOR_I32_F32_e64_dpp_gfx12
    UINT64_C(3582787584), UINT64_C(0),	// V_CVT_FLOOR_I32_F32_e64_gfx11
    UINT64_C(3582787584), UINT64_C(0),	// V_CVT_FLOOR_I32_F32_e64_gfx12
    UINT64_C(2113935872), UINT64_C(0),	// V_CVT_FLR_I32_F32_dpp8_gfx10
    UINT64_C(2113936122), UINT64_C(0),	// V_CVT_FLR_I32_F32_dpp_gfx10
    UINT64_C(2113936122), UINT64_C(0),	// V_CVT_FLR_I32_F32_dpp_vi
    UINT64_C(2113935872), UINT64_C(0),	// V_CVT_FLR_I32_F32_e32_gfx10
    UINT64_C(2113935872), UINT64_C(0),	// V_CVT_FLR_I32_F32_e32_gfx6_gfx7
    UINT64_C(2113935872), UINT64_C(0),	// V_CVT_FLR_I32_F32_e32_vi
    UINT64_C(3582787584), UINT64_C(0),	// V_CVT_FLR_I32_F32_e64_gfx10
    UINT64_C(3541696512), UINT64_C(0),	// V_CVT_FLR_I32_F32_e64_gfx6_gfx7
    UINT64_C(3511484416), UINT64_C(0),	// V_CVT_FLR_I32_F32_e64_vi
    UINT64_C(2113936121), UINT64_C(0),	// V_CVT_FLR_I32_F32_sdwa_gfx10
    UINT64_C(2113936121), UINT64_C(0),	// V_CVT_FLR_I32_F32_sdwa_gfx9
    UINT64_C(2113936121), UINT64_C(0),	// V_CVT_FLR_I32_F32_sdwa_vi
    UINT64_C(2113971712), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_fake16_dpp8_gfx11
    UINT64_C(2113971712), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_fake16_dpp8_gfx12
    UINT64_C(2113971962), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_fake16_dpp_gfx11
    UINT64_C(2113971962), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_fake16_dpp_gfx12
    UINT64_C(2113971712), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_fake16_e32_gfx11
    UINT64_C(2113971712), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_fake16_e32_gfx12
    UINT64_C(3587375104), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3587375104), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077329199104), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077329199104), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_fake16_e64_dpp_gfx12
    UINT64_C(3587375104), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_fake16_e64_gfx11
    UINT64_C(3587375104), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_fake16_e64_gfx12
    UINT64_C(2113971712), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_t16_dpp8_gfx11
    UINT64_C(2113971712), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_t16_dpp8_gfx12
    UINT64_C(2113971962), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_t16_dpp_gfx11
    UINT64_C(2113971962), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_t16_dpp_gfx12
    UINT64_C(2113971712), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_t16_e32_gfx11
    UINT64_C(2113971712), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_t16_e32_gfx12
    UINT64_C(3587375104), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_t16_e64_dpp8_gfx11
    UINT64_C(3587375104), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077329199104), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_t16_e64_dpp_gfx11
    UINT64_C(1077329199104), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_t16_e64_dpp_gfx12
    UINT64_C(3587375104), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_t16_e64_gfx11
    UINT64_C(3587375104), UINT64_C(0),	// V_CVT_I16_F16V_CVT_I16_F16_t16_e64_gfx12
    UINT64_C(2113971712), UINT64_C(0),	// V_CVT_I16_F16_dpp8_gfx10
    UINT64_C(2113971962), UINT64_C(0),	// V_CVT_I16_F16_dpp_gfx10
    UINT64_C(2113960186), UINT64_C(0),	// V_CVT_I16_F16_dpp_vi
    UINT64_C(2113971712), UINT64_C(0),	// V_CVT_I16_F16_e32_gfx10
    UINT64_C(2113959936), UINT64_C(0),	// V_CVT_I16_F16_e32_vi
    UINT64_C(3587375104), UINT64_C(0),	// V_CVT_I16_F16_e64_gfx10
    UINT64_C(3514564608), UINT64_C(0),	// V_CVT_I16_F16_e64_vi
    UINT64_C(2113971961), UINT64_C(0),	// V_CVT_I16_F16_sdwa_gfx10
    UINT64_C(2113960185), UINT64_C(0),	// V_CVT_I16_F16_sdwa_gfx9
    UINT64_C(2113960185), UINT64_C(0),	// V_CVT_I16_F16_sdwa_vi
    UINT64_C(2113933312), UINT64_C(0),	// V_CVT_I32_F32_dpp8_gfx10
    UINT64_C(2113933312), UINT64_C(0),	// V_CVT_I32_F32_dpp8_gfx11
    UINT64_C(2113933312), UINT64_C(0),	// V_CVT_I32_F32_dpp8_gfx12
    UINT64_C(2113933562), UINT64_C(0),	// V_CVT_I32_F32_dpp_gfx10
    UINT64_C(2113933562), UINT64_C(0),	// V_CVT_I32_F32_dpp_gfx11
    UINT64_C(2113933562), UINT64_C(0),	// V_CVT_I32_F32_dpp_gfx12
    UINT64_C(2113933562), UINT64_C(0),	// V_CVT_I32_F32_dpp_vi
    UINT64_C(2113933312), UINT64_C(0),	// V_CVT_I32_F32_e32_gfx10
    UINT64_C(2113933312), UINT64_C(0),	// V_CVT_I32_F32_e32_gfx11
    UINT64_C(2113933312), UINT64_C(0),	// V_CVT_I32_F32_e32_gfx12
    UINT64_C(2113933312), UINT64_C(0),	// V_CVT_I32_F32_e32_gfx6_gfx7
    UINT64_C(2113933312), UINT64_C(0),	// V_CVT_I32_F32_e32_vi
    UINT64_C(3582459904), UINT64_C(0),	// V_CVT_I32_F32_e64_dpp8_gfx11
    UINT64_C(3582459904), UINT64_C(0),	// V_CVT_I32_F32_e64_dpp8_gfx12
    UINT64_C(1077324283904), UINT64_C(0),	// V_CVT_I32_F32_e64_dpp_gfx11
    UINT64_C(1077324283904), UINT64_C(0),	// V_CVT_I32_F32_e64_dpp_gfx12
    UINT64_C(3582459904), UINT64_C(0),	// V_CVT_I32_F32_e64_gfx10
    UINT64_C(3582459904), UINT64_C(0),	// V_CVT_I32_F32_e64_gfx11
    UINT64_C(3582459904), UINT64_C(0),	// V_CVT_I32_F32_e64_gfx12
    UINT64_C(3541041152), UINT64_C(0),	// V_CVT_I32_F32_e64_gfx6_gfx7
    UINT64_C(3511156736), UINT64_C(0),	// V_CVT_I32_F32_e64_vi
    UINT64_C(2113933561), UINT64_C(0),	// V_CVT_I32_F32_sdwa_gfx10
    UINT64_C(2113933561), UINT64_C(0),	// V_CVT_I32_F32_sdwa_gfx9
    UINT64_C(2113933561), UINT64_C(0),	// V_CVT_I32_F32_sdwa_vi
    UINT64_C(2113931002), UINT64_C(0),	// V_CVT_I32_F64_dpp_gfx12
    UINT64_C(2113931002), UINT64_C(0),	// V_CVT_I32_F64_dpp_vi
    UINT64_C(2113930752), UINT64_C(0),	// V_CVT_I32_F64_e32_gfx10
    UINT64_C(2113930752), UINT64_C(0),	// V_CVT_I32_F64_e32_gfx11
    UINT64_C(2113930752), UINT64_C(0),	// V_CVT_I32_F64_e32_gfx12
    UINT64_C(2113930752), UINT64_C(0),	// V_CVT_I32_F64_e32_gfx6_gfx7
    UINT64_C(2113930752), UINT64_C(0),	// V_CVT_I32_F64_e32_vi
    UINT64_C(1077323956224), UINT64_C(0),	// V_CVT_I32_F64_e64_dpp_gfx12
    UINT64_C(3582132224), UINT64_C(0),	// V_CVT_I32_F64_e64_gfx10
    UINT64_C(3582132224), UINT64_C(0),	// V_CVT_I32_F64_e64_gfx11
    UINT64_C(3582132224), UINT64_C(0),	// V_CVT_I32_F64_e64_gfx12
    UINT64_C(3540385792), UINT64_C(0),	// V_CVT_I32_F64_e64_gfx6_gfx7
    UINT64_C(3510829056), UINT64_C(0),	// V_CVT_I32_F64_e64_vi
    UINT64_C(2113983488), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_fake16_dpp8_gfx11
    UINT64_C(2113983488), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_fake16_dpp8_gfx12
    UINT64_C(2113983738), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_fake16_dpp_gfx11
    UINT64_C(2113983738), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_fake16_dpp_gfx12
    UINT64_C(2113983488), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_fake16_e32_gfx11
    UINT64_C(2113983488), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_fake16_e32_gfx12
    UINT64_C(3588882432), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3588882432), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077330706432), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077330706432), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_fake16_e64_dpp_gfx12
    UINT64_C(3588882432), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_fake16_e64_gfx11
    UINT64_C(3588882432), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_fake16_e64_gfx12
    UINT64_C(2113983488), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_t16_dpp8_gfx11
    UINT64_C(2113983488), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_t16_dpp8_gfx12
    UINT64_C(2113983738), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_t16_dpp_gfx11
    UINT64_C(2113983738), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_t16_dpp_gfx12
    UINT64_C(2113983488), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_t16_e32_gfx11
    UINT64_C(2113983488), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_t16_e32_gfx12
    UINT64_C(3588882432), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_t16_e64_dpp8_gfx11
    UINT64_C(3588882432), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077330706432), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_t16_e64_dpp_gfx11
    UINT64_C(1077330706432), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_t16_e64_dpp_gfx12
    UINT64_C(3588882432), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_t16_e64_gfx11
    UINT64_C(3588882432), UINT64_C(0),	// V_CVT_I32_I16V_CVT_I32_I16_t16_e64_gfx12
    UINT64_C(2113935360), UINT64_C(0),	// V_CVT_NEAREST_I32_F32_dpp8_gfx11
    UINT64_C(2113935360), UINT64_C(0),	// V_CVT_NEAREST_I32_F32_dpp8_gfx12
    UINT64_C(2113935610), UINT64_C(0),	// V_CVT_NEAREST_I32_F32_dpp_gfx11
    UINT64_C(2113935610), UINT64_C(0),	// V_CVT_NEAREST_I32_F32_dpp_gfx12
    UINT64_C(2113935360), UINT64_C(0),	// V_CVT_NEAREST_I32_F32_e32_gfx11
    UINT64_C(2113935360), UINT64_C(0),	// V_CVT_NEAREST_I32_F32_e32_gfx12
    UINT64_C(3582722048), UINT64_C(0),	// V_CVT_NEAREST_I32_F32_e64_dpp8_gfx11
    UINT64_C(3582722048), UINT64_C(0),	// V_CVT_NEAREST_I32_F32_e64_dpp8_gfx12
    UINT64_C(1077324546048), UINT64_C(0),	// V_CVT_NEAREST_I32_F32_e64_dpp_gfx11
    UINT64_C(1077324546048), UINT64_C(0),	// V_CVT_NEAREST_I32_F32_e64_dpp_gfx12
    UINT64_C(3582722048), UINT64_C(0),	// V_CVT_NEAREST_I32_F32_e64_gfx11
    UINT64_C(3582722048), UINT64_C(0),	// V_CVT_NEAREST_I32_F32_e64_gfx12
    UINT64_C(2113979904), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_dpp8_gfx11
    UINT64_C(2113979904), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_dpp8_gfx12
    UINT64_C(2113980154), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_dpp_gfx11
    UINT64_C(2113980154), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_dpp_gfx12
    UINT64_C(2113979904), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e32_gfx11
    UINT64_C(2113979904), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e32_gfx12
    UINT64_C(3588423680), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3588423680), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077330247680), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077330247680), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e64_dpp_gfx12
    UINT64_C(3588423680), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e64_gfx11
    UINT64_C(3588423680), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e64_gfx12
    UINT64_C(2113979904), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_dpp8_gfx11
    UINT64_C(2113979904), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_dpp8_gfx12
    UINT64_C(2113980154), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_dpp_gfx11
    UINT64_C(2113980154), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_dpp_gfx12
    UINT64_C(2113979904), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e32_gfx11
    UINT64_C(2113979904), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e32_gfx12
    UINT64_C(3588423680), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e64_dpp8_gfx11
    UINT64_C(3588423680), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077330247680), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e64_dpp_gfx11
    UINT64_C(1077330247680), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e64_dpp_gfx12
    UINT64_C(3588423680), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e64_gfx11
    UINT64_C(3588423680), UINT64_C(0),	// V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e64_gfx12
    UINT64_C(2113979904), UINT64_C(0),	// V_CVT_NORM_I16_F16_dpp8_gfx10
    UINT64_C(2113980154), UINT64_C(0),	// V_CVT_NORM_I16_F16_dpp_gfx10
    UINT64_C(2113968890), UINT64_C(0),	// V_CVT_NORM_I16_F16_dpp_vi
    UINT64_C(2113979904), UINT64_C(0),	// V_CVT_NORM_I16_F16_e32_gfx10
    UINT64_C(2113968640), UINT64_C(0),	// V_CVT_NORM_I16_F16_e32_vi
    UINT64_C(3588423680), UINT64_C(0),	// V_CVT_NORM_I16_F16_e64_gfx10
    UINT64_C(3515678720), UINT64_C(0),	// V_CVT_NORM_I16_F16_e64_vi
    UINT64_C(2113980153), UINT64_C(0),	// V_CVT_NORM_I16_F16_sdwa_gfx10
    UINT64_C(2113968889), UINT64_C(0),	// V_CVT_NORM_I16_F16_sdwa_gfx9
    UINT64_C(2113968889), UINT64_C(0),	// V_CVT_NORM_I16_F16_sdwa_vi
    UINT64_C(2113980416), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_dpp8_gfx11
    UINT64_C(2113980416), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_dpp8_gfx12
    UINT64_C(2113980666), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_dpp_gfx11
    UINT64_C(2113980666), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_dpp_gfx12
    UINT64_C(2113980416), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e32_gfx11
    UINT64_C(2113980416), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e32_gfx12
    UINT64_C(3588489216), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3588489216), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077330313216), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077330313216), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e64_dpp_gfx12
    UINT64_C(3588489216), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e64_gfx11
    UINT64_C(3588489216), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e64_gfx12
    UINT64_C(2113980416), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_dpp8_gfx11
    UINT64_C(2113980416), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_dpp8_gfx12
    UINT64_C(2113980666), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_dpp_gfx11
    UINT64_C(2113980666), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_dpp_gfx12
    UINT64_C(2113980416), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e32_gfx11
    UINT64_C(2113980416), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e32_gfx12
    UINT64_C(3588489216), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e64_dpp8_gfx11
    UINT64_C(3588489216), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077330313216), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e64_dpp_gfx11
    UINT64_C(1077330313216), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e64_dpp_gfx12
    UINT64_C(3588489216), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e64_gfx11
    UINT64_C(3588489216), UINT64_C(0),	// V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e64_gfx12
    UINT64_C(2113980416), UINT64_C(0),	// V_CVT_NORM_U16_F16_dpp8_gfx10
    UINT64_C(2113980666), UINT64_C(0),	// V_CVT_NORM_U16_F16_dpp_gfx10
    UINT64_C(2113969402), UINT64_C(0),	// V_CVT_NORM_U16_F16_dpp_vi
    UINT64_C(2113980416), UINT64_C(0),	// V_CVT_NORM_U16_F16_e32_gfx10
    UINT64_C(2113969152), UINT64_C(0),	// V_CVT_NORM_U16_F16_e32_vi
    UINT64_C(3588489216), UINT64_C(0),	// V_CVT_NORM_U16_F16_e64_gfx10
    UINT64_C(3515744256), UINT64_C(0),	// V_CVT_NORM_U16_F16_e64_vi
    UINT64_C(2113980665), UINT64_C(0),	// V_CVT_NORM_U16_F16_sdwa_gfx10
    UINT64_C(2113969401), UINT64_C(0),	// V_CVT_NORM_U16_F16_sdwa_gfx9
    UINT64_C(2113969401), UINT64_C(0),	// V_CVT_NORM_U16_F16_sdwa_vi
    UINT64_C(2113936384), UINT64_C(0),	// V_CVT_OFF_F32_I4_dpp8_gfx10
    UINT64_C(2113936384), UINT64_C(0),	// V_CVT_OFF_F32_I4_dpp8_gfx11
    UINT64_C(2113936384), UINT64_C(0),	// V_CVT_OFF_F32_I4_dpp8_gfx12
    UINT64_C(2113936634), UINT64_C(0),	// V_CVT_OFF_F32_I4_dpp_gfx10
    UINT64_C(2113936634), UINT64_C(0),	// V_CVT_OFF_F32_I4_dpp_gfx11
    UINT64_C(2113936634), UINT64_C(0),	// V_CVT_OFF_F32_I4_dpp_gfx12
    UINT64_C(2113936634), UINT64_C(0),	// V_CVT_OFF_F32_I4_dpp_vi
    UINT64_C(2113936384), UINT64_C(0),	// V_CVT_OFF_F32_I4_e32_gfx10
    UINT64_C(2113936384), UINT64_C(0),	// V_CVT_OFF_F32_I4_e32_gfx11
    UINT64_C(2113936384), UINT64_C(0),	// V_CVT_OFF_F32_I4_e32_gfx12
    UINT64_C(2113936384), UINT64_C(0),	// V_CVT_OFF_F32_I4_e32_gfx6_gfx7
    UINT64_C(2113936384), UINT64_C(0),	// V_CVT_OFF_F32_I4_e32_vi
    UINT64_C(3582853120), UINT64_C(0),	// V_CVT_OFF_F32_I4_e64_dpp8_gfx11
    UINT64_C(3582853120), UINT64_C(0),	// V_CVT_OFF_F32_I4_e64_dpp8_gfx12
    UINT64_C(1077324677120), UINT64_C(0),	// V_CVT_OFF_F32_I4_e64_dpp_gfx11
    UINT64_C(1077324677120), UINT64_C(0),	// V_CVT_OFF_F32_I4_e64_dpp_gfx12
    UINT64_C(3582853120), UINT64_C(0),	// V_CVT_OFF_F32_I4_e64_gfx10
    UINT64_C(3582853120), UINT64_C(0),	// V_CVT_OFF_F32_I4_e64_gfx11
    UINT64_C(3582853120), UINT64_C(0),	// V_CVT_OFF_F32_I4_e64_gfx12
    UINT64_C(3541827584), UINT64_C(0),	// V_CVT_OFF_F32_I4_e64_gfx6_gfx7
    UINT64_C(3511549952), UINT64_C(0),	// V_CVT_OFF_F32_I4_e64_vi
    UINT64_C(2113936633), UINT64_C(0),	// V_CVT_OFF_F32_I4_sdwa_gfx10
    UINT64_C(2113936633), UINT64_C(0),	// V_CVT_OFF_F32_I4_sdwa_gfx9
    UINT64_C(2113936633), UINT64_C(0),	// V_CVT_OFF_F32_I4_sdwa_vi
    UINT64_C(1476395008), UINT64_C(0),	// V_CVT_PKACCUM_U8_F32_e32_gfx6_gfx7
    UINT64_C(3528982528), UINT64_C(0),	// V_CVT_PKACCUM_U8_F32_e64_gfx6_gfx7
    UINT64_C(3522166784), UINT64_C(0),	// V_CVT_PKACCUM_U8_F32_e64_vi
    UINT64_C(3608281088), UINT64_C(0),	// V_CVT_PKNORM_I16_F16_gfx10
    UINT64_C(3533242368), UINT64_C(0),	// V_CVT_PKNORM_I16_F16_vi
    UINT64_C(1509949440), UINT64_C(0),	// V_CVT_PKNORM_I16_F32_e32_gfx6_gfx7
    UINT64_C(3613917184), UINT64_C(0),	// V_CVT_PKNORM_I16_F32_e64_gfx10
    UINT64_C(3529113600), UINT64_C(0),	// V_CVT_PKNORM_I16_F32_e64_gfx6_gfx7
    UINT64_C(3532914688), UINT64_C(0),	// V_CVT_PKNORM_I16_F32_e64_vi
    UINT64_C(3608346624), UINT64_C(0),	// V_CVT_PKNORM_U16_F16_gfx10
    UINT64_C(3533307904), UINT64_C(0),	// V_CVT_PKNORM_U16_F16_vi
    UINT64_C(1543503872), UINT64_C(0),	// V_CVT_PKNORM_U16_F32_e32_gfx6_gfx7
    UINT64_C(3613982720), UINT64_C(0),	// V_CVT_PKNORM_U16_F32_e64_gfx10
    UINT64_C(3529244672), UINT64_C(0),	// V_CVT_PKNORM_U16_F32_e64_gfx6_gfx7
    UINT64_C(3532980224), UINT64_C(0),	// V_CVT_PKNORM_U16_F32_e64_vi
    UINT64_C(1577058304), UINT64_C(0),	// V_CVT_PKRTZ_F16_F32_dpp8_gfx10
    UINT64_C(1577058554), UINT64_C(0),	// V_CVT_PKRTZ_F16_F32_dpp_gfx10
    UINT64_C(1577058304), UINT64_C(0),	// V_CVT_PKRTZ_F16_F32_e32_gfx10
    UINT64_C(1577058304), UINT64_C(0),	// V_CVT_PKRTZ_F16_F32_e32_gfx6_gfx7
    UINT64_C(3576627200), UINT64_C(0),	// V_CVT_PKRTZ_F16_F32_e64_gfx10
    UINT64_C(3529375744), UINT64_C(0),	// V_CVT_PKRTZ_F16_F32_e64_gfx6_gfx7
    UINT64_C(3533045760), UINT64_C(0),	// V_CVT_PKRTZ_F16_F32_e64_vi
    UINT64_C(1577058553), UINT64_C(0),	// V_CVT_PKRTZ_F16_F32_sdwa_gfx10
    UINT64_C(3614244864), UINT64_C(0),	// V_CVT_PK_BF16_F32_e64_dpp8_gfx1250
    UINT64_C(1077356068864), UINT64_C(0),	// V_CVT_PK_BF16_F32_e64_dpp_gfx1250
    UINT64_C(3614244864), UINT64_C(0),	// V_CVT_PK_BF16_F32_e64_gfx1250
    UINT64_C(3530031104), UINT64_C(0),	// V_CVT_PK_BF16_F32_vi
    UINT64_C(3614638080), UINT64_C(0),	// V_CVT_PK_BF8_F16_gfx1250_fake16_e64_dpp8_gfx1250
    UINT64_C(1077356462080), UINT64_C(0),	// V_CVT_PK_BF8_F16_gfx1250_fake16_e64_dpp_gfx1250
    UINT64_C(3614638080), UINT64_C(0),	// V_CVT_PK_BF8_F16_gfx1250_fake16_e64_gfx1250
    UINT64_C(3614638080), UINT64_C(0),	// V_CVT_PK_BF8_F16_gfx1250_t16_e64_dpp8_gfx1250
    UINT64_C(1077356462080), UINT64_C(0),	// V_CVT_PK_BF8_F16_gfx1250_t16_e64_dpp_gfx1250
    UINT64_C(3614638080), UINT64_C(0),	// V_CVT_PK_BF8_F16_gfx1250_t16_e64_gfx1250
    UINT64_C(3614048256), UINT64_C(0),	// V_CVT_PK_BF8_F32_fake16_e64_dpp8_gfx11
    UINT64_C(3614048256), UINT64_C(0),	// V_CVT_PK_BF8_F32_fake16_e64_dpp8_gfx12
    UINT64_C(1077355872256), UINT64_C(0),	// V_CVT_PK_BF8_F32_fake16_e64_dpp_gfx11
    UINT64_C(1077355872256), UINT64_C(0),	// V_CVT_PK_BF8_F32_fake16_e64_dpp_gfx12
    UINT64_C(3614048256), UINT64_C(0),	// V_CVT_PK_BF8_F32_fake16_e64_gfx11
    UINT64_C(3614048256), UINT64_C(0),	// V_CVT_PK_BF8_F32_fake16_e64_gfx12
    UINT64_C(3614048256), UINT64_C(0),	// V_CVT_PK_BF8_F32_t16_e64_dpp8_gfx11
    UINT64_C(3614048256), UINT64_C(0),	// V_CVT_PK_BF8_F32_t16_e64_dpp8_gfx12
    UINT64_C(1077355872256), UINT64_C(0),	// V_CVT_PK_BF8_F32_t16_e64_dpp_gfx11
    UINT64_C(1077355872256), UINT64_C(0),	// V_CVT_PK_BF8_F32_t16_e64_dpp_gfx12
    UINT64_C(3614048256), UINT64_C(0),	// V_CVT_PK_BF8_F32_t16_e64_gfx11
    UINT64_C(3614048256), UINT64_C(0),	// V_CVT_PK_BF8_F32_t16_e64_gfx12
    UINT64_C(3533897728), UINT64_C(0),	// V_CVT_PK_BF8_F32_vi
    UINT64_C(2113989632), UINT64_C(0),	// V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_fake16_dpp8_gfx1250
    UINT64_C(2113989882), UINT64_C(0),	// V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_fake16_dpp_gfx1250
    UINT64_C(2113989632), UINT64_C(0),	// V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_fake16_e32_gfx1250
    UINT64_C(3589668864), UINT64_C(0),	// V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_fake16_e64_dpp8_gfx1250
    UINT64_C(1077331492864), UINT64_C(0),	// V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_fake16_e64_dpp_gfx1250
    UINT64_C(3589668864), UINT64_C(0),	// V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_fake16_e64_gfx1250
    UINT64_C(2113989632), UINT64_C(0),	// V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_t16_dpp8_gfx1250
    UINT64_C(2113989882), UINT64_C(0),	// V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_t16_dpp_gfx1250
    UINT64_C(2113989632), UINT64_C(0),	// V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_t16_e32_gfx1250
    UINT64_C(3589668864), UINT64_C(0),	// V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_t16_e64_dpp8_gfx1250
    UINT64_C(1077331492864), UINT64_C(0),	// V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_t16_e64_dpp_gfx1250
    UINT64_C(3589668864), UINT64_C(0),	// V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_t16_e64_gfx1250
    UINT64_C(3614375936), UINT64_C(0),	// V_CVT_PK_F16_F32_e64_dpp8_gfx1250
    UINT64_C(1077356199936), UINT64_C(0),	// V_CVT_PK_F16_F32_e64_dpp_gfx1250
    UINT64_C(3614375936), UINT64_C(0),	// V_CVT_PK_F16_F32_e64_gfx1250
    UINT64_C(3529965568), UINT64_C(0),	// V_CVT_PK_F16_F32_gfx9
    UINT64_C(2113989120), UINT64_C(0),	// V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_fake16_dpp8_gfx1250
    UINT64_C(2113989370), UINT64_C(0),	// V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_fake16_dpp_gfx1250
    UINT64_C(2113989120), UINT64_C(0),	// V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_fake16_e32_gfx1250
    UINT64_C(3589603328), UINT64_C(0),	// V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_fake16_e64_dpp8_gfx1250
    UINT64_C(1077331427328), UINT64_C(0),	// V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_fake16_e64_dpp_gfx1250
    UINT64_C(3589603328), UINT64_C(0),	// V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_fake16_e64_gfx1250
    UINT64_C(2113989120), UINT64_C(0),	// V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_t16_dpp8_gfx1250
    UINT64_C(2113989370), UINT64_C(0),	// V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_t16_dpp_gfx1250
    UINT64_C(2113989120), UINT64_C(0),	// V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_t16_e32_gfx1250
    UINT64_C(3589603328), UINT64_C(0),	// V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_t16_e64_dpp8_gfx1250
    UINT64_C(1077331427328), UINT64_C(0),	// V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_t16_e64_dpp_gfx1250
    UINT64_C(3589603328), UINT64_C(0),	// V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_t16_e64_gfx1250
    UINT64_C(2113974010), UINT64_C(0),	// V_CVT_PK_F32_BF8_dpp_gfx9
    UINT64_C(2113973760), UINT64_C(0),	// V_CVT_PK_F32_BF8_e32_vi
    UINT64_C(3516334080), UINT64_C(0),	// V_CVT_PK_F32_BF8_e64_vi
    UINT64_C(2113986048), UINT64_C(0),	// V_CVT_PK_F32_BF8_fake16_e32_gfx12
    UINT64_C(3589210112), UINT64_C(0),	// V_CVT_PK_F32_BF8_fake16_e64_gfx12
    UINT64_C(6599183740665), UINT64_C(0),	// V_CVT_PK_F32_BF8_sdwa_gfx9
    UINT64_C(2113986048), UINT64_C(0),	// V_CVT_PK_F32_BF8_t16_e32_gfx12
    UINT64_C(3589210112), UINT64_C(0),	// V_CVT_PK_F32_BF8_t16_e64_gfx12
    UINT64_C(2113973498), UINT64_C(0),	// V_CVT_PK_F32_FP8_dpp_gfx9
    UINT64_C(2113973248), UINT64_C(0),	// V_CVT_PK_F32_FP8_e32_vi
    UINT64_C(3516268544), UINT64_C(0),	// V_CVT_PK_F32_FP8_e64_vi
    UINT64_C(2113985536), UINT64_C(0),	// V_CVT_PK_F32_FP8_fake16_e32_gfx12
    UINT64_C(3589144576), UINT64_C(0),	// V_CVT_PK_F32_FP8_fake16_e64_gfx12
    UINT64_C(6599183740153), UINT64_C(0),	// V_CVT_PK_F32_FP8_sdwa_gfx9
    UINT64_C(2113985536), UINT64_C(0),	// V_CVT_PK_F32_FP8_t16_e32_gfx12
    UINT64_C(3589144576), UINT64_C(0),	// V_CVT_PK_F32_FP8_t16_e64_gfx12
    UINT64_C(3614572544), UINT64_C(0),	// V_CVT_PK_FP8_F16_gfx1250_fake16_e64_dpp8_gfx1250
    UINT64_C(1077356396544), UINT64_C(0),	// V_CVT_PK_FP8_F16_gfx1250_fake16_e64_dpp_gfx1250
    UINT64_C(3614572544), UINT64_C(0),	// V_CVT_PK_FP8_F16_gfx1250_fake16_e64_gfx1250
    UINT64_C(3614572544), UINT64_C(0),	// V_CVT_PK_FP8_F16_gfx1250_t16_e64_dpp8_gfx1250
    UINT64_C(1077356396544), UINT64_C(0),	// V_CVT_PK_FP8_F16_gfx1250_t16_e64_dpp_gfx1250
    UINT64_C(3614572544), UINT64_C(0),	// V_CVT_PK_FP8_F16_gfx1250_t16_e64_gfx1250
    UINT64_C(3613982720), UINT64_C(0),	// V_CVT_PK_FP8_F32_fake16_e64_dpp8_gfx11
    UINT64_C(3613982720), UINT64_C(0),	// V_CVT_PK_FP8_F32_fake16_e64_dpp8_gfx12
    UINT64_C(1077355806720), UINT64_C(0),	// V_CVT_PK_FP8_F32_fake16_e64_dpp_gfx11
    UINT64_C(1077355806720), UINT64_C(0),	// V_CVT_PK_FP8_F32_fake16_e64_dpp_gfx12
    UINT64_C(3613982720), UINT64_C(0),	// V_CVT_PK_FP8_F32_fake16_e64_gfx11
    UINT64_C(3613982720), UINT64_C(0),	// V_CVT_PK_FP8_F32_fake16_e64_gfx12
    UINT64_C(3613982720), UINT64_C(0),	// V_CVT_PK_FP8_F32_gfx1250_fake16_e64_dpp8_gfx1250
    UINT64_C(1077355806720), UINT64_C(0),	// V_CVT_PK_FP8_F32_gfx1250_fake16_e64_dpp_gfx1250
    UINT64_C(3613982720), UINT64_C(0),	// V_CVT_PK_FP8_F32_gfx1250_fake16_e64_gfx1250
    UINT64_C(3613982720), UINT64_C(0),	// V_CVT_PK_FP8_F32_gfx1250_t16_e64_dpp8_gfx1250
    UINT64_C(1077355806720), UINT64_C(0),	// V_CVT_PK_FP8_F32_gfx1250_t16_e64_dpp_gfx1250
    UINT64_C(3613982720), UINT64_C(0),	// V_CVT_PK_FP8_F32_gfx1250_t16_e64_gfx1250
    UINT64_C(3613982720), UINT64_C(0),	// V_CVT_PK_FP8_F32_t16_e64_dpp8_gfx11
    UINT64_C(3613982720), UINT64_C(0),	// V_CVT_PK_FP8_F32_t16_e64_dpp8_gfx12
    UINT64_C(1077355806720), UINT64_C(0),	// V_CVT_PK_FP8_F32_t16_e64_dpp_gfx11
    UINT64_C(1077355806720), UINT64_C(0),	// V_CVT_PK_FP8_F32_t16_e64_dpp_gfx12
    UINT64_C(3613982720), UINT64_C(0),	// V_CVT_PK_FP8_F32_t16_e64_gfx11
    UINT64_C(3613982720), UINT64_C(0),	// V_CVT_PK_FP8_F32_t16_e64_gfx12
    UINT64_C(3533832192), UINT64_C(0),	// V_CVT_PK_FP8_F32_vi
    UINT64_C(3607494656), UINT64_C(0),	// V_CVT_PK_I16_F32_e64_dpp8_gfx11
    UINT64_C(3607494656), UINT64_C(0),	// V_CVT_PK_I16_F32_e64_dpp8_gfx12
    UINT64_C(1077349318656), UINT64_C(0),	// V_CVT_PK_I16_F32_e64_dpp_gfx11
    UINT64_C(1077349318656), UINT64_C(0),	// V_CVT_PK_I16_F32_e64_dpp_gfx12
    UINT64_C(3607494656), UINT64_C(0),	// V_CVT_PK_I16_F32_e64_gfx11
    UINT64_C(3607494656), UINT64_C(0),	// V_CVT_PK_I16_F32_e64_gfx12
    UINT64_C(1644167168), UINT64_C(0),	// V_CVT_PK_I16_I32_e32_gfx6_gfx7
    UINT64_C(3609460736), UINT64_C(0),	// V_CVT_PK_I16_I32_e64_dpp8_gfx11
    UINT64_C(3609460736), UINT64_C(0),	// V_CVT_PK_I16_I32_e64_dpp8_gfx12
    UINT64_C(1077351284736), UINT64_C(0),	// V_CVT_PK_I16_I32_e64_dpp_gfx11
    UINT64_C(1077351284736), UINT64_C(0),	// V_CVT_PK_I16_I32_e64_dpp_gfx12
    UINT64_C(3614113792), UINT64_C(0),	// V_CVT_PK_I16_I32_e64_gfx10
    UINT64_C(3609460736), UINT64_C(0),	// V_CVT_PK_I16_I32_e64_gfx11
    UINT64_C(3609460736), UINT64_C(0),	// V_CVT_PK_I16_I32_e64_gfx12
    UINT64_C(3529637888), UINT64_C(0),	// V_CVT_PK_I16_I32_e64_gfx6_gfx7
    UINT64_C(3533176832), UINT64_C(0),	// V_CVT_PK_I16_I32_e64_vi
    UINT64_C(3608281088), UINT64_C(0),	// V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3608281088), UINT64_C(0),	// V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077350105088), UINT64_C(0),	// V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077350105088), UINT64_C(0),	// V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_fake16_e64_dpp_gfx12
    UINT64_C(3608281088), UINT64_C(0),	// V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_fake16_e64_gfx11
    UINT64_C(3608281088), UINT64_C(0),	// V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_fake16_e64_gfx12
    UINT64_C(3608281088), UINT64_C(0),	// V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_t16_e64_dpp8_gfx11
    UINT64_C(3608281088), UINT64_C(0),	// V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077350105088), UINT64_C(0),	// V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_t16_e64_dpp_gfx11
    UINT64_C(1077350105088), UINT64_C(0),	// V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_t16_e64_dpp_gfx12
    UINT64_C(3608281088), UINT64_C(0),	// V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_t16_e64_gfx11
    UINT64_C(3608281088), UINT64_C(0),	// V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_t16_e64_gfx12
    UINT64_C(3609264128), UINT64_C(0),	// V_CVT_PK_NORM_I16_F32_e64_dpp8_gfx11
    UINT64_C(3609264128), UINT64_C(0),	// V_CVT_PK_NORM_I16_F32_e64_dpp8_gfx12
    UINT64_C(1077351088128), UINT64_C(0),	// V_CVT_PK_NORM_I16_F32_e64_dpp_gfx11
    UINT64_C(1077351088128), UINT64_C(0),	// V_CVT_PK_NORM_I16_F32_e64_dpp_gfx12
    UINT64_C(3609264128), UINT64_C(0),	// V_CVT_PK_NORM_I16_F32_e64_gfx11
    UINT64_C(3609264128), UINT64_C(0),	// V_CVT_PK_NORM_I16_F32_e64_gfx12
    UINT64_C(3608346624), UINT64_C(0),	// V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3608346624), UINT64_C(0),	// V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077350170624), UINT64_C(0),	// V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077350170624), UINT64_C(0),	// V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_fake16_e64_dpp_gfx12
    UINT64_C(3608346624), UINT64_C(0),	// V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_fake16_e64_gfx11
    UINT64_C(3608346624), UINT64_C(0),	// V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_fake16_e64_gfx12
    UINT64_C(3608346624), UINT64_C(0),	// V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_t16_e64_dpp8_gfx11
    UINT64_C(3608346624), UINT64_C(0),	// V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077350170624), UINT64_C(0),	// V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_t16_e64_dpp_gfx11
    UINT64_C(1077350170624), UINT64_C(0),	// V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_t16_e64_dpp_gfx12
    UINT64_C(3608346624), UINT64_C(0),	// V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_t16_e64_gfx11
    UINT64_C(3608346624), UINT64_C(0),	// V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_t16_e64_gfx12
    UINT64_C(3609329664), UINT64_C(0),	// V_CVT_PK_NORM_U16_F32_e64_dpp8_gfx11
    UINT64_C(3609329664), UINT64_C(0),	// V_CVT_PK_NORM_U16_F32_e64_dpp8_gfx12
    UINT64_C(1077351153664), UINT64_C(0),	// V_CVT_PK_NORM_U16_F32_e64_dpp_gfx11
    UINT64_C(1077351153664), UINT64_C(0),	// V_CVT_PK_NORM_U16_F32_e64_dpp_gfx12
    UINT64_C(3609329664), UINT64_C(0),	// V_CVT_PK_NORM_U16_F32_e64_gfx11
    UINT64_C(3609329664), UINT64_C(0),	// V_CVT_PK_NORM_U16_F32_e64_gfx12
    UINT64_C(1577058304), UINT64_C(0),	// V_CVT_PK_RTZ_F16_F32_dpp8_gfx11
    UINT64_C(1577058304), UINT64_C(0),	// V_CVT_PK_RTZ_F16_F32_dpp8_gfx12
    UINT64_C(1577058554), UINT64_C(0),	// V_CVT_PK_RTZ_F16_F32_dpp_gfx11
    UINT64_C(1577058554), UINT64_C(0),	// V_CVT_PK_RTZ_F16_F32_dpp_gfx12
    UINT64_C(1577058304), UINT64_C(0),	// V_CVT_PK_RTZ_F16_F32_e32_gfx11
    UINT64_C(1577058304), UINT64_C(0),	// V_CVT_PK_RTZ_F16_F32_e32_gfx12
    UINT64_C(3576627200), UINT64_C(0),	// V_CVT_PK_RTZ_F16_F32_e64_dpp8_gfx11
    UINT64_C(3576627200), UINT64_C(0),	// V_CVT_PK_RTZ_F16_F32_e64_dpp8_gfx12
    UINT64_C(1077318451200), UINT64_C(0),	// V_CVT_PK_RTZ_F16_F32_e64_dpp_gfx11
    UINT64_C(1077318451200), UINT64_C(0),	// V_CVT_PK_RTZ_F16_F32_e64_dpp_gfx12
    UINT64_C(3576627200), UINT64_C(0),	// V_CVT_PK_RTZ_F16_F32_e64_gfx11
    UINT64_C(3576627200), UINT64_C(0),	// V_CVT_PK_RTZ_F16_F32_e64_gfx12
    UINT64_C(3607560192), UINT64_C(0),	// V_CVT_PK_U16_F32_e64_dpp8_gfx11
    UINT64_C(3607560192), UINT64_C(0),	// V_CVT_PK_U16_F32_e64_dpp8_gfx12
    UINT64_C(1077349384192), UINT64_C(0),	// V_CVT_PK_U16_F32_e64_dpp_gfx11
    UINT64_C(1077349384192), UINT64_C(0),	// V_CVT_PK_U16_F32_e64_dpp_gfx12
    UINT64_C(3607560192), UINT64_C(0),	// V_CVT_PK_U16_F32_e64_gfx11
    UINT64_C(3607560192), UINT64_C(0),	// V_CVT_PK_U16_F32_e64_gfx12
    UINT64_C(1610612736), UINT64_C(0),	// V_CVT_PK_U16_U32_e32_gfx6_gfx7
    UINT64_C(3609395200), UINT64_C(0),	// V_CVT_PK_U16_U32_e64_dpp8_gfx11
    UINT64_C(3609395200), UINT64_C(0),	// V_CVT_PK_U16_U32_e64_dpp8_gfx12
    UINT64_C(1077351219200), UINT64_C(0),	// V_CVT_PK_U16_U32_e64_dpp_gfx11
    UINT64_C(1077351219200), UINT64_C(0),	// V_CVT_PK_U16_U32_e64_dpp_gfx12
    UINT64_C(3614048256), UINT64_C(0),	// V_CVT_PK_U16_U32_e64_gfx10
    UINT64_C(3609395200), UINT64_C(0),	// V_CVT_PK_U16_U32_e64_gfx11
    UINT64_C(3609395200), UINT64_C(0),	// V_CVT_PK_U16_U32_e64_gfx12
    UINT64_C(3529506816), UINT64_C(0),	// V_CVT_PK_U16_U32_e64_gfx6_gfx7
    UINT64_C(3533111296), UINT64_C(0),	// V_CVT_PK_U16_U32_e64_vi
    UINT64_C(3592814592), UINT64_C(0),	// V_CVT_PK_U8_F32_e64_dpp8_gfx11
    UINT64_C(3592814592), UINT64_C(0),	// V_CVT_PK_U8_F32_e64_dpp8_gfx12
    UINT64_C(1077334638592), UINT64_C(0),	// V_CVT_PK_U8_F32_e64_dpp_gfx11
    UINT64_C(1077334638592), UINT64_C(0),	// V_CVT_PK_U8_F32_e64_dpp_gfx12
    UINT64_C(3592814592), UINT64_C(0),	// V_CVT_PK_U8_F32_e64_gfx11
    UINT64_C(3592814592), UINT64_C(0),	// V_CVT_PK_U8_F32_e64_gfx12
    UINT64_C(3579707392), UINT64_C(0),	// V_CVT_PK_U8_F32_gfx10
    UINT64_C(3535536128), UINT64_C(0),	// V_CVT_PK_U8_F32_gfx6_gfx7
    UINT64_C(3520921600), UINT64_C(0),	// V_CVT_PK_U8_F32_vi
    UINT64_C(2113935360), UINT64_C(0),	// V_CVT_RPI_I32_F32_dpp8_gfx10
    UINT64_C(2113935610), UINT64_C(0),	// V_CVT_RPI_I32_F32_dpp_gfx10
    UINT64_C(2113935610), UINT64_C(0),	// V_CVT_RPI_I32_F32_dpp_vi
    UINT64_C(2113935360), UINT64_C(0),	// V_CVT_RPI_I32_F32_e32_gfx10
    UINT64_C(2113935360), UINT64_C(0),	// V_CVT_RPI_I32_F32_e32_gfx6_gfx7
    UINT64_C(2113935360), UINT64_C(0),	// V_CVT_RPI_I32_F32_e32_vi
    UINT64_C(3582722048), UINT64_C(0),	// V_CVT_RPI_I32_F32_e64_gfx10
    UINT64_C(3541565440), UINT64_C(0),	// V_CVT_RPI_I32_F32_e64_gfx6_gfx7
    UINT64_C(3511418880), UINT64_C(0),	// V_CVT_RPI_I32_F32_e64_vi
    UINT64_C(2113935609), UINT64_C(0),	// V_CVT_RPI_I32_F32_sdwa_gfx10
    UINT64_C(2113935609), UINT64_C(0),	// V_CVT_RPI_I32_F32_sdwa_gfx9
    UINT64_C(2113935609), UINT64_C(0),	// V_CVT_RPI_I32_F32_sdwa_vi
    UINT64_C(3528654848), UINT64_C(0),	// V_CVT_SCALEF32_2XPK16_BF6_F32_gfx9
    UINT64_C(3528589312), UINT64_C(0),	// V_CVT_SCALEF32_2XPK16_FP6_F32_gfx9
    UINT64_C(3528130560), UINT64_C(0),	// V_CVT_SCALEF32_F16_BF8_vi
    UINT64_C(3528065024), UINT64_C(0),	// V_CVT_SCALEF32_F16_FP8_vi
    UINT64_C(3527147520), UINT64_C(0),	// V_CVT_SCALEF32_F32_BF8_vi
    UINT64_C(3527081984), UINT64_C(0),	// V_CVT_SCALEF32_F32_FP8_vi
    UINT64_C(3604086784), UINT64_C(0),	// V_CVT_SCALEF32_PK16_BF6_BF16_e64_gfx1250
    UINT64_C(3603955712), UINT64_C(0),	// V_CVT_SCALEF32_PK16_BF6_F16_e64_gfx1250
    UINT64_C(3603824640), UINT64_C(0),	// V_CVT_SCALEF32_PK16_BF6_F32_e64_gfx1250
    UINT64_C(3604021248), UINT64_C(0),	// V_CVT_SCALEF32_PK16_FP6_BF16_e64_gfx1250
    UINT64_C(3603890176), UINT64_C(0),	// V_CVT_SCALEF32_PK16_FP6_F16_e64_gfx1250
    UINT64_C(3603759104), UINT64_C(0),	// V_CVT_SCALEF32_PK16_FP6_F32_e64_gfx1250
    UINT64_C(3529703424), UINT64_C(0),	// V_CVT_SCALEF32_PK32_BF16_BF6_gfx9
    UINT64_C(3529572352), UINT64_C(0),	// V_CVT_SCALEF32_PK32_BF16_FP6_gfx9
    UINT64_C(3529179136), UINT64_C(0),	// V_CVT_SCALEF32_PK32_BF6_BF16_gfx9
    UINT64_C(3529113600), UINT64_C(0),	// V_CVT_SCALEF32_PK32_BF6_F16_gfx9
    UINT64_C(3529637888), UINT64_C(0),	// V_CVT_SCALEF32_PK32_F16_BF6_gfx9
    UINT64_C(3529506816), UINT64_C(0),	// V_CVT_SCALEF32_PK32_F16_FP6_gfx9
    UINT64_C(3528916992), UINT64_C(0),	// V_CVT_SCALEF32_PK32_F32_BF6_gfx9
    UINT64_C(3528851456), UINT64_C(0),	// V_CVT_SCALEF32_PK32_F32_FP6_gfx9
    UINT64_C(3529048064), UINT64_C(0),	// V_CVT_SCALEF32_PK32_FP6_BF16_gfx9
    UINT64_C(3528982528), UINT64_C(0),	// V_CVT_SCALEF32_PK32_FP6_F16_gfx9
    UINT64_C(3602186240), UINT64_C(0),	// V_CVT_SCALEF32_PK8_BF8_BF16_e64_gfx1250
    UINT64_C(3603300352), UINT64_C(0),	// V_CVT_SCALEF32_PK8_BF8_F16_e64_gfx1250
    UINT64_C(3603234816), UINT64_C(0),	// V_CVT_SCALEF32_PK8_BF8_F32_e64_gfx1250
    UINT64_C(3602382848), UINT64_C(0),	// V_CVT_SCALEF32_PK8_FP4_BF16_e64_gfx1250
    UINT64_C(3602055168), UINT64_C(0),	// V_CVT_SCALEF32_PK8_FP4_F16_e64_gfx1250
    UINT64_C(3601858560), UINT64_C(0),	// V_CVT_SCALEF32_PK8_FP4_F32_e64_gfx1250
    UINT64_C(3602120704), UINT64_C(0),	// V_CVT_SCALEF32_PK8_FP8_BF16_e64_gfx1250
    UINT64_C(3603169280), UINT64_C(0),	// V_CVT_SCALEF32_PK8_FP8_F16_e64_gfx1250
    UINT64_C(3603103744), UINT64_C(0),	// V_CVT_SCALEF32_PK8_FP8_F32_e64_gfx1250
    UINT64_C(3530162176), UINT64_C(0),	// V_CVT_SCALEF32_PK_BF16_BF8_vi
    UINT64_C(3528523776), UINT64_C(0),	// V_CVT_SCALEF32_PK_BF16_FP4_vi
    UINT64_C(3530096640), UINT64_C(0),	// V_CVT_SCALEF32_PK_BF16_FP8_vi
    UINT64_C(3527737344), UINT64_C(0),	// V_CVT_SCALEF32_PK_BF8_BF16_vi
    UINT64_C(3527475200), UINT64_C(0),	// V_CVT_SCALEF32_PK_BF8_F16_vi
    UINT64_C(3526754304), UINT64_C(0),	// V_CVT_SCALEF32_PK_BF8_F32_vi
    UINT64_C(3527999488), UINT64_C(0),	// V_CVT_SCALEF32_PK_F16_BF8_vi
    UINT64_C(3528458240), UINT64_C(0),	// V_CVT_SCALEF32_PK_F16_FP4_vi
    UINT64_C(3527933952), UINT64_C(0),	// V_CVT_SCALEF32_PK_F16_FP8_vi
    UINT64_C(3527016448), UINT64_C(0),	// V_CVT_SCALEF32_PK_F32_BF8_vi
    UINT64_C(3527344128), UINT64_C(0),	// V_CVT_SCALEF32_PK_F32_FP4_vi
    UINT64_C(3526950912), UINT64_C(0),	// V_CVT_SCALEF32_PK_F32_FP8_vi
    UINT64_C(3528261632), UINT64_C(0),	// V_CVT_SCALEF32_PK_FP4_BF16_vi
    UINT64_C(3528196096), UINT64_C(0),	// V_CVT_SCALEF32_PK_FP4_F16_vi
    UINT64_C(3527213056), UINT64_C(0),	// V_CVT_SCALEF32_PK_FP4_F32_vi
    UINT64_C(3527671808), UINT64_C(0),	// V_CVT_SCALEF32_PK_FP8_BF16_vi
    UINT64_C(3527409664), UINT64_C(0),	// V_CVT_SCALEF32_PK_FP8_F16_vi
    UINT64_C(3526688768), UINT64_C(0),	// V_CVT_SCALEF32_PK_FP8_F32_vi
    UINT64_C(3527868416), UINT64_C(0),	// V_CVT_SCALEF32_SR_BF8_BF16_vi
    UINT64_C(3527606272), UINT64_C(0),	// V_CVT_SCALEF32_SR_BF8_F16_vi
    UINT64_C(3526885376), UINT64_C(0),	// V_CVT_SCALEF32_SR_BF8_F32_vi
    UINT64_C(3527802880), UINT64_C(0),	// V_CVT_SCALEF32_SR_FP8_BF16_vi
    UINT64_C(3527540736), UINT64_C(0),	// V_CVT_SCALEF32_SR_FP8_F16_vi
    UINT64_C(3526819840), UINT64_C(0),	// V_CVT_SCALEF32_SR_FP8_F32_vi
    UINT64_C(3604480000), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK16_BF6_BF16_e64_gfx1250
    UINT64_C(3604348928), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK16_BF6_F16_e64_gfx1250
    UINT64_C(3604217856), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK16_BF6_F32_e64_gfx1250
    UINT64_C(3604414464), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK16_FP6_BF16_e64_gfx1250
    UINT64_C(3604283392), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK16_FP6_F16_e64_gfx1250
    UINT64_C(3604152320), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK16_FP6_F32_e64_gfx1250
    UINT64_C(3529441280), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK32_BF6_BF16_gfx9
    UINT64_C(3529375744), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK32_BF6_F16_gfx9
    UINT64_C(3528785920), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK32_BF6_F32_gfx9
    UINT64_C(3529310208), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK32_FP6_BF16_gfx9
    UINT64_C(3529244672), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK32_FP6_F16_gfx9
    UINT64_C(3528720384), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK32_FP6_F32_gfx9
    UINT64_C(3603038208), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK8_BF8_BF16_e64_gfx1250
    UINT64_C(3602972672), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK8_BF8_F16_e64_gfx1250
    UINT64_C(3600351232), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK8_BF8_F32_e64_gfx1250
    UINT64_C(3602644992), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK8_FP4_BF16_e64_gfx1250
    UINT64_C(3602448384), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK8_FP4_F16_e64_gfx1250
    UINT64_C(3600220160), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK8_FP4_F32_e64_gfx1250
    UINT64_C(3602907136), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK8_FP8_BF16_e64_gfx1250
    UINT64_C(3602841600), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK8_FP8_F16_e64_gfx1250
    UINT64_C(3600285696), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK8_FP8_F32_e64_gfx1250
    UINT64_C(3528392704), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK_FP4_BF16_vi
    UINT64_C(3528327168), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK_FP4_F16_vi
    UINT64_C(3527278592), UINT64_C(0),	// V_CVT_SCALEF32_SR_PK_FP4_F32_vi
    UINT64_C(3603628032), UINT64_C(0),	// V_CVT_SCALE_PK16_BF16_BF6_e64_gfx1250
    UINT64_C(3603431424), UINT64_C(0),	// V_CVT_SCALE_PK16_BF16_FP6_e64_gfx1250
    UINT64_C(3603562496), UINT64_C(0),	// V_CVT_SCALE_PK16_F16_BF6_e64_gfx1250
    UINT64_C(3603365888), UINT64_C(0),	// V_CVT_SCALE_PK16_F16_FP6_e64_gfx1250
    UINT64_C(3603693568), UINT64_C(0),	// V_CVT_SCALE_PK16_F32_BF6_e64_gfx1250
    UINT64_C(3603496960), UINT64_C(0),	// V_CVT_SCALE_PK16_F32_FP6_e64_gfx1250
    UINT64_C(3601596416), UINT64_C(0),	// V_CVT_SCALE_PK8_BF16_BF8_e64_gfx1250
    UINT64_C(3600809984), UINT64_C(0),	// V_CVT_SCALE_PK8_BF16_FP4_e64_gfx1250
    UINT64_C(3601399808), UINT64_C(0),	// V_CVT_SCALE_PK8_BF16_FP8_e64_gfx1250
    UINT64_C(3601530880), UINT64_C(0),	// V_CVT_SCALE_PK8_F16_BF8_e64_gfx1250
    UINT64_C(3600744448), UINT64_C(0),	// V_CVT_SCALE_PK8_F16_FP4_e64_gfx1250
    UINT64_C(3601334272), UINT64_C(0),	// V_CVT_SCALE_PK8_F16_FP8_e64_gfx1250
    UINT64_C(3601661952), UINT64_C(0),	// V_CVT_SCALE_PK8_F32_BF8_e64_gfx1250
    UINT64_C(3600875520), UINT64_C(0),	// V_CVT_SCALE_PK8_F32_FP4_e64_gfx1250
    UINT64_C(3601465344), UINT64_C(0),	// V_CVT_SCALE_PK8_F32_FP8_e64_gfx1250
    UINT64_C(3534159872), UINT64_C(0),	// V_CVT_SR_BF16_F32_vi
    UINT64_C(3614769152), UINT64_C(0),	// V_CVT_SR_BF8_F16_fake16_e64_dpp8_gfx1250
    UINT64_C(1077356593152), UINT64_C(0),	// V_CVT_SR_BF8_F16_fake16_e64_dpp_gfx1250
    UINT64_C(3614769152), UINT64_C(0),	// V_CVT_SR_BF8_F16_fake16_e64_gfx1250
    UINT64_C(3614769152), UINT64_C(0),	// V_CVT_SR_BF8_F16_t16_e64_dpp8_gfx1250
    UINT64_C(1077356593152), UINT64_C(0),	// V_CVT_SR_BF8_F16_t16_e64_dpp_gfx1250
    UINT64_C(3614769152), UINT64_C(0),	// V_CVT_SR_BF8_F16_t16_e64_gfx1250
    UINT64_C(3614179328), UINT64_C(0),	// V_CVT_SR_BF8_F32_gfx12_e64_dpp8_gfx11
    UINT64_C(3614179328), UINT64_C(0),	// V_CVT_SR_BF8_F32_gfx12_e64_dpp8_gfx12
    UINT64_C(1077356003328), UINT64_C(0),	// V_CVT_SR_BF8_F32_gfx12_e64_dpp_gfx11
    UINT64_C(1077356003328), UINT64_C(0),	// V_CVT_SR_BF8_F32_gfx12_e64_dpp_gfx12
    UINT64_C(3614179328), UINT64_C(0),	// V_CVT_SR_BF8_F32_gfx12_e64_gfx11
    UINT64_C(3614179328), UINT64_C(0),	// V_CVT_SR_BF8_F32_gfx12_e64_gfx12
    UINT64_C(3534028800), UINT64_C(0),	// V_CVT_SR_BF8_F32_vi
    UINT64_C(3534094336), UINT64_C(0),	// V_CVT_SR_F16_F32_vi
    UINT64_C(3614703616), UINT64_C(0),	// V_CVT_SR_FP8_F16_fake16_e64_dpp8_gfx1250
    UINT64_C(1077356527616), UINT64_C(0),	// V_CVT_SR_FP8_F16_fake16_e64_dpp_gfx1250
    UINT64_C(3614703616), UINT64_C(0),	// V_CVT_SR_FP8_F16_fake16_e64_gfx1250
    UINT64_C(3614703616), UINT64_C(0),	// V_CVT_SR_FP8_F16_t16_e64_dpp8_gfx1250
    UINT64_C(1077356527616), UINT64_C(0),	// V_CVT_SR_FP8_F16_t16_e64_dpp_gfx1250
    UINT64_C(3614703616), UINT64_C(0),	// V_CVT_SR_FP8_F16_t16_e64_gfx1250
    UINT64_C(3614113792), UINT64_C(0),	// V_CVT_SR_FP8_F32_gfx1250_e64_dpp8_gfx1250
    UINT64_C(1077355937792), UINT64_C(0),	// V_CVT_SR_FP8_F32_gfx1250_e64_dpp_gfx1250
    UINT64_C(3614113792), UINT64_C(0),	// V_CVT_SR_FP8_F32_gfx1250_e64_gfx1250
    UINT64_C(3614113792), UINT64_C(0),	// V_CVT_SR_FP8_F32_gfx12_e64_dpp8_gfx11
    UINT64_C(3614113792), UINT64_C(0),	// V_CVT_SR_FP8_F32_gfx12_e64_dpp8_gfx12
    UINT64_C(1077355937792), UINT64_C(0),	// V_CVT_SR_FP8_F32_gfx12_e64_dpp_gfx11
    UINT64_C(1077355937792), UINT64_C(0),	// V_CVT_SR_FP8_F32_gfx12_e64_dpp_gfx12
    UINT64_C(3614113792), UINT64_C(0),	// V_CVT_SR_FP8_F32_gfx12_e64_gfx11
    UINT64_C(3614113792), UINT64_C(0),	// V_CVT_SR_FP8_F32_gfx12_e64_gfx12
    UINT64_C(3533963264), UINT64_C(0),	// V_CVT_SR_FP8_F32_vi
    UINT64_C(3614310400), UINT64_C(0),	// V_CVT_SR_PK_BF16_F32_e64_dpp8_gfx1250
    UINT64_C(1077356134400), UINT64_C(0),	// V_CVT_SR_PK_BF16_F32_e64_dpp_gfx1250
    UINT64_C(3614310400), UINT64_C(0),	// V_CVT_SR_PK_BF16_F32_e64_gfx1250
    UINT64_C(3614441472), UINT64_C(0),	// V_CVT_SR_PK_F16_F32_e64_dpp8_gfx1250
    UINT64_C(1077356265472), UINT64_C(0),	// V_CVT_SR_PK_F16_F32_e64_dpp_gfx1250
    UINT64_C(3614441472), UINT64_C(0),	// V_CVT_SR_PK_F16_F32_e64_gfx1250
    UINT64_C(2113971200), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_fake16_dpp8_gfx11
    UINT64_C(2113971200), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_fake16_dpp8_gfx12
    UINT64_C(2113971450), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_fake16_dpp_gfx11
    UINT64_C(2113971450), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_fake16_dpp_gfx12
    UINT64_C(2113971200), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_fake16_e32_gfx11
    UINT64_C(2113971200), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_fake16_e32_gfx12
    UINT64_C(3587309568), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3587309568), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077329133568), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077329133568), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_fake16_e64_dpp_gfx12
    UINT64_C(3587309568), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_fake16_e64_gfx11
    UINT64_C(3587309568), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_fake16_e64_gfx12
    UINT64_C(2113971200), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_t16_dpp8_gfx11
    UINT64_C(2113971200), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_t16_dpp8_gfx12
    UINT64_C(2113971450), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_t16_dpp_gfx11
    UINT64_C(2113971450), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_t16_dpp_gfx12
    UINT64_C(2113971200), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_t16_e32_gfx11
    UINT64_C(2113971200), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_t16_e32_gfx12
    UINT64_C(3587309568), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_t16_e64_dpp8_gfx11
    UINT64_C(3587309568), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077329133568), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_t16_e64_dpp_gfx11
    UINT64_C(1077329133568), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_t16_e64_dpp_gfx12
    UINT64_C(3587309568), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_t16_e64_gfx11
    UINT64_C(3587309568), UINT64_C(0),	// V_CVT_U16_F16V_CVT_U16_F16_t16_e64_gfx12
    UINT64_C(2113971200), UINT64_C(0),	// V_CVT_U16_F16_dpp8_gfx10
    UINT64_C(2113971450), UINT64_C(0),	// V_CVT_U16_F16_dpp_gfx10
    UINT64_C(2113959674), UINT64_C(0),	// V_CVT_U16_F16_dpp_vi
    UINT64_C(2113971200), UINT64_C(0),	// V_CVT_U16_F16_e32_gfx10
    UINT64_C(2113959424), UINT64_C(0),	// V_CVT_U16_F16_e32_vi
    UINT64_C(3587309568), UINT64_C(0),	// V_CVT_U16_F16_e64_gfx10
    UINT64_C(3514499072), UINT64_C(0),	// V_CVT_U16_F16_e64_vi
    UINT64_C(2113971449), UINT64_C(0),	// V_CVT_U16_F16_sdwa_gfx10
    UINT64_C(2113959673), UINT64_C(0),	// V_CVT_U16_F16_sdwa_gfx9
    UINT64_C(2113959673), UINT64_C(0),	// V_CVT_U16_F16_sdwa_vi
    UINT64_C(2113932800), UINT64_C(0),	// V_CVT_U32_F32_dpp8_gfx10
    UINT64_C(2113932800), UINT64_C(0),	// V_CVT_U32_F32_dpp8_gfx11
    UINT64_C(2113932800), UINT64_C(0),	// V_CVT_U32_F32_dpp8_gfx12
    UINT64_C(2113933050), UINT64_C(0),	// V_CVT_U32_F32_dpp_gfx10
    UINT64_C(2113933050), UINT64_C(0),	// V_CVT_U32_F32_dpp_gfx11
    UINT64_C(2113933050), UINT64_C(0),	// V_CVT_U32_F32_dpp_gfx12
    UINT64_C(2113933050), UINT64_C(0),	// V_CVT_U32_F32_dpp_vi
    UINT64_C(2113932800), UINT64_C(0),	// V_CVT_U32_F32_e32_gfx10
    UINT64_C(2113932800), UINT64_C(0),	// V_CVT_U32_F32_e32_gfx11
    UINT64_C(2113932800), UINT64_C(0),	// V_CVT_U32_F32_e32_gfx12
    UINT64_C(2113932800), UINT64_C(0),	// V_CVT_U32_F32_e32_gfx6_gfx7
    UINT64_C(2113932800), UINT64_C(0),	// V_CVT_U32_F32_e32_vi
    UINT64_C(3582394368), UINT64_C(0),	// V_CVT_U32_F32_e64_dpp8_gfx11
    UINT64_C(3582394368), UINT64_C(0),	// V_CVT_U32_F32_e64_dpp8_gfx12
    UINT64_C(1077324218368), UINT64_C(0),	// V_CVT_U32_F32_e64_dpp_gfx11
    UINT64_C(1077324218368), UINT64_C(0),	// V_CVT_U32_F32_e64_dpp_gfx12
    UINT64_C(3582394368), UINT64_C(0),	// V_CVT_U32_F32_e64_gfx10
    UINT64_C(3582394368), UINT64_C(0),	// V_CVT_U32_F32_e64_gfx11
    UINT64_C(3582394368), UINT64_C(0),	// V_CVT_U32_F32_e64_gfx12
    UINT64_C(3540910080), UINT64_C(0),	// V_CVT_U32_F32_e64_gfx6_gfx7
    UINT64_C(3511091200), UINT64_C(0),	// V_CVT_U32_F32_e64_vi
    UINT64_C(2113933049), UINT64_C(0),	// V_CVT_U32_F32_sdwa_gfx10
    UINT64_C(2113933049), UINT64_C(0),	// V_CVT_U32_F32_sdwa_gfx9
    UINT64_C(2113933049), UINT64_C(0),	// V_CVT_U32_F32_sdwa_vi
    UINT64_C(2113940218), UINT64_C(0),	// V_CVT_U32_F64_dpp_gfx12
    UINT64_C(2113940218), UINT64_C(0),	// V_CVT_U32_F64_dpp_vi
    UINT64_C(2113939968), UINT64_C(0),	// V_CVT_U32_F64_e32_gfx10
    UINT64_C(2113939968), UINT64_C(0),	// V_CVT_U32_F64_e32_gfx11
    UINT64_C(2113939968), UINT64_C(0),	// V_CVT_U32_F64_e32_gfx12
    UINT64_C(2113939968), UINT64_C(0),	// V_CVT_U32_F64_e32_gfx6_gfx7
    UINT64_C(2113939968), UINT64_C(0),	// V_CVT_U32_F64_e32_vi
    UINT64_C(1077325135872), UINT64_C(0),	// V_CVT_U32_F64_e64_dpp_gfx12
    UINT64_C(3583311872), UINT64_C(0),	// V_CVT_U32_F64_e64_gfx10
    UINT64_C(3583311872), UINT64_C(0),	// V_CVT_U32_F64_e64_gfx11
    UINT64_C(3583311872), UINT64_C(0),	// V_CVT_U32_F64_e64_gfx12
    UINT64_C(3542745088), UINT64_C(0),	// V_CVT_U32_F64_e64_gfx6_gfx7
    UINT64_C(3512008704), UINT64_C(0),	// V_CVT_U32_F64_e64_vi
    UINT64_C(2113984000), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_fake16_dpp8_gfx11
    UINT64_C(2113984000), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_fake16_dpp8_gfx12
    UINT64_C(2113984250), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_fake16_dpp_gfx11
    UINT64_C(2113984250), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_fake16_dpp_gfx12
    UINT64_C(2113984000), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_fake16_e32_gfx11
    UINT64_C(2113984000), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_fake16_e32_gfx12
    UINT64_C(3588947968), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3588947968), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077330771968), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077330771968), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_fake16_e64_dpp_gfx12
    UINT64_C(3588947968), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_fake16_e64_gfx11
    UINT64_C(3588947968), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_fake16_e64_gfx12
    UINT64_C(2113984000), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_t16_dpp8_gfx11
    UINT64_C(2113984000), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_t16_dpp8_gfx12
    UINT64_C(2113984250), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_t16_dpp_gfx11
    UINT64_C(2113984250), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_t16_dpp_gfx12
    UINT64_C(2113984000), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_t16_e32_gfx11
    UINT64_C(2113984000), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_t16_e32_gfx12
    UINT64_C(3588947968), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_t16_e64_dpp8_gfx11
    UINT64_C(3588947968), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077330771968), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_t16_e64_dpp_gfx11
    UINT64_C(1077330771968), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_t16_e64_dpp_gfx12
    UINT64_C(3588947968), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_t16_e64_gfx11
    UINT64_C(3588947968), UINT64_C(0),	// V_CVT_U32_U16V_CVT_U32_U16_t16_e64_gfx12
    UINT64_C(3595829248), UINT64_C(0),	// V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_fake16_e64_dpp8_gfx11
    UINT64_C(3595829248), UINT64_C(0),	// V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_fake16_e64_dpp8_gfx12
    UINT64_C(1077337653248), UINT64_C(0),	// V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_fake16_e64_dpp_gfx11
    UINT64_C(1077337653248), UINT64_C(0),	// V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_fake16_e64_dpp_gfx12
    UINT64_C(3595829248), UINT64_C(0),	// V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_fake16_e64_gfx11
    UINT64_C(3595829248), UINT64_C(0),	// V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_fake16_e64_gfx12
    UINT64_C(3595829248), UINT64_C(0),	// V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_t16_e64_dpp8_gfx11
    UINT64_C(3595829248), UINT64_C(0),	// V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_t16_e64_dpp8_gfx12
    UINT64_C(1077337653248), UINT64_C(0),	// V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_t16_e64_dpp_gfx11
    UINT64_C(1077337653248), UINT64_C(0),	// V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_t16_e64_dpp_gfx12
    UINT64_C(3595829248), UINT64_C(0),	// V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_t16_e64_gfx11
    UINT64_C(3595829248), UINT64_C(0),	// V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_t16_e64_gfx12
    UINT64_C(3613327360), UINT64_C(0),	// V_DIV_FIXUP_F16_gfx10
    UINT64_C(3523674112), UINT64_C(0),	// V_DIV_FIXUP_F16_gfx9_gfx9
    UINT64_C(3522101248), UINT64_C(0),	// V_DIV_FIXUP_F16_vi
    UINT64_C(3592880128), UINT64_C(0),	// V_DIV_FIXUP_F32_e64_gfx11
    UINT64_C(3592880128), UINT64_C(0),	// V_DIV_FIXUP_F32_e64_gfx12
    UINT64_C(3579772928), UINT64_C(0),	// V_DIV_FIXUP_F32_gfx10
    UINT64_C(3535667200), UINT64_C(0),	// V_DIV_FIXUP_F32_gfx6_gfx7
    UINT64_C(3520987136), UINT64_C(0),	// V_DIV_FIXUP_F32_vi
    UINT64_C(1077334769664), UINT64_C(0),	// V_DIV_FIXUP_F64_e64_dpp_gfx1250
    UINT64_C(3592945664), UINT64_C(0),	// V_DIV_FIXUP_F64_e64_gfx11
    UINT64_C(3592945664), UINT64_C(0),	// V_DIV_FIXUP_F64_e64_gfx12
    UINT64_C(3592945664), UINT64_C(0),	// V_DIV_FIXUP_F64_e64_gfx1250
    UINT64_C(3579838464), UINT64_C(0),	// V_DIV_FIXUP_F64_gfx10
    UINT64_C(3535798272), UINT64_C(0),	// V_DIV_FIXUP_F64_gfx6_gfx7
    UINT64_C(3521052672), UINT64_C(0),	// V_DIV_FIXUP_F64_vi
    UINT64_C(3522101248), UINT64_C(0),	// V_DIV_FIXUP_LEGACY_F16_gfx9
    UINT64_C(3593928704), UINT64_C(0),	// V_DIV_FMAS_F32_e64_gfx11
    UINT64_C(3593928704), UINT64_C(0),	// V_DIV_FMAS_F32_e64_gfx12
    UINT64_C(3580821504), UINT64_C(0),	// V_DIV_FMAS_F32_gfx10
    UINT64_C(3537764352), UINT64_C(0),	// V_DIV_FMAS_F32_gfx6_gfx7
    UINT64_C(3521249280), UINT64_C(0),	// V_DIV_FMAS_F32_vi
    UINT64_C(1077335818240), UINT64_C(0),	// V_DIV_FMAS_F64_e64_dpp_gfx1250
    UINT64_C(3593994240), UINT64_C(0),	// V_DIV_FMAS_F64_e64_gfx11
    UINT64_C(3593994240), UINT64_C(0),	// V_DIV_FMAS_F64_e64_gfx12
    UINT64_C(3593994240), UINT64_C(0),	// V_DIV_FMAS_F64_e64_gfx1250
    UINT64_C(3580887040), UINT64_C(0),	// V_DIV_FMAS_F64_gfx10
    UINT64_C(3537895424), UINT64_C(0),	// V_DIV_FMAS_F64_gfx6_gfx7
    UINT64_C(3521314816), UINT64_C(0),	// V_DIV_FMAS_F64_vi
    UINT64_C(3606839296), UINT64_C(0),	// V_DIV_SCALE_F32_e64_gfx11
    UINT64_C(3606839296), UINT64_C(0),	// V_DIV_SCALE_F32_e64_gfx12
    UINT64_C(3580690432), UINT64_C(0),	// V_DIV_SCALE_F32_gfx10
    UINT64_C(3537502208), UINT64_C(0),	// V_DIV_SCALE_F32_gfx6_gfx7
    UINT64_C(3521118208), UINT64_C(0),	// V_DIV_SCALE_F32_vi
    UINT64_C(1077348728832), UINT64_C(0),	// V_DIV_SCALE_F64_e64_dpp_gfx1250
    UINT64_C(3606904832), UINT64_C(0),	// V_DIV_SCALE_F64_e64_gfx11
    UINT64_C(3606904832), UINT64_C(0),	// V_DIV_SCALE_F64_e64_gfx12
    UINT64_C(3606904832), UINT64_C(0),	// V_DIV_SCALE_F64_e64_gfx1250
    UINT64_C(3580755968), UINT64_C(0),	// V_DIV_SCALE_F64_gfx10
    UINT64_C(3537633280), UINT64_C(0),	// V_DIV_SCALE_F64_gfx6_gfx7
    UINT64_C(3521183744), UINT64_C(0),	// V_DIV_SCALE_F64_vi
    UINT64_C(67108864), UINT64_C(0),	// V_DOT2ACC_F32_F16_dpp8_gfx11
    UINT64_C(67109114), UINT64_C(0),	// V_DOT2ACC_F32_F16_dpp_gfx11
    UINT64_C(67108864), UINT64_C(0),	// V_DOT2ACC_F32_F16_e32_gfx11
    UINT64_C(738197754), UINT64_C(0),	// V_DOT2C_F32_BF16_dpp_vi
    UINT64_C(738197504), UINT64_C(0),	// V_DOT2C_F32_BF16_e32_vi
    UINT64_C(3507879936), UINT64_C(0),	// V_DOT2C_F32_BF16_e64_vi
    UINT64_C(67108864), UINT64_C(0),	// V_DOT2C_F32_F16_dpp8_gfx10
    UINT64_C(67109114), UINT64_C(0),	// V_DOT2C_F32_F16_dpp_gfx10
    UINT64_C(1845494010), UINT64_C(0),	// V_DOT2C_F32_F16_dpp_vi
    UINT64_C(67108864), UINT64_C(0),	// V_DOT2C_F32_F16_e32_gfx10
    UINT64_C(1845493760), UINT64_C(0),	// V_DOT2C_F32_F16_e32_vi
    UINT64_C(3510042624), UINT64_C(0),	// V_DOT2C_F32_F16_e64_vi
    UINT64_C(1879048442), UINT64_C(0),	// V_DOT2C_I32_I16_dpp_vi
    UINT64_C(1879048192), UINT64_C(0),	// V_DOT2C_I32_I16_e32_vi
    UINT64_C(3510108160), UINT64_C(0),	// V_DOT2C_I32_I16_e64_vi
    UINT64_C(3597074432), UINT64_C(0),	// V_DOT2_BF16_BF16_fake16_e64_dpp8_gfx11
    UINT64_C(3597074432), UINT64_C(0),	// V_DOT2_BF16_BF16_fake16_e64_dpp8_gfx12
    UINT64_C(1077338898432), UINT64_C(0),	// V_DOT2_BF16_BF16_fake16_e64_dpp_gfx11
    UINT64_C(1077338898432), UINT64_C(0),	// V_DOT2_BF16_BF16_fake16_e64_dpp_gfx12
    UINT64_C(3597074432), UINT64_C(0),	// V_DOT2_BF16_BF16_fake16_e64_gfx11
    UINT64_C(3597074432), UINT64_C(0),	// V_DOT2_BF16_BF16_fake16_e64_gfx12
    UINT64_C(3597074432), UINT64_C(0),	// V_DOT2_BF16_BF16_t16_e64_dpp8_gfx11
    UINT64_C(3597074432), UINT64_C(0),	// V_DOT2_BF16_BF16_t16_e64_dpp8_gfx12
    UINT64_C(1077338898432), UINT64_C(0),	// V_DOT2_BF16_BF16_t16_e64_dpp_gfx11
    UINT64_C(1077338898432), UINT64_C(0),	// V_DOT2_BF16_BF16_t16_e64_dpp_gfx12
    UINT64_C(3597074432), UINT64_C(0),	// V_DOT2_BF16_BF16_t16_e64_gfx11
    UINT64_C(3597074432), UINT64_C(0),	// V_DOT2_BF16_BF16_t16_e64_gfx12
    UINT64_C(3597008896), UINT64_C(0),	// V_DOT2_F16_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3597008896), UINT64_C(0),	// V_DOT2_F16_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077338832896), UINT64_C(0),	// V_DOT2_F16_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077338832896), UINT64_C(0),	// V_DOT2_F16_F16_fake16_e64_dpp_gfx12
    UINT64_C(3597008896), UINT64_C(0),	// V_DOT2_F16_F16_fake16_e64_gfx11
    UINT64_C(3597008896), UINT64_C(0),	// V_DOT2_F16_F16_fake16_e64_gfx12
    UINT64_C(3597008896), UINT64_C(0),	// V_DOT2_F16_F16_t16_e64_dpp8_gfx11
    UINT64_C(3597008896), UINT64_C(0),	// V_DOT2_F16_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077338832896), UINT64_C(0),	// V_DOT2_F16_F16_t16_e64_dpp_gfx11
    UINT64_C(1077338832896), UINT64_C(0),	// V_DOT2_F16_F16_t16_e64_dpp_gfx12
    UINT64_C(3597008896), UINT64_C(0),	// V_DOT2_F16_F16_t16_e64_gfx11
    UINT64_C(3597008896), UINT64_C(0),	// V_DOT2_F16_F16_t16_e64_gfx12
    UINT64_C(3424256000), UINT64_C(0),	// V_DOT2_F32_BF16_dpp8_gfx11
    UINT64_C(3424256000), UINT64_C(0),	// V_DOT2_F32_BF16_dpp8_gfx12
    UINT64_C(1077166080000), UINT64_C(0),	// V_DOT2_F32_BF16_dpp_gfx11
    UINT64_C(1077166080000), UINT64_C(0),	// V_DOT2_F32_BF16_dpp_gfx12
    UINT64_C(3424256000), UINT64_C(0),	// V_DOT2_F32_BF16_gfx11
    UINT64_C(3424256000), UINT64_C(0),	// V_DOT2_F32_BF16_gfx12
    UINT64_C(3550085120), UINT64_C(0),	// V_DOT2_F32_BF16_vi
    UINT64_C(3423797248), UINT64_C(0),	// V_DOT2_F32_F16_dpp8_gfx11
    UINT64_C(3423797248), UINT64_C(0),	// V_DOT2_F32_F16_dpp8_gfx12
    UINT64_C(1077165621248), UINT64_C(0),	// V_DOT2_F32_F16_dpp_gfx11
    UINT64_C(1077165621248), UINT64_C(0),	// V_DOT2_F32_F16_dpp_gfx12
    UINT64_C(3423797248), UINT64_C(0),	// V_DOT2_F32_F16_gfx10
    UINT64_C(3423797248), UINT64_C(0),	// V_DOT2_F32_F16_gfx11
    UINT64_C(3423797248), UINT64_C(0),	// V_DOT2_F32_F16_gfx12
    UINT64_C(3550674944), UINT64_C(0),	// V_DOT2_F32_F16_vi
    UINT64_C(3423862784), UINT64_C(0),	// V_DOT2_I32_I16_gfx10
    UINT64_C(3550871552), UINT64_C(0),	// V_DOT2_I32_I16_vi
    UINT64_C(3423928320), UINT64_C(0),	// V_DOT2_U32_U16_gfx10
    UINT64_C(3550937088), UINT64_C(0),	// V_DOT2_U32_U16_vi
    UINT64_C(436207616), UINT64_C(0),	// V_DOT4C_I32_I8_dpp8_gfx10
    UINT64_C(436207866), UINT64_C(0),	// V_DOT4C_I32_I8_dpp_gfx10
    UINT64_C(1912602874), UINT64_C(0),	// V_DOT4C_I32_I8_dpp_vi
    UINT64_C(436207616), UINT64_C(0),	// V_DOT4C_I32_I8_e32_gfx10
    UINT64_C(1912602624), UINT64_C(0),	// V_DOT4C_I32_I8_e32_vi
    UINT64_C(3510173696), UINT64_C(0),	// V_DOT4C_I32_I8_e64_vi
    UINT64_C(1729382260335394816), UINT64_C(0),	// V_DOT4_F32_BF8_BF8_dpp8_gfx12
    UINT64_C(1729383334077218816), UINT64_C(0),	// V_DOT4_F32_BF8_BF8_dpp_gfx12
    UINT64_C(1729382260335394816), UINT64_C(0),	// V_DOT4_F32_BF8_BF8_gfx12
    UINT64_C(1729382260335263744), UINT64_C(0),	// V_DOT4_F32_BF8_FP8_dpp8_gfx12
    UINT64_C(1729383334077087744), UINT64_C(0),	// V_DOT4_F32_BF8_FP8_dpp_gfx12
    UINT64_C(1729382260335263744), UINT64_C(0),	// V_DOT4_F32_BF8_FP8_gfx12
    UINT64_C(1729382260335198208), UINT64_C(0),	// V_DOT4_F32_FP8_BF8_dpp8_gfx12
    UINT64_C(1729383334077022208), UINT64_C(0),	// V_DOT4_F32_FP8_BF8_dpp_gfx12
    UINT64_C(1729382260335198208), UINT64_C(0),	// V_DOT4_F32_FP8_BF8_gfx12
    UINT64_C(1729382260335329280), UINT64_C(0),	// V_DOT4_F32_FP8_FP8_dpp8_gfx12
    UINT64_C(1729383334077153280), UINT64_C(0),	// V_DOT4_F32_FP8_FP8_dpp_gfx12
    UINT64_C(1729382260335329280), UINT64_C(0),	// V_DOT4_F32_FP8_FP8_gfx12
    UINT64_C(3423993856), UINT64_C(0),	// V_DOT4_I32_I8_gfx10
    UINT64_C(3551002624), UINT64_C(0),	// V_DOT4_I32_I8_vi
    UINT64_C(3423993856), UINT64_C(0),	// V_DOT4_I32_IU8_gfx11
    UINT64_C(3423993856), UINT64_C(0),	// V_DOT4_I32_IU8_gfx12
    UINT64_C(3424059392), UINT64_C(0),	// V_DOT4_U32_U8_gfx10
    UINT64_C(3424059392), UINT64_C(0),	// V_DOT4_U32_U8_gfx11
    UINT64_C(3424059392), UINT64_C(0),	// V_DOT4_U32_U8_gfx12
    UINT64_C(3551068160), UINT64_C(0),	// V_DOT4_U32_U8_vi
    UINT64_C(67108864), UINT64_C(0),	// V_DOT8C_I32_I4_dpp8_gfx10
    UINT64_C(67109114), UINT64_C(0),	// V_DOT8C_I32_I4_dpp_gfx10
    UINT64_C(1946157306), UINT64_C(0),	// V_DOT8C_I32_I4_dpp_vi
    UINT64_C(67108864), UINT64_C(0),	// V_DOT8C_I32_I4_e32_gfx10
    UINT64_C(1946157056), UINT64_C(0),	// V_DOT8C_I32_I4_e32_vi
    UINT64_C(3510239232), UINT64_C(0),	// V_DOT8C_I32_I4_e64_vi
    UINT64_C(3424124928), UINT64_C(0),	// V_DOT8_I32_I4_gfx10
    UINT64_C(3551133696), UINT64_C(0),	// V_DOT8_I32_I4_vi
    UINT64_C(3424124928), UINT64_C(0),	// V_DOT8_I32_IU4_gfx11
    UINT64_C(3424124928), UINT64_C(0),	// V_DOT8_I32_IU4_gfx12
    UINT64_C(3424190464), UINT64_C(0),	// V_DOT8_U32_U4_gfx10
    UINT64_C(3424190464), UINT64_C(0),	// V_DOT8_U32_U4_gfx11
    UINT64_C(3424190464), UINT64_C(0),	// V_DOT8_U32_U4_gfx12
    UINT64_C(3551199232), UINT64_C(0),	// V_DOT8_U32_U4_vi
    UINT64_C(3473948672), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3372744704), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_ADD_F32_e32_gfx11
    UINT64_C(3372744704), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_ADD_F32_e32_gfx12
    UINT64_C(3372744704), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_ADD_F32_e32_gfx1250
    UINT64_C(3473997824), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3374317568), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_ADD_U32_e32_gfx11
    UINT64_C(3374317568), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_ADD_U32_e32_gfx12
    UINT64_C(3374317568), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_ADD_U32_e32_gfx1250
    UINT64_C(3374579712), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_AND_B32_e32_gfx11
    UINT64_C(3374579712), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_AND_B32_e32_gfx12
    UINT64_C(3474022400), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3375104000), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_ASHRREV_I32_e32_gfx1250
    UINT64_C(3474006016), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3473969152), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3373400064), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32_gfx11
    UINT64_C(3373400064), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32_gfx12
    UINT64_C(3373400064), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32_gfx1250
    UINT64_C(3473985536), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3373924352), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_DOT2C_F32_BF16_e32_gfx11
    UINT64_C(3373924352), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_DOT2C_F32_BF16_e32_gfx12
    UINT64_C(3373924352), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250
    UINT64_C(3473981440), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3373793280), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_DOT2C_F32_F16_e32_gfx11
    UINT64_C(3373793280), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_DOT2C_F32_F16_e32_gfx12
    UINT64_C(3373793280), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_DOT2C_F32_F16_e32_gfx1250
    UINT64_C(3372351488), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_FMAAK_F32_gfx11
    UINT64_C(3372351488), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_FMAAK_F32_gfx12
    UINT64_C(3372351488), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_FMAAK_F32_gfx1250
    UINT64_C(3473932288), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3372220416), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_FMAC_F32_e32_gfx11
    UINT64_C(3372220416), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_FMAC_F32_e32_gfx12
    UINT64_C(3372220416), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_FMAC_F32_e32_gfx1250
    UINT64_C(3372482560), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_FMAMK_F32_gfx11
    UINT64_C(3372482560), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_FMAMK_F32_gfx12
    UINT64_C(3372482560), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_FMAMK_F32_gfx1250
    UINT64_C(3474010112), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3474001920), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3374448640), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_LSHLREV_B32_e32_gfx11
    UINT64_C(3374448640), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_LSHLREV_B32_e32_gfx12
    UINT64_C(3374448640), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_LSHLREV_B32_e32_gfx1250
    UINT64_C(3474018304), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3374972928), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_LSHRREV_B32_e32_gfx1250
    UINT64_C(3473973248), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3373531136), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MAX_F32_e32_gfx11
    UINT64_C(3373531136), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MAX_F32_e32_gfx12
    UINT64_C(3373531136), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MAX_F32_e32_gfx1250
    UINT64_C(3474026496), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3375235072), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MAX_I32_e32_gfx1250
    UINT64_C(3473977344), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3373662208), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MIN_F32_e32_gfx11
    UINT64_C(3373662208), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MIN_F32_e32_gfx12
    UINT64_C(3373662208), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MIN_F32_e32_gfx1250
    UINT64_C(3474030592), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3375366144), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MIN_I32_e32_gfx1250
    UINT64_C(3473965056), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3373268992), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MOV_B32_e32_gfx11
    UINT64_C(3373268992), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MOV_B32_e32_gfx12
    UINT64_C(3373268992), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MOV_B32_e32_gfx1250
    UINT64_C(3473944576), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3372613632), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MUL_F32_e32_gfx11
    UINT64_C(3372613632), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MUL_F32_e32_gfx12
    UINT64_C(3372613632), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MUL_F32_e32_gfx1250
    UINT64_C(3473960960), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3373137920), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MUL_LEGACY_F32_e32_gfx11
    UINT64_C(3373137920), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MUL_LEGACY_F32_e32_gfx12
    UINT64_C(3373137920), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250
    UINT64_C(3473956864), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3373006848), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_SUBREV_F32_e32_gfx11
    UINT64_C(3373006848), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_SUBREV_F32_e32_gfx12
    UINT64_C(3373006848), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_SUBREV_F32_e32_gfx1250
    UINT64_C(3473952768), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3372875776), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_SUB_F32_e32_gfx11
    UINT64_C(3372875776), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_SUB_F32_e32_gfx12
    UINT64_C(3372875776), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_SUB_F32_e32_gfx1250
    UINT64_C(3474014208), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3374841856), UINT64_C(0),	// V_DUAL_ADD_F32_e32_X_SUB_U32_e32_gfx1250
    UINT64_C(3481550848), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3481600000), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3481624576), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3481608192), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3481571328), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3481587712), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3481583616), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3481534464), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3481612288), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3481604096), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3481620480), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3481575424), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3481628672), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3481579520), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3481632768), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3481567232), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3481546752), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3481563136), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3481559040), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3481554944), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3481616384), UINT64_C(0),	// V_DUAL_ADD_F64_pseudo_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3477094400), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3477143552), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3477168128), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3477151744), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3477114880), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3477131264), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3477127168), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3477078016), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3477155840), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3477147648), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3477164032), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3477118976), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3477172224), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3477123072), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3477176320), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3477110784), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3477090304), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3477106688), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3477102592), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3477098496), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3477159936), UINT64_C(0),	// V_DUAL_ADD_U32_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3478667264), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3478716416), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3478740992), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3478724608), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3478687744), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3478704128), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3478700032), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3478650880), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3478728704), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3478720512), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3478736896), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3478691840), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3478745088), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3478695936), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3478749184), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3478683648), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3478663168), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3478679552), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3478675456), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3478671360), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3478732800), UINT64_C(0),	// V_DUAL_ASHRREV_I32_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3475259392), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3393716224), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32_gfx11
    UINT64_C(3393716224), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32_gfx12
    UINT64_C(3393716224), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32_gfx1250
    UINT64_C(3475308544), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3395289088), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_ADD_U32_e32_gfx11
    UINT64_C(3395289088), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_ADD_U32_e32_gfx12
    UINT64_C(3395289088), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_ADD_U32_e32_gfx1250
    UINT64_C(3395551232), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_AND_B32_e32_gfx11
    UINT64_C(3395551232), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_AND_B32_e32_gfx12
    UINT64_C(3475333120), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3396075520), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_ASHRREV_I32_e32_gfx1250
    UINT64_C(3475316736), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3475279872), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3394371584), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_CNDMASK_B32_e32_gfx11
    UINT64_C(3394371584), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_CNDMASK_B32_e32_gfx12
    UINT64_C(3394371584), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_CNDMASK_B32_e32_gfx1250
    UINT64_C(3475296256), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3394895872), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_BF16_e32_gfx11
    UINT64_C(3394895872), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_BF16_e32_gfx12
    UINT64_C(3394895872), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_BF16_e32_gfx1250
    UINT64_C(3475292160), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3394764800), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_F16_e32_gfx11
    UINT64_C(3394764800), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_F16_e32_gfx12
    UINT64_C(3394764800), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_F16_e32_gfx1250
    UINT64_C(3393323008), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_FMAAK_F32_gfx11
    UINT64_C(3393323008), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_FMAAK_F32_gfx12
    UINT64_C(3393323008), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_FMAAK_F32_gfx1250
    UINT64_C(3475243008), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3393191936), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32_gfx11
    UINT64_C(3393191936), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32_gfx12
    UINT64_C(3393191936), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32_gfx1250
    UINT64_C(3393454080), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_FMAMK_F32_gfx11
    UINT64_C(3393454080), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_FMAMK_F32_gfx12
    UINT64_C(3393454080), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_FMAMK_F32_gfx1250
    UINT64_C(3475320832), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3475312640), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3395420160), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_LSHLREV_B32_e32_gfx11
    UINT64_C(3395420160), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_LSHLREV_B32_e32_gfx12
    UINT64_C(3395420160), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_LSHLREV_B32_e32_gfx1250
    UINT64_C(3475329024), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3395944448), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_LSHRREV_B32_e32_gfx1250
    UINT64_C(3475283968), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3394502656), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MAX_F32_e32_gfx11
    UINT64_C(3394502656), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MAX_F32_e32_gfx12
    UINT64_C(3394502656), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MAX_F32_e32_gfx1250
    UINT64_C(3475337216), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3396206592), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MAX_I32_e32_gfx1250
    UINT64_C(3475288064), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3394633728), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MIN_F32_e32_gfx11
    UINT64_C(3394633728), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MIN_F32_e32_gfx12
    UINT64_C(3394633728), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MIN_F32_e32_gfx1250
    UINT64_C(3475341312), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3396337664), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MIN_I32_e32_gfx1250
    UINT64_C(3475275776), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3394240512), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MOV_B32_e32_gfx11
    UINT64_C(3394240512), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MOV_B32_e32_gfx12
    UINT64_C(3394240512), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MOV_B32_e32_gfx1250
    UINT64_C(3475255296), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3393585152), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx11
    UINT64_C(3393585152), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx12
    UINT64_C(3393585152), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx1250
    UINT64_C(3475271680), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3394109440), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MUL_LEGACY_F32_e32_gfx11
    UINT64_C(3394109440), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MUL_LEGACY_F32_e32_gfx12
    UINT64_C(3394109440), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_MUL_LEGACY_F32_e32_gfx1250
    UINT64_C(3475267584), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3393978368), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_SUBREV_F32_e32_gfx11
    UINT64_C(3393978368), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_SUBREV_F32_e32_gfx12
    UINT64_C(3393978368), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_SUBREV_F32_e32_gfx1250
    UINT64_C(3475263488), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3393847296), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32_gfx11
    UINT64_C(3393847296), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32_gfx12
    UINT64_C(3393847296), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32_gfx1250
    UINT64_C(3475324928), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3395813376), UINT64_C(0),	// V_DUAL_CNDMASK_B32_e32_X_SUB_U32_e32_gfx1250
    UINT64_C(3476307968), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3410493440), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_ADD_F32_e32_gfx11
    UINT64_C(3410493440), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_ADD_F32_e32_gfx12
    UINT64_C(3410493440), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_ADD_F32_e32_gfx1250
    UINT64_C(3476357120), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3412066304), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_ADD_U32_e32_gfx11
    UINT64_C(3412066304), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_ADD_U32_e32_gfx12
    UINT64_C(3412066304), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_ADD_U32_e32_gfx1250
    UINT64_C(3412328448), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_AND_B32_e32_gfx11
    UINT64_C(3412328448), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_AND_B32_e32_gfx12
    UINT64_C(3476381696), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3412852736), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_ASHRREV_I32_e32_gfx1250
    UINT64_C(3476365312), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3476328448), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3411148800), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_CNDMASK_B32_e32_gfx11
    UINT64_C(3411148800), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_CNDMASK_B32_e32_gfx12
    UINT64_C(3411148800), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_CNDMASK_B32_e32_gfx1250
    UINT64_C(3476344832), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3411673088), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_BF16_e32_gfx11
    UINT64_C(3411673088), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_BF16_e32_gfx12
    UINT64_C(3411673088), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_BF16_e32_gfx1250
    UINT64_C(3476340736), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3411542016), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_F16_e32_gfx11
    UINT64_C(3411542016), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_F16_e32_gfx12
    UINT64_C(3411542016), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_F16_e32_gfx1250
    UINT64_C(3410100224), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_FMAAK_F32_gfx11
    UINT64_C(3410100224), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_FMAAK_F32_gfx12
    UINT64_C(3410100224), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_FMAAK_F32_gfx1250
    UINT64_C(3476291584), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3409969152), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_FMAC_F32_e32_gfx11
    UINT64_C(3409969152), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_FMAC_F32_e32_gfx12
    UINT64_C(3409969152), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_FMAC_F32_e32_gfx1250
    UINT64_C(3410231296), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_FMAMK_F32_gfx11
    UINT64_C(3410231296), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_FMAMK_F32_gfx12
    UINT64_C(3410231296), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_FMAMK_F32_gfx1250
    UINT64_C(3476369408), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3476361216), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3412197376), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_LSHLREV_B32_e32_gfx11
    UINT64_C(3412197376), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_LSHLREV_B32_e32_gfx12
    UINT64_C(3412197376), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_LSHLREV_B32_e32_gfx1250
    UINT64_C(3476377600), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3412721664), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_LSHRREV_B32_e32_gfx1250
    UINT64_C(3476332544), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3411279872), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MAX_F32_e32_gfx11
    UINT64_C(3411279872), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MAX_F32_e32_gfx12
    UINT64_C(3411279872), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MAX_F32_e32_gfx1250
    UINT64_C(3476385792), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3412983808), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MAX_I32_e32_gfx1250
    UINT64_C(3476336640), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3411410944), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MIN_F32_e32_gfx11
    UINT64_C(3411410944), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MIN_F32_e32_gfx12
    UINT64_C(3411410944), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MIN_F32_e32_gfx1250
    UINT64_C(3476389888), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3413114880), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MIN_I32_e32_gfx1250
    UINT64_C(3476324352), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3411017728), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MOV_B32_e32_gfx11
    UINT64_C(3411017728), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MOV_B32_e32_gfx12
    UINT64_C(3411017728), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MOV_B32_e32_gfx1250
    UINT64_C(3476303872), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3410362368), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MUL_F32_e32_gfx11
    UINT64_C(3410362368), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MUL_F32_e32_gfx12
    UINT64_C(3410362368), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MUL_F32_e32_gfx1250
    UINT64_C(3476320256), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3410886656), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MUL_LEGACY_F32_e32_gfx11
    UINT64_C(3410886656), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MUL_LEGACY_F32_e32_gfx12
    UINT64_C(3410886656), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_MUL_LEGACY_F32_e32_gfx1250
    UINT64_C(3476316160), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3410755584), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_SUBREV_F32_e32_gfx11
    UINT64_C(3410755584), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_SUBREV_F32_e32_gfx12
    UINT64_C(3410755584), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_SUBREV_F32_e32_gfx1250
    UINT64_C(3476312064), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3410624512), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_SUB_F32_e32_gfx11
    UINT64_C(3410624512), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_SUB_F32_e32_gfx12
    UINT64_C(3410624512), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_SUB_F32_e32_gfx1250
    UINT64_C(3476373504), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3412590592), UINT64_C(0),	// V_DUAL_DOT2C_F32_BF16_e32_X_SUB_U32_e32_gfx1250
    UINT64_C(3476045824), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3406299136), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_ADD_F32_e32_gfx11
    UINT64_C(3406299136), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_ADD_F32_e32_gfx12
    UINT64_C(3406299136), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_ADD_F32_e32_gfx1250
    UINT64_C(3476094976), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3407872000), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_ADD_U32_e32_gfx11
    UINT64_C(3407872000), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_ADD_U32_e32_gfx12
    UINT64_C(3407872000), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_ADD_U32_e32_gfx1250
    UINT64_C(3408134144), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_AND_B32_e32_gfx11
    UINT64_C(3408134144), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_AND_B32_e32_gfx12
    UINT64_C(3476119552), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3408658432), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_ASHRREV_I32_e32_gfx1250
    UINT64_C(3476103168), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3476066304), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3406954496), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_CNDMASK_B32_e32_gfx11
    UINT64_C(3406954496), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_CNDMASK_B32_e32_gfx12
    UINT64_C(3406954496), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_CNDMASK_B32_e32_gfx1250
    UINT64_C(3476082688), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3407478784), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_BF16_e32_gfx11
    UINT64_C(3407478784), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_BF16_e32_gfx12
    UINT64_C(3407478784), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_BF16_e32_gfx1250
    UINT64_C(3476078592), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3407347712), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_F16_e32_gfx11
    UINT64_C(3407347712), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_F16_e32_gfx12
    UINT64_C(3407347712), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_F16_e32_gfx1250
    UINT64_C(3405905920), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_FMAAK_F32_gfx11
    UINT64_C(3405905920), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_FMAAK_F32_gfx12
    UINT64_C(3405905920), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_FMAAK_F32_gfx1250
    UINT64_C(3476029440), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3405774848), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_FMAC_F32_e32_gfx11
    UINT64_C(3405774848), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_FMAC_F32_e32_gfx12
    UINT64_C(3405774848), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_FMAC_F32_e32_gfx1250
    UINT64_C(3406036992), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_FMAMK_F32_gfx11
    UINT64_C(3406036992), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_FMAMK_F32_gfx12
    UINT64_C(3406036992), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_FMAMK_F32_gfx1250
    UINT64_C(3476107264), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3476099072), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3408003072), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_LSHLREV_B32_e32_gfx11
    UINT64_C(3408003072), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_LSHLREV_B32_e32_gfx12
    UINT64_C(3408003072), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_LSHLREV_B32_e32_gfx1250
    UINT64_C(3476115456), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3408527360), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_LSHRREV_B32_e32_gfx1250
    UINT64_C(3476070400), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3407085568), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MAX_F32_e32_gfx11
    UINT64_C(3407085568), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MAX_F32_e32_gfx12
    UINT64_C(3407085568), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MAX_F32_e32_gfx1250
    UINT64_C(3476123648), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3408789504), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MAX_I32_e32_gfx1250
    UINT64_C(3476074496), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3407216640), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MIN_F32_e32_gfx11
    UINT64_C(3407216640), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MIN_F32_e32_gfx12
    UINT64_C(3407216640), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MIN_F32_e32_gfx1250
    UINT64_C(3476127744), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3408920576), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MIN_I32_e32_gfx1250
    UINT64_C(3476062208), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3406823424), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MOV_B32_e32_gfx11
    UINT64_C(3406823424), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MOV_B32_e32_gfx12
    UINT64_C(3406823424), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MOV_B32_e32_gfx1250
    UINT64_C(3476041728), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3406168064), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MUL_F32_e32_gfx11
    UINT64_C(3406168064), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MUL_F32_e32_gfx12
    UINT64_C(3406168064), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MUL_F32_e32_gfx1250
    UINT64_C(3476058112), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3406692352), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MUL_LEGACY_F32_e32_gfx11
    UINT64_C(3406692352), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MUL_LEGACY_F32_e32_gfx12
    UINT64_C(3406692352), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_MUL_LEGACY_F32_e32_gfx1250
    UINT64_C(3476054016), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3406561280), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_SUBREV_F32_e32_gfx11
    UINT64_C(3406561280), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_SUBREV_F32_e32_gfx12
    UINT64_C(3406561280), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_SUBREV_F32_e32_gfx1250
    UINT64_C(3476049920), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3406430208), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_SUB_F32_e32_gfx11
    UINT64_C(3406430208), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_SUB_F32_e32_gfx12
    UINT64_C(3406430208), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_SUB_F32_e32_gfx1250
    UINT64_C(3476111360), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3408396288), UINT64_C(0),	// V_DUAL_DOT2C_F32_F16_e32_X_SUB_U32_e32_gfx1250
    UINT64_C(3360161792), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_ADD_F32_e32_gfx11
    UINT64_C(3360161792), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_ADD_F32_e32_gfx12
    UINT64_C(3360161792), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_ADD_F32_e32_gfx1250
    UINT64_C(3361734656), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_ADD_U32_e32_gfx11
    UINT64_C(3361734656), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_ADD_U32_e32_gfx12
    UINT64_C(3361734656), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_ADD_U32_e32_gfx1250
    UINT64_C(3361996800), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_AND_B32_e32_gfx11
    UINT64_C(3361996800), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_AND_B32_e32_gfx12
    UINT64_C(3362521088), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_ASHRREV_I32_e32_gfx1250
    UINT64_C(3360817152), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_CNDMASK_B32_e32_gfx11
    UINT64_C(3360817152), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_CNDMASK_B32_e32_gfx12
    UINT64_C(3360817152), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_CNDMASK_B32_e32_gfx1250
    UINT64_C(3361341440), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_DOT2C_F32_BF16_e32_gfx11
    UINT64_C(3361341440), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_DOT2C_F32_BF16_e32_gfx12
    UINT64_C(3361341440), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_DOT2C_F32_BF16_e32_gfx1250
    UINT64_C(3361210368), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_DOT2C_F32_F16_e32_gfx11
    UINT64_C(3361210368), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_DOT2C_F32_F16_e32_gfx12
    UINT64_C(3361210368), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_DOT2C_F32_F16_e32_gfx1250
    UINT64_C(3359768576), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_FMAAK_F32_gfx11
    UINT64_C(3359768576), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_FMAAK_F32_gfx12
    UINT64_C(3359768576), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_FMAAK_F32_gfx1250
    UINT64_C(3359637504), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_FMAC_F32_e32_gfx11
    UINT64_C(3359637504), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_FMAC_F32_e32_gfx12
    UINT64_C(3359637504), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_FMAC_F32_e32_gfx1250
    UINT64_C(3359899648), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_FMAMK_F32_gfx11
    UINT64_C(3359899648), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_FMAMK_F32_gfx12
    UINT64_C(3359899648), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_FMAMK_F32_gfx1250
    UINT64_C(3361865728), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_LSHLREV_B32_e32_gfx11
    UINT64_C(3361865728), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_LSHLREV_B32_e32_gfx12
    UINT64_C(3361865728), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_LSHLREV_B32_e32_gfx1250
    UINT64_C(3362390016), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_LSHRREV_B32_e32_gfx1250
    UINT64_C(3360948224), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_MAX_F32_e32_gfx11
    UINT64_C(3360948224), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_MAX_F32_e32_gfx12
    UINT64_C(3360948224), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_MAX_F32_e32_gfx1250
    UINT64_C(3362652160), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_MAX_I32_e32_gfx1250
    UINT64_C(3361079296), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_MIN_F32_e32_gfx11
    UINT64_C(3361079296), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_MIN_F32_e32_gfx12
    UINT64_C(3361079296), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_MIN_F32_e32_gfx1250
    UINT64_C(3362783232), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_MIN_I32_e32_gfx1250
    UINT64_C(3360686080), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_MOV_B32_e32_gfx11
    UINT64_C(3360686080), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_MOV_B32_e32_gfx12
    UINT64_C(3360686080), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_MOV_B32_e32_gfx1250
    UINT64_C(3360030720), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_MUL_F32_e32_gfx11
    UINT64_C(3360030720), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_MUL_F32_e32_gfx12
    UINT64_C(3360030720), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_MUL_F32_e32_gfx1250
    UINT64_C(3360555008), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_MUL_LEGACY_F32_e32_gfx11
    UINT64_C(3360555008), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_MUL_LEGACY_F32_e32_gfx12
    UINT64_C(3360555008), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_MUL_LEGACY_F32_e32_gfx1250
    UINT64_C(3360423936), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_SUBREV_F32_e32_gfx11
    UINT64_C(3360423936), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_SUBREV_F32_e32_gfx12
    UINT64_C(3360423936), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_SUBREV_F32_e32_gfx1250
    UINT64_C(3360292864), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_SUB_F32_e32_gfx11
    UINT64_C(3360292864), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_SUB_F32_e32_gfx12
    UINT64_C(3360292864), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_SUB_F32_e32_gfx1250
    UINT64_C(3362258944), UINT64_C(0),	// V_DUAL_FMAAK_F32_X_SUB_U32_e32_gfx1250
    UINT64_C(3472900096), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3355967488), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_ADD_F32_e32_gfx11
    UINT64_C(3355967488), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_ADD_F32_e32_gfx12
    UINT64_C(3355967488), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_ADD_F32_e32_gfx1250
    UINT64_C(3472949248), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3357540352), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_ADD_U32_e32_gfx11
    UINT64_C(3357540352), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_ADD_U32_e32_gfx12
    UINT64_C(3357540352), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_ADD_U32_e32_gfx1250
    UINT64_C(3357802496), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_AND_B32_e32_gfx11
    UINT64_C(3357802496), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_AND_B32_e32_gfx12
    UINT64_C(3472973824), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3358326784), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_ASHRREV_I32_e32_gfx1250
    UINT64_C(3472957440), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3472920576), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3356622848), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_gfx11
    UINT64_C(3356622848), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_gfx12
    UINT64_C(3356622848), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_gfx1250
    UINT64_C(3472936960), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3357147136), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_DOT2C_F32_BF16_e32_gfx11
    UINT64_C(3357147136), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_DOT2C_F32_BF16_e32_gfx12
    UINT64_C(3357147136), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250
    UINT64_C(3472932864), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3357016064), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_DOT2C_F32_F16_e32_gfx11
    UINT64_C(3357016064), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_DOT2C_F32_F16_e32_gfx12
    UINT64_C(3357016064), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_DOT2C_F32_F16_e32_gfx1250
    UINT64_C(3355574272), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_FMAAK_F32_gfx11
    UINT64_C(3355574272), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_FMAAK_F32_gfx12
    UINT64_C(3355574272), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_FMAAK_F32_gfx1250
    UINT64_C(3472883712), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3355443200), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_FMAC_F32_e32_gfx11
    UINT64_C(3355443200), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_FMAC_F32_e32_gfx12
    UINT64_C(3355443200), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_FMAC_F32_e32_gfx1250
    UINT64_C(3355705344), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_FMAMK_F32_gfx11
    UINT64_C(3355705344), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_FMAMK_F32_gfx12
    UINT64_C(3355705344), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_FMAMK_F32_gfx1250
    UINT64_C(3472961536), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3472953344), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3357671424), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_LSHLREV_B32_e32_gfx11
    UINT64_C(3357671424), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_LSHLREV_B32_e32_gfx12
    UINT64_C(3357671424), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_LSHLREV_B32_e32_gfx1250
    UINT64_C(3472969728), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3358195712), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_LSHRREV_B32_e32_gfx1250
    UINT64_C(3472924672), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3356753920), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MAX_F32_e32_gfx11
    UINT64_C(3356753920), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MAX_F32_e32_gfx12
    UINT64_C(3356753920), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MAX_F32_e32_gfx1250
    UINT64_C(3472977920), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3358457856), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MAX_I32_e32_gfx1250
    UINT64_C(3472928768), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3356884992), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MIN_F32_e32_gfx11
    UINT64_C(3356884992), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MIN_F32_e32_gfx12
    UINT64_C(3356884992), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MIN_F32_e32_gfx1250
    UINT64_C(3472982016), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3358588928), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MIN_I32_e32_gfx1250
    UINT64_C(3472916480), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3356491776), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MOV_B32_e32_gfx11
    UINT64_C(3356491776), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MOV_B32_e32_gfx12
    UINT64_C(3356491776), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MOV_B32_e32_gfx1250
    UINT64_C(3472896000), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3355836416), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MUL_F32_e32_gfx11
    UINT64_C(3355836416), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MUL_F32_e32_gfx12
    UINT64_C(3355836416), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MUL_F32_e32_gfx1250
    UINT64_C(3472912384), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3356360704), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MUL_LEGACY_F32_e32_gfx11
    UINT64_C(3356360704), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MUL_LEGACY_F32_e32_gfx12
    UINT64_C(3356360704), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250
    UINT64_C(3472908288), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3356229632), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_SUBREV_F32_e32_gfx11
    UINT64_C(3356229632), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_SUBREV_F32_e32_gfx12
    UINT64_C(3356229632), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_SUBREV_F32_e32_gfx1250
    UINT64_C(3472904192), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3356098560), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_SUB_F32_e32_gfx11
    UINT64_C(3356098560), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_SUB_F32_e32_gfx12
    UINT64_C(3356098560), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_SUB_F32_e32_gfx1250
    UINT64_C(3472965632), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3358064640), UINT64_C(0),	// V_DUAL_FMAC_F32_e32_X_SUB_U32_e32_gfx1250
    UINT64_C(3364356096), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_ADD_F32_e32_gfx11
    UINT64_C(3364356096), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_ADD_F32_e32_gfx12
    UINT64_C(3364356096), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_ADD_F32_e32_gfx1250
    UINT64_C(3365928960), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_ADD_U32_e32_gfx11
    UINT64_C(3365928960), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_ADD_U32_e32_gfx12
    UINT64_C(3365928960), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_ADD_U32_e32_gfx1250
    UINT64_C(3366191104), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_AND_B32_e32_gfx11
    UINT64_C(3366191104), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_AND_B32_e32_gfx12
    UINT64_C(3366715392), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_ASHRREV_I32_e32_gfx1250
    UINT64_C(3365011456), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_CNDMASK_B32_e32_gfx11
    UINT64_C(3365011456), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_CNDMASK_B32_e32_gfx12
    UINT64_C(3365011456), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_CNDMASK_B32_e32_gfx1250
    UINT64_C(3365535744), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_DOT2C_F32_BF16_e32_gfx11
    UINT64_C(3365535744), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_DOT2C_F32_BF16_e32_gfx12
    UINT64_C(3365535744), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_DOT2C_F32_BF16_e32_gfx1250
    UINT64_C(3365404672), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_DOT2C_F32_F16_e32_gfx11
    UINT64_C(3365404672), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_DOT2C_F32_F16_e32_gfx12
    UINT64_C(3365404672), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_DOT2C_F32_F16_e32_gfx1250
    UINT64_C(3363962880), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_FMAAK_F32_gfx11
    UINT64_C(3363962880), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_FMAAK_F32_gfx12
    UINT64_C(3363962880), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_FMAAK_F32_gfx1250
    UINT64_C(3363831808), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_FMAC_F32_e32_gfx11
    UINT64_C(3363831808), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_FMAC_F32_e32_gfx12
    UINT64_C(3363831808), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_FMAC_F32_e32_gfx1250
    UINT64_C(3364093952), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_FMAMK_F32_gfx11
    UINT64_C(3364093952), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_FMAMK_F32_gfx12
    UINT64_C(3364093952), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_FMAMK_F32_gfx1250
    UINT64_C(3366060032), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_LSHLREV_B32_e32_gfx11
    UINT64_C(3366060032), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_LSHLREV_B32_e32_gfx12
    UINT64_C(3366060032), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_LSHLREV_B32_e32_gfx1250
    UINT64_C(3366584320), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_LSHRREV_B32_e32_gfx1250
    UINT64_C(3365142528), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_MAX_F32_e32_gfx11
    UINT64_C(3365142528), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_MAX_F32_e32_gfx12
    UINT64_C(3365142528), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_MAX_F32_e32_gfx1250
    UINT64_C(3366846464), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_MAX_I32_e32_gfx1250
    UINT64_C(3365273600), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_MIN_F32_e32_gfx11
    UINT64_C(3365273600), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_MIN_F32_e32_gfx12
    UINT64_C(3365273600), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_MIN_F32_e32_gfx1250
    UINT64_C(3366977536), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_MIN_I32_e32_gfx1250
    UINT64_C(3364880384), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_MOV_B32_e32_gfx11
    UINT64_C(3364880384), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_MOV_B32_e32_gfx12
    UINT64_C(3364880384), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_MOV_B32_e32_gfx1250
    UINT64_C(3364225024), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_MUL_F32_e32_gfx11
    UINT64_C(3364225024), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_MUL_F32_e32_gfx12
    UINT64_C(3364225024), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_MUL_F32_e32_gfx1250
    UINT64_C(3364749312), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_MUL_LEGACY_F32_e32_gfx11
    UINT64_C(3364749312), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_MUL_LEGACY_F32_e32_gfx12
    UINT64_C(3364749312), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_MUL_LEGACY_F32_e32_gfx1250
    UINT64_C(3364618240), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_SUBREV_F32_e32_gfx11
    UINT64_C(3364618240), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_SUBREV_F32_e32_gfx12
    UINT64_C(3364618240), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_SUBREV_F32_e32_gfx1250
    UINT64_C(3364487168), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_SUB_F32_e32_gfx11
    UINT64_C(3364487168), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_SUB_F32_e32_gfx12
    UINT64_C(3364487168), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_SUB_F32_e32_gfx1250
    UINT64_C(3366453248), UINT64_C(0),	// V_DUAL_FMAMK_F32_X_SUB_U32_e32_gfx1250
    UINT64_C(3477880832), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3477929984), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3477954560), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3477938176), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3477901312), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3477917696), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3477913600), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3477864448), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3477942272), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3477934080), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3477950464), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3477905408), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3477958656), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3477909504), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3477962752), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3477897216), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3477876736), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3477893120), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3477889024), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3477884928), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3477946368), UINT64_C(0),	// V_DUAL_FMA_F32_e64_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3481288704), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3481337856), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3481362432), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3481346048), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3481309184), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3481325568), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3481321472), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3481272320), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3481350144), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3481341952), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3481358336), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3481313280), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3481366528), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3481317376), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3481370624), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3481305088), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3481284608), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3481300992), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3481296896), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3481292800), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3481354240), UINT64_C(0),	// V_DUAL_FMA_F64_e64_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3477356544), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3477405696), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3477430272), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3477413888), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3477377024), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3477393408), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3477389312), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3477340160), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3477417984), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3477409792), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3477426176), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3477381120), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3477434368), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3477385216), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3477438464), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3477372928), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3477352448), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3477368832), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3477364736), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3477360640), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3477422080), UINT64_C(0),	// V_DUAL_LSHLREV_B32_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3478405120), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3478454272), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3478478848), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3478462464), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3478425600), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3478441984), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3478437888), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3478388736), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3478466560), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3478458368), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3478474752), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3478429696), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3478482944), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3478433792), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3478487040), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3478421504), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3478401024), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3478417408), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3478413312), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3478409216), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3478470656), UINT64_C(0),	// V_DUAL_LSHRREV_B32_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3475521536), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3397910528), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_ADD_F32_e32_gfx11
    UINT64_C(3397910528), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_ADD_F32_e32_gfx12
    UINT64_C(3397910528), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_ADD_F32_e32_gfx1250
    UINT64_C(3475570688), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3399483392), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_ADD_U32_e32_gfx11
    UINT64_C(3399483392), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_ADD_U32_e32_gfx12
    UINT64_C(3399483392), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_ADD_U32_e32_gfx1250
    UINT64_C(3399745536), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_AND_B32_e32_gfx11
    UINT64_C(3399745536), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_AND_B32_e32_gfx12
    UINT64_C(3475595264), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3400269824), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_ASHRREV_I32_e32_gfx1250
    UINT64_C(3475578880), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3475542016), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3398565888), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_CNDMASK_B32_e32_gfx11
    UINT64_C(3398565888), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_CNDMASK_B32_e32_gfx12
    UINT64_C(3398565888), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_CNDMASK_B32_e32_gfx1250
    UINT64_C(3475558400), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3399090176), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_DOT2C_F32_BF16_e32_gfx11
    UINT64_C(3399090176), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_DOT2C_F32_BF16_e32_gfx12
    UINT64_C(3399090176), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250
    UINT64_C(3475554304), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3398959104), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_DOT2C_F32_F16_e32_gfx11
    UINT64_C(3398959104), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_DOT2C_F32_F16_e32_gfx12
    UINT64_C(3398959104), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_DOT2C_F32_F16_e32_gfx1250
    UINT64_C(3397517312), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_FMAAK_F32_gfx11
    UINT64_C(3397517312), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_FMAAK_F32_gfx12
    UINT64_C(3397517312), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_FMAAK_F32_gfx1250
    UINT64_C(3475505152), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3397386240), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_FMAC_F32_e32_gfx11
    UINT64_C(3397386240), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_FMAC_F32_e32_gfx12
    UINT64_C(3397386240), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_FMAC_F32_e32_gfx1250
    UINT64_C(3397648384), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_FMAMK_F32_gfx11
    UINT64_C(3397648384), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_FMAMK_F32_gfx12
    UINT64_C(3397648384), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_FMAMK_F32_gfx1250
    UINT64_C(3475582976), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3475574784), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3399614464), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_LSHLREV_B32_e32_gfx11
    UINT64_C(3399614464), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_LSHLREV_B32_e32_gfx12
    UINT64_C(3399614464), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_LSHLREV_B32_e32_gfx1250
    UINT64_C(3475591168), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3400138752), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_LSHRREV_B32_e32_gfx1250
    UINT64_C(3475546112), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3398696960), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MAX_F32_e32_gfx11
    UINT64_C(3398696960), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MAX_F32_e32_gfx12
    UINT64_C(3398696960), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MAX_F32_e32_gfx1250
    UINT64_C(3475599360), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3400400896), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MAX_I32_e32_gfx1250
    UINT64_C(3475550208), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3398828032), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MIN_F32_e32_gfx11
    UINT64_C(3398828032), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MIN_F32_e32_gfx12
    UINT64_C(3398828032), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MIN_F32_e32_gfx1250
    UINT64_C(3475603456), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3400531968), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MIN_I32_e32_gfx1250
    UINT64_C(3475537920), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3398434816), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MOV_B32_e32_gfx11
    UINT64_C(3398434816), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MOV_B32_e32_gfx12
    UINT64_C(3398434816), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MOV_B32_e32_gfx1250
    UINT64_C(3475517440), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3397779456), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MUL_F32_e32_gfx11
    UINT64_C(3397779456), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MUL_F32_e32_gfx12
    UINT64_C(3397779456), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MUL_F32_e32_gfx1250
    UINT64_C(3475533824), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3398303744), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MUL_LEGACY_F32_e32_gfx11
    UINT64_C(3398303744), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MUL_LEGACY_F32_e32_gfx12
    UINT64_C(3398303744), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250
    UINT64_C(3475529728), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3398172672), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_SUBREV_F32_e32_gfx11
    UINT64_C(3398172672), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_SUBREV_F32_e32_gfx12
    UINT64_C(3398172672), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_SUBREV_F32_e32_gfx1250
    UINT64_C(3475525632), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3398041600), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_SUB_F32_e32_gfx11
    UINT64_C(3398041600), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_SUB_F32_e32_gfx12
    UINT64_C(3398041600), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_SUB_F32_e32_gfx1250
    UINT64_C(3475587072), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3400007680), UINT64_C(0),	// V_DUAL_MAX_F32_e32_X_SUB_U32_e32_gfx1250
    UINT64_C(3482075136), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3482124288), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3482148864), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3482132480), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3482095616), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3482112000), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3482107904), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3482058752), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3482136576), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3482128384), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3482144768), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3482099712), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3482152960), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3482103808), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3482157056), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3482091520), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3482071040), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3482087424), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3482083328), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3482079232), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3482140672), UINT64_C(0),	// V_DUAL_MAX_NUM_F64_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3475783680), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3402104832), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_ADD_F32_e32_gfx11
    UINT64_C(3402104832), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_ADD_F32_e32_gfx12
    UINT64_C(3402104832), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_ADD_F32_e32_gfx1250
    UINT64_C(3475832832), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3403677696), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_ADD_U32_e32_gfx11
    UINT64_C(3403677696), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_ADD_U32_e32_gfx12
    UINT64_C(3403677696), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_ADD_U32_e32_gfx1250
    UINT64_C(3403939840), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_AND_B32_e32_gfx11
    UINT64_C(3403939840), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_AND_B32_e32_gfx12
    UINT64_C(3475857408), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3404464128), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_ASHRREV_I32_e32_gfx1250
    UINT64_C(3475841024), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3475804160), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3402760192), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_CNDMASK_B32_e32_gfx11
    UINT64_C(3402760192), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_CNDMASK_B32_e32_gfx12
    UINT64_C(3402760192), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_CNDMASK_B32_e32_gfx1250
    UINT64_C(3475820544), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3403284480), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_DOT2C_F32_BF16_e32_gfx11
    UINT64_C(3403284480), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_DOT2C_F32_BF16_e32_gfx12
    UINT64_C(3403284480), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250
    UINT64_C(3475816448), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3403153408), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_DOT2C_F32_F16_e32_gfx11
    UINT64_C(3403153408), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_DOT2C_F32_F16_e32_gfx12
    UINT64_C(3403153408), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_DOT2C_F32_F16_e32_gfx1250
    UINT64_C(3401711616), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_FMAAK_F32_gfx11
    UINT64_C(3401711616), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_FMAAK_F32_gfx12
    UINT64_C(3401711616), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_FMAAK_F32_gfx1250
    UINT64_C(3475767296), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3401580544), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_FMAC_F32_e32_gfx11
    UINT64_C(3401580544), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_FMAC_F32_e32_gfx12
    UINT64_C(3401580544), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_FMAC_F32_e32_gfx1250
    UINT64_C(3401842688), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_FMAMK_F32_gfx11
    UINT64_C(3401842688), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_FMAMK_F32_gfx12
    UINT64_C(3401842688), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_FMAMK_F32_gfx1250
    UINT64_C(3475845120), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3475836928), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3403808768), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_LSHLREV_B32_e32_gfx11
    UINT64_C(3403808768), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_LSHLREV_B32_e32_gfx12
    UINT64_C(3403808768), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_LSHLREV_B32_e32_gfx1250
    UINT64_C(3475853312), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3404333056), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_LSHRREV_B32_e32_gfx1250
    UINT64_C(3475808256), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3402891264), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MAX_F32_e32_gfx11
    UINT64_C(3402891264), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MAX_F32_e32_gfx12
    UINT64_C(3402891264), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MAX_F32_e32_gfx1250
    UINT64_C(3475861504), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3404595200), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MAX_I32_e32_gfx1250
    UINT64_C(3475812352), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3403022336), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MIN_F32_e32_gfx11
    UINT64_C(3403022336), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MIN_F32_e32_gfx12
    UINT64_C(3403022336), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MIN_F32_e32_gfx1250
    UINT64_C(3475865600), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3404726272), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MIN_I32_e32_gfx1250
    UINT64_C(3475800064), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3402629120), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MOV_B32_e32_gfx11
    UINT64_C(3402629120), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MOV_B32_e32_gfx12
    UINT64_C(3402629120), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MOV_B32_e32_gfx1250
    UINT64_C(3475779584), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3401973760), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MUL_F32_e32_gfx11
    UINT64_C(3401973760), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MUL_F32_e32_gfx12
    UINT64_C(3401973760), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MUL_F32_e32_gfx1250
    UINT64_C(3475795968), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3402498048), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MUL_LEGACY_F32_e32_gfx11
    UINT64_C(3402498048), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MUL_LEGACY_F32_e32_gfx12
    UINT64_C(3402498048), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250
    UINT64_C(3475791872), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3402366976), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_SUBREV_F32_e32_gfx11
    UINT64_C(3402366976), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_SUBREV_F32_e32_gfx12
    UINT64_C(3402366976), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_SUBREV_F32_e32_gfx1250
    UINT64_C(3475787776), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3402235904), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_SUB_F32_e32_gfx11
    UINT64_C(3402235904), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_SUB_F32_e32_gfx12
    UINT64_C(3402235904), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_SUB_F32_e32_gfx1250
    UINT64_C(3475849216), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3404201984), UINT64_C(0),	// V_DUAL_MIN_F32_e32_X_SUB_U32_e32_gfx1250
    UINT64_C(3482337280), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3482386432), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3482411008), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3482394624), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3482357760), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3482374144), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3482370048), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3482320896), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3482398720), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3482390528), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3482406912), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3482361856), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3482415104), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3482365952), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3482419200), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3482353664), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3482333184), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3482349568), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3482345472), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3482341376), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3482402816), UINT64_C(0),	// V_DUAL_MIN_NUM_F64_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3474997248), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3389521920), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_ADD_F32_e32_gfx11
    UINT64_C(3389521920), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_ADD_F32_e32_gfx12
    UINT64_C(3389521920), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_ADD_F32_e32_gfx1250
    UINT64_C(3475046400), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3391094784), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_ADD_U32_e32_gfx11
    UINT64_C(3391094784), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_ADD_U32_e32_gfx12
    UINT64_C(3391094784), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_ADD_U32_e32_gfx1250
    UINT64_C(3391356928), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_AND_B32_e32_gfx11
    UINT64_C(3391356928), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_AND_B32_e32_gfx12
    UINT64_C(3475070976), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3391881216), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_ASHRREV_I32_e32_gfx1250
    UINT64_C(3475054592), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3475017728), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3390177280), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_CNDMASK_B32_e32_gfx11
    UINT64_C(3390177280), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_CNDMASK_B32_e32_gfx12
    UINT64_C(3390177280), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_CNDMASK_B32_e32_gfx1250
    UINT64_C(3475034112), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3390701568), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_DOT2C_F32_BF16_e32_gfx11
    UINT64_C(3390701568), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_DOT2C_F32_BF16_e32_gfx12
    UINT64_C(3390701568), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_DOT2C_F32_BF16_e32_gfx1250
    UINT64_C(3475030016), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3390570496), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_DOT2C_F32_F16_e32_gfx11
    UINT64_C(3390570496), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_DOT2C_F32_F16_e32_gfx12
    UINT64_C(3390570496), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_DOT2C_F32_F16_e32_gfx1250
    UINT64_C(3389128704), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_FMAAK_F32_gfx11
    UINT64_C(3389128704), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_FMAAK_F32_gfx12
    UINT64_C(3389128704), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_FMAAK_F32_gfx1250
    UINT64_C(3474980864), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3388997632), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_FMAC_F32_e32_gfx11
    UINT64_C(3388997632), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_FMAC_F32_e32_gfx12
    UINT64_C(3388997632), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_FMAC_F32_e32_gfx1250
    UINT64_C(3389259776), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_FMAMK_F32_gfx11
    UINT64_C(3389259776), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_FMAMK_F32_gfx12
    UINT64_C(3389259776), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_FMAMK_F32_gfx1250
    UINT64_C(3475058688), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3475050496), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3391225856), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_LSHLREV_B32_e32_gfx11
    UINT64_C(3391225856), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_LSHLREV_B32_e32_gfx12
    UINT64_C(3391225856), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_LSHLREV_B32_e32_gfx1250
    UINT64_C(3475066880), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3391750144), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_LSHRREV_B32_e32_gfx1250
    UINT64_C(3475021824), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3390308352), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MAX_F32_e32_gfx11
    UINT64_C(3390308352), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MAX_F32_e32_gfx12
    UINT64_C(3390308352), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MAX_F32_e32_gfx1250
    UINT64_C(3475075072), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3392012288), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MAX_I32_e32_gfx1250
    UINT64_C(3475025920), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3390439424), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MIN_F32_e32_gfx11
    UINT64_C(3390439424), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MIN_F32_e32_gfx12
    UINT64_C(3390439424), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MIN_F32_e32_gfx1250
    UINT64_C(3475079168), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3392143360), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MIN_I32_e32_gfx1250
    UINT64_C(3475013632), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3390046208), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx11
    UINT64_C(3390046208), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx12
    UINT64_C(3390046208), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx1250
    UINT64_C(3474993152), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3389390848), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MUL_F32_e32_gfx11
    UINT64_C(3389390848), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MUL_F32_e32_gfx12
    UINT64_C(3389390848), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MUL_F32_e32_gfx1250
    UINT64_C(3475009536), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3389915136), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MUL_LEGACY_F32_e32_gfx11
    UINT64_C(3389915136), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MUL_LEGACY_F32_e32_gfx12
    UINT64_C(3389915136), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_MUL_LEGACY_F32_e32_gfx1250
    UINT64_C(3475005440), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3389784064), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_SUBREV_F32_e32_gfx11
    UINT64_C(3389784064), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_SUBREV_F32_e32_gfx12
    UINT64_C(3389784064), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_SUBREV_F32_e32_gfx1250
    UINT64_C(3475001344), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3389652992), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_SUB_F32_e32_gfx11
    UINT64_C(3389652992), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_SUB_F32_e32_gfx12
    UINT64_C(3389652992), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_SUB_F32_e32_gfx1250
    UINT64_C(3475062784), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3391619072), UINT64_C(0),	// V_DUAL_MOV_B32_e32_X_SUB_U32_e32_gfx1250
    UINT64_C(3473686528), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3368550400), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_ADD_F32_e32_gfx11
    UINT64_C(3368550400), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_ADD_F32_e32_gfx12
    UINT64_C(3368550400), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_ADD_F32_e32_gfx1250
    UINT64_C(3473735680), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3370123264), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_ADD_U32_e32_gfx11
    UINT64_C(3370123264), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_ADD_U32_e32_gfx12
    UINT64_C(3370123264), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_ADD_U32_e32_gfx1250
    UINT64_C(3370385408), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_AND_B32_e32_gfx11
    UINT64_C(3370385408), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_AND_B32_e32_gfx12
    UINT64_C(3473760256), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3370909696), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_ASHRREV_I32_e32_gfx1250
    UINT64_C(3473743872), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3473707008), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3369205760), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32_gfx11
    UINT64_C(3369205760), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32_gfx12
    UINT64_C(3369205760), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32_gfx1250
    UINT64_C(3473723392), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3369730048), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_DOT2C_F32_BF16_e32_gfx11
    UINT64_C(3369730048), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_DOT2C_F32_BF16_e32_gfx12
    UINT64_C(3369730048), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250
    UINT64_C(3473719296), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3369598976), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_DOT2C_F32_F16_e32_gfx11
    UINT64_C(3369598976), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_DOT2C_F32_F16_e32_gfx12
    UINT64_C(3369598976), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_DOT2C_F32_F16_e32_gfx1250
    UINT64_C(3368157184), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_FMAAK_F32_gfx11
    UINT64_C(3368157184), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_FMAAK_F32_gfx12
    UINT64_C(3368157184), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_FMAAK_F32_gfx1250
    UINT64_C(3473670144), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3368026112), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_FMAC_F32_e32_gfx11
    UINT64_C(3368026112), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_FMAC_F32_e32_gfx12
    UINT64_C(3368026112), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_FMAC_F32_e32_gfx1250
    UINT64_C(3368288256), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_FMAMK_F32_gfx11
    UINT64_C(3368288256), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_FMAMK_F32_gfx12
    UINT64_C(3368288256), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_FMAMK_F32_gfx1250
    UINT64_C(3473747968), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3473739776), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3370254336), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_LSHLREV_B32_e32_gfx11
    UINT64_C(3370254336), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_LSHLREV_B32_e32_gfx12
    UINT64_C(3370254336), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_LSHLREV_B32_e32_gfx1250
    UINT64_C(3473756160), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3370778624), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_LSHRREV_B32_e32_gfx1250
    UINT64_C(3473711104), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3369336832), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MAX_F32_e32_gfx11
    UINT64_C(3369336832), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MAX_F32_e32_gfx12
    UINT64_C(3369336832), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MAX_F32_e32_gfx1250
    UINT64_C(3473764352), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3371040768), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MAX_I32_e32_gfx1250
    UINT64_C(3473715200), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3369467904), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MIN_F32_e32_gfx11
    UINT64_C(3369467904), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MIN_F32_e32_gfx12
    UINT64_C(3369467904), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MIN_F32_e32_gfx1250
    UINT64_C(3473768448), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3371171840), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MIN_I32_e32_gfx1250
    UINT64_C(3473702912), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3369074688), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MOV_B32_e32_gfx11
    UINT64_C(3369074688), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MOV_B32_e32_gfx12
    UINT64_C(3369074688), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MOV_B32_e32_gfx1250
    UINT64_C(3473682432), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3368419328), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MUL_F32_e32_gfx11
    UINT64_C(3368419328), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MUL_F32_e32_gfx12
    UINT64_C(3368419328), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MUL_F32_e32_gfx1250
    UINT64_C(3473698816), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3368943616), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MUL_LEGACY_F32_e32_gfx11
    UINT64_C(3368943616), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MUL_LEGACY_F32_e32_gfx12
    UINT64_C(3368943616), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250
    UINT64_C(3473694720), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3368812544), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_SUBREV_F32_e32_gfx11
    UINT64_C(3368812544), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_SUBREV_F32_e32_gfx12
    UINT64_C(3368812544), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_SUBREV_F32_e32_gfx1250
    UINT64_C(3473690624), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3368681472), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_SUB_F32_e32_gfx11
    UINT64_C(3368681472), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_SUB_F32_e32_gfx12
    UINT64_C(3368681472), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_SUB_F32_e32_gfx1250
    UINT64_C(3473752064), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3370647552), UINT64_C(0),	// V_DUAL_MUL_F32_e32_X_SUB_U32_e32_gfx1250
    UINT64_C(3481812992), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3481862144), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3481886720), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3481870336), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3481833472), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3481849856), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3481845760), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3481796608), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3481874432), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3481866240), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3481882624), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3481837568), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3481890816), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3481841664), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3481894912), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3481829376), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3481808896), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3481825280), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3481821184), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3481817088), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3481878528), UINT64_C(0),	// V_DUAL_MUL_F64_pseudo_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3474735104), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3385327616), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_ADD_F32_e32_gfx11
    UINT64_C(3385327616), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_ADD_F32_e32_gfx12
    UINT64_C(3385327616), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_ADD_F32_e32_gfx1250
    UINT64_C(3474784256), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3386900480), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_ADD_U32_e32_gfx11
    UINT64_C(3386900480), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_ADD_U32_e32_gfx12
    UINT64_C(3386900480), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_ADD_U32_e32_gfx1250
    UINT64_C(3387162624), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_AND_B32_e32_gfx11
    UINT64_C(3387162624), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_AND_B32_e32_gfx12
    UINT64_C(3474808832), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3387686912), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_ASHRREV_I32_e32_gfx1250
    UINT64_C(3474792448), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3474755584), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3385982976), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_CNDMASK_B32_e32_gfx11
    UINT64_C(3385982976), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_CNDMASK_B32_e32_gfx12
    UINT64_C(3385982976), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_CNDMASK_B32_e32_gfx1250
    UINT64_C(3474771968), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3386507264), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_BF16_e32_gfx11
    UINT64_C(3386507264), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_BF16_e32_gfx12
    UINT64_C(3386507264), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250
    UINT64_C(3474767872), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3386376192), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_F16_e32_gfx11
    UINT64_C(3386376192), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_F16_e32_gfx12
    UINT64_C(3386376192), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_F16_e32_gfx1250
    UINT64_C(3384934400), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_FMAAK_F32_gfx11
    UINT64_C(3384934400), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_FMAAK_F32_gfx12
    UINT64_C(3384934400), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_FMAAK_F32_gfx1250
    UINT64_C(3474718720), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3384803328), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_FMAC_F32_e32_gfx11
    UINT64_C(3384803328), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_FMAC_F32_e32_gfx12
    UINT64_C(3384803328), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_FMAC_F32_e32_gfx1250
    UINT64_C(3385065472), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_FMAMK_F32_gfx11
    UINT64_C(3385065472), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_FMAMK_F32_gfx12
    UINT64_C(3385065472), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_FMAMK_F32_gfx1250
    UINT64_C(3474796544), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3474788352), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3387031552), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_LSHLREV_B32_e32_gfx11
    UINT64_C(3387031552), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_LSHLREV_B32_e32_gfx12
    UINT64_C(3387031552), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_LSHLREV_B32_e32_gfx1250
    UINT64_C(3474804736), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3387555840), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_LSHRREV_B32_e32_gfx1250
    UINT64_C(3474759680), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3386114048), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MAX_F32_e32_gfx11
    UINT64_C(3386114048), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MAX_F32_e32_gfx12
    UINT64_C(3386114048), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MAX_F32_e32_gfx1250
    UINT64_C(3474812928), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3387817984), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MAX_I32_e32_gfx1250
    UINT64_C(3474763776), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3386245120), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MIN_F32_e32_gfx11
    UINT64_C(3386245120), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MIN_F32_e32_gfx12
    UINT64_C(3386245120), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MIN_F32_e32_gfx1250
    UINT64_C(3474817024), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3387949056), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MIN_I32_e32_gfx1250
    UINT64_C(3474751488), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3385851904), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MOV_B32_e32_gfx11
    UINT64_C(3385851904), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MOV_B32_e32_gfx12
    UINT64_C(3385851904), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MOV_B32_e32_gfx1250
    UINT64_C(3474731008), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3385196544), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MUL_F32_e32_gfx11
    UINT64_C(3385196544), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MUL_F32_e32_gfx12
    UINT64_C(3385196544), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MUL_F32_e32_gfx1250
    UINT64_C(3474747392), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3385720832), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MUL_LEGACY_F32_e32_gfx11
    UINT64_C(3385720832), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MUL_LEGACY_F32_e32_gfx12
    UINT64_C(3385720832), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250
    UINT64_C(3474743296), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3385589760), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_SUBREV_F32_e32_gfx11
    UINT64_C(3385589760), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_SUBREV_F32_e32_gfx12
    UINT64_C(3385589760), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_SUBREV_F32_e32_gfx1250
    UINT64_C(3474739200), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3385458688), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_SUB_F32_e32_gfx11
    UINT64_C(3385458688), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_SUB_F32_e32_gfx12
    UINT64_C(3385458688), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_SUB_F32_e32_gfx1250
    UINT64_C(3474800640), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3387424768), UINT64_C(0),	// V_DUAL_MUL_LEGACY_F32_e32_X_SUB_U32_e32_gfx1250
    UINT64_C(3474472960), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3381133312), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_ADD_F32_e32_gfx11
    UINT64_C(3381133312), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_ADD_F32_e32_gfx12
    UINT64_C(3381133312), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_ADD_F32_e32_gfx1250
    UINT64_C(3474522112), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3382706176), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_ADD_U32_e32_gfx11
    UINT64_C(3382706176), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_ADD_U32_e32_gfx12
    UINT64_C(3382706176), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_ADD_U32_e32_gfx1250
    UINT64_C(3382968320), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_AND_B32_e32_gfx11
    UINT64_C(3382968320), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_AND_B32_e32_gfx12
    UINT64_C(3474546688), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3383492608), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_ASHRREV_I32_e32_gfx1250
    UINT64_C(3474530304), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3474493440), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3381788672), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_CNDMASK_B32_e32_gfx11
    UINT64_C(3381788672), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_CNDMASK_B32_e32_gfx12
    UINT64_C(3381788672), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_CNDMASK_B32_e32_gfx1250
    UINT64_C(3474509824), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3382312960), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_BF16_e32_gfx11
    UINT64_C(3382312960), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_BF16_e32_gfx12
    UINT64_C(3382312960), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250
    UINT64_C(3474505728), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3382181888), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_F16_e32_gfx11
    UINT64_C(3382181888), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_F16_e32_gfx12
    UINT64_C(3382181888), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_F16_e32_gfx1250
    UINT64_C(3380740096), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_FMAAK_F32_gfx11
    UINT64_C(3380740096), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_FMAAK_F32_gfx12
    UINT64_C(3380740096), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_FMAAK_F32_gfx1250
    UINT64_C(3474456576), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3380609024), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_FMAC_F32_e32_gfx11
    UINT64_C(3380609024), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_FMAC_F32_e32_gfx12
    UINT64_C(3380609024), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_FMAC_F32_e32_gfx1250
    UINT64_C(3380871168), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_FMAMK_F32_gfx11
    UINT64_C(3380871168), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_FMAMK_F32_gfx12
    UINT64_C(3380871168), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_FMAMK_F32_gfx1250
    UINT64_C(3474534400), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3474526208), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3382837248), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_LSHLREV_B32_e32_gfx11
    UINT64_C(3382837248), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_LSHLREV_B32_e32_gfx12
    UINT64_C(3382837248), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_LSHLREV_B32_e32_gfx1250
    UINT64_C(3474542592), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3383361536), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_LSHRREV_B32_e32_gfx1250
    UINT64_C(3474497536), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3381919744), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MAX_F32_e32_gfx11
    UINT64_C(3381919744), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MAX_F32_e32_gfx12
    UINT64_C(3381919744), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MAX_F32_e32_gfx1250
    UINT64_C(3474550784), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3383623680), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MAX_I32_e32_gfx1250
    UINT64_C(3474501632), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3382050816), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MIN_F32_e32_gfx11
    UINT64_C(3382050816), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MIN_F32_e32_gfx12
    UINT64_C(3382050816), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MIN_F32_e32_gfx1250
    UINT64_C(3474554880), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3383754752), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MIN_I32_e32_gfx1250
    UINT64_C(3474489344), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3381657600), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MOV_B32_e32_gfx11
    UINT64_C(3381657600), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MOV_B32_e32_gfx12
    UINT64_C(3381657600), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MOV_B32_e32_gfx1250
    UINT64_C(3474468864), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3381002240), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MUL_F32_e32_gfx11
    UINT64_C(3381002240), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MUL_F32_e32_gfx12
    UINT64_C(3381002240), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MUL_F32_e32_gfx1250
    UINT64_C(3474485248), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3381526528), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MUL_LEGACY_F32_e32_gfx11
    UINT64_C(3381526528), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MUL_LEGACY_F32_e32_gfx12
    UINT64_C(3381526528), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250
    UINT64_C(3474481152), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3381395456), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_SUBREV_F32_e32_gfx11
    UINT64_C(3381395456), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_SUBREV_F32_e32_gfx12
    UINT64_C(3381395456), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_SUBREV_F32_e32_gfx1250
    UINT64_C(3474477056), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3381264384), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_SUB_F32_e32_gfx11
    UINT64_C(3381264384), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_SUB_F32_e32_gfx12
    UINT64_C(3381264384), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_SUB_F32_e32_gfx1250
    UINT64_C(3474538496), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3383230464), UINT64_C(0),	// V_DUAL_SUBREV_F32_e32_X_SUB_U32_e32_gfx1250
    UINT64_C(3474210816), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3376939008), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_ADD_F32_e32_gfx11
    UINT64_C(3376939008), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_ADD_F32_e32_gfx12
    UINT64_C(3376939008), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_ADD_F32_e32_gfx1250
    UINT64_C(3474259968), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3378511872), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_ADD_U32_e32_gfx11
    UINT64_C(3378511872), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_ADD_U32_e32_gfx12
    UINT64_C(3378511872), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_ADD_U32_e32_gfx1250
    UINT64_C(3378774016), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_AND_B32_e32_gfx11
    UINT64_C(3378774016), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_AND_B32_e32_gfx12
    UINT64_C(3474284544), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3379298304), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_ASHRREV_I32_e32_gfx1250
    UINT64_C(3474268160), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3474231296), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3377594368), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32_gfx11
    UINT64_C(3377594368), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32_gfx12
    UINT64_C(3377594368), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32_gfx1250
    UINT64_C(3474247680), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3378118656), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_DOT2C_F32_BF16_e32_gfx11
    UINT64_C(3378118656), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_DOT2C_F32_BF16_e32_gfx12
    UINT64_C(3378118656), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250
    UINT64_C(3474243584), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3377987584), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_DOT2C_F32_F16_e32_gfx11
    UINT64_C(3377987584), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_DOT2C_F32_F16_e32_gfx12
    UINT64_C(3377987584), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_DOT2C_F32_F16_e32_gfx1250
    UINT64_C(3376545792), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_FMAAK_F32_gfx11
    UINT64_C(3376545792), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_FMAAK_F32_gfx12
    UINT64_C(3376545792), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_FMAAK_F32_gfx1250
    UINT64_C(3474194432), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3376414720), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_FMAC_F32_e32_gfx11
    UINT64_C(3376414720), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_FMAC_F32_e32_gfx12
    UINT64_C(3376414720), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_FMAC_F32_e32_gfx1250
    UINT64_C(3376676864), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_FMAMK_F32_gfx11
    UINT64_C(3376676864), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_FMAMK_F32_gfx12
    UINT64_C(3376676864), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_FMAMK_F32_gfx1250
    UINT64_C(3474272256), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3474264064), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3378642944), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_LSHLREV_B32_e32_gfx11
    UINT64_C(3378642944), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_LSHLREV_B32_e32_gfx12
    UINT64_C(3378642944), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_LSHLREV_B32_e32_gfx1250
    UINT64_C(3474280448), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3379167232), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_LSHRREV_B32_e32_gfx1250
    UINT64_C(3474235392), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3377725440), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MAX_F32_e32_gfx11
    UINT64_C(3377725440), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MAX_F32_e32_gfx12
    UINT64_C(3377725440), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MAX_F32_e32_gfx1250
    UINT64_C(3474288640), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3379429376), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MAX_I32_e32_gfx1250
    UINT64_C(3474239488), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3377856512), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MIN_F32_e32_gfx11
    UINT64_C(3377856512), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MIN_F32_e32_gfx12
    UINT64_C(3377856512), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MIN_F32_e32_gfx1250
    UINT64_C(3474292736), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3379560448), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MIN_I32_e32_gfx1250
    UINT64_C(3474227200), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3377463296), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MOV_B32_e32_gfx11
    UINT64_C(3377463296), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MOV_B32_e32_gfx12
    UINT64_C(3377463296), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MOV_B32_e32_gfx1250
    UINT64_C(3474206720), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3376807936), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx11
    UINT64_C(3376807936), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx12
    UINT64_C(3376807936), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx1250
    UINT64_C(3474223104), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3377332224), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MUL_LEGACY_F32_e32_gfx11
    UINT64_C(3377332224), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MUL_LEGACY_F32_e32_gfx12
    UINT64_C(3377332224), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250
    UINT64_C(3474219008), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3377201152), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_SUBREV_F32_e32_gfx11
    UINT64_C(3377201152), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_SUBREV_F32_e32_gfx12
    UINT64_C(3377201152), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_SUBREV_F32_e32_gfx1250
    UINT64_C(3474214912), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3377070080), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_SUB_F32_e32_gfx11
    UINT64_C(3377070080), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_SUB_F32_e32_gfx12
    UINT64_C(3377070080), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_SUB_F32_e32_gfx1250
    UINT64_C(3474276352), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(3379036160), UINT64_C(0),	// V_DUAL_SUB_F32_e32_X_SUB_U32_e32_gfx1250
    UINT64_C(3478142976), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_ADD_F32_e32_e96_gfx1250
    UINT64_C(3478192128), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_ADD_U32_e32_e96_gfx1250
    UINT64_C(3478216704), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_ASHRREV_I32_e32_e96_gfx1250
    UINT64_C(3478200320), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_BITOP2_B32_e64_e96_gfx1250
    UINT64_C(3478163456), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_CNDMASK_B32_e32_e96_gfx1250
    UINT64_C(3478179840), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250
    UINT64_C(3478175744), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250
    UINT64_C(3478126592), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_FMAC_F32_e32_e96_gfx1250
    UINT64_C(3478204416), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_FMA_F32_e64_e96_gfx1250
    UINT64_C(3478196224), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_LSHLREV_B32_e32_e96_gfx1250
    UINT64_C(3478212608), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_LSHRREV_B32_e32_e96_gfx1250
    UINT64_C(3478167552), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_MAX_F32_e32_e96_gfx1250
    UINT64_C(3478220800), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_MAX_I32_e32_e96_gfx1250
    UINT64_C(3478171648), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_MIN_F32_e32_e96_gfx1250
    UINT64_C(3478224896), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_MIN_I32_e32_e96_gfx1250
    UINT64_C(3478159360), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_MOV_B32_e32_e96_gfx1250
    UINT64_C(3478138880), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_MUL_F32_e32_e96_gfx1250
    UINT64_C(3478155264), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250
    UINT64_C(3478151168), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_SUBREV_F32_e32_e96_gfx1250
    UINT64_C(3478147072), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_SUB_F32_e32_e96_gfx1250
    UINT64_C(3478208512), UINT64_C(0),	// V_DUAL_SUB_U32_e32_X_SUB_U32_e32_e96_gfx1250
    UINT64_C(2113993216), UINT64_C(0),	// V_EXP_BF16V_EXP_BF16_fake16_dpp8_gfx1250
    UINT64_C(2113993466), UINT64_C(0),	// V_EXP_BF16V_EXP_BF16_fake16_dpp_gfx1250
    UINT64_C(2113993216), UINT64_C(0),	// V_EXP_BF16V_EXP_BF16_fake16_e32_gfx1250
    UINT64_C(3590127616), UINT64_C(0),	// V_EXP_BF16V_EXP_BF16_fake16_e64_dpp8_gfx1250
    UINT64_C(1077331951616), UINT64_C(0),	// V_EXP_BF16V_EXP_BF16_fake16_e64_dpp_gfx1250
    UINT64_C(3590127616), UINT64_C(0),	// V_EXP_BF16V_EXP_BF16_fake16_e64_gfx1250
    UINT64_C(2113993216), UINT64_C(0),	// V_EXP_BF16V_EXP_BF16_t16_dpp8_gfx1250
    UINT64_C(2113993466), UINT64_C(0),	// V_EXP_BF16V_EXP_BF16_t16_dpp_gfx1250
    UINT64_C(2113993216), UINT64_C(0),	// V_EXP_BF16V_EXP_BF16_t16_e32_gfx1250
    UINT64_C(3590127616), UINT64_C(0),	// V_EXP_BF16V_EXP_BF16_t16_e64_dpp8_gfx1250
    UINT64_C(1077331951616), UINT64_C(0),	// V_EXP_BF16V_EXP_BF16_t16_e64_dpp_gfx1250
    UINT64_C(3590127616), UINT64_C(0),	// V_EXP_BF16V_EXP_BF16_t16_e64_gfx1250
    UINT64_C(2113974272), UINT64_C(0),	// V_EXP_F16_dpp8_gfx10
    UINT64_C(2113974522), UINT64_C(0),	// V_EXP_F16_dpp_gfx10
    UINT64_C(2113962746), UINT64_C(0),	// V_EXP_F16_dpp_vi
    UINT64_C(2113974272), UINT64_C(0),	// V_EXP_F16_e32_gfx10
    UINT64_C(2113962496), UINT64_C(0),	// V_EXP_F16_e32_vi
    UINT64_C(3587702784), UINT64_C(0),	// V_EXP_F16_e64_gfx10
    UINT64_C(3514892288), UINT64_C(0),	// V_EXP_F16_e64_vi
    UINT64_C(2113974272), UINT64_C(0),	// V_EXP_F16_fake16_dpp8_gfx11
    UINT64_C(2113974272), UINT64_C(0),	// V_EXP_F16_fake16_dpp8_gfx12
    UINT64_C(2113974522), UINT64_C(0),	// V_EXP_F16_fake16_dpp_gfx11
    UINT64_C(2113974522), UINT64_C(0),	// V_EXP_F16_fake16_dpp_gfx12
    UINT64_C(2113974272), UINT64_C(0),	// V_EXP_F16_fake16_e32_gfx11
    UINT64_C(2113974272), UINT64_C(0),	// V_EXP_F16_fake16_e32_gfx12
    UINT64_C(3587702784), UINT64_C(0),	// V_EXP_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3587702784), UINT64_C(0),	// V_EXP_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077329526784), UINT64_C(0),	// V_EXP_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077329526784), UINT64_C(0),	// V_EXP_F16_fake16_e64_dpp_gfx12
    UINT64_C(3587702784), UINT64_C(0),	// V_EXP_F16_fake16_e64_gfx11
    UINT64_C(3587702784), UINT64_C(0),	// V_EXP_F16_fake16_e64_gfx12
    UINT64_C(2113974521), UINT64_C(0),	// V_EXP_F16_sdwa_gfx10
    UINT64_C(2113962745), UINT64_C(0),	// V_EXP_F16_sdwa_gfx9
    UINT64_C(2113962745), UINT64_C(0),	// V_EXP_F16_sdwa_vi
    UINT64_C(2113974272), UINT64_C(0),	// V_EXP_F16_t16_dpp8_gfx11
    UINT64_C(2113974272), UINT64_C(0),	// V_EXP_F16_t16_dpp8_gfx12
    UINT64_C(2113974522), UINT64_C(0),	// V_EXP_F16_t16_dpp_gfx11
    UINT64_C(2113974522), UINT64_C(0),	// V_EXP_F16_t16_dpp_gfx12
    UINT64_C(2113974272), UINT64_C(0),	// V_EXP_F16_t16_e32_gfx11
    UINT64_C(2113974272), UINT64_C(0),	// V_EXP_F16_t16_e32_gfx12
    UINT64_C(3587702784), UINT64_C(0),	// V_EXP_F16_t16_e64_dpp8_gfx11
    UINT64_C(3587702784), UINT64_C(0),	// V_EXP_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077329526784), UINT64_C(0),	// V_EXP_F16_t16_e64_dpp_gfx11
    UINT64_C(1077329526784), UINT64_C(0),	// V_EXP_F16_t16_e64_dpp_gfx12
    UINT64_C(3587702784), UINT64_C(0),	// V_EXP_F16_t16_e64_gfx11
    UINT64_C(3587702784), UINT64_C(0),	// V_EXP_F16_t16_e64_gfx12
    UINT64_C(2113948160), UINT64_C(0),	// V_EXP_F32_dpp8_gfx10
    UINT64_C(2113948160), UINT64_C(0),	// V_EXP_F32_dpp8_gfx11
    UINT64_C(2113948160), UINT64_C(0),	// V_EXP_F32_dpp8_gfx12
    UINT64_C(2113948410), UINT64_C(0),	// V_EXP_F32_dpp_gfx10
    UINT64_C(2113948410), UINT64_C(0),	// V_EXP_F32_dpp_gfx11
    UINT64_C(2113948410), UINT64_C(0),	// V_EXP_F32_dpp_gfx12
    UINT64_C(2113945850), UINT64_C(0),	// V_EXP_F32_dpp_vi
    UINT64_C(2113948160), UINT64_C(0),	// V_EXP_F32_e32_gfx10
    UINT64_C(2113948160), UINT64_C(0),	// V_EXP_F32_e32_gfx11
    UINT64_C(2113948160), UINT64_C(0),	// V_EXP_F32_e32_gfx12
    UINT64_C(2113948160), UINT64_C(0),	// V_EXP_F32_e32_gfx6_gfx7
    UINT64_C(2113945600), UINT64_C(0),	// V_EXP_F32_e32_vi
    UINT64_C(3584360448), UINT64_C(0),	// V_EXP_F32_e64_dpp8_gfx11
    UINT64_C(3584360448), UINT64_C(0),	// V_EXP_F32_e64_dpp8_gfx12
    UINT64_C(1077326184448), UINT64_C(0),	// V_EXP_F32_e64_dpp_gfx11
    UINT64_C(1077326184448), UINT64_C(0),	// V_EXP_F32_e64_dpp_gfx12
    UINT64_C(3584360448), UINT64_C(0),	// V_EXP_F32_e64_gfx10
    UINT64_C(3584360448), UINT64_C(0),	// V_EXP_F32_e64_gfx11
    UINT64_C(3584360448), UINT64_C(0),	// V_EXP_F32_e64_gfx12
    UINT64_C(3544842240), UINT64_C(0),	// V_EXP_F32_e64_gfx6_gfx7
    UINT64_C(3512729600), UINT64_C(0),	// V_EXP_F32_e64_vi
    UINT64_C(2113948409), UINT64_C(0),	// V_EXP_F32_sdwa_gfx10
    UINT64_C(2113945849), UINT64_C(0),	// V_EXP_F32_sdwa_gfx9
    UINT64_C(2113945849), UINT64_C(0),	// V_EXP_F32_sdwa_vi
    UINT64_C(2113967866), UINT64_C(0),	// V_EXP_LEGACY_F32_dpp_vi
    UINT64_C(2113965056), UINT64_C(0),	// V_EXP_LEGACY_F32_e32_gfx7
    UINT64_C(2113967616), UINT64_C(0),	// V_EXP_LEGACY_F32_e32_vi
    UINT64_C(3549167616), UINT64_C(0),	// V_EXP_LEGACY_F32_e64_gfx7
    UINT64_C(3515547648), UINT64_C(0),	// V_EXP_LEGACY_F32_e64_vi
    UINT64_C(2113967865), UINT64_C(0),	// V_EXP_LEGACY_F32_sdwa_gfx9
    UINT64_C(2113967865), UINT64_C(0),	// V_EXP_LEGACY_F32_sdwa_vi
    UINT64_C(2113959424), UINT64_C(0),	// V_FFBH_I32_dpp8_gfx10
    UINT64_C(2113959674), UINT64_C(0),	// V_FFBH_I32_dpp_gfx10
    UINT64_C(2113953530), UINT64_C(0),	// V_FFBH_I32_dpp_vi
    UINT64_C(2113959424), UINT64_C(0),	// V_FFBH_I32_e32_gfx10
    UINT64_C(2113959424), UINT64_C(0),	// V_FFBH_I32_e32_gfx6_gfx7
    UINT64_C(2113953280), UINT64_C(0),	// V_FFBH_I32_e32_vi
    UINT64_C(3585802240), UINT64_C(0),	// V_FFBH_I32_e64_gfx10
    UINT64_C(3547725824), UINT64_C(0),	// V_FFBH_I32_e64_gfx6_gfx7
    UINT64_C(3513712640), UINT64_C(0),	// V_FFBH_I32_e64_vi
    UINT64_C(2113959673), UINT64_C(0),	// V_FFBH_I32_sdwa_gfx10
    UINT64_C(2113953529), UINT64_C(0),	// V_FFBH_I32_sdwa_gfx9
    UINT64_C(2113953529), UINT64_C(0),	// V_FFBH_I32_sdwa_vi
    UINT64_C(2113958400), UINT64_C(0),	// V_FFBH_U32_dpp8_gfx10
    UINT64_C(2113958650), UINT64_C(0),	// V_FFBH_U32_dpp_gfx10
    UINT64_C(2113952506), UINT64_C(0),	// V_FFBH_U32_dpp_vi
    UINT64_C(2113958400), UINT64_C(0),	// V_FFBH_U32_e32_gfx10
    UINT64_C(2113958400), UINT64_C(0),	// V_FFBH_U32_e32_gfx6_gfx7
    UINT64_C(2113952256), UINT64_C(0),	// V_FFBH_U32_e32_vi
    UINT64_C(3585671168), UINT64_C(0),	// V_FFBH_U32_e64_gfx10
    UINT64_C(3547463680), UINT64_C(0),	// V_FFBH_U32_e64_gfx6_gfx7
    UINT64_C(3513581568), UINT64_C(0),	// V_FFBH_U32_e64_vi
    UINT64_C(2113958649), UINT64_C(0),	// V_FFBH_U32_sdwa_gfx10
    UINT64_C(2113952505), UINT64_C(0),	// V_FFBH_U32_sdwa_gfx9
    UINT64_C(2113952505), UINT64_C(0),	// V_FFBH_U32_sdwa_vi
    UINT64_C(2113958912), UINT64_C(0),	// V_FFBL_B32_dpp8_gfx10
    UINT64_C(2113959162), UINT64_C(0),	// V_FFBL_B32_dpp_gfx10
    UINT64_C(2113953018), UINT64_C(0),	// V_FFBL_B32_dpp_vi
    UINT64_C(2113958912), UINT64_C(0),	// V_FFBL_B32_e32_gfx10
    UINT64_C(2113958912), UINT64_C(0),	// V_FFBL_B32_e32_gfx6_gfx7
    UINT64_C(2113952768), UINT64_C(0),	// V_FFBL_B32_e32_vi
    UINT64_C(3585736704), UINT64_C(0),	// V_FFBL_B32_e64_gfx10
    UINT64_C(3547594752), UINT64_C(0),	// V_FFBL_B32_e64_gfx6_gfx7
    UINT64_C(3513647104), UINT64_C(0),	// V_FFBL_B32_e64_vi
    UINT64_C(2113959161), UINT64_C(0),	// V_FFBL_B32_sdwa_gfx10
    UINT64_C(2113953017), UINT64_C(0),	// V_FFBL_B32_sdwa_gfx9
    UINT64_C(2113953017), UINT64_C(0),	// V_FFBL_B32_sdwa_vi
    UINT64_C(2113975808), UINT64_C(0),	// V_FLOOR_F16_dpp8_gfx10
    UINT64_C(2113976058), UINT64_C(0),	// V_FLOOR_F16_dpp_gfx10
    UINT64_C(2113964282), UINT64_C(0),	// V_FLOOR_F16_dpp_vi
    UINT64_C(2113975808), UINT64_C(0),	// V_FLOOR_F16_e32_gfx10
    UINT64_C(2113964032), UINT64_C(0),	// V_FLOOR_F16_e32_vi
    UINT64_C(3587899392), UINT64_C(0),	// V_FLOOR_F16_e64_gfx10
    UINT64_C(3515088896), UINT64_C(0),	// V_FLOOR_F16_e64_vi
    UINT64_C(2113975808), UINT64_C(0),	// V_FLOOR_F16_fake16_dpp8_gfx11
    UINT64_C(2113975808), UINT64_C(0),	// V_FLOOR_F16_fake16_dpp8_gfx12
    UINT64_C(2113976058), UINT64_C(0),	// V_FLOOR_F16_fake16_dpp_gfx11
    UINT64_C(2113976058), UINT64_C(0),	// V_FLOOR_F16_fake16_dpp_gfx12
    UINT64_C(2113975808), UINT64_C(0),	// V_FLOOR_F16_fake16_e32_gfx11
    UINT64_C(2113975808), UINT64_C(0),	// V_FLOOR_F16_fake16_e32_gfx12
    UINT64_C(3587899392), UINT64_C(0),	// V_FLOOR_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3587899392), UINT64_C(0),	// V_FLOOR_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077329723392), UINT64_C(0),	// V_FLOOR_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077329723392), UINT64_C(0),	// V_FLOOR_F16_fake16_e64_dpp_gfx12
    UINT64_C(3587899392), UINT64_C(0),	// V_FLOOR_F16_fake16_e64_gfx11
    UINT64_C(3587899392), UINT64_C(0),	// V_FLOOR_F16_fake16_e64_gfx12
    UINT64_C(2113976057), UINT64_C(0),	// V_FLOOR_F16_sdwa_gfx10
    UINT64_C(2113964281), UINT64_C(0),	// V_FLOOR_F16_sdwa_gfx9
    UINT64_C(2113964281), UINT64_C(0),	// V_FLOOR_F16_sdwa_vi
    UINT64_C(2113975808), UINT64_C(0),	// V_FLOOR_F16_t16_dpp8_gfx11
    UINT64_C(2113975808), UINT64_C(0),	// V_FLOOR_F16_t16_dpp8_gfx12
    UINT64_C(2113976058), UINT64_C(0),	// V_FLOOR_F16_t16_dpp_gfx11
    UINT64_C(2113976058), UINT64_C(0),	// V_FLOOR_F16_t16_dpp_gfx12
    UINT64_C(2113975808), UINT64_C(0),	// V_FLOOR_F16_t16_e32_gfx11
    UINT64_C(2113975808), UINT64_C(0),	// V_FLOOR_F16_t16_e32_gfx12
    UINT64_C(3587899392), UINT64_C(0),	// V_FLOOR_F16_t16_e64_dpp8_gfx11
    UINT64_C(3587899392), UINT64_C(0),	// V_FLOOR_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077329723392), UINT64_C(0),	// V_FLOOR_F16_t16_e64_dpp_gfx11
    UINT64_C(1077329723392), UINT64_C(0),	// V_FLOOR_F16_t16_e64_dpp_gfx12
    UINT64_C(3587899392), UINT64_C(0),	// V_FLOOR_F16_t16_e64_gfx11
    UINT64_C(3587899392), UINT64_C(0),	// V_FLOOR_F16_t16_e64_gfx12
    UINT64_C(2113947648), UINT64_C(0),	// V_FLOOR_F32_dpp8_gfx10
    UINT64_C(2113947648), UINT64_C(0),	// V_FLOOR_F32_dpp8_gfx11
    UINT64_C(2113947648), UINT64_C(0),	// V_FLOOR_F32_dpp8_gfx12
    UINT64_C(2113947898), UINT64_C(0),	// V_FLOOR_F32_dpp_gfx10
    UINT64_C(2113947898), UINT64_C(0),	// V_FLOOR_F32_dpp_gfx11
    UINT64_C(2113947898), UINT64_C(0),	// V_FLOOR_F32_dpp_gfx12
    UINT64_C(2113945338), UINT64_C(0),	// V_FLOOR_F32_dpp_vi
    UINT64_C(2113947648), UINT64_C(0),	// V_FLOOR_F32_e32_gfx10
    UINT64_C(2113947648), UINT64_C(0),	// V_FLOOR_F32_e32_gfx11
    UINT64_C(2113947648), UINT64_C(0),	// V_FLOOR_F32_e32_gfx12
    UINT64_C(2113947648), UINT64_C(0),	// V_FLOOR_F32_e32_gfx6_gfx7
    UINT64_C(2113945088), UINT64_C(0),	// V_FLOOR_F32_e32_vi
    UINT64_C(3584294912), UINT64_C(0),	// V_FLOOR_F32_e64_dpp8_gfx11
    UINT64_C(3584294912), UINT64_C(0),	// V_FLOOR_F32_e64_dpp8_gfx12
    UINT64_C(1077326118912), UINT64_C(0),	// V_FLOOR_F32_e64_dpp_gfx11
    UINT64_C(1077326118912), UINT64_C(0),	// V_FLOOR_F32_e64_dpp_gfx12
    UINT64_C(3584294912), UINT64_C(0),	// V_FLOOR_F32_e64_gfx10
    UINT64_C(3584294912), UINT64_C(0),	// V_FLOOR_F32_e64_gfx11
    UINT64_C(3584294912), UINT64_C(0),	// V_FLOOR_F32_e64_gfx12
    UINT64_C(3544711168), UINT64_C(0),	// V_FLOOR_F32_e64_gfx6_gfx7
    UINT64_C(3512664064), UINT64_C(0),	// V_FLOOR_F32_e64_vi
    UINT64_C(2113947897), UINT64_C(0),	// V_FLOOR_F32_sdwa_gfx10
    UINT64_C(2113945337), UINT64_C(0),	// V_FLOOR_F32_sdwa_gfx9
    UINT64_C(2113945337), UINT64_C(0),	// V_FLOOR_F32_sdwa_vi
    UINT64_C(2113942778), UINT64_C(0),	// V_FLOOR_F64_dpp_gfx12
    UINT64_C(2113942778), UINT64_C(0),	// V_FLOOR_F64_dpp_vi
    UINT64_C(2113942528), UINT64_C(0),	// V_FLOOR_F64_e32_gfx10
    UINT64_C(2113942528), UINT64_C(0),	// V_FLOOR_F64_e32_gfx11
    UINT64_C(2113942528), UINT64_C(0),	// V_FLOOR_F64_e32_gfx12
    UINT64_C(2113942528), UINT64_C(0),	// V_FLOOR_F64_e32_gfx7
    UINT64_C(2113942528), UINT64_C(0),	// V_FLOOR_F64_e32_vi
    UINT64_C(1077325463552), UINT64_C(0),	// V_FLOOR_F64_e64_dpp_gfx12
    UINT64_C(3583639552), UINT64_C(0),	// V_FLOOR_F64_e64_gfx10
    UINT64_C(3583639552), UINT64_C(0),	// V_FLOOR_F64_e64_gfx11
    UINT64_C(3583639552), UINT64_C(0),	// V_FLOOR_F64_e64_gfx12
    UINT64_C(3543400448), UINT64_C(0),	// V_FLOOR_F64_e64_gfx7
    UINT64_C(3512336384), UINT64_C(0),	// V_FLOOR_F64_e64_vi
    UINT64_C(1879048192), UINT64_C(0),	// V_FMAAK_F16_fake16_gfx11
    UINT64_C(1879048192), UINT64_C(0),	// V_FMAAK_F16_fake16_gfx12
    UINT64_C(1879048192), UINT64_C(0),	// V_FMAAK_F16_gfx10
    UINT64_C(1879048192), UINT64_C(0),	// V_FMAAK_F16_t16_gfx11
    UINT64_C(1879048192), UINT64_C(0),	// V_FMAAK_F16_t16_gfx12
    UINT64_C(1509949440), UINT64_C(0),	// V_FMAAK_F32_gfx10
    UINT64_C(1509949440), UINT64_C(0),	// V_FMAAK_F32_gfx11
    UINT64_C(1509949440), UINT64_C(0),	// V_FMAAK_F32_gfx12
    UINT64_C(805306368), UINT64_C(0),	// V_FMAAK_F32_gfx940
    UINT64_C(1207959552), UINT64_C(0),	// V_FMAAK_F64_gfx1250
    UINT64_C(201326592), UINT64_C(0),	// V_FMAC_DX9_ZERO_F32_e32_gfx11
    UINT64_C(3573940224), UINT64_C(0),	// V_FMAC_DX9_ZERO_F32_e64_gfx11
    UINT64_C(1811939328), UINT64_C(0),	// V_FMAC_F16_dpp8_gfx10
    UINT64_C(1811939578), UINT64_C(0),	// V_FMAC_F16_dpp_gfx10
    UINT64_C(1811939328), UINT64_C(0),	// V_FMAC_F16_e32_gfx10
    UINT64_C(3577085952), UINT64_C(0),	// V_FMAC_F16_e64_gfx10
    UINT64_C(1811939328), UINT64_C(0),	// V_FMAC_F16_fake16_dpp8_gfx11
    UINT64_C(1811939328), UINT64_C(0),	// V_FMAC_F16_fake16_dpp8_gfx12
    UINT64_C(1811939578), UINT64_C(0),	// V_FMAC_F16_fake16_dpp_gfx11
    UINT64_C(1811939578), UINT64_C(0),	// V_FMAC_F16_fake16_dpp_gfx12
    UINT64_C(1811939328), UINT64_C(0),	// V_FMAC_F16_fake16_e32_gfx11
    UINT64_C(1811939328), UINT64_C(0),	// V_FMAC_F16_fake16_e32_gfx12
    UINT64_C(3577085952), UINT64_C(0),	// V_FMAC_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3577085952), UINT64_C(0),	// V_FMAC_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077318909952), UINT64_C(0),	// V_FMAC_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077318909952), UINT64_C(0),	// V_FMAC_F16_fake16_e64_dpp_gfx12
    UINT64_C(3577085952), UINT64_C(0),	// V_FMAC_F16_fake16_e64_gfx11
    UINT64_C(3577085952), UINT64_C(0),	// V_FMAC_F16_fake16_e64_gfx12
    UINT64_C(1811939328), UINT64_C(0),	// V_FMAC_F16_t16_dpp8_gfx11
    UINT64_C(1811939328), UINT64_C(0),	// V_FMAC_F16_t16_dpp8_gfx12
    UINT64_C(1811939578), UINT64_C(0),	// V_FMAC_F16_t16_dpp_gfx11
    UINT64_C(1811939578), UINT64_C(0),	// V_FMAC_F16_t16_dpp_gfx12
    UINT64_C(1811939328), UINT64_C(0),	// V_FMAC_F16_t16_e32_gfx11
    UINT64_C(1811939328), UINT64_C(0),	// V_FMAC_F16_t16_e32_gfx12
    UINT64_C(3577085952), UINT64_C(0),	// V_FMAC_F16_t16_e64_dpp8_gfx11
    UINT64_C(3577085952), UINT64_C(0),	// V_FMAC_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077318909952), UINT64_C(0),	// V_FMAC_F16_t16_e64_dpp_gfx11
    UINT64_C(1077318909952), UINT64_C(0),	// V_FMAC_F16_t16_e64_dpp_gfx12
    UINT64_C(3577085952), UINT64_C(0),	// V_FMAC_F16_t16_e64_gfx11
    UINT64_C(3577085952), UINT64_C(0),	// V_FMAC_F16_t16_e64_gfx12
    UINT64_C(1442840576), UINT64_C(0),	// V_FMAC_F32_dpp8_gfx10
    UINT64_C(1442840576), UINT64_C(0),	// V_FMAC_F32_dpp8_gfx11
    UINT64_C(1442840576), UINT64_C(0),	// V_FMAC_F32_dpp8_gfx12
    UINT64_C(1442840826), UINT64_C(0),	// V_FMAC_F32_dpp_gfx10
    UINT64_C(1442840826), UINT64_C(0),	// V_FMAC_F32_dpp_gfx11
    UINT64_C(1442840826), UINT64_C(0),	// V_FMAC_F32_dpp_gfx12
    UINT64_C(1979711738), UINT64_C(0),	// V_FMAC_F32_dpp_vi
    UINT64_C(1442840576), UINT64_C(0),	// V_FMAC_F32_e32_gfx10
    UINT64_C(1442840576), UINT64_C(0),	// V_FMAC_F32_e32_gfx11
    UINT64_C(1442840576), UINT64_C(0),	// V_FMAC_F32_e32_gfx12
    UINT64_C(1979711488), UINT64_C(0),	// V_FMAC_F32_e32_vi
    UINT64_C(3576365056), UINT64_C(0),	// V_FMAC_F32_e64_dpp8_gfx11
    UINT64_C(3576365056), UINT64_C(0),	// V_FMAC_F32_e64_dpp8_gfx12
    UINT64_C(1077318189056), UINT64_C(0),	// V_FMAC_F32_e64_dpp_gfx11
    UINT64_C(1077318189056), UINT64_C(0),	// V_FMAC_F32_e64_dpp_gfx12
    UINT64_C(3576365056), UINT64_C(0),	// V_FMAC_F32_e64_gfx10
    UINT64_C(3576365056), UINT64_C(0),	// V_FMAC_F32_e64_gfx11
    UINT64_C(3576365056), UINT64_C(0),	// V_FMAC_F32_e64_gfx12
    UINT64_C(3510304768), UINT64_C(0),	// V_FMAC_F32_e64_vi
    UINT64_C(1979711737), UINT64_C(0),	// V_FMAC_F32_sdwa_vi
    UINT64_C(771752186), UINT64_C(0),	// V_FMAC_F64_dpp_gfx12
    UINT64_C(134217978), UINT64_C(0),	// V_FMAC_F64_dpp_gfx90a
    UINT64_C(771751936), UINT64_C(0),	// V_FMAC_F64_e32_gfx12
    UINT64_C(134217728), UINT64_C(0),	// V_FMAC_F64_e32_gfx90a
    UINT64_C(1077316878336), UINT64_C(0),	// V_FMAC_F64_e64_dpp_gfx12
    UINT64_C(3575054336), UINT64_C(0),	// V_FMAC_F64_e64_gfx12
    UINT64_C(3506700288), UINT64_C(0),	// V_FMAC_F64_e64_gfx90a
    UINT64_C(201326592), UINT64_C(0),	// V_FMAC_LEGACY_F32_e32_gfx10
    UINT64_C(3573940224), UINT64_C(0),	// V_FMAC_LEGACY_F32_e64_gfx10
    UINT64_C(1845493760), UINT64_C(0),	// V_FMAMK_F16_fake16_gfx11
    UINT64_C(1845493760), UINT64_C(0),	// V_FMAMK_F16_fake16_gfx12
    UINT64_C(1845493760), UINT64_C(0),	// V_FMAMK_F16_gfx10
    UINT64_C(1845493760), UINT64_C(0),	// V_FMAMK_F16_t16_gfx11
    UINT64_C(1845493760), UINT64_C(0),	// V_FMAMK_F16_t16_gfx12
    UINT64_C(1476395008), UINT64_C(0),	// V_FMAMK_F32_gfx10
    UINT64_C(1476395008), UINT64_C(0),	// V_FMAMK_F32_gfx11
    UINT64_C(1476395008), UINT64_C(0),	// V_FMAMK_F32_gfx12
    UINT64_C(771751936), UINT64_C(0),	// V_FMAMK_F32_gfx940
    UINT64_C(1174405120), UINT64_C(0),	// V_FMAMK_F64_gfx1250
    UINT64_C(3590914048), UINT64_C(0),	// V_FMA_DX9_ZERO_F32_e64_gfx11
    UINT64_C(3590914048), UINT64_C(0),	// V_FMA_DX9_ZERO_F32_e64_gfx12
    UINT64_C(3595042816), UINT64_C(0),	// V_FMA_F16V_FMA_F16_gfx9_fake16_e64_dpp8_gfx11
    UINT64_C(3595042816), UINT64_C(0),	// V_FMA_F16V_FMA_F16_gfx9_fake16_e64_dpp8_gfx12
    UINT64_C(1077336866816), UINT64_C(0),	// V_FMA_F16V_FMA_F16_gfx9_fake16_e64_dpp_gfx11
    UINT64_C(1077336866816), UINT64_C(0),	// V_FMA_F16V_FMA_F16_gfx9_fake16_e64_dpp_gfx12
    UINT64_C(3595042816), UINT64_C(0),	// V_FMA_F16V_FMA_F16_gfx9_fake16_e64_gfx11
    UINT64_C(3595042816), UINT64_C(0),	// V_FMA_F16V_FMA_F16_gfx9_fake16_e64_gfx12
    UINT64_C(3595042816), UINT64_C(0),	// V_FMA_F16V_FMA_F16_gfx9_t16_e64_dpp8_gfx11
    UINT64_C(3595042816), UINT64_C(0),	// V_FMA_F16V_FMA_F16_gfx9_t16_e64_dpp8_gfx12
    UINT64_C(1077336866816), UINT64_C(0),	// V_FMA_F16V_FMA_F16_gfx9_t16_e64_dpp_gfx11
    UINT64_C(1077336866816), UINT64_C(0),	// V_FMA_F16V_FMA_F16_gfx9_t16_e64_dpp_gfx12
    UINT64_C(3595042816), UINT64_C(0),	// V_FMA_F16V_FMA_F16_gfx9_t16_e64_gfx11
    UINT64_C(3595042816), UINT64_C(0),	// V_FMA_F16V_FMA_F16_gfx9_t16_e64_gfx12
    UINT64_C(3612016640), UINT64_C(0),	// V_FMA_F16_gfx10
    UINT64_C(3523608576), UINT64_C(0),	// V_FMA_F16_gfx9_gfx9
    UINT64_C(3522035712), UINT64_C(0),	// V_FMA_F16_vi
    UINT64_C(3591569408), UINT64_C(0),	// V_FMA_F32_e64_dpp8_gfx11
    UINT64_C(3591569408), UINT64_C(0),	// V_FMA_F32_e64_dpp8_gfx12
    UINT64_C(1077333393408), UINT64_C(0),	// V_FMA_F32_e64_dpp_gfx11
    UINT64_C(1077333393408), UINT64_C(0),	// V_FMA_F32_e64_dpp_gfx12
    UINT64_C(3591569408), UINT64_C(0),	// V_FMA_F32_e64_gfx11
    UINT64_C(3591569408), UINT64_C(0),	// V_FMA_F32_e64_gfx12
    UINT64_C(3578462208), UINT64_C(0),	// V_FMA_F32_gfx10
    UINT64_C(3533045760), UINT64_C(0),	// V_FMA_F32_gfx6_gfx7
    UINT64_C(3519741952), UINT64_C(0),	// V_FMA_F32_vi
    UINT64_C(1077333458944), UINT64_C(0),	// V_FMA_F64_e64_dpp_gfx1250
    UINT64_C(3591634944), UINT64_C(0),	// V_FMA_F64_e64_gfx11
    UINT64_C(3591634944), UINT64_C(0),	// V_FMA_F64_e64_gfx12
    UINT64_C(3591634944), UINT64_C(0),	// V_FMA_F64_e64_gfx1250
    UINT64_C(3578527744), UINT64_C(0),	// V_FMA_F64_gfx10
    UINT64_C(3533176832), UINT64_C(0),	// V_FMA_F64_gfx6_gfx7
    UINT64_C(3519807488), UINT64_C(0),	// V_FMA_F64_vi
    UINT64_C(3522035712), UINT64_C(0),	// V_FMA_LEGACY_F16_gfx9
    UINT64_C(3577741312), UINT64_C(0),	// V_FMA_LEGACY_F32_gfx10
    UINT64_C(3426680832), UINT64_C(0),	// V_FMA_MIXHI_BF16_dpp8_gfx1250
    UINT64_C(1077168504832), UINT64_C(0),	// V_FMA_MIXHI_BF16_dpp_gfx1250
    UINT64_C(3426680832), UINT64_C(0),	// V_FMA_MIXHI_BF16_gfx1250
    UINT64_C(3424780288), UINT64_C(0),	// V_FMA_MIXHI_F16_dpp8_gfx11
    UINT64_C(3424780288), UINT64_C(0),	// V_FMA_MIXHI_F16_dpp8_gfx12
    UINT64_C(1077166604288), UINT64_C(0),	// V_FMA_MIXHI_F16_dpp_gfx11
    UINT64_C(1077166604288), UINT64_C(0),	// V_FMA_MIXHI_F16_dpp_gfx12
    UINT64_C(3424780288), UINT64_C(0),	// V_FMA_MIXHI_F16_gfx10
    UINT64_C(3424780288), UINT64_C(0),	// V_FMA_MIXHI_F16_gfx11
    UINT64_C(3424780288), UINT64_C(0),	// V_FMA_MIXHI_F16_gfx12
    UINT64_C(3550609408), UINT64_C(0),	// V_FMA_MIXHI_F16_vi
    UINT64_C(3426615296), UINT64_C(0),	// V_FMA_MIXLO_BF16_dpp8_gfx1250
    UINT64_C(1077168439296), UINT64_C(0),	// V_FMA_MIXLO_BF16_dpp_gfx1250
    UINT64_C(3426615296), UINT64_C(0),	// V_FMA_MIXLO_BF16_gfx1250
    UINT64_C(3424714752), UINT64_C(0),	// V_FMA_MIXLO_F16_dpp8_gfx11
    UINT64_C(3424714752), UINT64_C(0),	// V_FMA_MIXLO_F16_dpp8_gfx12
    UINT64_C(1077166538752), UINT64_C(0),	// V_FMA_MIXLO_F16_dpp_gfx11
    UINT64_C(1077166538752), UINT64_C(0),	// V_FMA_MIXLO_F16_dpp_gfx12
    UINT64_C(3424714752), UINT64_C(0),	// V_FMA_MIXLO_F16_gfx10
    UINT64_C(3424714752), UINT64_C(0),	// V_FMA_MIXLO_F16_gfx11
    UINT64_C(3424714752), UINT64_C(0),	// V_FMA_MIXLO_F16_gfx12
    UINT64_C(3550543872), UINT64_C(0),	// V_FMA_MIXLO_F16_vi
    UINT64_C(3426549760), UINT64_C(0),	// V_FMA_MIX_F32_BF16_dpp8_gfx1250
    UINT64_C(1077168373760), UINT64_C(0),	// V_FMA_MIX_F32_BF16_dpp_gfx1250
    UINT64_C(3426549760), UINT64_C(0),	// V_FMA_MIX_F32_BF16_gfx1250
    UINT64_C(3424649216), UINT64_C(0),	// V_FMA_MIX_F32_dpp8_gfx11
    UINT64_C(3424649216), UINT64_C(0),	// V_FMA_MIX_F32_dpp8_gfx12
    UINT64_C(1077166473216), UINT64_C(0),	// V_FMA_MIX_F32_dpp_gfx11
    UINT64_C(1077166473216), UINT64_C(0),	// V_FMA_MIX_F32_dpp_gfx12
    UINT64_C(3424649216), UINT64_C(0),	// V_FMA_MIX_F32_gfx10
    UINT64_C(3424649216), UINT64_C(0),	// V_FMA_MIX_F32_gfx11
    UINT64_C(3424649216), UINT64_C(0),	// V_FMA_MIX_F32_gfx12
    UINT64_C(3550478336), UINT64_C(0),	// V_FMA_MIX_F32_vi
    UINT64_C(2113977856), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_fake16_dpp8_gfx11
    UINT64_C(2113977856), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_fake16_dpp8_gfx12
    UINT64_C(2113978106), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_fake16_dpp_gfx11
    UINT64_C(2113978106), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_fake16_dpp_gfx12
    UINT64_C(2113977856), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_fake16_e32_gfx11
    UINT64_C(2113977856), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_fake16_e32_gfx12
    UINT64_C(3588161536), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3588161536), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077329985536), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077329985536), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_fake16_e64_dpp_gfx12
    UINT64_C(3588161536), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_fake16_e64_gfx11
    UINT64_C(3588161536), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_fake16_e64_gfx12
    UINT64_C(2113977856), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_t16_dpp8_gfx11
    UINT64_C(2113977856), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_t16_dpp8_gfx12
    UINT64_C(2113978106), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_t16_dpp_gfx11
    UINT64_C(2113978106), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_t16_dpp_gfx12
    UINT64_C(2113977856), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_t16_e32_gfx11
    UINT64_C(2113977856), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_t16_e32_gfx12
    UINT64_C(3588161536), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_t16_e64_dpp8_gfx11
    UINT64_C(3588161536), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077329985536), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_t16_e64_dpp_gfx11
    UINT64_C(1077329985536), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_t16_e64_dpp_gfx12
    UINT64_C(3588161536), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_t16_e64_gfx11
    UINT64_C(3588161536), UINT64_C(0),	// V_FRACT_F16V_FRACT_F16_t16_e64_gfx12
    UINT64_C(2113977856), UINT64_C(0),	// V_FRACT_F16_dpp8_gfx10
    UINT64_C(2113978106), UINT64_C(0),	// V_FRACT_F16_dpp_gfx10
    UINT64_C(2113966330), UINT64_C(0),	// V_FRACT_F16_dpp_vi
    UINT64_C(2113977856), UINT64_C(0),	// V_FRACT_F16_e32_gfx10
    UINT64_C(2113966080), UINT64_C(0),	// V_FRACT_F16_e32_vi
    UINT64_C(3588161536), UINT64_C(0),	// V_FRACT_F16_e64_gfx10
    UINT64_C(3515351040), UINT64_C(0),	// V_FRACT_F16_e64_vi
    UINT64_C(2113978105), UINT64_C(0),	// V_FRACT_F16_sdwa_gfx10
    UINT64_C(2113966329), UINT64_C(0),	// V_FRACT_F16_sdwa_gfx9
    UINT64_C(2113966329), UINT64_C(0),	// V_FRACT_F16_sdwa_vi
    UINT64_C(2113945600), UINT64_C(0),	// V_FRACT_F32_dpp8_gfx10
    UINT64_C(2113945600), UINT64_C(0),	// V_FRACT_F32_dpp8_gfx11
    UINT64_C(2113945600), UINT64_C(0),	// V_FRACT_F32_dpp8_gfx12
    UINT64_C(2113945850), UINT64_C(0),	// V_FRACT_F32_dpp_gfx10
    UINT64_C(2113945850), UINT64_C(0),	// V_FRACT_F32_dpp_gfx11
    UINT64_C(2113945850), UINT64_C(0),	// V_FRACT_F32_dpp_gfx12
    UINT64_C(2113943290), UINT64_C(0),	// V_FRACT_F32_dpp_vi
    UINT64_C(2113945600), UINT64_C(0),	// V_FRACT_F32_e32_gfx10
    UINT64_C(2113945600), UINT64_C(0),	// V_FRACT_F32_e32_gfx11
    UINT64_C(2113945600), UINT64_C(0),	// V_FRACT_F32_e32_gfx12
    UINT64_C(2113945600), UINT64_C(0),	// V_FRACT_F32_e32_gfx6_gfx7
    UINT64_C(2113943040), UINT64_C(0),	// V_FRACT_F32_e32_vi
    UINT64_C(3584032768), UINT64_C(0),	// V_FRACT_F32_e64_dpp8_gfx11
    UINT64_C(3584032768), UINT64_C(0),	// V_FRACT_F32_e64_dpp8_gfx12
    UINT64_C(1077325856768), UINT64_C(0),	// V_FRACT_F32_e64_dpp_gfx11
    UINT64_C(1077325856768), UINT64_C(0),	// V_FRACT_F32_e64_dpp_gfx12
    UINT64_C(3584032768), UINT64_C(0),	// V_FRACT_F32_e64_gfx10
    UINT64_C(3584032768), UINT64_C(0),	// V_FRACT_F32_e64_gfx11
    UINT64_C(3584032768), UINT64_C(0),	// V_FRACT_F32_e64_gfx12
    UINT64_C(3544186880), UINT64_C(0),	// V_FRACT_F32_e64_gfx6_gfx7
    UINT64_C(3512401920), UINT64_C(0),	// V_FRACT_F32_e64_vi
    UINT64_C(2113945849), UINT64_C(0),	// V_FRACT_F32_sdwa_gfx10
    UINT64_C(2113943289), UINT64_C(0),	// V_FRACT_F32_sdwa_gfx9
    UINT64_C(2113943289), UINT64_C(0),	// V_FRACT_F32_sdwa_vi
    UINT64_C(2113961210), UINT64_C(0),	// V_FRACT_F64_dpp_gfx12
    UINT64_C(2113955066), UINT64_C(0),	// V_FRACT_F64_dpp_vi
    UINT64_C(2113960960), UINT64_C(0),	// V_FRACT_F64_e32_gfx10
    UINT64_C(2113960960), UINT64_C(0),	// V_FRACT_F64_e32_gfx11
    UINT64_C(2113960960), UINT64_C(0),	// V_FRACT_F64_e32_gfx12
    UINT64_C(2113960960), UINT64_C(0),	// V_FRACT_F64_e32_gfx6_gfx7
    UINT64_C(2113954816), UINT64_C(0),	// V_FRACT_F64_e32_vi
    UINT64_C(1077327822848), UINT64_C(0),	// V_FRACT_F64_e64_dpp_gfx12
    UINT64_C(3585998848), UINT64_C(0),	// V_FRACT_F64_e64_gfx10
    UINT64_C(3585998848), UINT64_C(0),	// V_FRACT_F64_e64_gfx11
    UINT64_C(3585998848), UINT64_C(0),	// V_FRACT_F64_e64_gfx12
    UINT64_C(3548119040), UINT64_C(0),	// V_FRACT_F64_e64_gfx6_gfx7
    UINT64_C(3513909248), UINT64_C(0),	// V_FRACT_F64_e64_vi
    UINT64_C(2113975296), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_dpp8_gfx11
    UINT64_C(2113975296), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_dpp8_gfx12
    UINT64_C(2113975546), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_dpp_gfx11
    UINT64_C(2113975546), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_dpp_gfx12
    UINT64_C(2113975296), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e32_gfx11
    UINT64_C(2113975296), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e32_gfx12
    UINT64_C(3587833856), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3587833856), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077329657856), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077329657856), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e64_dpp_gfx12
    UINT64_C(3587833856), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e64_gfx11
    UINT64_C(3587833856), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e64_gfx12
    UINT64_C(2113975296), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_dpp8_gfx11
    UINT64_C(2113975296), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_dpp8_gfx12
    UINT64_C(2113975546), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_dpp_gfx11
    UINT64_C(2113975546), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_dpp_gfx12
    UINT64_C(2113975296), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e32_gfx11
    UINT64_C(2113975296), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e32_gfx12
    UINT64_C(3587833856), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e64_dpp8_gfx11
    UINT64_C(3587833856), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077329657856), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e64_dpp_gfx11
    UINT64_C(1077329657856), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e64_dpp_gfx12
    UINT64_C(3587833856), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e64_gfx11
    UINT64_C(3587833856), UINT64_C(0),	// V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e64_gfx12
    UINT64_C(2113975296), UINT64_C(0),	// V_FREXP_EXP_I16_F16_dpp8_gfx10
    UINT64_C(2113975546), UINT64_C(0),	// V_FREXP_EXP_I16_F16_dpp_gfx10
    UINT64_C(2113963770), UINT64_C(0),	// V_FREXP_EXP_I16_F16_dpp_vi
    UINT64_C(2113975296), UINT64_C(0),	// V_FREXP_EXP_I16_F16_e32_gfx10
    UINT64_C(2113963520), UINT64_C(0),	// V_FREXP_EXP_I16_F16_e32_vi
    UINT64_C(3587833856), UINT64_C(0),	// V_FREXP_EXP_I16_F16_e64_gfx10
    UINT64_C(3515023360), UINT64_C(0),	// V_FREXP_EXP_I16_F16_e64_vi
    UINT64_C(2113975545), UINT64_C(0),	// V_FREXP_EXP_I16_F16_sdwa_gfx10
    UINT64_C(2113963769), UINT64_C(0),	// V_FREXP_EXP_I16_F16_sdwa_gfx9
    UINT64_C(2113963769), UINT64_C(0),	// V_FREXP_EXP_I16_F16_sdwa_vi
    UINT64_C(2113961472), UINT64_C(0),	// V_FREXP_EXP_I32_F32_dpp8_gfx10
    UINT64_C(2113961472), UINT64_C(0),	// V_FREXP_EXP_I32_F32_dpp8_gfx11
    UINT64_C(2113961472), UINT64_C(0),	// V_FREXP_EXP_I32_F32_dpp8_gfx12
    UINT64_C(2113961722), UINT64_C(0),	// V_FREXP_EXP_I32_F32_dpp_gfx10
    UINT64_C(2113961722), UINT64_C(0),	// V_FREXP_EXP_I32_F32_dpp_gfx11
    UINT64_C(2113961722), UINT64_C(0),	// V_FREXP_EXP_I32_F32_dpp_gfx12
    UINT64_C(2113955578), UINT64_C(0),	// V_FREXP_EXP_I32_F32_dpp_vi
    UINT64_C(2113961472), UINT64_C(0),	// V_FREXP_EXP_I32_F32_e32_gfx10
    UINT64_C(2113961472), UINT64_C(0),	// V_FREXP_EXP_I32_F32_e32_gfx11
    UINT64_C(2113961472), UINT64_C(0),	// V_FREXP_EXP_I32_F32_e32_gfx12
    UINT64_C(2113961472), UINT64_C(0),	// V_FREXP_EXP_I32_F32_e32_gfx6_gfx7
    UINT64_C(2113955328), UINT64_C(0),	// V_FREXP_EXP_I32_F32_e32_vi
    UINT64_C(3586064384), UINT64_C(0),	// V_FREXP_EXP_I32_F32_e64_dpp8_gfx11
    UINT64_C(3586064384), UINT64_C(0),	// V_FREXP_EXP_I32_F32_e64_dpp8_gfx12
    UINT64_C(1077327888384), UINT64_C(0),	// V_FREXP_EXP_I32_F32_e64_dpp_gfx11
    UINT64_C(1077327888384), UINT64_C(0),	// V_FREXP_EXP_I32_F32_e64_dpp_gfx12
    UINT64_C(3586064384), UINT64_C(0),	// V_FREXP_EXP_I32_F32_e64_gfx10
    UINT64_C(3586064384), UINT64_C(0),	// V_FREXP_EXP_I32_F32_e64_gfx11
    UINT64_C(3586064384), UINT64_C(0),	// V_FREXP_EXP_I32_F32_e64_gfx12
    UINT64_C(3548250112), UINT64_C(0),	// V_FREXP_EXP_I32_F32_e64_gfx6_gfx7
    UINT64_C(3513974784), UINT64_C(0),	// V_FREXP_EXP_I32_F32_e64_vi
    UINT64_C(2113961721), UINT64_C(0),	// V_FREXP_EXP_I32_F32_sdwa_gfx10
    UINT64_C(2113955577), UINT64_C(0),	// V_FREXP_EXP_I32_F32_sdwa_gfx9
    UINT64_C(2113955577), UINT64_C(0),	// V_FREXP_EXP_I32_F32_sdwa_vi
    UINT64_C(2113960186), UINT64_C(0),	// V_FREXP_EXP_I32_F64_dpp_gfx12
    UINT64_C(2113954042), UINT64_C(0),	// V_FREXP_EXP_I32_F64_dpp_vi
    UINT64_C(2113959936), UINT64_C(0),	// V_FREXP_EXP_I32_F64_e32_gfx10
    UINT64_C(2113959936), UINT64_C(0),	// V_FREXP_EXP_I32_F64_e32_gfx11
    UINT64_C(2113959936), UINT64_C(0),	// V_FREXP_EXP_I32_F64_e32_gfx12
    UINT64_C(2113959936), UINT64_C(0),	// V_FREXP_EXP_I32_F64_e32_gfx6_gfx7
    UINT64_C(2113953792), UINT64_C(0),	// V_FREXP_EXP_I32_F64_e32_vi
    UINT64_C(1077327691776), UINT64_C(0),	// V_FREXP_EXP_I32_F64_e64_dpp_gfx12
    UINT64_C(3585867776), UINT64_C(0),	// V_FREXP_EXP_I32_F64_e64_gfx10
    UINT64_C(3585867776), UINT64_C(0),	// V_FREXP_EXP_I32_F64_e64_gfx11
    UINT64_C(3585867776), UINT64_C(0),	// V_FREXP_EXP_I32_F64_e64_gfx12
    UINT64_C(3547856896), UINT64_C(0),	// V_FREXP_EXP_I32_F64_e64_gfx6_gfx7
    UINT64_C(3513778176), UINT64_C(0),	// V_FREXP_EXP_I32_F64_e64_vi
    UINT64_C(2113974784), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_dpp8_gfx11
    UINT64_C(2113974784), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_dpp8_gfx12
    UINT64_C(2113975034), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_dpp_gfx11
    UINT64_C(2113975034), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_dpp_gfx12
    UINT64_C(2113974784), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e32_gfx11
    UINT64_C(2113974784), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e32_gfx12
    UINT64_C(3587768320), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3587768320), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077329592320), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077329592320), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e64_dpp_gfx12
    UINT64_C(3587768320), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e64_gfx11
    UINT64_C(3587768320), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e64_gfx12
    UINT64_C(2113974784), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_dpp8_gfx11
    UINT64_C(2113974784), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_dpp8_gfx12
    UINT64_C(2113975034), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_dpp_gfx11
    UINT64_C(2113975034), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_dpp_gfx12
    UINT64_C(2113974784), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e32_gfx11
    UINT64_C(2113974784), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e32_gfx12
    UINT64_C(3587768320), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e64_dpp8_gfx11
    UINT64_C(3587768320), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077329592320), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e64_dpp_gfx11
    UINT64_C(1077329592320), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e64_dpp_gfx12
    UINT64_C(3587768320), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e64_gfx11
    UINT64_C(3587768320), UINT64_C(0),	// V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e64_gfx12
    UINT64_C(2113974784), UINT64_C(0),	// V_FREXP_MANT_F16_dpp8_gfx10
    UINT64_C(2113975034), UINT64_C(0),	// V_FREXP_MANT_F16_dpp_gfx10
    UINT64_C(2113963258), UINT64_C(0),	// V_FREXP_MANT_F16_dpp_vi
    UINT64_C(2113974784), UINT64_C(0),	// V_FREXP_MANT_F16_e32_gfx10
    UINT64_C(2113963008), UINT64_C(0),	// V_FREXP_MANT_F16_e32_vi
    UINT64_C(3587768320), UINT64_C(0),	// V_FREXP_MANT_F16_e64_gfx10
    UINT64_C(3514957824), UINT64_C(0),	// V_FREXP_MANT_F16_e64_vi
    UINT64_C(2113975033), UINT64_C(0),	// V_FREXP_MANT_F16_sdwa_gfx10
    UINT64_C(2113963257), UINT64_C(0),	// V_FREXP_MANT_F16_sdwa_gfx9
    UINT64_C(2113963257), UINT64_C(0),	// V_FREXP_MANT_F16_sdwa_vi
    UINT64_C(2113961984), UINT64_C(0),	// V_FREXP_MANT_F32_dpp8_gfx10
    UINT64_C(2113961984), UINT64_C(0),	// V_FREXP_MANT_F32_dpp8_gfx11
    UINT64_C(2113961984), UINT64_C(0),	// V_FREXP_MANT_F32_dpp8_gfx12
    UINT64_C(2113962234), UINT64_C(0),	// V_FREXP_MANT_F32_dpp_gfx10
    UINT64_C(2113962234), UINT64_C(0),	// V_FREXP_MANT_F32_dpp_gfx11
    UINT64_C(2113962234), UINT64_C(0),	// V_FREXP_MANT_F32_dpp_gfx12
    UINT64_C(2113956090), UINT64_C(0),	// V_FREXP_MANT_F32_dpp_vi
    UINT64_C(2113961984), UINT64_C(0),	// V_FREXP_MANT_F32_e32_gfx10
    UINT64_C(2113961984), UINT64_C(0),	// V_FREXP_MANT_F32_e32_gfx11
    UINT64_C(2113961984), UINT64_C(0),	// V_FREXP_MANT_F32_e32_gfx12
    UINT64_C(2113961984), UINT64_C(0),	// V_FREXP_MANT_F32_e32_gfx6_gfx7
    UINT64_C(2113955840), UINT64_C(0),	// V_FREXP_MANT_F32_e32_vi
    UINT64_C(3586129920), UINT64_C(0),	// V_FREXP_MANT_F32_e64_dpp8_gfx11
    UINT64_C(3586129920), UINT64_C(0),	// V_FREXP_MANT_F32_e64_dpp8_gfx12
    UINT64_C(1077327953920), UINT64_C(0),	// V_FREXP_MANT_F32_e64_dpp_gfx11
    UINT64_C(1077327953920), UINT64_C(0),	// V_FREXP_MANT_F32_e64_dpp_gfx12
    UINT64_C(3586129920), UINT64_C(0),	// V_FREXP_MANT_F32_e64_gfx10
    UINT64_C(3586129920), UINT64_C(0),	// V_FREXP_MANT_F32_e64_gfx11
    UINT64_C(3586129920), UINT64_C(0),	// V_FREXP_MANT_F32_e64_gfx12
    UINT64_C(3548381184), UINT64_C(0),	// V_FREXP_MANT_F32_e64_gfx6_gfx7
    UINT64_C(3514040320), UINT64_C(0),	// V_FREXP_MANT_F32_e64_vi
    UINT64_C(2113962233), UINT64_C(0),	// V_FREXP_MANT_F32_sdwa_gfx10
    UINT64_C(2113956089), UINT64_C(0),	// V_FREXP_MANT_F32_sdwa_gfx9
    UINT64_C(2113956089), UINT64_C(0),	// V_FREXP_MANT_F32_sdwa_vi
    UINT64_C(2113960698), UINT64_C(0),	// V_FREXP_MANT_F64_dpp_gfx12
    UINT64_C(2113954554), UINT64_C(0),	// V_FREXP_MANT_F64_dpp_vi
    UINT64_C(2113960448), UINT64_C(0),	// V_FREXP_MANT_F64_e32_gfx10
    UINT64_C(2113960448), UINT64_C(0),	// V_FREXP_MANT_F64_e32_gfx11
    UINT64_C(2113960448), UINT64_C(0),	// V_FREXP_MANT_F64_e32_gfx12
    UINT64_C(2113960448), UINT64_C(0),	// V_FREXP_MANT_F64_e32_gfx6_gfx7
    UINT64_C(2113954304), UINT64_C(0),	// V_FREXP_MANT_F64_e32_vi
    UINT64_C(1077327757312), UINT64_C(0),	// V_FREXP_MANT_F64_e64_dpp_gfx12
    UINT64_C(3585933312), UINT64_C(0),	// V_FREXP_MANT_F64_e64_gfx10
    UINT64_C(3585933312), UINT64_C(0),	// V_FREXP_MANT_F64_e64_gfx11
    UINT64_C(3585933312), UINT64_C(0),	// V_FREXP_MANT_F64_e64_gfx12
    UINT64_C(3547987968), UINT64_C(0),	// V_FREXP_MANT_F64_e64_gfx6_gfx7
    UINT64_C(3513843712), UINT64_C(0),	// V_FREXP_MANT_F64_e64_vi
    UINT64_C(0), UINT64_C(0),	// V_ILLEGAL
    UINT64_C(3590455296), UINT64_C(0),	// V_INTERP_MOV_F32_e64_gfx10
    UINT64_C(3530686464), UINT64_C(0),	// V_INTERP_MOV_F32_e64_vi
    UINT64_C(3355574272), UINT64_C(0),	// V_INTERP_MOV_F32_gfx10
    UINT64_C(3355574272), UINT64_C(0),	// V_INTERP_MOV_F32_si
    UINT64_C(3556900864), UINT64_C(0),	// V_INTERP_MOV_F32_vi
    UINT64_C(3439460352), UINT64_C(0),	// V_INTERP_P10_F16_F32_inreg_fake16_gfx11
    UINT64_C(3439460352), UINT64_C(0),	// V_INTERP_P10_F16_F32_inreg_fake16_gfx12
    UINT64_C(3439460352), UINT64_C(0),	// V_INTERP_P10_F16_F32_inreg_t16_gfx11
    UINT64_C(3439460352), UINT64_C(0),	// V_INTERP_P10_F16_F32_inreg_t16_gfx12
    UINT64_C(3439329280), UINT64_C(0),	// V_INTERP_P10_F32_inreg_gfx11
    UINT64_C(3439329280), UINT64_C(0),	// V_INTERP_P10_F32_inreg_gfx12
    UINT64_C(3439591424), UINT64_C(0),	// V_INTERP_P10_RTZ_F16_F32_inreg_fake16_gfx11
    UINT64_C(3439591424), UINT64_C(0),	// V_INTERP_P10_RTZ_F16_F32_inreg_fake16_gfx12
    UINT64_C(3439591424), UINT64_C(0),	// V_INTERP_P10_RTZ_F16_F32_inreg_t16_gfx11
    UINT64_C(3439591424), UINT64_C(0),	// V_INTERP_P10_RTZ_F16_F32_inreg_t16_gfx12
    UINT64_C(3611426816), UINT64_C(0),	// V_INTERP_P1LL_F16_gfx10
    UINT64_C(3530817536), UINT64_C(0),	// V_INTERP_P1LL_F16_vi
    UINT64_C(3611492352), UINT64_C(0),	// V_INTERP_P1LV_F16_gfx10
    UINT64_C(3530883072), UINT64_C(0),	// V_INTERP_P1LV_F16_vi
    UINT64_C(3355443200), UINT64_C(0),	// V_INTERP_P1_F32_16bank_gfx10
    UINT64_C(3355443200), UINT64_C(0),	// V_INTERP_P1_F32_16bank_si
    UINT64_C(3556769792), UINT64_C(0),	// V_INTERP_P1_F32_16bank_vi
    UINT64_C(3590324224), UINT64_C(0),	// V_INTERP_P1_F32_e64_gfx10
    UINT64_C(3530555392), UINT64_C(0),	// V_INTERP_P1_F32_e64_vi
    UINT64_C(3355443200), UINT64_C(0),	// V_INTERP_P1_F32_gfx10
    UINT64_C(3355443200), UINT64_C(0),	// V_INTERP_P1_F32_si
    UINT64_C(3556769792), UINT64_C(0),	// V_INTERP_P1_F32_vi
    UINT64_C(3439525888), UINT64_C(0),	// V_INTERP_P2_F16_F32_inreg_fake16_gfx11
    UINT64_C(3439525888), UINT64_C(0),	// V_INTERP_P2_F16_F32_inreg_fake16_gfx12
    UINT64_C(3439525888), UINT64_C(0),	// V_INTERP_P2_F16_F32_inreg_t16_gfx11
    UINT64_C(3439525888), UINT64_C(0),	// V_INTERP_P2_F16_F32_inreg_t16_gfx12
    UINT64_C(3612999680), UINT64_C(0),	// V_INTERP_P2_F16_gfx10
    UINT64_C(3531014144), UINT64_C(0),	// V_INTERP_P2_F16_opsel_gfx9
    UINT64_C(3530948608), UINT64_C(0),	// V_INTERP_P2_F16_vi
    UINT64_C(3590389760), UINT64_C(0),	// V_INTERP_P2_F32_e64_gfx10
    UINT64_C(3530620928), UINT64_C(0),	// V_INTERP_P2_F32_e64_vi
    UINT64_C(3355508736), UINT64_C(0),	// V_INTERP_P2_F32_gfx10
    UINT64_C(3439394816), UINT64_C(0),	// V_INTERP_P2_F32_inreg_gfx11
    UINT64_C(3439394816), UINT64_C(0),	// V_INTERP_P2_F32_inreg_gfx12
    UINT64_C(3355508736), UINT64_C(0),	// V_INTERP_P2_F32_si
    UINT64_C(3556835328), UINT64_C(0),	// V_INTERP_P2_F32_vi
    UINT64_C(3530948608), UINT64_C(0),	// V_INTERP_P2_LEGACY_F16_gfx9
    UINT64_C(3439656960), UINT64_C(0),	// V_INTERP_P2_RTZ_F16_F32_inreg_fake16_gfx11
    UINT64_C(3439656960), UINT64_C(0),	// V_INTERP_P2_RTZ_F16_F32_inreg_fake16_gfx12
    UINT64_C(3439656960), UINT64_C(0),	// V_INTERP_P2_RTZ_F16_F32_inreg_t16_gfx11
    UINT64_C(3439656960), UINT64_C(0),	// V_INTERP_P2_RTZ_F16_F32_inreg_t16_gfx12
    UINT64_C(1979711488), UINT64_C(0),	// V_LDEXP_F16_dpp8_gfx10
    UINT64_C(1979711738), UINT64_C(0),	// V_LDEXP_F16_dpp_gfx10
    UINT64_C(1711276282), UINT64_C(0),	// V_LDEXP_F16_dpp_vi
    UINT64_C(1979711488), UINT64_C(0),	// V_LDEXP_F16_e32_gfx10
    UINT64_C(1711276032), UINT64_C(0),	// V_LDEXP_F16_e32_vi
    UINT64_C(3577413632), UINT64_C(0),	// V_LDEXP_F16_e64_gfx10
    UINT64_C(3509780480), UINT64_C(0),	// V_LDEXP_F16_e64_vi
    UINT64_C(1979711488), UINT64_C(0),	// V_LDEXP_F16_fake16_dpp8_gfx11
    UINT64_C(1979711488), UINT64_C(0),	// V_LDEXP_F16_fake16_dpp8_gfx12
    UINT64_C(1979711738), UINT64_C(0),	// V_LDEXP_F16_fake16_dpp_gfx11
    UINT64_C(1979711738), UINT64_C(0),	// V_LDEXP_F16_fake16_dpp_gfx12
    UINT64_C(1979711488), UINT64_C(0),	// V_LDEXP_F16_fake16_e32_gfx11
    UINT64_C(1979711488), UINT64_C(0),	// V_LDEXP_F16_fake16_e32_gfx12
    UINT64_C(3577413632), UINT64_C(0),	// V_LDEXP_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3577413632), UINT64_C(0),	// V_LDEXP_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077319237632), UINT64_C(0),	// V_LDEXP_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077319237632), UINT64_C(0),	// V_LDEXP_F16_fake16_e64_dpp_gfx12
    UINT64_C(3577413632), UINT64_C(0),	// V_LDEXP_F16_fake16_e64_gfx11
    UINT64_C(3577413632), UINT64_C(0),	// V_LDEXP_F16_fake16_e64_gfx12
    UINT64_C(1979711737), UINT64_C(0),	// V_LDEXP_F16_sdwa_gfx10
    UINT64_C(1711276281), UINT64_C(0),	// V_LDEXP_F16_sdwa_gfx9
    UINT64_C(1711276281), UINT64_C(0),	// V_LDEXP_F16_sdwa_vi
    UINT64_C(1979711488), UINT64_C(0),	// V_LDEXP_F16_t16_dpp8_gfx11
    UINT64_C(1979711488), UINT64_C(0),	// V_LDEXP_F16_t16_dpp8_gfx12
    UINT64_C(1979711738), UINT64_C(0),	// V_LDEXP_F16_t16_dpp_gfx11
    UINT64_C(1979711738), UINT64_C(0),	// V_LDEXP_F16_t16_dpp_gfx12
    UINT64_C(1979711488), UINT64_C(0),	// V_LDEXP_F16_t16_e32_gfx11
    UINT64_C(1979711488), UINT64_C(0),	// V_LDEXP_F16_t16_e32_gfx12
    UINT64_C(3577413632), UINT64_C(0),	// V_LDEXP_F16_t16_e64_dpp8_gfx11
    UINT64_C(3577413632), UINT64_C(0),	// V_LDEXP_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077319237632), UINT64_C(0),	// V_LDEXP_F16_t16_e64_dpp_gfx11
    UINT64_C(1077319237632), UINT64_C(0),	// V_LDEXP_F16_t16_e64_dpp_gfx12
    UINT64_C(3577413632), UINT64_C(0),	// V_LDEXP_F16_t16_e64_gfx11
    UINT64_C(3577413632), UINT64_C(0),	// V_LDEXP_F16_t16_e64_gfx12
    UINT64_C(1442840576), UINT64_C(0),	// V_LDEXP_F32_e32_gfx6_gfx7
    UINT64_C(3608936448), UINT64_C(0),	// V_LDEXP_F32_e64_dpp8_gfx11
    UINT64_C(3608936448), UINT64_C(0),	// V_LDEXP_F32_e64_dpp8_gfx12
    UINT64_C(1077350760448), UINT64_C(0),	// V_LDEXP_F32_e64_dpp_gfx11
    UINT64_C(1077350760448), UINT64_C(0),	// V_LDEXP_F32_e64_dpp_gfx12
    UINT64_C(3613523968), UINT64_C(0),	// V_LDEXP_F32_e64_gfx10
    UINT64_C(3608936448), UINT64_C(0),	// V_LDEXP_F32_e64_gfx11
    UINT64_C(3608936448), UINT64_C(0),	// V_LDEXP_F32_e64_gfx12
    UINT64_C(3528851456), UINT64_C(0),	// V_LDEXP_F32_e64_gfx6_gfx7
    UINT64_C(3532128256), UINT64_C(0),	// V_LDEXP_F32_e64_vi
    UINT64_C(1077351743488), UINT64_C(0),	// V_LDEXP_F64_e64_dpp_gfx1250
    UINT64_C(3609919488), UINT64_C(0),	// V_LDEXP_F64_e64_gfx11
    UINT64_C(3609919488), UINT64_C(0),	// V_LDEXP_F64_e64_gfx12
    UINT64_C(3609919488), UINT64_C(0),	// V_LDEXP_F64_e64_gfx1250
    UINT64_C(3580362752), UINT64_C(0),	// V_LDEXP_F64_gfx10
    UINT64_C(3536846848), UINT64_C(0),	// V_LDEXP_F64_gfx6_gfx7
    UINT64_C(3531866112), UINT64_C(0),	// V_LDEXP_F64_vi
    UINT64_C(3591700480), UINT64_C(0),	// V_LERP_U8_e64_dpp8_gfx11
    UINT64_C(3591700480), UINT64_C(0),	// V_LERP_U8_e64_dpp8_gfx12
    UINT64_C(1077333524480), UINT64_C(0),	// V_LERP_U8_e64_dpp_gfx11
    UINT64_C(1077333524480), UINT64_C(0),	// V_LERP_U8_e64_dpp_gfx12
    UINT64_C(3591700480), UINT64_C(0),	// V_LERP_U8_e64_gfx11
    UINT64_C(3591700480), UINT64_C(0),	// V_LERP_U8_e64_gfx12
    UINT64_C(3578593280), UINT64_C(0),	// V_LERP_U8_gfx10
    UINT64_C(3533307904), UINT64_C(0),	// V_LERP_U8_gfx6_gfx7
    UINT64_C(3519873024), UINT64_C(0),	// V_LERP_U8_vi
    UINT64_C(2113992704), UINT64_C(0),	// V_LOG_BF16V_LOG_BF16_fake16_dpp8_gfx1250
    UINT64_C(2113992954), UINT64_C(0),	// V_LOG_BF16V_LOG_BF16_fake16_dpp_gfx1250
    UINT64_C(2113992704), UINT64_C(0),	// V_LOG_BF16V_LOG_BF16_fake16_e32_gfx1250
    UINT64_C(3590062080), UINT64_C(0),	// V_LOG_BF16V_LOG_BF16_fake16_e64_dpp8_gfx1250
    UINT64_C(1077331886080), UINT64_C(0),	// V_LOG_BF16V_LOG_BF16_fake16_e64_dpp_gfx1250
    UINT64_C(3590062080), UINT64_C(0),	// V_LOG_BF16V_LOG_BF16_fake16_e64_gfx1250
    UINT64_C(2113992704), UINT64_C(0),	// V_LOG_BF16V_LOG_BF16_t16_dpp8_gfx1250
    UINT64_C(2113992954), UINT64_C(0),	// V_LOG_BF16V_LOG_BF16_t16_dpp_gfx1250
    UINT64_C(2113992704), UINT64_C(0),	// V_LOG_BF16V_LOG_BF16_t16_e32_gfx1250
    UINT64_C(3590062080), UINT64_C(0),	// V_LOG_BF16V_LOG_BF16_t16_e64_dpp8_gfx1250
    UINT64_C(1077331886080), UINT64_C(0),	// V_LOG_BF16V_LOG_BF16_t16_e64_dpp_gfx1250
    UINT64_C(3590062080), UINT64_C(0),	// V_LOG_BF16V_LOG_BF16_t16_e64_gfx1250
    UINT64_C(2113948672), UINT64_C(0),	// V_LOG_CLAMP_F32_e32_gfx6_gfx7
    UINT64_C(3544973312), UINT64_C(0),	// V_LOG_CLAMP_F32_e64_gfx6_gfx7
    UINT64_C(2113973760), UINT64_C(0),	// V_LOG_F16_dpp8_gfx10
    UINT64_C(2113974010), UINT64_C(0),	// V_LOG_F16_dpp_gfx10
    UINT64_C(2113962234), UINT64_C(0),	// V_LOG_F16_dpp_vi
    UINT64_C(2113973760), UINT64_C(0),	// V_LOG_F16_e32_gfx10
    UINT64_C(2113961984), UINT64_C(0),	// V_LOG_F16_e32_vi
    UINT64_C(3587637248), UINT64_C(0),	// V_LOG_F16_e64_gfx10
    UINT64_C(3514826752), UINT64_C(0),	// V_LOG_F16_e64_vi
    UINT64_C(2113973760), UINT64_C(0),	// V_LOG_F16_fake16_dpp8_gfx11
    UINT64_C(2113973760), UINT64_C(0),	// V_LOG_F16_fake16_dpp8_gfx12
    UINT64_C(2113974010), UINT64_C(0),	// V_LOG_F16_fake16_dpp_gfx11
    UINT64_C(2113974010), UINT64_C(0),	// V_LOG_F16_fake16_dpp_gfx12
    UINT64_C(2113973760), UINT64_C(0),	// V_LOG_F16_fake16_e32_gfx11
    UINT64_C(2113973760), UINT64_C(0),	// V_LOG_F16_fake16_e32_gfx12
    UINT64_C(3587637248), UINT64_C(0),	// V_LOG_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3587637248), UINT64_C(0),	// V_LOG_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077329461248), UINT64_C(0),	// V_LOG_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077329461248), UINT64_C(0),	// V_LOG_F16_fake16_e64_dpp_gfx12
    UINT64_C(3587637248), UINT64_C(0),	// V_LOG_F16_fake16_e64_gfx11
    UINT64_C(3587637248), UINT64_C(0),	// V_LOG_F16_fake16_e64_gfx12
    UINT64_C(2113974009), UINT64_C(0),	// V_LOG_F16_sdwa_gfx10
    UINT64_C(2113962233), UINT64_C(0),	// V_LOG_F16_sdwa_gfx9
    UINT64_C(2113962233), UINT64_C(0),	// V_LOG_F16_sdwa_vi
    UINT64_C(2113973760), UINT64_C(0),	// V_LOG_F16_t16_dpp8_gfx11
    UINT64_C(2113973760), UINT64_C(0),	// V_LOG_F16_t16_dpp8_gfx12
    UINT64_C(2113974010), UINT64_C(0),	// V_LOG_F16_t16_dpp_gfx11
    UINT64_C(2113974010), UINT64_C(0),	// V_LOG_F16_t16_dpp_gfx12
    UINT64_C(2113973760), UINT64_C(0),	// V_LOG_F16_t16_e32_gfx11
    UINT64_C(2113973760), UINT64_C(0),	// V_LOG_F16_t16_e32_gfx12
    UINT64_C(3587637248), UINT64_C(0),	// V_LOG_F16_t16_e64_dpp8_gfx11
    UINT64_C(3587637248), UINT64_C(0),	// V_LOG_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077329461248), UINT64_C(0),	// V_LOG_F16_t16_e64_dpp_gfx11
    UINT64_C(1077329461248), UINT64_C(0),	// V_LOG_F16_t16_e64_dpp_gfx12
    UINT64_C(3587637248), UINT64_C(0),	// V_LOG_F16_t16_e64_gfx11
    UINT64_C(3587637248), UINT64_C(0),	// V_LOG_F16_t16_e64_gfx12
    UINT64_C(2113949184), UINT64_C(0),	// V_LOG_F32_dpp8_gfx10
    UINT64_C(2113949184), UINT64_C(0),	// V_LOG_F32_dpp8_gfx11
    UINT64_C(2113949184), UINT64_C(0),	// V_LOG_F32_dpp8_gfx12
    UINT64_C(2113949434), UINT64_C(0),	// V_LOG_F32_dpp_gfx10
    UINT64_C(2113949434), UINT64_C(0),	// V_LOG_F32_dpp_gfx11
    UINT64_C(2113949434), UINT64_C(0),	// V_LOG_F32_dpp_gfx12
    UINT64_C(2113946362), UINT64_C(0),	// V_LOG_F32_dpp_vi
    UINT64_C(2113949184), UINT64_C(0),	// V_LOG_F32_e32_gfx10
    UINT64_C(2113949184), UINT64_C(0),	// V_LOG_F32_e32_gfx11
    UINT64_C(2113949184), UINT64_C(0),	// V_LOG_F32_e32_gfx12
    UINT64_C(2113949184), UINT64_C(0),	// V_LOG_F32_e32_gfx6_gfx7
    UINT64_C(2113946112), UINT64_C(0),	// V_LOG_F32_e32_vi
    UINT64_C(3584491520), UINT64_C(0),	// V_LOG_F32_e64_dpp8_gfx11
    UINT64_C(3584491520), UINT64_C(0),	// V_LOG_F32_e64_dpp8_gfx12
    UINT64_C(1077326315520), UINT64_C(0),	// V_LOG_F32_e64_dpp_gfx11
    UINT64_C(1077326315520), UINT64_C(0),	// V_LOG_F32_e64_dpp_gfx12
    UINT64_C(3584491520), UINT64_C(0),	// V_LOG_F32_e64_gfx10
    UINT64_C(3584491520), UINT64_C(0),	// V_LOG_F32_e64_gfx11
    UINT64_C(3584491520), UINT64_C(0),	// V_LOG_F32_e64_gfx12
    UINT64_C(3545104384), UINT64_C(0),	// V_LOG_F32_e64_gfx6_gfx7
    UINT64_C(3512795136), UINT64_C(0),	// V_LOG_F32_e64_vi
    UINT64_C(2113949433), UINT64_C(0),	// V_LOG_F32_sdwa_gfx10
    UINT64_C(2113946361), UINT64_C(0),	// V_LOG_F32_sdwa_gfx9
    UINT64_C(2113946361), UINT64_C(0),	// V_LOG_F32_sdwa_vi
    UINT64_C(2113968378), UINT64_C(0),	// V_LOG_LEGACY_F32_dpp_vi
    UINT64_C(2113964544), UINT64_C(0),	// V_LOG_LEGACY_F32_e32_gfx7
    UINT64_C(2113968128), UINT64_C(0),	// V_LOG_LEGACY_F32_e32_vi
    UINT64_C(3549036544), UINT64_C(0),	// V_LOG_LEGACY_F32_e64_gfx7
    UINT64_C(3515613184), UINT64_C(0),	// V_LOG_LEGACY_F32_e64_vi
    UINT64_C(2113968377), UINT64_C(0),	// V_LOG_LEGACY_F32_sdwa_gfx9
    UINT64_C(2113968377), UINT64_C(0),	// V_LOG_LEGACY_F32_sdwa_vi
    UINT64_C(1409286394), UINT64_C(0),	// V_LSHLREV_B16_dpp_vi
    UINT64_C(1409286144), UINT64_C(0),	// V_LSHLREV_B16_e32_vi
    UINT64_C(3509190656), UINT64_C(0),	// V_LSHLREV_B16_e64_vi
    UINT64_C(3610771456), UINT64_C(0),	// V_LSHLREV_B16_fake16_e64_dpp8_gfx11
    UINT64_C(3610771456), UINT64_C(0),	// V_LSHLREV_B16_fake16_e64_dpp8_gfx12
    UINT64_C(1077352595456), UINT64_C(0),	// V_LSHLREV_B16_fake16_e64_dpp_gfx11
    UINT64_C(1077352595456), UINT64_C(0),	// V_LSHLREV_B16_fake16_e64_dpp_gfx12
    UINT64_C(3610771456), UINT64_C(0),	// V_LSHLREV_B16_fake16_e64_gfx11
    UINT64_C(3610771456), UINT64_C(0),	// V_LSHLREV_B16_fake16_e64_gfx12
    UINT64_C(3608412160), UINT64_C(0),	// V_LSHLREV_B16_gfx10
    UINT64_C(1409286393), UINT64_C(0),	// V_LSHLREV_B16_sdwa_gfx9
    UINT64_C(1409286393), UINT64_C(0),	// V_LSHLREV_B16_sdwa_vi
    UINT64_C(3610771456), UINT64_C(0),	// V_LSHLREV_B16_t16_e64_dpp8_gfx11
    UINT64_C(3610771456), UINT64_C(0),	// V_LSHLREV_B16_t16_e64_dpp8_gfx12
    UINT64_C(1077352595456), UINT64_C(0),	// V_LSHLREV_B16_t16_e64_dpp_gfx11
    UINT64_C(1077352595456), UINT64_C(0),	// V_LSHLREV_B16_t16_e64_dpp_gfx12
    UINT64_C(3610771456), UINT64_C(0),	// V_LSHLREV_B16_t16_e64_gfx11
    UINT64_C(3610771456), UINT64_C(0),	// V_LSHLREV_B16_t16_e64_gfx12
    UINT64_C(872415232), UINT64_C(0),	// V_LSHLREV_B32_dpp8_gfx10
    UINT64_C(805306368), UINT64_C(0),	// V_LSHLREV_B32_dpp8_gfx11
    UINT64_C(805306368), UINT64_C(0),	// V_LSHLREV_B32_dpp8_gfx12
    UINT64_C(872415482), UINT64_C(0),	// V_LSHLREV_B32_dpp_gfx10
    UINT64_C(805306618), UINT64_C(0),	// V_LSHLREV_B32_dpp_gfx11
    UINT64_C(805306618), UINT64_C(0),	// V_LSHLREV_B32_dpp_gfx12
    UINT64_C(603980026), UINT64_C(0),	// V_LSHLREV_B32_dpp_vi
    UINT64_C(872415232), UINT64_C(0),	// V_LSHLREV_B32_e32_gfx10
    UINT64_C(805306368), UINT64_C(0),	// V_LSHLREV_B32_e32_gfx11
    UINT64_C(805306368), UINT64_C(0),	// V_LSHLREV_B32_e32_gfx12
    UINT64_C(872415232), UINT64_C(0),	// V_LSHLREV_B32_e32_gfx6_gfx7
    UINT64_C(603979776), UINT64_C(0),	// V_LSHLREV_B32_e32_vi
    UINT64_C(3575119872), UINT64_C(0),	// V_LSHLREV_B32_e64_dpp8_gfx11
    UINT64_C(3575119872), UINT64_C(0),	// V_LSHLREV_B32_e64_dpp8_gfx12
    UINT64_C(1077316943872), UINT64_C(0),	// V_LSHLREV_B32_e64_dpp_gfx11
    UINT64_C(1077316943872), UINT64_C(0),	// V_LSHLREV_B32_e64_dpp_gfx12
    UINT64_C(3575250944), UINT64_C(0),	// V_LSHLREV_B32_e64_gfx10
    UINT64_C(3575119872), UINT64_C(0),	// V_LSHLREV_B32_e64_gfx11
    UINT64_C(3575119872), UINT64_C(0),	// V_LSHLREV_B32_e64_gfx12
    UINT64_C(3526623232), UINT64_C(0),	// V_LSHLREV_B32_e64_gfx6_gfx7
    UINT64_C(3507617792), UINT64_C(0),	// V_LSHLREV_B32_e64_vi
    UINT64_C(872415481), UINT64_C(0),	// V_LSHLREV_B32_sdwa_gfx10
    UINT64_C(603980025), UINT64_C(0),	// V_LSHLREV_B32_sdwa_gfx9
    UINT64_C(603980025), UINT64_C(0),	// V_LSHLREV_B32_sdwa_vi
    UINT64_C(1040187642), UINT64_C(0),	// V_LSHLREV_B64_dpp_gfx12
    UINT64_C(1040187392), UINT64_C(0),	// V_LSHLREV_B64_e32_gfx12
    UINT64_C(1077317402624), UINT64_C(0),	// V_LSHLREV_B64_e64_dpp_gfx12
    UINT64_C(3611033600), UINT64_C(0),	// V_LSHLREV_B64_e64_gfx11
    UINT64_C(3575578624), UINT64_C(0),	// V_LSHLREV_B64_e64_gfx12
    UINT64_C(3607035904), UINT64_C(0),	// V_LSHLREV_B64_gfx10
    UINT64_C(3532587008), UINT64_C(0),	// V_LSHLREV_B64_vi
    UINT64_C(3594911744), UINT64_C(0),	// V_LSHL_ADD_U32_e64_dpp8_gfx11
    UINT64_C(3594911744), UINT64_C(0),	// V_LSHL_ADD_U32_e64_dpp8_gfx12
    UINT64_C(1077336735744), UINT64_C(0),	// V_LSHL_ADD_U32_e64_dpp_gfx11
    UINT64_C(1077336735744), UINT64_C(0),	// V_LSHL_ADD_U32_e64_dpp_gfx12
    UINT64_C(3594911744), UINT64_C(0),	// V_LSHL_ADD_U32_e64_gfx11
    UINT64_C(3594911744), UINT64_C(0),	// V_LSHL_ADD_U32_e64_gfx12
    UINT64_C(3611688960), UINT64_C(0),	// V_LSHL_ADD_U32_gfx10
    UINT64_C(3523018752), UINT64_C(0),	// V_LSHL_ADD_U32_vi
    UINT64_C(1077337522176), UINT64_C(0),	// V_LSHL_ADD_U64_e64_dpp_gfx1250
    UINT64_C(3595698176), UINT64_C(0),	// V_LSHL_ADD_U64_e64_gfx1250
    UINT64_C(3523739648), UINT64_C(0),	// V_LSHL_ADD_U64_vi
    UINT64_C(838860800), UINT64_C(0),	// V_LSHL_B32_e32_gfx6_gfx7
    UINT64_C(3526492160), UINT64_C(0),	// V_LSHL_B32_e64_gfx6_gfx7
    UINT64_C(3535929344), UINT64_C(0),	// V_LSHL_B64_gfx6_gfx7
    UINT64_C(3595960320), UINT64_C(0),	// V_LSHL_OR_B32_e64_dpp8_gfx11
    UINT64_C(3595960320), UINT64_C(0),	// V_LSHL_OR_B32_e64_dpp8_gfx12
    UINT64_C(1077337784320), UINT64_C(0),	// V_LSHL_OR_B32_e64_dpp_gfx11
    UINT64_C(1077337784320), UINT64_C(0),	// V_LSHL_OR_B32_e64_dpp_gfx12
    UINT64_C(3595960320), UINT64_C(0),	// V_LSHL_OR_B32_e64_gfx11
    UINT64_C(3595960320), UINT64_C(0),	// V_LSHL_OR_B32_e64_gfx12
    UINT64_C(3614375936), UINT64_C(0),	// V_LSHL_OR_B32_gfx10
    UINT64_C(3523215360), UINT64_C(0),	// V_LSHL_OR_B32_vi
    UINT64_C(1442840826), UINT64_C(0),	// V_LSHRREV_B16_dpp_vi
    UINT64_C(1442840576), UINT64_C(0),	// V_LSHRREV_B16_e32_vi
    UINT64_C(3509256192), UINT64_C(0),	// V_LSHRREV_B16_e64_vi
    UINT64_C(3610836992), UINT64_C(0),	// V_LSHRREV_B16_fake16_e64_dpp8_gfx11
    UINT64_C(3610836992), UINT64_C(0),	// V_LSHRREV_B16_fake16_e64_dpp8_gfx12
    UINT64_C(1077352660992), UINT64_C(0),	// V_LSHRREV_B16_fake16_e64_dpp_gfx11
    UINT64_C(1077352660992), UINT64_C(0),	// V_LSHRREV_B16_fake16_e64_dpp_gfx12
    UINT64_C(3610836992), UINT64_C(0),	// V_LSHRREV_B16_fake16_e64_gfx11
    UINT64_C(3610836992), UINT64_C(0),	// V_LSHRREV_B16_fake16_e64_gfx12
    UINT64_C(3607560192), UINT64_C(0),	// V_LSHRREV_B16_gfx10
    UINT64_C(1442840825), UINT64_C(0),	// V_LSHRREV_B16_sdwa_gfx9
    UINT64_C(1442840825), UINT64_C(0),	// V_LSHRREV_B16_sdwa_vi
    UINT64_C(3610836992), UINT64_C(0),	// V_LSHRREV_B16_t16_e64_dpp8_gfx11
    UINT64_C(3610836992), UINT64_C(0),	// V_LSHRREV_B16_t16_e64_dpp8_gfx12
    UINT64_C(1077352660992), UINT64_C(0),	// V_LSHRREV_B16_t16_e64_dpp_gfx11
    UINT64_C(1077352660992), UINT64_C(0),	// V_LSHRREV_B16_t16_e64_dpp_gfx12
    UINT64_C(3610836992), UINT64_C(0),	// V_LSHRREV_B16_t16_e64_gfx11
    UINT64_C(3610836992), UINT64_C(0),	// V_LSHRREV_B16_t16_e64_gfx12
    UINT64_C(738197504), UINT64_C(0),	// V_LSHRREV_B32_dpp8_gfx10
    UINT64_C(838860800), UINT64_C(0),	// V_LSHRREV_B32_dpp8_gfx11
    UINT64_C(838860800), UINT64_C(0),	// V_LSHRREV_B32_dpp8_gfx12
    UINT64_C(738197754), UINT64_C(0),	// V_LSHRREV_B32_dpp_gfx10
    UINT64_C(838861050), UINT64_C(0),	// V_LSHRREV_B32_dpp_gfx11
    UINT64_C(838861050), UINT64_C(0),	// V_LSHRREV_B32_dpp_gfx12
    UINT64_C(536871162), UINT64_C(0),	// V_LSHRREV_B32_dpp_vi
    UINT64_C(738197504), UINT64_C(0),	// V_LSHRREV_B32_e32_gfx10
    UINT64_C(838860800), UINT64_C(0),	// V_LSHRREV_B32_e32_gfx11
    UINT64_C(838860800), UINT64_C(0),	// V_LSHRREV_B32_e32_gfx12
    UINT64_C(738197504), UINT64_C(0),	// V_LSHRREV_B32_e32_gfx6_gfx7
    UINT64_C(536870912), UINT64_C(0),	// V_LSHRREV_B32_e32_vi
    UINT64_C(3575185408), UINT64_C(0),	// V_LSHRREV_B32_e64_dpp8_gfx11
    UINT64_C(3575185408), UINT64_C(0),	// V_LSHRREV_B32_e64_dpp8_gfx12
    UINT64_C(1077317009408), UINT64_C(0),	// V_LSHRREV_B32_e64_dpp_gfx11
    UINT64_C(1077317009408), UINT64_C(0),	// V_LSHRREV_B32_e64_dpp_gfx12
    UINT64_C(3574988800), UINT64_C(0),	// V_LSHRREV_B32_e64_gfx10
    UINT64_C(3575185408), UINT64_C(0),	// V_LSHRREV_B32_e64_gfx11
    UINT64_C(3575185408), UINT64_C(0),	// V_LSHRREV_B32_e64_gfx12
    UINT64_C(3526098944), UINT64_C(0),	// V_LSHRREV_B32_e64_gfx6_gfx7
    UINT64_C(3507486720), UINT64_C(0),	// V_LSHRREV_B32_e64_vi
    UINT64_C(738197753), UINT64_C(0),	// V_LSHRREV_B32_sdwa_gfx10
    UINT64_C(536871161), UINT64_C(0),	// V_LSHRREV_B32_sdwa_gfx9
    UINT64_C(536871161), UINT64_C(0),	// V_LSHRREV_B32_sdwa_vi
    UINT64_C(1077352923136), UINT64_C(0),	// V_LSHRREV_B64_e64_dpp_gfx1250
    UINT64_C(3611099136), UINT64_C(0),	// V_LSHRREV_B64_e64_gfx11
    UINT64_C(3611099136), UINT64_C(0),	// V_LSHRREV_B64_e64_gfx12
    UINT64_C(3611099136), UINT64_C(0),	// V_LSHRREV_B64_e64_gfx1250
    UINT64_C(3607101440), UINT64_C(0),	// V_LSHRREV_B64_gfx10
    UINT64_C(3532652544), UINT64_C(0),	// V_LSHRREV_B64_vi
    UINT64_C(704643072), UINT64_C(0),	// V_LSHR_B32_e32_gfx6_gfx7
    UINT64_C(3525967872), UINT64_C(0),	// V_LSHR_B32_e64_gfx6_gfx7
    UINT64_C(3536060416), UINT64_C(0),	// V_LSHR_B64_gfx6_gfx7
    UINT64_C(1174405370), UINT64_C(0),	// V_MAC_F16_dpp_vi
    UINT64_C(1174405120), UINT64_C(0),	// V_MAC_F16_e32_vi
    UINT64_C(3508731904), UINT64_C(0),	// V_MAC_F16_e64_vi
    UINT64_C(1174405369), UINT64_C(0),	// V_MAC_F16_sdwa_vi
    UINT64_C(1040187392), UINT64_C(0),	// V_MAC_F32_dpp8_gfx10
    UINT64_C(1040187642), UINT64_C(0),	// V_MAC_F32_dpp_gfx10
    UINT64_C(738197754), UINT64_C(0),	// V_MAC_F32_dpp_vi
    UINT64_C(1040187392), UINT64_C(0),	// V_MAC_F32_e32_gfx10
    UINT64_C(1040187392), UINT64_C(0),	// V_MAC_F32_e32_gfx6_gfx7
    UINT64_C(738197504), UINT64_C(0),	// V_MAC_F32_e32_vi
    UINT64_C(3575578624), UINT64_C(0),	// V_MAC_F32_e64_gfx10
    UINT64_C(3527278592), UINT64_C(0),	// V_MAC_F32_e64_gfx6_gfx7
    UINT64_C(3507879936), UINT64_C(0),	// V_MAC_F32_e64_vi
    UINT64_C(738197753), UINT64_C(0),	// V_MAC_F32_sdwa_vi
    UINT64_C(201326592), UINT64_C(0),	// V_MAC_LEGACY_F32_e32_gfx10
    UINT64_C(201326592), UINT64_C(0),	// V_MAC_LEGACY_F32_e32_gfx6_gfx7
    UINT64_C(3573940224), UINT64_C(0),	// V_MAC_LEGACY_F32_e64_gfx10
    UINT64_C(3524001792), UINT64_C(0),	// V_MAC_LEGACY_F32_e64_gfx6_gfx7
    UINT64_C(1241513984), UINT64_C(0),	// V_MADAK_F16_vi
    UINT64_C(1107296256), UINT64_C(0),	// V_MADAK_F32_gfx10
    UINT64_C(1107296256), UINT64_C(0),	// V_MADAK_F32_gfx6_gfx7
    UINT64_C(805306368), UINT64_C(0),	// V_MADAK_F32_vi
    UINT64_C(1207959552), UINT64_C(0),	// V_MADMK_F16_vi
    UINT64_C(1073741824), UINT64_C(0),	// V_MADMK_F32_gfx10
    UINT64_C(1073741824), UINT64_C(0),	// V_MADMK_F32_gfx6_gfx7
    UINT64_C(771751936), UINT64_C(0),	// V_MADMK_F32_vi
    UINT64_C(1077348859904), UINT64_C(0),	// V_MAD_CO_I64_I32_e64_dpp_gfx12
    UINT64_C(3607035904), UINT64_C(0),	// V_MAD_CO_I64_I32_e64_gfx12
    UINT64_C(1077348794368), UINT64_C(0),	// V_MAD_CO_U64_U32_e64_dpp_gfx12
    UINT64_C(3606970368), UINT64_C(0),	// V_MAD_CO_U64_U32_e64_gfx12
    UINT64_C(3523411968), UINT64_C(0),	// V_MAD_F16_gfx9_gfx9
    UINT64_C(3521773568), UINT64_C(0),	// V_MAD_F16_vi
    UINT64_C(3577806848), UINT64_C(0),	// V_MAD_F32_gfx10
    UINT64_C(3531735040), UINT64_C(0),	// V_MAD_F32_gfx6_gfx7
    UINT64_C(3519086592), UINT64_C(0),	// V_MAD_F32_vi
    UINT64_C(3595763712), UINT64_C(0),	// V_MAD_I16V_MAD_I16_gfx9_fake16_e64_dpp8_gfx11
    UINT64_C(3595763712), UINT64_C(0),	// V_MAD_I16V_MAD_I16_gfx9_fake16_e64_dpp8_gfx12
    UINT64_C(1077337587712), UINT64_C(0),	// V_MAD_I16V_MAD_I16_gfx9_fake16_e64_dpp_gfx11
    UINT64_C(1077337587712), UINT64_C(0),	// V_MAD_I16V_MAD_I16_gfx9_fake16_e64_dpp_gfx12
    UINT64_C(3595763712), UINT64_C(0),	// V_MAD_I16V_MAD_I16_gfx9_fake16_e64_gfx11
    UINT64_C(3595763712), UINT64_C(0),	// V_MAD_I16V_MAD_I16_gfx9_fake16_e64_gfx12
    UINT64_C(3595763712), UINT64_C(0),	// V_MAD_I16V_MAD_I16_gfx9_t16_e64_dpp8_gfx11
    UINT64_C(3595763712), UINT64_C(0),	// V_MAD_I16V_MAD_I16_gfx9_t16_e64_dpp8_gfx12
    UINT64_C(1077337587712), UINT64_C(0),	// V_MAD_I16V_MAD_I16_gfx9_t16_e64_dpp_gfx11
    UINT64_C(1077337587712), UINT64_C(0),	// V_MAD_I16V_MAD_I16_gfx9_t16_e64_dpp_gfx12
    UINT64_C(3595763712), UINT64_C(0),	// V_MAD_I16V_MAD_I16_gfx9_t16_e64_gfx11
    UINT64_C(3595763712), UINT64_C(0),	// V_MAD_I16V_MAD_I16_gfx9_t16_e64_gfx12
    UINT64_C(3613261824), UINT64_C(0),	// V_MAD_I16_gfx10
    UINT64_C(3523543040), UINT64_C(0),	// V_MAD_I16_gfx9_gfx9
    UINT64_C(3521904640), UINT64_C(0),	// V_MAD_I16_vi
    UINT64_C(3596222464), UINT64_C(0),	// V_MAD_I32_I16V_MAD_I32_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3596222464), UINT64_C(0),	// V_MAD_I32_I16V_MAD_I32_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077338046464), UINT64_C(0),	// V_MAD_I32_I16V_MAD_I32_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077338046464), UINT64_C(0),	// V_MAD_I32_I16V_MAD_I32_I16_fake16_e64_dpp_gfx12
    UINT64_C(3596222464), UINT64_C(0),	// V_MAD_I32_I16V_MAD_I32_I16_fake16_e64_gfx11
    UINT64_C(3596222464), UINT64_C(0),	// V_MAD_I32_I16V_MAD_I32_I16_fake16_e64_gfx12
    UINT64_C(3596222464), UINT64_C(0),	// V_MAD_I32_I16V_MAD_I32_I16_t16_e64_dpp8_gfx11
    UINT64_C(3596222464), UINT64_C(0),	// V_MAD_I32_I16V_MAD_I32_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077338046464), UINT64_C(0),	// V_MAD_I32_I16V_MAD_I32_I16_t16_e64_dpp_gfx11
    UINT64_C(1077338046464), UINT64_C(0),	// V_MAD_I32_I16V_MAD_I32_I16_t16_e64_dpp_gfx12
    UINT64_C(3596222464), UINT64_C(0),	// V_MAD_I32_I16V_MAD_I32_I16_t16_e64_gfx11
    UINT64_C(3596222464), UINT64_C(0),	// V_MAD_I32_I16V_MAD_I32_I16_t16_e64_gfx12
    UINT64_C(3614769152), UINT64_C(0),	// V_MAD_I32_I16_gfx10
    UINT64_C(3522297856), UINT64_C(0),	// V_MAD_I32_I16_vi
    UINT64_C(3590979584), UINT64_C(0),	// V_MAD_I32_I24_e64_dpp8_gfx11
    UINT64_C(3590979584), UINT64_C(0),	// V_MAD_I32_I24_e64_dpp8_gfx12
    UINT64_C(1077332803584), UINT64_C(0),	// V_MAD_I32_I24_e64_dpp_gfx11
    UINT64_C(1077332803584), UINT64_C(0),	// V_MAD_I32_I24_e64_dpp_gfx12
    UINT64_C(3590979584), UINT64_C(0),	// V_MAD_I32_I24_e64_gfx11
    UINT64_C(3590979584), UINT64_C(0),	// V_MAD_I32_I24_e64_gfx12
    UINT64_C(3577872384), UINT64_C(0),	// V_MAD_I32_I24_gfx10
    UINT64_C(3531866112), UINT64_C(0),	// V_MAD_I32_I24_gfx6_gfx7
    UINT64_C(3519152128), UINT64_C(0),	// V_MAD_I32_I24_vi
    UINT64_C(3581345792), UINT64_C(0),	// V_MAD_I64_I32_gfx10
    UINT64_C(3607035904), UINT64_C(0),	// V_MAD_I64_I32_gfx11_e64_gfx11
    UINT64_C(3538812928), UINT64_C(0),	// V_MAD_I64_I32_gfx7
    UINT64_C(3521708032), UINT64_C(0),	// V_MAD_I64_I32_vi
    UINT64_C(3521773568), UINT64_C(0),	// V_MAD_LEGACY_F16_gfx9
    UINT64_C(3577741312), UINT64_C(0),	// V_MAD_LEGACY_F32_gfx10
    UINT64_C(3531603968), UINT64_C(0),	// V_MAD_LEGACY_F32_gfx6_gfx7
    UINT64_C(3519021056), UINT64_C(0),	// V_MAD_LEGACY_F32_vi
    UINT64_C(3521904640), UINT64_C(0),	// V_MAD_LEGACY_I16_gfx9
    UINT64_C(3521839104), UINT64_C(0),	// V_MAD_LEGACY_U16_gfx9
    UINT64_C(3550609408), UINT64_C(0),	// V_MAD_MIXHI_F16_vi
    UINT64_C(3550543872), UINT64_C(0),	// V_MAD_MIXLO_F16_vi
    UINT64_C(3550478336), UINT64_C(0),	// V_MAD_MIX_F32_vi
    UINT64_C(1077348597760), UINT64_C(0),	// V_MAD_NC_I64_I32_e64_dpp_gfx1250
    UINT64_C(3606773760), UINT64_C(0),	// V_MAD_NC_I64_I32_e64_gfx1250
    UINT64_C(1077348532224), UINT64_C(0),	// V_MAD_NC_U64_U32_e64_dpp_gfx1250
    UINT64_C(3606708224), UINT64_C(0),	// V_MAD_NC_U64_U32_e64_gfx1250
    UINT64_C(3594584064), UINT64_C(0),	// V_MAD_U16V_MAD_U16_gfx9_fake16_e64_dpp8_gfx11
    UINT64_C(3594584064), UINT64_C(0),	// V_MAD_U16V_MAD_U16_gfx9_fake16_e64_dpp8_gfx12
    UINT64_C(1077336408064), UINT64_C(0),	// V_MAD_U16V_MAD_U16_gfx9_fake16_e64_dpp_gfx11
    UINT64_C(1077336408064), UINT64_C(0),	// V_MAD_U16V_MAD_U16_gfx9_fake16_e64_dpp_gfx12
    UINT64_C(3594584064), UINT64_C(0),	// V_MAD_U16V_MAD_U16_gfx9_fake16_e64_gfx11
    UINT64_C(3594584064), UINT64_C(0),	// V_MAD_U16V_MAD_U16_gfx9_fake16_e64_gfx12
    UINT64_C(3594584064), UINT64_C(0),	// V_MAD_U16V_MAD_U16_gfx9_t16_e64_dpp8_gfx11
    UINT64_C(3594584064), UINT64_C(0),	// V_MAD_U16V_MAD_U16_gfx9_t16_e64_dpp8_gfx12
    UINT64_C(1077336408064), UINT64_C(0),	// V_MAD_U16V_MAD_U16_gfx9_t16_e64_dpp_gfx11
    UINT64_C(1077336408064), UINT64_C(0),	// V_MAD_U16V_MAD_U16_gfx9_t16_e64_dpp_gfx12
    UINT64_C(3594584064), UINT64_C(0),	// V_MAD_U16V_MAD_U16_gfx9_t16_e64_gfx11
    UINT64_C(3594584064), UINT64_C(0),	// V_MAD_U16V_MAD_U16_gfx9_t16_e64_gfx12
    UINT64_C(3611295744), UINT64_C(0),	// V_MAD_U16_gfx10
    UINT64_C(3523477504), UINT64_C(0),	// V_MAD_U16_gfx9_gfx9
    UINT64_C(3521839104), UINT64_C(0),	// V_MAD_U16_vi
    UINT64_C(3596156928), UINT64_C(0),	// V_MAD_U32_U16V_MAD_U32_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3596156928), UINT64_C(0),	// V_MAD_U32_U16V_MAD_U32_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077337980928), UINT64_C(0),	// V_MAD_U32_U16V_MAD_U32_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077337980928), UINT64_C(0),	// V_MAD_U32_U16V_MAD_U32_U16_fake16_e64_dpp_gfx12
    UINT64_C(3596156928), UINT64_C(0),	// V_MAD_U32_U16V_MAD_U32_U16_fake16_e64_gfx11
    UINT64_C(3596156928), UINT64_C(0),	// V_MAD_U32_U16V_MAD_U32_U16_fake16_e64_gfx12
    UINT64_C(3596156928), UINT64_C(0),	// V_MAD_U32_U16V_MAD_U32_U16_t16_e64_dpp8_gfx11
    UINT64_C(3596156928), UINT64_C(0),	// V_MAD_U32_U16V_MAD_U32_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077337980928), UINT64_C(0),	// V_MAD_U32_U16V_MAD_U32_U16_t16_e64_dpp_gfx11
    UINT64_C(1077337980928), UINT64_C(0),	// V_MAD_U32_U16V_MAD_U32_U16_t16_e64_dpp_gfx12
    UINT64_C(3596156928), UINT64_C(0),	// V_MAD_U32_U16V_MAD_U32_U16_t16_e64_gfx11
    UINT64_C(3596156928), UINT64_C(0),	// V_MAD_U32_U16V_MAD_U32_U16_t16_e64_gfx12
    UINT64_C(3614638080), UINT64_C(0),	// V_MAD_U32_U16_gfx10
    UINT64_C(3522232320), UINT64_C(0),	// V_MAD_U32_U16_vi
    UINT64_C(3591045120), UINT64_C(0),	// V_MAD_U32_U24_e64_dpp8_gfx11
    UINT64_C(3591045120), UINT64_C(0),	// V_MAD_U32_U24_e64_dpp8_gfx12
    UINT64_C(1077332869120), UINT64_C(0),	// V_MAD_U32_U24_e64_dpp_gfx11
    UINT64_C(1077332869120), UINT64_C(0),	// V_MAD_U32_U24_e64_dpp_gfx12
    UINT64_C(3591045120), UINT64_C(0),	// V_MAD_U32_U24_e64_gfx11
    UINT64_C(3591045120), UINT64_C(0),	// V_MAD_U32_U24_e64_gfx12
    UINT64_C(3577937920), UINT64_C(0),	// V_MAD_U32_U24_gfx10
    UINT64_C(3531997184), UINT64_C(0),	// V_MAD_U32_U24_gfx6_gfx7
    UINT64_C(3519217664), UINT64_C(0),	// V_MAD_U32_U24_vi
    UINT64_C(1077335621632), UINT64_C(0),	// V_MAD_U32_e64_dpp_gfx1250
    UINT64_C(3593797632), UINT64_C(0),	// V_MAD_U32_e64_gfx1250
    UINT64_C(3581280256), UINT64_C(0),	// V_MAD_U64_U32_gfx10
    UINT64_C(3606970368), UINT64_C(0),	// V_MAD_U64_U32_gfx11_e64_gfx11
    UINT64_C(3538681856), UINT64_C(0),	// V_MAD_U64_U32_gfx7
    UINT64_C(3521642496), UINT64_C(0),	// V_MAD_U64_U32_vi
    UINT64_C(3595304960), UINT64_C(0),	// V_MAX3_F16_fake16_e64_dpp8_gfx11
    UINT64_C(1077337128960), UINT64_C(0),	// V_MAX3_F16_fake16_e64_dpp_gfx11
    UINT64_C(3595304960), UINT64_C(0),	// V_MAX3_F16_fake16_e64_gfx11
    UINT64_C(3612606464), UINT64_C(0),	// V_MAX3_F16_gfx10
    UINT64_C(3595304960), UINT64_C(0),	// V_MAX3_F16_t16_e64_dpp8_gfx11
    UINT64_C(1077337128960), UINT64_C(0),	// V_MAX3_F16_t16_e64_dpp_gfx11
    UINT64_C(3595304960), UINT64_C(0),	// V_MAX3_F16_t16_e64_gfx11
    UINT64_C(3522625536), UINT64_C(0),	// V_MAX3_F16_vi
    UINT64_C(3592159232), UINT64_C(0),	// V_MAX3_F32_e64_dpp8_gfx11
    UINT64_C(1077333983232), UINT64_C(0),	// V_MAX3_F32_e64_dpp_gfx11
    UINT64_C(3592159232), UINT64_C(0),	// V_MAX3_F32_e64_gfx11
    UINT64_C(3579052032), UINT64_C(0),	// V_MAX3_F32_gfx10
    UINT64_C(3534225408), UINT64_C(0),	// V_MAX3_F32_gfx6_gfx7
    UINT64_C(3520266240), UINT64_C(0),	// V_MAX3_F32_vi
    UINT64_C(3595370496), UINT64_C(0),	// V_MAX3_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3595370496), UINT64_C(0),	// V_MAX3_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077337194496), UINT64_C(0),	// V_MAX3_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077337194496), UINT64_C(0),	// V_MAX3_I16_fake16_e64_dpp_gfx12
    UINT64_C(3595370496), UINT64_C(0),	// V_MAX3_I16_fake16_e64_gfx11
    UINT64_C(3595370496), UINT64_C(0),	// V_MAX3_I16_fake16_e64_gfx12
    UINT64_C(3612672000), UINT64_C(0),	// V_MAX3_I16_gfx10
    UINT64_C(3595370496), UINT64_C(0),	// V_MAX3_I16_t16_e64_dpp8_gfx11
    UINT64_C(3595370496), UINT64_C(0),	// V_MAX3_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077337194496), UINT64_C(0),	// V_MAX3_I16_t16_e64_dpp_gfx11
    UINT64_C(1077337194496), UINT64_C(0),	// V_MAX3_I16_t16_e64_dpp_gfx12
    UINT64_C(3595370496), UINT64_C(0),	// V_MAX3_I16_t16_e64_gfx11
    UINT64_C(3595370496), UINT64_C(0),	// V_MAX3_I16_t16_e64_gfx12
    UINT64_C(3522691072), UINT64_C(0),	// V_MAX3_I16_vi
    UINT64_C(3592224768), UINT64_C(0),	// V_MAX3_I32_e64_dpp8_gfx11
    UINT64_C(3592224768), UINT64_C(0),	// V_MAX3_I32_e64_dpp8_gfx12
    UINT64_C(1077334048768), UINT64_C(0),	// V_MAX3_I32_e64_dpp_gfx11
    UINT64_C(1077334048768), UINT64_C(0),	// V_MAX3_I32_e64_dpp_gfx12
    UINT64_C(3592224768), UINT64_C(0),	// V_MAX3_I32_e64_gfx11
    UINT64_C(3592224768), UINT64_C(0),	// V_MAX3_I32_e64_gfx12
    UINT64_C(3579117568), UINT64_C(0),	// V_MAX3_I32_gfx10
    UINT64_C(3534356480), UINT64_C(0),	// V_MAX3_I32_gfx6_gfx7
    UINT64_C(3520331776), UINT64_C(0),	// V_MAX3_I32_vi
    UINT64_C(3593207808), UINT64_C(0),	// V_MAX3_NUM_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077335031808), UINT64_C(0),	// V_MAX3_NUM_F16_fake16_e64_dpp_gfx12
    UINT64_C(3593207808), UINT64_C(0),	// V_MAX3_NUM_F16_fake16_e64_gfx12
    UINT64_C(3593207808), UINT64_C(0),	// V_MAX3_NUM_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077335031808), UINT64_C(0),	// V_MAX3_NUM_F16_t16_e64_dpp_gfx12
    UINT64_C(3593207808), UINT64_C(0),	// V_MAX3_NUM_F16_t16_e64_gfx12
    UINT64_C(3593076736), UINT64_C(0),	// V_MAX3_NUM_F32_e64_dpp8_gfx12
    UINT64_C(1077334900736), UINT64_C(0),	// V_MAX3_NUM_F32_e64_dpp_gfx12
    UINT64_C(3593076736), UINT64_C(0),	// V_MAX3_NUM_F32_e64_gfx12
    UINT64_C(3595436032), UINT64_C(0),	// V_MAX3_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3595436032), UINT64_C(0),	// V_MAX3_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077337260032), UINT64_C(0),	// V_MAX3_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077337260032), UINT64_C(0),	// V_MAX3_U16_fake16_e64_dpp_gfx12
    UINT64_C(3595436032), UINT64_C(0),	// V_MAX3_U16_fake16_e64_gfx11
    UINT64_C(3595436032), UINT64_C(0),	// V_MAX3_U16_fake16_e64_gfx12
    UINT64_C(3612737536), UINT64_C(0),	// V_MAX3_U16_gfx10
    UINT64_C(3595436032), UINT64_C(0),	// V_MAX3_U16_t16_e64_dpp8_gfx11
    UINT64_C(3595436032), UINT64_C(0),	// V_MAX3_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077337260032), UINT64_C(0),	// V_MAX3_U16_t16_e64_dpp_gfx11
    UINT64_C(1077337260032), UINT64_C(0),	// V_MAX3_U16_t16_e64_dpp_gfx12
    UINT64_C(3595436032), UINT64_C(0),	// V_MAX3_U16_t16_e64_gfx11
    UINT64_C(3595436032), UINT64_C(0),	// V_MAX3_U16_t16_e64_gfx12
    UINT64_C(3522756608), UINT64_C(0),	// V_MAX3_U16_vi
    UINT64_C(3592290304), UINT64_C(0),	// V_MAX3_U32_e64_dpp8_gfx11
    UINT64_C(3592290304), UINT64_C(0),	// V_MAX3_U32_e64_dpp8_gfx12
    UINT64_C(1077334114304), UINT64_C(0),	// V_MAX3_U32_e64_dpp_gfx11
    UINT64_C(1077334114304), UINT64_C(0),	// V_MAX3_U32_e64_dpp_gfx12
    UINT64_C(3592290304), UINT64_C(0),	// V_MAX3_U32_e64_gfx11
    UINT64_C(3592290304), UINT64_C(0),	// V_MAX3_U32_e64_gfx12
    UINT64_C(3579183104), UINT64_C(0),	// V_MAX3_U32_gfx10
    UINT64_C(3534487552), UINT64_C(0),	// V_MAX3_U32_gfx6_gfx7
    UINT64_C(3520397312), UINT64_C(0),	// V_MAX3_U32_vi
    UINT64_C(3593469952), UINT64_C(0),	// V_MAXIMUM3_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077335293952), UINT64_C(0),	// V_MAXIMUM3_F16_fake16_e64_dpp_gfx12
    UINT64_C(3593469952), UINT64_C(0),	// V_MAXIMUM3_F16_fake16_e64_gfx12
    UINT64_C(3593469952), UINT64_C(0),	// V_MAXIMUM3_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077335293952), UINT64_C(0),	// V_MAXIMUM3_F16_t16_e64_dpp_gfx12
    UINT64_C(3593469952), UINT64_C(0),	// V_MAXIMUM3_F16_t16_e64_gfx12
    UINT64_C(3593338880), UINT64_C(0),	// V_MAXIMUM3_F32_e64_dpp8_gfx12
    UINT64_C(1077335162880), UINT64_C(0),	// V_MAXIMUM3_F32_e64_dpp_gfx12
    UINT64_C(3593338880), UINT64_C(0),	// V_MAXIMUM3_F32_e64_gfx12
    UINT64_C(3534290944), UINT64_C(0),	// V_MAXIMUM3_F32_vi
    UINT64_C(3597598720), UINT64_C(0),	// V_MAXIMUMMINIMUM_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077339422720), UINT64_C(0),	// V_MAXIMUMMINIMUM_F16_fake16_e64_dpp_gfx12
    UINT64_C(3597598720), UINT64_C(0),	// V_MAXIMUMMINIMUM_F16_fake16_e64_gfx12
    UINT64_C(3597598720), UINT64_C(0),	// V_MAXIMUMMINIMUM_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077339422720), UINT64_C(0),	// V_MAXIMUMMINIMUM_F16_t16_e64_dpp_gfx12
    UINT64_C(3597598720), UINT64_C(0),	// V_MAXIMUMMINIMUM_F16_t16_e64_gfx12
    UINT64_C(3597467648), UINT64_C(0),	// V_MAXIMUMMINIMUM_F32_e64_dpp8_gfx12
    UINT64_C(1077339291648), UINT64_C(0),	// V_MAXIMUMMINIMUM_F32_e64_dpp_gfx12
    UINT64_C(3597467648), UINT64_C(0),	// V_MAXIMUMMINIMUM_F32_e64_gfx12
    UINT64_C(3613917184), UINT64_C(0),	// V_MAXIMUM_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077355741184), UINT64_C(0),	// V_MAXIMUM_F16_fake16_e64_dpp_gfx12
    UINT64_C(3613917184), UINT64_C(0),	// V_MAXIMUM_F16_fake16_e64_gfx12
    UINT64_C(3613917184), UINT64_C(0),	// V_MAXIMUM_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077355741184), UINT64_C(0),	// V_MAXIMUM_F16_t16_e64_dpp_gfx12
    UINT64_C(3613917184), UINT64_C(0),	// V_MAXIMUM_F16_t16_e64_gfx12
    UINT64_C(3613786112), UINT64_C(0),	// V_MAXIMUM_F32_e64_dpp8_gfx12
    UINT64_C(1077355610112), UINT64_C(0),	// V_MAXIMUM_F32_e64_dpp_gfx12
    UINT64_C(3613786112), UINT64_C(0),	// V_MAXIMUM_F32_e64_gfx12
    UINT64_C(1077353250816), UINT64_C(0),	// V_MAXIMUM_F64_e64_dpp_gfx11
    UINT64_C(1077353250816), UINT64_C(0),	// V_MAXIMUM_F64_e64_dpp_gfx12
    UINT64_C(3611426816), UINT64_C(0),	// V_MAXIMUM_F64_e64_gfx11
    UINT64_C(3611426816), UINT64_C(0),	// V_MAXIMUM_F64_e64_gfx12
    UINT64_C(3596615680), UINT64_C(0),	// V_MAXMIN_F16_fake16_e64_dpp8_gfx11
    UINT64_C(1077338439680), UINT64_C(0),	// V_MAXMIN_F16_fake16_e64_dpp_gfx11
    UINT64_C(3596615680), UINT64_C(0),	// V_MAXMIN_F16_fake16_e64_gfx11
    UINT64_C(3596615680), UINT64_C(0),	// V_MAXMIN_F16_t16_e64_dpp8_gfx11
    UINT64_C(1077338439680), UINT64_C(0),	// V_MAXMIN_F16_t16_e64_dpp_gfx11
    UINT64_C(3596615680), UINT64_C(0),	// V_MAXMIN_F16_t16_e64_gfx11
    UINT64_C(3596484608), UINT64_C(0),	// V_MAXMIN_F32_e64_dpp8_gfx11
    UINT64_C(1077338308608), UINT64_C(0),	// V_MAXMIN_F32_e64_dpp_gfx11
    UINT64_C(3596484608), UINT64_C(0),	// V_MAXMIN_F32_e64_gfx11
    UINT64_C(3596877824), UINT64_C(0),	// V_MAXMIN_I32_e64_dpp8_gfx11
    UINT64_C(3596877824), UINT64_C(0),	// V_MAXMIN_I32_e64_dpp8_gfx12
    UINT64_C(1077338701824), UINT64_C(0),	// V_MAXMIN_I32_e64_dpp_gfx11
    UINT64_C(1077338701824), UINT64_C(0),	// V_MAXMIN_I32_e64_dpp_gfx12
    UINT64_C(3596877824), UINT64_C(0),	// V_MAXMIN_I32_e64_gfx11
    UINT64_C(3596877824), UINT64_C(0),	// V_MAXMIN_I32_e64_gfx12
    UINT64_C(3597336576), UINT64_C(0),	// V_MAXMIN_NUM_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077339160576), UINT64_C(0),	// V_MAXMIN_NUM_F16_fake16_e64_dpp_gfx12
    UINT64_C(3597336576), UINT64_C(0),	// V_MAXMIN_NUM_F16_fake16_e64_gfx12
    UINT64_C(3597336576), UINT64_C(0),	// V_MAXMIN_NUM_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077339160576), UINT64_C(0),	// V_MAXMIN_NUM_F16_t16_e64_dpp_gfx12
    UINT64_C(3597336576), UINT64_C(0),	// V_MAXMIN_NUM_F16_t16_e64_gfx12
    UINT64_C(3597205504), UINT64_C(0),	// V_MAXMIN_NUM_F32_e64_dpp8_gfx12
    UINT64_C(1077339029504), UINT64_C(0),	// V_MAXMIN_NUM_F32_e64_dpp_gfx12
    UINT64_C(3597205504), UINT64_C(0),	// V_MAXMIN_NUM_F32_e64_gfx12
    UINT64_C(3596746752), UINT64_C(0),	// V_MAXMIN_U32_e64_dpp8_gfx11
    UINT64_C(3596746752), UINT64_C(0),	// V_MAXMIN_U32_e64_dpp8_gfx12
    UINT64_C(1077338570752), UINT64_C(0),	// V_MAXMIN_U32_e64_dpp_gfx11
    UINT64_C(1077338570752), UINT64_C(0),	// V_MAXMIN_U32_e64_dpp_gfx12
    UINT64_C(3596746752), UINT64_C(0),	// V_MAXMIN_U32_e64_gfx11
    UINT64_C(3596746752), UINT64_C(0),	// V_MAXMIN_U32_e64_gfx12
    UINT64_C(1912602624), UINT64_C(0),	// V_MAX_F16V_MAX_F16_fake16_dpp8_gfx11
    UINT64_C(1912602874), UINT64_C(0),	// V_MAX_F16V_MAX_F16_fake16_dpp_gfx11
    UINT64_C(1912602624), UINT64_C(0),	// V_MAX_F16V_MAX_F16_fake16_e32_gfx11
    UINT64_C(3577282560), UINT64_C(0),	// V_MAX_F16V_MAX_F16_fake16_e64_dpp8_gfx11
    UINT64_C(1077319106560), UINT64_C(0),	// V_MAX_F16V_MAX_F16_fake16_e64_dpp_gfx11
    UINT64_C(3577282560), UINT64_C(0),	// V_MAX_F16V_MAX_F16_fake16_e64_gfx11
    UINT64_C(1912602624), UINT64_C(0),	// V_MAX_F16V_MAX_F16_t16_dpp8_gfx11
    UINT64_C(1912602874), UINT64_C(0),	// V_MAX_F16V_MAX_F16_t16_dpp_gfx11
    UINT64_C(1912602624), UINT64_C(0),	// V_MAX_F16V_MAX_F16_t16_e32_gfx11
    UINT64_C(3577282560), UINT64_C(0),	// V_MAX_F16V_MAX_F16_t16_e64_dpp8_gfx11
    UINT64_C(1077319106560), UINT64_C(0),	// V_MAX_F16V_MAX_F16_t16_e64_dpp_gfx11
    UINT64_C(3577282560), UINT64_C(0),	// V_MAX_F16V_MAX_F16_t16_e64_gfx11
    UINT64_C(1912602624), UINT64_C(0),	// V_MAX_F16_dpp8_gfx10
    UINT64_C(1912602874), UINT64_C(0),	// V_MAX_F16_dpp_gfx10
    UINT64_C(1509949690), UINT64_C(0),	// V_MAX_F16_dpp_vi
    UINT64_C(1912602624), UINT64_C(0),	// V_MAX_F16_e32_gfx10
    UINT64_C(1509949440), UINT64_C(0),	// V_MAX_F16_e32_vi
    UINT64_C(3577282560), UINT64_C(0),	// V_MAX_F16_e64_gfx10
    UINT64_C(3509387264), UINT64_C(0),	// V_MAX_F16_e64_vi
    UINT64_C(1912602873), UINT64_C(0),	// V_MAX_F16_sdwa_gfx10
    UINT64_C(1509949689), UINT64_C(0),	// V_MAX_F16_sdwa_gfx9
    UINT64_C(1509949689), UINT64_C(0),	// V_MAX_F16_sdwa_vi
    UINT64_C(536870912), UINT64_C(0),	// V_MAX_F32_dpp8_gfx10
    UINT64_C(536870912), UINT64_C(0),	// V_MAX_F32_dpp8_gfx11
    UINT64_C(536871162), UINT64_C(0),	// V_MAX_F32_dpp_gfx10
    UINT64_C(536871162), UINT64_C(0),	// V_MAX_F32_dpp_gfx11
    UINT64_C(369099002), UINT64_C(0),	// V_MAX_F32_dpp_vi
    UINT64_C(536870912), UINT64_C(0),	// V_MAX_F32_e32_gfx10
    UINT64_C(536870912), UINT64_C(0),	// V_MAX_F32_e32_gfx11
    UINT64_C(536870912), UINT64_C(0),	// V_MAX_F32_e32_gfx6_gfx7
    UINT64_C(369098752), UINT64_C(0),	// V_MAX_F32_e32_vi
    UINT64_C(3574595584), UINT64_C(0),	// V_MAX_F32_e64_dpp8_gfx11
    UINT64_C(1077316419584), UINT64_C(0),	// V_MAX_F32_e64_dpp_gfx11
    UINT64_C(3574595584), UINT64_C(0),	// V_MAX_F32_e64_gfx10
    UINT64_C(3574595584), UINT64_C(0),	// V_MAX_F32_e64_gfx11
    UINT64_C(3525312512), UINT64_C(0),	// V_MAX_F32_e64_gfx6_gfx7
    UINT64_C(3507159040), UINT64_C(0),	// V_MAX_F32_e64_vi
    UINT64_C(536871161), UINT64_C(0),	// V_MAX_F32_sdwa_gfx10
    UINT64_C(369099001), UINT64_C(0),	// V_MAX_F32_sdwa_gfx9
    UINT64_C(369099001), UINT64_C(0),	// V_MAX_F32_sdwa_vi
    UINT64_C(3609853952), UINT64_C(0),	// V_MAX_F64_e64_gfx11
    UINT64_C(3580297216), UINT64_C(0),	// V_MAX_F64_gfx10
    UINT64_C(3536715776), UINT64_C(0),	// V_MAX_F64_gfx6_gfx7
    UINT64_C(3531800576), UINT64_C(0),	// V_MAX_F64_vi
    UINT64_C(1610612986), UINT64_C(0),	// V_MAX_I16_dpp_vi
    UINT64_C(1610612736), UINT64_C(0),	// V_MAX_I16_e32_vi
    UINT64_C(3509583872), UINT64_C(0),	// V_MAX_I16_e64_vi
    UINT64_C(3607756800), UINT64_C(0),	// V_MAX_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3607756800), UINT64_C(0),	// V_MAX_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077349580800), UINT64_C(0),	// V_MAX_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077349580800), UINT64_C(0),	// V_MAX_I16_fake16_e64_dpp_gfx12
    UINT64_C(3607756800), UINT64_C(0),	// V_MAX_I16_fake16_e64_gfx11
    UINT64_C(3607756800), UINT64_C(0),	// V_MAX_I16_fake16_e64_gfx12
    UINT64_C(3607756800), UINT64_C(0),	// V_MAX_I16_gfx10
    UINT64_C(1610612985), UINT64_C(0),	// V_MAX_I16_sdwa_gfx9
    UINT64_C(1610612985), UINT64_C(0),	// V_MAX_I16_sdwa_vi
    UINT64_C(3607756800), UINT64_C(0),	// V_MAX_I16_t16_e64_dpp8_gfx11
    UINT64_C(3607756800), UINT64_C(0),	// V_MAX_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077349580800), UINT64_C(0),	// V_MAX_I16_t16_e64_dpp_gfx11
    UINT64_C(1077349580800), UINT64_C(0),	// V_MAX_I16_t16_e64_dpp_gfx12
    UINT64_C(3607756800), UINT64_C(0),	// V_MAX_I16_t16_e64_gfx11
    UINT64_C(3607756800), UINT64_C(0),	// V_MAX_I16_t16_e64_gfx12
    UINT64_C(603979776), UINT64_C(0),	// V_MAX_I32_dpp8_gfx10
    UINT64_C(603979776), UINT64_C(0),	// V_MAX_I32_dpp8_gfx11
    UINT64_C(603979776), UINT64_C(0),	// V_MAX_I32_dpp8_gfx12
    UINT64_C(603980026), UINT64_C(0),	// V_MAX_I32_dpp_gfx10
    UINT64_C(603980026), UINT64_C(0),	// V_MAX_I32_dpp_gfx11
    UINT64_C(603980026), UINT64_C(0),	// V_MAX_I32_dpp_gfx12
    UINT64_C(436207866), UINT64_C(0),	// V_MAX_I32_dpp_vi
    UINT64_C(603979776), UINT64_C(0),	// V_MAX_I32_e32_gfx10
    UINT64_C(603979776), UINT64_C(0),	// V_MAX_I32_e32_gfx11
    UINT64_C(603979776), UINT64_C(0),	// V_MAX_I32_e32_gfx12
    UINT64_C(603979776), UINT64_C(0),	// V_MAX_I32_e32_gfx6_gfx7
    UINT64_C(436207616), UINT64_C(0),	// V_MAX_I32_e32_vi
    UINT64_C(3574726656), UINT64_C(0),	// V_MAX_I32_e64_dpp8_gfx11
    UINT64_C(3574726656), UINT64_C(0),	// V_MAX_I32_e64_dpp8_gfx12
    UINT64_C(1077316550656), UINT64_C(0),	// V_MAX_I32_e64_dpp_gfx11
    UINT64_C(1077316550656), UINT64_C(0),	// V_MAX_I32_e64_dpp_gfx12
    UINT64_C(3574726656), UINT64_C(0),	// V_MAX_I32_e64_gfx10
    UINT64_C(3574726656), UINT64_C(0),	// V_MAX_I32_e64_gfx11
    UINT64_C(3574726656), UINT64_C(0),	// V_MAX_I32_e64_gfx12
    UINT64_C(3525574656), UINT64_C(0),	// V_MAX_I32_e64_gfx6_gfx7
    UINT64_C(3507290112), UINT64_C(0),	// V_MAX_I32_e64_vi
    UINT64_C(603980025), UINT64_C(0),	// V_MAX_I32_sdwa_gfx10
    UINT64_C(436207865), UINT64_C(0),	// V_MAX_I32_sdwa_gfx9
    UINT64_C(436207865), UINT64_C(0),	// V_MAX_I32_sdwa_vi
    UINT64_C(1077350694912), UINT64_C(0),	// V_MAX_I64_e64_dpp_gfx1250
    UINT64_C(3608870912), UINT64_C(0),	// V_MAX_I64_e64_gfx1250
    UINT64_C(469762048), UINT64_C(0),	// V_MAX_LEGACY_F32_e32_gfx6_gfx7
    UINT64_C(3525050368), UINT64_C(0),	// V_MAX_LEGACY_F32_e64_gfx6_gfx7
    UINT64_C(1644167168), UINT64_C(0),	// V_MAX_NUM_F16_fake16_dpp8_gfx12
    UINT64_C(1644167418), UINT64_C(0),	// V_MAX_NUM_F16_fake16_dpp_gfx12
    UINT64_C(1644167168), UINT64_C(0),	// V_MAX_NUM_F16_fake16_e32_gfx12
    UINT64_C(3576758272), UINT64_C(0),	// V_MAX_NUM_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077318582272), UINT64_C(0),	// V_MAX_NUM_F16_fake16_e64_dpp_gfx12
    UINT64_C(3576758272), UINT64_C(0),	// V_MAX_NUM_F16_fake16_e64_gfx12
    UINT64_C(1644167168), UINT64_C(0),	// V_MAX_NUM_F16_t16_dpp8_gfx12
    UINT64_C(1644167418), UINT64_C(0),	// V_MAX_NUM_F16_t16_dpp_gfx12
    UINT64_C(1644167168), UINT64_C(0),	// V_MAX_NUM_F16_t16_e32_gfx12
    UINT64_C(3576758272), UINT64_C(0),	// V_MAX_NUM_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077318582272), UINT64_C(0),	// V_MAX_NUM_F16_t16_e64_dpp_gfx12
    UINT64_C(3576758272), UINT64_C(0),	// V_MAX_NUM_F16_t16_e64_gfx12
    UINT64_C(738197504), UINT64_C(0),	// V_MAX_NUM_F32_dpp8_gfx12
    UINT64_C(738197754), UINT64_C(0),	// V_MAX_NUM_F32_dpp_gfx12
    UINT64_C(738197504), UINT64_C(0),	// V_MAX_NUM_F32_e32_gfx12
    UINT64_C(3574988800), UINT64_C(0),	// V_MAX_NUM_F32_e64_dpp8_gfx12
    UINT64_C(1077316812800), UINT64_C(0),	// V_MAX_NUM_F32_e64_dpp_gfx12
    UINT64_C(3574988800), UINT64_C(0),	// V_MAX_NUM_F32_e64_gfx12
    UINT64_C(469762298), UINT64_C(0),	// V_MAX_NUM_F64_dpp_gfx12
    UINT64_C(469762048), UINT64_C(0),	// V_MAX_NUM_F64_e32_gfx12
    UINT64_C(1077316288512), UINT64_C(0),	// V_MAX_NUM_F64_e64_dpp_gfx12
    UINT64_C(3574464512), UINT64_C(0),	// V_MAX_NUM_F64_e64_gfx12
    UINT64_C(1577058554), UINT64_C(0),	// V_MAX_U16_dpp_vi
    UINT64_C(1577058304), UINT64_C(0),	// V_MAX_U16_e32_vi
    UINT64_C(3509518336), UINT64_C(0),	// V_MAX_U16_e64_vi
    UINT64_C(3607691264), UINT64_C(0),	// V_MAX_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3607691264), UINT64_C(0),	// V_MAX_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077349515264), UINT64_C(0),	// V_MAX_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077349515264), UINT64_C(0),	// V_MAX_U16_fake16_e64_dpp_gfx12
    UINT64_C(3607691264), UINT64_C(0),	// V_MAX_U16_fake16_e64_gfx11
    UINT64_C(3607691264), UINT64_C(0),	// V_MAX_U16_fake16_e64_gfx12
    UINT64_C(3607691264), UINT64_C(0),	// V_MAX_U16_gfx10
    UINT64_C(1577058553), UINT64_C(0),	// V_MAX_U16_sdwa_gfx9
    UINT64_C(1577058553), UINT64_C(0),	// V_MAX_U16_sdwa_vi
    UINT64_C(3607691264), UINT64_C(0),	// V_MAX_U16_t16_e64_dpp8_gfx11
    UINT64_C(3607691264), UINT64_C(0),	// V_MAX_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077349515264), UINT64_C(0),	// V_MAX_U16_t16_e64_dpp_gfx11
    UINT64_C(1077349515264), UINT64_C(0),	// V_MAX_U16_t16_e64_dpp_gfx12
    UINT64_C(3607691264), UINT64_C(0),	// V_MAX_U16_t16_e64_gfx11
    UINT64_C(3607691264), UINT64_C(0),	// V_MAX_U16_t16_e64_gfx12
    UINT64_C(671088640), UINT64_C(0),	// V_MAX_U32_dpp8_gfx10
    UINT64_C(671088640), UINT64_C(0),	// V_MAX_U32_dpp8_gfx11
    UINT64_C(671088640), UINT64_C(0),	// V_MAX_U32_dpp8_gfx12
    UINT64_C(671088890), UINT64_C(0),	// V_MAX_U32_dpp_gfx10
    UINT64_C(671088890), UINT64_C(0),	// V_MAX_U32_dpp_gfx11
    UINT64_C(671088890), UINT64_C(0),	// V_MAX_U32_dpp_gfx12
    UINT64_C(503316730), UINT64_C(0),	// V_MAX_U32_dpp_vi
    UINT64_C(671088640), UINT64_C(0),	// V_MAX_U32_e32_gfx10
    UINT64_C(671088640), UINT64_C(0),	// V_MAX_U32_e32_gfx11
    UINT64_C(671088640), UINT64_C(0),	// V_MAX_U32_e32_gfx12
    UINT64_C(671088640), UINT64_C(0),	// V_MAX_U32_e32_gfx6_gfx7
    UINT64_C(503316480), UINT64_C(0),	// V_MAX_U32_e32_vi
    UINT64_C(3574857728), UINT64_C(0),	// V_MAX_U32_e64_dpp8_gfx11
    UINT64_C(3574857728), UINT64_C(0),	// V_MAX_U32_e64_dpp8_gfx12
    UINT64_C(1077316681728), UINT64_C(0),	// V_MAX_U32_e64_dpp_gfx11
    UINT64_C(1077316681728), UINT64_C(0),	// V_MAX_U32_e64_dpp_gfx12
    UINT64_C(3574857728), UINT64_C(0),	// V_MAX_U32_e64_gfx10
    UINT64_C(3574857728), UINT64_C(0),	// V_MAX_U32_e64_gfx11
    UINT64_C(3574857728), UINT64_C(0),	// V_MAX_U32_e64_gfx12
    UINT64_C(3525836800), UINT64_C(0),	// V_MAX_U32_e64_gfx6_gfx7
    UINT64_C(3507421184), UINT64_C(0),	// V_MAX_U32_e64_vi
    UINT64_C(671088889), UINT64_C(0),	// V_MAX_U32_sdwa_gfx10
    UINT64_C(503316729), UINT64_C(0),	// V_MAX_U32_sdwa_gfx9
    UINT64_C(503316729), UINT64_C(0),	// V_MAX_U32_sdwa_vi
    UINT64_C(1077350563840), UINT64_C(0),	// V_MAX_U64_e64_dpp_gfx1250
    UINT64_C(3608739840), UINT64_C(0),	// V_MAX_U64_e64_gfx1250
    UINT64_C(1207959552), UINT64_C(0),	// V_MBCNT_HI_U32_B32_e32_gfx6_gfx7
    UINT64_C(3609198592), UINT64_C(0),	// V_MBCNT_HI_U32_B32_e64_dpp8_gfx11
    UINT64_C(3609198592), UINT64_C(0),	// V_MBCNT_HI_U32_B32_e64_dpp8_gfx12
    UINT64_C(1077351022592), UINT64_C(0),	// V_MBCNT_HI_U32_B32_e64_dpp_gfx11
    UINT64_C(1077351022592), UINT64_C(0),	// V_MBCNT_HI_U32_B32_e64_dpp_gfx12
    UINT64_C(3613786112), UINT64_C(0),	// V_MBCNT_HI_U32_B32_e64_gfx10
    UINT64_C(3609198592), UINT64_C(0),	// V_MBCNT_HI_U32_B32_e64_gfx11
    UINT64_C(3609198592), UINT64_C(0),	// V_MBCNT_HI_U32_B32_e64_gfx12
    UINT64_C(3527933952), UINT64_C(0),	// V_MBCNT_HI_U32_B32_e64_gfx6_gfx7
    UINT64_C(3532455936), UINT64_C(0),	// V_MBCNT_HI_U32_B32_e64_vi
    UINT64_C(1174405120), UINT64_C(0),	// V_MBCNT_LO_U32_B32_e32_gfx6_gfx7
    UINT64_C(3609133056), UINT64_C(0),	// V_MBCNT_LO_U32_B32_e64_dpp8_gfx11
    UINT64_C(3609133056), UINT64_C(0),	// V_MBCNT_LO_U32_B32_e64_dpp8_gfx12
    UINT64_C(1077350957056), UINT64_C(0),	// V_MBCNT_LO_U32_B32_e64_dpp_gfx11
    UINT64_C(1077350957056), UINT64_C(0),	// V_MBCNT_LO_U32_B32_e64_dpp_gfx12
    UINT64_C(3613720576), UINT64_C(0),	// V_MBCNT_LO_U32_B32_e64_gfx10
    UINT64_C(3609133056), UINT64_C(0),	// V_MBCNT_LO_U32_B32_e64_gfx11
    UINT64_C(3609133056), UINT64_C(0),	// V_MBCNT_LO_U32_B32_e64_gfx12
    UINT64_C(3527802880), UINT64_C(0),	// V_MBCNT_LO_U32_B32_e64_gfx6_gfx7
    UINT64_C(3532390400), UINT64_C(0),	// V_MBCNT_LO_U32_B32_e64_vi
    UINT64_C(3595501568), UINT64_C(0),	// V_MED3_F16_fake16_e64_dpp8_gfx11
    UINT64_C(1077337325568), UINT64_C(0),	// V_MED3_F16_fake16_e64_dpp_gfx11
    UINT64_C(3595501568), UINT64_C(0),	// V_MED3_F16_fake16_e64_gfx11
    UINT64_C(3612803072), UINT64_C(0),	// V_MED3_F16_gfx10
    UINT64_C(3595501568), UINT64_C(0),	// V_MED3_F16_t16_e64_dpp8_gfx11
    UINT64_C(1077337325568), UINT64_C(0),	// V_MED3_F16_t16_e64_dpp_gfx11
    UINT64_C(3595501568), UINT64_C(0),	// V_MED3_F16_t16_e64_gfx11
    UINT64_C(3522822144), UINT64_C(0),	// V_MED3_F16_vi
    UINT64_C(3592355840), UINT64_C(0),	// V_MED3_F32_e64_dpp8_gfx11
    UINT64_C(1077334179840), UINT64_C(0),	// V_MED3_F32_e64_dpp_gfx11
    UINT64_C(3592355840), UINT64_C(0),	// V_MED3_F32_e64_gfx11
    UINT64_C(3579248640), UINT64_C(0),	// V_MED3_F32_gfx10
    UINT64_C(3534618624), UINT64_C(0),	// V_MED3_F32_gfx6_gfx7
    UINT64_C(3520462848), UINT64_C(0),	// V_MED3_F32_vi
    UINT64_C(3595567104), UINT64_C(0),	// V_MED3_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3595567104), UINT64_C(0),	// V_MED3_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077337391104), UINT64_C(0),	// V_MED3_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077337391104), UINT64_C(0),	// V_MED3_I16_fake16_e64_dpp_gfx12
    UINT64_C(3595567104), UINT64_C(0),	// V_MED3_I16_fake16_e64_gfx11
    UINT64_C(3595567104), UINT64_C(0),	// V_MED3_I16_fake16_e64_gfx12
    UINT64_C(3612868608), UINT64_C(0),	// V_MED3_I16_gfx10
    UINT64_C(3595567104), UINT64_C(0),	// V_MED3_I16_t16_e64_dpp8_gfx11
    UINT64_C(3595567104), UINT64_C(0),	// V_MED3_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077337391104), UINT64_C(0),	// V_MED3_I16_t16_e64_dpp_gfx11
    UINT64_C(1077337391104), UINT64_C(0),	// V_MED3_I16_t16_e64_dpp_gfx12
    UINT64_C(3595567104), UINT64_C(0),	// V_MED3_I16_t16_e64_gfx11
    UINT64_C(3595567104), UINT64_C(0),	// V_MED3_I16_t16_e64_gfx12
    UINT64_C(3522887680), UINT64_C(0),	// V_MED3_I16_vi
    UINT64_C(3592421376), UINT64_C(0),	// V_MED3_I32_e64_dpp8_gfx11
    UINT64_C(3592421376), UINT64_C(0),	// V_MED3_I32_e64_dpp8_gfx12
    UINT64_C(1077334245376), UINT64_C(0),	// V_MED3_I32_e64_dpp_gfx11
    UINT64_C(1077334245376), UINT64_C(0),	// V_MED3_I32_e64_dpp_gfx12
    UINT64_C(3592421376), UINT64_C(0),	// V_MED3_I32_e64_gfx11
    UINT64_C(3592421376), UINT64_C(0),	// V_MED3_I32_e64_gfx12
    UINT64_C(3579314176), UINT64_C(0),	// V_MED3_I32_gfx10
    UINT64_C(3534749696), UINT64_C(0),	// V_MED3_I32_gfx6_gfx7
    UINT64_C(3520528384), UINT64_C(0),	// V_MED3_I32_vi
    UINT64_C(3593601024), UINT64_C(0),	// V_MED3_NUM_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077335425024), UINT64_C(0),	// V_MED3_NUM_F16_fake16_e64_dpp_gfx12
    UINT64_C(3593601024), UINT64_C(0),	// V_MED3_NUM_F16_fake16_e64_gfx12
    UINT64_C(3593601024), UINT64_C(0),	// V_MED3_NUM_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077335425024), UINT64_C(0),	// V_MED3_NUM_F16_t16_e64_dpp_gfx12
    UINT64_C(3593601024), UINT64_C(0),	// V_MED3_NUM_F16_t16_e64_gfx12
    UINT64_C(3593535488), UINT64_C(0),	// V_MED3_NUM_F32_e64_dpp8_gfx12
    UINT64_C(1077335359488), UINT64_C(0),	// V_MED3_NUM_F32_e64_dpp_gfx12
    UINT64_C(3593535488), UINT64_C(0),	// V_MED3_NUM_F32_e64_gfx12
    UINT64_C(3595632640), UINT64_C(0),	// V_MED3_U16V_MED3_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3595632640), UINT64_C(0),	// V_MED3_U16V_MED3_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077337456640), UINT64_C(0),	// V_MED3_U16V_MED3_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077337456640), UINT64_C(0),	// V_MED3_U16V_MED3_U16_fake16_e64_dpp_gfx12
    UINT64_C(3595632640), UINT64_C(0),	// V_MED3_U16V_MED3_U16_fake16_e64_gfx11
    UINT64_C(3595632640), UINT64_C(0),	// V_MED3_U16V_MED3_U16_fake16_e64_gfx12
    UINT64_C(3595632640), UINT64_C(0),	// V_MED3_U16V_MED3_U16_t16_e64_dpp8_gfx11
    UINT64_C(3595632640), UINT64_C(0),	// V_MED3_U16V_MED3_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077337456640), UINT64_C(0),	// V_MED3_U16V_MED3_U16_t16_e64_dpp_gfx11
    UINT64_C(1077337456640), UINT64_C(0),	// V_MED3_U16V_MED3_U16_t16_e64_dpp_gfx12
    UINT64_C(3595632640), UINT64_C(0),	// V_MED3_U16V_MED3_U16_t16_e64_gfx11
    UINT64_C(3595632640), UINT64_C(0),	// V_MED3_U16V_MED3_U16_t16_e64_gfx12
    UINT64_C(3612934144), UINT64_C(0),	// V_MED3_U16_gfx10
    UINT64_C(3522953216), UINT64_C(0),	// V_MED3_U16_vi
    UINT64_C(3592486912), UINT64_C(0),	// V_MED3_U32_e64_dpp8_gfx11
    UINT64_C(3592486912), UINT64_C(0),	// V_MED3_U32_e64_dpp8_gfx12
    UINT64_C(1077334310912), UINT64_C(0),	// V_MED3_U32_e64_dpp_gfx11
    UINT64_C(1077334310912), UINT64_C(0),	// V_MED3_U32_e64_dpp_gfx12
    UINT64_C(3592486912), UINT64_C(0),	// V_MED3_U32_e64_gfx11
    UINT64_C(3592486912), UINT64_C(0),	// V_MED3_U32_e64_gfx12
    UINT64_C(3579379712), UINT64_C(0),	// V_MED3_U32_gfx10
    UINT64_C(3534880768), UINT64_C(0),	// V_MED3_U32_gfx6_gfx7
    UINT64_C(3520593920), UINT64_C(0),	// V_MED3_U32_vi
    UINT64_C(3551363072), UINT64_C(0),	// V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd
    UINT64_C(3551330304), UINT64_C(0),	// V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd
    UINT64_C(3551363072), UINT64_C(0),	// V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd
    UINT64_C(3551330304), UINT64_C(0),	// V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd
    UINT64_C(3551363072), UINT64_C(0),	// V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd
    UINT64_C(3551330304), UINT64_C(0),	// V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd
    UINT64_C(3551363072), UINT64_C(0),	// V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd
    UINT64_C(3551330304), UINT64_C(0),	// V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd
    UINT64_C(3551363072), UINT64_C(0),	// V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd
    UINT64_C(3551330304), UINT64_C(0),	// V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd
    UINT64_C(3551363072), UINT64_C(0),	// V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd
    UINT64_C(3551330304), UINT64_C(0),	// V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd
    UINT64_C(3551363072), UINT64_C(0),	// V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd
    UINT64_C(3551330304), UINT64_C(0),	// V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd
    UINT64_C(3551363072), UINT64_C(0),	// V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd
    UINT64_C(3551330304), UINT64_C(0),	// V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd
    UINT64_C(3551363072), UINT64_C(0),	// V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd
    UINT64_C(3551330304), UINT64_C(0),	// V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd
    UINT64_C(3555164160), UINT64_C(0),	// V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd
    UINT64_C(3555131392), UINT64_C(0),	// V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd
    UINT64_C(3554770944), UINT64_C(0),	// V_MFMA_F32_16X16X16BF16_1K_gfx940_acd
    UINT64_C(3554738176), UINT64_C(0),	// V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd
    UINT64_C(3553460224), UINT64_C(0),	// V_MFMA_F32_16X16X16F16_gfx90a_acd
    UINT64_C(3553427456), UINT64_C(0),	// V_MFMA_F32_16X16X16F16_gfx90a_vcd
    UINT64_C(3553460224), UINT64_C(0),	// V_MFMA_F32_16X16X16F16_gfx940_acd
    UINT64_C(3553427456), UINT64_C(0),	// V_MFMA_F32_16X16X16F16_gfx940_vcd
    UINT64_C(3553427456), UINT64_C(0),	// V_MFMA_F32_16X16X16F16_vi
    UINT64_C(3552673792), UINT64_C(0),	// V_MFMA_F32_16X16X1F32_gfx90a_acd
    UINT64_C(3552641024), UINT64_C(0),	// V_MFMA_F32_16X16X1F32_gfx90a_vcd
    UINT64_C(3552673792), UINT64_C(0),	// V_MFMA_F32_16X16X1F32_gfx940_acd
    UINT64_C(3552641024), UINT64_C(0),	// V_MFMA_F32_16X16X1F32_gfx940_vcd
    UINT64_C(3552641024), UINT64_C(0),	// V_MFMA_F32_16X16X1F32_vi
    UINT64_C(3555295232), UINT64_C(0),	// V_MFMA_F32_16X16X2BF16_gfx90a_acd
    UINT64_C(3555262464), UINT64_C(0),	// V_MFMA_F32_16X16X2BF16_gfx90a_vcd
    UINT64_C(3555262464), UINT64_C(0),	// V_MFMA_F32_16X16X2BF16_vi
    UINT64_C(3551887360), UINT64_C(0),	// V_MFMA_F32_16X16X32_BF16_gfx940_acd
    UINT64_C(3551854592), UINT64_C(0),	// V_MFMA_F32_16X16X32_BF16_gfx940_vcd
    UINT64_C(3555753984), UINT64_C(0),	// V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd
    UINT64_C(3555721216), UINT64_C(0),	// V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd
    UINT64_C(3555819520), UINT64_C(0),	// V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd
    UINT64_C(3555786752), UINT64_C(0),	// V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd
    UINT64_C(3553918976), UINT64_C(0),	// V_MFMA_F32_16X16X32_F16_gfx940_acd
    UINT64_C(3553886208), UINT64_C(0),	// V_MFMA_F32_16X16X32_F16_gfx940_vcd
    UINT64_C(3555885056), UINT64_C(0),	// V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd
    UINT64_C(3555852288), UINT64_C(0),	// V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd
    UINT64_C(3555950592), UINT64_C(0),	// V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd
    UINT64_C(3555917824), UINT64_C(0),	// V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd
    UINT64_C(3554967552), UINT64_C(0),	// V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd
    UINT64_C(3554934784), UINT64_C(0),	// V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd
    UINT64_C(3554574336), UINT64_C(0),	// V_MFMA_F32_16X16X4BF16_1K_gfx940_acd
    UINT64_C(3554541568), UINT64_C(0),	// V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd
    UINT64_C(3553198080), UINT64_C(0),	// V_MFMA_F32_16X16X4F16_gfx90a_acd
    UINT64_C(3553165312), UINT64_C(0),	// V_MFMA_F32_16X16X4F16_gfx90a_vcd
    UINT64_C(3553198080), UINT64_C(0),	// V_MFMA_F32_16X16X4F16_gfx940_acd
    UINT64_C(3553165312), UINT64_C(0),	// V_MFMA_F32_16X16X4F16_gfx940_vcd
    UINT64_C(3553165312), UINT64_C(0),	// V_MFMA_F32_16X16X4F16_vi
    UINT64_C(3552935936), UINT64_C(0),	// V_MFMA_F32_16X16X4F32_gfx90a_acd
    UINT64_C(3552903168), UINT64_C(0),	// V_MFMA_F32_16X16X4F32_gfx90a_vcd
    UINT64_C(3552935936), UINT64_C(0),	// V_MFMA_F32_16X16X4F32_gfx940_acd
    UINT64_C(3552903168), UINT64_C(0),	// V_MFMA_F32_16X16X4F32_gfx940_vcd
    UINT64_C(3552903168), UINT64_C(0),	// V_MFMA_F32_16X16X4F32_vi
    UINT64_C(3555557376), UINT64_C(0),	// V_MFMA_F32_16X16X8BF16_gfx90a_acd
    UINT64_C(3555524608), UINT64_C(0),	// V_MFMA_F32_16X16X8BF16_gfx90a_vcd
    UINT64_C(3555524608), UINT64_C(0),	// V_MFMA_F32_16X16X8BF16_vi
    UINT64_C(3552477184), UINT64_C(0),	// V_MFMA_F32_16X16X8XF32_gfx940_acd
    UINT64_C(3552444416), UINT64_C(0),	// V_MFMA_F32_16X16X8XF32_gfx940_vcd
    UINT64_C(3552018432), UINT64_C(0),	// V_MFMA_F32_32X32X16_BF16_gfx940_acd
    UINT64_C(3551985664), UINT64_C(0),	// V_MFMA_F32_32X32X16_BF16_gfx940_vcd
    UINT64_C(3556016128), UINT64_C(0),	// V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd
    UINT64_C(3555983360), UINT64_C(0),	// V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd
    UINT64_C(3556081664), UINT64_C(0),	// V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd
    UINT64_C(3556048896), UINT64_C(0),	// V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd
    UINT64_C(3553984512), UINT64_C(0),	// V_MFMA_F32_32X32X16_F16_gfx940_acd
    UINT64_C(3553951744), UINT64_C(0),	// V_MFMA_F32_32X32X16_F16_gfx940_vcd
    UINT64_C(3556147200), UINT64_C(0),	// V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd
    UINT64_C(3556114432), UINT64_C(0),	// V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd
    UINT64_C(3556212736), UINT64_C(0),	// V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd
    UINT64_C(3556179968), UINT64_C(0),	// V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd
    UINT64_C(3552608256), UINT64_C(0),	// V_MFMA_F32_32X32X1F32_gfx90a_acd
    UINT64_C(3552575488), UINT64_C(0),	// V_MFMA_F32_32X32X1F32_gfx90a_vcd
    UINT64_C(3552608256), UINT64_C(0),	// V_MFMA_F32_32X32X1F32_gfx940_acd
    UINT64_C(3552575488), UINT64_C(0),	// V_MFMA_F32_32X32X1F32_gfx940_vcd
    UINT64_C(3552575488), UINT64_C(0),	// V_MFMA_F32_32X32X1F32_vi
    UINT64_C(3555229696), UINT64_C(0),	// V_MFMA_F32_32X32X2BF16_gfx90a_acd
    UINT64_C(3555196928), UINT64_C(0),	// V_MFMA_F32_32X32X2BF16_gfx90a_vcd
    UINT64_C(3555196928), UINT64_C(0),	// V_MFMA_F32_32X32X2BF16_vi
    UINT64_C(3552870400), UINT64_C(0),	// V_MFMA_F32_32X32X2F32_gfx90a_acd
    UINT64_C(3552837632), UINT64_C(0),	// V_MFMA_F32_32X32X2F32_gfx90a_vcd
    UINT64_C(3552870400), UINT64_C(0),	// V_MFMA_F32_32X32X2F32_gfx940_acd
    UINT64_C(3552837632), UINT64_C(0),	// V_MFMA_F32_32X32X2F32_gfx940_vcd
    UINT64_C(3552837632), UINT64_C(0),	// V_MFMA_F32_32X32X2F32_vi
    UINT64_C(3554902016), UINT64_C(0),	// V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd
    UINT64_C(3554869248), UINT64_C(0),	// V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd
    UINT64_C(3554508800), UINT64_C(0),	// V_MFMA_F32_32X32X4BF16_1K_gfx940_acd
    UINT64_C(3554476032), UINT64_C(0),	// V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd
    UINT64_C(3555491840), UINT64_C(0),	// V_MFMA_F32_32X32X4BF16_gfx90a_acd
    UINT64_C(3555459072), UINT64_C(0),	// V_MFMA_F32_32X32X4BF16_gfx90a_vcd
    UINT64_C(3555459072), UINT64_C(0),	// V_MFMA_F32_32X32X4BF16_vi
    UINT64_C(3553132544), UINT64_C(0),	// V_MFMA_F32_32X32X4F16_gfx90a_acd
    UINT64_C(3553099776), UINT64_C(0),	// V_MFMA_F32_32X32X4F16_gfx90a_vcd
    UINT64_C(3553132544), UINT64_C(0),	// V_MFMA_F32_32X32X4F16_gfx940_acd
    UINT64_C(3553099776), UINT64_C(0),	// V_MFMA_F32_32X32X4F16_gfx940_vcd
    UINT64_C(3553099776), UINT64_C(0),	// V_MFMA_F32_32X32X4F16_vi
    UINT64_C(3552542720), UINT64_C(0),	// V_MFMA_F32_32X32X4XF32_gfx940_acd
    UINT64_C(3552509952), UINT64_C(0),	// V_MFMA_F32_32X32X4XF32_gfx940_vcd
    UINT64_C(3551428608), UINT64_C(0),	// V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd
    UINT64_C(3551395840), UINT64_C(0),	// V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd
    UINT64_C(3551428608), UINT64_C(0),	// V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd
    UINT64_C(3551395840), UINT64_C(0),	// V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd
    UINT64_C(3551428608), UINT64_C(0),	// V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd
    UINT64_C(3551395840), UINT64_C(0),	// V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd
    UINT64_C(3551428608), UINT64_C(0),	// V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd
    UINT64_C(3551395840), UINT64_C(0),	// V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd
    UINT64_C(3551428608), UINT64_C(0),	// V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd
    UINT64_C(3551395840), UINT64_C(0),	// V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd
    UINT64_C(3551428608), UINT64_C(0),	// V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd
    UINT64_C(3551395840), UINT64_C(0),	// V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd
    UINT64_C(3551428608), UINT64_C(0),	// V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd
    UINT64_C(3551395840), UINT64_C(0),	// V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd
    UINT64_C(3551428608), UINT64_C(0),	// V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd
    UINT64_C(3551395840), UINT64_C(0),	// V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd
    UINT64_C(3551428608), UINT64_C(0),	// V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd
    UINT64_C(3551395840), UINT64_C(0),	// V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd
    UINT64_C(3555098624), UINT64_C(0),	// V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd
    UINT64_C(3555065856), UINT64_C(0),	// V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd
    UINT64_C(3554705408), UINT64_C(0),	// V_MFMA_F32_32X32X8BF16_1K_gfx940_acd
    UINT64_C(3554672640), UINT64_C(0),	// V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd
    UINT64_C(3553394688), UINT64_C(0),	// V_MFMA_F32_32X32X8F16_gfx90a_acd
    UINT64_C(3553361920), UINT64_C(0),	// V_MFMA_F32_32X32X8F16_gfx90a_vcd
    UINT64_C(3553394688), UINT64_C(0),	// V_MFMA_F32_32X32X8F16_gfx940_acd
    UINT64_C(3553361920), UINT64_C(0),	// V_MFMA_F32_32X32X8F16_gfx940_vcd
    UINT64_C(3553361920), UINT64_C(0),	// V_MFMA_F32_32X32X8F16_vi
    UINT64_C(3552739328), UINT64_C(0),	// V_MFMA_F32_4X4X1F32_gfx90a_acd
    UINT64_C(3552706560), UINT64_C(0),	// V_MFMA_F32_4X4X1F32_gfx90a_vcd
    UINT64_C(3552739328), UINT64_C(0),	// V_MFMA_F32_4X4X1F32_gfx940_acd
    UINT64_C(3552706560), UINT64_C(0),	// V_MFMA_F32_4X4X1F32_gfx940_vcd
    UINT64_C(3552706560), UINT64_C(0),	// V_MFMA_F32_4X4X1F32_vi
    UINT64_C(3555426304), UINT64_C(0),	// V_MFMA_F32_4X4X2BF16_gfx90a_acd
    UINT64_C(3555393536), UINT64_C(0),	// V_MFMA_F32_4X4X2BF16_gfx90a_vcd
    UINT64_C(3555393536), UINT64_C(0),	// V_MFMA_F32_4X4X2BF16_vi
    UINT64_C(3555033088), UINT64_C(0),	// V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd
    UINT64_C(3555000320), UINT64_C(0),	// V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd
    UINT64_C(3554639872), UINT64_C(0),	// V_MFMA_F32_4X4X4BF16_1K_gfx940_acd
    UINT64_C(3554607104), UINT64_C(0),	// V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd
    UINT64_C(3553263616), UINT64_C(0),	// V_MFMA_F32_4X4X4F16_gfx90a_acd
    UINT64_C(3553230848), UINT64_C(0),	// V_MFMA_F32_4X4X4F16_gfx90a_vcd
    UINT64_C(3553263616), UINT64_C(0),	// V_MFMA_F32_4X4X4F16_gfx940_acd
    UINT64_C(3553230848), UINT64_C(0),	// V_MFMA_F32_4X4X4F16_gfx940_vcd
    UINT64_C(3553230848), UINT64_C(0),	// V_MFMA_F32_4X4X4F16_vi
    UINT64_C(3555622912), UINT64_C(0),	// V_MFMA_F64_16X16X4F64_gfx90a_acd
    UINT64_C(3555590144), UINT64_C(0),	// V_MFMA_F64_16X16X4F64_gfx90a_vcd
    UINT64_C(3555622912), UINT64_C(0),	// V_MFMA_F64_16X16X4F64_gfx940_acd
    UINT64_C(3555590144), UINT64_C(0),	// V_MFMA_F64_16X16X4F64_gfx940_vcd
    UINT64_C(3555688448), UINT64_C(0),	// V_MFMA_F64_4X4X4F64_gfx90a_acd
    UINT64_C(3555655680), UINT64_C(0),	// V_MFMA_F64_4X4X4F64_gfx90a_vcd
    UINT64_C(3555688448), UINT64_C(0),	// V_MFMA_F64_4X4X4F64_gfx940_acd
    UINT64_C(3555655680), UINT64_C(0),	// V_MFMA_F64_4X4X4F64_gfx940_vcd
    UINT64_C(3553984512), UINT64_C(0),	// V_MFMA_I32_16X16X16I8_gfx90a_acd
    UINT64_C(3553951744), UINT64_C(0),	// V_MFMA_I32_16X16X16I8_gfx90a_vcd
    UINT64_C(3553951744), UINT64_C(0),	// V_MFMA_I32_16X16X16I8_vi
    UINT64_C(3554115584), UINT64_C(0),	// V_MFMA_I32_16X16X32I8_gfx940_acd
    UINT64_C(3554082816), UINT64_C(0),	// V_MFMA_I32_16X16X32I8_gfx940_vcd
    UINT64_C(3553722368), UINT64_C(0),	// V_MFMA_I32_16X16X4I8_gfx90a_acd
    UINT64_C(3553689600), UINT64_C(0),	// V_MFMA_I32_16X16X4I8_gfx90a_vcd
    UINT64_C(3553722368), UINT64_C(0),	// V_MFMA_I32_16X16X4I8_gfx940_acd
    UINT64_C(3553689600), UINT64_C(0),	// V_MFMA_I32_16X16X4I8_gfx940_vcd
    UINT64_C(3553689600), UINT64_C(0),	// V_MFMA_I32_16X16X4I8_vi
    UINT64_C(3551952896), UINT64_C(0),	// V_MFMA_I32_16X16X64_I8_gfx940_acd
    UINT64_C(3551920128), UINT64_C(0),	// V_MFMA_I32_16X16X64_I8_gfx940_vcd
    UINT64_C(3554050048), UINT64_C(0),	// V_MFMA_I32_32X32X16I8_gfx940_acd
    UINT64_C(3554017280), UINT64_C(0),	// V_MFMA_I32_32X32X16I8_gfx940_vcd
    UINT64_C(3552083968), UINT64_C(0),	// V_MFMA_I32_32X32X32_I8_gfx940_acd
    UINT64_C(3552051200), UINT64_C(0),	// V_MFMA_I32_32X32X32_I8_gfx940_vcd
    UINT64_C(3553656832), UINT64_C(0),	// V_MFMA_I32_32X32X4I8_gfx90a_acd
    UINT64_C(3553624064), UINT64_C(0),	// V_MFMA_I32_32X32X4I8_gfx90a_vcd
    UINT64_C(3553656832), UINT64_C(0),	// V_MFMA_I32_32X32X4I8_gfx940_acd
    UINT64_C(3553624064), UINT64_C(0),	// V_MFMA_I32_32X32X4I8_gfx940_vcd
    UINT64_C(3553624064), UINT64_C(0),	// V_MFMA_I32_32X32X4I8_vi
    UINT64_C(3553918976), UINT64_C(0),	// V_MFMA_I32_32X32X8I8_gfx90a_acd
    UINT64_C(3553886208), UINT64_C(0),	// V_MFMA_I32_32X32X8I8_gfx90a_vcd
    UINT64_C(3553886208), UINT64_C(0),	// V_MFMA_I32_32X32X8I8_vi
    UINT64_C(3553787904), UINT64_C(0),	// V_MFMA_I32_4X4X4I8_gfx90a_acd
    UINT64_C(3553755136), UINT64_C(0),	// V_MFMA_I32_4X4X4I8_gfx90a_vcd
    UINT64_C(3553787904), UINT64_C(0),	// V_MFMA_I32_4X4X4I8_gfx940_acd
    UINT64_C(3553755136), UINT64_C(0),	// V_MFMA_I32_4X4X4I8_gfx940_vcd
    UINT64_C(3553755136), UINT64_C(0),	// V_MFMA_I32_4X4X4I8_vi
    UINT64_C(3551264768), UINT64_C(0),	// V_MFMA_LD_SCALE_B32_vi
    UINT64_C(3551264768), UINT64_C(3551365120),	// V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd
    UINT64_C(3551264768), UINT64_C(3551332352),	// V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd
    UINT64_C(3551264768), UINT64_C(3551365120),	// V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd
    UINT64_C(3551264768), UINT64_C(3551332352),	// V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd
    UINT64_C(3551264768), UINT64_C(3551365120),	// V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd
    UINT64_C(3551264768), UINT64_C(3551332352),	// V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd
    UINT64_C(3551264768), UINT64_C(3551365120),	// V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd
    UINT64_C(3551264768), UINT64_C(3551332352),	// V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd
    UINT64_C(3551264768), UINT64_C(3551365120),	// V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd
    UINT64_C(3551264768), UINT64_C(3551332352),	// V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd
    UINT64_C(3551264768), UINT64_C(3551365120),	// V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd
    UINT64_C(3551264768), UINT64_C(3551332352),	// V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd
    UINT64_C(3551264768), UINT64_C(3551365120),	// V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd
    UINT64_C(3551264768), UINT64_C(3551332352),	// V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd
    UINT64_C(3551264768), UINT64_C(3551365120),	// V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd
    UINT64_C(3551264768), UINT64_C(3551332352),	// V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd
    UINT64_C(3551264768), UINT64_C(3551365120),	// V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd
    UINT64_C(3551264768), UINT64_C(3551332352),	// V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd
    UINT64_C(3551264768), UINT64_C(3551430656),	// V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd
    UINT64_C(3551264768), UINT64_C(3551397888),	// V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd
    UINT64_C(3551264768), UINT64_C(3551430656),	// V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd
    UINT64_C(3551264768), UINT64_C(3551397888),	// V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd
    UINT64_C(3551264768), UINT64_C(3551430656),	// V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd
    UINT64_C(3551264768), UINT64_C(3551397888),	// V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd
    UINT64_C(3551264768), UINT64_C(3551430656),	// V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd
    UINT64_C(3551264768), UINT64_C(3551397888),	// V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd
    UINT64_C(3551264768), UINT64_C(3551430656),	// V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd
    UINT64_C(3551264768), UINT64_C(3551397888),	// V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd
    UINT64_C(3551264768), UINT64_C(3551430656),	// V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd
    UINT64_C(3551264768), UINT64_C(3551397888),	// V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd
    UINT64_C(3551264768), UINT64_C(3551430656),	// V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd
    UINT64_C(3551264768), UINT64_C(3551397888),	// V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd
    UINT64_C(3551264768), UINT64_C(3551430656),	// V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd
    UINT64_C(3551264768), UINT64_C(3551397888),	// V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd
    UINT64_C(3551264768), UINT64_C(3551430656),	// V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd
    UINT64_C(3551264768), UINT64_C(3551397888),	// V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd
    UINT64_C(3595108352), UINT64_C(0),	// V_MIN3_F16_fake16_e64_dpp8_gfx11
    UINT64_C(1077336932352), UINT64_C(0),	// V_MIN3_F16_fake16_e64_dpp_gfx11
    UINT64_C(3595108352), UINT64_C(0),	// V_MIN3_F16_fake16_e64_gfx11
    UINT64_C(3612409856), UINT64_C(0),	// V_MIN3_F16_gfx10
    UINT64_C(3595108352), UINT64_C(0),	// V_MIN3_F16_t16_e64_dpp8_gfx11
    UINT64_C(1077336932352), UINT64_C(0),	// V_MIN3_F16_t16_e64_dpp_gfx11
    UINT64_C(3595108352), UINT64_C(0),	// V_MIN3_F16_t16_e64_gfx11
    UINT64_C(3522428928), UINT64_C(0),	// V_MIN3_F16_vi
    UINT64_C(3591962624), UINT64_C(0),	// V_MIN3_F32_e64_dpp8_gfx11
    UINT64_C(1077333786624), UINT64_C(0),	// V_MIN3_F32_e64_dpp_gfx11
    UINT64_C(3591962624), UINT64_C(0),	// V_MIN3_F32_e64_gfx11
    UINT64_C(3578855424), UINT64_C(0),	// V_MIN3_F32_gfx10
    UINT64_C(3533832192), UINT64_C(0),	// V_MIN3_F32_gfx6_gfx7
    UINT64_C(3520069632), UINT64_C(0),	// V_MIN3_F32_vi
    UINT64_C(3595173888), UINT64_C(0),	// V_MIN3_I16V_MIN3_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3595173888), UINT64_C(0),	// V_MIN3_I16V_MIN3_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077336997888), UINT64_C(0),	// V_MIN3_I16V_MIN3_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077336997888), UINT64_C(0),	// V_MIN3_I16V_MIN3_I16_fake16_e64_dpp_gfx12
    UINT64_C(3595173888), UINT64_C(0),	// V_MIN3_I16V_MIN3_I16_fake16_e64_gfx11
    UINT64_C(3595173888), UINT64_C(0),	// V_MIN3_I16V_MIN3_I16_fake16_e64_gfx12
    UINT64_C(3595173888), UINT64_C(0),	// V_MIN3_I16V_MIN3_I16_t16_e64_dpp8_gfx11
    UINT64_C(3595173888), UINT64_C(0),	// V_MIN3_I16V_MIN3_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077336997888), UINT64_C(0),	// V_MIN3_I16V_MIN3_I16_t16_e64_dpp_gfx11
    UINT64_C(1077336997888), UINT64_C(0),	// V_MIN3_I16V_MIN3_I16_t16_e64_dpp_gfx12
    UINT64_C(3595173888), UINT64_C(0),	// V_MIN3_I16V_MIN3_I16_t16_e64_gfx11
    UINT64_C(3595173888), UINT64_C(0),	// V_MIN3_I16V_MIN3_I16_t16_e64_gfx12
    UINT64_C(3612475392), UINT64_C(0),	// V_MIN3_I16_gfx10
    UINT64_C(3522494464), UINT64_C(0),	// V_MIN3_I16_vi
    UINT64_C(3592028160), UINT64_C(0),	// V_MIN3_I32_e64_dpp8_gfx11
    UINT64_C(3592028160), UINT64_C(0),	// V_MIN3_I32_e64_dpp8_gfx12
    UINT64_C(1077333852160), UINT64_C(0),	// V_MIN3_I32_e64_dpp_gfx11
    UINT64_C(1077333852160), UINT64_C(0),	// V_MIN3_I32_e64_dpp_gfx12
    UINT64_C(3592028160), UINT64_C(0),	// V_MIN3_I32_e64_gfx11
    UINT64_C(3592028160), UINT64_C(0),	// V_MIN3_I32_e64_gfx12
    UINT64_C(3578920960), UINT64_C(0),	// V_MIN3_I32_gfx10
    UINT64_C(3533963264), UINT64_C(0),	// V_MIN3_I32_gfx6_gfx7
    UINT64_C(3520135168), UINT64_C(0),	// V_MIN3_I32_vi
    UINT64_C(3593142272), UINT64_C(0),	// V_MIN3_NUM_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077334966272), UINT64_C(0),	// V_MIN3_NUM_F16_fake16_e64_dpp_gfx12
    UINT64_C(3593142272), UINT64_C(0),	// V_MIN3_NUM_F16_fake16_e64_gfx12
    UINT64_C(3593142272), UINT64_C(0),	// V_MIN3_NUM_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077334966272), UINT64_C(0),	// V_MIN3_NUM_F16_t16_e64_dpp_gfx12
    UINT64_C(3593142272), UINT64_C(0),	// V_MIN3_NUM_F16_t16_e64_gfx12
    UINT64_C(3593011200), UINT64_C(0),	// V_MIN3_NUM_F32_e64_dpp8_gfx12
    UINT64_C(1077334835200), UINT64_C(0),	// V_MIN3_NUM_F32_e64_dpp_gfx12
    UINT64_C(3593011200), UINT64_C(0),	// V_MIN3_NUM_F32_e64_gfx12
    UINT64_C(3595239424), UINT64_C(0),	// V_MIN3_U16V_MIN3_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3595239424), UINT64_C(0),	// V_MIN3_U16V_MIN3_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077337063424), UINT64_C(0),	// V_MIN3_U16V_MIN3_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077337063424), UINT64_C(0),	// V_MIN3_U16V_MIN3_U16_fake16_e64_dpp_gfx12
    UINT64_C(3595239424), UINT64_C(0),	// V_MIN3_U16V_MIN3_U16_fake16_e64_gfx11
    UINT64_C(3595239424), UINT64_C(0),	// V_MIN3_U16V_MIN3_U16_fake16_e64_gfx12
    UINT64_C(3595239424), UINT64_C(0),	// V_MIN3_U16V_MIN3_U16_t16_e64_dpp8_gfx11
    UINT64_C(3595239424), UINT64_C(0),	// V_MIN3_U16V_MIN3_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077337063424), UINT64_C(0),	// V_MIN3_U16V_MIN3_U16_t16_e64_dpp_gfx11
    UINT64_C(1077337063424), UINT64_C(0),	// V_MIN3_U16V_MIN3_U16_t16_e64_dpp_gfx12
    UINT64_C(3595239424), UINT64_C(0),	// V_MIN3_U16V_MIN3_U16_t16_e64_gfx11
    UINT64_C(3595239424), UINT64_C(0),	// V_MIN3_U16V_MIN3_U16_t16_e64_gfx12
    UINT64_C(3612540928), UINT64_C(0),	// V_MIN3_U16_gfx10
    UINT64_C(3522560000), UINT64_C(0),	// V_MIN3_U16_vi
    UINT64_C(3592093696), UINT64_C(0),	// V_MIN3_U32_e64_dpp8_gfx11
    UINT64_C(3592093696), UINT64_C(0),	// V_MIN3_U32_e64_dpp8_gfx12
    UINT64_C(1077333917696), UINT64_C(0),	// V_MIN3_U32_e64_dpp_gfx11
    UINT64_C(1077333917696), UINT64_C(0),	// V_MIN3_U32_e64_dpp_gfx12
    UINT64_C(3592093696), UINT64_C(0),	// V_MIN3_U32_e64_gfx11
    UINT64_C(3592093696), UINT64_C(0),	// V_MIN3_U32_e64_gfx12
    UINT64_C(3578986496), UINT64_C(0),	// V_MIN3_U32_gfx10
    UINT64_C(3534094336), UINT64_C(0),	// V_MIN3_U32_gfx6_gfx7
    UINT64_C(3520200704), UINT64_C(0),	// V_MIN3_U32_vi
    UINT64_C(3593404416), UINT64_C(0),	// V_MINIMUM3_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077335228416), UINT64_C(0),	// V_MINIMUM3_F16_fake16_e64_dpp_gfx12
    UINT64_C(3593404416), UINT64_C(0),	// V_MINIMUM3_F16_fake16_e64_gfx12
    UINT64_C(3593404416), UINT64_C(0),	// V_MINIMUM3_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077335228416), UINT64_C(0),	// V_MINIMUM3_F16_t16_e64_dpp_gfx12
    UINT64_C(3593404416), UINT64_C(0),	// V_MINIMUM3_F16_t16_e64_gfx12
    UINT64_C(3593273344), UINT64_C(0),	// V_MINIMUM3_F32_e64_dpp8_gfx12
    UINT64_C(1077335097344), UINT64_C(0),	// V_MINIMUM3_F32_e64_dpp_gfx12
    UINT64_C(3593273344), UINT64_C(0),	// V_MINIMUM3_F32_e64_gfx12
    UINT64_C(3534225408), UINT64_C(0),	// V_MINIMUM3_F32_vi
    UINT64_C(3597533184), UINT64_C(0),	// V_MINIMUMMAXIMUM_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077339357184), UINT64_C(0),	// V_MINIMUMMAXIMUM_F16_fake16_e64_dpp_gfx12
    UINT64_C(3597533184), UINT64_C(0),	// V_MINIMUMMAXIMUM_F16_fake16_e64_gfx12
    UINT64_C(3597533184), UINT64_C(0),	// V_MINIMUMMAXIMUM_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077339357184), UINT64_C(0),	// V_MINIMUMMAXIMUM_F16_t16_e64_dpp_gfx12
    UINT64_C(3597533184), UINT64_C(0),	// V_MINIMUMMAXIMUM_F16_t16_e64_gfx12
    UINT64_C(3597402112), UINT64_C(0),	// V_MINIMUMMAXIMUM_F32_e64_dpp8_gfx12
    UINT64_C(1077339226112), UINT64_C(0),	// V_MINIMUMMAXIMUM_F32_e64_dpp_gfx12
    UINT64_C(3597402112), UINT64_C(0),	// V_MINIMUMMAXIMUM_F32_e64_gfx12
    UINT64_C(3613851648), UINT64_C(0),	// V_MINIMUM_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077355675648), UINT64_C(0),	// V_MINIMUM_F16_fake16_e64_dpp_gfx12
    UINT64_C(3613851648), UINT64_C(0),	// V_MINIMUM_F16_fake16_e64_gfx12
    UINT64_C(3613851648), UINT64_C(0),	// V_MINIMUM_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077355675648), UINT64_C(0),	// V_MINIMUM_F16_t16_e64_dpp_gfx12
    UINT64_C(3613851648), UINT64_C(0),	// V_MINIMUM_F16_t16_e64_gfx12
    UINT64_C(3613720576), UINT64_C(0),	// V_MINIMUM_F32_e64_dpp8_gfx12
    UINT64_C(1077355544576), UINT64_C(0),	// V_MINIMUM_F32_e64_dpp_gfx12
    UINT64_C(3613720576), UINT64_C(0),	// V_MINIMUM_F32_e64_gfx12
    UINT64_C(1077353185280), UINT64_C(0),	// V_MINIMUM_F64_e64_dpp_gfx11
    UINT64_C(1077353185280), UINT64_C(0),	// V_MINIMUM_F64_e64_dpp_gfx12
    UINT64_C(3611361280), UINT64_C(0),	// V_MINIMUM_F64_e64_gfx11
    UINT64_C(3611361280), UINT64_C(0),	// V_MINIMUM_F64_e64_gfx12
    UINT64_C(3596681216), UINT64_C(0),	// V_MINMAX_F16_fake16_e64_dpp8_gfx11
    UINT64_C(1077338505216), UINT64_C(0),	// V_MINMAX_F16_fake16_e64_dpp_gfx11
    UINT64_C(3596681216), UINT64_C(0),	// V_MINMAX_F16_fake16_e64_gfx11
    UINT64_C(3596681216), UINT64_C(0),	// V_MINMAX_F16_t16_e64_dpp8_gfx11
    UINT64_C(1077338505216), UINT64_C(0),	// V_MINMAX_F16_t16_e64_dpp_gfx11
    UINT64_C(3596681216), UINT64_C(0),	// V_MINMAX_F16_t16_e64_gfx11
    UINT64_C(3596550144), UINT64_C(0),	// V_MINMAX_F32_e64_dpp8_gfx11
    UINT64_C(1077338374144), UINT64_C(0),	// V_MINMAX_F32_e64_dpp_gfx11
    UINT64_C(3596550144), UINT64_C(0),	// V_MINMAX_F32_e64_gfx11
    UINT64_C(3596943360), UINT64_C(0),	// V_MINMAX_I32_e64_dpp8_gfx11
    UINT64_C(3596943360), UINT64_C(0),	// V_MINMAX_I32_e64_dpp8_gfx12
    UINT64_C(1077338767360), UINT64_C(0),	// V_MINMAX_I32_e64_dpp_gfx11
    UINT64_C(1077338767360), UINT64_C(0),	// V_MINMAX_I32_e64_dpp_gfx12
    UINT64_C(3596943360), UINT64_C(0),	// V_MINMAX_I32_e64_gfx11
    UINT64_C(3596943360), UINT64_C(0),	// V_MINMAX_I32_e64_gfx12
    UINT64_C(3597271040), UINT64_C(0),	// V_MINMAX_NUM_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077339095040), UINT64_C(0),	// V_MINMAX_NUM_F16_fake16_e64_dpp_gfx12
    UINT64_C(3597271040), UINT64_C(0),	// V_MINMAX_NUM_F16_fake16_e64_gfx12
    UINT64_C(3597271040), UINT64_C(0),	// V_MINMAX_NUM_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077339095040), UINT64_C(0),	// V_MINMAX_NUM_F16_t16_e64_dpp_gfx12
    UINT64_C(3597271040), UINT64_C(0),	// V_MINMAX_NUM_F16_t16_e64_gfx12
    UINT64_C(3597139968), UINT64_C(0),	// V_MINMAX_NUM_F32_e64_dpp8_gfx12
    UINT64_C(1077338963968), UINT64_C(0),	// V_MINMAX_NUM_F32_e64_dpp_gfx12
    UINT64_C(3597139968), UINT64_C(0),	// V_MINMAX_NUM_F32_e64_gfx12
    UINT64_C(3596812288), UINT64_C(0),	// V_MINMAX_U32_e64_dpp8_gfx11
    UINT64_C(3596812288), UINT64_C(0),	// V_MINMAX_U32_e64_dpp8_gfx12
    UINT64_C(1077338636288), UINT64_C(0),	// V_MINMAX_U32_e64_dpp_gfx11
    UINT64_C(1077338636288), UINT64_C(0),	// V_MINMAX_U32_e64_dpp_gfx12
    UINT64_C(3596812288), UINT64_C(0),	// V_MINMAX_U32_e64_gfx11
    UINT64_C(3596812288), UINT64_C(0),	// V_MINMAX_U32_e64_gfx12
    UINT64_C(1946157056), UINT64_C(0),	// V_MIN_F16V_MIN_F16_fake16_dpp8_gfx11
    UINT64_C(1946157306), UINT64_C(0),	// V_MIN_F16V_MIN_F16_fake16_dpp_gfx11
    UINT64_C(1946157056), UINT64_C(0),	// V_MIN_F16V_MIN_F16_fake16_e32_gfx11
    UINT64_C(3577348096), UINT64_C(0),	// V_MIN_F16V_MIN_F16_fake16_e64_dpp8_gfx11
    UINT64_C(1077319172096), UINT64_C(0),	// V_MIN_F16V_MIN_F16_fake16_e64_dpp_gfx11
    UINT64_C(3577348096), UINT64_C(0),	// V_MIN_F16V_MIN_F16_fake16_e64_gfx11
    UINT64_C(1946157056), UINT64_C(0),	// V_MIN_F16V_MIN_F16_t16_dpp8_gfx11
    UINT64_C(1946157306), UINT64_C(0),	// V_MIN_F16V_MIN_F16_t16_dpp_gfx11
    UINT64_C(1946157056), UINT64_C(0),	// V_MIN_F16V_MIN_F16_t16_e32_gfx11
    UINT64_C(3577348096), UINT64_C(0),	// V_MIN_F16V_MIN_F16_t16_e64_dpp8_gfx11
    UINT64_C(1077319172096), UINT64_C(0),	// V_MIN_F16V_MIN_F16_t16_e64_dpp_gfx11
    UINT64_C(3577348096), UINT64_C(0),	// V_MIN_F16V_MIN_F16_t16_e64_gfx11
    UINT64_C(1946157056), UINT64_C(0),	// V_MIN_F16_dpp8_gfx10
    UINT64_C(1946157306), UINT64_C(0),	// V_MIN_F16_dpp_gfx10
    UINT64_C(1543504122), UINT64_C(0),	// V_MIN_F16_dpp_vi
    UINT64_C(1946157056), UINT64_C(0),	// V_MIN_F16_e32_gfx10
    UINT64_C(1543503872), UINT64_C(0),	// V_MIN_F16_e32_vi
    UINT64_C(3577348096), UINT64_C(0),	// V_MIN_F16_e64_gfx10
    UINT64_C(3509452800), UINT64_C(0),	// V_MIN_F16_e64_vi
    UINT64_C(1946157305), UINT64_C(0),	// V_MIN_F16_sdwa_gfx10
    UINT64_C(1543504121), UINT64_C(0),	// V_MIN_F16_sdwa_gfx9
    UINT64_C(1543504121), UINT64_C(0),	// V_MIN_F16_sdwa_vi
    UINT64_C(503316480), UINT64_C(0),	// V_MIN_F32_dpp8_gfx10
    UINT64_C(503316480), UINT64_C(0),	// V_MIN_F32_dpp8_gfx11
    UINT64_C(503316730), UINT64_C(0),	// V_MIN_F32_dpp_gfx10
    UINT64_C(503316730), UINT64_C(0),	// V_MIN_F32_dpp_gfx11
    UINT64_C(335544570), UINT64_C(0),	// V_MIN_F32_dpp_vi
    UINT64_C(503316480), UINT64_C(0),	// V_MIN_F32_e32_gfx10
    UINT64_C(503316480), UINT64_C(0),	// V_MIN_F32_e32_gfx11
    UINT64_C(503316480), UINT64_C(0),	// V_MIN_F32_e32_gfx6_gfx7
    UINT64_C(335544320), UINT64_C(0),	// V_MIN_F32_e32_vi
    UINT64_C(3574530048), UINT64_C(0),	// V_MIN_F32_e64_dpp8_gfx11
    UINT64_C(1077316354048), UINT64_C(0),	// V_MIN_F32_e64_dpp_gfx11
    UINT64_C(3574530048), UINT64_C(0),	// V_MIN_F32_e64_gfx10
    UINT64_C(3574530048), UINT64_C(0),	// V_MIN_F32_e64_gfx11
    UINT64_C(3525181440), UINT64_C(0),	// V_MIN_F32_e64_gfx6_gfx7
    UINT64_C(3507093504), UINT64_C(0),	// V_MIN_F32_e64_vi
    UINT64_C(503316729), UINT64_C(0),	// V_MIN_F32_sdwa_gfx10
    UINT64_C(335544569), UINT64_C(0),	// V_MIN_F32_sdwa_gfx9
    UINT64_C(335544569), UINT64_C(0),	// V_MIN_F32_sdwa_vi
    UINT64_C(3609788416), UINT64_C(0),	// V_MIN_F64_e64_gfx11
    UINT64_C(3580231680), UINT64_C(0),	// V_MIN_F64_gfx10
    UINT64_C(3536584704), UINT64_C(0),	// V_MIN_F64_gfx6_gfx7
    UINT64_C(3531735040), UINT64_C(0),	// V_MIN_F64_vi
    UINT64_C(1677721850), UINT64_C(0),	// V_MIN_I16_dpp_vi
    UINT64_C(1677721600), UINT64_C(0),	// V_MIN_I16_e32_vi
    UINT64_C(3509714944), UINT64_C(0),	// V_MIN_I16_e64_vi
    UINT64_C(3607887872), UINT64_C(0),	// V_MIN_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3607887872), UINT64_C(0),	// V_MIN_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077349711872), UINT64_C(0),	// V_MIN_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077349711872), UINT64_C(0),	// V_MIN_I16_fake16_e64_dpp_gfx12
    UINT64_C(3607887872), UINT64_C(0),	// V_MIN_I16_fake16_e64_gfx11
    UINT64_C(3607887872), UINT64_C(0),	// V_MIN_I16_fake16_e64_gfx12
    UINT64_C(3607887872), UINT64_C(0),	// V_MIN_I16_gfx10
    UINT64_C(1677721849), UINT64_C(0),	// V_MIN_I16_sdwa_gfx9
    UINT64_C(1677721849), UINT64_C(0),	// V_MIN_I16_sdwa_vi
    UINT64_C(3607887872), UINT64_C(0),	// V_MIN_I16_t16_e64_dpp8_gfx11
    UINT64_C(3607887872), UINT64_C(0),	// V_MIN_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077349711872), UINT64_C(0),	// V_MIN_I16_t16_e64_dpp_gfx11
    UINT64_C(1077349711872), UINT64_C(0),	// V_MIN_I16_t16_e64_dpp_gfx12
    UINT64_C(3607887872), UINT64_C(0),	// V_MIN_I16_t16_e64_gfx11
    UINT64_C(3607887872), UINT64_C(0),	// V_MIN_I16_t16_e64_gfx12
    UINT64_C(570425344), UINT64_C(0),	// V_MIN_I32_dpp8_gfx10
    UINT64_C(570425344), UINT64_C(0),	// V_MIN_I32_dpp8_gfx11
    UINT64_C(570425344), UINT64_C(0),	// V_MIN_I32_dpp8_gfx12
    UINT64_C(570425594), UINT64_C(0),	// V_MIN_I32_dpp_gfx10
    UINT64_C(570425594), UINT64_C(0),	// V_MIN_I32_dpp_gfx11
    UINT64_C(570425594), UINT64_C(0),	// V_MIN_I32_dpp_gfx12
    UINT64_C(402653434), UINT64_C(0),	// V_MIN_I32_dpp_vi
    UINT64_C(570425344), UINT64_C(0),	// V_MIN_I32_e32_gfx10
    UINT64_C(570425344), UINT64_C(0),	// V_MIN_I32_e32_gfx11
    UINT64_C(570425344), UINT64_C(0),	// V_MIN_I32_e32_gfx12
    UINT64_C(570425344), UINT64_C(0),	// V_MIN_I32_e32_gfx6_gfx7
    UINT64_C(402653184), UINT64_C(0),	// V_MIN_I32_e32_vi
    UINT64_C(3574661120), UINT64_C(0),	// V_MIN_I32_e64_dpp8_gfx11
    UINT64_C(3574661120), UINT64_C(0),	// V_MIN_I32_e64_dpp8_gfx12
    UINT64_C(1077316485120), UINT64_C(0),	// V_MIN_I32_e64_dpp_gfx11
    UINT64_C(1077316485120), UINT64_C(0),	// V_MIN_I32_e64_dpp_gfx12
    UINT64_C(3574661120), UINT64_C(0),	// V_MIN_I32_e64_gfx10
    UINT64_C(3574661120), UINT64_C(0),	// V_MIN_I32_e64_gfx11
    UINT64_C(3574661120), UINT64_C(0),	// V_MIN_I32_e64_gfx12
    UINT64_C(3525443584), UINT64_C(0),	// V_MIN_I32_e64_gfx6_gfx7
    UINT64_C(3507224576), UINT64_C(0),	// V_MIN_I32_e64_vi
    UINT64_C(570425593), UINT64_C(0),	// V_MIN_I32_sdwa_gfx10
    UINT64_C(402653433), UINT64_C(0),	// V_MIN_I32_sdwa_gfx9
    UINT64_C(402653433), UINT64_C(0),	// V_MIN_I32_sdwa_vi
    UINT64_C(1077350629376), UINT64_C(0),	// V_MIN_I64_e64_dpp_gfx1250
    UINT64_C(3608805376), UINT64_C(0),	// V_MIN_I64_e64_gfx1250
    UINT64_C(436207616), UINT64_C(0),	// V_MIN_LEGACY_F32_e32_gfx6_gfx7
    UINT64_C(3524919296), UINT64_C(0),	// V_MIN_LEGACY_F32_e64_gfx6_gfx7
    UINT64_C(1610612736), UINT64_C(0),	// V_MIN_NUM_F16_fake16_dpp8_gfx12
    UINT64_C(1610612986), UINT64_C(0),	// V_MIN_NUM_F16_fake16_dpp_gfx12
    UINT64_C(1610612736), UINT64_C(0),	// V_MIN_NUM_F16_fake16_e32_gfx12
    UINT64_C(3576692736), UINT64_C(0),	// V_MIN_NUM_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077318516736), UINT64_C(0),	// V_MIN_NUM_F16_fake16_e64_dpp_gfx12
    UINT64_C(3576692736), UINT64_C(0),	// V_MIN_NUM_F16_fake16_e64_gfx12
    UINT64_C(1610612736), UINT64_C(0),	// V_MIN_NUM_F16_t16_dpp8_gfx12
    UINT64_C(1610612986), UINT64_C(0),	// V_MIN_NUM_F16_t16_dpp_gfx12
    UINT64_C(1610612736), UINT64_C(0),	// V_MIN_NUM_F16_t16_e32_gfx12
    UINT64_C(3576692736), UINT64_C(0),	// V_MIN_NUM_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077318516736), UINT64_C(0),	// V_MIN_NUM_F16_t16_e64_dpp_gfx12
    UINT64_C(3576692736), UINT64_C(0),	// V_MIN_NUM_F16_t16_e64_gfx12
    UINT64_C(704643072), UINT64_C(0),	// V_MIN_NUM_F32_dpp8_gfx12
    UINT64_C(704643322), UINT64_C(0),	// V_MIN_NUM_F32_dpp_gfx12
    UINT64_C(704643072), UINT64_C(0),	// V_MIN_NUM_F32_e32_gfx12
    UINT64_C(3574923264), UINT64_C(0),	// V_MIN_NUM_F32_e64_dpp8_gfx12
    UINT64_C(1077316747264), UINT64_C(0),	// V_MIN_NUM_F32_e64_dpp_gfx12
    UINT64_C(3574923264), UINT64_C(0),	// V_MIN_NUM_F32_e64_gfx12
    UINT64_C(436207866), UINT64_C(0),	// V_MIN_NUM_F64_dpp_gfx12
    UINT64_C(436207616), UINT64_C(0),	// V_MIN_NUM_F64_e32_gfx12
    UINT64_C(1077316222976), UINT64_C(0),	// V_MIN_NUM_F64_e64_dpp_gfx12
    UINT64_C(3574398976), UINT64_C(0),	// V_MIN_NUM_F64_e64_gfx12
    UINT64_C(1644167418), UINT64_C(0),	// V_MIN_U16_dpp_vi
    UINT64_C(1644167168), UINT64_C(0),	// V_MIN_U16_e32_vi
    UINT64_C(3509649408), UINT64_C(0),	// V_MIN_U16_e64_vi
    UINT64_C(3607822336), UINT64_C(0),	// V_MIN_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3607822336), UINT64_C(0),	// V_MIN_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077349646336), UINT64_C(0),	// V_MIN_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077349646336), UINT64_C(0),	// V_MIN_U16_fake16_e64_dpp_gfx12
    UINT64_C(3607822336), UINT64_C(0),	// V_MIN_U16_fake16_e64_gfx11
    UINT64_C(3607822336), UINT64_C(0),	// V_MIN_U16_fake16_e64_gfx12
    UINT64_C(3607822336), UINT64_C(0),	// V_MIN_U16_gfx10
    UINT64_C(1644167417), UINT64_C(0),	// V_MIN_U16_sdwa_gfx9
    UINT64_C(1644167417), UINT64_C(0),	// V_MIN_U16_sdwa_vi
    UINT64_C(3607822336), UINT64_C(0),	// V_MIN_U16_t16_e64_dpp8_gfx11
    UINT64_C(3607822336), UINT64_C(0),	// V_MIN_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077349646336), UINT64_C(0),	// V_MIN_U16_t16_e64_dpp_gfx11
    UINT64_C(1077349646336), UINT64_C(0),	// V_MIN_U16_t16_e64_dpp_gfx12
    UINT64_C(3607822336), UINT64_C(0),	// V_MIN_U16_t16_e64_gfx11
    UINT64_C(3607822336), UINT64_C(0),	// V_MIN_U16_t16_e64_gfx12
    UINT64_C(637534208), UINT64_C(0),	// V_MIN_U32_dpp8_gfx10
    UINT64_C(637534208), UINT64_C(0),	// V_MIN_U32_dpp8_gfx11
    UINT64_C(637534208), UINT64_C(0),	// V_MIN_U32_dpp8_gfx12
    UINT64_C(637534458), UINT64_C(0),	// V_MIN_U32_dpp_gfx10
    UINT64_C(637534458), UINT64_C(0),	// V_MIN_U32_dpp_gfx11
    UINT64_C(637534458), UINT64_C(0),	// V_MIN_U32_dpp_gfx12
    UINT64_C(469762298), UINT64_C(0),	// V_MIN_U32_dpp_vi
    UINT64_C(637534208), UINT64_C(0),	// V_MIN_U32_e32_gfx10
    UINT64_C(637534208), UINT64_C(0),	// V_MIN_U32_e32_gfx11
    UINT64_C(637534208), UINT64_C(0),	// V_MIN_U32_e32_gfx12
    UINT64_C(637534208), UINT64_C(0),	// V_MIN_U32_e32_gfx6_gfx7
    UINT64_C(469762048), UINT64_C(0),	// V_MIN_U32_e32_vi
    UINT64_C(3574792192), UINT64_C(0),	// V_MIN_U32_e64_dpp8_gfx11
    UINT64_C(3574792192), UINT64_C(0),	// V_MIN_U32_e64_dpp8_gfx12
    UINT64_C(1077316616192), UINT64_C(0),	// V_MIN_U32_e64_dpp_gfx11
    UINT64_C(1077316616192), UINT64_C(0),	// V_MIN_U32_e64_dpp_gfx12
    UINT64_C(3574792192), UINT64_C(0),	// V_MIN_U32_e64_gfx10
    UINT64_C(3574792192), UINT64_C(0),	// V_MIN_U32_e64_gfx11
    UINT64_C(3574792192), UINT64_C(0),	// V_MIN_U32_e64_gfx12
    UINT64_C(3525705728), UINT64_C(0),	// V_MIN_U32_e64_gfx6_gfx7
    UINT64_C(3507355648), UINT64_C(0),	// V_MIN_U32_e64_vi
    UINT64_C(637534457), UINT64_C(0),	// V_MIN_U32_sdwa_gfx10
    UINT64_C(469762297), UINT64_C(0),	// V_MIN_U32_sdwa_gfx9
    UINT64_C(469762297), UINT64_C(0),	// V_MIN_U32_sdwa_vi
    UINT64_C(1077350498304), UINT64_C(0),	// V_MIN_U64_e64_dpp_gfx1250
    UINT64_C(3608674304), UINT64_C(0),	// V_MIN_U64_e64_gfx1250
    UINT64_C(2113963008), UINT64_C(0),	// V_MOVRELD_B32_dpp8_gfx10
    UINT64_C(2113963008), UINT64_C(0),	// V_MOVRELD_B32_dpp8_gfx11
    UINT64_C(2113963008), UINT64_C(0),	// V_MOVRELD_B32_dpp8_gfx12
    UINT64_C(2113963258), UINT64_C(0),	// V_MOVRELD_B32_dpp_gfx10
    UINT64_C(2113963258), UINT64_C(0),	// V_MOVRELD_B32_dpp_gfx11
    UINT64_C(2113963258), UINT64_C(0),	// V_MOVRELD_B32_dpp_gfx12
    UINT64_C(2113963008), UINT64_C(0),	// V_MOVRELD_B32_e32_gfx10
    UINT64_C(2113963008), UINT64_C(0),	// V_MOVRELD_B32_e32_gfx11
    UINT64_C(2113963008), UINT64_C(0),	// V_MOVRELD_B32_e32_gfx12
    UINT64_C(2113963008), UINT64_C(0),	// V_MOVRELD_B32_e32_gfx6_gfx7
    UINT64_C(2113956864), UINT64_C(0),	// V_MOVRELD_B32_e32_vi
    UINT64_C(3586260992), UINT64_C(0),	// V_MOVRELD_B32_e64_dpp8_gfx11
    UINT64_C(3586260992), UINT64_C(0),	// V_MOVRELD_B32_e64_dpp8_gfx12
    UINT64_C(1077328084992), UINT64_C(0),	// V_MOVRELD_B32_e64_dpp_gfx11
    UINT64_C(1077328084992), UINT64_C(0),	// V_MOVRELD_B32_e64_dpp_gfx12
    UINT64_C(3586260992), UINT64_C(0),	// V_MOVRELD_B32_e64_gfx10
    UINT64_C(3586260992), UINT64_C(0),	// V_MOVRELD_B32_e64_gfx11
    UINT64_C(3586260992), UINT64_C(0),	// V_MOVRELD_B32_e64_gfx12
    UINT64_C(3548643328), UINT64_C(0),	// V_MOVRELD_B32_e64_gfx6_gfx7
    UINT64_C(3514171392), UINT64_C(0),	// V_MOVRELD_B32_e64_vi
    UINT64_C(2113963257), UINT64_C(0),	// V_MOVRELD_B32_sdwa_gfx10
    UINT64_C(2113966080), UINT64_C(0),	// V_MOVRELSD_2_B32_dpp8_gfx10
    UINT64_C(2113966080), UINT64_C(0),	// V_MOVRELSD_2_B32_dpp8_gfx11
    UINT64_C(2113966080), UINT64_C(0),	// V_MOVRELSD_2_B32_dpp8_gfx12
    UINT64_C(2113966330), UINT64_C(0),	// V_MOVRELSD_2_B32_dpp_gfx10
    UINT64_C(2113966330), UINT64_C(0),	// V_MOVRELSD_2_B32_dpp_gfx11
    UINT64_C(2113966330), UINT64_C(0),	// V_MOVRELSD_2_B32_dpp_gfx12
    UINT64_C(2113966080), UINT64_C(0),	// V_MOVRELSD_2_B32_e32_gfx10
    UINT64_C(2113966080), UINT64_C(0),	// V_MOVRELSD_2_B32_e32_gfx11
    UINT64_C(2113966080), UINT64_C(0),	// V_MOVRELSD_2_B32_e32_gfx12
    UINT64_C(3586654208), UINT64_C(0),	// V_MOVRELSD_2_B32_e64_dpp8_gfx11
    UINT64_C(3586654208), UINT64_C(0),	// V_MOVRELSD_2_B32_e64_dpp8_gfx12
    UINT64_C(1077328478208), UINT64_C(0),	// V_MOVRELSD_2_B32_e64_dpp_gfx11
    UINT64_C(1077328478208), UINT64_C(0),	// V_MOVRELSD_2_B32_e64_dpp_gfx12
    UINT64_C(3586654208), UINT64_C(0),	// V_MOVRELSD_2_B32_e64_gfx10
    UINT64_C(3586654208), UINT64_C(0),	// V_MOVRELSD_2_B32_e64_gfx11
    UINT64_C(3586654208), UINT64_C(0),	// V_MOVRELSD_2_B32_e64_gfx12
    UINT64_C(2113966329), UINT64_C(0),	// V_MOVRELSD_2_B32_sdwa_gfx10
    UINT64_C(2113964032), UINT64_C(0),	// V_MOVRELSD_B32_dpp8_gfx10
    UINT64_C(2113964032), UINT64_C(0),	// V_MOVRELSD_B32_dpp8_gfx11
    UINT64_C(2113964032), UINT64_C(0),	// V_MOVRELSD_B32_dpp8_gfx12
    UINT64_C(2113964282), UINT64_C(0),	// V_MOVRELSD_B32_dpp_gfx10
    UINT64_C(2113964282), UINT64_C(0),	// V_MOVRELSD_B32_dpp_gfx11
    UINT64_C(2113964282), UINT64_C(0),	// V_MOVRELSD_B32_dpp_gfx12
    UINT64_C(2113964032), UINT64_C(0),	// V_MOVRELSD_B32_e32_gfx10
    UINT64_C(2113964032), UINT64_C(0),	// V_MOVRELSD_B32_e32_gfx11
    UINT64_C(2113964032), UINT64_C(0),	// V_MOVRELSD_B32_e32_gfx12
    UINT64_C(2113964032), UINT64_C(0),	// V_MOVRELSD_B32_e32_gfx6_gfx7
    UINT64_C(2113957888), UINT64_C(0),	// V_MOVRELSD_B32_e32_vi
    UINT64_C(3586392064), UINT64_C(0),	// V_MOVRELSD_B32_e64_dpp8_gfx11
    UINT64_C(3586392064), UINT64_C(0),	// V_MOVRELSD_B32_e64_dpp8_gfx12
    UINT64_C(1077328216064), UINT64_C(0),	// V_MOVRELSD_B32_e64_dpp_gfx11
    UINT64_C(1077328216064), UINT64_C(0),	// V_MOVRELSD_B32_e64_dpp_gfx12
    UINT64_C(3586392064), UINT64_C(0),	// V_MOVRELSD_B32_e64_gfx10
    UINT64_C(3586392064), UINT64_C(0),	// V_MOVRELSD_B32_e64_gfx11
    UINT64_C(3586392064), UINT64_C(0),	// V_MOVRELSD_B32_e64_gfx12
    UINT64_C(3548905472), UINT64_C(0),	// V_MOVRELSD_B32_e64_gfx6_gfx7
    UINT64_C(3514302464), UINT64_C(0),	// V_MOVRELSD_B32_e64_vi
    UINT64_C(2113964281), UINT64_C(0),	// V_MOVRELSD_B32_sdwa_gfx10
    UINT64_C(2113963520), UINT64_C(0),	// V_MOVRELS_B32_dpp8_gfx10
    UINT64_C(2113963520), UINT64_C(0),	// V_MOVRELS_B32_dpp8_gfx11
    UINT64_C(2113963520), UINT64_C(0),	// V_MOVRELS_B32_dpp8_gfx12
    UINT64_C(2113963770), UINT64_C(0),	// V_MOVRELS_B32_dpp_gfx10
    UINT64_C(2113963770), UINT64_C(0),	// V_MOVRELS_B32_dpp_gfx11
    UINT64_C(2113963770), UINT64_C(0),	// V_MOVRELS_B32_dpp_gfx12
    UINT64_C(2113963520), UINT64_C(0),	// V_MOVRELS_B32_e32_gfx10
    UINT64_C(2113963520), UINT64_C(0),	// V_MOVRELS_B32_e32_gfx11
    UINT64_C(2113963520), UINT64_C(0),	// V_MOVRELS_B32_e32_gfx12
    UINT64_C(2113963520), UINT64_C(0),	// V_MOVRELS_B32_e32_gfx6_gfx7
    UINT64_C(2113957376), UINT64_C(0),	// V_MOVRELS_B32_e32_vi
    UINT64_C(3586326528), UINT64_C(0),	// V_MOVRELS_B32_e64_dpp8_gfx11
    UINT64_C(3586326528), UINT64_C(0),	// V_MOVRELS_B32_e64_dpp8_gfx12
    UINT64_C(1077328150528), UINT64_C(0),	// V_MOVRELS_B32_e64_dpp_gfx11
    UINT64_C(1077328150528), UINT64_C(0),	// V_MOVRELS_B32_e64_dpp_gfx12
    UINT64_C(3586326528), UINT64_C(0),	// V_MOVRELS_B32_e64_gfx10
    UINT64_C(3586326528), UINT64_C(0),	// V_MOVRELS_B32_e64_gfx11
    UINT64_C(3586326528), UINT64_C(0),	// V_MOVRELS_B32_e64_gfx12
    UINT64_C(3548774400), UINT64_C(0),	// V_MOVRELS_B32_e64_gfx6_gfx7
    UINT64_C(3514236928), UINT64_C(0),	// V_MOVRELS_B32_e64_vi
    UINT64_C(2113963769), UINT64_C(0),	// V_MOVRELS_B32_sdwa_gfx10
    UINT64_C(2113943552), UINT64_C(0),	// V_MOV_B16_t16_dpp8_gfx11
    UINT64_C(2113943552), UINT64_C(0),	// V_MOV_B16_t16_dpp8_gfx12
    UINT64_C(2113943802), UINT64_C(0),	// V_MOV_B16_t16_dpp_gfx11
    UINT64_C(2113943802), UINT64_C(0),	// V_MOV_B16_t16_dpp_gfx12
    UINT64_C(2113943552), UINT64_C(0),	// V_MOV_B16_t16_e32_gfx11
    UINT64_C(2113943552), UINT64_C(0),	// V_MOV_B16_t16_e32_gfx12
    UINT64_C(3583770624), UINT64_C(0),	// V_MOV_B16_t16_e64_dpp8_gfx11
    UINT64_C(3583770624), UINT64_C(0),	// V_MOV_B16_t16_e64_dpp8_gfx12
    UINT64_C(1077325594624), UINT64_C(0),	// V_MOV_B16_t16_e64_dpp_gfx11
    UINT64_C(1077325594624), UINT64_C(0),	// V_MOV_B16_t16_e64_dpp_gfx12
    UINT64_C(3583770624), UINT64_C(0),	// V_MOV_B16_t16_e64_gfx11
    UINT64_C(3583770624), UINT64_C(0),	// V_MOV_B16_t16_e64_gfx12
    UINT64_C(2113929728), UINT64_C(0),	// V_MOV_B32_dpp8_gfx10
    UINT64_C(2113929728), UINT64_C(0),	// V_MOV_B32_dpp8_gfx11
    UINT64_C(2113929728), UINT64_C(0),	// V_MOV_B32_dpp8_gfx12
    UINT64_C(2113929978), UINT64_C(0),	// V_MOV_B32_dpp_gfx10
    UINT64_C(2113929978), UINT64_C(0),	// V_MOV_B32_dpp_gfx11
    UINT64_C(2113929978), UINT64_C(0),	// V_MOV_B32_dpp_gfx12
    UINT64_C(2113929978), UINT64_C(0),	// V_MOV_B32_dpp_vi
    UINT64_C(2113929728), UINT64_C(0),	// V_MOV_B32_e32_gfx10
    UINT64_C(2113929728), UINT64_C(0),	// V_MOV_B32_e32_gfx11
    UINT64_C(2113929728), UINT64_C(0),	// V_MOV_B32_e32_gfx12
    UINT64_C(2113929728), UINT64_C(0),	// V_MOV_B32_e32_gfx6_gfx7
    UINT64_C(2113929728), UINT64_C(0),	// V_MOV_B32_e32_vi
    UINT64_C(3582001152), UINT64_C(0),	// V_MOV_B32_e64_dpp8_gfx11
    UINT64_C(3582001152), UINT64_C(0),	// V_MOV_B32_e64_dpp8_gfx12
    UINT64_C(1077323825152), UINT64_C(0),	// V_MOV_B32_e64_dpp_gfx11
    UINT64_C(1077323825152), UINT64_C(0),	// V_MOV_B32_e64_dpp_gfx12
    UINT64_C(3582001152), UINT64_C(0),	// V_MOV_B32_e64_gfx10
    UINT64_C(3582001152), UINT64_C(0),	// V_MOV_B32_e64_gfx11
    UINT64_C(3582001152), UINT64_C(0),	// V_MOV_B32_e64_gfx12
    UINT64_C(3540123648), UINT64_C(0),	// V_MOV_B32_e64_gfx6_gfx7
    UINT64_C(3510697984), UINT64_C(0),	// V_MOV_B32_e64_vi
    UINT64_C(2113929977), UINT64_C(0),	// V_MOV_B32_sdwa_gfx10
    UINT64_C(2113929977), UINT64_C(0),	// V_MOV_B32_sdwa_gfx9
    UINT64_C(2113929977), UINT64_C(0),	// V_MOV_B32_sdwa_vi
    UINT64_C(2113944314), UINT64_C(0),	// V_MOV_B64_dpp_gfx1250
    UINT64_C(2113958138), UINT64_C(0),	// V_MOV_B64_dpp_gfx9
    UINT64_C(2113944064), UINT64_C(0),	// V_MOV_B64_e32_gfx1250
    UINT64_C(2113957888), UINT64_C(0),	// V_MOV_B64_e32_vi
    UINT64_C(1077325660160), UINT64_C(0),	// V_MOV_B64_e64_dpp_gfx1250
    UINT64_C(3583836160), UINT64_C(0),	// V_MOV_B64_e64_gfx1250
    UINT64_C(3514302464), UINT64_C(0),	// V_MOV_B64_e64_vi
    UINT64_C(3594190848), UINT64_C(0),	// V_MQSAD_PK_U16_U8_e64_gfx11
    UINT64_C(3594190848), UINT64_C(0),	// V_MQSAD_PK_U16_U8_e64_gfx12
    UINT64_C(3581083648), UINT64_C(0),	// V_MQSAD_PK_U16_U8_gfx10
    UINT64_C(3538288640), UINT64_C(0),	// V_MQSAD_PK_U16_U8_gfx6_gfx7
    UINT64_C(3521511424), UINT64_C(0),	// V_MQSAD_PK_U16_U8_vi
    UINT64_C(3594321920), UINT64_C(0),	// V_MQSAD_U32_U8_e64_gfx11
    UINT64_C(3594321920), UINT64_C(0),	// V_MQSAD_U32_U8_e64_gfx12
    UINT64_C(3581214720), UINT64_C(0),	// V_MQSAD_U32_U8_gfx10
    UINT64_C(3538550784), UINT64_C(0),	// V_MQSAD_U32_U8_gfx7
    UINT64_C(3521576960), UINT64_C(0),	// V_MQSAD_U32_U8_vi
    UINT64_C(3594059776), UINT64_C(0),	// V_MSAD_U8_e64_dpp8_gfx11
    UINT64_C(3594059776), UINT64_C(0),	// V_MSAD_U8_e64_dpp8_gfx12
    UINT64_C(1077335883776), UINT64_C(0),	// V_MSAD_U8_e64_dpp_gfx11
    UINT64_C(1077335883776), UINT64_C(0),	// V_MSAD_U8_e64_dpp_gfx12
    UINT64_C(3594059776), UINT64_C(0),	// V_MSAD_U8_e64_gfx11
    UINT64_C(3594059776), UINT64_C(0),	// V_MSAD_U8_e64_gfx12
    UINT64_C(3580952576), UINT64_C(0),	// V_MSAD_U8_gfx10
    UINT64_C(3538026496), UINT64_C(0),	// V_MSAD_U8_gfx6_gfx7
    UINT64_C(3521380352), UINT64_C(0),	// V_MSAD_U8_vi
    UINT64_C(3591897088), UINT64_C(0),	// V_MULLIT_F32_e64_dpp8_gfx11
    UINT64_C(3591897088), UINT64_C(0),	// V_MULLIT_F32_e64_dpp8_gfx12
    UINT64_C(1077333721088), UINT64_C(0),	// V_MULLIT_F32_e64_dpp_gfx11
    UINT64_C(1077333721088), UINT64_C(0),	// V_MULLIT_F32_e64_dpp_gfx12
    UINT64_C(3591897088), UINT64_C(0),	// V_MULLIT_F32_e64_gfx11
    UINT64_C(3591897088), UINT64_C(0),	// V_MULLIT_F32_e64_gfx12
    UINT64_C(3578789888), UINT64_C(0),	// V_MULLIT_F32_gfx10
    UINT64_C(3533701120), UINT64_C(0),	// V_MULLIT_F32_gfx6_gfx7
    UINT64_C(234881024), UINT64_C(0),	// V_MUL_DX9_ZERO_F32_dpp8_gfx11
    UINT64_C(234881024), UINT64_C(0),	// V_MUL_DX9_ZERO_F32_dpp8_gfx12
    UINT64_C(234881274), UINT64_C(0),	// V_MUL_DX9_ZERO_F32_dpp_gfx11
    UINT64_C(234881274), UINT64_C(0),	// V_MUL_DX9_ZERO_F32_dpp_gfx12
    UINT64_C(234881024), UINT64_C(0),	// V_MUL_DX9_ZERO_F32_e32_gfx11
    UINT64_C(234881024), UINT64_C(0),	// V_MUL_DX9_ZERO_F32_e32_gfx12
    UINT64_C(3574005760), UINT64_C(0),	// V_MUL_DX9_ZERO_F32_e64_dpp8_gfx11
    UINT64_C(3574005760), UINT64_C(0),	// V_MUL_DX9_ZERO_F32_e64_dpp8_gfx12
    UINT64_C(1077315829760), UINT64_C(0),	// V_MUL_DX9_ZERO_F32_e64_dpp_gfx11
    UINT64_C(1077315829760), UINT64_C(0),	// V_MUL_DX9_ZERO_F32_e64_dpp_gfx12
    UINT64_C(3574005760), UINT64_C(0),	// V_MUL_DX9_ZERO_F32_e64_gfx11
    UINT64_C(3574005760), UINT64_C(0),	// V_MUL_DX9_ZERO_F32_e64_gfx12
    UINT64_C(1778384896), UINT64_C(0),	// V_MUL_F16_dpp8_gfx10
    UINT64_C(1778385146), UINT64_C(0),	// V_MUL_F16_dpp_gfx10
    UINT64_C(1140850938), UINT64_C(0),	// V_MUL_F16_dpp_vi
    UINT64_C(1778384896), UINT64_C(0),	// V_MUL_F16_e32_gfx10
    UINT64_C(1140850688), UINT64_C(0),	// V_MUL_F16_e32_vi
    UINT64_C(3577020416), UINT64_C(0),	// V_MUL_F16_e64_gfx10
    UINT64_C(3508666368), UINT64_C(0),	// V_MUL_F16_e64_vi
    UINT64_C(1778384896), UINT64_C(0),	// V_MUL_F16_fake16_dpp8_gfx11
    UINT64_C(1778384896), UINT64_C(0),	// V_MUL_F16_fake16_dpp8_gfx12
    UINT64_C(1778385146), UINT64_C(0),	// V_MUL_F16_fake16_dpp_gfx11
    UINT64_C(1778385146), UINT64_C(0),	// V_MUL_F16_fake16_dpp_gfx12
    UINT64_C(1778384896), UINT64_C(0),	// V_MUL_F16_fake16_e32_gfx11
    UINT64_C(1778384896), UINT64_C(0),	// V_MUL_F16_fake16_e32_gfx12
    UINT64_C(3577020416), UINT64_C(0),	// V_MUL_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3577020416), UINT64_C(0),	// V_MUL_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077318844416), UINT64_C(0),	// V_MUL_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077318844416), UINT64_C(0),	// V_MUL_F16_fake16_e64_dpp_gfx12
    UINT64_C(3577020416), UINT64_C(0),	// V_MUL_F16_fake16_e64_gfx11
    UINT64_C(3577020416), UINT64_C(0),	// V_MUL_F16_fake16_e64_gfx12
    UINT64_C(1778385145), UINT64_C(0),	// V_MUL_F16_sdwa_gfx10
    UINT64_C(1140850937), UINT64_C(0),	// V_MUL_F16_sdwa_gfx9
    UINT64_C(1140850937), UINT64_C(0),	// V_MUL_F16_sdwa_vi
    UINT64_C(1778384896), UINT64_C(0),	// V_MUL_F16_t16_dpp8_gfx11
    UINT64_C(1778384896), UINT64_C(0),	// V_MUL_F16_t16_dpp8_gfx12
    UINT64_C(1778385146), UINT64_C(0),	// V_MUL_F16_t16_dpp_gfx11
    UINT64_C(1778385146), UINT64_C(0),	// V_MUL_F16_t16_dpp_gfx12
    UINT64_C(1778384896), UINT64_C(0),	// V_MUL_F16_t16_e32_gfx11
    UINT64_C(1778384896), UINT64_C(0),	// V_MUL_F16_t16_e32_gfx12
    UINT64_C(3577020416), UINT64_C(0),	// V_MUL_F16_t16_e64_dpp8_gfx11
    UINT64_C(3577020416), UINT64_C(0),	// V_MUL_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077318844416), UINT64_C(0),	// V_MUL_F16_t16_e64_dpp_gfx11
    UINT64_C(1077318844416), UINT64_C(0),	// V_MUL_F16_t16_e64_dpp_gfx12
    UINT64_C(3577020416), UINT64_C(0),	// V_MUL_F16_t16_e64_gfx11
    UINT64_C(3577020416), UINT64_C(0),	// V_MUL_F16_t16_e64_gfx12
    UINT64_C(268435456), UINT64_C(0),	// V_MUL_F32_dpp8_gfx10
    UINT64_C(268435456), UINT64_C(0),	// V_MUL_F32_dpp8_gfx11
    UINT64_C(268435456), UINT64_C(0),	// V_MUL_F32_dpp8_gfx12
    UINT64_C(268435706), UINT64_C(0),	// V_MUL_F32_dpp_gfx10
    UINT64_C(268435706), UINT64_C(0),	// V_MUL_F32_dpp_gfx11
    UINT64_C(268435706), UINT64_C(0),	// V_MUL_F32_dpp_gfx12
    UINT64_C(167772410), UINT64_C(0),	// V_MUL_F32_dpp_vi
    UINT64_C(268435456), UINT64_C(0),	// V_MUL_F32_e32_gfx10
    UINT64_C(268435456), UINT64_C(0),	// V_MUL_F32_e32_gfx11
    UINT64_C(268435456), UINT64_C(0),	// V_MUL_F32_e32_gfx12
    UINT64_C(268435456), UINT64_C(0),	// V_MUL_F32_e32_gfx6_gfx7
    UINT64_C(167772160), UINT64_C(0),	// V_MUL_F32_e32_vi
    UINT64_C(3574071296), UINT64_C(0),	// V_MUL_F32_e64_dpp8_gfx11
    UINT64_C(3574071296), UINT64_C(0),	// V_MUL_F32_e64_dpp8_gfx12
    UINT64_C(1077315895296), UINT64_C(0),	// V_MUL_F32_e64_dpp_gfx11
    UINT64_C(1077315895296), UINT64_C(0),	// V_MUL_F32_e64_dpp_gfx12
    UINT64_C(3574071296), UINT64_C(0),	// V_MUL_F32_e64_gfx10
    UINT64_C(3574071296), UINT64_C(0),	// V_MUL_F32_e64_gfx11
    UINT64_C(3574071296), UINT64_C(0),	// V_MUL_F32_e64_gfx12
    UINT64_C(3524263936), UINT64_C(0),	// V_MUL_F32_e64_gfx6_gfx7
    UINT64_C(3506765824), UINT64_C(0),	// V_MUL_F32_e64_vi
    UINT64_C(268435705), UINT64_C(0),	// V_MUL_F32_sdwa_gfx10
    UINT64_C(167772409), UINT64_C(0),	// V_MUL_F32_sdwa_gfx9
    UINT64_C(167772409), UINT64_C(0),	// V_MUL_F32_sdwa_vi
    UINT64_C(201326842), UINT64_C(0),	// V_MUL_F64_dpp_gfx12
    UINT64_C(201326592), UINT64_C(0),	// V_MUL_F64_e32_gfx12
    UINT64_C(1077315764224), UINT64_C(0),	// V_MUL_F64_e64_dpp_gfx12
    UINT64_C(3609722880), UINT64_C(0),	// V_MUL_F64_e64_gfx11
    UINT64_C(3573940224), UINT64_C(0),	// V_MUL_F64_e64_gfx12
    UINT64_C(3580166144), UINT64_C(0),	// V_MUL_F64_gfx10
    UINT64_C(3536453632), UINT64_C(0),	// V_MUL_F64_gfx6_gfx7
    UINT64_C(3531669504), UINT64_C(0),	// V_MUL_F64_vi
    UINT64_C(335544320), UINT64_C(0),	// V_MUL_HI_I32_I24_dpp8_gfx10
    UINT64_C(335544320), UINT64_C(0),	// V_MUL_HI_I32_I24_dpp8_gfx11
    UINT64_C(335544320), UINT64_C(0),	// V_MUL_HI_I32_I24_dpp8_gfx12
    UINT64_C(335544570), UINT64_C(0),	// V_MUL_HI_I32_I24_dpp_gfx10
    UINT64_C(335544570), UINT64_C(0),	// V_MUL_HI_I32_I24_dpp_gfx11
    UINT64_C(335544570), UINT64_C(0),	// V_MUL_HI_I32_I24_dpp_gfx12
    UINT64_C(234881274), UINT64_C(0),	// V_MUL_HI_I32_I24_dpp_vi
    UINT64_C(335544320), UINT64_C(0),	// V_MUL_HI_I32_I24_e32_gfx10
    UINT64_C(335544320), UINT64_C(0),	// V_MUL_HI_I32_I24_e32_gfx11
    UINT64_C(335544320), UINT64_C(0),	// V_MUL_HI_I32_I24_e32_gfx12
    UINT64_C(335544320), UINT64_C(0),	// V_MUL_HI_I32_I24_e32_gfx6_gfx7
    UINT64_C(234881024), UINT64_C(0),	// V_MUL_HI_I32_I24_e32_vi
    UINT64_C(3574202368), UINT64_C(0),	// V_MUL_HI_I32_I24_e64_dpp8_gfx11
    UINT64_C(3574202368), UINT64_C(0),	// V_MUL_HI_I32_I24_e64_dpp8_gfx12
    UINT64_C(1077316026368), UINT64_C(0),	// V_MUL_HI_I32_I24_e64_dpp_gfx11
    UINT64_C(1077316026368), UINT64_C(0),	// V_MUL_HI_I32_I24_e64_dpp_gfx12
    UINT64_C(3574202368), UINT64_C(0),	// V_MUL_HI_I32_I24_e64_gfx10
    UINT64_C(3574202368), UINT64_C(0),	// V_MUL_HI_I32_I24_e64_gfx11
    UINT64_C(3574202368), UINT64_C(0),	// V_MUL_HI_I32_I24_e64_gfx12
    UINT64_C(3524526080), UINT64_C(0),	// V_MUL_HI_I32_I24_e64_gfx6_gfx7
    UINT64_C(3506896896), UINT64_C(0),	// V_MUL_HI_I32_I24_e64_vi
    UINT64_C(335544569), UINT64_C(0),	// V_MUL_HI_I32_I24_sdwa_gfx10
    UINT64_C(234881273), UINT64_C(0),	// V_MUL_HI_I32_I24_sdwa_gfx9
    UINT64_C(234881273), UINT64_C(0),	// V_MUL_HI_I32_I24_sdwa_vi
    UINT64_C(1077351940096), UINT64_C(0),	// V_MUL_HI_I32_e64_dpp_gfx1250
    UINT64_C(3610116096), UINT64_C(0),	// V_MUL_HI_I32_e64_gfx11
    UINT64_C(3610116096), UINT64_C(0),	// V_MUL_HI_I32_e64_gfx12
    UINT64_C(3610116096), UINT64_C(0),	// V_MUL_HI_I32_e64_gfx1250
    UINT64_C(3580624896), UINT64_C(0),	// V_MUL_HI_I32_gfx10
    UINT64_C(3537371136), UINT64_C(0),	// V_MUL_HI_I32_gfx6_gfx7
    UINT64_C(3532062720), UINT64_C(0),	// V_MUL_HI_I32_vi
    UINT64_C(402653184), UINT64_C(0),	// V_MUL_HI_U32_U24_dpp8_gfx10
    UINT64_C(402653184), UINT64_C(0),	// V_MUL_HI_U32_U24_dpp8_gfx11
    UINT64_C(402653184), UINT64_C(0),	// V_MUL_HI_U32_U24_dpp8_gfx12
    UINT64_C(402653434), UINT64_C(0),	// V_MUL_HI_U32_U24_dpp_gfx10
    UINT64_C(402653434), UINT64_C(0),	// V_MUL_HI_U32_U24_dpp_gfx11
    UINT64_C(402653434), UINT64_C(0),	// V_MUL_HI_U32_U24_dpp_gfx12
    UINT64_C(301990138), UINT64_C(0),	// V_MUL_HI_U32_U24_dpp_vi
    UINT64_C(402653184), UINT64_C(0),	// V_MUL_HI_U32_U24_e32_gfx10
    UINT64_C(402653184), UINT64_C(0),	// V_MUL_HI_U32_U24_e32_gfx11
    UINT64_C(402653184), UINT64_C(0),	// V_MUL_HI_U32_U24_e32_gfx12
    UINT64_C(402653184), UINT64_C(0),	// V_MUL_HI_U32_U24_e32_gfx6_gfx7
    UINT64_C(301989888), UINT64_C(0),	// V_MUL_HI_U32_U24_e32_vi
    UINT64_C(3574333440), UINT64_C(0),	// V_MUL_HI_U32_U24_e64_dpp8_gfx11
    UINT64_C(3574333440), UINT64_C(0),	// V_MUL_HI_U32_U24_e64_dpp8_gfx12
    UINT64_C(1077316157440), UINT64_C(0),	// V_MUL_HI_U32_U24_e64_dpp_gfx11
    UINT64_C(1077316157440), UINT64_C(0),	// V_MUL_HI_U32_U24_e64_dpp_gfx12
    UINT64_C(3574333440), UINT64_C(0),	// V_MUL_HI_U32_U24_e64_gfx10
    UINT64_C(3574333440), UINT64_C(0),	// V_MUL_HI_U32_U24_e64_gfx11
    UINT64_C(3574333440), UINT64_C(0),	// V_MUL_HI_U32_U24_e64_gfx12
    UINT64_C(3524788224), UINT64_C(0),	// V_MUL_HI_U32_U24_e64_gfx6_gfx7
    UINT64_C(3507027968), UINT64_C(0),	// V_MUL_HI_U32_U24_e64_vi
    UINT64_C(402653433), UINT64_C(0),	// V_MUL_HI_U32_U24_sdwa_gfx10
    UINT64_C(301990137), UINT64_C(0),	// V_MUL_HI_U32_U24_sdwa_gfx9
    UINT64_C(301990137), UINT64_C(0),	// V_MUL_HI_U32_U24_sdwa_vi
    UINT64_C(1077351874560), UINT64_C(0),	// V_MUL_HI_U32_e64_dpp_gfx1250
    UINT64_C(3610050560), UINT64_C(0),	// V_MUL_HI_U32_e64_gfx11
    UINT64_C(3610050560), UINT64_C(0),	// V_MUL_HI_U32_e64_gfx12
    UINT64_C(3610050560), UINT64_C(0),	// V_MUL_HI_U32_e64_gfx1250
    UINT64_C(3580493824), UINT64_C(0),	// V_MUL_HI_U32_gfx10
    UINT64_C(3537108992), UINT64_C(0),	// V_MUL_HI_U32_gfx6_gfx7
    UINT64_C(3531997184), UINT64_C(0),	// V_MUL_HI_U32_vi
    UINT64_C(301989888), UINT64_C(0),	// V_MUL_I32_I24_dpp8_gfx10
    UINT64_C(301989888), UINT64_C(0),	// V_MUL_I32_I24_dpp8_gfx11
    UINT64_C(301989888), UINT64_C(0),	// V_MUL_I32_I24_dpp8_gfx12
    UINT64_C(301990138), UINT64_C(0),	// V_MUL_I32_I24_dpp_gfx10
    UINT64_C(301990138), UINT64_C(0),	// V_MUL_I32_I24_dpp_gfx11
    UINT64_C(301990138), UINT64_C(0),	// V_MUL_I32_I24_dpp_gfx12
    UINT64_C(201326842), UINT64_C(0),	// V_MUL_I32_I24_dpp_vi
    UINT64_C(301989888), UINT64_C(0),	// V_MUL_I32_I24_e32_gfx10
    UINT64_C(301989888), UINT64_C(0),	// V_MUL_I32_I24_e32_gfx11
    UINT64_C(301989888), UINT64_C(0),	// V_MUL_I32_I24_e32_gfx12
    UINT64_C(301989888), UINT64_C(0),	// V_MUL_I32_I24_e32_gfx6_gfx7
    UINT64_C(201326592), UINT64_C(0),	// V_MUL_I32_I24_e32_vi
    UINT64_C(3574136832), UINT64_C(0),	// V_MUL_I32_I24_e64_dpp8_gfx11
    UINT64_C(3574136832), UINT64_C(0),	// V_MUL_I32_I24_e64_dpp8_gfx12
    UINT64_C(1077315960832), UINT64_C(0),	// V_MUL_I32_I24_e64_dpp_gfx11
    UINT64_C(1077315960832), UINT64_C(0),	// V_MUL_I32_I24_e64_dpp_gfx12
    UINT64_C(3574136832), UINT64_C(0),	// V_MUL_I32_I24_e64_gfx10
    UINT64_C(3574136832), UINT64_C(0),	// V_MUL_I32_I24_e64_gfx11
    UINT64_C(3574136832), UINT64_C(0),	// V_MUL_I32_I24_e64_gfx12
    UINT64_C(3524395008), UINT64_C(0),	// V_MUL_I32_I24_e64_gfx6_gfx7
    UINT64_C(3506831360), UINT64_C(0),	// V_MUL_I32_I24_e64_vi
    UINT64_C(301990137), UINT64_C(0),	// V_MUL_I32_I24_sdwa_gfx10
    UINT64_C(201326841), UINT64_C(0),	// V_MUL_I32_I24_sdwa_gfx9
    UINT64_C(201326841), UINT64_C(0),	// V_MUL_I32_I24_sdwa_vi
    UINT64_C(234881024), UINT64_C(0),	// V_MUL_LEGACY_F32_dpp8_gfx10
    UINT64_C(234881274), UINT64_C(0),	// V_MUL_LEGACY_F32_dpp_gfx10
    UINT64_C(134217978), UINT64_C(0),	// V_MUL_LEGACY_F32_dpp_vi
    UINT64_C(234881024), UINT64_C(0),	// V_MUL_LEGACY_F32_e32_gfx10
    UINT64_C(234881024), UINT64_C(0),	// V_MUL_LEGACY_F32_e32_gfx6_gfx7
    UINT64_C(134217728), UINT64_C(0),	// V_MUL_LEGACY_F32_e32_vi
    UINT64_C(3574005760), UINT64_C(0),	// V_MUL_LEGACY_F32_e64_gfx10
    UINT64_C(3524132864), UINT64_C(0),	// V_MUL_LEGACY_F32_e64_gfx6_gfx7
    UINT64_C(3533766656), UINT64_C(0),	// V_MUL_LEGACY_F32_e64_gfx90a
    UINT64_C(3506700288), UINT64_C(0),	// V_MUL_LEGACY_F32_e64_vi
    UINT64_C(234881273), UINT64_C(0),	// V_MUL_LEGACY_F32_sdwa_gfx10
    UINT64_C(134217977), UINT64_C(0),	// V_MUL_LEGACY_F32_sdwa_gfx9
    UINT64_C(134217977), UINT64_C(0),	// V_MUL_LEGACY_F32_sdwa_vi
    UINT64_C(3580559360), UINT64_C(0),	// V_MUL_LO_I32_gfx10
    UINT64_C(3537240064), UINT64_C(0),	// V_MUL_LO_I32_gfx6_gfx7
    UINT64_C(3531931648), UINT64_C(0),	// V_MUL_LO_I32_vi
    UINT64_C(1375731962), UINT64_C(0),	// V_MUL_LO_U16_dpp_vi
    UINT64_C(1375731712), UINT64_C(0),	// V_MUL_LO_U16_e32_vi
    UINT64_C(3509125120), UINT64_C(0),	// V_MUL_LO_U16_e64_vi
    UINT64_C(3607429120), UINT64_C(0),	// V_MUL_LO_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3607429120), UINT64_C(0),	// V_MUL_LO_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077349253120), UINT64_C(0),	// V_MUL_LO_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077349253120), UINT64_C(0),	// V_MUL_LO_U16_fake16_e64_dpp_gfx12
    UINT64_C(3607429120), UINT64_C(0),	// V_MUL_LO_U16_fake16_e64_gfx11
    UINT64_C(3607429120), UINT64_C(0),	// V_MUL_LO_U16_fake16_e64_gfx12
    UINT64_C(3607429120), UINT64_C(0),	// V_MUL_LO_U16_gfx10
    UINT64_C(1375731961), UINT64_C(0),	// V_MUL_LO_U16_sdwa_gfx9
    UINT64_C(1375731961), UINT64_C(0),	// V_MUL_LO_U16_sdwa_vi
    UINT64_C(3607429120), UINT64_C(0),	// V_MUL_LO_U16_t16_e64_dpp8_gfx11
    UINT64_C(3607429120), UINT64_C(0),	// V_MUL_LO_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077349253120), UINT64_C(0),	// V_MUL_LO_U16_t16_e64_dpp_gfx11
    UINT64_C(1077349253120), UINT64_C(0),	// V_MUL_LO_U16_t16_e64_dpp_gfx12
    UINT64_C(3607429120), UINT64_C(0),	// V_MUL_LO_U16_t16_e64_gfx11
    UINT64_C(3607429120), UINT64_C(0),	// V_MUL_LO_U16_t16_e64_gfx12
    UINT64_C(1077351809024), UINT64_C(0),	// V_MUL_LO_U32_e64_dpp_gfx1250
    UINT64_C(3609985024), UINT64_C(0),	// V_MUL_LO_U32_e64_gfx11
    UINT64_C(3609985024), UINT64_C(0),	// V_MUL_LO_U32_e64_gfx12
    UINT64_C(3609985024), UINT64_C(0),	// V_MUL_LO_U32_e64_gfx1250
    UINT64_C(3580428288), UINT64_C(0),	// V_MUL_LO_U32_gfx10
    UINT64_C(3536977920), UINT64_C(0),	// V_MUL_LO_U32_gfx6_gfx7
    UINT64_C(3531931648), UINT64_C(0),	// V_MUL_LO_U32_vi
    UINT64_C(369098752), UINT64_C(0),	// V_MUL_U32_U24_dpp8_gfx10
    UINT64_C(369098752), UINT64_C(0),	// V_MUL_U32_U24_dpp8_gfx11
    UINT64_C(369098752), UINT64_C(0),	// V_MUL_U32_U24_dpp8_gfx12
    UINT64_C(369099002), UINT64_C(0),	// V_MUL_U32_U24_dpp_gfx10
    UINT64_C(369099002), UINT64_C(0),	// V_MUL_U32_U24_dpp_gfx11
    UINT64_C(369099002), UINT64_C(0),	// V_MUL_U32_U24_dpp_gfx12
    UINT64_C(268435706), UINT64_C(0),	// V_MUL_U32_U24_dpp_vi
    UINT64_C(369098752), UINT64_C(0),	// V_MUL_U32_U24_e32_gfx10
    UINT64_C(369098752), UINT64_C(0),	// V_MUL_U32_U24_e32_gfx11
    UINT64_C(369098752), UINT64_C(0),	// V_MUL_U32_U24_e32_gfx12
    UINT64_C(369098752), UINT64_C(0),	// V_MUL_U32_U24_e32_gfx6_gfx7
    UINT64_C(268435456), UINT64_C(0),	// V_MUL_U32_U24_e32_vi
    UINT64_C(3574267904), UINT64_C(0),	// V_MUL_U32_U24_e64_dpp8_gfx11
    UINT64_C(3574267904), UINT64_C(0),	// V_MUL_U32_U24_e64_dpp8_gfx12
    UINT64_C(1077316091904), UINT64_C(0),	// V_MUL_U32_U24_e64_dpp_gfx11
    UINT64_C(1077316091904), UINT64_C(0),	// V_MUL_U32_U24_e64_dpp_gfx12
    UINT64_C(3574267904), UINT64_C(0),	// V_MUL_U32_U24_e64_gfx10
    UINT64_C(3574267904), UINT64_C(0),	// V_MUL_U32_U24_e64_gfx11
    UINT64_C(3574267904), UINT64_C(0),	// V_MUL_U32_U24_e64_gfx12
    UINT64_C(3524657152), UINT64_C(0),	// V_MUL_U32_U24_e64_gfx6_gfx7
    UINT64_C(3506962432), UINT64_C(0),	// V_MUL_U32_U24_e64_vi
    UINT64_C(369099001), UINT64_C(0),	// V_MUL_U32_U24_sdwa_gfx10
    UINT64_C(268435705), UINT64_C(0),	// V_MUL_U32_U24_sdwa_gfx9
    UINT64_C(268435705), UINT64_C(0),	// V_MUL_U32_U24_sdwa_vi
    UINT64_C(1409286144), UINT64_C(0),	// V_MUL_U64_e32_gfx1250
    UINT64_C(3576299520), UINT64_C(0),	// V_MUL_U64_e64_gfx1250
    UINT64_C(2113929216), UINT64_C(0),	// V_NOP_dpp8_gfx10
    UINT64_C(2113929466), UINT64_C(0),	// V_NOP_dpp_gfx10
    UINT64_C(2113929466), UINT64_C(0),	// V_NOP_dpp_vi
    UINT64_C(2113929216), UINT64_C(0),	// V_NOP_e32_gfx10
    UINT64_C(2113929216), UINT64_C(0),	// V_NOP_e32_gfx11
    UINT64_C(2113929216), UINT64_C(0),	// V_NOP_e32_gfx12
    UINT64_C(2113929216), UINT64_C(0),	// V_NOP_e32_gfx6_gfx7
    UINT64_C(2113929216), UINT64_C(0),	// V_NOP_e32_vi
    UINT64_C(3581935616), UINT64_C(0),	// V_NOP_e64_gfx10
    UINT64_C(3581935616), UINT64_C(0),	// V_NOP_e64_gfx11
    UINT64_C(3581935616), UINT64_C(0),	// V_NOP_e64_gfx12
    UINT64_C(3539992576), UINT64_C(0),	// V_NOP_e64_gfx6_gfx7
    UINT64_C(3510632448), UINT64_C(0),	// V_NOP_e64_vi
    UINT64_C(2113929465), UINT64_C(0),	// V_NOP_sdwa_gfx10
    UINT64_C(2113929465), UINT64_C(0),	// V_NOP_sdwa_gfx9
    UINT64_C(2113929465), UINT64_C(0),	// V_NOP_sdwa_vi
    UINT64_C(2113982976), UINT64_C(0),	// V_NOT_B16V_NOT_B16_fake16_dpp8_gfx11
    UINT64_C(2113982976), UINT64_C(0),	// V_NOT_B16V_NOT_B16_fake16_dpp8_gfx12
    UINT64_C(2113983226), UINT64_C(0),	// V_NOT_B16V_NOT_B16_fake16_dpp_gfx11
    UINT64_C(2113983226), UINT64_C(0),	// V_NOT_B16V_NOT_B16_fake16_dpp_gfx12
    UINT64_C(2113982976), UINT64_C(0),	// V_NOT_B16V_NOT_B16_fake16_e32_gfx11
    UINT64_C(2113982976), UINT64_C(0),	// V_NOT_B16V_NOT_B16_fake16_e32_gfx12
    UINT64_C(3588816896), UINT64_C(0),	// V_NOT_B16V_NOT_B16_fake16_e64_dpp8_gfx11
    UINT64_C(3588816896), UINT64_C(0),	// V_NOT_B16V_NOT_B16_fake16_e64_dpp8_gfx12
    UINT64_C(1077330640896), UINT64_C(0),	// V_NOT_B16V_NOT_B16_fake16_e64_dpp_gfx11
    UINT64_C(1077330640896), UINT64_C(0),	// V_NOT_B16V_NOT_B16_fake16_e64_dpp_gfx12
    UINT64_C(3588816896), UINT64_C(0),	// V_NOT_B16V_NOT_B16_fake16_e64_gfx11
    UINT64_C(3588816896), UINT64_C(0),	// V_NOT_B16V_NOT_B16_fake16_e64_gfx12
    UINT64_C(2113982976), UINT64_C(0),	// V_NOT_B16V_NOT_B16_t16_dpp8_gfx11
    UINT64_C(2113982976), UINT64_C(0),	// V_NOT_B16V_NOT_B16_t16_dpp8_gfx12
    UINT64_C(2113983226), UINT64_C(0),	// V_NOT_B16V_NOT_B16_t16_dpp_gfx11
    UINT64_C(2113983226), UINT64_C(0),	// V_NOT_B16V_NOT_B16_t16_dpp_gfx12
    UINT64_C(2113982976), UINT64_C(0),	// V_NOT_B16V_NOT_B16_t16_e32_gfx11
    UINT64_C(2113982976), UINT64_C(0),	// V_NOT_B16V_NOT_B16_t16_e32_gfx12
    UINT64_C(3588816896), UINT64_C(0),	// V_NOT_B16V_NOT_B16_t16_e64_dpp8_gfx11
    UINT64_C(3588816896), UINT64_C(0),	// V_NOT_B16V_NOT_B16_t16_e64_dpp8_gfx12
    UINT64_C(1077330640896), UINT64_C(0),	// V_NOT_B16V_NOT_B16_t16_e64_dpp_gfx11
    UINT64_C(1077330640896), UINT64_C(0),	// V_NOT_B16V_NOT_B16_t16_e64_dpp_gfx12
    UINT64_C(3588816896), UINT64_C(0),	// V_NOT_B16V_NOT_B16_t16_e64_gfx11
    UINT64_C(3588816896), UINT64_C(0),	// V_NOT_B16V_NOT_B16_t16_e64_gfx12
    UINT64_C(2113957376), UINT64_C(0),	// V_NOT_B32_dpp8_gfx10
    UINT64_C(2113957376), UINT64_C(0),	// V_NOT_B32_dpp8_gfx11
    UINT64_C(2113957376), UINT64_C(0),	// V_NOT_B32_dpp8_gfx12
    UINT64_C(2113957626), UINT64_C(0),	// V_NOT_B32_dpp_gfx10
    UINT64_C(2113957626), UINT64_C(0),	// V_NOT_B32_dpp_gfx11
    UINT64_C(2113957626), UINT64_C(0),	// V_NOT_B32_dpp_gfx12
    UINT64_C(2113951482), UINT64_C(0),	// V_NOT_B32_dpp_vi
    UINT64_C(2113957376), UINT64_C(0),	// V_NOT_B32_e32_gfx10
    UINT64_C(2113957376), UINT64_C(0),	// V_NOT_B32_e32_gfx11
    UINT64_C(2113957376), UINT64_C(0),	// V_NOT_B32_e32_gfx12
    UINT64_C(2113957376), UINT64_C(0),	// V_NOT_B32_e32_gfx6_gfx7
    UINT64_C(2113951232), UINT64_C(0),	// V_NOT_B32_e32_vi
    UINT64_C(3585540096), UINT64_C(0),	// V_NOT_B32_e64_dpp8_gfx11
    UINT64_C(3585540096), UINT64_C(0),	// V_NOT_B32_e64_dpp8_gfx12
    UINT64_C(1077327364096), UINT64_C(0),	// V_NOT_B32_e64_dpp_gfx11
    UINT64_C(1077327364096), UINT64_C(0),	// V_NOT_B32_e64_dpp_gfx12
    UINT64_C(3585540096), UINT64_C(0),	// V_NOT_B32_e64_gfx10
    UINT64_C(3585540096), UINT64_C(0),	// V_NOT_B32_e64_gfx11
    UINT64_C(3585540096), UINT64_C(0),	// V_NOT_B32_e64_gfx12
    UINT64_C(3547201536), UINT64_C(0),	// V_NOT_B32_e64_gfx6_gfx7
    UINT64_C(3513450496), UINT64_C(0),	// V_NOT_B32_e64_vi
    UINT64_C(2113957625), UINT64_C(0),	// V_NOT_B32_sdwa_gfx10
    UINT64_C(2113951481), UINT64_C(0),	// V_NOT_B32_sdwa_gfx9
    UINT64_C(2113951481), UINT64_C(0),	// V_NOT_B32_sdwa_vi
    UINT64_C(3596091392), UINT64_C(0),	// V_OR3_B32_e64_dpp8_gfx11
    UINT64_C(3596091392), UINT64_C(0),	// V_OR3_B32_e64_dpp8_gfx12
    UINT64_C(1077337915392), UINT64_C(0),	// V_OR3_B32_e64_dpp_gfx11
    UINT64_C(1077337915392), UINT64_C(0),	// V_OR3_B32_e64_dpp_gfx12
    UINT64_C(3596091392), UINT64_C(0),	// V_OR3_B32_e64_gfx11
    UINT64_C(3596091392), UINT64_C(0),	// V_OR3_B32_e64_gfx12
    UINT64_C(3614572544), UINT64_C(0),	// V_OR3_B32_gfx10
    UINT64_C(3523346432), UINT64_C(0),	// V_OR3_B32_vi
    UINT64_C(3613589504), UINT64_C(0),	// V_OR_B16_fake16_e64_dpp8_gfx11
    UINT64_C(3613589504), UINT64_C(0),	// V_OR_B16_fake16_e64_dpp8_gfx12
    UINT64_C(1077355413504), UINT64_C(0),	// V_OR_B16_fake16_e64_dpp_gfx11
    UINT64_C(1077355413504), UINT64_C(0),	// V_OR_B16_fake16_e64_dpp_gfx12
    UINT64_C(3613589504), UINT64_C(0),	// V_OR_B16_fake16_e64_gfx11
    UINT64_C(3613589504), UINT64_C(0),	// V_OR_B16_fake16_e64_gfx12
    UINT64_C(3613589504), UINT64_C(0),	// V_OR_B16_t16_e64_dpp8_gfx11
    UINT64_C(3613589504), UINT64_C(0),	// V_OR_B16_t16_e64_dpp8_gfx12
    UINT64_C(1077355413504), UINT64_C(0),	// V_OR_B16_t16_e64_dpp_gfx11
    UINT64_C(1077355413504), UINT64_C(0),	// V_OR_B16_t16_e64_dpp_gfx12
    UINT64_C(3613589504), UINT64_C(0),	// V_OR_B16_t16_e64_gfx11
    UINT64_C(3613589504), UINT64_C(0),	// V_OR_B16_t16_e64_gfx12
    UINT64_C(939524096), UINT64_C(0),	// V_OR_B32_dpp8_gfx10
    UINT64_C(939524096), UINT64_C(0),	// V_OR_B32_dpp8_gfx11
    UINT64_C(939524096), UINT64_C(0),	// V_OR_B32_dpp8_gfx12
    UINT64_C(939524346), UINT64_C(0),	// V_OR_B32_dpp_gfx10
    UINT64_C(939524346), UINT64_C(0),	// V_OR_B32_dpp_gfx11
    UINT64_C(939524346), UINT64_C(0),	// V_OR_B32_dpp_gfx12
    UINT64_C(671088890), UINT64_C(0),	// V_OR_B32_dpp_vi
    UINT64_C(939524096), UINT64_C(0),	// V_OR_B32_e32_gfx10
    UINT64_C(939524096), UINT64_C(0),	// V_OR_B32_e32_gfx11
    UINT64_C(939524096), UINT64_C(0),	// V_OR_B32_e32_gfx12
    UINT64_C(939524096), UINT64_C(0),	// V_OR_B32_e32_gfx6_gfx7
    UINT64_C(671088640), UINT64_C(0),	// V_OR_B32_e32_vi
    UINT64_C(3575382016), UINT64_C(0),	// V_OR_B32_e64_dpp8_gfx11
    UINT64_C(3575382016), UINT64_C(0),	// V_OR_B32_e64_dpp8_gfx12
    UINT64_C(1077317206016), UINT64_C(0),	// V_OR_B32_e64_dpp_gfx11
    UINT64_C(1077317206016), UINT64_C(0),	// V_OR_B32_e64_dpp_gfx12
    UINT64_C(3575382016), UINT64_C(0),	// V_OR_B32_e64_gfx10
    UINT64_C(3575382016), UINT64_C(0),	// V_OR_B32_e64_gfx11
    UINT64_C(3575382016), UINT64_C(0),	// V_OR_B32_e64_gfx12
    UINT64_C(3526885376), UINT64_C(0),	// V_OR_B32_e64_gfx6_gfx7
    UINT64_C(3507748864), UINT64_C(0),	// V_OR_B32_e64_vi
    UINT64_C(939524345), UINT64_C(0),	// V_OR_B32_sdwa_gfx10
    UINT64_C(671088889), UINT64_C(0),	// V_OR_B32_sdwa_gfx9
    UINT64_C(671088889), UINT64_C(0),	// V_OR_B32_sdwa_vi
    UINT64_C(3608215552), UINT64_C(0),	// V_PACK_B32_F16V_PACK_B32_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3608215552), UINT64_C(0),	// V_PACK_B32_F16V_PACK_B32_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077350039552), UINT64_C(0),	// V_PACK_B32_F16V_PACK_B32_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077350039552), UINT64_C(0),	// V_PACK_B32_F16V_PACK_B32_F16_fake16_e64_dpp_gfx12
    UINT64_C(3608215552), UINT64_C(0),	// V_PACK_B32_F16V_PACK_B32_F16_fake16_e64_gfx11
    UINT64_C(3608215552), UINT64_C(0),	// V_PACK_B32_F16V_PACK_B32_F16_fake16_e64_gfx12
    UINT64_C(3608215552), UINT64_C(0),	// V_PACK_B32_F16V_PACK_B32_F16_t16_e64_dpp8_gfx11
    UINT64_C(3608215552), UINT64_C(0),	// V_PACK_B32_F16V_PACK_B32_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077350039552), UINT64_C(0),	// V_PACK_B32_F16V_PACK_B32_F16_t16_e64_dpp_gfx11
    UINT64_C(1077350039552), UINT64_C(0),	// V_PACK_B32_F16V_PACK_B32_F16_t16_e64_dpp_gfx12
    UINT64_C(3608215552), UINT64_C(0),	// V_PACK_B32_F16V_PACK_B32_F16_t16_e64_gfx11
    UINT64_C(3608215552), UINT64_C(0),	// V_PACK_B32_F16V_PACK_B32_F16_t16_e64_gfx12
    UINT64_C(3608215552), UINT64_C(0),	// V_PACK_B32_F16_gfx10
    UINT64_C(3533701120), UINT64_C(0),	// V_PACK_B32_F16_vi
    UINT64_C(3596288000), UINT64_C(0),	// V_PERMLANE16_B32_e64_gfx11
    UINT64_C(3596288000), UINT64_C(0),	// V_PERMLANE16_B32_e64_gfx12
    UINT64_C(3614900224), UINT64_C(0),	// V_PERMLANE16_B32_gfx10
    UINT64_C(2113966592), UINT64_C(0),	// V_PERMLANE16_SWAP_B32_e32_gfx1250
    UINT64_C(2113974784), UINT64_C(0),	// V_PERMLANE16_SWAP_B32_e32_gfx9
    UINT64_C(3586719744), UINT64_C(0),	// V_PERMLANE16_SWAP_B32_e64_gfx1250
    UINT64_C(3516465152), UINT64_C(0),	// V_PERMLANE16_SWAP_B32_e64_gfx9
    UINT64_C(3608084480), UINT64_C(0),	// V_PERMLANE16_VAR_B32_e64_gfx12
    UINT64_C(2113975296), UINT64_C(0),	// V_PERMLANE32_SWAP_B32_e32_gfx9
    UINT64_C(3516530688), UINT64_C(0),	// V_PERMLANE32_SWAP_B32_e64_gfx9
    UINT64_C(2113981952), UINT64_C(0),	// V_PERMLANE64_B32_gfx11
    UINT64_C(2113981952), UINT64_C(0),	// V_PERMLANE64_B32_gfx12
    UINT64_C(3596353536), UINT64_C(0),	// V_PERMLANEX16_B32_e64_gfx11
    UINT64_C(3596353536), UINT64_C(0),	// V_PERMLANEX16_B32_e64_gfx12
    UINT64_C(3614965760), UINT64_C(0),	// V_PERMLANEX16_B32_gfx10
    UINT64_C(3608150016), UINT64_C(0),	// V_PERMLANEX16_VAR_B32_e64_gfx12
    UINT64_C(3597664256), UINT64_C(0),	// V_PERMLANE_BCAST_B32_e64_gfx12
    UINT64_C(3597795328), UINT64_C(0),	// V_PERMLANE_DOWN_B32_e64_gfx12
    UINT64_C(3608412160), UINT64_C(0),	// V_PERMLANE_IDX_GEN_B32_e64_gfx12
    UINT64_C(3597729792), UINT64_C(0),	// V_PERMLANE_UP_B32_e64_gfx12
    UINT64_C(3597860864), UINT64_C(0),	// V_PERMLANE_XOR_B32_e64_gfx12
    UINT64_C(3594780672), UINT64_C(0),	// V_PERM_B32_e64_dpp8_gfx11
    UINT64_C(3594780672), UINT64_C(0),	// V_PERM_B32_e64_dpp8_gfx12
    UINT64_C(1077336604672), UINT64_C(0),	// V_PERM_B32_e64_dpp_gfx11
    UINT64_C(1077336604672), UINT64_C(0),	// V_PERM_B32_e64_dpp_gfx12
    UINT64_C(3594780672), UINT64_C(0),	// V_PERM_B32_e64_gfx11
    UINT64_C(3594780672), UINT64_C(0),	// V_PERM_B32_e64_gfx12
    UINT64_C(3611557888), UINT64_C(0),	// V_PERM_B32_gfx10
    UINT64_C(3521970176), UINT64_C(0),	// V_PERM_B32_vi
    UINT64_C(3594452992), UINT64_C(0),	// V_PERM_PK16_B4_U4_e64_gfx1250
    UINT64_C(3594649600), UINT64_C(0),	// V_PERM_PK16_B6_U4_e64_gfx1250
    UINT64_C(3594715136), UINT64_C(0),	// V_PERM_PK16_B8_U4_e64_gfx1250
    UINT64_C(2113943040), UINT64_C(0),	// V_PIPEFLUSH_e32_gfx10
    UINT64_C(2113943040), UINT64_C(0),	// V_PIPEFLUSH_e32_gfx11
    UINT64_C(2113943040), UINT64_C(0),	// V_PIPEFLUSH_e32_gfx12
    UINT64_C(3583705088), UINT64_C(0),	// V_PIPEFLUSH_e64_gfx10
    UINT64_C(3583705088), UINT64_C(0),	// V_PIPEFLUSH_e64_gfx11
    UINT64_C(3583705088), UINT64_C(0),	// V_PIPEFLUSH_e64_gfx12
    UINT64_C(3424845824), UINT64_C(0),	// V_PK_ADD_BF16_gfx1250
    UINT64_C(3423535104), UINT64_C(0),	// V_PK_ADD_F16_gfx10
    UINT64_C(3423535104), UINT64_C(0),	// V_PK_ADD_F16_gfx11
    UINT64_C(3423535104), UINT64_C(0),	// V_PK_ADD_F16_gfx12
    UINT64_C(3549364224), UINT64_C(0),	// V_PK_ADD_F16_vi
    UINT64_C(3425239040), UINT64_C(0),	// V_PK_ADD_F32_gfx12
    UINT64_C(3551657984), UINT64_C(0),	// V_PK_ADD_F32_vi
    UINT64_C(3422683136), UINT64_C(0),	// V_PK_ADD_I16_gfx10
    UINT64_C(3422683136), UINT64_C(0),	// V_PK_ADD_I16_gfx11
    UINT64_C(3422683136), UINT64_C(0),	// V_PK_ADD_I16_gfx12
    UINT64_C(3548512256), UINT64_C(0),	// V_PK_ADD_I16_vi
    UINT64_C(3423862784), UINT64_C(0),	// V_PK_ADD_MAX_I16_gfx1250
    UINT64_C(3423928320), UINT64_C(0),	// V_PK_ADD_MAX_U16_gfx1250
    UINT64_C(3425501184), UINT64_C(0),	// V_PK_ADD_MIN_I16_gfx1250
    UINT64_C(3425566720), UINT64_C(0),	// V_PK_ADD_MIN_U16_gfx1250
    UINT64_C(3423207424), UINT64_C(0),	// V_PK_ADD_U16_gfx10
    UINT64_C(3423207424), UINT64_C(0),	// V_PK_ADD_U16_gfx11
    UINT64_C(3423207424), UINT64_C(0),	// V_PK_ADD_U16_gfx12
    UINT64_C(3549036544), UINT64_C(0),	// V_PK_ADD_U16_vi
    UINT64_C(3422945280), UINT64_C(0),	// V_PK_ASHRREV_I16_gfx10
    UINT64_C(3422945280), UINT64_C(0),	// V_PK_ASHRREV_I16_gfx11
    UINT64_C(3422945280), UINT64_C(0),	// V_PK_ASHRREV_I16_gfx12
    UINT64_C(3548774400), UINT64_C(0),	// V_PK_ASHRREV_I16_vi
    UINT64_C(2013265920), UINT64_C(0),	// V_PK_FMAC_F16_dpp8_gfx10
    UINT64_C(2013266170), UINT64_C(0),	// V_PK_FMAC_F16_dpp_gfx10
    UINT64_C(2013266170), UINT64_C(0),	// V_PK_FMAC_F16_dpp_gfx9
    UINT64_C(2013265920), UINT64_C(0),	// V_PK_FMAC_F16_e32_gfx10
    UINT64_C(2013265920), UINT64_C(0),	// V_PK_FMAC_F16_e32_gfx11
    UINT64_C(2013265920), UINT64_C(0),	// V_PK_FMAC_F16_e32_gfx12
    UINT64_C(2013265920), UINT64_C(0),	// V_PK_FMAC_F16_e32_gfx9
    UINT64_C(2013265920), UINT64_C(0),	// V_PK_FMAC_F16_e32_vi
    UINT64_C(3510370304), UINT64_C(0),	// V_PK_FMAC_F16_e64_gfx9
    UINT64_C(2013266169), UINT64_C(0),	// V_PK_FMAC_F16_sdwa_gfx9
    UINT64_C(3423666176), UINT64_C(0),	// V_PK_FMA_BF16_gfx1250
    UINT64_C(3423469568), UINT64_C(0),	// V_PK_FMA_F16_gfx10
    UINT64_C(3423469568), UINT64_C(0),	// V_PK_FMA_F16_gfx11
    UINT64_C(3423469568), UINT64_C(0),	// V_PK_FMA_F16_gfx12
    UINT64_C(3549298688), UINT64_C(0),	// V_PK_FMA_F16_vi
    UINT64_C(3424583680), UINT64_C(0),	// V_PK_FMA_F32_gfx12
    UINT64_C(3551526912), UINT64_C(0),	// V_PK_FMA_F32_vi
    UINT64_C(3422814208), UINT64_C(0),	// V_PK_LSHLREV_B16_gfx10
    UINT64_C(3422814208), UINT64_C(0),	// V_PK_LSHLREV_B16_gfx11
    UINT64_C(3422814208), UINT64_C(0),	// V_PK_LSHLREV_B16_gfx12
    UINT64_C(3548643328), UINT64_C(0),	// V_PK_LSHLREV_B16_vi
    UINT64_C(3422879744), UINT64_C(0),	// V_PK_LSHRREV_B16_gfx10
    UINT64_C(3422879744), UINT64_C(0),	// V_PK_LSHRREV_B16_gfx11
    UINT64_C(3422879744), UINT64_C(0),	// V_PK_LSHRREV_B16_gfx12
    UINT64_C(3548708864), UINT64_C(0),	// V_PK_LSHRREV_B16_vi
    UINT64_C(3422552064), UINT64_C(0),	// V_PK_MAD_I16_gfx10
    UINT64_C(3422552064), UINT64_C(0),	// V_PK_MAD_I16_gfx11
    UINT64_C(3422552064), UINT64_C(0),	// V_PK_MAD_I16_gfx12
    UINT64_C(3548381184), UINT64_C(0),	// V_PK_MAD_I16_vi
    UINT64_C(3423141888), UINT64_C(0),	// V_PK_MAD_U16_gfx10
    UINT64_C(3423141888), UINT64_C(0),	// V_PK_MAD_U16_gfx11
    UINT64_C(3423141888), UINT64_C(0),	// V_PK_MAD_U16_gfx12
    UINT64_C(3548971008), UINT64_C(0),	// V_PK_MAD_U16_vi
    UINT64_C(3425632256), UINT64_C(0),	// V_PK_MAX3_I16_gfx1250
    UINT64_C(3426287616), UINT64_C(0),	// V_PK_MAX3_NUM_F16_gfx1250
    UINT64_C(3425697792), UINT64_C(0),	// V_PK_MAX3_U16_gfx1250
    UINT64_C(3426156544), UINT64_C(0),	// V_PK_MAXIMUM3_F16_gfx1250
    UINT64_C(3550216192), UINT64_C(0),	// V_PK_MAXIMUM3_F16_vi
    UINT64_C(3424518144), UINT64_C(0),	// V_PK_MAXIMUM_F16_gfx12
    UINT64_C(3423731712), UINT64_C(0),	// V_PK_MAX_F16_gfx10
    UINT64_C(3423731712), UINT64_C(0),	// V_PK_MAX_F16_gfx11
    UINT64_C(3549560832), UINT64_C(0),	// V_PK_MAX_F16_vi
    UINT64_C(3423010816), UINT64_C(0),	// V_PK_MAX_I16_gfx10
    UINT64_C(3423010816), UINT64_C(0),	// V_PK_MAX_I16_gfx11
    UINT64_C(3423010816), UINT64_C(0),	// V_PK_MAX_I16_gfx12
    UINT64_C(3548839936), UINT64_C(0),	// V_PK_MAX_I16_vi
    UINT64_C(3425435648), UINT64_C(0),	// V_PK_MAX_NUM_BF16_gfx1250
    UINT64_C(3424387072), UINT64_C(0),	// V_PK_MAX_NUM_F16_gfx12
    UINT64_C(3423338496), UINT64_C(0),	// V_PK_MAX_U16_gfx10
    UINT64_C(3423338496), UINT64_C(0),	// V_PK_MAX_U16_gfx11
    UINT64_C(3423338496), UINT64_C(0),	// V_PK_MAX_U16_gfx12
    UINT64_C(3549167616), UINT64_C(0),	// V_PK_MAX_U16_vi
    UINT64_C(3425763328), UINT64_C(0),	// V_PK_MIN3_I16_gfx1250
    UINT64_C(3426222080), UINT64_C(0),	// V_PK_MIN3_NUM_F16_gfx1250
    UINT64_C(3425828864), UINT64_C(0),	// V_PK_MIN3_U16_gfx1250
    UINT64_C(3426091008), UINT64_C(0),	// V_PK_MINIMUM3_F16_gfx1250
    UINT64_C(3550150656), UINT64_C(0),	// V_PK_MINIMUM3_F16_vi
    UINT64_C(3424452608), UINT64_C(0),	// V_PK_MINIMUM_F16_gfx12
    UINT64_C(3423666176), UINT64_C(0),	// V_PK_MIN_F16_gfx10
    UINT64_C(3423666176), UINT64_C(0),	// V_PK_MIN_F16_gfx11
    UINT64_C(3549495296), UINT64_C(0),	// V_PK_MIN_F16_vi
    UINT64_C(3423076352), UINT64_C(0),	// V_PK_MIN_I16_gfx10
    UINT64_C(3423076352), UINT64_C(0),	// V_PK_MIN_I16_gfx11
    UINT64_C(3423076352), UINT64_C(0),	// V_PK_MIN_I16_gfx12
    UINT64_C(3548905472), UINT64_C(0),	// V_PK_MIN_I16_vi
    UINT64_C(3425370112), UINT64_C(0),	// V_PK_MIN_NUM_BF16_gfx1250
    UINT64_C(3424321536), UINT64_C(0),	// V_PK_MIN_NUM_F16_gfx12
    UINT64_C(3423404032), UINT64_C(0),	// V_PK_MIN_U16_gfx10
    UINT64_C(3423404032), UINT64_C(0),	// V_PK_MIN_U16_gfx11
    UINT64_C(3423404032), UINT64_C(0),	// V_PK_MIN_U16_gfx12
    UINT64_C(3549233152), UINT64_C(0),	// V_PK_MIN_U16_vi
    UINT64_C(3551723520), UINT64_C(0),	// V_PK_MOV_B32_vi
    UINT64_C(3425304576), UINT64_C(0),	// V_PK_MUL_BF16_gfx1250
    UINT64_C(3423600640), UINT64_C(0),	// V_PK_MUL_F16_gfx10
    UINT64_C(3423600640), UINT64_C(0),	// V_PK_MUL_F16_gfx11
    UINT64_C(3423600640), UINT64_C(0),	// V_PK_MUL_F16_gfx12
    UINT64_C(3549429760), UINT64_C(0),	// V_PK_MUL_F16_vi
    UINT64_C(3425173504), UINT64_C(0),	// V_PK_MUL_F32_gfx12
    UINT64_C(3551592448), UINT64_C(0),	// V_PK_MUL_F32_vi
    UINT64_C(3422617600), UINT64_C(0),	// V_PK_MUL_LO_U16_gfx10
    UINT64_C(3422617600), UINT64_C(0),	// V_PK_MUL_LO_U16_gfx11
    UINT64_C(3422617600), UINT64_C(0),	// V_PK_MUL_LO_U16_gfx12
    UINT64_C(3548446720), UINT64_C(0),	// V_PK_MUL_LO_U16_vi
    UINT64_C(3422748672), UINT64_C(0),	// V_PK_SUB_I16_gfx10
    UINT64_C(3422748672), UINT64_C(0),	// V_PK_SUB_I16_gfx11
    UINT64_C(3422748672), UINT64_C(0),	// V_PK_SUB_I16_gfx12
    UINT64_C(3548577792), UINT64_C(0),	// V_PK_SUB_I16_vi
    UINT64_C(3423272960), UINT64_C(0),	// V_PK_SUB_U16_gfx10
    UINT64_C(3423272960), UINT64_C(0),	// V_PK_SUB_U16_gfx11
    UINT64_C(3423272960), UINT64_C(0),	// V_PK_SUB_U16_gfx12
    UINT64_C(3549102080), UINT64_C(0),	// V_PK_SUB_U16_vi
    UINT64_C(2113967616), UINT64_C(0),	// V_PRNG_B32_dpp8_gfx1250
    UINT64_C(2113967866), UINT64_C(0),	// V_PRNG_B32_dpp_gfx1250
    UINT64_C(2113974522), UINT64_C(0),	// V_PRNG_B32_dpp_gfx9
    UINT64_C(2113967616), UINT64_C(0),	// V_PRNG_B32_e32_gfx1250
    UINT64_C(2113974272), UINT64_C(0),	// V_PRNG_B32_e32_vi
    UINT64_C(3586850816), UINT64_C(0),	// V_PRNG_B32_e64_dpp8_gfx1250
    UINT64_C(1077328674816), UINT64_C(0),	// V_PRNG_B32_e64_dpp_gfx1250
    UINT64_C(3586850816), UINT64_C(0),	// V_PRNG_B32_e64_gfx1250
    UINT64_C(3516399616), UINT64_C(0),	// V_PRNG_B32_e64_vi
    UINT64_C(2113974521), UINT64_C(0),	// V_PRNG_B32_sdwa_gfx9
    UINT64_C(3594125312), UINT64_C(0),	// V_QSAD_PK_U16_U8_e64_gfx11
    UINT64_C(3594125312), UINT64_C(0),	// V_QSAD_PK_U16_U8_e64_gfx12
    UINT64_C(3581018112), UINT64_C(0),	// V_QSAD_PK_U16_U8_gfx10
    UINT64_C(3538157568), UINT64_C(0),	// V_QSAD_PK_U16_U8_gfx7
    UINT64_C(3521445888), UINT64_C(0),	// V_QSAD_PK_U16_U8_vi
    UINT64_C(2113991168), UINT64_C(0),	// V_RCP_BF16V_RCP_BF16_fake16_dpp8_gfx1250
    UINT64_C(2113991418), UINT64_C(0),	// V_RCP_BF16V_RCP_BF16_fake16_dpp_gfx1250
    UINT64_C(2113991168), UINT64_C(0),	// V_RCP_BF16V_RCP_BF16_fake16_e32_gfx1250
    UINT64_C(3589865472), UINT64_C(0),	// V_RCP_BF16V_RCP_BF16_fake16_e64_dpp8_gfx1250
    UINT64_C(1077331689472), UINT64_C(0),	// V_RCP_BF16V_RCP_BF16_fake16_e64_dpp_gfx1250
    UINT64_C(3589865472), UINT64_C(0),	// V_RCP_BF16V_RCP_BF16_fake16_e64_gfx1250
    UINT64_C(2113991168), UINT64_C(0),	// V_RCP_BF16V_RCP_BF16_t16_dpp8_gfx1250
    UINT64_C(2113991418), UINT64_C(0),	// V_RCP_BF16V_RCP_BF16_t16_dpp_gfx1250
    UINT64_C(2113991168), UINT64_C(0),	// V_RCP_BF16V_RCP_BF16_t16_e32_gfx1250
    UINT64_C(3589865472), UINT64_C(0),	// V_RCP_BF16V_RCP_BF16_t16_e64_dpp8_gfx1250
    UINT64_C(1077331689472), UINT64_C(0),	// V_RCP_BF16V_RCP_BF16_t16_e64_dpp_gfx1250
    UINT64_C(3589865472), UINT64_C(0),	// V_RCP_BF16V_RCP_BF16_t16_e64_gfx1250
    UINT64_C(2113949696), UINT64_C(0),	// V_RCP_CLAMP_F32_e32_gfx6_gfx7
    UINT64_C(3545235456), UINT64_C(0),	// V_RCP_CLAMP_F32_e64_gfx6_gfx7
    UINT64_C(2113953792), UINT64_C(0),	// V_RCP_CLAMP_F64_e32_gfx6_gfx7
    UINT64_C(3546284032), UINT64_C(0),	// V_RCP_CLAMP_F64_e64_gfx6_gfx7
    UINT64_C(2113972224), UINT64_C(0),	// V_RCP_F16_dpp8_gfx10
    UINT64_C(2113972474), UINT64_C(0),	// V_RCP_F16_dpp_gfx10
    UINT64_C(2113960698), UINT64_C(0),	// V_RCP_F16_dpp_vi
    UINT64_C(2113972224), UINT64_C(0),	// V_RCP_F16_e32_gfx10
    UINT64_C(2113960448), UINT64_C(0),	// V_RCP_F16_e32_vi
    UINT64_C(3587440640), UINT64_C(0),	// V_RCP_F16_e64_gfx10
    UINT64_C(3514630144), UINT64_C(0),	// V_RCP_F16_e64_vi
    UINT64_C(2113972224), UINT64_C(0),	// V_RCP_F16_fake16_dpp8_gfx11
    UINT64_C(2113972224), UINT64_C(0),	// V_RCP_F16_fake16_dpp8_gfx12
    UINT64_C(2113972474), UINT64_C(0),	// V_RCP_F16_fake16_dpp_gfx11
    UINT64_C(2113972474), UINT64_C(0),	// V_RCP_F16_fake16_dpp_gfx12
    UINT64_C(2113972224), UINT64_C(0),	// V_RCP_F16_fake16_e32_gfx11
    UINT64_C(2113972224), UINT64_C(0),	// V_RCP_F16_fake16_e32_gfx12
    UINT64_C(3587440640), UINT64_C(0),	// V_RCP_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3587440640), UINT64_C(0),	// V_RCP_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077329264640), UINT64_C(0),	// V_RCP_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077329264640), UINT64_C(0),	// V_RCP_F16_fake16_e64_dpp_gfx12
    UINT64_C(3587440640), UINT64_C(0),	// V_RCP_F16_fake16_e64_gfx11
    UINT64_C(3587440640), UINT64_C(0),	// V_RCP_F16_fake16_e64_gfx12
    UINT64_C(2113972473), UINT64_C(0),	// V_RCP_F16_sdwa_gfx10
    UINT64_C(2113960697), UINT64_C(0),	// V_RCP_F16_sdwa_gfx9
    UINT64_C(2113960697), UINT64_C(0),	// V_RCP_F16_sdwa_vi
    UINT64_C(2113972224), UINT64_C(0),	// V_RCP_F16_t16_dpp8_gfx11
    UINT64_C(2113972224), UINT64_C(0),	// V_RCP_F16_t16_dpp8_gfx12
    UINT64_C(2113972474), UINT64_C(0),	// V_RCP_F16_t16_dpp_gfx11
    UINT64_C(2113972474), UINT64_C(0),	// V_RCP_F16_t16_dpp_gfx12
    UINT64_C(2113972224), UINT64_C(0),	// V_RCP_F16_t16_e32_gfx11
    UINT64_C(2113972224), UINT64_C(0),	// V_RCP_F16_t16_e32_gfx12
    UINT64_C(3587440640), UINT64_C(0),	// V_RCP_F16_t16_e64_dpp8_gfx11
    UINT64_C(3587440640), UINT64_C(0),	// V_RCP_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077329264640), UINT64_C(0),	// V_RCP_F16_t16_e64_dpp_gfx11
    UINT64_C(1077329264640), UINT64_C(0),	// V_RCP_F16_t16_e64_dpp_gfx12
    UINT64_C(3587440640), UINT64_C(0),	// V_RCP_F16_t16_e64_gfx11
    UINT64_C(3587440640), UINT64_C(0),	// V_RCP_F16_t16_e64_gfx12
    UINT64_C(2113950720), UINT64_C(0),	// V_RCP_F32_dpp8_gfx10
    UINT64_C(2113950720), UINT64_C(0),	// V_RCP_F32_dpp8_gfx11
    UINT64_C(2113950720), UINT64_C(0),	// V_RCP_F32_dpp8_gfx12
    UINT64_C(2113950970), UINT64_C(0),	// V_RCP_F32_dpp_gfx10
    UINT64_C(2113950970), UINT64_C(0),	// V_RCP_F32_dpp_gfx11
    UINT64_C(2113950970), UINT64_C(0),	// V_RCP_F32_dpp_gfx12
    UINT64_C(2113946874), UINT64_C(0),	// V_RCP_F32_dpp_vi
    UINT64_C(2113950720), UINT64_C(0),	// V_RCP_F32_e32_gfx10
    UINT64_C(2113950720), UINT64_C(0),	// V_RCP_F32_e32_gfx11
    UINT64_C(2113950720), UINT64_C(0),	// V_RCP_F32_e32_gfx12
    UINT64_C(2113950720), UINT64_C(0),	// V_RCP_F32_e32_gfx6_gfx7
    UINT64_C(2113946624), UINT64_C(0),	// V_RCP_F32_e32_vi
    UINT64_C(3584688128), UINT64_C(0),	// V_RCP_F32_e64_dpp8_gfx11
    UINT64_C(3584688128), UINT64_C(0),	// V_RCP_F32_e64_dpp8_gfx12
    UINT64_C(1077326512128), UINT64_C(0),	// V_RCP_F32_e64_dpp_gfx11
    UINT64_C(1077326512128), UINT64_C(0),	// V_RCP_F32_e64_dpp_gfx12
    UINT64_C(3584688128), UINT64_C(0),	// V_RCP_F32_e64_gfx10
    UINT64_C(3584688128), UINT64_C(0),	// V_RCP_F32_e64_gfx11
    UINT64_C(3584688128), UINT64_C(0),	// V_RCP_F32_e64_gfx12
    UINT64_C(3545497600), UINT64_C(0),	// V_RCP_F32_e64_gfx6_gfx7
    UINT64_C(3512860672), UINT64_C(0),	// V_RCP_F32_e64_vi
    UINT64_C(2113950969), UINT64_C(0),	// V_RCP_F32_sdwa_gfx10
    UINT64_C(2113946873), UINT64_C(0),	// V_RCP_F32_sdwa_gfx9
    UINT64_C(2113946873), UINT64_C(0),	// V_RCP_F32_sdwa_vi
    UINT64_C(2113948410), UINT64_C(0),	// V_RCP_F64_dpp_vi
    UINT64_C(2113953280), UINT64_C(0),	// V_RCP_F64_e32_gfx10
    UINT64_C(2113953280), UINT64_C(0),	// V_RCP_F64_e32_gfx11
    UINT64_C(2113953280), UINT64_C(0),	// V_RCP_F64_e32_gfx12
    UINT64_C(2113953280), UINT64_C(0),	// V_RCP_F64_e32_gfx6_gfx7
    UINT64_C(2113948160), UINT64_C(0),	// V_RCP_F64_e32_vi
    UINT64_C(3585015808), UINT64_C(0),	// V_RCP_F64_e64_gfx10
    UINT64_C(3585015808), UINT64_C(0),	// V_RCP_F64_e64_gfx11
    UINT64_C(3585015808), UINT64_C(0),	// V_RCP_F64_e64_gfx12
    UINT64_C(3546152960), UINT64_C(0),	// V_RCP_F64_e64_gfx6_gfx7
    UINT64_C(3513057280), UINT64_C(0),	// V_RCP_F64_e64_vi
    UINT64_C(2113951232), UINT64_C(0),	// V_RCP_IFLAG_F32_dpp8_gfx10
    UINT64_C(2113951232), UINT64_C(0),	// V_RCP_IFLAG_F32_dpp8_gfx11
    UINT64_C(2113951232), UINT64_C(0),	// V_RCP_IFLAG_F32_dpp8_gfx12
    UINT64_C(2113951482), UINT64_C(0),	// V_RCP_IFLAG_F32_dpp_gfx10
    UINT64_C(2113951482), UINT64_C(0),	// V_RCP_IFLAG_F32_dpp_gfx11
    UINT64_C(2113951482), UINT64_C(0),	// V_RCP_IFLAG_F32_dpp_gfx12
    UINT64_C(2113947386), UINT64_C(0),	// V_RCP_IFLAG_F32_dpp_vi
    UINT64_C(2113951232), UINT64_C(0),	// V_RCP_IFLAG_F32_e32_gfx10
    UINT64_C(2113951232), UINT64_C(0),	// V_RCP_IFLAG_F32_e32_gfx11
    UINT64_C(2113951232), UINT64_C(0),	// V_RCP_IFLAG_F32_e32_gfx12
    UINT64_C(2113951232), UINT64_C(0),	// V_RCP_IFLAG_F32_e32_gfx6_gfx7
    UINT64_C(2113947136), UINT64_C(0),	// V_RCP_IFLAG_F32_e32_vi
    UINT64_C(3584753664), UINT64_C(0),	// V_RCP_IFLAG_F32_e64_dpp8_gfx11
    UINT64_C(3584753664), UINT64_C(0),	// V_RCP_IFLAG_F32_e64_dpp8_gfx12
    UINT64_C(1077326577664), UINT64_C(0),	// V_RCP_IFLAG_F32_e64_dpp_gfx11
    UINT64_C(1077326577664), UINT64_C(0),	// V_RCP_IFLAG_F32_e64_dpp_gfx12
    UINT64_C(3584753664), UINT64_C(0),	// V_RCP_IFLAG_F32_e64_gfx10
    UINT64_C(3584753664), UINT64_C(0),	// V_RCP_IFLAG_F32_e64_gfx11
    UINT64_C(3584753664), UINT64_C(0),	// V_RCP_IFLAG_F32_e64_gfx12
    UINT64_C(3545628672), UINT64_C(0),	// V_RCP_IFLAG_F32_e64_gfx6_gfx7
    UINT64_C(3512926208), UINT64_C(0),	// V_RCP_IFLAG_F32_e64_vi
    UINT64_C(2113951481), UINT64_C(0),	// V_RCP_IFLAG_F32_sdwa_gfx10
    UINT64_C(2113947385), UINT64_C(0),	// V_RCP_IFLAG_F32_sdwa_gfx9
    UINT64_C(2113947385), UINT64_C(0),	// V_RCP_IFLAG_F32_sdwa_vi
    UINT64_C(2113950208), UINT64_C(0),	// V_RCP_LEGACY_F32_e32_gfx6_gfx7
    UINT64_C(3545366528), UINT64_C(0),	// V_RCP_LEGACY_F32_e64_gfx6_gfx7
    UINT64_C(2113930240), UINT64_C(0),	// V_READFIRSTLANE_B32_gfx10
    UINT64_C(2113930240), UINT64_C(0),	// V_READFIRSTLANE_B32_gfx11
    UINT64_C(2113930240), UINT64_C(0),	// V_READFIRSTLANE_B32_gfx12
    UINT64_C(2113930240), UINT64_C(0),	// V_READFIRSTLANE_B32_gfx6_gfx7
    UINT64_C(2113930240), UINT64_C(0),	// V_READFIRSTLANE_B32_vi
    UINT64_C(3613392896), UINT64_C(0),	// V_READLANE_B32_e64_gfx11
    UINT64_C(3613392896), UINT64_C(0),	// V_READLANE_B32_e64_gfx12
    UINT64_C(3613392896), UINT64_C(0),	// V_READLANE_B32_gfx10
    UINT64_C(33554432), UINT64_C(0),	// V_READLANE_B32_gfx6_gfx7
    UINT64_C(3532193792), UINT64_C(0),	// V_READLANE_B32_vi
    UINT64_C(2113977344), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_fake16_dpp8_gfx11
    UINT64_C(2113977344), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_fake16_dpp8_gfx12
    UINT64_C(2113977594), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_fake16_dpp_gfx11
    UINT64_C(2113977594), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_fake16_dpp_gfx12
    UINT64_C(2113977344), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_fake16_e32_gfx11
    UINT64_C(2113977344), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_fake16_e32_gfx12
    UINT64_C(3588096000), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3588096000), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077329920000), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077329920000), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_fake16_e64_dpp_gfx12
    UINT64_C(3588096000), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_fake16_e64_gfx11
    UINT64_C(3588096000), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_fake16_e64_gfx12
    UINT64_C(2113977344), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_t16_dpp8_gfx11
    UINT64_C(2113977344), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_t16_dpp8_gfx12
    UINT64_C(2113977594), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_t16_dpp_gfx11
    UINT64_C(2113977594), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_t16_dpp_gfx12
    UINT64_C(2113977344), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_t16_e32_gfx11
    UINT64_C(2113977344), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_t16_e32_gfx12
    UINT64_C(3588096000), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_t16_e64_dpp8_gfx11
    UINT64_C(3588096000), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077329920000), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_t16_e64_dpp_gfx11
    UINT64_C(1077329920000), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_t16_e64_dpp_gfx12
    UINT64_C(3588096000), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_t16_e64_gfx11
    UINT64_C(3588096000), UINT64_C(0),	// V_RNDNE_F16V_RNDNE_F16_t16_e64_gfx12
    UINT64_C(2113977344), UINT64_C(0),	// V_RNDNE_F16_dpp8_gfx10
    UINT64_C(2113977594), UINT64_C(0),	// V_RNDNE_F16_dpp_gfx10
    UINT64_C(2113965818), UINT64_C(0),	// V_RNDNE_F16_dpp_vi
    UINT64_C(2113977344), UINT64_C(0),	// V_RNDNE_F16_e32_gfx10
    UINT64_C(2113965568), UINT64_C(0),	// V_RNDNE_F16_e32_vi
    UINT64_C(3588096000), UINT64_C(0),	// V_RNDNE_F16_e64_gfx10
    UINT64_C(3515285504), UINT64_C(0),	// V_RNDNE_F16_e64_vi
    UINT64_C(2113977593), UINT64_C(0),	// V_RNDNE_F16_sdwa_gfx10
    UINT64_C(2113965817), UINT64_C(0),	// V_RNDNE_F16_sdwa_gfx9
    UINT64_C(2113965817), UINT64_C(0),	// V_RNDNE_F16_sdwa_vi
    UINT64_C(2113947136), UINT64_C(0),	// V_RNDNE_F32_dpp8_gfx10
    UINT64_C(2113947136), UINT64_C(0),	// V_RNDNE_F32_dpp8_gfx11
    UINT64_C(2113947136), UINT64_C(0),	// V_RNDNE_F32_dpp8_gfx12
    UINT64_C(2113947386), UINT64_C(0),	// V_RNDNE_F32_dpp_gfx10
    UINT64_C(2113947386), UINT64_C(0),	// V_RNDNE_F32_dpp_gfx11
    UINT64_C(2113947386), UINT64_C(0),	// V_RNDNE_F32_dpp_gfx12
    UINT64_C(2113944826), UINT64_C(0),	// V_RNDNE_F32_dpp_vi
    UINT64_C(2113947136), UINT64_C(0),	// V_RNDNE_F32_e32_gfx10
    UINT64_C(2113947136), UINT64_C(0),	// V_RNDNE_F32_e32_gfx11
    UINT64_C(2113947136), UINT64_C(0),	// V_RNDNE_F32_e32_gfx12
    UINT64_C(2113947136), UINT64_C(0),	// V_RNDNE_F32_e32_gfx6_gfx7
    UINT64_C(2113944576), UINT64_C(0),	// V_RNDNE_F32_e32_vi
    UINT64_C(3584229376), UINT64_C(0),	// V_RNDNE_F32_e64_dpp8_gfx11
    UINT64_C(3584229376), UINT64_C(0),	// V_RNDNE_F32_e64_dpp8_gfx12
    UINT64_C(1077326053376), UINT64_C(0),	// V_RNDNE_F32_e64_dpp_gfx11
    UINT64_C(1077326053376), UINT64_C(0),	// V_RNDNE_F32_e64_dpp_gfx12
    UINT64_C(3584229376), UINT64_C(0),	// V_RNDNE_F32_e64_gfx10
    UINT64_C(3584229376), UINT64_C(0),	// V_RNDNE_F32_e64_gfx11
    UINT64_C(3584229376), UINT64_C(0),	// V_RNDNE_F32_e64_gfx12
    UINT64_C(3544580096), UINT64_C(0),	// V_RNDNE_F32_e64_gfx6_gfx7
    UINT64_C(3512598528), UINT64_C(0),	// V_RNDNE_F32_e64_vi
    UINT64_C(2113947385), UINT64_C(0),	// V_RNDNE_F32_sdwa_gfx10
    UINT64_C(2113944825), UINT64_C(0),	// V_RNDNE_F32_sdwa_gfx9
    UINT64_C(2113944825), UINT64_C(0),	// V_RNDNE_F32_sdwa_vi
    UINT64_C(2113942266), UINT64_C(0),	// V_RNDNE_F64_dpp_gfx12
    UINT64_C(2113942266), UINT64_C(0),	// V_RNDNE_F64_dpp_vi
    UINT64_C(2113942016), UINT64_C(0),	// V_RNDNE_F64_e32_gfx10
    UINT64_C(2113942016), UINT64_C(0),	// V_RNDNE_F64_e32_gfx11
    UINT64_C(2113942016), UINT64_C(0),	// V_RNDNE_F64_e32_gfx12
    UINT64_C(2113942016), UINT64_C(0),	// V_RNDNE_F64_e32_gfx7
    UINT64_C(2113942016), UINT64_C(0),	// V_RNDNE_F64_e32_vi
    UINT64_C(1077325398016), UINT64_C(0),	// V_RNDNE_F64_e64_dpp_gfx12
    UINT64_C(3583574016), UINT64_C(0),	// V_RNDNE_F64_e64_gfx10
    UINT64_C(3583574016), UINT64_C(0),	// V_RNDNE_F64_e64_gfx11
    UINT64_C(3583574016), UINT64_C(0),	// V_RNDNE_F64_e64_gfx12
    UINT64_C(3543269376), UINT64_C(0),	// V_RNDNE_F64_e64_gfx7
    UINT64_C(3512270848), UINT64_C(0),	// V_RNDNE_F64_e64_vi
    UINT64_C(2113992192), UINT64_C(0),	// V_RSQ_BF16V_RSQ_BF16_fake16_dpp8_gfx1250
    UINT64_C(2113992442), UINT64_C(0),	// V_RSQ_BF16V_RSQ_BF16_fake16_dpp_gfx1250
    UINT64_C(2113992192), UINT64_C(0),	// V_RSQ_BF16V_RSQ_BF16_fake16_e32_gfx1250
    UINT64_C(3589996544), UINT64_C(0),	// V_RSQ_BF16V_RSQ_BF16_fake16_e64_dpp8_gfx1250
    UINT64_C(1077331820544), UINT64_C(0),	// V_RSQ_BF16V_RSQ_BF16_fake16_e64_dpp_gfx1250
    UINT64_C(3589996544), UINT64_C(0),	// V_RSQ_BF16V_RSQ_BF16_fake16_e64_gfx1250
    UINT64_C(2113992192), UINT64_C(0),	// V_RSQ_BF16V_RSQ_BF16_t16_dpp8_gfx1250
    UINT64_C(2113992442), UINT64_C(0),	// V_RSQ_BF16V_RSQ_BF16_t16_dpp_gfx1250
    UINT64_C(2113992192), UINT64_C(0),	// V_RSQ_BF16V_RSQ_BF16_t16_e32_gfx1250
    UINT64_C(3589996544), UINT64_C(0),	// V_RSQ_BF16V_RSQ_BF16_t16_e64_dpp8_gfx1250
    UINT64_C(1077331820544), UINT64_C(0),	// V_RSQ_BF16V_RSQ_BF16_t16_e64_dpp_gfx1250
    UINT64_C(3589996544), UINT64_C(0),	// V_RSQ_BF16V_RSQ_BF16_t16_e64_gfx1250
    UINT64_C(2113951744), UINT64_C(0),	// V_RSQ_CLAMP_F32_e32_gfx6_gfx7
    UINT64_C(3545759744), UINT64_C(0),	// V_RSQ_CLAMP_F32_e64_gfx6_gfx7
    UINT64_C(2113954816), UINT64_C(0),	// V_RSQ_CLAMP_F64_e32_gfx6_gfx7
    UINT64_C(3546546176), UINT64_C(0),	// V_RSQ_CLAMP_F64_e64_gfx6_gfx7
    UINT64_C(2113973248), UINT64_C(0),	// V_RSQ_F16_dpp8_gfx10
    UINT64_C(2113973498), UINT64_C(0),	// V_RSQ_F16_dpp_gfx10
    UINT64_C(2113961722), UINT64_C(0),	// V_RSQ_F16_dpp_vi
    UINT64_C(2113973248), UINT64_C(0),	// V_RSQ_F16_e32_gfx10
    UINT64_C(2113961472), UINT64_C(0),	// V_RSQ_F16_e32_vi
    UINT64_C(3587571712), UINT64_C(0),	// V_RSQ_F16_e64_gfx10
    UINT64_C(3514761216), UINT64_C(0),	// V_RSQ_F16_e64_vi
    UINT64_C(2113973248), UINT64_C(0),	// V_RSQ_F16_fake16_dpp8_gfx11
    UINT64_C(2113973248), UINT64_C(0),	// V_RSQ_F16_fake16_dpp8_gfx12
    UINT64_C(2113973498), UINT64_C(0),	// V_RSQ_F16_fake16_dpp_gfx11
    UINT64_C(2113973498), UINT64_C(0),	// V_RSQ_F16_fake16_dpp_gfx12
    UINT64_C(2113973248), UINT64_C(0),	// V_RSQ_F16_fake16_e32_gfx11
    UINT64_C(2113973248), UINT64_C(0),	// V_RSQ_F16_fake16_e32_gfx12
    UINT64_C(3587571712), UINT64_C(0),	// V_RSQ_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3587571712), UINT64_C(0),	// V_RSQ_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077329395712), UINT64_C(0),	// V_RSQ_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077329395712), UINT64_C(0),	// V_RSQ_F16_fake16_e64_dpp_gfx12
    UINT64_C(3587571712), UINT64_C(0),	// V_RSQ_F16_fake16_e64_gfx11
    UINT64_C(3587571712), UINT64_C(0),	// V_RSQ_F16_fake16_e64_gfx12
    UINT64_C(2113973497), UINT64_C(0),	// V_RSQ_F16_sdwa_gfx10
    UINT64_C(2113961721), UINT64_C(0),	// V_RSQ_F16_sdwa_gfx9
    UINT64_C(2113961721), UINT64_C(0),	// V_RSQ_F16_sdwa_vi
    UINT64_C(2113973248), UINT64_C(0),	// V_RSQ_F16_t16_dpp8_gfx11
    UINT64_C(2113973248), UINT64_C(0),	// V_RSQ_F16_t16_dpp8_gfx12
    UINT64_C(2113973498), UINT64_C(0),	// V_RSQ_F16_t16_dpp_gfx11
    UINT64_C(2113973498), UINT64_C(0),	// V_RSQ_F16_t16_dpp_gfx12
    UINT64_C(2113973248), UINT64_C(0),	// V_RSQ_F16_t16_e32_gfx11
    UINT64_C(2113973248), UINT64_C(0),	// V_RSQ_F16_t16_e32_gfx12
    UINT64_C(3587571712), UINT64_C(0),	// V_RSQ_F16_t16_e64_dpp8_gfx11
    UINT64_C(3587571712), UINT64_C(0),	// V_RSQ_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077329395712), UINT64_C(0),	// V_RSQ_F16_t16_e64_dpp_gfx11
    UINT64_C(1077329395712), UINT64_C(0),	// V_RSQ_F16_t16_e64_dpp_gfx12
    UINT64_C(3587571712), UINT64_C(0),	// V_RSQ_F16_t16_e64_gfx11
    UINT64_C(3587571712), UINT64_C(0),	// V_RSQ_F16_t16_e64_gfx12
    UINT64_C(2113952768), UINT64_C(0),	// V_RSQ_F32_dpp8_gfx10
    UINT64_C(2113952768), UINT64_C(0),	// V_RSQ_F32_dpp8_gfx11
    UINT64_C(2113952768), UINT64_C(0),	// V_RSQ_F32_dpp8_gfx12
    UINT64_C(2113953018), UINT64_C(0),	// V_RSQ_F32_dpp_gfx10
    UINT64_C(2113953018), UINT64_C(0),	// V_RSQ_F32_dpp_gfx11
    UINT64_C(2113953018), UINT64_C(0),	// V_RSQ_F32_dpp_gfx12
    UINT64_C(2113947898), UINT64_C(0),	// V_RSQ_F32_dpp_vi
    UINT64_C(2113952768), UINT64_C(0),	// V_RSQ_F32_e32_gfx10
    UINT64_C(2113952768), UINT64_C(0),	// V_RSQ_F32_e32_gfx11
    UINT64_C(2113952768), UINT64_C(0),	// V_RSQ_F32_e32_gfx12
    UINT64_C(2113952768), UINT64_C(0),	// V_RSQ_F32_e32_gfx6_gfx7
    UINT64_C(2113947648), UINT64_C(0),	// V_RSQ_F32_e32_vi
    UINT64_C(3584950272), UINT64_C(0),	// V_RSQ_F32_e64_dpp8_gfx11
    UINT64_C(3584950272), UINT64_C(0),	// V_RSQ_F32_e64_dpp8_gfx12
    UINT64_C(1077326774272), UINT64_C(0),	// V_RSQ_F32_e64_dpp_gfx11
    UINT64_C(1077326774272), UINT64_C(0),	// V_RSQ_F32_e64_dpp_gfx12
    UINT64_C(3584950272), UINT64_C(0),	// V_RSQ_F32_e64_gfx10
    UINT64_C(3584950272), UINT64_C(0),	// V_RSQ_F32_e64_gfx11
    UINT64_C(3584950272), UINT64_C(0),	// V_RSQ_F32_e64_gfx12
    UINT64_C(3546021888), UINT64_C(0),	// V_RSQ_F32_e64_gfx6_gfx7
    UINT64_C(3512991744), UINT64_C(0),	// V_RSQ_F32_e64_vi
    UINT64_C(2113953017), UINT64_C(0),	// V_RSQ_F32_sdwa_gfx10
    UINT64_C(2113947897), UINT64_C(0),	// V_RSQ_F32_sdwa_gfx9
    UINT64_C(2113947897), UINT64_C(0),	// V_RSQ_F32_sdwa_vi
    UINT64_C(2113948922), UINT64_C(0),	// V_RSQ_F64_dpp_vi
    UINT64_C(2113954304), UINT64_C(0),	// V_RSQ_F64_e32_gfx10
    UINT64_C(2113954304), UINT64_C(0),	// V_RSQ_F64_e32_gfx11
    UINT64_C(2113954304), UINT64_C(0),	// V_RSQ_F64_e32_gfx12
    UINT64_C(2113954304), UINT64_C(0),	// V_RSQ_F64_e32_gfx6_gfx7
    UINT64_C(2113948672), UINT64_C(0),	// V_RSQ_F64_e32_vi
    UINT64_C(3585146880), UINT64_C(0),	// V_RSQ_F64_e64_gfx10
    UINT64_C(3585146880), UINT64_C(0),	// V_RSQ_F64_e64_gfx11
    UINT64_C(3585146880), UINT64_C(0),	// V_RSQ_F64_e64_gfx12
    UINT64_C(3546415104), UINT64_C(0),	// V_RSQ_F64_e64_gfx6_gfx7
    UINT64_C(3513122816), UINT64_C(0),	// V_RSQ_F64_e64_vi
    UINT64_C(2113952256), UINT64_C(0),	// V_RSQ_LEGACY_F32_e32_gfx6_gfx7
    UINT64_C(3545890816), UINT64_C(0),	// V_RSQ_LEGACY_F32_e64_gfx6_gfx7
    UINT64_C(3592617984), UINT64_C(0),	// V_SAD_HI_U8_e64_dpp8_gfx11
    UINT64_C(3592617984), UINT64_C(0),	// V_SAD_HI_U8_e64_dpp8_gfx12
    UINT64_C(1077334441984), UINT64_C(0),	// V_SAD_HI_U8_e64_dpp_gfx11
    UINT64_C(1077334441984), UINT64_C(0),	// V_SAD_HI_U8_e64_dpp_gfx12
    UINT64_C(3592617984), UINT64_C(0),	// V_SAD_HI_U8_e64_gfx11
    UINT64_C(3592617984), UINT64_C(0),	// V_SAD_HI_U8_e64_gfx12
    UINT64_C(3579510784), UINT64_C(0),	// V_SAD_HI_U8_gfx10
    UINT64_C(3535142912), UINT64_C(0),	// V_SAD_HI_U8_gfx6_gfx7
    UINT64_C(3520724992), UINT64_C(0),	// V_SAD_HI_U8_vi
    UINT64_C(3592683520), UINT64_C(0),	// V_SAD_U16_e64_dpp8_gfx11
    UINT64_C(3592683520), UINT64_C(0),	// V_SAD_U16_e64_dpp8_gfx12
    UINT64_C(1077334507520), UINT64_C(0),	// V_SAD_U16_e64_dpp_gfx11
    UINT64_C(1077334507520), UINT64_C(0),	// V_SAD_U16_e64_dpp_gfx12
    UINT64_C(3592683520), UINT64_C(0),	// V_SAD_U16_e64_gfx11
    UINT64_C(3592683520), UINT64_C(0),	// V_SAD_U16_e64_gfx12
    UINT64_C(3579576320), UINT64_C(0),	// V_SAD_U16_gfx10
    UINT64_C(3535273984), UINT64_C(0),	// V_SAD_U16_gfx6_gfx7
    UINT64_C(3520790528), UINT64_C(0),	// V_SAD_U16_vi
    UINT64_C(3592749056), UINT64_C(0),	// V_SAD_U32_e64_dpp8_gfx11
    UINT64_C(3592749056), UINT64_C(0),	// V_SAD_U32_e64_dpp8_gfx12
    UINT64_C(1077334573056), UINT64_C(0),	// V_SAD_U32_e64_dpp_gfx11
    UINT64_C(1077334573056), UINT64_C(0),	// V_SAD_U32_e64_dpp_gfx12
    UINT64_C(3592749056), UINT64_C(0),	// V_SAD_U32_e64_gfx11
    UINT64_C(3592749056), UINT64_C(0),	// V_SAD_U32_e64_gfx12
    UINT64_C(3579641856), UINT64_C(0),	// V_SAD_U32_gfx10
    UINT64_C(3535405056), UINT64_C(0),	// V_SAD_U32_gfx6_gfx7
    UINT64_C(3520856064), UINT64_C(0),	// V_SAD_U32_vi
    UINT64_C(3592552448), UINT64_C(0),	// V_SAD_U8_e64_dpp8_gfx11
    UINT64_C(3592552448), UINT64_C(0),	// V_SAD_U8_e64_dpp8_gfx12
    UINT64_C(1077334376448), UINT64_C(0),	// V_SAD_U8_e64_dpp_gfx11
    UINT64_C(1077334376448), UINT64_C(0),	// V_SAD_U8_e64_dpp_gfx12
    UINT64_C(3592552448), UINT64_C(0),	// V_SAD_U8_e64_gfx11
    UINT64_C(3592552448), UINT64_C(0),	// V_SAD_U8_e64_gfx12
    UINT64_C(3579445248), UINT64_C(0),	// V_SAD_U8_gfx10
    UINT64_C(3535011840), UINT64_C(0),	// V_SAD_U8_gfx6_gfx7
    UINT64_C(3520659456), UINT64_C(0),	// V_SAD_U8_vi
    UINT64_C(2113988096), UINT64_C(0),	// V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_fake16_dpp8_gfx1250
    UINT64_C(2113988346), UINT64_C(0),	// V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_fake16_dpp_gfx1250
    UINT64_C(2113988096), UINT64_C(0),	// V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_fake16_e32_gfx1250
    UINT64_C(3589472256), UINT64_C(0),	// V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_fake16_e64_dpp8_gfx1250
    UINT64_C(1077331296256), UINT64_C(0),	// V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_fake16_e64_dpp_gfx1250
    UINT64_C(3589472256), UINT64_C(0),	// V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_fake16_e64_gfx1250
    UINT64_C(2113988096), UINT64_C(0),	// V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_t16_dpp8_gfx1250
    UINT64_C(2113988346), UINT64_C(0),	// V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_t16_dpp_gfx1250
    UINT64_C(2113988096), UINT64_C(0),	// V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_t16_e32_gfx1250
    UINT64_C(3589472256), UINT64_C(0),	// V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_t16_e64_dpp8_gfx1250
    UINT64_C(1077331296256), UINT64_C(0),	// V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_t16_e64_dpp_gfx1250
    UINT64_C(3589472256), UINT64_C(0),	// V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_t16_e64_gfx1250
    UINT64_C(2113988608), UINT64_C(0),	// V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_fake16_dpp8_gfx1250
    UINT64_C(2113988858), UINT64_C(0),	// V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_fake16_dpp_gfx1250
    UINT64_C(2113988608), UINT64_C(0),	// V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_fake16_e32_gfx1250
    UINT64_C(3589537792), UINT64_C(0),	// V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_fake16_e64_dpp8_gfx1250
    UINT64_C(1077331361792), UINT64_C(0),	// V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_fake16_e64_dpp_gfx1250
    UINT64_C(3589537792), UINT64_C(0),	// V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_fake16_e64_gfx1250
    UINT64_C(2113988608), UINT64_C(0),	// V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_t16_dpp8_gfx1250
    UINT64_C(2113988858), UINT64_C(0),	// V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_t16_dpp_gfx1250
    UINT64_C(2113988608), UINT64_C(0),	// V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_t16_e32_gfx1250
    UINT64_C(3589537792), UINT64_C(0),	// V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_t16_e64_dpp8_gfx1250
    UINT64_C(1077331361792), UINT64_C(0),	// V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_t16_e64_dpp_gfx1250
    UINT64_C(3589537792), UINT64_C(0),	// V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_t16_e64_gfx1250
    UINT64_C(2113979392), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_dpp8_gfx11
    UINT64_C(2113979392), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_dpp8_gfx12
    UINT64_C(2113979642), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_dpp_gfx11
    UINT64_C(2113979642), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_dpp_gfx12
    UINT64_C(2113979392), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e32_gfx11
    UINT64_C(2113979392), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e32_gfx12
    UINT64_C(3588358144), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3588358144), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077330182144), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077330182144), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e64_dpp_gfx12
    UINT64_C(3588358144), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e64_gfx11
    UINT64_C(3588358144), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e64_gfx12
    UINT64_C(2113979392), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_dpp8_gfx11
    UINT64_C(2113979392), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_dpp8_gfx12
    UINT64_C(2113979642), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_dpp_gfx11
    UINT64_C(2113979642), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_dpp_gfx12
    UINT64_C(2113979392), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e32_gfx11
    UINT64_C(2113979392), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e32_gfx12
    UINT64_C(3588358144), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e64_dpp8_gfx11
    UINT64_C(3588358144), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077330182144), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e64_dpp_gfx11
    UINT64_C(1077330182144), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e64_dpp_gfx12
    UINT64_C(3588358144), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e64_gfx11
    UINT64_C(3588358144), UINT64_C(0),	// V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e64_gfx12
    UINT64_C(2113979392), UINT64_C(0),	// V_SAT_PK_U8_I16_dpp8_gfx10
    UINT64_C(2113979642), UINT64_C(0),	// V_SAT_PK_U8_I16_dpp_gfx10
    UINT64_C(2113969914), UINT64_C(0),	// V_SAT_PK_U8_I16_dpp_vi
    UINT64_C(2113979392), UINT64_C(0),	// V_SAT_PK_U8_I16_e32_gfx10
    UINT64_C(2113969664), UINT64_C(0),	// V_SAT_PK_U8_I16_e32_vi
    UINT64_C(3588358144), UINT64_C(0),	// V_SAT_PK_U8_I16_e64_gfx10
    UINT64_C(3515809792), UINT64_C(0),	// V_SAT_PK_U8_I16_e64_vi
    UINT64_C(2113979641), UINT64_C(0),	// V_SAT_PK_U8_I16_sdwa_gfx10
    UINT64_C(2113969913), UINT64_C(0),	// V_SAT_PK_U8_I16_sdwa_gfx9
    UINT64_C(2113969913), UINT64_C(0),	// V_SAT_PK_U8_I16_sdwa_vi
    UINT64_C(2113957626), UINT64_C(0),	// V_SCREEN_PARTITION_4SE_B32_dpp_gfx9
    UINT64_C(2113957376), UINT64_C(0),	// V_SCREEN_PARTITION_4SE_B32_e32_vi
    UINT64_C(3514236928), UINT64_C(0),	// V_SCREEN_PARTITION_4SE_B32_e64_vi
    UINT64_C(2113957625), UINT64_C(0),	// V_SCREEN_PARTITION_4SE_B32_sdwa_gfx9
    UINT64_C(2113993728), UINT64_C(0),	// V_SIN_BF16V_SIN_BF16_fake16_dpp8_gfx1250
    UINT64_C(2113993978), UINT64_C(0),	// V_SIN_BF16V_SIN_BF16_fake16_dpp_gfx1250
    UINT64_C(2113993728), UINT64_C(0),	// V_SIN_BF16V_SIN_BF16_fake16_e32_gfx1250
    UINT64_C(3590193152), UINT64_C(0),	// V_SIN_BF16V_SIN_BF16_fake16_e64_dpp8_gfx1250
    UINT64_C(1077332017152), UINT64_C(0),	// V_SIN_BF16V_SIN_BF16_fake16_e64_dpp_gfx1250
    UINT64_C(3590193152), UINT64_C(0),	// V_SIN_BF16V_SIN_BF16_fake16_e64_gfx1250
    UINT64_C(2113993728), UINT64_C(0),	// V_SIN_BF16V_SIN_BF16_t16_dpp8_gfx1250
    UINT64_C(2113993978), UINT64_C(0),	// V_SIN_BF16V_SIN_BF16_t16_dpp_gfx1250
    UINT64_C(2113993728), UINT64_C(0),	// V_SIN_BF16V_SIN_BF16_t16_e32_gfx1250
    UINT64_C(3590193152), UINT64_C(0),	// V_SIN_BF16V_SIN_BF16_t16_e64_dpp8_gfx1250
    UINT64_C(1077332017152), UINT64_C(0),	// V_SIN_BF16V_SIN_BF16_t16_e64_dpp_gfx1250
    UINT64_C(3590193152), UINT64_C(0),	// V_SIN_BF16V_SIN_BF16_t16_e64_gfx1250
    UINT64_C(2113978368), UINT64_C(0),	// V_SIN_F16V_SIN_F16_fake16_dpp8_gfx11
    UINT64_C(2113978368), UINT64_C(0),	// V_SIN_F16V_SIN_F16_fake16_dpp8_gfx12
    UINT64_C(2113978618), UINT64_C(0),	// V_SIN_F16V_SIN_F16_fake16_dpp_gfx11
    UINT64_C(2113978618), UINT64_C(0),	// V_SIN_F16V_SIN_F16_fake16_dpp_gfx12
    UINT64_C(2113978368), UINT64_C(0),	// V_SIN_F16V_SIN_F16_fake16_e32_gfx11
    UINT64_C(2113978368), UINT64_C(0),	// V_SIN_F16V_SIN_F16_fake16_e32_gfx12
    UINT64_C(3588227072), UINT64_C(0),	// V_SIN_F16V_SIN_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3588227072), UINT64_C(0),	// V_SIN_F16V_SIN_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077330051072), UINT64_C(0),	// V_SIN_F16V_SIN_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077330051072), UINT64_C(0),	// V_SIN_F16V_SIN_F16_fake16_e64_dpp_gfx12
    UINT64_C(3588227072), UINT64_C(0),	// V_SIN_F16V_SIN_F16_fake16_e64_gfx11
    UINT64_C(3588227072), UINT64_C(0),	// V_SIN_F16V_SIN_F16_fake16_e64_gfx12
    UINT64_C(2113978368), UINT64_C(0),	// V_SIN_F16V_SIN_F16_t16_dpp8_gfx11
    UINT64_C(2113978368), UINT64_C(0),	// V_SIN_F16V_SIN_F16_t16_dpp8_gfx12
    UINT64_C(2113978618), UINT64_C(0),	// V_SIN_F16V_SIN_F16_t16_dpp_gfx11
    UINT64_C(2113978618), UINT64_C(0),	// V_SIN_F16V_SIN_F16_t16_dpp_gfx12
    UINT64_C(2113978368), UINT64_C(0),	// V_SIN_F16V_SIN_F16_t16_e32_gfx11
    UINT64_C(2113978368), UINT64_C(0),	// V_SIN_F16V_SIN_F16_t16_e32_gfx12
    UINT64_C(3588227072), UINT64_C(0),	// V_SIN_F16V_SIN_F16_t16_e64_dpp8_gfx11
    UINT64_C(3588227072), UINT64_C(0),	// V_SIN_F16V_SIN_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077330051072), UINT64_C(0),	// V_SIN_F16V_SIN_F16_t16_e64_dpp_gfx11
    UINT64_C(1077330051072), UINT64_C(0),	// V_SIN_F16V_SIN_F16_t16_e64_dpp_gfx12
    UINT64_C(3588227072), UINT64_C(0),	// V_SIN_F16V_SIN_F16_t16_e64_gfx11
    UINT64_C(3588227072), UINT64_C(0),	// V_SIN_F16V_SIN_F16_t16_e64_gfx12
    UINT64_C(2113978368), UINT64_C(0),	// V_SIN_F16_dpp8_gfx10
    UINT64_C(2113978618), UINT64_C(0),	// V_SIN_F16_dpp_gfx10
    UINT64_C(2113966842), UINT64_C(0),	// V_SIN_F16_dpp_vi
    UINT64_C(2113978368), UINT64_C(0),	// V_SIN_F16_e32_gfx10
    UINT64_C(2113966592), UINT64_C(0),	// V_SIN_F16_e32_vi
    UINT64_C(3588227072), UINT64_C(0),	// V_SIN_F16_e64_gfx10
    UINT64_C(3515416576), UINT64_C(0),	// V_SIN_F16_e64_vi
    UINT64_C(2113978617), UINT64_C(0),	// V_SIN_F16_sdwa_gfx10
    UINT64_C(2113966841), UINT64_C(0),	// V_SIN_F16_sdwa_gfx9
    UINT64_C(2113966841), UINT64_C(0),	// V_SIN_F16_sdwa_vi
    UINT64_C(2113956352), UINT64_C(0),	// V_SIN_F32_dpp8_gfx10
    UINT64_C(2113956352), UINT64_C(0),	// V_SIN_F32_dpp8_gfx11
    UINT64_C(2113956352), UINT64_C(0),	// V_SIN_F32_dpp8_gfx12
    UINT64_C(2113956602), UINT64_C(0),	// V_SIN_F32_dpp_gfx10
    UINT64_C(2113956602), UINT64_C(0),	// V_SIN_F32_dpp_gfx11
    UINT64_C(2113956602), UINT64_C(0),	// V_SIN_F32_dpp_gfx12
    UINT64_C(2113950458), UINT64_C(0),	// V_SIN_F32_dpp_vi
    UINT64_C(2113956352), UINT64_C(0),	// V_SIN_F32_e32_gfx10
    UINT64_C(2113956352), UINT64_C(0),	// V_SIN_F32_e32_gfx11
    UINT64_C(2113956352), UINT64_C(0),	// V_SIN_F32_e32_gfx12
    UINT64_C(2113956352), UINT64_C(0),	// V_SIN_F32_e32_gfx6_gfx7
    UINT64_C(2113950208), UINT64_C(0),	// V_SIN_F32_e32_vi
    UINT64_C(3585409024), UINT64_C(0),	// V_SIN_F32_e64_dpp8_gfx11
    UINT64_C(3585409024), UINT64_C(0),	// V_SIN_F32_e64_dpp8_gfx12
    UINT64_C(1077327233024), UINT64_C(0),	// V_SIN_F32_e64_dpp_gfx11
    UINT64_C(1077327233024), UINT64_C(0),	// V_SIN_F32_e64_dpp_gfx12
    UINT64_C(3585409024), UINT64_C(0),	// V_SIN_F32_e64_gfx10
    UINT64_C(3585409024), UINT64_C(0),	// V_SIN_F32_e64_gfx11
    UINT64_C(3585409024), UINT64_C(0),	// V_SIN_F32_e64_gfx12
    UINT64_C(3546939392), UINT64_C(0),	// V_SIN_F32_e64_gfx6_gfx7
    UINT64_C(3513319424), UINT64_C(0),	// V_SIN_F32_e64_vi
    UINT64_C(2113956601), UINT64_C(0),	// V_SIN_F32_sdwa_gfx10
    UINT64_C(2113950457), UINT64_C(0),	// V_SIN_F32_sdwa_gfx9
    UINT64_C(2113950457), UINT64_C(0),	// V_SIN_F32_sdwa_vi
    UINT64_C(3552247808), UINT64_C(0),	// V_SMFMAC_F32_16X16X128_BF8_BF8_gfx940
    UINT64_C(3552313344), UINT64_C(0),	// V_SMFMAC_F32_16X16X128_BF8_FP8_gfx940
    UINT64_C(3552378880), UINT64_C(0),	// V_SMFMAC_F32_16X16X128_FP8_BF8_gfx940
    UINT64_C(3552772096), UINT64_C(0),	// V_SMFMAC_F32_16X16X128_FP8_FP8_gfx940
    UINT64_C(3555065856), UINT64_C(0),	// V_SMFMAC_F32_16X16X32_BF16_gfx940
    UINT64_C(3554803712), UINT64_C(0),	// V_SMFMAC_F32_16X16X32_F16_gfx940
    UINT64_C(3552116736), UINT64_C(0),	// V_SMFMAC_F32_16X16X64_BF16_gfx940
    UINT64_C(3556245504), UINT64_C(0),	// V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940
    UINT64_C(3556311040), UINT64_C(0),	// V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940
    UINT64_C(3554279424), UINT64_C(0),	// V_SMFMAC_F32_16X16X64_F16_gfx940
    UINT64_C(3556376576), UINT64_C(0),	// V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940
    UINT64_C(3556442112), UINT64_C(0),	// V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940
    UINT64_C(3555196928), UINT64_C(0),	// V_SMFMAC_F32_32X32X16_BF16_gfx940
    UINT64_C(3554934784), UINT64_C(0),	// V_SMFMAC_F32_32X32X16_F16_gfx940
    UINT64_C(3552968704), UINT64_C(0),	// V_SMFMAC_F32_32X32X32_BF16_gfx940
    UINT64_C(3556507648), UINT64_C(0),	// V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940
    UINT64_C(3556573184), UINT64_C(0),	// V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940
    UINT64_C(3554344960), UINT64_C(0),	// V_SMFMAC_F32_32X32X32_F16_gfx940
    UINT64_C(3556638720), UINT64_C(0),	// V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940
    UINT64_C(3556704256), UINT64_C(0),	// V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940
    UINT64_C(3553296384), UINT64_C(0),	// V_SMFMAC_F32_32X32X64_BF8_BF8_gfx940
    UINT64_C(3553492992), UINT64_C(0),	// V_SMFMAC_F32_32X32X64_BF8_FP8_gfx940
    UINT64_C(3553558528), UINT64_C(0),	// V_SMFMAC_F32_32X32X64_FP8_BF8_gfx940
    UINT64_C(3553820672), UINT64_C(0),	// V_SMFMAC_F32_32X32X64_FP8_FP8_gfx940
    UINT64_C(3552182272), UINT64_C(0),	// V_SMFMAC_I32_16X16X128_I8_gfx940
    UINT64_C(3555328000), UINT64_C(0),	// V_SMFMAC_I32_16X16X64_I8_gfx940
    UINT64_C(3555459072), UINT64_C(0),	// V_SMFMAC_I32_32X32X32_I8_gfx940
    UINT64_C(3553034240), UINT64_C(0),	// V_SMFMAC_I32_32X32X64_I8_gfx940
    UINT64_C(2113991680), UINT64_C(0),	// V_SQRT_BF16V_SQRT_BF16_fake16_dpp8_gfx1250
    UINT64_C(2113991930), UINT64_C(0),	// V_SQRT_BF16V_SQRT_BF16_fake16_dpp_gfx1250
    UINT64_C(2113991680), UINT64_C(0),	// V_SQRT_BF16V_SQRT_BF16_fake16_e32_gfx1250
    UINT64_C(3589931008), UINT64_C(0),	// V_SQRT_BF16V_SQRT_BF16_fake16_e64_dpp8_gfx1250
    UINT64_C(1077331755008), UINT64_C(0),	// V_SQRT_BF16V_SQRT_BF16_fake16_e64_dpp_gfx1250
    UINT64_C(3589931008), UINT64_C(0),	// V_SQRT_BF16V_SQRT_BF16_fake16_e64_gfx1250
    UINT64_C(2113991680), UINT64_C(0),	// V_SQRT_BF16V_SQRT_BF16_t16_dpp8_gfx1250
    UINT64_C(2113991930), UINT64_C(0),	// V_SQRT_BF16V_SQRT_BF16_t16_dpp_gfx1250
    UINT64_C(2113991680), UINT64_C(0),	// V_SQRT_BF16V_SQRT_BF16_t16_e32_gfx1250
    UINT64_C(3589931008), UINT64_C(0),	// V_SQRT_BF16V_SQRT_BF16_t16_e64_dpp8_gfx1250
    UINT64_C(1077331755008), UINT64_C(0),	// V_SQRT_BF16V_SQRT_BF16_t16_e64_dpp_gfx1250
    UINT64_C(3589931008), UINT64_C(0),	// V_SQRT_BF16V_SQRT_BF16_t16_e64_gfx1250
    UINT64_C(2113972736), UINT64_C(0),	// V_SQRT_F16_dpp8_gfx10
    UINT64_C(2113972986), UINT64_C(0),	// V_SQRT_F16_dpp_gfx10
    UINT64_C(2113961210), UINT64_C(0),	// V_SQRT_F16_dpp_vi
    UINT64_C(2113972736), UINT64_C(0),	// V_SQRT_F16_e32_gfx10
    UINT64_C(2113960960), UINT64_C(0),	// V_SQRT_F16_e32_vi
    UINT64_C(3587506176), UINT64_C(0),	// V_SQRT_F16_e64_gfx10
    UINT64_C(3514695680), UINT64_C(0),	// V_SQRT_F16_e64_vi
    UINT64_C(2113972736), UINT64_C(0),	// V_SQRT_F16_fake16_dpp8_gfx11
    UINT64_C(2113972736), UINT64_C(0),	// V_SQRT_F16_fake16_dpp8_gfx12
    UINT64_C(2113972986), UINT64_C(0),	// V_SQRT_F16_fake16_dpp_gfx11
    UINT64_C(2113972986), UINT64_C(0),	// V_SQRT_F16_fake16_dpp_gfx12
    UINT64_C(2113972736), UINT64_C(0),	// V_SQRT_F16_fake16_e32_gfx11
    UINT64_C(2113972736), UINT64_C(0),	// V_SQRT_F16_fake16_e32_gfx12
    UINT64_C(3587506176), UINT64_C(0),	// V_SQRT_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3587506176), UINT64_C(0),	// V_SQRT_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077329330176), UINT64_C(0),	// V_SQRT_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077329330176), UINT64_C(0),	// V_SQRT_F16_fake16_e64_dpp_gfx12
    UINT64_C(3587506176), UINT64_C(0),	// V_SQRT_F16_fake16_e64_gfx11
    UINT64_C(3587506176), UINT64_C(0),	// V_SQRT_F16_fake16_e64_gfx12
    UINT64_C(2113972985), UINT64_C(0),	// V_SQRT_F16_sdwa_gfx10
    UINT64_C(2113961209), UINT64_C(0),	// V_SQRT_F16_sdwa_gfx9
    UINT64_C(2113961209), UINT64_C(0),	// V_SQRT_F16_sdwa_vi
    UINT64_C(2113972736), UINT64_C(0),	// V_SQRT_F16_t16_dpp8_gfx11
    UINT64_C(2113972736), UINT64_C(0),	// V_SQRT_F16_t16_dpp8_gfx12
    UINT64_C(2113972986), UINT64_C(0),	// V_SQRT_F16_t16_dpp_gfx11
    UINT64_C(2113972986), UINT64_C(0),	// V_SQRT_F16_t16_dpp_gfx12
    UINT64_C(2113972736), UINT64_C(0),	// V_SQRT_F16_t16_e32_gfx11
    UINT64_C(2113972736), UINT64_C(0),	// V_SQRT_F16_t16_e32_gfx12
    UINT64_C(3587506176), UINT64_C(0),	// V_SQRT_F16_t16_e64_dpp8_gfx11
    UINT64_C(3587506176), UINT64_C(0),	// V_SQRT_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077329330176), UINT64_C(0),	// V_SQRT_F16_t16_e64_dpp_gfx11
    UINT64_C(1077329330176), UINT64_C(0),	// V_SQRT_F16_t16_e64_dpp_gfx12
    UINT64_C(3587506176), UINT64_C(0),	// V_SQRT_F16_t16_e64_gfx11
    UINT64_C(3587506176), UINT64_C(0),	// V_SQRT_F16_t16_e64_gfx12
    UINT64_C(2113955328), UINT64_C(0),	// V_SQRT_F32_dpp8_gfx10
    UINT64_C(2113955328), UINT64_C(0),	// V_SQRT_F32_dpp8_gfx11
    UINT64_C(2113955328), UINT64_C(0),	// V_SQRT_F32_dpp8_gfx12
    UINT64_C(2113955578), UINT64_C(0),	// V_SQRT_F32_dpp_gfx10
    UINT64_C(2113955578), UINT64_C(0),	// V_SQRT_F32_dpp_gfx11
    UINT64_C(2113955578), UINT64_C(0),	// V_SQRT_F32_dpp_gfx12
    UINT64_C(2113949434), UINT64_C(0),	// V_SQRT_F32_dpp_vi
    UINT64_C(2113955328), UINT64_C(0),	// V_SQRT_F32_e32_gfx10
    UINT64_C(2113955328), UINT64_C(0),	// V_SQRT_F32_e32_gfx11
    UINT64_C(2113955328), UINT64_C(0),	// V_SQRT_F32_e32_gfx12
    UINT64_C(2113955328), UINT64_C(0),	// V_SQRT_F32_e32_gfx6_gfx7
    UINT64_C(2113949184), UINT64_C(0),	// V_SQRT_F32_e32_vi
    UINT64_C(3585277952), UINT64_C(0),	// V_SQRT_F32_e64_dpp8_gfx11
    UINT64_C(3585277952), UINT64_C(0),	// V_SQRT_F32_e64_dpp8_gfx12
    UINT64_C(1077327101952), UINT64_C(0),	// V_SQRT_F32_e64_dpp_gfx11
    UINT64_C(1077327101952), UINT64_C(0),	// V_SQRT_F32_e64_dpp_gfx12
    UINT64_C(3585277952), UINT64_C(0),	// V_SQRT_F32_e64_gfx10
    UINT64_C(3585277952), UINT64_C(0),	// V_SQRT_F32_e64_gfx11
    UINT64_C(3585277952), UINT64_C(0),	// V_SQRT_F32_e64_gfx12
    UINT64_C(3546677248), UINT64_C(0),	// V_SQRT_F32_e64_gfx6_gfx7
    UINT64_C(3513188352), UINT64_C(0),	// V_SQRT_F32_e64_vi
    UINT64_C(2113955577), UINT64_C(0),	// V_SQRT_F32_sdwa_gfx10
    UINT64_C(2113949433), UINT64_C(0),	// V_SQRT_F32_sdwa_gfx9
    UINT64_C(2113949433), UINT64_C(0),	// V_SQRT_F32_sdwa_vi
    UINT64_C(2113949946), UINT64_C(0),	// V_SQRT_F64_dpp_vi
    UINT64_C(2113955840), UINT64_C(0),	// V_SQRT_F64_e32_gfx10
    UINT64_C(2113955840), UINT64_C(0),	// V_SQRT_F64_e32_gfx11
    UINT64_C(2113955840), UINT64_C(0),	// V_SQRT_F64_e32_gfx12
    UINT64_C(2113955840), UINT64_C(0),	// V_SQRT_F64_e32_gfx6_gfx7
    UINT64_C(2113949696), UINT64_C(0),	// V_SQRT_F64_e32_vi
    UINT64_C(3585343488), UINT64_C(0),	// V_SQRT_F64_e64_gfx10
    UINT64_C(3585343488), UINT64_C(0),	// V_SQRT_F64_e64_gfx11
    UINT64_C(3585343488), UINT64_C(0),	// V_SQRT_F64_e64_gfx12
    UINT64_C(3546808320), UINT64_C(0),	// V_SQRT_F64_e64_gfx6_gfx7
    UINT64_C(3513253888), UINT64_C(0),	// V_SQRT_F64_e64_vi
    UINT64_C(1006633210), UINT64_C(0),	// V_SUBBREV_CO_U32_dpp_gfx9
    UINT64_C(1006632960), UINT64_C(0),	// V_SUBBREV_CO_U32_e32_gfx9
    UINT64_C(3508404224), UINT64_C(0),	// V_SUBBREV_CO_U32_e64_gfx9
    UINT64_C(1006633209), UINT64_C(0),	// V_SUBBREV_CO_U32_sdwa_gfx9
    UINT64_C(1006633210), UINT64_C(0),	// V_SUBBREV_U32_dpp_vi
    UINT64_C(1409286144), UINT64_C(0),	// V_SUBBREV_U32_e32_gfx6_gfx7
    UINT64_C(1006632960), UINT64_C(0),	// V_SUBBREV_U32_e32_vi
    UINT64_C(3528720384), UINT64_C(0),	// V_SUBBREV_U32_e64_gfx6_gfx7
    UINT64_C(3508404224), UINT64_C(0),	// V_SUBBREV_U32_e64_vi
    UINT64_C(1006633209), UINT64_C(0),	// V_SUBBREV_U32_sdwa_vi
    UINT64_C(973078778), UINT64_C(0),	// V_SUBB_CO_U32_dpp_gfx9
    UINT64_C(973078528), UINT64_C(0),	// V_SUBB_CO_U32_e32_gfx9
    UINT64_C(3508338688), UINT64_C(0),	// V_SUBB_CO_U32_e64_gfx9
    UINT64_C(973078777), UINT64_C(0),	// V_SUBB_CO_U32_sdwa_gfx9
    UINT64_C(973078778), UINT64_C(0),	// V_SUBB_U32_dpp_vi
    UINT64_C(1375731712), UINT64_C(0),	// V_SUBB_U32_e32_gfx6_gfx7
    UINT64_C(973078528), UINT64_C(0),	// V_SUBB_U32_e32_vi
    UINT64_C(3528589312), UINT64_C(0),	// V_SUBB_U32_e64_gfx6_gfx7
    UINT64_C(3508338688), UINT64_C(0),	// V_SUBB_U32_e64_vi
    UINT64_C(973078777), UINT64_C(0),	// V_SUBB_U32_sdwa_vi
    UINT64_C(1409286144), UINT64_C(0),	// V_SUBREV_CO_CI_U32_dpp8_gfx10
    UINT64_C(1140850688), UINT64_C(0),	// V_SUBREV_CO_CI_U32_dpp8_gfx11
    UINT64_C(1140850688), UINT64_C(0),	// V_SUBREV_CO_CI_U32_dpp8_gfx12
    UINT64_C(1409286144), UINT64_C(0),	// V_SUBREV_CO_CI_U32_dpp8_w32_gfx10
    UINT64_C(1140850688), UINT64_C(0),	// V_SUBREV_CO_CI_U32_dpp8_w32_gfx11
    UINT64_C(1140850688), UINT64_C(0),	// V_SUBREV_CO_CI_U32_dpp8_w32_gfx12
    UINT64_C(1409286144), UINT64_C(0),	// V_SUBREV_CO_CI_U32_dpp8_w64_gfx10
    UINT64_C(1140850688), UINT64_C(0),	// V_SUBREV_CO_CI_U32_dpp8_w64_gfx11
    UINT64_C(1140850688), UINT64_C(0),	// V_SUBREV_CO_CI_U32_dpp8_w64_gfx12
    UINT64_C(1409286394), UINT64_C(0),	// V_SUBREV_CO_CI_U32_dpp_gfx10
    UINT64_C(1140850938), UINT64_C(0),	// V_SUBREV_CO_CI_U32_dpp_gfx11
    UINT64_C(1140850938), UINT64_C(0),	// V_SUBREV_CO_CI_U32_dpp_gfx12
    UINT64_C(1409286394), UINT64_C(0),	// V_SUBREV_CO_CI_U32_dpp_w32_gfx10
    UINT64_C(1140850938), UINT64_C(0),	// V_SUBREV_CO_CI_U32_dpp_w32_gfx11
    UINT64_C(1140850938), UINT64_C(0),	// V_SUBREV_CO_CI_U32_dpp_w32_gfx12
    UINT64_C(1409286394), UINT64_C(0),	// V_SUBREV_CO_CI_U32_dpp_w64_gfx10
    UINT64_C(1140850938), UINT64_C(0),	// V_SUBREV_CO_CI_U32_dpp_w64_gfx11
    UINT64_C(1140850938), UINT64_C(0),	// V_SUBREV_CO_CI_U32_dpp_w64_gfx12
    UINT64_C(1409286144), UINT64_C(0),	// V_SUBREV_CO_CI_U32_e32_gfx10
    UINT64_C(1140850688), UINT64_C(0),	// V_SUBREV_CO_CI_U32_e32_gfx11
    UINT64_C(1140850688), UINT64_C(0),	// V_SUBREV_CO_CI_U32_e32_gfx12
    UINT64_C(3575775232), UINT64_C(0),	// V_SUBREV_CO_CI_U32_e64_dpp8_gfx11
    UINT64_C(3575775232), UINT64_C(0),	// V_SUBREV_CO_CI_U32_e64_dpp8_gfx12
    UINT64_C(1077317599232), UINT64_C(0),	// V_SUBREV_CO_CI_U32_e64_dpp_gfx11
    UINT64_C(1077317599232), UINT64_C(0),	// V_SUBREV_CO_CI_U32_e64_dpp_gfx12
    UINT64_C(3576299520), UINT64_C(0),	// V_SUBREV_CO_CI_U32_e64_gfx10
    UINT64_C(3575775232), UINT64_C(0),	// V_SUBREV_CO_CI_U32_e64_gfx11
    UINT64_C(3575775232), UINT64_C(0),	// V_SUBREV_CO_CI_U32_e64_gfx12
    UINT64_C(1409286393), UINT64_C(0),	// V_SUBREV_CO_CI_U32_sdwa_gfx10
    UINT64_C(1409286393), UINT64_C(0),	// V_SUBREV_CO_CI_U32_sdwa_w32_gfx10
    UINT64_C(1409286393), UINT64_C(0),	// V_SUBREV_CO_CI_U32_sdwa_w64_gfx10
    UINT64_C(905969914), UINT64_C(0),	// V_SUBREV_CO_U32_dpp_gfx9
    UINT64_C(905969664), UINT64_C(0),	// V_SUBREV_CO_U32_e32_gfx9
    UINT64_C(3607232512), UINT64_C(0),	// V_SUBREV_CO_U32_e64_dpp8_gfx11
    UINT64_C(3607232512), UINT64_C(0),	// V_SUBREV_CO_U32_e64_dpp8_gfx12
    UINT64_C(1077349056512), UINT64_C(0),	// V_SUBREV_CO_U32_e64_dpp_gfx11
    UINT64_C(1077349056512), UINT64_C(0),	// V_SUBREV_CO_U32_e64_dpp_gfx12
    UINT64_C(3608739840), UINT64_C(0),	// V_SUBREV_CO_U32_e64_gfx10
    UINT64_C(3607232512), UINT64_C(0),	// V_SUBREV_CO_U32_e64_gfx11
    UINT64_C(3607232512), UINT64_C(0),	// V_SUBREV_CO_U32_e64_gfx12
    UINT64_C(3508207616), UINT64_C(0),	// V_SUBREV_CO_U32_e64_gfx9
    UINT64_C(905969913), UINT64_C(0),	// V_SUBREV_CO_U32_sdwa_gfx9
    UINT64_C(1744830464), UINT64_C(0),	// V_SUBREV_F16_dpp8_gfx10
    UINT64_C(1744830714), UINT64_C(0),	// V_SUBREV_F16_dpp_gfx10
    UINT64_C(1107296506), UINT64_C(0),	// V_SUBREV_F16_dpp_vi
    UINT64_C(1744830464), UINT64_C(0),	// V_SUBREV_F16_e32_gfx10
    UINT64_C(1107296256), UINT64_C(0),	// V_SUBREV_F16_e32_vi
    UINT64_C(3576954880), UINT64_C(0),	// V_SUBREV_F16_e64_gfx10
    UINT64_C(3508600832), UINT64_C(0),	// V_SUBREV_F16_e64_vi
    UINT64_C(1744830464), UINT64_C(0),	// V_SUBREV_F16_fake16_dpp8_gfx11
    UINT64_C(1744830464), UINT64_C(0),	// V_SUBREV_F16_fake16_dpp8_gfx12
    UINT64_C(1744830714), UINT64_C(0),	// V_SUBREV_F16_fake16_dpp_gfx11
    UINT64_C(1744830714), UINT64_C(0),	// V_SUBREV_F16_fake16_dpp_gfx12
    UINT64_C(1744830464), UINT64_C(0),	// V_SUBREV_F16_fake16_e32_gfx11
    UINT64_C(1744830464), UINT64_C(0),	// V_SUBREV_F16_fake16_e32_gfx12
    UINT64_C(3576954880), UINT64_C(0),	// V_SUBREV_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3576954880), UINT64_C(0),	// V_SUBREV_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077318778880), UINT64_C(0),	// V_SUBREV_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077318778880), UINT64_C(0),	// V_SUBREV_F16_fake16_e64_dpp_gfx12
    UINT64_C(3576954880), UINT64_C(0),	// V_SUBREV_F16_fake16_e64_gfx11
    UINT64_C(3576954880), UINT64_C(0),	// V_SUBREV_F16_fake16_e64_gfx12
    UINT64_C(1744830713), UINT64_C(0),	// V_SUBREV_F16_sdwa_gfx10
    UINT64_C(1107296505), UINT64_C(0),	// V_SUBREV_F16_sdwa_gfx9
    UINT64_C(1107296505), UINT64_C(0),	// V_SUBREV_F16_sdwa_vi
    UINT64_C(1744830464), UINT64_C(0),	// V_SUBREV_F16_t16_dpp8_gfx11
    UINT64_C(1744830464), UINT64_C(0),	// V_SUBREV_F16_t16_dpp8_gfx12
    UINT64_C(1744830714), UINT64_C(0),	// V_SUBREV_F16_t16_dpp_gfx11
    UINT64_C(1744830714), UINT64_C(0),	// V_SUBREV_F16_t16_dpp_gfx12
    UINT64_C(1744830464), UINT64_C(0),	// V_SUBREV_F16_t16_e32_gfx11
    UINT64_C(1744830464), UINT64_C(0),	// V_SUBREV_F16_t16_e32_gfx12
    UINT64_C(3576954880), UINT64_C(0),	// V_SUBREV_F16_t16_e64_dpp8_gfx11
    UINT64_C(3576954880), UINT64_C(0),	// V_SUBREV_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077318778880), UINT64_C(0),	// V_SUBREV_F16_t16_e64_dpp_gfx11
    UINT64_C(1077318778880), UINT64_C(0),	// V_SUBREV_F16_t16_e64_dpp_gfx12
    UINT64_C(3576954880), UINT64_C(0),	// V_SUBREV_F16_t16_e64_gfx11
    UINT64_C(3576954880), UINT64_C(0),	// V_SUBREV_F16_t16_e64_gfx12
    UINT64_C(167772160), UINT64_C(0),	// V_SUBREV_F32_dpp8_gfx10
    UINT64_C(167772160), UINT64_C(0),	// V_SUBREV_F32_dpp8_gfx11
    UINT64_C(167772160), UINT64_C(0),	// V_SUBREV_F32_dpp8_gfx12
    UINT64_C(167772410), UINT64_C(0),	// V_SUBREV_F32_dpp_gfx10
    UINT64_C(167772410), UINT64_C(0),	// V_SUBREV_F32_dpp_gfx11
    UINT64_C(167772410), UINT64_C(0),	// V_SUBREV_F32_dpp_gfx12
    UINT64_C(100663546), UINT64_C(0),	// V_SUBREV_F32_dpp_vi
    UINT64_C(167772160), UINT64_C(0),	// V_SUBREV_F32_e32_gfx10
    UINT64_C(167772160), UINT64_C(0),	// V_SUBREV_F32_e32_gfx11
    UINT64_C(167772160), UINT64_C(0),	// V_SUBREV_F32_e32_gfx12
    UINT64_C(167772160), UINT64_C(0),	// V_SUBREV_F32_e32_gfx6_gfx7
    UINT64_C(100663296), UINT64_C(0),	// V_SUBREV_F32_e32_vi
    UINT64_C(3573874688), UINT64_C(0),	// V_SUBREV_F32_e64_dpp8_gfx11
    UINT64_C(3573874688), UINT64_C(0),	// V_SUBREV_F32_e64_dpp8_gfx12
    UINT64_C(1077315698688), UINT64_C(0),	// V_SUBREV_F32_e64_dpp_gfx11
    UINT64_C(1077315698688), UINT64_C(0),	// V_SUBREV_F32_e64_dpp_gfx12
    UINT64_C(3573874688), UINT64_C(0),	// V_SUBREV_F32_e64_gfx10
    UINT64_C(3573874688), UINT64_C(0),	// V_SUBREV_F32_e64_gfx11
    UINT64_C(3573874688), UINT64_C(0),	// V_SUBREV_F32_e64_gfx12
    UINT64_C(3523870720), UINT64_C(0),	// V_SUBREV_F32_e64_gfx6_gfx7
    UINT64_C(3506634752), UINT64_C(0),	// V_SUBREV_F32_e64_vi
    UINT64_C(167772409), UINT64_C(0),	// V_SUBREV_F32_sdwa_gfx10
    UINT64_C(100663545), UINT64_C(0),	// V_SUBREV_F32_sdwa_gfx9
    UINT64_C(100663545), UINT64_C(0),	// V_SUBREV_F32_sdwa_vi
    UINT64_C(1308622848), UINT64_C(0),	// V_SUBREV_I32_e32_gfx6_gfx7
    UINT64_C(3528327168), UINT64_C(0),	// V_SUBREV_I32_e64_gfx6_gfx7
    UINT64_C(1308622848), UINT64_C(0),	// V_SUBREV_NC_U32_dpp8_gfx10
    UINT64_C(1308622848), UINT64_C(0),	// V_SUBREV_NC_U32_dpp8_gfx11
    UINT64_C(1308622848), UINT64_C(0),	// V_SUBREV_NC_U32_dpp8_gfx12
    UINT64_C(1308623098), UINT64_C(0),	// V_SUBREV_NC_U32_dpp_gfx10
    UINT64_C(1308623098), UINT64_C(0),	// V_SUBREV_NC_U32_dpp_gfx11
    UINT64_C(1308623098), UINT64_C(0),	// V_SUBREV_NC_U32_dpp_gfx12
    UINT64_C(1308622848), UINT64_C(0),	// V_SUBREV_NC_U32_e32_gfx10
    UINT64_C(1308622848), UINT64_C(0),	// V_SUBREV_NC_U32_e32_gfx11
    UINT64_C(1308622848), UINT64_C(0),	// V_SUBREV_NC_U32_e32_gfx12
    UINT64_C(3576102912), UINT64_C(0),	// V_SUBREV_NC_U32_e64_dpp8_gfx11
    UINT64_C(3576102912), UINT64_C(0),	// V_SUBREV_NC_U32_e64_dpp8_gfx12
    UINT64_C(1077317926912), UINT64_C(0),	// V_SUBREV_NC_U32_e64_dpp_gfx11
    UINT64_C(1077317926912), UINT64_C(0),	// V_SUBREV_NC_U32_e64_dpp_gfx12
    UINT64_C(3576102912), UINT64_C(0),	// V_SUBREV_NC_U32_e64_gfx10
    UINT64_C(3576102912), UINT64_C(0),	// V_SUBREV_NC_U32_e64_gfx11
    UINT64_C(3576102912), UINT64_C(0),	// V_SUBREV_NC_U32_e64_gfx12
    UINT64_C(1308623097), UINT64_C(0),	// V_SUBREV_NC_U32_sdwa_gfx10
    UINT64_C(1342177530), UINT64_C(0),	// V_SUBREV_U16_dpp_vi
    UINT64_C(1342177280), UINT64_C(0),	// V_SUBREV_U16_e32_vi
    UINT64_C(3509059584), UINT64_C(0),	// V_SUBREV_U16_e64_vi
    UINT64_C(1342177529), UINT64_C(0),	// V_SUBREV_U16_sdwa_gfx9
    UINT64_C(1342177529), UINT64_C(0),	// V_SUBREV_U16_sdwa_vi
    UINT64_C(1811939578), UINT64_C(0),	// V_SUBREV_U32_dpp_gfx9
    UINT64_C(905969914), UINT64_C(0),	// V_SUBREV_U32_dpp_vi
    UINT64_C(1811939328), UINT64_C(0),	// V_SUBREV_U32_e32_gfx9
    UINT64_C(905969664), UINT64_C(0),	// V_SUBREV_U32_e32_vi
    UINT64_C(3509977088), UINT64_C(0),	// V_SUBREV_U32_e64_gfx9
    UINT64_C(3508207616), UINT64_C(0),	// V_SUBREV_U32_e64_vi
    UINT64_C(1811939577), UINT64_C(0),	// V_SUBREV_U32_sdwa_gfx9
    UINT64_C(905969913), UINT64_C(0),	// V_SUBREV_U32_sdwa_vi
    UINT64_C(1375731712), UINT64_C(0),	// V_SUB_CO_CI_U32_dpp8_gfx10
    UINT64_C(1107296256), UINT64_C(0),	// V_SUB_CO_CI_U32_dpp8_gfx11
    UINT64_C(1107296256), UINT64_C(0),	// V_SUB_CO_CI_U32_dpp8_gfx12
    UINT64_C(1375731712), UINT64_C(0),	// V_SUB_CO_CI_U32_dpp8_w32_gfx10
    UINT64_C(1107296256), UINT64_C(0),	// V_SUB_CO_CI_U32_dpp8_w32_gfx11
    UINT64_C(1107296256), UINT64_C(0),	// V_SUB_CO_CI_U32_dpp8_w32_gfx12
    UINT64_C(1375731712), UINT64_C(0),	// V_SUB_CO_CI_U32_dpp8_w64_gfx10
    UINT64_C(1107296256), UINT64_C(0),	// V_SUB_CO_CI_U32_dpp8_w64_gfx11
    UINT64_C(1107296256), UINT64_C(0),	// V_SUB_CO_CI_U32_dpp8_w64_gfx12
    UINT64_C(1375731962), UINT64_C(0),	// V_SUB_CO_CI_U32_dpp_gfx10
    UINT64_C(1107296506), UINT64_C(0),	// V_SUB_CO_CI_U32_dpp_gfx11
    UINT64_C(1107296506), UINT64_C(0),	// V_SUB_CO_CI_U32_dpp_gfx12
    UINT64_C(1375731962), UINT64_C(0),	// V_SUB_CO_CI_U32_dpp_w32_gfx10
    UINT64_C(1107296506), UINT64_C(0),	// V_SUB_CO_CI_U32_dpp_w32_gfx11
    UINT64_C(1107296506), UINT64_C(0),	// V_SUB_CO_CI_U32_dpp_w32_gfx12
    UINT64_C(1375731962), UINT64_C(0),	// V_SUB_CO_CI_U32_dpp_w64_gfx10
    UINT64_C(1107296506), UINT64_C(0),	// V_SUB_CO_CI_U32_dpp_w64_gfx11
    UINT64_C(1107296506), UINT64_C(0),	// V_SUB_CO_CI_U32_dpp_w64_gfx12
    UINT64_C(1375731712), UINT64_C(0),	// V_SUB_CO_CI_U32_e32_gfx10
    UINT64_C(1107296256), UINT64_C(0),	// V_SUB_CO_CI_U32_e32_gfx11
    UINT64_C(1107296256), UINT64_C(0),	// V_SUB_CO_CI_U32_e32_gfx12
    UINT64_C(3575709696), UINT64_C(0),	// V_SUB_CO_CI_U32_e64_dpp8_gfx11
    UINT64_C(3575709696), UINT64_C(0),	// V_SUB_CO_CI_U32_e64_dpp8_gfx12
    UINT64_C(1077317533696), UINT64_C(0),	// V_SUB_CO_CI_U32_e64_dpp_gfx11
    UINT64_C(1077317533696), UINT64_C(0),	// V_SUB_CO_CI_U32_e64_dpp_gfx12
    UINT64_C(3576233984), UINT64_C(0),	// V_SUB_CO_CI_U32_e64_gfx10
    UINT64_C(3575709696), UINT64_C(0),	// V_SUB_CO_CI_U32_e64_gfx11
    UINT64_C(3575709696), UINT64_C(0),	// V_SUB_CO_CI_U32_e64_gfx12
    UINT64_C(1375731961), UINT64_C(0),	// V_SUB_CO_CI_U32_sdwa_gfx10
    UINT64_C(1375731961), UINT64_C(0),	// V_SUB_CO_CI_U32_sdwa_w32_gfx10
    UINT64_C(1375731961), UINT64_C(0),	// V_SUB_CO_CI_U32_sdwa_w64_gfx10
    UINT64_C(872415482), UINT64_C(0),	// V_SUB_CO_U32_dpp_gfx9
    UINT64_C(872415232), UINT64_C(0),	// V_SUB_CO_U32_e32_gfx9
    UINT64_C(3607166976), UINT64_C(0),	// V_SUB_CO_U32_e64_dpp8_gfx11
    UINT64_C(3607166976), UINT64_C(0),	// V_SUB_CO_U32_e64_dpp8_gfx12
    UINT64_C(1077348990976), UINT64_C(0),	// V_SUB_CO_U32_e64_dpp_gfx11
    UINT64_C(1077348990976), UINT64_C(0),	// V_SUB_CO_U32_e64_dpp_gfx12
    UINT64_C(3608150016), UINT64_C(0),	// V_SUB_CO_U32_e64_gfx10
    UINT64_C(3607166976), UINT64_C(0),	// V_SUB_CO_U32_e64_gfx11
    UINT64_C(3607166976), UINT64_C(0),	// V_SUB_CO_U32_e64_gfx12
    UINT64_C(3508142080), UINT64_C(0),	// V_SUB_CO_U32_e64_gfx9
    UINT64_C(872415481), UINT64_C(0),	// V_SUB_CO_U32_sdwa_gfx9
    UINT64_C(1711276032), UINT64_C(0),	// V_SUB_F16_dpp8_gfx10
    UINT64_C(1711276282), UINT64_C(0),	// V_SUB_F16_dpp_gfx10
    UINT64_C(1073742074), UINT64_C(0),	// V_SUB_F16_dpp_vi
    UINT64_C(1711276032), UINT64_C(0),	// V_SUB_F16_e32_gfx10
    UINT64_C(1073741824), UINT64_C(0),	// V_SUB_F16_e32_vi
    UINT64_C(3576889344), UINT64_C(0),	// V_SUB_F16_e64_gfx10
    UINT64_C(3508535296), UINT64_C(0),	// V_SUB_F16_e64_vi
    UINT64_C(1711276032), UINT64_C(0),	// V_SUB_F16_fake16_dpp8_gfx11
    UINT64_C(1711276032), UINT64_C(0),	// V_SUB_F16_fake16_dpp8_gfx12
    UINT64_C(1711276282), UINT64_C(0),	// V_SUB_F16_fake16_dpp_gfx11
    UINT64_C(1711276282), UINT64_C(0),	// V_SUB_F16_fake16_dpp_gfx12
    UINT64_C(1711276032), UINT64_C(0),	// V_SUB_F16_fake16_e32_gfx11
    UINT64_C(1711276032), UINT64_C(0),	// V_SUB_F16_fake16_e32_gfx12
    UINT64_C(3576889344), UINT64_C(0),	// V_SUB_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3576889344), UINT64_C(0),	// V_SUB_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077318713344), UINT64_C(0),	// V_SUB_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077318713344), UINT64_C(0),	// V_SUB_F16_fake16_e64_dpp_gfx12
    UINT64_C(3576889344), UINT64_C(0),	// V_SUB_F16_fake16_e64_gfx11
    UINT64_C(3576889344), UINT64_C(0),	// V_SUB_F16_fake16_e64_gfx12
    UINT64_C(1711276281), UINT64_C(0),	// V_SUB_F16_sdwa_gfx10
    UINT64_C(1073742073), UINT64_C(0),	// V_SUB_F16_sdwa_gfx9
    UINT64_C(1073742073), UINT64_C(0),	// V_SUB_F16_sdwa_vi
    UINT64_C(1711276032), UINT64_C(0),	// V_SUB_F16_t16_dpp8_gfx11
    UINT64_C(1711276032), UINT64_C(0),	// V_SUB_F16_t16_dpp8_gfx12
    UINT64_C(1711276282), UINT64_C(0),	// V_SUB_F16_t16_dpp_gfx11
    UINT64_C(1711276282), UINT64_C(0),	// V_SUB_F16_t16_dpp_gfx12
    UINT64_C(1711276032), UINT64_C(0),	// V_SUB_F16_t16_e32_gfx11
    UINT64_C(1711276032), UINT64_C(0),	// V_SUB_F16_t16_e32_gfx12
    UINT64_C(3576889344), UINT64_C(0),	// V_SUB_F16_t16_e64_dpp8_gfx11
    UINT64_C(3576889344), UINT64_C(0),	// V_SUB_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077318713344), UINT64_C(0),	// V_SUB_F16_t16_e64_dpp_gfx11
    UINT64_C(1077318713344), UINT64_C(0),	// V_SUB_F16_t16_e64_dpp_gfx12
    UINT64_C(3576889344), UINT64_C(0),	// V_SUB_F16_t16_e64_gfx11
    UINT64_C(3576889344), UINT64_C(0),	// V_SUB_F16_t16_e64_gfx12
    UINT64_C(134217728), UINT64_C(0),	// V_SUB_F32_dpp8_gfx10
    UINT64_C(134217728), UINT64_C(0),	// V_SUB_F32_dpp8_gfx11
    UINT64_C(134217728), UINT64_C(0),	// V_SUB_F32_dpp8_gfx12
    UINT64_C(134217978), UINT64_C(0),	// V_SUB_F32_dpp_gfx10
    UINT64_C(134217978), UINT64_C(0),	// V_SUB_F32_dpp_gfx11
    UINT64_C(134217978), UINT64_C(0),	// V_SUB_F32_dpp_gfx12
    UINT64_C(67109114), UINT64_C(0),	// V_SUB_F32_dpp_vi
    UINT64_C(134217728), UINT64_C(0),	// V_SUB_F32_e32_gfx10
    UINT64_C(134217728), UINT64_C(0),	// V_SUB_F32_e32_gfx11
    UINT64_C(134217728), UINT64_C(0),	// V_SUB_F32_e32_gfx12
    UINT64_C(134217728), UINT64_C(0),	// V_SUB_F32_e32_gfx6_gfx7
    UINT64_C(67108864), UINT64_C(0),	// V_SUB_F32_e32_vi
    UINT64_C(3573809152), UINT64_C(0),	// V_SUB_F32_e64_dpp8_gfx11
    UINT64_C(3573809152), UINT64_C(0),	// V_SUB_F32_e64_dpp8_gfx12
    UINT64_C(1077315633152), UINT64_C(0),	// V_SUB_F32_e64_dpp_gfx11
    UINT64_C(1077315633152), UINT64_C(0),	// V_SUB_F32_e64_dpp_gfx12
    UINT64_C(3573809152), UINT64_C(0),	// V_SUB_F32_e64_gfx10
    UINT64_C(3573809152), UINT64_C(0),	// V_SUB_F32_e64_gfx11
    UINT64_C(3573809152), UINT64_C(0),	// V_SUB_F32_e64_gfx12
    UINT64_C(3523739648), UINT64_C(0),	// V_SUB_F32_e64_gfx6_gfx7
    UINT64_C(3506569216), UINT64_C(0),	// V_SUB_F32_e64_vi
    UINT64_C(134217977), UINT64_C(0),	// V_SUB_F32_sdwa_gfx10
    UINT64_C(67109113), UINT64_C(0),	// V_SUB_F32_sdwa_gfx9
    UINT64_C(67109113), UINT64_C(0),	// V_SUB_F32_sdwa_vi
    UINT64_C(3533635584), UINT64_C(0),	// V_SUB_I16_vi
    UINT64_C(1275068416), UINT64_C(0),	// V_SUB_I32_e32_gfx6_gfx7
    UINT64_C(3528196096), UINT64_C(0),	// V_SUB_I32_e64_gfx6_gfx7
    UINT64_C(3533504512), UINT64_C(0),	// V_SUB_I32_vi
    UINT64_C(3608018944), UINT64_C(0),	// V_SUB_NC_I16V_SUB_I16_fake16_e64_dpp8_gfx11
    UINT64_C(3608018944), UINT64_C(0),	// V_SUB_NC_I16V_SUB_I16_fake16_e64_dpp8_gfx12
    UINT64_C(1077349842944), UINT64_C(0),	// V_SUB_NC_I16V_SUB_I16_fake16_e64_dpp_gfx11
    UINT64_C(1077349842944), UINT64_C(0),	// V_SUB_NC_I16V_SUB_I16_fake16_e64_dpp_gfx12
    UINT64_C(3608018944), UINT64_C(0),	// V_SUB_NC_I16V_SUB_I16_fake16_e64_gfx11
    UINT64_C(3608018944), UINT64_C(0),	// V_SUB_NC_I16V_SUB_I16_fake16_e64_gfx12
    UINT64_C(3608018944), UINT64_C(0),	// V_SUB_NC_I16V_SUB_I16_t16_e64_dpp8_gfx11
    UINT64_C(3608018944), UINT64_C(0),	// V_SUB_NC_I16V_SUB_I16_t16_e64_dpp8_gfx12
    UINT64_C(1077349842944), UINT64_C(0),	// V_SUB_NC_I16V_SUB_I16_t16_e64_dpp_gfx11
    UINT64_C(1077349842944), UINT64_C(0),	// V_SUB_NC_I16V_SUB_I16_t16_e64_dpp_gfx12
    UINT64_C(3608018944), UINT64_C(0),	// V_SUB_NC_I16V_SUB_I16_t16_e64_gfx11
    UINT64_C(3608018944), UINT64_C(0),	// V_SUB_NC_I16V_SUB_I16_t16_e64_gfx12
    UINT64_C(3608018944), UINT64_C(0),	// V_SUB_NC_I16_gfx10
    UINT64_C(3609526272), UINT64_C(0),	// V_SUB_NC_I32_e64_dpp8_gfx11
    UINT64_C(3609526272), UINT64_C(0),	// V_SUB_NC_I32_e64_dpp8_gfx12
    UINT64_C(1077351350272), UINT64_C(0),	// V_SUB_NC_I32_e64_dpp_gfx11
    UINT64_C(1077351350272), UINT64_C(0),	// V_SUB_NC_I32_e64_dpp_gfx12
    UINT64_C(3609526272), UINT64_C(0),	// V_SUB_NC_I32_e64_gfx11
    UINT64_C(3609526272), UINT64_C(0),	// V_SUB_NC_I32_e64_gfx12
    UINT64_C(3614834688), UINT64_C(0),	// V_SUB_NC_I32_gfx10
    UINT64_C(3607363584), UINT64_C(0),	// V_SUB_NC_U16_fake16_e64_dpp8_gfx11
    UINT64_C(3607363584), UINT64_C(0),	// V_SUB_NC_U16_fake16_e64_dpp8_gfx12
    UINT64_C(1077349187584), UINT64_C(0),	// V_SUB_NC_U16_fake16_e64_dpp_gfx11
    UINT64_C(1077349187584), UINT64_C(0),	// V_SUB_NC_U16_fake16_e64_dpp_gfx12
    UINT64_C(3607363584), UINT64_C(0),	// V_SUB_NC_U16_fake16_e64_gfx11
    UINT64_C(3607363584), UINT64_C(0),	// V_SUB_NC_U16_fake16_e64_gfx12
    UINT64_C(3607363584), UINT64_C(0),	// V_SUB_NC_U16_gfx10
    UINT64_C(3607363584), UINT64_C(0),	// V_SUB_NC_U16_t16_e64_dpp8_gfx11
    UINT64_C(3607363584), UINT64_C(0),	// V_SUB_NC_U16_t16_e64_dpp8_gfx12
    UINT64_C(1077349187584), UINT64_C(0),	// V_SUB_NC_U16_t16_e64_dpp_gfx11
    UINT64_C(1077349187584), UINT64_C(0),	// V_SUB_NC_U16_t16_e64_dpp_gfx12
    UINT64_C(3607363584), UINT64_C(0),	// V_SUB_NC_U16_t16_e64_gfx11
    UINT64_C(3607363584), UINT64_C(0),	// V_SUB_NC_U16_t16_e64_gfx12
    UINT64_C(1275068416), UINT64_C(0),	// V_SUB_NC_U32_dpp8_gfx10
    UINT64_C(1275068416), UINT64_C(0),	// V_SUB_NC_U32_dpp8_gfx11
    UINT64_C(1275068416), UINT64_C(0),	// V_SUB_NC_U32_dpp8_gfx12
    UINT64_C(1275068666), UINT64_C(0),	// V_SUB_NC_U32_dpp_gfx10
    UINT64_C(1275068666), UINT64_C(0),	// V_SUB_NC_U32_dpp_gfx11
    UINT64_C(1275068666), UINT64_C(0),	// V_SUB_NC_U32_dpp_gfx12
    UINT64_C(1275068416), UINT64_C(0),	// V_SUB_NC_U32_e32_gfx10
    UINT64_C(1275068416), UINT64_C(0),	// V_SUB_NC_U32_e32_gfx11
    UINT64_C(1275068416), UINT64_C(0),	// V_SUB_NC_U32_e32_gfx12
    UINT64_C(3576037376), UINT64_C(0),	// V_SUB_NC_U32_e64_dpp8_gfx11
    UINT64_C(3576037376), UINT64_C(0),	// V_SUB_NC_U32_e64_dpp8_gfx12
    UINT64_C(1077317861376), UINT64_C(0),	// V_SUB_NC_U32_e64_dpp_gfx11
    UINT64_C(1077317861376), UINT64_C(0),	// V_SUB_NC_U32_e64_dpp_gfx12
    UINT64_C(3576037376), UINT64_C(0),	// V_SUB_NC_U32_e64_gfx10
    UINT64_C(3576037376), UINT64_C(0),	// V_SUB_NC_U32_e64_gfx11
    UINT64_C(3576037376), UINT64_C(0),	// V_SUB_NC_U32_e64_gfx12
    UINT64_C(1275068665), UINT64_C(0),	// V_SUB_NC_U32_sdwa_gfx10
    UINT64_C(1308623098), UINT64_C(0),	// V_SUB_U16_dpp_vi
    UINT64_C(1308622848), UINT64_C(0),	// V_SUB_U16_e32_vi
    UINT64_C(3508994048), UINT64_C(0),	// V_SUB_U16_e64_vi
    UINT64_C(1308623097), UINT64_C(0),	// V_SUB_U16_sdwa_gfx9
    UINT64_C(1308623097), UINT64_C(0),	// V_SUB_U16_sdwa_vi
    UINT64_C(1778385146), UINT64_C(0),	// V_SUB_U32_dpp_gfx9
    UINT64_C(872415482), UINT64_C(0),	// V_SUB_U32_dpp_vi
    UINT64_C(1778384896), UINT64_C(0),	// V_SUB_U32_e32_gfx9
    UINT64_C(872415232), UINT64_C(0),	// V_SUB_U32_e32_vi
    UINT64_C(3509911552), UINT64_C(0),	// V_SUB_U32_e64_gfx9
    UINT64_C(3508142080), UINT64_C(0),	// V_SUB_U32_e64_vi
    UINT64_C(1778385145), UINT64_C(0),	// V_SUB_U32_sdwa_gfx9
    UINT64_C(872415481), UINT64_C(0),	// V_SUB_U32_sdwa_vi
    UINT64_C(1375731962), UINT64_C(0),	// V_SUB_U64_dpp_gfx1250
    UINT64_C(1375731712), UINT64_C(0),	// V_SUB_U64_e32_gfx1250
    UINT64_C(1077318057984), UINT64_C(0),	// V_SUB_U64_e64_dpp_gfx1250
    UINT64_C(3576233984), UINT64_C(0),	// V_SUB_U64_e64_gfx1250
    UINT64_C(2113982464), UINT64_C(0),	// V_SWAPREL_B32_gfx10
    UINT64_C(2113982464), UINT64_C(0),	// V_SWAPREL_B32_gfx11
    UINT64_C(2113982464), UINT64_C(0),	// V_SWAPREL_B32_gfx12
    UINT64_C(2113981440), UINT64_C(0),	// V_SWAP_B16_gfx11
    UINT64_C(2113981440), UINT64_C(0),	// V_SWAP_B16_gfx12
    UINT64_C(2113980928), UINT64_C(0),	// V_SWAP_B32_gfx10
    UINT64_C(2113980928), UINT64_C(0),	// V_SWAP_B32_gfx11
    UINT64_C(2113980928), UINT64_C(0),	// V_SWAP_B32_gfx12
    UINT64_C(2113970688), UINT64_C(0),	// V_SWAP_B32_vi
    UINT64_C(1729382260339703808), UINT64_C(0),	// V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250
    UINT64_C(1729382260338278400), UINT64_C(0),	// V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12
    UINT64_C(1729382260338278400), UINT64_C(0),	// V_SWMMAC_BF16_16X16X32_BF16_w64_twoaddr_gfx12
    UINT64_C(1729382260339638272), UINT64_C(0),	// V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250
    UINT64_C(1729382260340817920), UINT64_C(0),	// V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250
    UINT64_C(1729382260340752384), UINT64_C(0),	// V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250
    UINT64_C(1729382260340686848), UINT64_C(0),	// V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250
    UINT64_C(1729382260340621312), UINT64_C(0),	// V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250
    UINT64_C(1729382260338212864), UINT64_C(0),	// V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12
    UINT64_C(1729382260338212864), UINT64_C(0),	// V_SWMMAC_F16_16X16X32_F16_w64_twoaddr_gfx12
    UINT64_C(1729382260339572736), UINT64_C(0),	// V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250
    UINT64_C(1729382260340555776), UINT64_C(0),	// V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250
    UINT64_C(1729382260340490240), UINT64_C(0),	// V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250
    UINT64_C(1729382260340424704), UINT64_C(0),	// V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250
    UINT64_C(1729382260340359168), UINT64_C(0),	// V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250
    UINT64_C(1729382260338147328), UINT64_C(0),	// V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12
    UINT64_C(1729382260338147328), UINT64_C(0),	// V_SWMMAC_F32_16X16X32_BF16_w64_twoaddr_gfx12
    UINT64_C(1729382260338737152), UINT64_C(0),	// V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx12
    UINT64_C(1729382260338737152), UINT64_C(0),	// V_SWMMAC_F32_16X16X32_BF8_BF8_w64_twoaddr_gfx12
    UINT64_C(1729382260338671616), UINT64_C(0),	// V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx12
    UINT64_C(1729382260338671616), UINT64_C(0),	// V_SWMMAC_F32_16X16X32_BF8_FP8_w64_twoaddr_gfx12
    UINT64_C(1729382260338081792), UINT64_C(0),	// V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12
    UINT64_C(1729382260338081792), UINT64_C(0),	// V_SWMMAC_F32_16X16X32_F16_w64_twoaddr_gfx12
    UINT64_C(1729382260338606080), UINT64_C(0),	// V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx12
    UINT64_C(1729382260338606080), UINT64_C(0),	// V_SWMMAC_F32_16X16X32_FP8_BF8_w64_twoaddr_gfx12
    UINT64_C(1729382260338540544), UINT64_C(0),	// V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx12
    UINT64_C(1729382260338540544), UINT64_C(0),	// V_SWMMAC_F32_16X16X32_FP8_FP8_w64_twoaddr_gfx12
    UINT64_C(1729382260339507200), UINT64_C(0),	// V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250
    UINT64_C(1729382260339441664), UINT64_C(0),	// V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250
    UINT64_C(1729382260340883456), UINT64_C(0),	// V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_gfx1250
    UINT64_C(1729382260338409472), UINT64_C(0),	// V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx12
    UINT64_C(1729382260338409472), UINT64_C(0),	// V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx12
    UINT64_C(1729382260338343936), UINT64_C(0),	// V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx12
    UINT64_C(1729382260338343936), UINT64_C(0),	// V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx12
    UINT64_C(1729382260338475008), UINT64_C(0),	// V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx12
    UINT64_C(1729382260338475008), UINT64_C(0),	// V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx12
    UINT64_C(3598778368), UINT64_C(0),	// V_S_EXP_F16_e64_gfx12
    UINT64_C(3598712832), UINT64_C(0),	// V_S_EXP_F32_e64_gfx12
    UINT64_C(3598909440), UINT64_C(0),	// V_S_LOG_F16_e64_gfx12
    UINT64_C(3598843904), UINT64_C(0),	// V_S_LOG_F32_e64_gfx12
    UINT64_C(3599040512), UINT64_C(0),	// V_S_RCP_F16_e64_gfx12
    UINT64_C(3598974976), UINT64_C(0),	// V_S_RCP_F32_e64_gfx12
    UINT64_C(3599171584), UINT64_C(0),	// V_S_RSQ_F16_e64_gfx12
    UINT64_C(3599106048), UINT64_C(0),	// V_S_RSQ_F32_e64_gfx12
    UINT64_C(3599302656), UINT64_C(0),	// V_S_SQRT_F16_e64_gfx12
    UINT64_C(3599237120), UINT64_C(0),	// V_S_SQRT_F32_e64_gfx12
    UINT64_C(2113967104), UINT64_C(0),	// V_TANH_BF16V_TANH_BF16_fake16_dpp8_gfx1250
    UINT64_C(2113967354), UINT64_C(0),	// V_TANH_BF16V_TANH_BF16_fake16_dpp_gfx1250
    UINT64_C(2113967104), UINT64_C(0),	// V_TANH_BF16V_TANH_BF16_fake16_e32_gfx1250
    UINT64_C(3586785280), UINT64_C(0),	// V_TANH_BF16V_TANH_BF16_fake16_e64_dpp8_gfx1250
    UINT64_C(1077328609280), UINT64_C(0),	// V_TANH_BF16V_TANH_BF16_fake16_e64_dpp_gfx1250
    UINT64_C(3586785280), UINT64_C(0),	// V_TANH_BF16V_TANH_BF16_fake16_e64_gfx1250
    UINT64_C(2113967104), UINT64_C(0),	// V_TANH_BF16V_TANH_BF16_t16_dpp8_gfx1250
    UINT64_C(2113967354), UINT64_C(0),	// V_TANH_BF16V_TANH_BF16_t16_dpp_gfx1250
    UINT64_C(2113967104), UINT64_C(0),	// V_TANH_BF16V_TANH_BF16_t16_e32_gfx1250
    UINT64_C(3586785280), UINT64_C(0),	// V_TANH_BF16V_TANH_BF16_t16_e64_dpp8_gfx1250
    UINT64_C(1077328609280), UINT64_C(0),	// V_TANH_BF16V_TANH_BF16_t16_e64_dpp_gfx1250
    UINT64_C(3586785280), UINT64_C(0),	// V_TANH_BF16V_TANH_BF16_t16_e64_gfx1250
    UINT64_C(2113945088), UINT64_C(0),	// V_TANH_F16V_TANH_F16_fake16_dpp8_gfx1250
    UINT64_C(2113945338), UINT64_C(0),	// V_TANH_F16V_TANH_F16_fake16_dpp_gfx1250
    UINT64_C(2113945088), UINT64_C(0),	// V_TANH_F16V_TANH_F16_fake16_e32_gfx1250
    UINT64_C(3583967232), UINT64_C(0),	// V_TANH_F16V_TANH_F16_fake16_e64_dpp8_gfx1250
    UINT64_C(1077325791232), UINT64_C(0),	// V_TANH_F16V_TANH_F16_fake16_e64_dpp_gfx1250
    UINT64_C(3583967232), UINT64_C(0),	// V_TANH_F16V_TANH_F16_fake16_e64_gfx1250
    UINT64_C(2113945088), UINT64_C(0),	// V_TANH_F16V_TANH_F16_t16_dpp8_gfx1250
    UINT64_C(2113945338), UINT64_C(0),	// V_TANH_F16V_TANH_F16_t16_dpp_gfx1250
    UINT64_C(2113945088), UINT64_C(0),	// V_TANH_F16V_TANH_F16_t16_e32_gfx1250
    UINT64_C(3583967232), UINT64_C(0),	// V_TANH_F16V_TANH_F16_t16_e64_dpp8_gfx1250
    UINT64_C(1077325791232), UINT64_C(0),	// V_TANH_F16V_TANH_F16_t16_e64_dpp_gfx1250
    UINT64_C(3583967232), UINT64_C(0),	// V_TANH_F16V_TANH_F16_t16_e64_gfx1250
    UINT64_C(2113944576), UINT64_C(0),	// V_TANH_F32_dpp8_gfx1250
    UINT64_C(2113944826), UINT64_C(0),	// V_TANH_F32_dpp_gfx1250
    UINT64_C(2113944576), UINT64_C(0),	// V_TANH_F32_e32_gfx1250
    UINT64_C(3583901696), UINT64_C(0),	// V_TANH_F32_e64_dpp8_gfx1250
    UINT64_C(1077325725696), UINT64_C(0),	// V_TANH_F32_e64_dpp_gfx1250
    UINT64_C(3583901696), UINT64_C(0),	// V_TANH_F32_e64_gfx1250
    UINT64_C(3610181632), UINT64_C(0),	// V_TRIG_PREOP_F64_e64_gfx11
    UINT64_C(3610181632), UINT64_C(0),	// V_TRIG_PREOP_F64_e64_gfx12
    UINT64_C(3581149184), UINT64_C(0),	// V_TRIG_PREOP_F64_gfx10
    UINT64_C(3538419712), UINT64_C(0),	// V_TRIG_PREOP_F64_gfx6_gfx7
    UINT64_C(3532783616), UINT64_C(0),	// V_TRIG_PREOP_F64_vi
    UINT64_C(2113976832), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_fake16_dpp8_gfx11
    UINT64_C(2113976832), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_fake16_dpp8_gfx12
    UINT64_C(2113977082), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_fake16_dpp_gfx11
    UINT64_C(2113977082), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_fake16_dpp_gfx12
    UINT64_C(2113976832), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_fake16_e32_gfx11
    UINT64_C(2113976832), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_fake16_e32_gfx12
    UINT64_C(3588030464), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_fake16_e64_dpp8_gfx11
    UINT64_C(3588030464), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_fake16_e64_dpp8_gfx12
    UINT64_C(1077329854464), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_fake16_e64_dpp_gfx11
    UINT64_C(1077329854464), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_fake16_e64_dpp_gfx12
    UINT64_C(3588030464), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_fake16_e64_gfx11
    UINT64_C(3588030464), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_fake16_e64_gfx12
    UINT64_C(2113976832), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_t16_dpp8_gfx11
    UINT64_C(2113976832), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_t16_dpp8_gfx12
    UINT64_C(2113977082), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_t16_dpp_gfx11
    UINT64_C(2113977082), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_t16_dpp_gfx12
    UINT64_C(2113976832), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_t16_e32_gfx11
    UINT64_C(2113976832), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_t16_e32_gfx12
    UINT64_C(3588030464), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_t16_e64_dpp8_gfx11
    UINT64_C(3588030464), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_t16_e64_dpp8_gfx12
    UINT64_C(1077329854464), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_t16_e64_dpp_gfx11
    UINT64_C(1077329854464), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_t16_e64_dpp_gfx12
    UINT64_C(3588030464), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_t16_e64_gfx11
    UINT64_C(3588030464), UINT64_C(0),	// V_TRUNC_F16V_TRUNC_F16_t16_e64_gfx12
    UINT64_C(2113976832), UINT64_C(0),	// V_TRUNC_F16_dpp8_gfx10
    UINT64_C(2113977082), UINT64_C(0),	// V_TRUNC_F16_dpp_gfx10
    UINT64_C(2113965306), UINT64_C(0),	// V_TRUNC_F16_dpp_vi
    UINT64_C(2113976832), UINT64_C(0),	// V_TRUNC_F16_e32_gfx10
    UINT64_C(2113965056), UINT64_C(0),	// V_TRUNC_F16_e32_vi
    UINT64_C(3588030464), UINT64_C(0),	// V_TRUNC_F16_e64_gfx10
    UINT64_C(3515219968), UINT64_C(0),	// V_TRUNC_F16_e64_vi
    UINT64_C(2113977081), UINT64_C(0),	// V_TRUNC_F16_sdwa_gfx10
    UINT64_C(2113965305), UINT64_C(0),	// V_TRUNC_F16_sdwa_gfx9
    UINT64_C(2113965305), UINT64_C(0),	// V_TRUNC_F16_sdwa_vi
    UINT64_C(2113946112), UINT64_C(0),	// V_TRUNC_F32_dpp8_gfx10
    UINT64_C(2113946112), UINT64_C(0),	// V_TRUNC_F32_dpp8_gfx11
    UINT64_C(2113946112), UINT64_C(0),	// V_TRUNC_F32_dpp8_gfx12
    UINT64_C(2113946362), UINT64_C(0),	// V_TRUNC_F32_dpp_gfx10
    UINT64_C(2113946362), UINT64_C(0),	// V_TRUNC_F32_dpp_gfx11
    UINT64_C(2113946362), UINT64_C(0),	// V_TRUNC_F32_dpp_gfx12
    UINT64_C(2113943802), UINT64_C(0),	// V_TRUNC_F32_dpp_vi
    UINT64_C(2113946112), UINT64_C(0),	// V_TRUNC_F32_e32_gfx10
    UINT64_C(2113946112), UINT64_C(0),	// V_TRUNC_F32_e32_gfx11
    UINT64_C(2113946112), UINT64_C(0),	// V_TRUNC_F32_e32_gfx12
    UINT64_C(2113946112), UINT64_C(0),	// V_TRUNC_F32_e32_gfx6_gfx7
    UINT64_C(2113943552), UINT64_C(0),	// V_TRUNC_F32_e32_vi
    UINT64_C(3584098304), UINT64_C(0),	// V_TRUNC_F32_e64_dpp8_gfx11
    UINT64_C(3584098304), UINT64_C(0),	// V_TRUNC_F32_e64_dpp8_gfx12
    UINT64_C(1077325922304), UINT64_C(0),	// V_TRUNC_F32_e64_dpp_gfx11
    UINT64_C(1077325922304), UINT64_C(0),	// V_TRUNC_F32_e64_dpp_gfx12
    UINT64_C(3584098304), UINT64_C(0),	// V_TRUNC_F32_e64_gfx10
    UINT64_C(3584098304), UINT64_C(0),	// V_TRUNC_F32_e64_gfx11
    UINT64_C(3584098304), UINT64_C(0),	// V_TRUNC_F32_e64_gfx12
    UINT64_C(3544317952), UINT64_C(0),	// V_TRUNC_F32_e64_gfx6_gfx7
    UINT64_C(3512467456), UINT64_C(0),	// V_TRUNC_F32_e64_vi
    UINT64_C(2113946361), UINT64_C(0),	// V_TRUNC_F32_sdwa_gfx10
    UINT64_C(2113943801), UINT64_C(0),	// V_TRUNC_F32_sdwa_gfx9
    UINT64_C(2113943801), UINT64_C(0),	// V_TRUNC_F32_sdwa_vi
    UINT64_C(2113941242), UINT64_C(0),	// V_TRUNC_F64_dpp_gfx12
    UINT64_C(2113941242), UINT64_C(0),	// V_TRUNC_F64_dpp_vi
    UINT64_C(2113940992), UINT64_C(0),	// V_TRUNC_F64_e32_gfx10
    UINT64_C(2113940992), UINT64_C(0),	// V_TRUNC_F64_e32_gfx11
    UINT64_C(2113940992), UINT64_C(0),	// V_TRUNC_F64_e32_gfx12
    UINT64_C(2113940992), UINT64_C(0),	// V_TRUNC_F64_e32_gfx7
    UINT64_C(2113940992), UINT64_C(0),	// V_TRUNC_F64_e32_vi
    UINT64_C(1077325266944), UINT64_C(0),	// V_TRUNC_F64_e64_dpp_gfx12
    UINT64_C(3583442944), UINT64_C(0),	// V_TRUNC_F64_e64_gfx10
    UINT64_C(3583442944), UINT64_C(0),	// V_TRUNC_F64_e64_gfx11
    UINT64_C(3583442944), UINT64_C(0),	// V_TRUNC_F64_e64_gfx12
    UINT64_C(3543007232), UINT64_C(0),	// V_TRUNC_F64_e64_gfx7
    UINT64_C(3512139776), UINT64_C(0),	// V_TRUNC_F64_e64_vi
    UINT64_C(1729382260339376128), UINT64_C(0),	// V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250
    UINT64_C(3426942976), UINT64_C(0),	// V_WMMA_BF16_16X16X16_BF16_twoaddr_w32_gfx11
    UINT64_C(3426942976), UINT64_C(0),	// V_WMMA_BF16_16X16X16_BF16_twoaddr_w64_gfx11
    UINT64_C(1729382260337229824), UINT64_C(0),	// V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx12
    UINT64_C(1729382260337229824), UINT64_C(0),	// V_WMMA_BF16_16X16X16_BF16_w64_twoaddr_gfx12
    UINT64_C(1729382260339310592), UINT64_C(0),	// V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250
    UINT64_C(1729382260341669888), UINT64_C(0),	// V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250
    UINT64_C(1729382260341604352), UINT64_C(0),	// V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250
    UINT64_C(1729382260341538816), UINT64_C(0),	// V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250
    UINT64_C(1729382260341473280), UINT64_C(0),	// V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250
    UINT64_C(3426877440), UINT64_C(0),	// V_WMMA_F16_16X16X16_F16_twoaddr_w32_gfx11
    UINT64_C(3426877440), UINT64_C(0),	// V_WMMA_F16_16X16X16_F16_twoaddr_w64_gfx11
    UINT64_C(1729382260337164288), UINT64_C(0),	// V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx12
    UINT64_C(1729382260337164288), UINT64_C(0),	// V_WMMA_F16_16X16X16_F16_w64_twoaddr_gfx12
    UINT64_C(1729382260339179520), UINT64_C(0),	// V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250
    UINT64_C(1729382260340228096), UINT64_C(0),	// V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_gfx1250
    UINT64_C(1729382260340162560), UINT64_C(0),	// V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_gfx1250
    UINT64_C(1729382260340097024), UINT64_C(0),	// V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_gfx1250
    UINT64_C(1729382260340031488), UINT64_C(0),	// V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_gfx1250
    UINT64_C(1729382260341407744), UINT64_C(0),	// V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250
    UINT64_C(1729382260341342208), UINT64_C(0),	// V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250
    UINT64_C(3425894400), UINT64_C(0),	// V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_gfx1250
    UINT64_C(3425894400), UINT64_C(0),	// V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_gfx1250
    UINT64_C(3425894400), UINT64_C(0),	// V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_gfx1250
    UINT64_C(3425894400), UINT64_C(0),	// V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_gfx1250
    UINT64_C(3425894400), UINT64_C(0),	// V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_gfx1250
    UINT64_C(3425894400), UINT64_C(0),	// V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_gfx1250
    UINT64_C(3425894400), UINT64_C(0),	// V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_gfx1250
    UINT64_C(3425894400), UINT64_C(0),	// V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_gfx1250
    UINT64_C(3425894400), UINT64_C(0),	// V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_gfx1250
    UINT64_C(1729382260341276672), UINT64_C(0),	// V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250
    UINT64_C(1729382260341211136), UINT64_C(0),	// V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250
    UINT64_C(3426811904), UINT64_C(0),	// V_WMMA_F32_16X16X16_BF16_twoaddr_w32_gfx11
    UINT64_C(3426811904), UINT64_C(0),	// V_WMMA_F32_16X16X16_BF16_twoaddr_w64_gfx11
    UINT64_C(1729382260337098752), UINT64_C(0),	// V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx12
    UINT64_C(1729382260337098752), UINT64_C(0),	// V_WMMA_F32_16X16X16_BF16_w64_twoaddr_gfx12
    UINT64_C(1729382260337623040), UINT64_C(0),	// V_WMMA_F32_16X16X16_BF8_BF8_w32_twoaddr_gfx12
    UINT64_C(1729382260337623040), UINT64_C(0),	// V_WMMA_F32_16X16X16_BF8_BF8_w64_twoaddr_gfx12
    UINT64_C(1729382260337557504), UINT64_C(0),	// V_WMMA_F32_16X16X16_BF8_FP8_w32_twoaddr_gfx12
    UINT64_C(1729382260337557504), UINT64_C(0),	// V_WMMA_F32_16X16X16_BF8_FP8_w64_twoaddr_gfx12
    UINT64_C(3426746368), UINT64_C(0),	// V_WMMA_F32_16X16X16_F16_twoaddr_w32_gfx11
    UINT64_C(3426746368), UINT64_C(0),	// V_WMMA_F32_16X16X16_F16_twoaddr_w64_gfx11
    UINT64_C(1729382260337033216), UINT64_C(0),	// V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx12
    UINT64_C(1729382260337033216), UINT64_C(0),	// V_WMMA_F32_16X16X16_F16_w64_twoaddr_gfx12
    UINT64_C(1729382260337491968), UINT64_C(0),	// V_WMMA_F32_16X16X16_FP8_BF8_w32_twoaddr_gfx12
    UINT64_C(1729382260337491968), UINT64_C(0),	// V_WMMA_F32_16X16X16_FP8_BF8_w64_twoaddr_gfx12
    UINT64_C(1729382260337426432), UINT64_C(0),	// V_WMMA_F32_16X16X16_FP8_FP8_w32_twoaddr_gfx12
    UINT64_C(1729382260337426432), UINT64_C(0),	// V_WMMA_F32_16X16X16_FP8_FP8_w64_twoaddr_gfx12
    UINT64_C(1729382260339245056), UINT64_C(0),	// V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250
    UINT64_C(1729382260339113984), UINT64_C(0),	// V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250
    UINT64_C(1729382260338917376), UINT64_C(0),	// V_WMMA_F32_16X16X4_F32_w32_twoaddr_gfx1250
    UINT64_C(1729382260339965952), UINT64_C(0),	// V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_gfx1250
    UINT64_C(1729382260339900416), UINT64_C(0),	// V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_gfx1250
    UINT64_C(1729382260339834880), UINT64_C(0),	// V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_gfx1250
    UINT64_C(1729382260339769344), UINT64_C(0),	// V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_gfx1250
    UINT64_C(1729382260341751808), UINT64_C(0),	// V_WMMA_F32_32X16X128_F4_w32_twoaddr_gfx1250
    UINT64_C(3427074048), UINT64_C(0),	// V_WMMA_I32_16X16X16_IU4_twoaddr_w32_gfx11
    UINT64_C(3427074048), UINT64_C(0),	// V_WMMA_I32_16X16X16_IU4_twoaddr_w64_gfx11
    UINT64_C(1729382260337360896), UINT64_C(0),	// V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx12
    UINT64_C(1729382260337360896), UINT64_C(0),	// V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx12
    UINT64_C(3427008512), UINT64_C(0),	// V_WMMA_I32_16X16X16_IU8_twoaddr_w32_gfx11
    UINT64_C(3427008512), UINT64_C(0),	// V_WMMA_I32_16X16X16_IU8_twoaddr_w64_gfx11
    UINT64_C(1729382260337295360), UINT64_C(0),	// V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx12
    UINT64_C(1729382260337295360), UINT64_C(0),	// V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx12
    UINT64_C(1729382260337688576), UINT64_C(0),	// V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx12
    UINT64_C(1729382260337688576), UINT64_C(0),	// V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx12
    UINT64_C(1729382260340293632), UINT64_C(0),	// V_WMMA_I32_16X16X64_IU8_w32_twoaddr_gfx1250
    UINT64_C(288230379578064896), UINT64_C(0),	// V_WMMA_LD_SCALE16_PAIRED_B64_gfx1250
    UINT64_C(288230379577737216), UINT64_C(0),	// V_WMMA_LD_SCALE_PAIRED_B32_gfx1250
    UINT64_C(288230379578064896), UINT64_C(3425894400),	// V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250
    UINT64_C(288230379578064896), UINT64_C(3425894400),	// V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250
    UINT64_C(288230379578064896), UINT64_C(3425894400),	// V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250
    UINT64_C(288230379578064896), UINT64_C(3425894400),	// V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250
    UINT64_C(288230379578064896), UINT64_C(3425894400),	// V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250
    UINT64_C(288230379578064896), UINT64_C(3425894400),	// V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250
    UINT64_C(288230379578064896), UINT64_C(3425894400),	// V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250
    UINT64_C(288230379578064896), UINT64_C(3425894400),	// V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250
    UINT64_C(288230379578064896), UINT64_C(3425894400),	// V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250
    UINT64_C(288230379578064896), UINT64_C(1729382260341751808),	// V_WMMA_SCALE16_F32_32X16X128_F4_w32_gfx1250
    UINT64_C(288230379577737216), UINT64_C(3425894400),	// V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250
    UINT64_C(288230379577737216), UINT64_C(3425894400),	// V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250
    UINT64_C(288230379577737216), UINT64_C(3425894400),	// V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250
    UINT64_C(288230379577737216), UINT64_C(3425894400),	// V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250
    UINT64_C(288230379577737216), UINT64_C(3425894400),	// V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250
    UINT64_C(288230379577737216), UINT64_C(3425894400),	// V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250
    UINT64_C(288230379577737216), UINT64_C(3425894400),	// V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250
    UINT64_C(288230379577737216), UINT64_C(3425894400),	// V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250
    UINT64_C(288230379577737216), UINT64_C(3425894400),	// V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250
    UINT64_C(288230379577737216), UINT64_C(1729382260341751808),	// V_WMMA_SCALE_F32_32X16X128_F4_w32_gfx1250
    UINT64_C(3613458432), UINT64_C(0),	// V_WRITELANE_B32_e64_gfx11
    UINT64_C(3613458432), UINT64_C(0),	// V_WRITELANE_B32_e64_gfx12
    UINT64_C(3613458432), UINT64_C(0),	// V_WRITELANE_B32_gfx10
    UINT64_C(67108864), UINT64_C(0),	// V_WRITELANE_B32_gfx6_gfx7
    UINT64_C(3532259328), UINT64_C(0),	// V_WRITELANE_B32_vi
    UINT64_C(3594846208), UINT64_C(0),	// V_XAD_U32_e64_dpp8_gfx11
    UINT64_C(3594846208), UINT64_C(0),	// V_XAD_U32_e64_dpp8_gfx12
    UINT64_C(1077336670208), UINT64_C(0),	// V_XAD_U32_e64_dpp_gfx11
    UINT64_C(1077336670208), UINT64_C(0),	// V_XAD_U32_e64_dpp_gfx12
    UINT64_C(3594846208), UINT64_C(0),	// V_XAD_U32_e64_gfx11
    UINT64_C(3594846208), UINT64_C(0),	// V_XAD_U32_e64_gfx12
    UINT64_C(3611623424), UINT64_C(0),	// V_XAD_U32_gfx10
    UINT64_C(3522363392), UINT64_C(0),	// V_XAD_U32_vi
    UINT64_C(1006632960), UINT64_C(0),	// V_XNOR_B32_dpp8_gfx10
    UINT64_C(1006632960), UINT64_C(0),	// V_XNOR_B32_dpp8_gfx11
    UINT64_C(1006632960), UINT64_C(0),	// V_XNOR_B32_dpp8_gfx12
    UINT64_C(1006633210), UINT64_C(0),	// V_XNOR_B32_dpp_gfx10
    UINT64_C(1006633210), UINT64_C(0),	// V_XNOR_B32_dpp_gfx11
    UINT64_C(1006633210), UINT64_C(0),	// V_XNOR_B32_dpp_gfx12
    UINT64_C(2046820602), UINT64_C(0),	// V_XNOR_B32_dpp_vi
    UINT64_C(1006632960), UINT64_C(0),	// V_XNOR_B32_e32_gfx10
    UINT64_C(1006632960), UINT64_C(0),	// V_XNOR_B32_e32_gfx11
    UINT64_C(1006632960), UINT64_C(0),	// V_XNOR_B32_e32_gfx12
    UINT64_C(2046820352), UINT64_C(0),	// V_XNOR_B32_e32_vi
    UINT64_C(3575513088), UINT64_C(0),	// V_XNOR_B32_e64_dpp8_gfx11
    UINT64_C(3575513088), UINT64_C(0),	// V_XNOR_B32_e64_dpp8_gfx12
    UINT64_C(1077317337088), UINT64_C(0),	// V_XNOR_B32_e64_dpp_gfx11
    UINT64_C(1077317337088), UINT64_C(0),	// V_XNOR_B32_e64_dpp_gfx12
    UINT64_C(3575513088), UINT64_C(0),	// V_XNOR_B32_e64_gfx10
    UINT64_C(3575513088), UINT64_C(0),	// V_XNOR_B32_e64_gfx11
    UINT64_C(3575513088), UINT64_C(0),	// V_XNOR_B32_e64_gfx12
    UINT64_C(3510435840), UINT64_C(0),	// V_XNOR_B32_e64_vi
    UINT64_C(1006633209), UINT64_C(0),	// V_XNOR_B32_sdwa_gfx10
    UINT64_C(2046820601), UINT64_C(0),	// V_XNOR_B32_sdwa_gfx9
    UINT64_C(2046820601), UINT64_C(0),	// V_XNOR_B32_sdwa_vi
    UINT64_C(3594518528), UINT64_C(0),	// V_XOR3_B32_e64_dpp8_gfx11
    UINT64_C(3594518528), UINT64_C(0),	// V_XOR3_B32_e64_dpp8_gfx12
    UINT64_C(1077336342528), UINT64_C(0),	// V_XOR3_B32_e64_dpp_gfx11
    UINT64_C(1077336342528), UINT64_C(0),	// V_XOR3_B32_e64_dpp_gfx12
    UINT64_C(3594518528), UINT64_C(0),	// V_XOR3_B32_e64_gfx11
    UINT64_C(3594518528), UINT64_C(0),	// V_XOR3_B32_e64_gfx12
    UINT64_C(3581411328), UINT64_C(0),	// V_XOR3_B32_gfx10
    UINT64_C(3613655040), UINT64_C(0),	// V_XOR_B16_fake16_e64_dpp8_gfx11
    UINT64_C(3613655040), UINT64_C(0),	// V_XOR_B16_fake16_e64_dpp8_gfx12
    UINT64_C(1077355479040), UINT64_C(0),	// V_XOR_B16_fake16_e64_dpp_gfx11
    UINT64_C(1077355479040), UINT64_C(0),	// V_XOR_B16_fake16_e64_dpp_gfx12
    UINT64_C(3613655040), UINT64_C(0),	// V_XOR_B16_fake16_e64_gfx11
    UINT64_C(3613655040), UINT64_C(0),	// V_XOR_B16_fake16_e64_gfx12
    UINT64_C(3613655040), UINT64_C(0),	// V_XOR_B16_t16_e64_dpp8_gfx11
    UINT64_C(3613655040), UINT64_C(0),	// V_XOR_B16_t16_e64_dpp8_gfx12
    UINT64_C(1077355479040), UINT64_C(0),	// V_XOR_B16_t16_e64_dpp_gfx11
    UINT64_C(1077355479040), UINT64_C(0),	// V_XOR_B16_t16_e64_dpp_gfx12
    UINT64_C(3613655040), UINT64_C(0),	// V_XOR_B16_t16_e64_gfx11
    UINT64_C(3613655040), UINT64_C(0),	// V_XOR_B16_t16_e64_gfx12
    UINT64_C(973078528), UINT64_C(0),	// V_XOR_B32_dpp8_gfx10
    UINT64_C(973078528), UINT64_C(0),	// V_XOR_B32_dpp8_gfx11
    UINT64_C(973078528), UINT64_C(0),	// V_XOR_B32_dpp8_gfx12
    UINT64_C(973078778), UINT64_C(0),	// V_XOR_B32_dpp_gfx10
    UINT64_C(973078778), UINT64_C(0),	// V_XOR_B32_dpp_gfx11
    UINT64_C(973078778), UINT64_C(0),	// V_XOR_B32_dpp_gfx12
    UINT64_C(704643322), UINT64_C(0),	// V_XOR_B32_dpp_vi
    UINT64_C(973078528), UINT64_C(0),	// V_XOR_B32_e32_gfx10
    UINT64_C(973078528), UINT64_C(0),	// V_XOR_B32_e32_gfx11
    UINT64_C(973078528), UINT64_C(0),	// V_XOR_B32_e32_gfx12
    UINT64_C(973078528), UINT64_C(0),	// V_XOR_B32_e32_gfx6_gfx7
    UINT64_C(704643072), UINT64_C(0),	// V_XOR_B32_e32_vi
    UINT64_C(3575447552), UINT64_C(0),	// V_XOR_B32_e64_dpp8_gfx11
    UINT64_C(3575447552), UINT64_C(0),	// V_XOR_B32_e64_dpp8_gfx12
    UINT64_C(1077317271552), UINT64_C(0),	// V_XOR_B32_e64_dpp_gfx11
    UINT64_C(1077317271552), UINT64_C(0),	// V_XOR_B32_e64_dpp_gfx12
    UINT64_C(3575447552), UINT64_C(0),	// V_XOR_B32_e64_gfx10
    UINT64_C(3575447552), UINT64_C(0),	// V_XOR_B32_e64_gfx11
    UINT64_C(3575447552), UINT64_C(0),	// V_XOR_B32_e64_gfx12
    UINT64_C(3527016448), UINT64_C(0),	// V_XOR_B32_e64_gfx6_gfx7
    UINT64_C(3507814400), UINT64_C(0),	// V_XOR_B32_e64_vi
    UINT64_C(973078777), UINT64_C(0),	// V_XOR_B32_sdwa_gfx10
    UINT64_C(704643321), UINT64_C(0),	// V_XOR_B32_sdwa_gfx9
    UINT64_C(704643321), UINT64_C(0),	// V_XOR_B32_sdwa_vi
  };
  constexpr unsigned FirstSupportedOpcode = 11055;

  const unsigned opcode = MI.getOpcode();
  if (opcode < FirstSupportedOpcode)
    reportUnsupportedInst(MI);
  unsigned TableIndex = opcode - FirstSupportedOpcode;
  if (Scratch.getBitWidth() != 128)
    Scratch = Scratch.zext(128);
  Inst = APInt(128, ArrayRef(InstBits + TableIndex * 2, 2));
  APInt &Value = Inst;
  APInt &op = Scratch;
  switch (opcode) {
    case AMDGPU::BUFFER_GL0_INV_gfx10:
    case AMDGPU::BUFFER_GL0_INV_gfx11:
    case AMDGPU::BUFFER_GL1_INV_gfx10:
    case AMDGPU::BUFFER_GL1_INV_gfx11:
    case AMDGPU::BUFFER_INVL2_gfx90a:
    case AMDGPU::BUFFER_WBINVL1_SC_gfx6:
    case AMDGPU::BUFFER_WBINVL1_VOL_gfx7:
    case AMDGPU::BUFFER_WBINVL1_VOL_vi:
    case AMDGPU::BUFFER_WBINVL1_gfx6_gfx7:
    case AMDGPU::BUFFER_WBINVL1_vi:
    case AMDGPU::DS_NOP_gfx10:
    case AMDGPU::DS_NOP_gfx11:
    case AMDGPU::DS_NOP_gfx12:
    case AMDGPU::DS_NOP_gfx6_gfx7:
    case AMDGPU::DS_NOP_vi:
    case AMDGPU::S_BARRIER_INIT_M0_gfx12:
    case AMDGPU::S_BARRIER_JOIN_M0_gfx12:
    case AMDGPU::S_BARRIER_LEAVE_gfx12:
    case AMDGPU::S_BARRIER_SIGNAL_ISFIRST_M0_gfx12:
    case AMDGPU::S_BARRIER_SIGNAL_M0_gfx12:
    case AMDGPU::S_BARRIER_gfx10:
    case AMDGPU::S_BARRIER_gfx11:
    case AMDGPU::S_BARRIER_gfx6_gfx7:
    case AMDGPU::S_BARRIER_vi:
    case AMDGPU::S_CODE_END_gfx10:
    case AMDGPU::S_CODE_END_gfx11:
    case AMDGPU::S_CODE_END_gfx12:
    case AMDGPU::S_DCACHE_INV_VOL_ci:
    case AMDGPU::S_DCACHE_INV_VOL_vi:
    case AMDGPU::S_DCACHE_INV_gfx10:
    case AMDGPU::S_DCACHE_INV_gfx11:
    case AMDGPU::S_DCACHE_INV_gfx12:
    case AMDGPU::S_DCACHE_INV_si:
    case AMDGPU::S_DCACHE_INV_vi:
    case AMDGPU::S_DCACHE_WB_VOL_vi:
    case AMDGPU::S_DCACHE_WB_gfx10:
    case AMDGPU::S_DCACHE_WB_vi:
    case AMDGPU::S_ENDPGM_ORDERED_PS_DONE_gfx10:
    case AMDGPU::S_ENDPGM_ORDERED_PS_DONE_gfx11:
    case AMDGPU::S_ENDPGM_ORDERED_PS_DONE_vi:
    case AMDGPU::S_ENDPGM_SAVED_gfx10:
    case AMDGPU::S_ENDPGM_SAVED_gfx11:
    case AMDGPU::S_ENDPGM_SAVED_gfx12:
    case AMDGPU::S_ENDPGM_SAVED_gfx6_gfx7:
    case AMDGPU::S_ENDPGM_SAVED_vi:
    case AMDGPU::S_GL1_INV_gfx10:
    case AMDGPU::S_GL1_INV_gfx11:
    case AMDGPU::S_ICACHE_INV_gfx10:
    case AMDGPU::S_ICACHE_INV_gfx11:
    case AMDGPU::S_ICACHE_INV_gfx12:
    case AMDGPU::S_ICACHE_INV_gfx6_gfx7:
    case AMDGPU::S_ICACHE_INV_vi:
    case AMDGPU::S_SET_GPR_IDX_OFF_vi:
    case AMDGPU::S_TTRACEDATA_gfx10:
    case AMDGPU::S_TTRACEDATA_gfx11:
    case AMDGPU::S_TTRACEDATA_gfx12:
    case AMDGPU::S_TTRACEDATA_gfx6_gfx7:
    case AMDGPU::S_TTRACEDATA_vi:
    case AMDGPU::S_WAIT_IDLE_gfx10:
    case AMDGPU::S_WAIT_IDLE_gfx11:
    case AMDGPU::S_WAIT_IDLE_gfx12:
    case AMDGPU::S_WAKEUP_BARRIER_M0_gfx12:
    case AMDGPU::S_WAKEUP_gfx10:
    case AMDGPU::S_WAKEUP_gfx11:
    case AMDGPU::S_WAKEUP_gfx12:
    case AMDGPU::S_WAKEUP_vi:
    case AMDGPU::V_CLREXCP_e32_gfx10:
    case AMDGPU::V_CLREXCP_e32_gfx6_gfx7:
    case AMDGPU::V_CLREXCP_e32_vi:
    case AMDGPU::V_CLREXCP_e64_gfx10:
    case AMDGPU::V_CLREXCP_e64_gfx6_gfx7:
    case AMDGPU::V_CLREXCP_e64_vi:
    case AMDGPU::V_ILLEGAL:
    case AMDGPU::V_NOP_e32_gfx10:
    case AMDGPU::V_NOP_e32_gfx11:
    case AMDGPU::V_NOP_e32_gfx12:
    case AMDGPU::V_NOP_e32_gfx6_gfx7:
    case AMDGPU::V_NOP_e32_vi:
    case AMDGPU::V_NOP_e64_gfx10:
    case AMDGPU::V_NOP_e64_gfx11:
    case AMDGPU::V_NOP_e64_gfx12:
    case AMDGPU::V_NOP_e64_gfx6_gfx7:
    case AMDGPU::V_NOP_e64_vi:
    case AMDGPU::V_NOP_sdwa_gfx10:
    case AMDGPU::V_NOP_sdwa_gfx9:
    case AMDGPU::V_NOP_sdwa_vi:
    case AMDGPU::V_PIPEFLUSH_e32_gfx10:
    case AMDGPU::V_PIPEFLUSH_e32_gfx11:
    case AMDGPU::V_PIPEFLUSH_e32_gfx12:
    case AMDGPU::V_PIPEFLUSH_e64_gfx10:
    case AMDGPU::V_PIPEFLUSH_e64_gfx11:
    case AMDGPU::V_PIPEFLUSH_e64_gfx12: {
      break;
    }
    case AMDGPU::DS_ADD_F32_gfx12:
    case AMDGPU::DS_ADD_F64_gfx12:
    case AMDGPU::DS_ADD_U32_gfx12:
    case AMDGPU::DS_ADD_U64_gfx12:
    case AMDGPU::DS_AND_B32_gfx12:
    case AMDGPU::DS_AND_B64_gfx12:
    case AMDGPU::DS_COND_SUB_U32_gfx12:
    case AMDGPU::DS_DEC_U32_gfx12:
    case AMDGPU::DS_DEC_U64_gfx12:
    case AMDGPU::DS_INC_U32_gfx12:
    case AMDGPU::DS_INC_U64_gfx12:
    case AMDGPU::DS_MAX_F32_gfx12:
    case AMDGPU::DS_MAX_F64_gfx12:
    case AMDGPU::DS_MAX_I32_gfx12:
    case AMDGPU::DS_MAX_I64_gfx12:
    case AMDGPU::DS_MAX_U32_gfx12:
    case AMDGPU::DS_MAX_U64_gfx12:
    case AMDGPU::DS_MIN_F32_gfx12:
    case AMDGPU::DS_MIN_F64_gfx12:
    case AMDGPU::DS_MIN_I32_gfx12:
    case AMDGPU::DS_MIN_I64_gfx12:
    case AMDGPU::DS_MIN_U32_gfx12:
    case AMDGPU::DS_MIN_U64_gfx12:
    case AMDGPU::DS_OR_B32_gfx12:
    case AMDGPU::DS_OR_B64_gfx12:
    case AMDGPU::DS_PK_ADD_BF16_gfx12:
    case AMDGPU::DS_PK_ADD_F16_gfx12:
    case AMDGPU::DS_RSUB_U32_gfx12:
    case AMDGPU::DS_RSUB_U64_gfx12:
    case AMDGPU::DS_SUB_CLAMP_U32_gfx12:
    case AMDGPU::DS_SUB_U32_gfx12:
    case AMDGPU::DS_SUB_U64_gfx12:
    case AMDGPU::DS_WRITE_B128_gfx12:
    case AMDGPU::DS_WRITE_B16_D16_HI_gfx12:
    case AMDGPU::DS_WRITE_B16_gfx12:
    case AMDGPU::DS_WRITE_B32_gfx12:
    case AMDGPU::DS_WRITE_B64_gfx12:
    case AMDGPU::DS_WRITE_B8_D16_HI_gfx12:
    case AMDGPU::DS_WRITE_B8_gfx12:
    case AMDGPU::DS_WRITE_B96_gfx12:
    case AMDGPU::DS_XOR_B32_gfx12:
    case AMDGPU::DS_XOR_B64_gfx12: {
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: data0
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_CMPSTORE_B32_gfx12:
    case AMDGPU::DS_CMPSTORE_B64_gfx12:
    case AMDGPU::DS_MSKOR_B32_gfx12:
    case AMDGPU::DS_MSKOR_B64_gfx12: {
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: data0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: data1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_WRITE2ST64_B32_gfx12:
    case AMDGPU::DS_WRITE2ST64_B64_gfx12:
    case AMDGPU::DS_WRITE2_B32_gfx12:
    case AMDGPU::DS_WRITE2_B64_gfx12: {
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: data0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: data1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: offset0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: offset1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 8, 8);
      break;
    }
    case AMDGPU::DS_ATOMIC_ASYNC_BARRIER_ARRIVE_B64_gfx12: {
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::LDS_PARAM_LOAD_gfx11: {
      // op: attrchan
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 8, 2);
      // op: attr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 0), 10, 6);
      // op: waitvdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 16, 4);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::DS_PARAM_LOAD_gfx12: {
      // op: attrchan
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 8, 2);
      // op: attr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 0), 10, 6);
      // op: waitvdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 16, 4);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: waitvsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 23, 1);
      break;
    }
    case AMDGPU::V_CVT_F32_BF8_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F32_FP8_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F32_FP8_e64_dpp_gfx12: {
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 11, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_F32_BF8_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_FP8_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_FP8_e64_dpp8_gfx12: {
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 11, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_F32_FP8_e64_dpp_gfx1250: {
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 11, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_F32_FP8_e64_dpp8_gfx1250: {
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 11, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F32_I32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F32_I32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F32_U32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F32_U32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE0_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE0_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE1_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE1_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE2_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE2_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE3_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE3_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F64_I32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F64_U32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_OFF_F32_I4_e64_dpp_gfx11:
    case AMDGPU::V_CVT_OFF_F32_I4_e64_dpp_gfx12: {
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE0_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE0_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE1_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE1_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE2_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE2_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE3_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE3_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_OFF_F32_I4_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_OFF_F32_I4_e64_dpp8_gfx12: {
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_ADD_NC_I32_e64_dpp_gfx11:
    case AMDGPU::V_ADD_NC_I32_e64_dpp_gfx12:
    case AMDGPU::V_ADD_NC_U32_e64_dpp_gfx11:
    case AMDGPU::V_ADD_NC_U32_e64_dpp_gfx12:
    case AMDGPU::V_ADD_U64_e64_dpp_gfx1250:
    case AMDGPU::V_MUL_I32_I24_e64_dpp_gfx11:
    case AMDGPU::V_MUL_I32_I24_e64_dpp_gfx12:
    case AMDGPU::V_MUL_U32_U24_e64_dpp_gfx11:
    case AMDGPU::V_MUL_U32_U24_e64_dpp_gfx12:
    case AMDGPU::V_SUBREV_NC_U32_e64_dpp_gfx11:
    case AMDGPU::V_SUBREV_NC_U32_e64_dpp_gfx12:
    case AMDGPU::V_SUB_NC_I32_e64_dpp_gfx11:
    case AMDGPU::V_SUB_NC_I32_e64_dpp_gfx12:
    case AMDGPU::V_SUB_NC_U32_e64_dpp_gfx11:
    case AMDGPU::V_SUB_NC_U32_e64_dpp_gfx12:
    case AMDGPU::V_SUB_U64_e64_dpp_gfx1250: {
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_ADD_NC_I32_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_NC_I32_e64_dpp8_gfx12:
    case AMDGPU::V_ADD_NC_U32_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_NC_U32_e64_dpp8_gfx12:
    case AMDGPU::V_MUL_I32_I24_e64_dpp8_gfx11:
    case AMDGPU::V_MUL_I32_I24_e64_dpp8_gfx12:
    case AMDGPU::V_MUL_U32_U24_e64_dpp8_gfx11:
    case AMDGPU::V_MUL_U32_U24_e64_dpp8_gfx12:
    case AMDGPU::V_SUBREV_NC_U32_e64_dpp8_gfx11:
    case AMDGPU::V_SUBREV_NC_U32_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_NC_I32_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_NC_I32_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_NC_U32_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_NC_U32_e64_dpp8_gfx12: {
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_ADD_MAX_I32_e64_dpp_gfx1250:
    case AMDGPU::V_ADD_MAX_U32_e64_dpp_gfx1250:
    case AMDGPU::V_ADD_MIN_I32_e64_dpp_gfx1250:
    case AMDGPU::V_ADD_MIN_U32_e64_dpp_gfx1250:
    case AMDGPU::V_MAD_I32_I24_e64_dpp_gfx11:
    case AMDGPU::V_MAD_I32_I24_e64_dpp_gfx12:
    case AMDGPU::V_MAD_NC_I64_I32_e64_dpp_gfx1250:
    case AMDGPU::V_MAD_NC_U64_U32_e64_dpp_gfx1250:
    case AMDGPU::V_MAD_U32_U24_e64_dpp_gfx11:
    case AMDGPU::V_MAD_U32_U24_e64_dpp_gfx12:
    case AMDGPU::V_MSAD_U8_e64_dpp_gfx11:
    case AMDGPU::V_MSAD_U8_e64_dpp_gfx12:
    case AMDGPU::V_SAD_HI_U8_e64_dpp_gfx11:
    case AMDGPU::V_SAD_HI_U8_e64_dpp_gfx12:
    case AMDGPU::V_SAD_U16_e64_dpp_gfx11:
    case AMDGPU::V_SAD_U16_e64_dpp_gfx12:
    case AMDGPU::V_SAD_U32_e64_dpp_gfx11:
    case AMDGPU::V_SAD_U32_e64_dpp_gfx12:
    case AMDGPU::V_SAD_U8_e64_dpp_gfx11:
    case AMDGPU::V_SAD_U8_e64_dpp_gfx12: {
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_ADD_MAX_I32_e64_dpp8_gfx1250:
    case AMDGPU::V_ADD_MAX_U32_e64_dpp8_gfx1250:
    case AMDGPU::V_ADD_MIN_I32_e64_dpp8_gfx1250:
    case AMDGPU::V_ADD_MIN_U32_e64_dpp8_gfx1250:
    case AMDGPU::V_MAD_I32_I24_e64_dpp8_gfx11:
    case AMDGPU::V_MAD_I32_I24_e64_dpp8_gfx12:
    case AMDGPU::V_MAD_U32_U24_e64_dpp8_gfx11:
    case AMDGPU::V_MAD_U32_U24_e64_dpp8_gfx12:
    case AMDGPU::V_MSAD_U8_e64_dpp8_gfx11:
    case AMDGPU::V_MSAD_U8_e64_dpp8_gfx12:
    case AMDGPU::V_SAD_HI_U8_e64_dpp8_gfx11:
    case AMDGPU::V_SAD_HI_U8_e64_dpp8_gfx12:
    case AMDGPU::V_SAD_U16_e64_dpp8_gfx11:
    case AMDGPU::V_SAD_U16_e64_dpp8_gfx12:
    case AMDGPU::V_SAD_U32_e64_dpp8_gfx11:
    case AMDGPU::V_SAD_U32_e64_dpp8_gfx12:
    case AMDGPU::V_SAD_U8_e64_dpp8_gfx11:
    case AMDGPU::V_SAD_U8_e64_dpp8_gfx12: {
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_ADD_CO_U32_e64_dpp_gfx11:
    case AMDGPU::V_ADD_CO_U32_e64_dpp_gfx12:
    case AMDGPU::V_SUBREV_CO_U32_e64_dpp_gfx11:
    case AMDGPU::V_SUBREV_CO_U32_e64_dpp_gfx12:
    case AMDGPU::V_SUB_CO_U32_e64_dpp_gfx11:
    case AMDGPU::V_SUB_CO_U32_e64_dpp_gfx12: {
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 8, 7);
      break;
    }
    case AMDGPU::V_ADD_CO_U32_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_CO_U32_e64_dpp8_gfx12:
    case AMDGPU::V_SUBREV_CO_U32_e64_dpp8_gfx11:
    case AMDGPU::V_SUBREV_CO_U32_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_CO_U32_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_CO_U32_e64_dpp8_gfx12: {
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 8, 7);
      break;
    }
    case AMDGPU::V_ADD_CO_CI_U32_e64_dpp_gfx11:
    case AMDGPU::V_ADD_CO_CI_U32_e64_dpp_gfx12:
    case AMDGPU::V_MAD_CO_I64_I32_e64_dpp_gfx12:
    case AMDGPU::V_MAD_CO_U64_U32_e64_dpp_gfx12:
    case AMDGPU::V_SUBREV_CO_CI_U32_e64_dpp_gfx11:
    case AMDGPU::V_SUBREV_CO_CI_U32_e64_dpp_gfx12:
    case AMDGPU::V_SUB_CO_CI_U32_e64_dpp_gfx11:
    case AMDGPU::V_SUB_CO_CI_U32_e64_dpp_gfx12: {
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 8, 7);
      break;
    }
    case AMDGPU::V_ADD_CO_CI_U32_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_CO_CI_U32_e64_dpp8_gfx12:
    case AMDGPU::V_SUBREV_CO_CI_U32_e64_dpp8_gfx11:
    case AMDGPU::V_SUBREV_CO_CI_U32_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_CO_CI_U32_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_CO_CI_U32_e64_dpp8_gfx12: {
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 8, 7);
      break;
    }
    case AMDGPU::BUFFER_INV_gfx940:
    case AMDGPU::BUFFER_WBL2_gfx90a:
    case AMDGPU::BUFFER_WBL2_gfx940: {
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 15, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      break;
    }
    case AMDGPU::GLOBAL_INV_gfx12:
    case AMDGPU::GLOBAL_WBINV_gfx12:
    case AMDGPU::GLOBAL_WB_gfx12:
    case AMDGPU::TENSOR_STOP_gfx1250: {
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      break;
    }
    case AMDGPU::SCRATCH_LOAD_LDS_DWORD_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_SBYTE_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_SSHORT_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_UBYTE_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_USHORT_ST_gfx940: {
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::SCRATCH_LOAD_LDS_DWORD_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_SBYTE_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_SSHORT_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_UBYTE_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_USHORT_ST_gfx10: {
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::FLAT_PREFETCH_B8_gfx1250:
    case AMDGPU::GLOBAL_PREFETCH_B8_gfx1250: {
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_ST_gfx12:
    case AMDGPU::SCRATCH_STORE_BYTE_ST_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX2_ST_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX3_ST_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX4_ST_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORD_ST_gfx12:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_ST_gfx12:
    case AMDGPU::SCRATCH_STORE_SHORT_ST_gfx12: {
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 55, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::GLOBAL_STORE_DWORD_ADDTID_gfx12:
    case AMDGPU::SCRATCH_STORE_BLOCK_ST_gfx12: {
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 55, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_gfx12:
    case AMDGPU::SCRATCH_STORE_BYTE_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX2_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX3_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX4_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORD_gfx12:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_gfx12:
    case AMDGPU::SCRATCH_STORE_SHORT_gfx12: {
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 55, 8);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_F32_gfx12:
    case AMDGPU::FLAT_ATOMIC_ADD_F64_gfx1250:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_ADD_gfx12:
    case AMDGPU::FLAT_ATOMIC_AND_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_AND_gfx12:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_gfx12:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_DEC_gfx12:
    case AMDGPU::FLAT_ATOMIC_FMAX_gfx12:
    case AMDGPU::FLAT_ATOMIC_FMIN_gfx12:
    case AMDGPU::FLAT_ATOMIC_INC_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_INC_gfx12:
    case AMDGPU::FLAT_ATOMIC_MAX_F64_gfx1250:
    case AMDGPU::FLAT_ATOMIC_MIN_F64_gfx1250:
    case AMDGPU::FLAT_ATOMIC_OR_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_OR_gfx12:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_BF16_gfx12:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_F16_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMAX_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMIN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_SUB_gfx12:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_SWAP_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMAX_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMIN_gfx12:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_XOR_gfx12:
    case AMDGPU::FLAT_STORE_BYTE_D16_HI_gfx12:
    case AMDGPU::FLAT_STORE_BYTE_gfx12:
    case AMDGPU::FLAT_STORE_DWORDX2_gfx12:
    case AMDGPU::FLAT_STORE_DWORDX3_gfx12:
    case AMDGPU::FLAT_STORE_DWORDX4_gfx12:
    case AMDGPU::FLAT_STORE_DWORD_gfx12:
    case AMDGPU::FLAT_STORE_SHORT_D16_HI_gfx12:
    case AMDGPU::FLAT_STORE_SHORT_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_AND_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_DEC_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_INC_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_OR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SUB_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_XOR_gfx12:
    case AMDGPU::GLOBAL_STORE_BYTE_D16_HI_gfx12:
    case AMDGPU::GLOBAL_STORE_BYTE_gfx12:
    case AMDGPU::GLOBAL_STORE_DWORDX2_gfx12:
    case AMDGPU::GLOBAL_STORE_DWORDX3_gfx12:
    case AMDGPU::GLOBAL_STORE_DWORDX4_gfx12:
    case AMDGPU::GLOBAL_STORE_DWORD_gfx12:
    case AMDGPU::GLOBAL_STORE_SHORT_D16_HI_gfx12:
    case AMDGPU::GLOBAL_STORE_SHORT_gfx12: {
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 55, 8);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::SCRATCH_STORE_BLOCK_gfx12: {
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 55, 8);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::FLAT_ATOMIC_COND_SUB_U32_gfx12:
    case AMDGPU::FLAT_ATOMIC_CSUB_U32_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CSUB_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_gfx12:
    case AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B128_gfx1250:
    case AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B32_gfx1250:
    case AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B64_gfx1250:
    case AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B8_gfx1250:
    case AMDGPU::GLOBAL_STORE_BLOCK_gfx12: {
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 55, 8);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::DS_GWS_BARRIER_gfx10:
    case AMDGPU::DS_GWS_BARRIER_gfx11:
    case AMDGPU::DS_GWS_BARRIER_gfx6_gfx7:
    case AMDGPU::DS_GWS_INIT_gfx10:
    case AMDGPU::DS_GWS_INIT_gfx11:
    case AMDGPU::DS_GWS_INIT_gfx6_gfx7:
    case AMDGPU::DS_GWS_SEMA_BR_gfx10:
    case AMDGPU::DS_GWS_SEMA_BR_gfx11:
    case AMDGPU::DS_GWS_SEMA_BR_gfx6_gfx7: {
      // op: data0
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_GWS_BARRIER_vi:
    case AMDGPU::DS_GWS_INIT_vi:
    case AMDGPU::DS_GWS_SEMA_BR_vi: {
      // op: data0
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 25, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_WRITE_ADDTID_B32_gfx12: {
      // op: data0
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V1_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V1_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V1_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V1_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V1_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V1_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V1_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V1_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V1_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V1_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V1_V1_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V2_V1_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V3_V1_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V4_V1_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V5_V1_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 55, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_V1_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_V2_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_V3_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_V4_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_V5_V1_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V1_V1_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V2_V1_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V3_V1_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V4_V1_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V5_V1_gfx12:
    case AMDGPU::IMAGE_STORE_V1_V1_gfx12:
    case AMDGPU::IMAGE_STORE_V2_V1_gfx12:
    case AMDGPU::IMAGE_STORE_V3_V1_gfx12:
    case AMDGPU::IMAGE_STORE_V4_V1_gfx12:
    case AMDGPU::IMAGE_STORE_V5_V1_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 55, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 5, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_nortn_V1_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 3, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 5, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      // op: samp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 55, 9);
      break;
    }
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V1_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V1_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V1_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V1_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 3, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 5, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V1_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V2_V1_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V3_V1_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V4_V1_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V5_V1_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 3, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      // op: samp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 55, 9);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_nortn_V2_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 3, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 5, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      // op: samp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 55, 9);
      break;
    }
    case AMDGPU::IMAGE_GATHER4H_V2_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4H_V4_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4H_V5_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V2_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V4_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V5_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_V2_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_V4_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_V5_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V1_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V2_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V3_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V4_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V5_V1_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 3, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 5, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      // op: samp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 55, 9);
      break;
    }
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V2_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V2_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V2_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V2_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 3, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 5, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V2_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V2_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V2_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V2_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V2_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V2_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V1_V2_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V2_V2_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V3_V2_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V4_V2_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V5_V2_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 55, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V1_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 55, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_V1_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_V2_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_V3_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_V4_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_V5_V2_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V1_V2_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V2_V2_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V3_V2_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V4_V2_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V5_V2_gfx12:
    case AMDGPU::IMAGE_STORE_V1_V2_gfx12:
    case AMDGPU::IMAGE_STORE_V2_V2_gfx12:
    case AMDGPU::IMAGE_STORE_V3_V2_gfx12:
    case AMDGPU::IMAGE_STORE_V4_V2_gfx12:
    case AMDGPU::IMAGE_STORE_V5_V2_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 55, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 5, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V3_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V3_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V3_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V3_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V3_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V3_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V1_V3_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V2_V3_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V3_V3_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V4_V3_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V5_V3_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 55, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vaddr2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V2_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 55, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_V1_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_V2_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_V3_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_V4_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_V5_V3_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V1_V3_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V2_V3_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V3_V3_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V4_V3_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V5_V3_gfx12:
    case AMDGPU::IMAGE_STORE_V1_V3_gfx12:
    case AMDGPU::IMAGE_STORE_V2_V3_gfx12:
    case AMDGPU::IMAGE_STORE_V3_V3_gfx12:
    case AMDGPU::IMAGE_STORE_V4_V3_gfx12:
    case AMDGPU::IMAGE_STORE_V5_V3_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 55, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 5, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vaddr2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V2_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V2_V2_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V3_V2_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V4_V2_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V5_V2_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 3, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      // op: samp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 55, 9);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_nortn_V3_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 3, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 5, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vaddr2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      // op: samp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 55, 9);
      break;
    }
    case AMDGPU::IMAGE_GATHER4H_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4H_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4H_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_O_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_O_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_O_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V5_V2_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 3, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 5, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      // op: samp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 55, 9);
      break;
    }
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V3_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V3_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V3_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V3_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 3, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 5, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vaddr2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V4_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V4_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V4_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V4_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V4_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V4_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V1_V4_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V2_V4_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V3_V4_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V4_V4_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V5_V4_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 55, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vaddr2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vaddr3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V3_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 55, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vaddr2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_V1_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_V2_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_V3_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_V4_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_V5_V4_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V1_V4_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V2_V4_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V3_V4_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V4_V4_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V5_V4_gfx12:
    case AMDGPU::IMAGE_STORE_V1_V4_gfx12:
    case AMDGPU::IMAGE_STORE_V2_V4_gfx12:
    case AMDGPU::IMAGE_STORE_V3_V4_gfx12:
    case AMDGPU::IMAGE_STORE_V4_V4_gfx12:
    case AMDGPU::IMAGE_STORE_V5_V4_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 55, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 5, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vaddr2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vaddr3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V3_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V2_V3_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V3_V3_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V4_V3_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V5_V3_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 3, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vaddr2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      // op: samp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 55, 9);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V12_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V4_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 3, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 5, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vaddr2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vaddr3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      // op: samp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 55, 9);
      break;
    }
    case AMDGPU::IMAGE_GATHER4H_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4H_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4H_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V5_V3_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 3, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 5, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vaddr2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      // op: samp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 55, 9);
      break;
    }
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V4_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V4_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V4_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V4_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 3, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 5, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vaddr2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vaddr3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V4_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 55, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vaddr2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vaddr3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      break;
    }
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V6_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V6_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V6_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V12_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V12_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V12_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V12_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V12_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V4_gfx12: {
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 0, 3);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 3, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 5, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 6, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 22, 4);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vaddr2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vaddr3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      // op: samp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 55, 9);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V8_nsa_gfx10: {
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(16), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(17), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(18), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V9_nsa_gfx10: {
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(17), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(18), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(19), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(16), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V10_nsa_gfx10: {
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(16), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(18), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(19), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(20), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(17), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V11_nsa_gfx10: {
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(16), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(17), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(19), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(20), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(21), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(18), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V12_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V12_nsa_gfx10: {
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(16), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(17), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(18), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(20), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(21), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(22), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(19), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_nortn_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_nortn_V4_gfx10: {
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V12_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_nortn_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_nortn_V4_gfx11: {
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 58, 5);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_nortn_V2_nsa_gfx10: {
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_nortn_V2_nsa_gfx11: {
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 58, 5);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_nortn_V3_nsa_gfx10: {
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_nortn_V3_nsa_gfx11: {
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 58, 5);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V4_nsa_gfx10: {
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V4_nsa_gfx11: {
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 58, 5);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V5_nsa_gfx10: {
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V12_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V5_nsa_gfx11: {
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 58, 5);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V6_nsa_gfx10: {
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(16), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V7_nsa_gfx10: {
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(16), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(17), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::V_NOP_dpp8_gfx10: {
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 40, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      break;
    }
    case AMDGPU::V_NOP_dpp_vi: {
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      break;
    }
    case AMDGPU::V_NOP_dpp_gfx10: {
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 50, 1);
      break;
    }
    case AMDGPU::EXP_DONE_gfx11:
    case AMDGPU::EXP_DONE_gfx12:
    case AMDGPU::EXP_ROW_DONE_gfx11:
    case AMDGPU::EXP_ROW_DONE_gfx12:
    case AMDGPU::EXP_ROW_gfx11:
    case AMDGPU::EXP_ROW_gfx12:
    case AMDGPU::EXP_gfx11:
    case AMDGPU::EXP_gfx12: {
      // op: en
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 0, 4);
      // op: tgt
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 0), 4, 6);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: src3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::EXP_DONE_gfx10:
    case AMDGPU::EXP_DONE_si:
    case AMDGPU::EXP_DONE_vi:
    case AMDGPU::EXP_gfx10:
    case AMDGPU::EXP_si:
    case AMDGPU::EXP_vi: {
      // op: en
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 0, 4);
      // op: tgt
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 0), 4, 6);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: src3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: compr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 10, 1);
      // op: vm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      break;
    }
    case AMDGPU::V_PERMLANE16_SWAP_B32_e64_gfx1250:
    case AMDGPU::V_PERMLANE16_SWAP_B32_e64_gfx9:
    case AMDGPU::V_PERMLANE32_SWAP_B32_e64_gfx9: {
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::DS_ADD_SRC2_F32_vi:
    case AMDGPU::DS_ADD_SRC2_U32_vi:
    case AMDGPU::DS_ADD_SRC2_U64_vi:
    case AMDGPU::DS_AND_SRC2_B32_vi:
    case AMDGPU::DS_AND_SRC2_B64_vi:
    case AMDGPU::DS_DEC_SRC2_U32_vi:
    case AMDGPU::DS_DEC_SRC2_U64_vi:
    case AMDGPU::DS_INC_SRC2_U32_vi:
    case AMDGPU::DS_INC_SRC2_U64_vi:
    case AMDGPU::DS_MAX_SRC2_F32_vi:
    case AMDGPU::DS_MAX_SRC2_F64_vi:
    case AMDGPU::DS_MAX_SRC2_I32_vi:
    case AMDGPU::DS_MAX_SRC2_I64_vi:
    case AMDGPU::DS_MAX_SRC2_U32_vi:
    case AMDGPU::DS_MAX_SRC2_U64_vi:
    case AMDGPU::DS_MIN_SRC2_F32_vi:
    case AMDGPU::DS_MIN_SRC2_F64_vi:
    case AMDGPU::DS_MIN_SRC2_I32_vi:
    case AMDGPU::DS_MIN_SRC2_I64_vi:
    case AMDGPU::DS_MIN_SRC2_U32_vi:
    case AMDGPU::DS_MIN_SRC2_U64_vi:
    case AMDGPU::DS_OR_SRC2_B32_vi:
    case AMDGPU::DS_OR_SRC2_B64_vi:
    case AMDGPU::DS_RSUB_SRC2_U32_vi:
    case AMDGPU::DS_RSUB_SRC2_U64_vi:
    case AMDGPU::DS_SUB_SRC2_U32_vi:
    case AMDGPU::DS_SUB_SRC2_U64_vi:
    case AMDGPU::DS_WRITE_SRC2_B32_vi:
    case AMDGPU::DS_WRITE_SRC2_B64_vi:
    case AMDGPU::DS_XOR_SRC2_B32_vi:
    case AMDGPU::DS_XOR_SRC2_B64_vi: {
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_WRITE_ADDTID_B32_vi: {
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: data0
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 25, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_ADD_SRC2_F32_gfx10:
    case AMDGPU::DS_ADD_SRC2_U32_gfx10:
    case AMDGPU::DS_ADD_SRC2_U32_gfx6_gfx7:
    case AMDGPU::DS_ADD_SRC2_U64_gfx10:
    case AMDGPU::DS_ADD_SRC2_U64_gfx6_gfx7:
    case AMDGPU::DS_AND_SRC2_B32_gfx10:
    case AMDGPU::DS_AND_SRC2_B32_gfx6_gfx7:
    case AMDGPU::DS_AND_SRC2_B64_gfx10:
    case AMDGPU::DS_AND_SRC2_B64_gfx6_gfx7:
    case AMDGPU::DS_DEC_SRC2_U32_gfx10:
    case AMDGPU::DS_DEC_SRC2_U32_gfx6_gfx7:
    case AMDGPU::DS_DEC_SRC2_U64_gfx10:
    case AMDGPU::DS_DEC_SRC2_U64_gfx6_gfx7:
    case AMDGPU::DS_INC_SRC2_U32_gfx10:
    case AMDGPU::DS_INC_SRC2_U32_gfx6_gfx7:
    case AMDGPU::DS_INC_SRC2_U64_gfx10:
    case AMDGPU::DS_INC_SRC2_U64_gfx6_gfx7:
    case AMDGPU::DS_MAX_SRC2_F32_gfx10:
    case AMDGPU::DS_MAX_SRC2_F32_gfx6_gfx7:
    case AMDGPU::DS_MAX_SRC2_F64_gfx10:
    case AMDGPU::DS_MAX_SRC2_F64_gfx6_gfx7:
    case AMDGPU::DS_MAX_SRC2_I32_gfx10:
    case AMDGPU::DS_MAX_SRC2_I32_gfx6_gfx7:
    case AMDGPU::DS_MAX_SRC2_I64_gfx10:
    case AMDGPU::DS_MAX_SRC2_I64_gfx6_gfx7:
    case AMDGPU::DS_MAX_SRC2_U32_gfx10:
    case AMDGPU::DS_MAX_SRC2_U32_gfx6_gfx7:
    case AMDGPU::DS_MAX_SRC2_U64_gfx10:
    case AMDGPU::DS_MAX_SRC2_U64_gfx6_gfx7:
    case AMDGPU::DS_MIN_SRC2_F32_gfx10:
    case AMDGPU::DS_MIN_SRC2_F32_gfx6_gfx7:
    case AMDGPU::DS_MIN_SRC2_F64_gfx10:
    case AMDGPU::DS_MIN_SRC2_F64_gfx6_gfx7:
    case AMDGPU::DS_MIN_SRC2_I32_gfx10:
    case AMDGPU::DS_MIN_SRC2_I32_gfx6_gfx7:
    case AMDGPU::DS_MIN_SRC2_I64_gfx10:
    case AMDGPU::DS_MIN_SRC2_I64_gfx6_gfx7:
    case AMDGPU::DS_MIN_SRC2_U32_gfx10:
    case AMDGPU::DS_MIN_SRC2_U32_gfx6_gfx7:
    case AMDGPU::DS_MIN_SRC2_U64_gfx10:
    case AMDGPU::DS_MIN_SRC2_U64_gfx6_gfx7:
    case AMDGPU::DS_OR_SRC2_B32_gfx10:
    case AMDGPU::DS_OR_SRC2_B32_gfx6_gfx7:
    case AMDGPU::DS_OR_SRC2_B64_gfx10:
    case AMDGPU::DS_OR_SRC2_B64_gfx6_gfx7:
    case AMDGPU::DS_RSUB_SRC2_U32_gfx10:
    case AMDGPU::DS_RSUB_SRC2_U32_gfx6_gfx7:
    case AMDGPU::DS_RSUB_SRC2_U64_gfx10:
    case AMDGPU::DS_RSUB_SRC2_U64_gfx6_gfx7:
    case AMDGPU::DS_SUB_SRC2_U32_gfx10:
    case AMDGPU::DS_SUB_SRC2_U32_gfx6_gfx7:
    case AMDGPU::DS_SUB_SRC2_U64_gfx10:
    case AMDGPU::DS_SUB_SRC2_U64_gfx6_gfx7:
    case AMDGPU::DS_WRITE_SRC2_B32_gfx10:
    case AMDGPU::DS_WRITE_SRC2_B32_gfx6_gfx7:
    case AMDGPU::DS_WRITE_SRC2_B64_gfx10:
    case AMDGPU::DS_WRITE_SRC2_B64_gfx6_gfx7:
    case AMDGPU::DS_XOR_SRC2_B32_gfx10:
    case AMDGPU::DS_XOR_SRC2_B32_gfx6_gfx7:
    case AMDGPU::DS_XOR_SRC2_B64_gfx10:
    case AMDGPU::DS_XOR_SRC2_B64_gfx6_gfx7: {
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_WRITE_ADDTID_B32_gfx10:
    case AMDGPU::DS_WRITE_ADDTID_B32_gfx11: {
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: data0
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_ADD_F32_vi:
    case AMDGPU::DS_ADD_F32_vi_gfx9:
    case AMDGPU::DS_ADD_F64_vi:
    case AMDGPU::DS_ADD_U32_vi:
    case AMDGPU::DS_ADD_U32_vi_gfx9:
    case AMDGPU::DS_ADD_U64_vi:
    case AMDGPU::DS_ADD_U64_vi_gfx9:
    case AMDGPU::DS_AND_B32_vi:
    case AMDGPU::DS_AND_B32_vi_gfx9:
    case AMDGPU::DS_AND_B64_vi:
    case AMDGPU::DS_AND_B64_vi_gfx9:
    case AMDGPU::DS_DEC_U32_vi:
    case AMDGPU::DS_DEC_U32_vi_gfx9:
    case AMDGPU::DS_DEC_U64_vi:
    case AMDGPU::DS_DEC_U64_vi_gfx9:
    case AMDGPU::DS_INC_U32_vi:
    case AMDGPU::DS_INC_U32_vi_gfx9:
    case AMDGPU::DS_INC_U64_vi:
    case AMDGPU::DS_INC_U64_vi_gfx9:
    case AMDGPU::DS_MAX_F32_vi:
    case AMDGPU::DS_MAX_F32_vi_gfx9:
    case AMDGPU::DS_MAX_F64_vi:
    case AMDGPU::DS_MAX_F64_vi_gfx9:
    case AMDGPU::DS_MAX_I32_vi:
    case AMDGPU::DS_MAX_I32_vi_gfx9:
    case AMDGPU::DS_MAX_I64_vi:
    case AMDGPU::DS_MAX_I64_vi_gfx9:
    case AMDGPU::DS_MAX_U32_vi:
    case AMDGPU::DS_MAX_U32_vi_gfx9:
    case AMDGPU::DS_MAX_U64_vi:
    case AMDGPU::DS_MAX_U64_vi_gfx9:
    case AMDGPU::DS_MIN_F32_vi:
    case AMDGPU::DS_MIN_F32_vi_gfx9:
    case AMDGPU::DS_MIN_F64_vi:
    case AMDGPU::DS_MIN_F64_vi_gfx9:
    case AMDGPU::DS_MIN_I32_vi:
    case AMDGPU::DS_MIN_I32_vi_gfx9:
    case AMDGPU::DS_MIN_I64_vi:
    case AMDGPU::DS_MIN_I64_vi_gfx9:
    case AMDGPU::DS_MIN_U32_vi:
    case AMDGPU::DS_MIN_U32_vi_gfx9:
    case AMDGPU::DS_MIN_U64_vi:
    case AMDGPU::DS_MIN_U64_vi_gfx9:
    case AMDGPU::DS_OR_B32_vi:
    case AMDGPU::DS_OR_B32_vi_gfx9:
    case AMDGPU::DS_OR_B64_vi:
    case AMDGPU::DS_OR_B64_vi_gfx9:
    case AMDGPU::DS_PK_ADD_BF16_vi:
    case AMDGPU::DS_PK_ADD_F16_vi:
    case AMDGPU::DS_RSUB_U32_vi:
    case AMDGPU::DS_RSUB_U32_vi_gfx9:
    case AMDGPU::DS_RSUB_U64_vi:
    case AMDGPU::DS_RSUB_U64_vi_gfx9:
    case AMDGPU::DS_SUB_U32_vi:
    case AMDGPU::DS_SUB_U32_vi_gfx9:
    case AMDGPU::DS_SUB_U64_vi:
    case AMDGPU::DS_SUB_U64_vi_gfx9:
    case AMDGPU::DS_WRITE_B128_vi:
    case AMDGPU::DS_WRITE_B128_vi_gfx9:
    case AMDGPU::DS_WRITE_B16_D16_HI_vi:
    case AMDGPU::DS_WRITE_B16_vi:
    case AMDGPU::DS_WRITE_B16_vi_gfx9:
    case AMDGPU::DS_WRITE_B32_vi:
    case AMDGPU::DS_WRITE_B32_vi_gfx9:
    case AMDGPU::DS_WRITE_B64_vi:
    case AMDGPU::DS_WRITE_B64_vi_gfx9:
    case AMDGPU::DS_WRITE_B8_D16_HI_vi:
    case AMDGPU::DS_WRITE_B8_vi:
    case AMDGPU::DS_WRITE_B8_vi_gfx9:
    case AMDGPU::DS_WRITE_B96_vi:
    case AMDGPU::DS_WRITE_B96_vi_gfx9:
    case AMDGPU::DS_XOR_B32_vi:
    case AMDGPU::DS_XOR_B32_vi_gfx9:
    case AMDGPU::DS_XOR_B64_vi:
    case AMDGPU::DS_XOR_B64_vi_gfx9: {
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: data0
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 25, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_ADD_F32_gfx10:
    case AMDGPU::DS_ADD_F32_gfx11:
    case AMDGPU::DS_ADD_U32_gfx10:
    case AMDGPU::DS_ADD_U32_gfx11:
    case AMDGPU::DS_ADD_U32_gfx6_gfx7:
    case AMDGPU::DS_ADD_U64_gfx10:
    case AMDGPU::DS_ADD_U64_gfx11:
    case AMDGPU::DS_ADD_U64_gfx6_gfx7:
    case AMDGPU::DS_AND_B32_gfx10:
    case AMDGPU::DS_AND_B32_gfx11:
    case AMDGPU::DS_AND_B32_gfx6_gfx7:
    case AMDGPU::DS_AND_B64_gfx10:
    case AMDGPU::DS_AND_B64_gfx11:
    case AMDGPU::DS_AND_B64_gfx6_gfx7:
    case AMDGPU::DS_DEC_U32_gfx10:
    case AMDGPU::DS_DEC_U32_gfx11:
    case AMDGPU::DS_DEC_U32_gfx6_gfx7:
    case AMDGPU::DS_DEC_U64_gfx10:
    case AMDGPU::DS_DEC_U64_gfx11:
    case AMDGPU::DS_DEC_U64_gfx6_gfx7:
    case AMDGPU::DS_INC_U32_gfx10:
    case AMDGPU::DS_INC_U32_gfx11:
    case AMDGPU::DS_INC_U32_gfx6_gfx7:
    case AMDGPU::DS_INC_U64_gfx10:
    case AMDGPU::DS_INC_U64_gfx11:
    case AMDGPU::DS_INC_U64_gfx6_gfx7:
    case AMDGPU::DS_MAX_F32_gfx10:
    case AMDGPU::DS_MAX_F32_gfx11:
    case AMDGPU::DS_MAX_F32_gfx6_gfx7:
    case AMDGPU::DS_MAX_F64_gfx10:
    case AMDGPU::DS_MAX_F64_gfx11:
    case AMDGPU::DS_MAX_F64_gfx6_gfx7:
    case AMDGPU::DS_MAX_I32_gfx10:
    case AMDGPU::DS_MAX_I32_gfx11:
    case AMDGPU::DS_MAX_I32_gfx6_gfx7:
    case AMDGPU::DS_MAX_I64_gfx10:
    case AMDGPU::DS_MAX_I64_gfx11:
    case AMDGPU::DS_MAX_I64_gfx6_gfx7:
    case AMDGPU::DS_MAX_U32_gfx10:
    case AMDGPU::DS_MAX_U32_gfx11:
    case AMDGPU::DS_MAX_U32_gfx6_gfx7:
    case AMDGPU::DS_MAX_U64_gfx10:
    case AMDGPU::DS_MAX_U64_gfx11:
    case AMDGPU::DS_MAX_U64_gfx6_gfx7:
    case AMDGPU::DS_MIN_F32_gfx10:
    case AMDGPU::DS_MIN_F32_gfx11:
    case AMDGPU::DS_MIN_F32_gfx6_gfx7:
    case AMDGPU::DS_MIN_F64_gfx10:
    case AMDGPU::DS_MIN_F64_gfx11:
    case AMDGPU::DS_MIN_F64_gfx6_gfx7:
    case AMDGPU::DS_MIN_I32_gfx10:
    case AMDGPU::DS_MIN_I32_gfx11:
    case AMDGPU::DS_MIN_I32_gfx6_gfx7:
    case AMDGPU::DS_MIN_I64_gfx10:
    case AMDGPU::DS_MIN_I64_gfx11:
    case AMDGPU::DS_MIN_I64_gfx6_gfx7:
    case AMDGPU::DS_MIN_U32_gfx10:
    case AMDGPU::DS_MIN_U32_gfx11:
    case AMDGPU::DS_MIN_U32_gfx6_gfx7:
    case AMDGPU::DS_MIN_U64_gfx10:
    case AMDGPU::DS_MIN_U64_gfx11:
    case AMDGPU::DS_MIN_U64_gfx6_gfx7:
    case AMDGPU::DS_OR_B32_gfx10:
    case AMDGPU::DS_OR_B32_gfx11:
    case AMDGPU::DS_OR_B32_gfx6_gfx7:
    case AMDGPU::DS_OR_B64_gfx10:
    case AMDGPU::DS_OR_B64_gfx11:
    case AMDGPU::DS_OR_B64_gfx6_gfx7:
    case AMDGPU::DS_RSUB_U32_gfx10:
    case AMDGPU::DS_RSUB_U32_gfx11:
    case AMDGPU::DS_RSUB_U32_gfx6_gfx7:
    case AMDGPU::DS_RSUB_U64_gfx10:
    case AMDGPU::DS_RSUB_U64_gfx11:
    case AMDGPU::DS_RSUB_U64_gfx6_gfx7:
    case AMDGPU::DS_SUB_U32_gfx10:
    case AMDGPU::DS_SUB_U32_gfx11:
    case AMDGPU::DS_SUB_U32_gfx6_gfx7:
    case AMDGPU::DS_SUB_U64_gfx10:
    case AMDGPU::DS_SUB_U64_gfx11:
    case AMDGPU::DS_SUB_U64_gfx6_gfx7:
    case AMDGPU::DS_WRITE_B128_gfx10:
    case AMDGPU::DS_WRITE_B128_gfx11:
    case AMDGPU::DS_WRITE_B128_gfx7:
    case AMDGPU::DS_WRITE_B16_D16_HI_gfx10:
    case AMDGPU::DS_WRITE_B16_D16_HI_gfx11:
    case AMDGPU::DS_WRITE_B16_gfx10:
    case AMDGPU::DS_WRITE_B16_gfx11:
    case AMDGPU::DS_WRITE_B16_gfx6_gfx7:
    case AMDGPU::DS_WRITE_B32_gfx10:
    case AMDGPU::DS_WRITE_B32_gfx11:
    case AMDGPU::DS_WRITE_B32_gfx6_gfx7:
    case AMDGPU::DS_WRITE_B64_gfx10:
    case AMDGPU::DS_WRITE_B64_gfx11:
    case AMDGPU::DS_WRITE_B64_gfx6_gfx7:
    case AMDGPU::DS_WRITE_B8_D16_HI_gfx10:
    case AMDGPU::DS_WRITE_B8_D16_HI_gfx11:
    case AMDGPU::DS_WRITE_B8_gfx10:
    case AMDGPU::DS_WRITE_B8_gfx11:
    case AMDGPU::DS_WRITE_B8_gfx6_gfx7:
    case AMDGPU::DS_WRITE_B96_gfx10:
    case AMDGPU::DS_WRITE_B96_gfx11:
    case AMDGPU::DS_WRITE_B96_gfx7:
    case AMDGPU::DS_XOR_B32_gfx10:
    case AMDGPU::DS_XOR_B32_gfx11:
    case AMDGPU::DS_XOR_B32_gfx6_gfx7:
    case AMDGPU::DS_XOR_B64_gfx10:
    case AMDGPU::DS_XOR_B64_gfx11:
    case AMDGPU::DS_XOR_B64_gfx6_gfx7: {
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: data0
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_CMPST_B32_vi:
    case AMDGPU::DS_CMPST_B32_vi_agpr:
    case AMDGPU::DS_CMPST_B32_vi_gfx9:
    case AMDGPU::DS_CMPST_B64_vi:
    case AMDGPU::DS_CMPST_B64_vi_agpr:
    case AMDGPU::DS_CMPST_B64_vi_gfx9:
    case AMDGPU::DS_CMPST_F32_vi:
    case AMDGPU::DS_CMPST_F32_vi_agpr:
    case AMDGPU::DS_CMPST_F32_vi_gfx9:
    case AMDGPU::DS_CMPST_F64_vi:
    case AMDGPU::DS_CMPST_F64_vi_agpr:
    case AMDGPU::DS_CMPST_F64_vi_gfx9:
    case AMDGPU::DS_MSKOR_B32_vi:
    case AMDGPU::DS_MSKOR_B32_vi_agpr:
    case AMDGPU::DS_MSKOR_B32_vi_gfx9:
    case AMDGPU::DS_MSKOR_B64_vi:
    case AMDGPU::DS_MSKOR_B64_vi_agpr:
    case AMDGPU::DS_MSKOR_B64_vi_gfx9: {
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: data0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: data1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_CMPSTORE_B32_gfx11:
    case AMDGPU::DS_CMPSTORE_B64_gfx11:
    case AMDGPU::DS_CMPSTORE_F32_gfx11:
    case AMDGPU::DS_CMPSTORE_F64_gfx11:
    case AMDGPU::DS_CMPST_B32_gfx10:
    case AMDGPU::DS_CMPST_B32_gfx6_gfx7:
    case AMDGPU::DS_CMPST_B64_gfx10:
    case AMDGPU::DS_CMPST_B64_gfx6_gfx7:
    case AMDGPU::DS_CMPST_F32_gfx10:
    case AMDGPU::DS_CMPST_F32_gfx6_gfx7:
    case AMDGPU::DS_CMPST_F64_gfx10:
    case AMDGPU::DS_CMPST_F64_gfx6_gfx7:
    case AMDGPU::DS_MSKOR_B32_gfx10:
    case AMDGPU::DS_MSKOR_B32_gfx11:
    case AMDGPU::DS_MSKOR_B32_gfx6_gfx7:
    case AMDGPU::DS_MSKOR_B64_gfx10:
    case AMDGPU::DS_MSKOR_B64_gfx11:
    case AMDGPU::DS_MSKOR_B64_gfx6_gfx7: {
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: data0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: data1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_WRITE2ST64_B32_vi:
    case AMDGPU::DS_WRITE2ST64_B32_vi_agpr:
    case AMDGPU::DS_WRITE2ST64_B32_vi_gfx9:
    case AMDGPU::DS_WRITE2ST64_B64_vi:
    case AMDGPU::DS_WRITE2ST64_B64_vi_agpr:
    case AMDGPU::DS_WRITE2ST64_B64_vi_gfx9:
    case AMDGPU::DS_WRITE2_B32_vi:
    case AMDGPU::DS_WRITE2_B32_vi_agpr:
    case AMDGPU::DS_WRITE2_B32_vi_gfx9:
    case AMDGPU::DS_WRITE2_B64_vi:
    case AMDGPU::DS_WRITE2_B64_vi_agpr:
    case AMDGPU::DS_WRITE2_B64_vi_gfx9: {
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: data0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: data1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: offset0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: offset1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 8, 8);
      break;
    }
    case AMDGPU::DS_WRITE2ST64_B32_gfx10:
    case AMDGPU::DS_WRITE2ST64_B32_gfx11:
    case AMDGPU::DS_WRITE2ST64_B32_gfx6_gfx7:
    case AMDGPU::DS_WRITE2ST64_B64_gfx10:
    case AMDGPU::DS_WRITE2ST64_B64_gfx11:
    case AMDGPU::DS_WRITE2ST64_B64_gfx6_gfx7:
    case AMDGPU::DS_WRITE2_B32_gfx10:
    case AMDGPU::DS_WRITE2_B32_gfx11:
    case AMDGPU::DS_WRITE2_B32_gfx6_gfx7:
    case AMDGPU::DS_WRITE2_B64_gfx10:
    case AMDGPU::DS_WRITE2_B64_gfx11:
    case AMDGPU::DS_WRITE2_B64_gfx6_gfx7: {
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: data0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: data1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: offset0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: offset1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 8, 8);
      break;
    }
    case AMDGPU::DS_GWS_SEMA_P_gfx10:
    case AMDGPU::DS_GWS_SEMA_P_gfx11:
    case AMDGPU::DS_GWS_SEMA_P_gfx6_gfx7:
    case AMDGPU::DS_GWS_SEMA_P_vi:
    case AMDGPU::DS_GWS_SEMA_RELEASE_ALL_gfx10:
    case AMDGPU::DS_GWS_SEMA_RELEASE_ALL_gfx11:
    case AMDGPU::DS_GWS_SEMA_RELEASE_ALL_gfx7:
    case AMDGPU::DS_GWS_SEMA_RELEASE_ALL_vi:
    case AMDGPU::DS_GWS_SEMA_V_gfx10:
    case AMDGPU::DS_GWS_SEMA_V_gfx11:
    case AMDGPU::DS_GWS_SEMA_V_gfx6_gfx7:
    case AMDGPU::DS_GWS_SEMA_V_vi: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::BUFFER_LOAD_DWORDX3_LDS_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX3_LDS_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_LDS_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX4_LDS_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_LDS_DWORD_gfx90a:
    case AMDGPU::BUFFER_STORE_LDS_DWORD_vi: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 15, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_gfx6_gfx7: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_gfx10: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 15, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORD_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_USHORT_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_DWORD_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_OFFSET_gfx11: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFSET_gfx90a: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_TFE_OFFSET_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_TFE_OFFSET_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_TFE_OFFSET_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_TFE_OFFSET_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_TFE_OFFSET_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_TFE_OFFSET_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_TFE_OFFSET_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_TFE_OFFSET_gfx80: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFSET_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_gfx940:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFSET_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFSET_gfx940:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_gfx90a: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 15, 1);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_vi: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 15, 1);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_LOAD_DWORDX3_LDS_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX3_LDS_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX3_LDS_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX3_LDS_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX3_LDS_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX3_LDS_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_LDS_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX4_LDS_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_LDS_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX4_LDS_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_LDS_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX4_LDS_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_vi: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 15, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORD_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_USHORT_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_BYTE_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORD_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_SHORT_OFFSET_gfx90a: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 15, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_BYTE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_DWORD_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_SHORT_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_OFFSET_vi: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 15, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_gfx6_gfx7: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_CSUB_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_gfx6_gfx7: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_gfx6_gfx7: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_BYTE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORD_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_SHORT_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_OFFSET_gfx6_gfx7: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_gfx10: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 15, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_DWORD_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_OFFSET_gfx10: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 15, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_gfx11: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_CSUB_OFFSET_gfx11: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_gfx11: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: format
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 19, 7);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_gfx6_gfx7: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: format
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 19, 7);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_gfx10: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 15, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: format
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 19, 7);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_gfx90a: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 53, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: format
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 19, 7);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFSET_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_vi: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 53, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: format
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 19, 7);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET_gfx12_format: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 41, 7);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      break;
    }
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_gfx12: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 41, 7);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: format
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 55, 7);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_OFFSET_gfx12_format: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 41, 7);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      break;
    }
    case AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORD_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORD_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_USHORT_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_USHORT_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORD_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORD_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORD_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_OFFEN_gfx11: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFEN_gfx90a: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFSET_RTN_gfx90a: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_TFE_BOTHEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_TFE_IDXEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_TFE_OFFEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_TFE_BOTHEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_TFE_IDXEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_TFE_OFFEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_TFE_BOTHEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_TFE_IDXEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_TFE_OFFEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_TFE_BOTHEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_TFE_IDXEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_TFE_OFFEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_TFE_BOTHEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_TFE_IDXEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_TFE_OFFEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_TFE_BOTHEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_TFE_IDXEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_TFE_OFFEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_TFE_BOTHEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_TFE_IDXEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_TFE_OFFEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_TFE_BOTHEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_TFE_IDXEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_TFE_OFFEN_gfx80: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_BOTHEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_IDXEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_BOTHEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_IDXEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_BOTHEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_IDXEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_IDXEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_IDXEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_gfx90a: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 15, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_vi: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 15, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFSET_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFSET_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFSET_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_gfx90a: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 15, 1);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_vi: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 15, 1);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORD_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORD_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_USHORT_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_USHORT_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_BYTE_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_BYTE_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_BYTE_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORD_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORD_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORD_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_SHORT_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_SHORT_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_SHORT_OFFEN_gfx90a: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 15, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_DWORD_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_DWORD_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_DWORD_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_OFFEN_vi: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 15, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_gfx6_gfx7: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_CSUB_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CSUB_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CSUB_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_gfx6_gfx7: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_gfx6_gfx7: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_CSUB_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_RTN_gfx6_gfx7: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_BYTE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_BYTE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_BYTE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_BYTE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX3_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX4_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORD_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORD_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORD_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORD_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_X_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_SHORT_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_SHORT_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_SHORT_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_SHORT_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_OFFEN_gfx6_gfx7: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORD_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORD_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORD_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_OFFEN_gfx10: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 15, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_gfx11: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_CSUB_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CSUB_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CSUB_OFFEN_gfx11: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_gfx11: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_CSUB_OFFSET_RTN_gfx11: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_gfx11: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: format
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 19, 7);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_ADDR64_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_ADDR64_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_ADDR64_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_ADDR64_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_ADDR64_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_ADDR64_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_ADDR64_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_ADDR64_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_gfx6_gfx7: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: format
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 19, 7);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_gfx10: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 15, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: format
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 19, 7);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_gfx90a: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 53, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: format
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 19, 7);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_IDXEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_vi: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 53, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: format
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 19, 7);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFEN_gfx12_format: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 41, 7);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      break;
    }
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_gfx12: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 41, 7);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: format
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 55, 7);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_OFFEN_gfx12_format: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 41, 7);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN_gfx12_format: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 41, 7);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 53, 2);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_OFFSET_RTN_gfx12_format: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 41, 7);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 53, 2);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFEN_RTN_gfx90a: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_BOTHEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_IDXEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_BOTHEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_IDXEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_BOTHEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_IDXEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_IDXEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_IDXEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_gfx90a: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 15, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_vi: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 15, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_gfx6_gfx7: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_CSUB_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CSUB_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CSUB_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_RTN_gfx6_gfx7: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 54, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_gfx11: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_CSUB_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CSUB_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CSUB_OFFEN_RTN_gfx11: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFEN_RTN_gfx12_format: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 41, 7);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 53, 2);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_OFFEN_RTN_gfx12_format: {
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 41, 7);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 53, 2);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      break;
    }
    case AMDGPU::S_PREFETCH_DATA_PC_REL_gfx12:
    case AMDGPU::S_PREFETCH_INST_PC_REL_gfx12: {
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 32, 24);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      // op: sdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 0), 6, 5);
      break;
    }
    case AMDGPU::TENSOR_LOAD_TO_LDS_D2_gfx1250:
    case AMDGPU::TENSOR_STORE_FROM_LDS_D2_gfx1250: {
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      break;
    }
    case AMDGPU::TENSOR_LOAD_TO_LDS_gfx1250:
    case AMDGPU::TENSOR_STORE_FROM_LDS_gfx1250: {
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 4, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vaddr2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vaddr3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      break;
    }
    case AMDGPU::TENSOR_SAVE_gfx1250: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::FLAT_PREFETCH_B8_SADDR_gfx1250:
    case AMDGPU::GLOBAL_PREFETCH_B8_SADDR_gfx1250: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B128_SADDR_gfx1250:
    case AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B32_SADDR_gfx1250:
    case AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B64_SADDR_gfx1250:
    case AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B8_SADDR_gfx1250: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 55, 8);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::SCRATCH_LOAD_LDS_DWORD_SADDR_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_DWORD_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_LDS_SBYTE_SADDR_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_SBYTE_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_LDS_SSHORT_SADDR_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_SSHORT_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_LDS_UBYTE_SADDR_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_UBYTE_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_LDS_USHORT_SADDR_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_USHORT_SADDR_vi: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::SCRATCH_LOAD_LDS_DWORD_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_SBYTE_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_SSHORT_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_UBYTE_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_USHORT_SADDR_gfx10: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR_gfx12:
    case AMDGPU::SCRATCH_STORE_BYTE_SADDR_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX2_SADDR_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX3_SADDR_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX4_SADDR_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORD_SADDR_gfx12:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR_gfx12:
    case AMDGPU::SCRATCH_STORE_SHORT_SADDR_gfx12: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 55, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::GLOBAL_STORE_DWORD_ADDTID_SADDR_gfx12:
    case AMDGPU::SCRATCH_STORE_BLOCK_SADDR_gfx12: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 55, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORD_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_SSHORT_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_USHORT_SADDR_gfx12: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::FLAT_LOAD_DWORDX2_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_DWORDX3_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_DWORDX4_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_DWORD_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_SBYTE_D16_HI_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_SBYTE_D16_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_SBYTE_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_SHORT_D16_HI_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_SHORT_D16_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_SSHORT_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_UBYTE_D16_HI_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_UBYTE_D16_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_UBYTE_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_USHORT_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_DWORD_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_SBYTE_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_SSHORT_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_UBYTE_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_USHORT_SADDR_gfx12: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::GLOBAL_LOAD_DWORD_ADDTID_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_BLOCK_SADDR_gfx12: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B128_SADDR_gfx1250:
    case AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B32_SADDR_gfx1250:
    case AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B64_SADDR_gfx1250:
    case AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B8_SADDR_gfx1250:
    case AMDGPU::CLUSTER_LOAD_B128_SADDR_gfx1250:
    case AMDGPU::CLUSTER_LOAD_B32_SADDR_gfx1250:
    case AMDGPU::CLUSTER_LOAD_B64_SADDR_gfx1250:
    case AMDGPU::FLAT_LOAD_MONITOR_B128_SADDR_gfx1250:
    case AMDGPU::FLAT_LOAD_MONITOR_B32_SADDR_gfx1250:
    case AMDGPU::FLAT_LOAD_MONITOR_B64_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B128_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B32_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B64_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B8_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_BLOCK_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_MONITOR_B128_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_MONITOR_B32_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_MONITOR_B64_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_TR4_B64_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_TR6_B96_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_TR_B128_w32_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_TR_B128_w32_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_TR_B128_w64_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_TR_B64_w32_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_TR_B64_w32_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_TR_B64_w64_SADDR_gfx12: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORD_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_SSHORT_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_USHORT_SADDR_gfx11: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 14, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORD_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_SBYTE_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_SSHORT_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_UBYTE_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_USHORT_SADDR_gfx10: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_DWORD_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_SBYTE_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_SSHORT_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_UBYTE_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_USHORT_SADDR_vi: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::GLOBAL_LOAD_DWORD_ADDTID_SADDR_gfx11: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 14, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::GLOBAL_LOAD_DWORD_ADDTID_SADDR_gfx10: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SVS_gfx12:
    case AMDGPU::SCRATCH_STORE_BYTE_SVS_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX2_SVS_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX3_SVS_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX4_SVS_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORD_SVS_gfx12:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SVS_gfx12:
    case AMDGPU::SCRATCH_STORE_SHORT_SVS_gfx12: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 55, 8);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_F32_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_ADD_F64_SADDR_gfx1250:
    case AMDGPU::FLAT_ATOMIC_ADD_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_AND_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_AND_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_DEC_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_FMAX_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_FMIN_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_INC_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_INC_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR_gfx1250:
    case AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR_gfx1250:
    case AMDGPU::FLAT_ATOMIC_OR_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_OR_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_BF16_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_F16_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMAX_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMIN_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_SUB_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_SWAP_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMAX_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMIN_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_XOR_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR_gfx12:
    case AMDGPU::FLAT_STORE_BYTE_D16_HI_SADDR_gfx12:
    case AMDGPU::FLAT_STORE_BYTE_SADDR_gfx12:
    case AMDGPU::FLAT_STORE_DWORDX2_SADDR_gfx12:
    case AMDGPU::FLAT_STORE_DWORDX3_SADDR_gfx12:
    case AMDGPU::FLAT_STORE_DWORDX4_SADDR_gfx12:
    case AMDGPU::FLAT_STORE_DWORD_SADDR_gfx12:
    case AMDGPU::FLAT_STORE_SHORT_D16_HI_SADDR_gfx12:
    case AMDGPU::FLAT_STORE_SHORT_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_AND_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_INC_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_OR_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR_gfx12:
    case AMDGPU::GLOBAL_STORE_BYTE_SADDR_gfx12:
    case AMDGPU::GLOBAL_STORE_DWORDX2_SADDR_gfx12:
    case AMDGPU::GLOBAL_STORE_DWORDX3_SADDR_gfx12:
    case AMDGPU::GLOBAL_STORE_DWORDX4_SADDR_gfx12:
    case AMDGPU::GLOBAL_STORE_DWORD_SADDR_gfx12:
    case AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR_gfx12:
    case AMDGPU::GLOBAL_STORE_SHORT_SADDR_gfx12: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 55, 8);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::SCRATCH_STORE_BLOCK_SVS_gfx12: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 55, 8);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::FLAT_ATOMIC_COND_SUB_U32_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_CSUB_U32_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CSUB_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_SADDR_gfx12:
    case AMDGPU::GLOBAL_STORE_BLOCK_SADDR_gfx12: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 55, 8);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::SCRATCH_LOAD_DWORDX2_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORD_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_SSHORT_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_USHORT_SVS_gfx12: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::SCRATCH_LOAD_BLOCK_SVS_gfx12: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_F32_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_ADD_F64_SADDR_RTN_gfx1250:
    case AMDGPU::FLAT_ATOMIC_ADD_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_AND_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_AND_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_COND_SUB_U32_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_CSUB_U32_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_DEC_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_FMAX_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_FMIN_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_INC_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_INC_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR_RTN_gfx1250:
    case AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR_RTN_gfx1250:
    case AMDGPU::FLAT_ATOMIC_OR_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_OR_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_BF16_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_F16_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMAX_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMIN_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SUB_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SWAP_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMAX_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMIN_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_XOR_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_RTN_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CSUB_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_RTN_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_RTN_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_gfx12: {
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 0, 7);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 53, 2);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 55, 8);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::S_DCACHE_DISCARD_IMM_gfx10:
    case AMDGPU::S_DCACHE_DISCARD_IMM_vi:
    case AMDGPU::S_DCACHE_DISCARD_X2_IMM_gfx10:
    case AMDGPU::S_DCACHE_DISCARD_X2_IMM_vi: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(21, 0), 32, 21);
      break;
    }
    case AMDGPU::S_BUFFER_PREFETCH_DATA_gfx12:
    case AMDGPU::S_PREFETCH_DATA_gfx12:
    case AMDGPU::S_PREFETCH_INST_gfx12: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 32, 24);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      // op: sdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 0), 6, 5);
      break;
    }
    case AMDGPU::S_DCACHE_DISCARD_SGPR_IMM_gfx10:
    case AMDGPU::S_DCACHE_DISCARD_SGPR_IMM_gfx9:
    case AMDGPU::S_DCACHE_DISCARD_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_DCACHE_DISCARD_X2_SGPR_IMM_gfx9: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(21, 0), 32, 21);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      break;
    }
    case AMDGPU::S_DCACHE_DISCARD_SGPR_vi:
    case AMDGPU::S_DCACHE_DISCARD_X2_SGPR_vi: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 32, 7);
      break;
    }
    case AMDGPU::S_DCACHE_DISCARD_SGPR_alt_gfx9:
    case AMDGPU::S_DCACHE_DISCARD_SGPR_gfx10:
    case AMDGPU::S_DCACHE_DISCARD_X2_SGPR_alt_gfx9:
    case AMDGPU::S_DCACHE_DISCARD_X2_SGPR_gfx10: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      break;
    }
    case AMDGPU::S_BUFFER_STORE_DWORDX2_IMM_vi:
    case AMDGPU::S_BUFFER_STORE_DWORDX4_IMM_vi:
    case AMDGPU::S_BUFFER_STORE_DWORD_IMM_vi:
    case AMDGPU::S_SCRATCH_STORE_DWORDX2_IMM_vi:
    case AMDGPU::S_SCRATCH_STORE_DWORDX4_IMM_vi:
    case AMDGPU::S_SCRATCH_STORE_DWORD_IMM_vi:
    case AMDGPU::S_STORE_DWORDX2_IMM_vi:
    case AMDGPU::S_STORE_DWORDX4_IMM_vi:
    case AMDGPU::S_STORE_DWORD_IMM_vi: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(21, 0), 32, 21);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: sdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      break;
    }
    case AMDGPU::S_BUFFER_STORE_DWORDX2_IMM_gfx10:
    case AMDGPU::S_BUFFER_STORE_DWORDX4_IMM_gfx10:
    case AMDGPU::S_BUFFER_STORE_DWORD_IMM_gfx10:
    case AMDGPU::S_SCRATCH_STORE_DWORDX2_IMM_gfx10:
    case AMDGPU::S_SCRATCH_STORE_DWORDX4_IMM_gfx10:
    case AMDGPU::S_SCRATCH_STORE_DWORD_IMM_gfx10:
    case AMDGPU::S_STORE_DWORDX2_IMM_gfx10:
    case AMDGPU::S_STORE_DWORDX4_IMM_gfx10:
    case AMDGPU::S_STORE_DWORD_IMM_gfx10: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(21, 0), 32, 21);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 14, 1);
      // op: sdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      break;
    }
    case AMDGPU::S_ATOMIC_ADD_IMM_gfx10:
    case AMDGPU::S_ATOMIC_ADD_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_AND_IMM_gfx10:
    case AMDGPU::S_ATOMIC_AND_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_IMM_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_DEC_IMM_gfx10:
    case AMDGPU::S_ATOMIC_DEC_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_INC_IMM_gfx10:
    case AMDGPU::S_ATOMIC_INC_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_OR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_OR_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SUB_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SUB_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_IMM_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_IMM_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_XOR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_XOR_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_IMM_gfx10: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(21, 0), 32, 21);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 14, 1);
      // op: sdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      break;
    }
    case AMDGPU::S_ATC_PROBE_BUFFER_IMM_gfx10:
    case AMDGPU::S_ATC_PROBE_BUFFER_IMM_gfx11:
    case AMDGPU::S_ATC_PROBE_BUFFER_IMM_vi:
    case AMDGPU::S_ATC_PROBE_IMM_gfx10:
    case AMDGPU::S_ATC_PROBE_IMM_gfx11:
    case AMDGPU::S_ATC_PROBE_IMM_vi:
    case AMDGPU::S_ATOMIC_ADD_IMM_vi:
    case AMDGPU::S_ATOMIC_ADD_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_AND_IMM_vi:
    case AMDGPU::S_ATOMIC_AND_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_CMPSWAP_IMM_vi:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_DEC_IMM_vi:
    case AMDGPU::S_ATOMIC_DEC_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_INC_IMM_vi:
    case AMDGPU::S_ATOMIC_INC_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_OR_IMM_vi:
    case AMDGPU::S_ATOMIC_OR_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_SMAX_IMM_vi:
    case AMDGPU::S_ATOMIC_SMAX_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_SMIN_IMM_vi:
    case AMDGPU::S_ATOMIC_SMIN_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_SUB_IMM_vi:
    case AMDGPU::S_ATOMIC_SUB_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_SWAP_IMM_vi:
    case AMDGPU::S_ATOMIC_SWAP_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_UMAX_IMM_vi:
    case AMDGPU::S_ATOMIC_UMAX_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_UMIN_IMM_vi:
    case AMDGPU::S_ATOMIC_UMIN_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_XOR_IMM_vi:
    case AMDGPU::S_ATOMIC_XOR_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_AND_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_INC_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_OR_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_IMM_vi: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(21, 0), 32, 21);
      // op: sdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      break;
    }
    case AMDGPU::S_ATC_PROBE_BUFFER_IMM_gfx12:
    case AMDGPU::S_ATC_PROBE_IMM_gfx12: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 32, 24);
      // op: sdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 0), 6, 5);
      break;
    }
    case AMDGPU::S_BUFFER_STORE_DWORDX2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_STORE_DWORDX4_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_STORE_DWORD_SGPR_IMM_gfx9:
    case AMDGPU::S_SCRATCH_STORE_DWORDX2_SGPR_IMM_gfx9:
    case AMDGPU::S_SCRATCH_STORE_DWORDX4_SGPR_IMM_gfx9:
    case AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_IMM_gfx9:
    case AMDGPU::S_STORE_DWORDX2_SGPR_IMM_gfx9:
    case AMDGPU::S_STORE_DWORDX4_SGPR_IMM_gfx9:
    case AMDGPU::S_STORE_DWORD_SGPR_IMM_gfx9: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(21, 0), 32, 21);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: sdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      break;
    }
    case AMDGPU::S_BUFFER_STORE_DWORDX2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_STORE_DWORDX4_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_STORE_DWORD_SGPR_IMM_gfx10:
    case AMDGPU::S_SCRATCH_STORE_DWORDX2_SGPR_IMM_gfx10:
    case AMDGPU::S_SCRATCH_STORE_DWORDX4_SGPR_IMM_gfx10:
    case AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_IMM_gfx10:
    case AMDGPU::S_STORE_DWORDX2_SGPR_IMM_gfx10:
    case AMDGPU::S_STORE_DWORDX4_SGPR_IMM_gfx10:
    case AMDGPU::S_STORE_DWORD_SGPR_IMM_gfx10: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(21, 0), 32, 21);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 14, 1);
      // op: sdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      break;
    }
    case AMDGPU::S_ATOMIC_ADD_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_ADD_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_AND_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_AND_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_DEC_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_DEC_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_INC_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_INC_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_OR_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_OR_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SUB_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SUB_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_XOR_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_XOR_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_IMM_gfx10: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(21, 0), 32, 21);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 14, 1);
      // op: sdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      break;
    }
    case AMDGPU::S_ATC_PROBE_BUFFER_SGPR_IMM_gfx10:
    case AMDGPU::S_ATC_PROBE_BUFFER_SGPR_IMM_gfx11:
    case AMDGPU::S_ATC_PROBE_BUFFER_SGPR_IMM_gfx9:
    case AMDGPU::S_ATC_PROBE_SGPR_IMM_gfx10:
    case AMDGPU::S_ATC_PROBE_SGPR_IMM_gfx11:
    case AMDGPU::S_ATC_PROBE_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_ADD_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_ADD_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_AND_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_AND_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_CMPSWAP_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_DEC_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_DEC_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_INC_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_INC_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_OR_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_OR_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_SMAX_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_SMAX_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_SMIN_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_SMIN_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_SUB_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_SUB_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_SWAP_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_SWAP_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_UMAX_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_UMAX_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_UMIN_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_UMIN_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_XOR_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_XOR_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_IMM_gfx9: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(21, 0), 32, 21);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      // op: sdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      break;
    }
    case AMDGPU::S_ATC_PROBE_BUFFER_SGPR_IMM_gfx12:
    case AMDGPU::S_ATC_PROBE_SGPR_IMM_gfx12: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 32, 24);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      // op: sdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 0), 6, 5);
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_B128_IMM_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B256_IMM_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B32_IMM_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B512_IMM_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B64_IMM_gfx11:
    case AMDGPU::S_LOAD_B128_IMM_gfx11:
    case AMDGPU::S_LOAD_B256_IMM_gfx11:
    case AMDGPU::S_LOAD_B32_IMM_gfx11:
    case AMDGPU::S_LOAD_B512_IMM_gfx11:
    case AMDGPU::S_LOAD_B64_IMM_gfx11: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(21, 0), 32, 21);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_vi:
    case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_vi:
    case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_vi:
    case AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_vi:
    case AMDGPU::S_BUFFER_LOAD_DWORD_IMM_vi:
    case AMDGPU::S_LOAD_DWORDX16_IMM_vi:
    case AMDGPU::S_LOAD_DWORDX2_IMM_vi:
    case AMDGPU::S_LOAD_DWORDX4_IMM_vi:
    case AMDGPU::S_LOAD_DWORDX8_IMM_vi:
    case AMDGPU::S_LOAD_DWORD_IMM_vi:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX2_IMM_vi:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX4_IMM_vi:
    case AMDGPU::S_SCRATCH_LOAD_DWORD_IMM_vi: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(21, 0), 32, 21);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORD_IMM_gfx10:
    case AMDGPU::S_LOAD_DWORDX16_IMM_gfx10:
    case AMDGPU::S_LOAD_DWORDX2_IMM_gfx10:
    case AMDGPU::S_LOAD_DWORDX4_IMM_gfx10:
    case AMDGPU::S_LOAD_DWORDX8_IMM_gfx10:
    case AMDGPU::S_LOAD_DWORD_IMM_gfx10:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX2_IMM_gfx10:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX4_IMM_gfx10:
    case AMDGPU::S_SCRATCH_LOAD_DWORD_IMM_gfx10: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(21, 0), 32, 21);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 14, 1);
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_B128_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_B256_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_B32_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_B512_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_B64_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_B96_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_I16_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_I8_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_U16_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_U8_IMM_gfx12:
    case AMDGPU::S_LOAD_B128_IMM_gfx12:
    case AMDGPU::S_LOAD_B256_IMM_gfx12:
    case AMDGPU::S_LOAD_B32_IMM_gfx12:
    case AMDGPU::S_LOAD_B512_IMM_gfx12:
    case AMDGPU::S_LOAD_B64_IMM_gfx12:
    case AMDGPU::S_LOAD_B96_IMM_gfx12:
    case AMDGPU::S_LOAD_I16_IMM_gfx12:
    case AMDGPU::S_LOAD_I8_IMM_gfx12:
    case AMDGPU::S_LOAD_U16_IMM_gfx12:
    case AMDGPU::S_LOAD_U8_IMM_gfx12: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 32, 24);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 56, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 23, 2);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 21, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 20, 1);
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_B128_SGPR_IMM_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B256_SGPR_IMM_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B32_SGPR_IMM_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B512_SGPR_IMM_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B64_SGPR_IMM_gfx11:
    case AMDGPU::S_LOAD_B128_SGPR_IMM_gfx11:
    case AMDGPU::S_LOAD_B256_SGPR_IMM_gfx11:
    case AMDGPU::S_LOAD_B32_SGPR_IMM_gfx11:
    case AMDGPU::S_LOAD_B512_SGPR_IMM_gfx11:
    case AMDGPU::S_LOAD_B64_SGPR_IMM_gfx11: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(21, 0), 32, 21);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM_gfx9:
    case AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_gfx9:
    case AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_gfx9:
    case AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_gfx9:
    case AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_gfx9:
    case AMDGPU::S_LOAD_DWORD_SGPR_IMM_gfx9:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX2_SGPR_IMM_gfx9:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX4_SGPR_IMM_gfx9:
    case AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_IMM_gfx9: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(21, 0), 32, 21);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM_gfx10:
    case AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_gfx10:
    case AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_gfx10:
    case AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_gfx10:
    case AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_gfx10:
    case AMDGPU::S_LOAD_DWORD_SGPR_IMM_gfx10:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX2_SGPR_IMM_gfx10:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX4_SGPR_IMM_gfx10:
    case AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_IMM_gfx10: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(21, 0), 32, 21);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 14, 1);
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_B128_SGPR_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_B256_SGPR_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_B32_SGPR_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_B512_SGPR_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_B64_SGPR_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_B96_SGPR_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_I16_SGPR_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_I8_SGPR_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_U16_SGPR_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_U8_SGPR_IMM_gfx12:
    case AMDGPU::S_LOAD_B128_SGPR_IMM_gfx12:
    case AMDGPU::S_LOAD_B256_SGPR_IMM_gfx12:
    case AMDGPU::S_LOAD_B32_SGPR_IMM_gfx12:
    case AMDGPU::S_LOAD_B512_SGPR_IMM_gfx12:
    case AMDGPU::S_LOAD_B64_SGPR_IMM_gfx12:
    case AMDGPU::S_LOAD_B96_SGPR_IMM_gfx12:
    case AMDGPU::S_LOAD_I16_SGPR_IMM_gfx12:
    case AMDGPU::S_LOAD_I8_SGPR_IMM_gfx12:
    case AMDGPU::S_LOAD_U16_SGPR_IMM_gfx12:
    case AMDGPU::S_LOAD_U8_SGPR_IMM_gfx12: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 32, 24);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 56, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 23, 2);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 21, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 20, 1);
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_vi:
    case AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_vi:
    case AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_vi:
    case AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_vi:
    case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_vi:
    case AMDGPU::S_LOAD_DWORDX16_SGPR_vi:
    case AMDGPU::S_LOAD_DWORDX2_SGPR_vi:
    case AMDGPU::S_LOAD_DWORDX4_SGPR_vi:
    case AMDGPU::S_LOAD_DWORDX8_SGPR_vi:
    case AMDGPU::S_LOAD_DWORD_SGPR_vi:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX2_SGPR_vi:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX4_SGPR_vi:
    case AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_vi: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 32, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_B128_SGPR_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B256_SGPR_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B32_SGPR_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B512_SGPR_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B64_SGPR_gfx11:
    case AMDGPU::S_LOAD_B128_SGPR_gfx11:
    case AMDGPU::S_LOAD_B256_SGPR_gfx11:
    case AMDGPU::S_LOAD_B32_SGPR_gfx11:
    case AMDGPU::S_LOAD_B512_SGPR_gfx11:
    case AMDGPU::S_LOAD_B64_SGPR_gfx11: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_alt_gfx9:
    case AMDGPU::S_LOAD_DWORDX16_SGPR_alt_gfx9:
    case AMDGPU::S_LOAD_DWORDX2_SGPR_alt_gfx9:
    case AMDGPU::S_LOAD_DWORDX4_SGPR_alt_gfx9:
    case AMDGPU::S_LOAD_DWORDX8_SGPR_alt_gfx9:
    case AMDGPU::S_LOAD_DWORD_SGPR_alt_gfx9:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX2_SGPR_alt_gfx9:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX4_SGPR_alt_gfx9:
    case AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_alt_gfx9: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_gfx10:
    case AMDGPU::S_LOAD_DWORDX16_SGPR_gfx10:
    case AMDGPU::S_LOAD_DWORDX2_SGPR_gfx10:
    case AMDGPU::S_LOAD_DWORDX4_SGPR_gfx10:
    case AMDGPU::S_LOAD_DWORDX8_SGPR_gfx10:
    case AMDGPU::S_LOAD_DWORD_SGPR_gfx10:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX2_SGPR_gfx10:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX4_SGPR_gfx10:
    case AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_gfx10: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 14, 1);
      break;
    }
    case AMDGPU::S_BUFFER_STORE_DWORDX2_SGPR_vi:
    case AMDGPU::S_BUFFER_STORE_DWORDX4_SGPR_vi:
    case AMDGPU::S_BUFFER_STORE_DWORD_SGPR_vi:
    case AMDGPU::S_SCRATCH_STORE_DWORDX2_SGPR_vi:
    case AMDGPU::S_SCRATCH_STORE_DWORDX4_SGPR_vi:
    case AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_vi:
    case AMDGPU::S_STORE_DWORDX2_SGPR_vi:
    case AMDGPU::S_STORE_DWORDX4_SGPR_vi:
    case AMDGPU::S_STORE_DWORD_SGPR_vi: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 32, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: sdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      break;
    }
    case AMDGPU::S_ATC_PROBE_BUFFER_SGPR_vi:
    case AMDGPU::S_ATC_PROBE_SGPR_vi:
    case AMDGPU::S_ATOMIC_ADD_SGPR_vi:
    case AMDGPU::S_ATOMIC_ADD_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_AND_SGPR_vi:
    case AMDGPU::S_ATOMIC_AND_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_CMPSWAP_SGPR_vi:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_DEC_SGPR_vi:
    case AMDGPU::S_ATOMIC_DEC_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_INC_SGPR_vi:
    case AMDGPU::S_ATOMIC_INC_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_OR_SGPR_vi:
    case AMDGPU::S_ATOMIC_OR_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_SMAX_SGPR_vi:
    case AMDGPU::S_ATOMIC_SMAX_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_SMIN_SGPR_vi:
    case AMDGPU::S_ATOMIC_SMIN_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_SUB_SGPR_vi:
    case AMDGPU::S_ATOMIC_SUB_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_SWAP_SGPR_vi:
    case AMDGPU::S_ATOMIC_SWAP_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_UMAX_SGPR_vi:
    case AMDGPU::S_ATOMIC_UMAX_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_UMIN_SGPR_vi:
    case AMDGPU::S_ATOMIC_UMIN_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_XOR_SGPR_vi:
    case AMDGPU::S_ATOMIC_XOR_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_vi: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 32, 7);
      // op: sdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      break;
    }
    case AMDGPU::S_BUFFER_STORE_DWORDX2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_STORE_DWORDX4_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_STORE_DWORD_SGPR_alt_gfx9:
    case AMDGPU::S_SCRATCH_STORE_DWORDX2_SGPR_alt_gfx9:
    case AMDGPU::S_SCRATCH_STORE_DWORDX4_SGPR_alt_gfx9:
    case AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_alt_gfx9:
    case AMDGPU::S_STORE_DWORDX2_SGPR_alt_gfx9:
    case AMDGPU::S_STORE_DWORDX4_SGPR_alt_gfx9:
    case AMDGPU::S_STORE_DWORD_SGPR_alt_gfx9: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: sdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      break;
    }
    case AMDGPU::S_BUFFER_STORE_DWORDX2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_STORE_DWORDX4_SGPR_gfx10:
    case AMDGPU::S_BUFFER_STORE_DWORD_SGPR_gfx10:
    case AMDGPU::S_SCRATCH_STORE_DWORDX2_SGPR_gfx10:
    case AMDGPU::S_SCRATCH_STORE_DWORDX4_SGPR_gfx10:
    case AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_gfx10:
    case AMDGPU::S_STORE_DWORDX2_SGPR_gfx10:
    case AMDGPU::S_STORE_DWORDX4_SGPR_gfx10:
    case AMDGPU::S_STORE_DWORD_SGPR_gfx10: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 14, 1);
      // op: sdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      break;
    }
    case AMDGPU::S_ATOMIC_ADD_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_ADD_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_AND_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_AND_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_DEC_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_DEC_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_INC_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_INC_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_OR_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_OR_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_SUB_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_SUB_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_XOR_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_XOR_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_gfx10: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 14, 1);
      // op: sdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      break;
    }
    case AMDGPU::S_ATC_PROBE_BUFFER_SGPR_alt_gfx9:
    case AMDGPU::S_ATC_PROBE_BUFFER_SGPR_gfx10:
    case AMDGPU::S_ATC_PROBE_BUFFER_SGPR_gfx11:
    case AMDGPU::S_ATC_PROBE_SGPR_alt_gfx9:
    case AMDGPU::S_ATC_PROBE_SGPR_gfx10:
    case AMDGPU::S_ATC_PROBE_SGPR_gfx11:
    case AMDGPU::S_ATOMIC_ADD_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_ADD_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_AND_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_AND_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_CMPSWAP_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_DEC_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_DEC_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_INC_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_INC_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_OR_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_OR_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_SMAX_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_SMAX_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_SMIN_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_SMIN_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_SUB_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_SUB_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_SWAP_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_SWAP_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_UMAX_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_UMAX_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_UMIN_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_UMIN_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_XOR_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_XOR_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_alt_gfx9: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      // op: sdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_ci:
    case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_ci:
    case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_ci:
    case AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_ci:
    case AMDGPU::S_BUFFER_LOAD_DWORD_IMM_ci:
    case AMDGPU::S_LOAD_DWORDX16_IMM_ci:
    case AMDGPU::S_LOAD_DWORDX2_IMM_ci:
    case AMDGPU::S_LOAD_DWORDX4_IMM_ci:
    case AMDGPU::S_LOAD_DWORDX8_IMM_ci:
    case AMDGPU::S_LOAD_DWORD_IMM_ci: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 9, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 15, 7);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(32, 0), 32, 32);
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_si:
    case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_si:
    case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_si:
    case AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_si:
    case AMDGPU::S_BUFFER_LOAD_DWORD_IMM_si:
    case AMDGPU::S_LOAD_DWORDX16_IMM_si:
    case AMDGPU::S_LOAD_DWORDX2_IMM_si:
    case AMDGPU::S_LOAD_DWORDX4_IMM_si:
    case AMDGPU::S_LOAD_DWORDX8_IMM_si:
    case AMDGPU::S_LOAD_DWORD_IMM_si: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 9, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 15, 7);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_si:
    case AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_si:
    case AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_si:
    case AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_si:
    case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_si:
    case AMDGPU::S_LOAD_DWORDX16_SGPR_si:
    case AMDGPU::S_LOAD_DWORDX2_SGPR_si:
    case AMDGPU::S_LOAD_DWORDX4_SGPR_si:
    case AMDGPU::S_LOAD_DWORDX8_SGPR_si:
    case AMDGPU::S_LOAD_DWORD_SGPR_si: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 9, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 15, 7);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::S_ATOMIC_ADD_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_ADD_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_AND_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_AND_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_CMPSWAP_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_DEC_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_DEC_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_INC_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_INC_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_OR_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_OR_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_SMAX_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_SMAX_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_SMIN_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_SMIN_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_SUB_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_SUB_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_SWAP_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_SWAP_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_UMAX_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_UMAX_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_UMIN_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_UMIN_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_XOR_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_XOR_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_AND_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_INC_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_OR_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_IMM_RTN_vi: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(21, 0), 32, 21);
      break;
    }
    case AMDGPU::S_ATOMIC_ADD_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_ADD_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_AND_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_AND_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_DEC_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_DEC_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_INC_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_INC_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_OR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_OR_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SUB_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SUB_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_XOR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_XOR_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_IMM_RTN_gfx10: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(21, 0), 32, 21);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 14, 1);
      break;
    }
    case AMDGPU::S_ATOMIC_ADD_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_ADD_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_AND_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_AND_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_CMPSWAP_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_DEC_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_DEC_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_INC_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_INC_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_OR_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_OR_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_SMAX_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_SMAX_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_SMIN_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_SMIN_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_SUB_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_SUB_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_SWAP_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_SWAP_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_UMAX_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_UMAX_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_UMIN_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_UMIN_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_XOR_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_XOR_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_IMM_RTN_gfx9: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(21, 0), 32, 21);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      break;
    }
    case AMDGPU::S_ATOMIC_ADD_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_ADD_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_AND_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_AND_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_DEC_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_DEC_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_INC_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_INC_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_OR_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_OR_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SUB_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SUB_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_XOR_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_XOR_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_IMM_RTN_gfx10: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      // op: offset
      op.clearAllBits();
      getSMEMOffsetEncoding(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(21, 0), 32, 21);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 14, 1);
      break;
    }
    case AMDGPU::S_ATOMIC_ADD_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_ADD_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_AND_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_AND_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_CMPSWAP_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_DEC_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_DEC_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_INC_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_INC_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_OR_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_OR_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_SMAX_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_SMAX_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_SMIN_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_SMIN_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_SUB_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_SUB_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_SWAP_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_SWAP_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_UMAX_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_UMAX_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_UMIN_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_UMIN_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_XOR_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_XOR_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_RTN_vi: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 32, 7);
      break;
    }
    case AMDGPU::S_ATOMIC_ADD_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_ADD_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_AND_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_AND_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_CMPSWAP_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_DEC_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_DEC_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_INC_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_INC_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_OR_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_OR_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_SMAX_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_SMAX_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_SMIN_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_SMIN_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_SUB_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_SUB_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_SWAP_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_SWAP_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_UMAX_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_UMAX_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_UMIN_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_UMIN_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_XOR_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_XOR_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_RTN_alt_gfx9: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      break;
    }
    case AMDGPU::S_ATOMIC_ADD_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_ADD_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_AND_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_AND_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_DEC_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_DEC_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_INC_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_INC_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_OR_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_OR_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SUB_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SUB_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_XOR_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_XOR_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_RTN_gfx10: {
      // op: sbase
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 1), 0, 6);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      // op: soffset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 57, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 14, 1);
      break;
    }
    case AMDGPU::S_MEMTIME_si: {
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 15, 7);
      break;
    }
    case AMDGPU::S_GETPC_B64_gfx10:
    case AMDGPU::S_GETPC_B64_gfx11:
    case AMDGPU::S_GETPC_B64_gfx12:
    case AMDGPU::S_GETPC_B64_gfx1250:
    case AMDGPU::S_GETPC_B64_gfx6_gfx7:
    case AMDGPU::S_GETPC_B64_vi:
    case AMDGPU::S_GET_BARRIER_STATE_M0_gfx12:
    case AMDGPU::S_GET_SHADER_CYCLES_U64_gfx12: {
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 16, 7);
      break;
    }
    case AMDGPU::S_CMOVK_I32_gfx10:
    case AMDGPU::S_CMOVK_I32_gfx11:
    case AMDGPU::S_CMOVK_I32_gfx12:
    case AMDGPU::S_CMOVK_I32_gfx6_gfx7:
    case AMDGPU::S_CMOVK_I32_vi:
    case AMDGPU::S_CMPK_EQ_I32_gfx10:
    case AMDGPU::S_CMPK_EQ_I32_gfx11:
    case AMDGPU::S_CMPK_EQ_I32_gfx6_gfx7:
    case AMDGPU::S_CMPK_EQ_I32_vi:
    case AMDGPU::S_CMPK_EQ_U32_gfx10:
    case AMDGPU::S_CMPK_EQ_U32_gfx11:
    case AMDGPU::S_CMPK_EQ_U32_gfx6_gfx7:
    case AMDGPU::S_CMPK_EQ_U32_vi:
    case AMDGPU::S_CMPK_GE_I32_gfx10:
    case AMDGPU::S_CMPK_GE_I32_gfx11:
    case AMDGPU::S_CMPK_GE_I32_gfx6_gfx7:
    case AMDGPU::S_CMPK_GE_I32_vi:
    case AMDGPU::S_CMPK_GE_U32_gfx10:
    case AMDGPU::S_CMPK_GE_U32_gfx11:
    case AMDGPU::S_CMPK_GE_U32_gfx6_gfx7:
    case AMDGPU::S_CMPK_GE_U32_vi:
    case AMDGPU::S_CMPK_GT_I32_gfx10:
    case AMDGPU::S_CMPK_GT_I32_gfx11:
    case AMDGPU::S_CMPK_GT_I32_gfx6_gfx7:
    case AMDGPU::S_CMPK_GT_I32_vi:
    case AMDGPU::S_CMPK_GT_U32_gfx10:
    case AMDGPU::S_CMPK_GT_U32_gfx11:
    case AMDGPU::S_CMPK_GT_U32_gfx6_gfx7:
    case AMDGPU::S_CMPK_GT_U32_vi:
    case AMDGPU::S_CMPK_LE_I32_gfx10:
    case AMDGPU::S_CMPK_LE_I32_gfx11:
    case AMDGPU::S_CMPK_LE_I32_gfx6_gfx7:
    case AMDGPU::S_CMPK_LE_I32_vi:
    case AMDGPU::S_CMPK_LE_U32_gfx10:
    case AMDGPU::S_CMPK_LE_U32_gfx11:
    case AMDGPU::S_CMPK_LE_U32_gfx6_gfx7:
    case AMDGPU::S_CMPK_LE_U32_vi:
    case AMDGPU::S_CMPK_LG_I32_gfx10:
    case AMDGPU::S_CMPK_LG_I32_gfx11:
    case AMDGPU::S_CMPK_LG_I32_gfx6_gfx7:
    case AMDGPU::S_CMPK_LG_I32_vi:
    case AMDGPU::S_CMPK_LG_U32_gfx10:
    case AMDGPU::S_CMPK_LG_U32_gfx11:
    case AMDGPU::S_CMPK_LG_U32_gfx6_gfx7:
    case AMDGPU::S_CMPK_LG_U32_vi:
    case AMDGPU::S_CMPK_LT_I32_gfx10:
    case AMDGPU::S_CMPK_LT_I32_gfx11:
    case AMDGPU::S_CMPK_LT_I32_gfx6_gfx7:
    case AMDGPU::S_CMPK_LT_I32_vi:
    case AMDGPU::S_CMPK_LT_U32_gfx10:
    case AMDGPU::S_CMPK_LT_U32_gfx11:
    case AMDGPU::S_CMPK_LT_U32_gfx6_gfx7:
    case AMDGPU::S_CMPK_LT_U32_vi:
    case AMDGPU::S_GETREG_B32_gfx10:
    case AMDGPU::S_GETREG_B32_gfx11:
    case AMDGPU::S_GETREG_B32_gfx12:
    case AMDGPU::S_GETREG_B32_gfx6_gfx7:
    case AMDGPU::S_GETREG_B32_vi:
    case AMDGPU::S_MOVK_I32_gfx10:
    case AMDGPU::S_MOVK_I32_gfx11:
    case AMDGPU::S_MOVK_I32_gfx12:
    case AMDGPU::S_MOVK_I32_gfx6_gfx7:
    case AMDGPU::S_MOVK_I32_vi:
    case AMDGPU::S_SETREG_B32_gfx10:
    case AMDGPU::S_SETREG_B32_gfx11:
    case AMDGPU::S_SETREG_B32_gfx12:
    case AMDGPU::S_SETREG_B32_gfx6_gfx7:
    case AMDGPU::S_SETREG_B32_vi:
    case AMDGPU::S_WAITCNT_EXPCNT_gfx10:
    case AMDGPU::S_WAITCNT_EXPCNT_gfx11:
    case AMDGPU::S_WAITCNT_LGKMCNT_gfx10:
    case AMDGPU::S_WAITCNT_LGKMCNT_gfx11:
    case AMDGPU::S_WAITCNT_VMCNT_gfx10:
    case AMDGPU::S_WAITCNT_VMCNT_gfx11:
    case AMDGPU::S_WAITCNT_VSCNT_gfx10:
    case AMDGPU::S_WAITCNT_VSCNT_gfx11: {
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 16, 7);
      // op: simm16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::S_ADDK_I32_gfx10:
    case AMDGPU::S_ADDK_I32_gfx11:
    case AMDGPU::S_ADDK_I32_gfx12:
    case AMDGPU::S_ADDK_I32_gfx6_gfx7:
    case AMDGPU::S_ADDK_I32_vi:
    case AMDGPU::S_MULK_I32_gfx10:
    case AMDGPU::S_MULK_I32_gfx11:
    case AMDGPU::S_MULK_I32_gfx12:
    case AMDGPU::S_MULK_I32_gfx6_gfx7:
    case AMDGPU::S_MULK_I32_vi: {
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 16, 7);
      // op: simm16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::S_CALL_B64_gfx10:
    case AMDGPU::S_CALL_B64_gfx11:
    case AMDGPU::S_CALL_B64_gfx12:
    case AMDGPU::S_CALL_B64_gfx1250:
    case AMDGPU::S_CALL_B64_vi:
    case AMDGPU::S_CBRANCH_I_FORK_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_I_FORK_vi: {
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 16, 7);
      // op: simm16
      op.clearAllBits();
      getSOPPBrEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::S_ABS_I32_gfx10:
    case AMDGPU::S_ABS_I32_gfx11:
    case AMDGPU::S_ABS_I32_gfx12:
    case AMDGPU::S_ABS_I32_gfx6_gfx7:
    case AMDGPU::S_ABS_I32_vi:
    case AMDGPU::S_ANDN1_SAVEEXEC_B32_gfx10:
    case AMDGPU::S_ANDN1_SAVEEXEC_B32_gfx11:
    case AMDGPU::S_ANDN1_SAVEEXEC_B32_gfx12:
    case AMDGPU::S_ANDN1_SAVEEXEC_B64_gfx10:
    case AMDGPU::S_ANDN1_SAVEEXEC_B64_gfx11:
    case AMDGPU::S_ANDN1_SAVEEXEC_B64_gfx12:
    case AMDGPU::S_ANDN1_SAVEEXEC_B64_vi:
    case AMDGPU::S_ANDN1_WREXEC_B32_gfx10:
    case AMDGPU::S_ANDN1_WREXEC_B32_gfx11:
    case AMDGPU::S_ANDN1_WREXEC_B32_gfx12:
    case AMDGPU::S_ANDN1_WREXEC_B64_gfx10:
    case AMDGPU::S_ANDN1_WREXEC_B64_gfx11:
    case AMDGPU::S_ANDN1_WREXEC_B64_gfx12:
    case AMDGPU::S_ANDN1_WREXEC_B64_vi:
    case AMDGPU::S_ANDN2_SAVEEXEC_B32_gfx10:
    case AMDGPU::S_ANDN2_SAVEEXEC_B32_gfx11:
    case AMDGPU::S_ANDN2_SAVEEXEC_B32_gfx12:
    case AMDGPU::S_ANDN2_SAVEEXEC_B64_gfx10:
    case AMDGPU::S_ANDN2_SAVEEXEC_B64_gfx11:
    case AMDGPU::S_ANDN2_SAVEEXEC_B64_gfx12:
    case AMDGPU::S_ANDN2_SAVEEXEC_B64_gfx6_gfx7:
    case AMDGPU::S_ANDN2_SAVEEXEC_B64_vi:
    case AMDGPU::S_ANDN2_WREXEC_B32_gfx10:
    case AMDGPU::S_ANDN2_WREXEC_B32_gfx11:
    case AMDGPU::S_ANDN2_WREXEC_B32_gfx12:
    case AMDGPU::S_ANDN2_WREXEC_B64_gfx10:
    case AMDGPU::S_ANDN2_WREXEC_B64_gfx11:
    case AMDGPU::S_ANDN2_WREXEC_B64_gfx12:
    case AMDGPU::S_ANDN2_WREXEC_B64_vi:
    case AMDGPU::S_AND_SAVEEXEC_B32_gfx10:
    case AMDGPU::S_AND_SAVEEXEC_B32_gfx11:
    case AMDGPU::S_AND_SAVEEXEC_B32_gfx12:
    case AMDGPU::S_AND_SAVEEXEC_B64_gfx10:
    case AMDGPU::S_AND_SAVEEXEC_B64_gfx11:
    case AMDGPU::S_AND_SAVEEXEC_B64_gfx12:
    case AMDGPU::S_AND_SAVEEXEC_B64_gfx6_gfx7:
    case AMDGPU::S_AND_SAVEEXEC_B64_vi:
    case AMDGPU::S_BCNT0_I32_B32_gfx10:
    case AMDGPU::S_BCNT0_I32_B32_gfx11:
    case AMDGPU::S_BCNT0_I32_B32_gfx12:
    case AMDGPU::S_BCNT0_I32_B32_gfx6_gfx7:
    case AMDGPU::S_BCNT0_I32_B32_vi:
    case AMDGPU::S_BCNT0_I32_B64_gfx10:
    case AMDGPU::S_BCNT0_I32_B64_gfx11:
    case AMDGPU::S_BCNT0_I32_B64_gfx12:
    case AMDGPU::S_BCNT0_I32_B64_gfx6_gfx7:
    case AMDGPU::S_BCNT0_I32_B64_vi:
    case AMDGPU::S_BCNT1_I32_B32_gfx10:
    case AMDGPU::S_BCNT1_I32_B32_gfx11:
    case AMDGPU::S_BCNT1_I32_B32_gfx12:
    case AMDGPU::S_BCNT1_I32_B32_gfx6_gfx7:
    case AMDGPU::S_BCNT1_I32_B32_vi:
    case AMDGPU::S_BCNT1_I32_B64_gfx10:
    case AMDGPU::S_BCNT1_I32_B64_gfx11:
    case AMDGPU::S_BCNT1_I32_B64_gfx12:
    case AMDGPU::S_BCNT1_I32_B64_gfx6_gfx7:
    case AMDGPU::S_BCNT1_I32_B64_vi:
    case AMDGPU::S_BITREPLICATE_B64_B32_gfx10:
    case AMDGPU::S_BITREPLICATE_B64_B32_gfx11:
    case AMDGPU::S_BITREPLICATE_B64_B32_gfx12:
    case AMDGPU::S_BITREPLICATE_B64_B32_vi:
    case AMDGPU::S_BITSET0_B32_gfx10:
    case AMDGPU::S_BITSET0_B32_gfx11:
    case AMDGPU::S_BITSET0_B32_gfx12:
    case AMDGPU::S_BITSET0_B32_gfx6_gfx7:
    case AMDGPU::S_BITSET0_B32_vi:
    case AMDGPU::S_BITSET0_B64_gfx10:
    case AMDGPU::S_BITSET0_B64_gfx11:
    case AMDGPU::S_BITSET0_B64_gfx12:
    case AMDGPU::S_BITSET0_B64_gfx6_gfx7:
    case AMDGPU::S_BITSET0_B64_vi:
    case AMDGPU::S_BITSET1_B32_gfx10:
    case AMDGPU::S_BITSET1_B32_gfx11:
    case AMDGPU::S_BITSET1_B32_gfx12:
    case AMDGPU::S_BITSET1_B32_gfx6_gfx7:
    case AMDGPU::S_BITSET1_B32_vi:
    case AMDGPU::S_BITSET1_B64_gfx10:
    case AMDGPU::S_BITSET1_B64_gfx11:
    case AMDGPU::S_BITSET1_B64_gfx12:
    case AMDGPU::S_BITSET1_B64_gfx6_gfx7:
    case AMDGPU::S_BITSET1_B64_vi:
    case AMDGPU::S_BREV_B32_gfx10:
    case AMDGPU::S_BREV_B32_gfx11:
    case AMDGPU::S_BREV_B32_gfx12:
    case AMDGPU::S_BREV_B32_gfx6_gfx7:
    case AMDGPU::S_BREV_B32_vi:
    case AMDGPU::S_BREV_B64_gfx10:
    case AMDGPU::S_BREV_B64_gfx11:
    case AMDGPU::S_BREV_B64_gfx12:
    case AMDGPU::S_BREV_B64_gfx6_gfx7:
    case AMDGPU::S_BREV_B64_vi:
    case AMDGPU::S_CEIL_F16_gfx11:
    case AMDGPU::S_CEIL_F16_gfx12:
    case AMDGPU::S_CEIL_F32_gfx11:
    case AMDGPU::S_CEIL_F32_gfx12:
    case AMDGPU::S_CMOV_B32_gfx10:
    case AMDGPU::S_CMOV_B32_gfx11:
    case AMDGPU::S_CMOV_B32_gfx12:
    case AMDGPU::S_CMOV_B32_gfx6_gfx7:
    case AMDGPU::S_CMOV_B32_vi:
    case AMDGPU::S_CMOV_B64_gfx10:
    case AMDGPU::S_CMOV_B64_gfx11:
    case AMDGPU::S_CMOV_B64_gfx12:
    case AMDGPU::S_CMOV_B64_gfx6_gfx7:
    case AMDGPU::S_CMOV_B64_vi:
    case AMDGPU::S_CVT_F16_F32_gfx11:
    case AMDGPU::S_CVT_F16_F32_gfx12:
    case AMDGPU::S_CVT_F32_F16_gfx11:
    case AMDGPU::S_CVT_F32_F16_gfx12:
    case AMDGPU::S_CVT_F32_I32_gfx11:
    case AMDGPU::S_CVT_F32_I32_gfx12:
    case AMDGPU::S_CVT_F32_U32_gfx11:
    case AMDGPU::S_CVT_F32_U32_gfx12:
    case AMDGPU::S_CVT_HI_F32_F16_gfx11:
    case AMDGPU::S_CVT_HI_F32_F16_gfx12:
    case AMDGPU::S_CVT_I32_F32_gfx11:
    case AMDGPU::S_CVT_I32_F32_gfx12:
    case AMDGPU::S_CVT_U32_F32_gfx11:
    case AMDGPU::S_CVT_U32_F32_gfx12:
    case AMDGPU::S_FF0_I32_B32_gfx10:
    case AMDGPU::S_FF0_I32_B32_gfx6_gfx7:
    case AMDGPU::S_FF0_I32_B32_vi:
    case AMDGPU::S_FF0_I32_B64_gfx10:
    case AMDGPU::S_FF0_I32_B64_gfx6_gfx7:
    case AMDGPU::S_FF0_I32_B64_vi:
    case AMDGPU::S_FF1_I32_B32_gfx10:
    case AMDGPU::S_FF1_I32_B32_gfx11:
    case AMDGPU::S_FF1_I32_B32_gfx12:
    case AMDGPU::S_FF1_I32_B32_gfx6_gfx7:
    case AMDGPU::S_FF1_I32_B32_vi:
    case AMDGPU::S_FF1_I32_B64_gfx10:
    case AMDGPU::S_FF1_I32_B64_gfx11:
    case AMDGPU::S_FF1_I32_B64_gfx12:
    case AMDGPU::S_FF1_I32_B64_gfx6_gfx7:
    case AMDGPU::S_FF1_I32_B64_vi:
    case AMDGPU::S_FLBIT_I32_B32_gfx10:
    case AMDGPU::S_FLBIT_I32_B32_gfx11:
    case AMDGPU::S_FLBIT_I32_B32_gfx12:
    case AMDGPU::S_FLBIT_I32_B32_gfx6_gfx7:
    case AMDGPU::S_FLBIT_I32_B32_vi:
    case AMDGPU::S_FLBIT_I32_B64_gfx10:
    case AMDGPU::S_FLBIT_I32_B64_gfx11:
    case AMDGPU::S_FLBIT_I32_B64_gfx12:
    case AMDGPU::S_FLBIT_I32_B64_gfx6_gfx7:
    case AMDGPU::S_FLBIT_I32_B64_vi:
    case AMDGPU::S_FLBIT_I32_I64_gfx10:
    case AMDGPU::S_FLBIT_I32_I64_gfx11:
    case AMDGPU::S_FLBIT_I32_I64_gfx12:
    case AMDGPU::S_FLBIT_I32_I64_gfx6_gfx7:
    case AMDGPU::S_FLBIT_I32_I64_vi:
    case AMDGPU::S_FLBIT_I32_gfx10:
    case AMDGPU::S_FLBIT_I32_gfx11:
    case AMDGPU::S_FLBIT_I32_gfx12:
    case AMDGPU::S_FLBIT_I32_gfx6_gfx7:
    case AMDGPU::S_FLBIT_I32_vi:
    case AMDGPU::S_FLOOR_F16_gfx11:
    case AMDGPU::S_FLOOR_F16_gfx12:
    case AMDGPU::S_FLOOR_F32_gfx11:
    case AMDGPU::S_FLOOR_F32_gfx12:
    case AMDGPU::S_GET_BARRIER_STATE_IMM_gfx12:
    case AMDGPU::S_MOVRELD_B32_gfx10:
    case AMDGPU::S_MOVRELD_B32_gfx11:
    case AMDGPU::S_MOVRELD_B32_gfx12:
    case AMDGPU::S_MOVRELD_B32_gfx6_gfx7:
    case AMDGPU::S_MOVRELD_B32_vi:
    case AMDGPU::S_MOVRELD_B64_gfx10:
    case AMDGPU::S_MOVRELD_B64_gfx11:
    case AMDGPU::S_MOVRELD_B64_gfx12:
    case AMDGPU::S_MOVRELD_B64_gfx6_gfx7:
    case AMDGPU::S_MOVRELD_B64_vi:
    case AMDGPU::S_MOVRELSD_2_B32_gfx10:
    case AMDGPU::S_MOVRELSD_2_B32_gfx11:
    case AMDGPU::S_MOVRELSD_2_B32_gfx12:
    case AMDGPU::S_MOVRELS_B32_gfx10:
    case AMDGPU::S_MOVRELS_B32_gfx11:
    case AMDGPU::S_MOVRELS_B32_gfx12:
    case AMDGPU::S_MOVRELS_B32_gfx6_gfx7:
    case AMDGPU::S_MOVRELS_B32_vi:
    case AMDGPU::S_MOVRELS_B64_gfx10:
    case AMDGPU::S_MOVRELS_B64_gfx11:
    case AMDGPU::S_MOVRELS_B64_gfx12:
    case AMDGPU::S_MOVRELS_B64_gfx6_gfx7:
    case AMDGPU::S_MOVRELS_B64_vi:
    case AMDGPU::S_MOV_B32_gfx10:
    case AMDGPU::S_MOV_B32_gfx11:
    case AMDGPU::S_MOV_B32_gfx12:
    case AMDGPU::S_MOV_B32_gfx6_gfx7:
    case AMDGPU::S_MOV_B32_vi:
    case AMDGPU::S_MOV_B64_gfx10:
    case AMDGPU::S_MOV_B64_gfx11:
    case AMDGPU::S_MOV_B64_gfx12:
    case AMDGPU::S_MOV_B64_gfx6_gfx7:
    case AMDGPU::S_MOV_B64_vi:
    case AMDGPU::S_NAND_SAVEEXEC_B32_gfx10:
    case AMDGPU::S_NAND_SAVEEXEC_B32_gfx11:
    case AMDGPU::S_NAND_SAVEEXEC_B32_gfx12:
    case AMDGPU::S_NAND_SAVEEXEC_B64_gfx10:
    case AMDGPU::S_NAND_SAVEEXEC_B64_gfx11:
    case AMDGPU::S_NAND_SAVEEXEC_B64_gfx12:
    case AMDGPU::S_NAND_SAVEEXEC_B64_gfx6_gfx7:
    case AMDGPU::S_NAND_SAVEEXEC_B64_vi:
    case AMDGPU::S_NOR_SAVEEXEC_B32_gfx10:
    case AMDGPU::S_NOR_SAVEEXEC_B32_gfx11:
    case AMDGPU::S_NOR_SAVEEXEC_B32_gfx12:
    case AMDGPU::S_NOR_SAVEEXEC_B64_gfx10:
    case AMDGPU::S_NOR_SAVEEXEC_B64_gfx11:
    case AMDGPU::S_NOR_SAVEEXEC_B64_gfx12:
    case AMDGPU::S_NOR_SAVEEXEC_B64_gfx6_gfx7:
    case AMDGPU::S_NOR_SAVEEXEC_B64_vi:
    case AMDGPU::S_NOT_B32_gfx10:
    case AMDGPU::S_NOT_B32_gfx11:
    case AMDGPU::S_NOT_B32_gfx12:
    case AMDGPU::S_NOT_B32_gfx6_gfx7:
    case AMDGPU::S_NOT_B32_vi:
    case AMDGPU::S_NOT_B64_gfx10:
    case AMDGPU::S_NOT_B64_gfx11:
    case AMDGPU::S_NOT_B64_gfx12:
    case AMDGPU::S_NOT_B64_gfx6_gfx7:
    case AMDGPU::S_NOT_B64_vi:
    case AMDGPU::S_ORN1_SAVEEXEC_B32_gfx10:
    case AMDGPU::S_ORN1_SAVEEXEC_B32_gfx11:
    case AMDGPU::S_ORN1_SAVEEXEC_B32_gfx12:
    case AMDGPU::S_ORN1_SAVEEXEC_B64_gfx10:
    case AMDGPU::S_ORN1_SAVEEXEC_B64_gfx11:
    case AMDGPU::S_ORN1_SAVEEXEC_B64_gfx12:
    case AMDGPU::S_ORN1_SAVEEXEC_B64_vi:
    case AMDGPU::S_ORN2_SAVEEXEC_B32_gfx10:
    case AMDGPU::S_ORN2_SAVEEXEC_B32_gfx11:
    case AMDGPU::S_ORN2_SAVEEXEC_B32_gfx12:
    case AMDGPU::S_ORN2_SAVEEXEC_B64_gfx10:
    case AMDGPU::S_ORN2_SAVEEXEC_B64_gfx11:
    case AMDGPU::S_ORN2_SAVEEXEC_B64_gfx12:
    case AMDGPU::S_ORN2_SAVEEXEC_B64_gfx6_gfx7:
    case AMDGPU::S_ORN2_SAVEEXEC_B64_vi:
    case AMDGPU::S_OR_SAVEEXEC_B32_gfx10:
    case AMDGPU::S_OR_SAVEEXEC_B32_gfx11:
    case AMDGPU::S_OR_SAVEEXEC_B32_gfx12:
    case AMDGPU::S_OR_SAVEEXEC_B64_gfx10:
    case AMDGPU::S_OR_SAVEEXEC_B64_gfx11:
    case AMDGPU::S_OR_SAVEEXEC_B64_gfx12:
    case AMDGPU::S_OR_SAVEEXEC_B64_gfx6_gfx7:
    case AMDGPU::S_OR_SAVEEXEC_B64_vi:
    case AMDGPU::S_QUADMASK_B32_gfx10:
    case AMDGPU::S_QUADMASK_B32_gfx11:
    case AMDGPU::S_QUADMASK_B32_gfx12:
    case AMDGPU::S_QUADMASK_B32_gfx6_gfx7:
    case AMDGPU::S_QUADMASK_B32_vi:
    case AMDGPU::S_QUADMASK_B64_gfx10:
    case AMDGPU::S_QUADMASK_B64_gfx11:
    case AMDGPU::S_QUADMASK_B64_gfx12:
    case AMDGPU::S_QUADMASK_B64_gfx6_gfx7:
    case AMDGPU::S_QUADMASK_B64_vi:
    case AMDGPU::S_RNDNE_F16_gfx11:
    case AMDGPU::S_RNDNE_F16_gfx12:
    case AMDGPU::S_RNDNE_F32_gfx11:
    case AMDGPU::S_RNDNE_F32_gfx12:
    case AMDGPU::S_SENDMSG_RTN_B32_gfx11:
    case AMDGPU::S_SENDMSG_RTN_B32_gfx12:
    case AMDGPU::S_SENDMSG_RTN_B64_gfx11:
    case AMDGPU::S_SENDMSG_RTN_B64_gfx12:
    case AMDGPU::S_SEXT_I32_I16_gfx10:
    case AMDGPU::S_SEXT_I32_I16_gfx11:
    case AMDGPU::S_SEXT_I32_I16_gfx12:
    case AMDGPU::S_SEXT_I32_I16_gfx6_gfx7:
    case AMDGPU::S_SEXT_I32_I16_vi:
    case AMDGPU::S_SEXT_I32_I8_gfx10:
    case AMDGPU::S_SEXT_I32_I8_gfx11:
    case AMDGPU::S_SEXT_I32_I8_gfx12:
    case AMDGPU::S_SEXT_I32_I8_gfx6_gfx7:
    case AMDGPU::S_SEXT_I32_I8_vi:
    case AMDGPU::S_SWAPPC_B64_gfx10:
    case AMDGPU::S_SWAPPC_B64_gfx11:
    case AMDGPU::S_SWAPPC_B64_gfx12:
    case AMDGPU::S_SWAPPC_B64_gfx1250:
    case AMDGPU::S_SWAPPC_B64_gfx6_gfx7:
    case AMDGPU::S_SWAPPC_B64_vi:
    case AMDGPU::S_TRUNC_F16_gfx11:
    case AMDGPU::S_TRUNC_F16_gfx12:
    case AMDGPU::S_TRUNC_F32_gfx11:
    case AMDGPU::S_TRUNC_F32_gfx12:
    case AMDGPU::S_WQM_B32_gfx10:
    case AMDGPU::S_WQM_B32_gfx11:
    case AMDGPU::S_WQM_B32_gfx12:
    case AMDGPU::S_WQM_B32_gfx6_gfx7:
    case AMDGPU::S_WQM_B32_vi:
    case AMDGPU::S_WQM_B64_gfx10:
    case AMDGPU::S_WQM_B64_gfx11:
    case AMDGPU::S_WQM_B64_gfx12:
    case AMDGPU::S_WQM_B64_gfx6_gfx7:
    case AMDGPU::S_WQM_B64_vi:
    case AMDGPU::S_XNOR_SAVEEXEC_B32_gfx10:
    case AMDGPU::S_XNOR_SAVEEXEC_B32_gfx11:
    case AMDGPU::S_XNOR_SAVEEXEC_B32_gfx12:
    case AMDGPU::S_XNOR_SAVEEXEC_B64_gfx10:
    case AMDGPU::S_XNOR_SAVEEXEC_B64_gfx11:
    case AMDGPU::S_XNOR_SAVEEXEC_B64_gfx12:
    case AMDGPU::S_XNOR_SAVEEXEC_B64_gfx6_gfx7:
    case AMDGPU::S_XNOR_SAVEEXEC_B64_vi:
    case AMDGPU::S_XOR_SAVEEXEC_B32_gfx10:
    case AMDGPU::S_XOR_SAVEEXEC_B32_gfx11:
    case AMDGPU::S_XOR_SAVEEXEC_B32_gfx12:
    case AMDGPU::S_XOR_SAVEEXEC_B64_gfx10:
    case AMDGPU::S_XOR_SAVEEXEC_B64_gfx11:
    case AMDGPU::S_XOR_SAVEEXEC_B64_gfx12:
    case AMDGPU::S_XOR_SAVEEXEC_B64_gfx6_gfx7:
    case AMDGPU::S_XOR_SAVEEXEC_B64_vi: {
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 16, 7);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::S_ABSDIFF_I32_gfx10:
    case AMDGPU::S_ABSDIFF_I32_gfx11:
    case AMDGPU::S_ABSDIFF_I32_gfx12:
    case AMDGPU::S_ABSDIFF_I32_gfx6_gfx7:
    case AMDGPU::S_ABSDIFF_I32_vi:
    case AMDGPU::S_ADDC_U32_gfx10:
    case AMDGPU::S_ADDC_U32_gfx11:
    case AMDGPU::S_ADDC_U32_gfx12:
    case AMDGPU::S_ADDC_U32_gfx6_gfx7:
    case AMDGPU::S_ADDC_U32_vi:
    case AMDGPU::S_ADD_F16_gfx11:
    case AMDGPU::S_ADD_F16_gfx12:
    case AMDGPU::S_ADD_F32_gfx11:
    case AMDGPU::S_ADD_F32_gfx12:
    case AMDGPU::S_ADD_I32_gfx10:
    case AMDGPU::S_ADD_I32_gfx11:
    case AMDGPU::S_ADD_I32_gfx12:
    case AMDGPU::S_ADD_I32_gfx6_gfx7:
    case AMDGPU::S_ADD_I32_vi:
    case AMDGPU::S_ADD_U32_gfx10:
    case AMDGPU::S_ADD_U32_gfx11:
    case AMDGPU::S_ADD_U32_gfx12:
    case AMDGPU::S_ADD_U32_gfx6_gfx7:
    case AMDGPU::S_ADD_U32_vi:
    case AMDGPU::S_ADD_U64_gfx12:
    case AMDGPU::S_ANDN2_B32_gfx10:
    case AMDGPU::S_ANDN2_B32_gfx11:
    case AMDGPU::S_ANDN2_B32_gfx12:
    case AMDGPU::S_ANDN2_B32_gfx6_gfx7:
    case AMDGPU::S_ANDN2_B32_vi:
    case AMDGPU::S_ANDN2_B64_gfx10:
    case AMDGPU::S_ANDN2_B64_gfx11:
    case AMDGPU::S_ANDN2_B64_gfx12:
    case AMDGPU::S_ANDN2_B64_gfx6_gfx7:
    case AMDGPU::S_ANDN2_B64_vi:
    case AMDGPU::S_AND_B32_gfx10:
    case AMDGPU::S_AND_B32_gfx11:
    case AMDGPU::S_AND_B32_gfx12:
    case AMDGPU::S_AND_B32_gfx6_gfx7:
    case AMDGPU::S_AND_B32_vi:
    case AMDGPU::S_AND_B64_gfx10:
    case AMDGPU::S_AND_B64_gfx11:
    case AMDGPU::S_AND_B64_gfx12:
    case AMDGPU::S_AND_B64_gfx6_gfx7:
    case AMDGPU::S_AND_B64_vi:
    case AMDGPU::S_ASHR_I32_gfx10:
    case AMDGPU::S_ASHR_I32_gfx11:
    case AMDGPU::S_ASHR_I32_gfx12:
    case AMDGPU::S_ASHR_I32_gfx6_gfx7:
    case AMDGPU::S_ASHR_I32_vi:
    case AMDGPU::S_ASHR_I64_gfx10:
    case AMDGPU::S_ASHR_I64_gfx11:
    case AMDGPU::S_ASHR_I64_gfx12:
    case AMDGPU::S_ASHR_I64_gfx6_gfx7:
    case AMDGPU::S_ASHR_I64_vi:
    case AMDGPU::S_BFE_I32_gfx10:
    case AMDGPU::S_BFE_I32_gfx11:
    case AMDGPU::S_BFE_I32_gfx12:
    case AMDGPU::S_BFE_I32_gfx6_gfx7:
    case AMDGPU::S_BFE_I32_vi:
    case AMDGPU::S_BFE_I64_gfx10:
    case AMDGPU::S_BFE_I64_gfx11:
    case AMDGPU::S_BFE_I64_gfx12:
    case AMDGPU::S_BFE_I64_gfx6_gfx7:
    case AMDGPU::S_BFE_I64_vi:
    case AMDGPU::S_BFE_U32_gfx10:
    case AMDGPU::S_BFE_U32_gfx11:
    case AMDGPU::S_BFE_U32_gfx12:
    case AMDGPU::S_BFE_U32_gfx6_gfx7:
    case AMDGPU::S_BFE_U32_vi:
    case AMDGPU::S_BFE_U64_gfx10:
    case AMDGPU::S_BFE_U64_gfx11:
    case AMDGPU::S_BFE_U64_gfx12:
    case AMDGPU::S_BFE_U64_gfx6_gfx7:
    case AMDGPU::S_BFE_U64_vi:
    case AMDGPU::S_BFM_B32_gfx10:
    case AMDGPU::S_BFM_B32_gfx11:
    case AMDGPU::S_BFM_B32_gfx12:
    case AMDGPU::S_BFM_B32_gfx6_gfx7:
    case AMDGPU::S_BFM_B32_vi:
    case AMDGPU::S_BFM_B64_gfx10:
    case AMDGPU::S_BFM_B64_gfx11:
    case AMDGPU::S_BFM_B64_gfx12:
    case AMDGPU::S_BFM_B64_gfx6_gfx7:
    case AMDGPU::S_BFM_B64_vi:
    case AMDGPU::S_CSELECT_B32_gfx10:
    case AMDGPU::S_CSELECT_B32_gfx11:
    case AMDGPU::S_CSELECT_B32_gfx12:
    case AMDGPU::S_CSELECT_B32_gfx6_gfx7:
    case AMDGPU::S_CSELECT_B32_vi:
    case AMDGPU::S_CSELECT_B64_gfx10:
    case AMDGPU::S_CSELECT_B64_gfx11:
    case AMDGPU::S_CSELECT_B64_gfx12:
    case AMDGPU::S_CSELECT_B64_gfx6_gfx7:
    case AMDGPU::S_CSELECT_B64_vi:
    case AMDGPU::S_CVT_PK_RTZ_F16_F32_gfx11:
    case AMDGPU::S_CVT_PK_RTZ_F16_F32_gfx12:
    case AMDGPU::S_FMAC_F16_gfx11:
    case AMDGPU::S_FMAC_F16_gfx12:
    case AMDGPU::S_FMAC_F32_gfx11:
    case AMDGPU::S_FMAC_F32_gfx12:
    case AMDGPU::S_LSHL1_ADD_U32_gfx10:
    case AMDGPU::S_LSHL1_ADD_U32_gfx11:
    case AMDGPU::S_LSHL1_ADD_U32_gfx12:
    case AMDGPU::S_LSHL1_ADD_U32_vi:
    case AMDGPU::S_LSHL2_ADD_U32_gfx10:
    case AMDGPU::S_LSHL2_ADD_U32_gfx11:
    case AMDGPU::S_LSHL2_ADD_U32_gfx12:
    case AMDGPU::S_LSHL2_ADD_U32_vi:
    case AMDGPU::S_LSHL3_ADD_U32_gfx10:
    case AMDGPU::S_LSHL3_ADD_U32_gfx11:
    case AMDGPU::S_LSHL3_ADD_U32_gfx12:
    case AMDGPU::S_LSHL3_ADD_U32_vi:
    case AMDGPU::S_LSHL4_ADD_U32_gfx10:
    case AMDGPU::S_LSHL4_ADD_U32_gfx11:
    case AMDGPU::S_LSHL4_ADD_U32_gfx12:
    case AMDGPU::S_LSHL4_ADD_U32_vi:
    case AMDGPU::S_LSHL_B32_gfx10:
    case AMDGPU::S_LSHL_B32_gfx11:
    case AMDGPU::S_LSHL_B32_gfx12:
    case AMDGPU::S_LSHL_B32_gfx6_gfx7:
    case AMDGPU::S_LSHL_B32_vi:
    case AMDGPU::S_LSHL_B64_gfx10:
    case AMDGPU::S_LSHL_B64_gfx11:
    case AMDGPU::S_LSHL_B64_gfx12:
    case AMDGPU::S_LSHL_B64_gfx6_gfx7:
    case AMDGPU::S_LSHL_B64_vi:
    case AMDGPU::S_LSHR_B32_gfx10:
    case AMDGPU::S_LSHR_B32_gfx11:
    case AMDGPU::S_LSHR_B32_gfx12:
    case AMDGPU::S_LSHR_B32_gfx6_gfx7:
    case AMDGPU::S_LSHR_B32_vi:
    case AMDGPU::S_LSHR_B64_gfx10:
    case AMDGPU::S_LSHR_B64_gfx11:
    case AMDGPU::S_LSHR_B64_gfx12:
    case AMDGPU::S_LSHR_B64_gfx6_gfx7:
    case AMDGPU::S_LSHR_B64_vi:
    case AMDGPU::S_MAXIMUM_F16_gfx12:
    case AMDGPU::S_MAXIMUM_F32_gfx12:
    case AMDGPU::S_MAX_F16_gfx11:
    case AMDGPU::S_MAX_F16_gfx12:
    case AMDGPU::S_MAX_F32_gfx11:
    case AMDGPU::S_MAX_F32_gfx12:
    case AMDGPU::S_MAX_I32_gfx10:
    case AMDGPU::S_MAX_I32_gfx11:
    case AMDGPU::S_MAX_I32_gfx12:
    case AMDGPU::S_MAX_I32_gfx6_gfx7:
    case AMDGPU::S_MAX_I32_vi:
    case AMDGPU::S_MAX_U32_gfx10:
    case AMDGPU::S_MAX_U32_gfx11:
    case AMDGPU::S_MAX_U32_gfx12:
    case AMDGPU::S_MAX_U32_gfx6_gfx7:
    case AMDGPU::S_MAX_U32_vi:
    case AMDGPU::S_MINIMUM_F16_gfx12:
    case AMDGPU::S_MINIMUM_F32_gfx12:
    case AMDGPU::S_MIN_F16_gfx11:
    case AMDGPU::S_MIN_F16_gfx12:
    case AMDGPU::S_MIN_F32_gfx11:
    case AMDGPU::S_MIN_F32_gfx12:
    case AMDGPU::S_MIN_I32_gfx10:
    case AMDGPU::S_MIN_I32_gfx11:
    case AMDGPU::S_MIN_I32_gfx12:
    case AMDGPU::S_MIN_I32_gfx6_gfx7:
    case AMDGPU::S_MIN_I32_vi:
    case AMDGPU::S_MIN_U32_gfx10:
    case AMDGPU::S_MIN_U32_gfx11:
    case AMDGPU::S_MIN_U32_gfx12:
    case AMDGPU::S_MIN_U32_gfx6_gfx7:
    case AMDGPU::S_MIN_U32_vi:
    case AMDGPU::S_MUL_F16_gfx11:
    case AMDGPU::S_MUL_F16_gfx12:
    case AMDGPU::S_MUL_F32_gfx11:
    case AMDGPU::S_MUL_F32_gfx12:
    case AMDGPU::S_MUL_HI_I32_gfx10:
    case AMDGPU::S_MUL_HI_I32_gfx11:
    case AMDGPU::S_MUL_HI_I32_gfx12:
    case AMDGPU::S_MUL_HI_I32_vi:
    case AMDGPU::S_MUL_HI_U32_gfx10:
    case AMDGPU::S_MUL_HI_U32_gfx11:
    case AMDGPU::S_MUL_HI_U32_gfx12:
    case AMDGPU::S_MUL_HI_U32_vi:
    case AMDGPU::S_MUL_I32_gfx10:
    case AMDGPU::S_MUL_I32_gfx11:
    case AMDGPU::S_MUL_I32_gfx12:
    case AMDGPU::S_MUL_I32_gfx6_gfx7:
    case AMDGPU::S_MUL_I32_vi:
    case AMDGPU::S_MUL_U64_gfx12:
    case AMDGPU::S_NAND_B32_gfx10:
    case AMDGPU::S_NAND_B32_gfx11:
    case AMDGPU::S_NAND_B32_gfx12:
    case AMDGPU::S_NAND_B32_gfx6_gfx7:
    case AMDGPU::S_NAND_B32_vi:
    case AMDGPU::S_NAND_B64_gfx10:
    case AMDGPU::S_NAND_B64_gfx11:
    case AMDGPU::S_NAND_B64_gfx12:
    case AMDGPU::S_NAND_B64_gfx6_gfx7:
    case AMDGPU::S_NAND_B64_vi:
    case AMDGPU::S_NOR_B32_gfx10:
    case AMDGPU::S_NOR_B32_gfx11:
    case AMDGPU::S_NOR_B32_gfx12:
    case AMDGPU::S_NOR_B32_gfx6_gfx7:
    case AMDGPU::S_NOR_B32_vi:
    case AMDGPU::S_NOR_B64_gfx10:
    case AMDGPU::S_NOR_B64_gfx11:
    case AMDGPU::S_NOR_B64_gfx12:
    case AMDGPU::S_NOR_B64_gfx6_gfx7:
    case AMDGPU::S_NOR_B64_vi:
    case AMDGPU::S_ORN2_B32_gfx10:
    case AMDGPU::S_ORN2_B32_gfx11:
    case AMDGPU::S_ORN2_B32_gfx12:
    case AMDGPU::S_ORN2_B32_gfx6_gfx7:
    case AMDGPU::S_ORN2_B32_vi:
    case AMDGPU::S_ORN2_B64_gfx10:
    case AMDGPU::S_ORN2_B64_gfx11:
    case AMDGPU::S_ORN2_B64_gfx12:
    case AMDGPU::S_ORN2_B64_gfx6_gfx7:
    case AMDGPU::S_ORN2_B64_vi:
    case AMDGPU::S_OR_B32_gfx10:
    case AMDGPU::S_OR_B32_gfx11:
    case AMDGPU::S_OR_B32_gfx12:
    case AMDGPU::S_OR_B32_gfx6_gfx7:
    case AMDGPU::S_OR_B32_vi:
    case AMDGPU::S_OR_B64_gfx10:
    case AMDGPU::S_OR_B64_gfx11:
    case AMDGPU::S_OR_B64_gfx12:
    case AMDGPU::S_OR_B64_gfx6_gfx7:
    case AMDGPU::S_OR_B64_vi:
    case AMDGPU::S_PACK_HH_B32_B16_gfx10:
    case AMDGPU::S_PACK_HH_B32_B16_gfx11:
    case AMDGPU::S_PACK_HH_B32_B16_gfx12:
    case AMDGPU::S_PACK_HH_B32_B16_vi:
    case AMDGPU::S_PACK_HL_B32_B16_gfx11:
    case AMDGPU::S_PACK_HL_B32_B16_gfx12:
    case AMDGPU::S_PACK_LH_B32_B16_gfx10:
    case AMDGPU::S_PACK_LH_B32_B16_gfx11:
    case AMDGPU::S_PACK_LH_B32_B16_gfx12:
    case AMDGPU::S_PACK_LH_B32_B16_vi:
    case AMDGPU::S_PACK_LL_B32_B16_gfx10:
    case AMDGPU::S_PACK_LL_B32_B16_gfx11:
    case AMDGPU::S_PACK_LL_B32_B16_gfx12:
    case AMDGPU::S_PACK_LL_B32_B16_vi:
    case AMDGPU::S_SUBB_U32_gfx10:
    case AMDGPU::S_SUBB_U32_gfx11:
    case AMDGPU::S_SUBB_U32_gfx12:
    case AMDGPU::S_SUBB_U32_gfx6_gfx7:
    case AMDGPU::S_SUBB_U32_vi:
    case AMDGPU::S_SUB_F16_gfx11:
    case AMDGPU::S_SUB_F16_gfx12:
    case AMDGPU::S_SUB_F32_gfx11:
    case AMDGPU::S_SUB_F32_gfx12:
    case AMDGPU::S_SUB_I32_gfx10:
    case AMDGPU::S_SUB_I32_gfx11:
    case AMDGPU::S_SUB_I32_gfx12:
    case AMDGPU::S_SUB_I32_gfx6_gfx7:
    case AMDGPU::S_SUB_I32_vi:
    case AMDGPU::S_SUB_U32_gfx10:
    case AMDGPU::S_SUB_U32_gfx11:
    case AMDGPU::S_SUB_U32_gfx12:
    case AMDGPU::S_SUB_U32_gfx6_gfx7:
    case AMDGPU::S_SUB_U32_vi:
    case AMDGPU::S_SUB_U64_gfx12:
    case AMDGPU::S_XNOR_B32_gfx10:
    case AMDGPU::S_XNOR_B32_gfx11:
    case AMDGPU::S_XNOR_B32_gfx12:
    case AMDGPU::S_XNOR_B32_gfx6_gfx7:
    case AMDGPU::S_XNOR_B32_vi:
    case AMDGPU::S_XNOR_B64_gfx10:
    case AMDGPU::S_XNOR_B64_gfx11:
    case AMDGPU::S_XNOR_B64_gfx12:
    case AMDGPU::S_XNOR_B64_gfx6_gfx7:
    case AMDGPU::S_XNOR_B64_vi:
    case AMDGPU::S_XOR_B32_gfx10:
    case AMDGPU::S_XOR_B32_gfx11:
    case AMDGPU::S_XOR_B32_gfx12:
    case AMDGPU::S_XOR_B32_gfx6_gfx7:
    case AMDGPU::S_XOR_B32_vi:
    case AMDGPU::S_XOR_B64_gfx10:
    case AMDGPU::S_XOR_B64_gfx11:
    case AMDGPU::S_XOR_B64_gfx12:
    case AMDGPU::S_XOR_B64_gfx6_gfx7:
    case AMDGPU::S_XOR_B64_vi: {
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 16, 7);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 8, 8);
      break;
    }
    case AMDGPU::S_FMAAK_F32_gfx11:
    case AMDGPU::S_FMAAK_F32_gfx12: {
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 16, 7);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 8, 8);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(32, 0), 32, 32);
      break;
    }
    case AMDGPU::S_FMAMK_F32_gfx11:
    case AMDGPU::S_FMAMK_F32_gfx12: {
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 16, 7);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 8, 8);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(32, 0), 32, 32);
      break;
    }
    case AMDGPU::S_GET_WAVEID_IN_WORKGROUP_gfx10:
    case AMDGPU::S_MEMREALTIME_gfx10:
    case AMDGPU::S_MEMREALTIME_vi:
    case AMDGPU::S_MEMTIME_gfx10:
    case AMDGPU::S_MEMTIME_vi: {
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 6, 7);
      break;
    }
    case AMDGPU::S_SUBVECTOR_LOOP_BEGIN_gfx10:
    case AMDGPU::S_SUBVECTOR_LOOP_BEGIN_gfx11:
    case AMDGPU::S_SUBVECTOR_LOOP_END_gfx10:
    case AMDGPU::S_SUBVECTOR_LOOP_END_gfx11: {
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 16, 7);
      // op: simm16
      op.clearAllBits();
      getSOPPBrEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::S_BARRIER_WAIT_gfx12:
    case AMDGPU::S_CLAUSE_gfx10:
    case AMDGPU::S_CLAUSE_gfx11:
    case AMDGPU::S_CLAUSE_gfx12:
    case AMDGPU::S_DECPERFLEVEL_gfx10:
    case AMDGPU::S_DECPERFLEVEL_gfx11:
    case AMDGPU::S_DECPERFLEVEL_gfx12:
    case AMDGPU::S_DECPERFLEVEL_gfx6_gfx7:
    case AMDGPU::S_DECPERFLEVEL_vi:
    case AMDGPU::S_DELAY_ALU_gfx11:
    case AMDGPU::S_DELAY_ALU_gfx12:
    case AMDGPU::S_DENORM_MODE_gfx10:
    case AMDGPU::S_DENORM_MODE_gfx11:
    case AMDGPU::S_DENORM_MODE_gfx12:
    case AMDGPU::S_ENDPGM_gfx10:
    case AMDGPU::S_ENDPGM_gfx11:
    case AMDGPU::S_ENDPGM_gfx12:
    case AMDGPU::S_ENDPGM_gfx6_gfx7:
    case AMDGPU::S_ENDPGM_vi:
    case AMDGPU::S_INCPERFLEVEL_gfx10:
    case AMDGPU::S_INCPERFLEVEL_gfx11:
    case AMDGPU::S_INCPERFLEVEL_gfx12:
    case AMDGPU::S_INCPERFLEVEL_gfx6_gfx7:
    case AMDGPU::S_INCPERFLEVEL_vi:
    case AMDGPU::S_INST_PREFETCH_gfx10:
    case AMDGPU::S_INST_PREFETCH_gfx11:
    case AMDGPU::S_MONITOR_SLEEP_gfx12:
    case AMDGPU::S_NOP_gfx10:
    case AMDGPU::S_NOP_gfx11:
    case AMDGPU::S_NOP_gfx12:
    case AMDGPU::S_NOP_gfx6_gfx7:
    case AMDGPU::S_NOP_vi:
    case AMDGPU::S_ROUND_MODE_gfx10:
    case AMDGPU::S_ROUND_MODE_gfx11:
    case AMDGPU::S_ROUND_MODE_gfx12:
    case AMDGPU::S_SENDMSGHALT_gfx10:
    case AMDGPU::S_SENDMSGHALT_gfx11:
    case AMDGPU::S_SENDMSGHALT_gfx12:
    case AMDGPU::S_SENDMSGHALT_gfx6_gfx7:
    case AMDGPU::S_SENDMSGHALT_vi:
    case AMDGPU::S_SENDMSG_gfx10:
    case AMDGPU::S_SENDMSG_gfx11:
    case AMDGPU::S_SENDMSG_gfx12:
    case AMDGPU::S_SENDMSG_gfx6_gfx7:
    case AMDGPU::S_SENDMSG_vi:
    case AMDGPU::S_SETHALT_gfx10:
    case AMDGPU::S_SETHALT_gfx11:
    case AMDGPU::S_SETHALT_gfx12:
    case AMDGPU::S_SETHALT_gfx6_gfx7:
    case AMDGPU::S_SETHALT_vi:
    case AMDGPU::S_SETKILL_gfx10:
    case AMDGPU::S_SETKILL_gfx11:
    case AMDGPU::S_SETKILL_gfx12:
    case AMDGPU::S_SETKILL_gfx6_gfx7:
    case AMDGPU::S_SETKILL_vi:
    case AMDGPU::S_SETPRIO_INC_WG_gfx12:
    case AMDGPU::S_SETPRIO_gfx10:
    case AMDGPU::S_SETPRIO_gfx11:
    case AMDGPU::S_SETPRIO_gfx12:
    case AMDGPU::S_SETPRIO_gfx6_gfx7:
    case AMDGPU::S_SETPRIO_vi:
    case AMDGPU::S_SET_GPR_IDX_MODE_vi:
    case AMDGPU::S_SET_VGPR_MSB_gfx12:
    case AMDGPU::S_SLEEP_gfx10:
    case AMDGPU::S_SLEEP_gfx11:
    case AMDGPU::S_SLEEP_gfx12:
    case AMDGPU::S_SLEEP_gfx6_gfx7:
    case AMDGPU::S_SLEEP_vi:
    case AMDGPU::S_TRAP_gfx10:
    case AMDGPU::S_TRAP_gfx11:
    case AMDGPU::S_TRAP_gfx12:
    case AMDGPU::S_TRAP_gfx6_gfx7:
    case AMDGPU::S_TRAP_vi:
    case AMDGPU::S_TTRACEDATA_IMM_gfx10:
    case AMDGPU::S_TTRACEDATA_IMM_gfx11:
    case AMDGPU::S_TTRACEDATA_IMM_gfx12:
    case AMDGPU::S_VERSION_gfx10:
    case AMDGPU::S_VERSION_gfx11:
    case AMDGPU::S_VERSION_gfx12:
    case AMDGPU::S_WAITCNT_DEPCTR_gfx10:
    case AMDGPU::S_WAITCNT_DEPCTR_gfx11:
    case AMDGPU::S_WAITCNT_DEPCTR_gfx12:
    case AMDGPU::S_WAITCNT_gfx10:
    case AMDGPU::S_WAITCNT_gfx11:
    case AMDGPU::S_WAITCNT_gfx12:
    case AMDGPU::S_WAITCNT_gfx6_gfx7:
    case AMDGPU::S_WAITCNT_vi:
    case AMDGPU::S_WAIT_ASYNCCNT_gfx12:
    case AMDGPU::S_WAIT_BVHCNT_gfx12:
    case AMDGPU::S_WAIT_DSCNT_gfx12:
    case AMDGPU::S_WAIT_EVENT_gfx11:
    case AMDGPU::S_WAIT_EVENT_gfx12:
    case AMDGPU::S_WAIT_EXPCNT_gfx12:
    case AMDGPU::S_WAIT_KMCNT_gfx12:
    case AMDGPU::S_WAIT_LOADCNT_DSCNT_gfx12:
    case AMDGPU::S_WAIT_LOADCNT_gfx12:
    case AMDGPU::S_WAIT_SAMPLECNT_gfx12:
    case AMDGPU::S_WAIT_STORECNT_DSCNT_gfx12:
    case AMDGPU::S_WAIT_STORECNT_gfx12:
    case AMDGPU::S_WAIT_TENSORCNT_gfx12:
    case AMDGPU::S_WAIT_XCNT_gfx12: {
      // op: simm16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::S_SETREG_IMM32_B32_gfx10:
    case AMDGPU::S_SETREG_IMM32_B32_gfx11:
    case AMDGPU::S_SETREG_IMM32_B32_gfx12:
    case AMDGPU::S_SETREG_IMM32_B32_gfx6_gfx7:
    case AMDGPU::S_SETREG_IMM32_B32_vi: {
      // op: simm16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(32, 0), 32, 32);
      break;
    }
    case AMDGPU::S_BRANCH_gfx10:
    case AMDGPU::S_BRANCH_gfx11:
    case AMDGPU::S_BRANCH_gfx12:
    case AMDGPU::S_BRANCH_gfx6_gfx7:
    case AMDGPU::S_BRANCH_pad_s_nop_gfx10:
    case AMDGPU::S_BRANCH_pad_s_nop_gfx11:
    case AMDGPU::S_BRANCH_pad_s_nop_gfx12:
    case AMDGPU::S_BRANCH_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_BRANCH_pad_s_nop_vi:
    case AMDGPU::S_BRANCH_vi:
    case AMDGPU::S_CBRANCH_CDBGSYS_AND_USER_gfx10:
    case AMDGPU::S_CBRANCH_CDBGSYS_AND_USER_gfx11:
    case AMDGPU::S_CBRANCH_CDBGSYS_AND_USER_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_CDBGSYS_AND_USER_pad_s_nop_gfx10:
    case AMDGPU::S_CBRANCH_CDBGSYS_AND_USER_pad_s_nop_gfx11:
    case AMDGPU::S_CBRANCH_CDBGSYS_AND_USER_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_CDBGSYS_AND_USER_pad_s_nop_vi:
    case AMDGPU::S_CBRANCH_CDBGSYS_AND_USER_vi:
    case AMDGPU::S_CBRANCH_CDBGSYS_OR_USER_gfx10:
    case AMDGPU::S_CBRANCH_CDBGSYS_OR_USER_gfx11:
    case AMDGPU::S_CBRANCH_CDBGSYS_OR_USER_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_CDBGSYS_OR_USER_pad_s_nop_gfx10:
    case AMDGPU::S_CBRANCH_CDBGSYS_OR_USER_pad_s_nop_gfx11:
    case AMDGPU::S_CBRANCH_CDBGSYS_OR_USER_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_CDBGSYS_OR_USER_pad_s_nop_vi:
    case AMDGPU::S_CBRANCH_CDBGSYS_OR_USER_vi:
    case AMDGPU::S_CBRANCH_CDBGSYS_gfx10:
    case AMDGPU::S_CBRANCH_CDBGSYS_gfx11:
    case AMDGPU::S_CBRANCH_CDBGSYS_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_CDBGSYS_pad_s_nop_gfx10:
    case AMDGPU::S_CBRANCH_CDBGSYS_pad_s_nop_gfx11:
    case AMDGPU::S_CBRANCH_CDBGSYS_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_CDBGSYS_pad_s_nop_vi:
    case AMDGPU::S_CBRANCH_CDBGSYS_vi:
    case AMDGPU::S_CBRANCH_CDBGUSER_gfx10:
    case AMDGPU::S_CBRANCH_CDBGUSER_gfx11:
    case AMDGPU::S_CBRANCH_CDBGUSER_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_CDBGUSER_pad_s_nop_gfx10:
    case AMDGPU::S_CBRANCH_CDBGUSER_pad_s_nop_gfx11:
    case AMDGPU::S_CBRANCH_CDBGUSER_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_CDBGUSER_pad_s_nop_vi:
    case AMDGPU::S_CBRANCH_CDBGUSER_vi:
    case AMDGPU::S_CBRANCH_EXECNZ_gfx10:
    case AMDGPU::S_CBRANCH_EXECNZ_gfx11:
    case AMDGPU::S_CBRANCH_EXECNZ_gfx12:
    case AMDGPU::S_CBRANCH_EXECNZ_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_EXECNZ_pad_s_nop_gfx10:
    case AMDGPU::S_CBRANCH_EXECNZ_pad_s_nop_gfx11:
    case AMDGPU::S_CBRANCH_EXECNZ_pad_s_nop_gfx12:
    case AMDGPU::S_CBRANCH_EXECNZ_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_EXECNZ_pad_s_nop_vi:
    case AMDGPU::S_CBRANCH_EXECNZ_vi:
    case AMDGPU::S_CBRANCH_EXECZ_gfx10:
    case AMDGPU::S_CBRANCH_EXECZ_gfx11:
    case AMDGPU::S_CBRANCH_EXECZ_gfx12:
    case AMDGPU::S_CBRANCH_EXECZ_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_EXECZ_pad_s_nop_gfx10:
    case AMDGPU::S_CBRANCH_EXECZ_pad_s_nop_gfx11:
    case AMDGPU::S_CBRANCH_EXECZ_pad_s_nop_gfx12:
    case AMDGPU::S_CBRANCH_EXECZ_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_EXECZ_pad_s_nop_vi:
    case AMDGPU::S_CBRANCH_EXECZ_vi:
    case AMDGPU::S_CBRANCH_SCC0_gfx10:
    case AMDGPU::S_CBRANCH_SCC0_gfx11:
    case AMDGPU::S_CBRANCH_SCC0_gfx12:
    case AMDGPU::S_CBRANCH_SCC0_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_SCC0_pad_s_nop_gfx10:
    case AMDGPU::S_CBRANCH_SCC0_pad_s_nop_gfx11:
    case AMDGPU::S_CBRANCH_SCC0_pad_s_nop_gfx12:
    case AMDGPU::S_CBRANCH_SCC0_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_SCC0_pad_s_nop_vi:
    case AMDGPU::S_CBRANCH_SCC0_vi:
    case AMDGPU::S_CBRANCH_SCC1_gfx10:
    case AMDGPU::S_CBRANCH_SCC1_gfx11:
    case AMDGPU::S_CBRANCH_SCC1_gfx12:
    case AMDGPU::S_CBRANCH_SCC1_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_SCC1_pad_s_nop_gfx10:
    case AMDGPU::S_CBRANCH_SCC1_pad_s_nop_gfx11:
    case AMDGPU::S_CBRANCH_SCC1_pad_s_nop_gfx12:
    case AMDGPU::S_CBRANCH_SCC1_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_SCC1_pad_s_nop_vi:
    case AMDGPU::S_CBRANCH_SCC1_vi:
    case AMDGPU::S_CBRANCH_VCCNZ_gfx10:
    case AMDGPU::S_CBRANCH_VCCNZ_gfx11:
    case AMDGPU::S_CBRANCH_VCCNZ_gfx12:
    case AMDGPU::S_CBRANCH_VCCNZ_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_VCCNZ_pad_s_nop_gfx10:
    case AMDGPU::S_CBRANCH_VCCNZ_pad_s_nop_gfx11:
    case AMDGPU::S_CBRANCH_VCCNZ_pad_s_nop_gfx12:
    case AMDGPU::S_CBRANCH_VCCNZ_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_VCCNZ_pad_s_nop_vi:
    case AMDGPU::S_CBRANCH_VCCNZ_vi:
    case AMDGPU::S_CBRANCH_VCCZ_gfx10:
    case AMDGPU::S_CBRANCH_VCCZ_gfx11:
    case AMDGPU::S_CBRANCH_VCCZ_gfx12:
    case AMDGPU::S_CBRANCH_VCCZ_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_VCCZ_pad_s_nop_gfx10:
    case AMDGPU::S_CBRANCH_VCCZ_pad_s_nop_gfx11:
    case AMDGPU::S_CBRANCH_VCCZ_pad_s_nop_gfx12:
    case AMDGPU::S_CBRANCH_VCCZ_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_VCCZ_pad_s_nop_vi:
    case AMDGPU::S_CBRANCH_VCCZ_vi: {
      // op: simm16
      op.clearAllBits();
      getSOPPBrEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::S_ADD_PC_I64_gfx12:
    case AMDGPU::S_ALLOC_VGPR_gfx12:
    case AMDGPU::S_BARRIER_INIT_IMM_gfx12:
    case AMDGPU::S_BARRIER_JOIN_IMM_gfx12:
    case AMDGPU::S_BARRIER_SIGNAL_IMM_gfx12:
    case AMDGPU::S_BARRIER_SIGNAL_ISFIRST_IMM_gfx12:
    case AMDGPU::S_CBRANCH_JOIN_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_JOIN_vi:
    case AMDGPU::S_RFE_B64_gfx10:
    case AMDGPU::S_RFE_B64_gfx11:
    case AMDGPU::S_RFE_B64_gfx12:
    case AMDGPU::S_RFE_B64_gfx1250:
    case AMDGPU::S_RFE_B64_gfx6_gfx7:
    case AMDGPU::S_RFE_B64_vi:
    case AMDGPU::S_SETPC_B64_gfx10:
    case AMDGPU::S_SETPC_B64_gfx11:
    case AMDGPU::S_SETPC_B64_gfx12:
    case AMDGPU::S_SETPC_B64_gfx1250:
    case AMDGPU::S_SETPC_B64_gfx6_gfx7:
    case AMDGPU::S_SETPC_B64_vi:
    case AMDGPU::S_SET_GPR_IDX_IDX_vi:
    case AMDGPU::S_SLEEP_VAR_gfx12:
    case AMDGPU::S_WAKEUP_BARRIER_IMM_gfx12: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::S_BITCMP0_B32_gfx10:
    case AMDGPU::S_BITCMP0_B32_gfx11:
    case AMDGPU::S_BITCMP0_B32_gfx12:
    case AMDGPU::S_BITCMP0_B32_gfx6_gfx7:
    case AMDGPU::S_BITCMP0_B32_vi:
    case AMDGPU::S_BITCMP0_B64_gfx10:
    case AMDGPU::S_BITCMP0_B64_gfx11:
    case AMDGPU::S_BITCMP0_B64_gfx12:
    case AMDGPU::S_BITCMP0_B64_gfx6_gfx7:
    case AMDGPU::S_BITCMP0_B64_vi:
    case AMDGPU::S_BITCMP1_B32_gfx10:
    case AMDGPU::S_BITCMP1_B32_gfx11:
    case AMDGPU::S_BITCMP1_B32_gfx12:
    case AMDGPU::S_BITCMP1_B32_gfx6_gfx7:
    case AMDGPU::S_BITCMP1_B32_vi:
    case AMDGPU::S_BITCMP1_B64_gfx10:
    case AMDGPU::S_BITCMP1_B64_gfx11:
    case AMDGPU::S_BITCMP1_B64_gfx12:
    case AMDGPU::S_BITCMP1_B64_gfx6_gfx7:
    case AMDGPU::S_BITCMP1_B64_vi:
    case AMDGPU::S_CBRANCH_G_FORK_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_G_FORK_vi:
    case AMDGPU::S_CMP_EQ_F16_gfx11:
    case AMDGPU::S_CMP_EQ_F16_gfx12:
    case AMDGPU::S_CMP_EQ_F32_gfx11:
    case AMDGPU::S_CMP_EQ_F32_gfx12:
    case AMDGPU::S_CMP_EQ_I32_gfx10:
    case AMDGPU::S_CMP_EQ_I32_gfx11:
    case AMDGPU::S_CMP_EQ_I32_gfx12:
    case AMDGPU::S_CMP_EQ_I32_gfx6_gfx7:
    case AMDGPU::S_CMP_EQ_I32_vi:
    case AMDGPU::S_CMP_EQ_U32_gfx10:
    case AMDGPU::S_CMP_EQ_U32_gfx11:
    case AMDGPU::S_CMP_EQ_U32_gfx12:
    case AMDGPU::S_CMP_EQ_U32_gfx6_gfx7:
    case AMDGPU::S_CMP_EQ_U32_vi:
    case AMDGPU::S_CMP_EQ_U64_gfx10:
    case AMDGPU::S_CMP_EQ_U64_gfx11:
    case AMDGPU::S_CMP_EQ_U64_gfx12:
    case AMDGPU::S_CMP_EQ_U64_vi:
    case AMDGPU::S_CMP_GE_F16_gfx11:
    case AMDGPU::S_CMP_GE_F16_gfx12:
    case AMDGPU::S_CMP_GE_F32_gfx11:
    case AMDGPU::S_CMP_GE_F32_gfx12:
    case AMDGPU::S_CMP_GE_I32_gfx10:
    case AMDGPU::S_CMP_GE_I32_gfx11:
    case AMDGPU::S_CMP_GE_I32_gfx12:
    case AMDGPU::S_CMP_GE_I32_gfx6_gfx7:
    case AMDGPU::S_CMP_GE_I32_vi:
    case AMDGPU::S_CMP_GE_U32_gfx10:
    case AMDGPU::S_CMP_GE_U32_gfx11:
    case AMDGPU::S_CMP_GE_U32_gfx12:
    case AMDGPU::S_CMP_GE_U32_gfx6_gfx7:
    case AMDGPU::S_CMP_GE_U32_vi:
    case AMDGPU::S_CMP_GT_F16_gfx11:
    case AMDGPU::S_CMP_GT_F16_gfx12:
    case AMDGPU::S_CMP_GT_F32_gfx11:
    case AMDGPU::S_CMP_GT_F32_gfx12:
    case AMDGPU::S_CMP_GT_I32_gfx10:
    case AMDGPU::S_CMP_GT_I32_gfx11:
    case AMDGPU::S_CMP_GT_I32_gfx12:
    case AMDGPU::S_CMP_GT_I32_gfx6_gfx7:
    case AMDGPU::S_CMP_GT_I32_vi:
    case AMDGPU::S_CMP_GT_U32_gfx10:
    case AMDGPU::S_CMP_GT_U32_gfx11:
    case AMDGPU::S_CMP_GT_U32_gfx12:
    case AMDGPU::S_CMP_GT_U32_gfx6_gfx7:
    case AMDGPU::S_CMP_GT_U32_vi:
    case AMDGPU::S_CMP_LE_F16_gfx11:
    case AMDGPU::S_CMP_LE_F16_gfx12:
    case AMDGPU::S_CMP_LE_F32_gfx11:
    case AMDGPU::S_CMP_LE_F32_gfx12:
    case AMDGPU::S_CMP_LE_I32_gfx10:
    case AMDGPU::S_CMP_LE_I32_gfx11:
    case AMDGPU::S_CMP_LE_I32_gfx12:
    case AMDGPU::S_CMP_LE_I32_gfx6_gfx7:
    case AMDGPU::S_CMP_LE_I32_vi:
    case AMDGPU::S_CMP_LE_U32_gfx10:
    case AMDGPU::S_CMP_LE_U32_gfx11:
    case AMDGPU::S_CMP_LE_U32_gfx12:
    case AMDGPU::S_CMP_LE_U32_gfx6_gfx7:
    case AMDGPU::S_CMP_LE_U32_vi:
    case AMDGPU::S_CMP_LG_F16_gfx11:
    case AMDGPU::S_CMP_LG_F16_gfx12:
    case AMDGPU::S_CMP_LG_F32_gfx11:
    case AMDGPU::S_CMP_LG_F32_gfx12:
    case AMDGPU::S_CMP_LG_I32_gfx10:
    case AMDGPU::S_CMP_LG_I32_gfx11:
    case AMDGPU::S_CMP_LG_I32_gfx12:
    case AMDGPU::S_CMP_LG_I32_gfx6_gfx7:
    case AMDGPU::S_CMP_LG_I32_vi:
    case AMDGPU::S_CMP_LG_U32_gfx10:
    case AMDGPU::S_CMP_LG_U32_gfx11:
    case AMDGPU::S_CMP_LG_U32_gfx12:
    case AMDGPU::S_CMP_LG_U32_gfx6_gfx7:
    case AMDGPU::S_CMP_LG_U32_vi:
    case AMDGPU::S_CMP_LG_U64_gfx10:
    case AMDGPU::S_CMP_LG_U64_gfx11:
    case AMDGPU::S_CMP_LG_U64_gfx12:
    case AMDGPU::S_CMP_LG_U64_vi:
    case AMDGPU::S_CMP_LT_F16_gfx11:
    case AMDGPU::S_CMP_LT_F16_gfx12:
    case AMDGPU::S_CMP_LT_F32_gfx11:
    case AMDGPU::S_CMP_LT_F32_gfx12:
    case AMDGPU::S_CMP_LT_I32_gfx10:
    case AMDGPU::S_CMP_LT_I32_gfx11:
    case AMDGPU::S_CMP_LT_I32_gfx12:
    case AMDGPU::S_CMP_LT_I32_gfx6_gfx7:
    case AMDGPU::S_CMP_LT_I32_vi:
    case AMDGPU::S_CMP_LT_U32_gfx10:
    case AMDGPU::S_CMP_LT_U32_gfx11:
    case AMDGPU::S_CMP_LT_U32_gfx12:
    case AMDGPU::S_CMP_LT_U32_gfx6_gfx7:
    case AMDGPU::S_CMP_LT_U32_vi:
    case AMDGPU::S_CMP_NEQ_F16_gfx11:
    case AMDGPU::S_CMP_NEQ_F16_gfx12:
    case AMDGPU::S_CMP_NEQ_F32_gfx11:
    case AMDGPU::S_CMP_NEQ_F32_gfx12:
    case AMDGPU::S_CMP_NGE_F16_gfx11:
    case AMDGPU::S_CMP_NGE_F16_gfx12:
    case AMDGPU::S_CMP_NGE_F32_gfx11:
    case AMDGPU::S_CMP_NGE_F32_gfx12:
    case AMDGPU::S_CMP_NGT_F16_gfx11:
    case AMDGPU::S_CMP_NGT_F16_gfx12:
    case AMDGPU::S_CMP_NGT_F32_gfx11:
    case AMDGPU::S_CMP_NGT_F32_gfx12:
    case AMDGPU::S_CMP_NLE_F16_gfx11:
    case AMDGPU::S_CMP_NLE_F16_gfx12:
    case AMDGPU::S_CMP_NLE_F32_gfx11:
    case AMDGPU::S_CMP_NLE_F32_gfx12:
    case AMDGPU::S_CMP_NLG_F16_gfx11:
    case AMDGPU::S_CMP_NLG_F16_gfx12:
    case AMDGPU::S_CMP_NLG_F32_gfx11:
    case AMDGPU::S_CMP_NLG_F32_gfx12:
    case AMDGPU::S_CMP_NLT_F16_gfx11:
    case AMDGPU::S_CMP_NLT_F16_gfx12:
    case AMDGPU::S_CMP_NLT_F32_gfx11:
    case AMDGPU::S_CMP_NLT_F32_gfx12:
    case AMDGPU::S_CMP_O_F16_gfx11:
    case AMDGPU::S_CMP_O_F16_gfx12:
    case AMDGPU::S_CMP_O_F32_gfx11:
    case AMDGPU::S_CMP_O_F32_gfx12:
    case AMDGPU::S_CMP_U_F16_gfx11:
    case AMDGPU::S_CMP_U_F16_gfx12:
    case AMDGPU::S_CMP_U_F32_gfx11:
    case AMDGPU::S_CMP_U_F32_gfx12:
    case AMDGPU::S_RFE_RESTORE_B64_vi:
    case AMDGPU::S_SETVSKIP_gfx6_gfx7:
    case AMDGPU::S_SETVSKIP_vi:
    case AMDGPU::S_SET_GPR_IDX_ON_vi: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 8, 8);
      break;
    }
    case AMDGPU::V_CMPSX_EQ_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_EQ_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_F_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_F_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_GE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_GE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_GT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_GT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LG_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LG_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NEQ_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NEQ_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NGE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NGE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NGT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NGT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLG_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLG_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_O_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_O_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_TRU_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_TRU_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_U_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_U_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_EQ_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_EQ_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_F_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_F_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_GE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_GE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_GT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_GT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_LE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_LE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_LG_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_LG_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_LT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_LT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NEQ_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NEQ_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NGE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NGE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NGT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NGT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLG_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLG_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_O_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_O_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_TRU_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_TRU_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_U_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_U_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_CLASS_F16_e32_gfx10:
    case AMDGPU::V_CMPX_CLASS_F16_e32_vi:
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_CLASS_F32_e32_gfx10:
    case AMDGPU::V_CMPX_CLASS_F32_e32_gfx11:
    case AMDGPU::V_CMPX_CLASS_F32_e32_gfx12:
    case AMDGPU::V_CMPX_CLASS_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_CLASS_F32_e32_vi:
    case AMDGPU::V_CMPX_CLASS_F64_e32_gfx10:
    case AMDGPU::V_CMPX_CLASS_F64_e32_gfx11:
    case AMDGPU::V_CMPX_CLASS_F64_e32_gfx12:
    case AMDGPU::V_CMPX_CLASS_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_CLASS_F64_e32_vi:
    case AMDGPU::V_CMPX_EQ_F16_e32_gfx10:
    case AMDGPU::V_CMPX_EQ_F16_e32_vi:
    case AMDGPU::V_CMPX_EQ_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_F32_e32_gfx10:
    case AMDGPU::V_CMPX_EQ_F32_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_F32_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_F32_e32_vi:
    case AMDGPU::V_CMPX_EQ_F64_e32_gfx10:
    case AMDGPU::V_CMPX_EQ_F64_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_F64_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_F64_e32_vi:
    case AMDGPU::V_CMPX_EQ_I16_e32_gfx10:
    case AMDGPU::V_CMPX_EQ_I16_e32_vi:
    case AMDGPU::V_CMPX_EQ_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_I32_e32_gfx10:
    case AMDGPU::V_CMPX_EQ_I32_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_I32_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_I32_e32_vi:
    case AMDGPU::V_CMPX_EQ_I64_e32_gfx10:
    case AMDGPU::V_CMPX_EQ_I64_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_I64_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_I64_e32_vi:
    case AMDGPU::V_CMPX_EQ_U16_e32_gfx10:
    case AMDGPU::V_CMPX_EQ_U16_e32_vi:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_U32_e32_gfx10:
    case AMDGPU::V_CMPX_EQ_U32_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_U32_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_U32_e32_vi:
    case AMDGPU::V_CMPX_EQ_U64_e32_gfx10:
    case AMDGPU::V_CMPX_EQ_U64_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_U64_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_U64_e32_vi:
    case AMDGPU::V_CMPX_F_F16_e32_gfx10:
    case AMDGPU::V_CMPX_F_F16_e32_vi:
    case AMDGPU::V_CMPX_F_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_F_F32_e32_gfx10:
    case AMDGPU::V_CMPX_F_F32_e32_gfx11:
    case AMDGPU::V_CMPX_F_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_F32_e32_vi:
    case AMDGPU::V_CMPX_F_F64_e32_gfx10:
    case AMDGPU::V_CMPX_F_F64_e32_gfx11:
    case AMDGPU::V_CMPX_F_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_F64_e32_vi:
    case AMDGPU::V_CMPX_F_I16_e32_vi:
    case AMDGPU::V_CMPX_F_I32_e32_gfx10:
    case AMDGPU::V_CMPX_F_I32_e32_gfx11:
    case AMDGPU::V_CMPX_F_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_I32_e32_vi:
    case AMDGPU::V_CMPX_F_I64_e32_gfx10:
    case AMDGPU::V_CMPX_F_I64_e32_gfx11:
    case AMDGPU::V_CMPX_F_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_I64_e32_vi:
    case AMDGPU::V_CMPX_F_U16_e32_vi:
    case AMDGPU::V_CMPX_F_U32_e32_gfx10:
    case AMDGPU::V_CMPX_F_U32_e32_gfx11:
    case AMDGPU::V_CMPX_F_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_U32_e32_vi:
    case AMDGPU::V_CMPX_F_U64_e32_gfx10:
    case AMDGPU::V_CMPX_F_U64_e32_gfx11:
    case AMDGPU::V_CMPX_F_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_U64_e32_vi:
    case AMDGPU::V_CMPX_GE_F16_e32_gfx10:
    case AMDGPU::V_CMPX_GE_F16_e32_vi:
    case AMDGPU::V_CMPX_GE_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_GE_F32_e32_gfx10:
    case AMDGPU::V_CMPX_GE_F32_e32_gfx11:
    case AMDGPU::V_CMPX_GE_F32_e32_gfx12:
    case AMDGPU::V_CMPX_GE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_F32_e32_vi:
    case AMDGPU::V_CMPX_GE_F64_e32_gfx10:
    case AMDGPU::V_CMPX_GE_F64_e32_gfx11:
    case AMDGPU::V_CMPX_GE_F64_e32_gfx12:
    case AMDGPU::V_CMPX_GE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_F64_e32_vi:
    case AMDGPU::V_CMPX_GE_I16_e32_gfx10:
    case AMDGPU::V_CMPX_GE_I16_e32_vi:
    case AMDGPU::V_CMPX_GE_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_GE_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_GE_I32_e32_gfx10:
    case AMDGPU::V_CMPX_GE_I32_e32_gfx11:
    case AMDGPU::V_CMPX_GE_I32_e32_gfx12:
    case AMDGPU::V_CMPX_GE_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_I32_e32_vi:
    case AMDGPU::V_CMPX_GE_I64_e32_gfx10:
    case AMDGPU::V_CMPX_GE_I64_e32_gfx11:
    case AMDGPU::V_CMPX_GE_I64_e32_gfx12:
    case AMDGPU::V_CMPX_GE_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_I64_e32_vi:
    case AMDGPU::V_CMPX_GE_U16_e32_gfx10:
    case AMDGPU::V_CMPX_GE_U16_e32_vi:
    case AMDGPU::V_CMPX_GE_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_GE_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_GE_U32_e32_gfx10:
    case AMDGPU::V_CMPX_GE_U32_e32_gfx11:
    case AMDGPU::V_CMPX_GE_U32_e32_gfx12:
    case AMDGPU::V_CMPX_GE_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_U32_e32_vi:
    case AMDGPU::V_CMPX_GE_U64_e32_gfx10:
    case AMDGPU::V_CMPX_GE_U64_e32_gfx11:
    case AMDGPU::V_CMPX_GE_U64_e32_gfx12:
    case AMDGPU::V_CMPX_GE_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_U64_e32_vi:
    case AMDGPU::V_CMPX_GT_F16_e32_gfx10:
    case AMDGPU::V_CMPX_GT_F16_e32_vi:
    case AMDGPU::V_CMPX_GT_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_GT_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_GT_F32_e32_gfx10:
    case AMDGPU::V_CMPX_GT_F32_e32_gfx11:
    case AMDGPU::V_CMPX_GT_F32_e32_gfx12:
    case AMDGPU::V_CMPX_GT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_F32_e32_vi:
    case AMDGPU::V_CMPX_GT_F64_e32_gfx10:
    case AMDGPU::V_CMPX_GT_F64_e32_gfx11:
    case AMDGPU::V_CMPX_GT_F64_e32_gfx12:
    case AMDGPU::V_CMPX_GT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_F64_e32_vi:
    case AMDGPU::V_CMPX_GT_I16_e32_gfx10:
    case AMDGPU::V_CMPX_GT_I16_e32_vi:
    case AMDGPU::V_CMPX_GT_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_GT_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_GT_I32_e32_gfx10:
    case AMDGPU::V_CMPX_GT_I32_e32_gfx11:
    case AMDGPU::V_CMPX_GT_I32_e32_gfx12:
    case AMDGPU::V_CMPX_GT_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_I32_e32_vi:
    case AMDGPU::V_CMPX_GT_I64_e32_gfx10:
    case AMDGPU::V_CMPX_GT_I64_e32_gfx11:
    case AMDGPU::V_CMPX_GT_I64_e32_gfx12:
    case AMDGPU::V_CMPX_GT_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_I64_e32_vi:
    case AMDGPU::V_CMPX_GT_U16_e32_gfx10:
    case AMDGPU::V_CMPX_GT_U16_e32_vi:
    case AMDGPU::V_CMPX_GT_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_GT_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_GT_U32_e32_gfx10:
    case AMDGPU::V_CMPX_GT_U32_e32_gfx11:
    case AMDGPU::V_CMPX_GT_U32_e32_gfx12:
    case AMDGPU::V_CMPX_GT_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_U32_e32_vi:
    case AMDGPU::V_CMPX_GT_U64_e32_gfx10:
    case AMDGPU::V_CMPX_GT_U64_e32_gfx11:
    case AMDGPU::V_CMPX_GT_U64_e32_gfx12:
    case AMDGPU::V_CMPX_GT_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_U64_e32_vi:
    case AMDGPU::V_CMPX_LE_F16_e32_gfx10:
    case AMDGPU::V_CMPX_LE_F16_e32_vi:
    case AMDGPU::V_CMPX_LE_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_LE_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_LE_F32_e32_gfx10:
    case AMDGPU::V_CMPX_LE_F32_e32_gfx11:
    case AMDGPU::V_CMPX_LE_F32_e32_gfx12:
    case AMDGPU::V_CMPX_LE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_F32_e32_vi:
    case AMDGPU::V_CMPX_LE_F64_e32_gfx10:
    case AMDGPU::V_CMPX_LE_F64_e32_gfx11:
    case AMDGPU::V_CMPX_LE_F64_e32_gfx12:
    case AMDGPU::V_CMPX_LE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_F64_e32_vi:
    case AMDGPU::V_CMPX_LE_I16_e32_gfx10:
    case AMDGPU::V_CMPX_LE_I16_e32_vi:
    case AMDGPU::V_CMPX_LE_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_LE_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_LE_I32_e32_gfx10:
    case AMDGPU::V_CMPX_LE_I32_e32_gfx11:
    case AMDGPU::V_CMPX_LE_I32_e32_gfx12:
    case AMDGPU::V_CMPX_LE_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_I32_e32_vi:
    case AMDGPU::V_CMPX_LE_I64_e32_gfx10:
    case AMDGPU::V_CMPX_LE_I64_e32_gfx11:
    case AMDGPU::V_CMPX_LE_I64_e32_gfx12:
    case AMDGPU::V_CMPX_LE_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_I64_e32_vi:
    case AMDGPU::V_CMPX_LE_U16_e32_gfx10:
    case AMDGPU::V_CMPX_LE_U16_e32_vi:
    case AMDGPU::V_CMPX_LE_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_LE_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_LE_U32_e32_gfx10:
    case AMDGPU::V_CMPX_LE_U32_e32_gfx11:
    case AMDGPU::V_CMPX_LE_U32_e32_gfx12:
    case AMDGPU::V_CMPX_LE_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_U32_e32_vi:
    case AMDGPU::V_CMPX_LE_U64_e32_gfx10:
    case AMDGPU::V_CMPX_LE_U64_e32_gfx11:
    case AMDGPU::V_CMPX_LE_U64_e32_gfx12:
    case AMDGPU::V_CMPX_LE_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_U64_e32_vi:
    case AMDGPU::V_CMPX_LG_F16_e32_gfx10:
    case AMDGPU::V_CMPX_LG_F16_e32_vi:
    case AMDGPU::V_CMPX_LG_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_LG_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_LG_F32_e32_gfx10:
    case AMDGPU::V_CMPX_LG_F32_e32_gfx11:
    case AMDGPU::V_CMPX_LG_F32_e32_gfx12:
    case AMDGPU::V_CMPX_LG_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LG_F32_e32_vi:
    case AMDGPU::V_CMPX_LG_F64_e32_gfx10:
    case AMDGPU::V_CMPX_LG_F64_e32_gfx11:
    case AMDGPU::V_CMPX_LG_F64_e32_gfx12:
    case AMDGPU::V_CMPX_LG_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LG_F64_e32_vi:
    case AMDGPU::V_CMPX_LT_F16_e32_gfx10:
    case AMDGPU::V_CMPX_LT_F16_e32_vi:
    case AMDGPU::V_CMPX_LT_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_LT_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_LT_F32_e32_gfx10:
    case AMDGPU::V_CMPX_LT_F32_e32_gfx11:
    case AMDGPU::V_CMPX_LT_F32_e32_gfx12:
    case AMDGPU::V_CMPX_LT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_F32_e32_vi:
    case AMDGPU::V_CMPX_LT_F64_e32_gfx10:
    case AMDGPU::V_CMPX_LT_F64_e32_gfx11:
    case AMDGPU::V_CMPX_LT_F64_e32_gfx12:
    case AMDGPU::V_CMPX_LT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_F64_e32_vi:
    case AMDGPU::V_CMPX_LT_I16_e32_gfx10:
    case AMDGPU::V_CMPX_LT_I16_e32_vi:
    case AMDGPU::V_CMPX_LT_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_LT_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_LT_I32_e32_gfx10:
    case AMDGPU::V_CMPX_LT_I32_e32_gfx11:
    case AMDGPU::V_CMPX_LT_I32_e32_gfx12:
    case AMDGPU::V_CMPX_LT_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_I32_e32_vi:
    case AMDGPU::V_CMPX_LT_I64_e32_gfx10:
    case AMDGPU::V_CMPX_LT_I64_e32_gfx11:
    case AMDGPU::V_CMPX_LT_I64_e32_gfx12:
    case AMDGPU::V_CMPX_LT_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_I64_e32_vi:
    case AMDGPU::V_CMPX_LT_U16_e32_gfx10:
    case AMDGPU::V_CMPX_LT_U16_e32_vi:
    case AMDGPU::V_CMPX_LT_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_LT_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_LT_U32_e32_gfx10:
    case AMDGPU::V_CMPX_LT_U32_e32_gfx11:
    case AMDGPU::V_CMPX_LT_U32_e32_gfx12:
    case AMDGPU::V_CMPX_LT_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_U32_e32_vi:
    case AMDGPU::V_CMPX_LT_U64_e32_gfx10:
    case AMDGPU::V_CMPX_LT_U64_e32_gfx11:
    case AMDGPU::V_CMPX_LT_U64_e32_gfx12:
    case AMDGPU::V_CMPX_LT_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_U64_e32_vi:
    case AMDGPU::V_CMPX_NEQ_F16_e32_gfx10:
    case AMDGPU::V_CMPX_NEQ_F16_e32_vi:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_NEQ_F32_e32_gfx10:
    case AMDGPU::V_CMPX_NEQ_F32_e32_gfx11:
    case AMDGPU::V_CMPX_NEQ_F32_e32_gfx12:
    case AMDGPU::V_CMPX_NEQ_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NEQ_F32_e32_vi:
    case AMDGPU::V_CMPX_NEQ_F64_e32_gfx10:
    case AMDGPU::V_CMPX_NEQ_F64_e32_gfx11:
    case AMDGPU::V_CMPX_NEQ_F64_e32_gfx12:
    case AMDGPU::V_CMPX_NEQ_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NEQ_F64_e32_vi:
    case AMDGPU::V_CMPX_NE_I16_e32_gfx10:
    case AMDGPU::V_CMPX_NE_I16_e32_vi:
    case AMDGPU::V_CMPX_NE_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_NE_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_NE_I32_e32_gfx10:
    case AMDGPU::V_CMPX_NE_I32_e32_gfx11:
    case AMDGPU::V_CMPX_NE_I32_e32_gfx12:
    case AMDGPU::V_CMPX_NE_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NE_I32_e32_vi:
    case AMDGPU::V_CMPX_NE_I64_e32_gfx10:
    case AMDGPU::V_CMPX_NE_I64_e32_gfx11:
    case AMDGPU::V_CMPX_NE_I64_e32_gfx12:
    case AMDGPU::V_CMPX_NE_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NE_I64_e32_vi:
    case AMDGPU::V_CMPX_NE_U16_e32_gfx10:
    case AMDGPU::V_CMPX_NE_U16_e32_vi:
    case AMDGPU::V_CMPX_NE_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_NE_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_NE_U32_e32_gfx10:
    case AMDGPU::V_CMPX_NE_U32_e32_gfx11:
    case AMDGPU::V_CMPX_NE_U32_e32_gfx12:
    case AMDGPU::V_CMPX_NE_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NE_U32_e32_vi:
    case AMDGPU::V_CMPX_NE_U64_e32_gfx10:
    case AMDGPU::V_CMPX_NE_U64_e32_gfx11:
    case AMDGPU::V_CMPX_NE_U64_e32_gfx12:
    case AMDGPU::V_CMPX_NE_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NE_U64_e32_vi:
    case AMDGPU::V_CMPX_NGE_F16_e32_gfx10:
    case AMDGPU::V_CMPX_NGE_F16_e32_vi:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_NGE_F32_e32_gfx10:
    case AMDGPU::V_CMPX_NGE_F32_e32_gfx11:
    case AMDGPU::V_CMPX_NGE_F32_e32_gfx12:
    case AMDGPU::V_CMPX_NGE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NGE_F32_e32_vi:
    case AMDGPU::V_CMPX_NGE_F64_e32_gfx10:
    case AMDGPU::V_CMPX_NGE_F64_e32_gfx11:
    case AMDGPU::V_CMPX_NGE_F64_e32_gfx12:
    case AMDGPU::V_CMPX_NGE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NGE_F64_e32_vi:
    case AMDGPU::V_CMPX_NGT_F16_e32_gfx10:
    case AMDGPU::V_CMPX_NGT_F16_e32_vi:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_NGT_F32_e32_gfx10:
    case AMDGPU::V_CMPX_NGT_F32_e32_gfx11:
    case AMDGPU::V_CMPX_NGT_F32_e32_gfx12:
    case AMDGPU::V_CMPX_NGT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NGT_F32_e32_vi:
    case AMDGPU::V_CMPX_NGT_F64_e32_gfx10:
    case AMDGPU::V_CMPX_NGT_F64_e32_gfx11:
    case AMDGPU::V_CMPX_NGT_F64_e32_gfx12:
    case AMDGPU::V_CMPX_NGT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NGT_F64_e32_vi:
    case AMDGPU::V_CMPX_NLE_F16_e32_gfx10:
    case AMDGPU::V_CMPX_NLE_F16_e32_vi:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_NLE_F32_e32_gfx10:
    case AMDGPU::V_CMPX_NLE_F32_e32_gfx11:
    case AMDGPU::V_CMPX_NLE_F32_e32_gfx12:
    case AMDGPU::V_CMPX_NLE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLE_F32_e32_vi:
    case AMDGPU::V_CMPX_NLE_F64_e32_gfx10:
    case AMDGPU::V_CMPX_NLE_F64_e32_gfx11:
    case AMDGPU::V_CMPX_NLE_F64_e32_gfx12:
    case AMDGPU::V_CMPX_NLE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLE_F64_e32_vi:
    case AMDGPU::V_CMPX_NLG_F16_e32_gfx10:
    case AMDGPU::V_CMPX_NLG_F16_e32_vi:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_NLG_F32_e32_gfx10:
    case AMDGPU::V_CMPX_NLG_F32_e32_gfx11:
    case AMDGPU::V_CMPX_NLG_F32_e32_gfx12:
    case AMDGPU::V_CMPX_NLG_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLG_F32_e32_vi:
    case AMDGPU::V_CMPX_NLG_F64_e32_gfx10:
    case AMDGPU::V_CMPX_NLG_F64_e32_gfx11:
    case AMDGPU::V_CMPX_NLG_F64_e32_gfx12:
    case AMDGPU::V_CMPX_NLG_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLG_F64_e32_vi:
    case AMDGPU::V_CMPX_NLT_F16_e32_gfx10:
    case AMDGPU::V_CMPX_NLT_F16_e32_vi:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_NLT_F32_e32_gfx10:
    case AMDGPU::V_CMPX_NLT_F32_e32_gfx11:
    case AMDGPU::V_CMPX_NLT_F32_e32_gfx12:
    case AMDGPU::V_CMPX_NLT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLT_F32_e32_vi:
    case AMDGPU::V_CMPX_NLT_F64_e32_gfx10:
    case AMDGPU::V_CMPX_NLT_F64_e32_gfx11:
    case AMDGPU::V_CMPX_NLT_F64_e32_gfx12:
    case AMDGPU::V_CMPX_NLT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLT_F64_e32_vi:
    case AMDGPU::V_CMPX_O_F16_e32_gfx10:
    case AMDGPU::V_CMPX_O_F16_e32_vi:
    case AMDGPU::V_CMPX_O_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_O_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_O_F32_e32_gfx10:
    case AMDGPU::V_CMPX_O_F32_e32_gfx11:
    case AMDGPU::V_CMPX_O_F32_e32_gfx12:
    case AMDGPU::V_CMPX_O_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_O_F32_e32_vi:
    case AMDGPU::V_CMPX_O_F64_e32_gfx10:
    case AMDGPU::V_CMPX_O_F64_e32_gfx11:
    case AMDGPU::V_CMPX_O_F64_e32_gfx12:
    case AMDGPU::V_CMPX_O_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_O_F64_e32_vi:
    case AMDGPU::V_CMPX_TRU_F16_e32_gfx10:
    case AMDGPU::V_CMPX_TRU_F16_e32_vi:
    case AMDGPU::V_CMPX_TRU_F32_e32_gfx10:
    case AMDGPU::V_CMPX_TRU_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_TRU_F32_e32_vi:
    case AMDGPU::V_CMPX_TRU_F64_e32_gfx10:
    case AMDGPU::V_CMPX_TRU_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_TRU_F64_e32_vi:
    case AMDGPU::V_CMPX_T_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_T_F32_e32_gfx11:
    case AMDGPU::V_CMPX_T_F64_e32_gfx11:
    case AMDGPU::V_CMPX_T_I16_e32_vi:
    case AMDGPU::V_CMPX_T_I32_e32_gfx10:
    case AMDGPU::V_CMPX_T_I32_e32_gfx11:
    case AMDGPU::V_CMPX_T_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_T_I32_e32_vi:
    case AMDGPU::V_CMPX_T_I64_e32_gfx10:
    case AMDGPU::V_CMPX_T_I64_e32_gfx11:
    case AMDGPU::V_CMPX_T_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_T_I64_e32_vi:
    case AMDGPU::V_CMPX_T_U16_e32_vi:
    case AMDGPU::V_CMPX_T_U32_e32_gfx10:
    case AMDGPU::V_CMPX_T_U32_e32_gfx11:
    case AMDGPU::V_CMPX_T_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_T_U32_e32_vi:
    case AMDGPU::V_CMPX_T_U64_e32_gfx10:
    case AMDGPU::V_CMPX_T_U64_e32_gfx11:
    case AMDGPU::V_CMPX_T_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_T_U64_e32_vi:
    case AMDGPU::V_CMPX_U_F16_e32_gfx10:
    case AMDGPU::V_CMPX_U_F16_e32_vi:
    case AMDGPU::V_CMPX_U_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_U_F32_e32_gfx10:
    case AMDGPU::V_CMPX_U_F32_e32_gfx11:
    case AMDGPU::V_CMPX_U_F32_e32_gfx12:
    case AMDGPU::V_CMPX_U_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_U_F32_e32_vi:
    case AMDGPU::V_CMPX_U_F64_e32_gfx10:
    case AMDGPU::V_CMPX_U_F64_e32_gfx11:
    case AMDGPU::V_CMPX_U_F64_e32_gfx12:
    case AMDGPU::V_CMPX_U_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_U_F64_e32_vi:
    case AMDGPU::V_CMP_CLASS_F16_e32_gfx10:
    case AMDGPU::V_CMP_CLASS_F16_e32_vi:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_CLASS_F32_e32_gfx10:
    case AMDGPU::V_CMP_CLASS_F32_e32_gfx11:
    case AMDGPU::V_CMP_CLASS_F32_e32_gfx12:
    case AMDGPU::V_CMP_CLASS_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_CLASS_F32_e32_vi:
    case AMDGPU::V_CMP_CLASS_F64_e32_gfx10:
    case AMDGPU::V_CMP_CLASS_F64_e32_gfx11:
    case AMDGPU::V_CMP_CLASS_F64_e32_gfx12:
    case AMDGPU::V_CMP_CLASS_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_CLASS_F64_e32_vi:
    case AMDGPU::V_CMP_EQ_F16_e32_gfx10:
    case AMDGPU::V_CMP_EQ_F16_e32_vi:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e32_gfx10:
    case AMDGPU::V_CMP_EQ_F32_e32_gfx11:
    case AMDGPU::V_CMP_EQ_F32_e32_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_F32_e32_vi:
    case AMDGPU::V_CMP_EQ_F64_e32_gfx10:
    case AMDGPU::V_CMP_EQ_F64_e32_gfx11:
    case AMDGPU::V_CMP_EQ_F64_e32_gfx12:
    case AMDGPU::V_CMP_EQ_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_F64_e32_vi:
    case AMDGPU::V_CMP_EQ_I16_e32_gfx10:
    case AMDGPU::V_CMP_EQ_I16_e32_vi:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e32_gfx10:
    case AMDGPU::V_CMP_EQ_I32_e32_gfx11:
    case AMDGPU::V_CMP_EQ_I32_e32_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_I32_e32_vi:
    case AMDGPU::V_CMP_EQ_I64_e32_gfx10:
    case AMDGPU::V_CMP_EQ_I64_e32_gfx11:
    case AMDGPU::V_CMP_EQ_I64_e32_gfx12:
    case AMDGPU::V_CMP_EQ_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_I64_e32_vi:
    case AMDGPU::V_CMP_EQ_U16_e32_gfx10:
    case AMDGPU::V_CMP_EQ_U16_e32_vi:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e32_gfx10:
    case AMDGPU::V_CMP_EQ_U32_e32_gfx11:
    case AMDGPU::V_CMP_EQ_U32_e32_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_U32_e32_vi:
    case AMDGPU::V_CMP_EQ_U64_e32_gfx10:
    case AMDGPU::V_CMP_EQ_U64_e32_gfx11:
    case AMDGPU::V_CMP_EQ_U64_e32_gfx12:
    case AMDGPU::V_CMP_EQ_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_U64_e32_vi:
    case AMDGPU::V_CMP_F_F16_e32_gfx10:
    case AMDGPU::V_CMP_F_F16_e32_vi:
    case AMDGPU::V_CMP_F_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_F_F32_e32_gfx10:
    case AMDGPU::V_CMP_F_F32_e32_gfx11:
    case AMDGPU::V_CMP_F_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_F_F32_e32_vi:
    case AMDGPU::V_CMP_F_F64_e32_gfx10:
    case AMDGPU::V_CMP_F_F64_e32_gfx11:
    case AMDGPU::V_CMP_F_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_F_F64_e32_vi:
    case AMDGPU::V_CMP_F_I16_e32_vi:
    case AMDGPU::V_CMP_F_I32_e32_gfx10:
    case AMDGPU::V_CMP_F_I32_e32_gfx11:
    case AMDGPU::V_CMP_F_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_F_I32_e32_vi:
    case AMDGPU::V_CMP_F_I64_e32_gfx10:
    case AMDGPU::V_CMP_F_I64_e32_gfx11:
    case AMDGPU::V_CMP_F_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_F_I64_e32_vi:
    case AMDGPU::V_CMP_F_U16_e32_vi:
    case AMDGPU::V_CMP_F_U32_e32_gfx10:
    case AMDGPU::V_CMP_F_U32_e32_gfx11:
    case AMDGPU::V_CMP_F_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_F_U32_e32_vi:
    case AMDGPU::V_CMP_F_U64_e32_gfx10:
    case AMDGPU::V_CMP_F_U64_e32_gfx11:
    case AMDGPU::V_CMP_F_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_F_U64_e32_vi:
    case AMDGPU::V_CMP_GE_F16_e32_gfx10:
    case AMDGPU::V_CMP_GE_F16_e32_vi:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_GE_F32_e32_gfx10:
    case AMDGPU::V_CMP_GE_F32_e32_gfx11:
    case AMDGPU::V_CMP_GE_F32_e32_gfx12:
    case AMDGPU::V_CMP_GE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_F32_e32_vi:
    case AMDGPU::V_CMP_GE_F64_e32_gfx10:
    case AMDGPU::V_CMP_GE_F64_e32_gfx11:
    case AMDGPU::V_CMP_GE_F64_e32_gfx12:
    case AMDGPU::V_CMP_GE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_F64_e32_vi:
    case AMDGPU::V_CMP_GE_I16_e32_gfx10:
    case AMDGPU::V_CMP_GE_I16_e32_vi:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_GE_I32_e32_gfx10:
    case AMDGPU::V_CMP_GE_I32_e32_gfx11:
    case AMDGPU::V_CMP_GE_I32_e32_gfx12:
    case AMDGPU::V_CMP_GE_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_I32_e32_vi:
    case AMDGPU::V_CMP_GE_I64_e32_gfx10:
    case AMDGPU::V_CMP_GE_I64_e32_gfx11:
    case AMDGPU::V_CMP_GE_I64_e32_gfx12:
    case AMDGPU::V_CMP_GE_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_I64_e32_vi:
    case AMDGPU::V_CMP_GE_U16_e32_gfx10:
    case AMDGPU::V_CMP_GE_U16_e32_vi:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_GE_U32_e32_gfx10:
    case AMDGPU::V_CMP_GE_U32_e32_gfx11:
    case AMDGPU::V_CMP_GE_U32_e32_gfx12:
    case AMDGPU::V_CMP_GE_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_U32_e32_vi:
    case AMDGPU::V_CMP_GE_U64_e32_gfx10:
    case AMDGPU::V_CMP_GE_U64_e32_gfx11:
    case AMDGPU::V_CMP_GE_U64_e32_gfx12:
    case AMDGPU::V_CMP_GE_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_U64_e32_vi:
    case AMDGPU::V_CMP_GT_F16_e32_gfx10:
    case AMDGPU::V_CMP_GT_F16_e32_vi:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_GT_F32_e32_gfx10:
    case AMDGPU::V_CMP_GT_F32_e32_gfx11:
    case AMDGPU::V_CMP_GT_F32_e32_gfx12:
    case AMDGPU::V_CMP_GT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_F32_e32_vi:
    case AMDGPU::V_CMP_GT_F64_e32_gfx10:
    case AMDGPU::V_CMP_GT_F64_e32_gfx11:
    case AMDGPU::V_CMP_GT_F64_e32_gfx12:
    case AMDGPU::V_CMP_GT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_F64_e32_vi:
    case AMDGPU::V_CMP_GT_I16_e32_gfx10:
    case AMDGPU::V_CMP_GT_I16_e32_vi:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_GT_I32_e32_gfx10:
    case AMDGPU::V_CMP_GT_I32_e32_gfx11:
    case AMDGPU::V_CMP_GT_I32_e32_gfx12:
    case AMDGPU::V_CMP_GT_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_I32_e32_vi:
    case AMDGPU::V_CMP_GT_I64_e32_gfx10:
    case AMDGPU::V_CMP_GT_I64_e32_gfx11:
    case AMDGPU::V_CMP_GT_I64_e32_gfx12:
    case AMDGPU::V_CMP_GT_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_I64_e32_vi:
    case AMDGPU::V_CMP_GT_U16_e32_gfx10:
    case AMDGPU::V_CMP_GT_U16_e32_vi:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_GT_U32_e32_gfx10:
    case AMDGPU::V_CMP_GT_U32_e32_gfx11:
    case AMDGPU::V_CMP_GT_U32_e32_gfx12:
    case AMDGPU::V_CMP_GT_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_U32_e32_vi:
    case AMDGPU::V_CMP_GT_U64_e32_gfx10:
    case AMDGPU::V_CMP_GT_U64_e32_gfx11:
    case AMDGPU::V_CMP_GT_U64_e32_gfx12:
    case AMDGPU::V_CMP_GT_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_U64_e32_vi:
    case AMDGPU::V_CMP_LE_F16_e32_gfx10:
    case AMDGPU::V_CMP_LE_F16_e32_vi:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_LE_F32_e32_gfx10:
    case AMDGPU::V_CMP_LE_F32_e32_gfx11:
    case AMDGPU::V_CMP_LE_F32_e32_gfx12:
    case AMDGPU::V_CMP_LE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_F32_e32_vi:
    case AMDGPU::V_CMP_LE_F64_e32_gfx10:
    case AMDGPU::V_CMP_LE_F64_e32_gfx11:
    case AMDGPU::V_CMP_LE_F64_e32_gfx12:
    case AMDGPU::V_CMP_LE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_F64_e32_vi:
    case AMDGPU::V_CMP_LE_I16_e32_gfx10:
    case AMDGPU::V_CMP_LE_I16_e32_vi:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_LE_I32_e32_gfx10:
    case AMDGPU::V_CMP_LE_I32_e32_gfx11:
    case AMDGPU::V_CMP_LE_I32_e32_gfx12:
    case AMDGPU::V_CMP_LE_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_I32_e32_vi:
    case AMDGPU::V_CMP_LE_I64_e32_gfx10:
    case AMDGPU::V_CMP_LE_I64_e32_gfx11:
    case AMDGPU::V_CMP_LE_I64_e32_gfx12:
    case AMDGPU::V_CMP_LE_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_I64_e32_vi:
    case AMDGPU::V_CMP_LE_U16_e32_gfx10:
    case AMDGPU::V_CMP_LE_U16_e32_vi:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_LE_U32_e32_gfx10:
    case AMDGPU::V_CMP_LE_U32_e32_gfx11:
    case AMDGPU::V_CMP_LE_U32_e32_gfx12:
    case AMDGPU::V_CMP_LE_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_U32_e32_vi:
    case AMDGPU::V_CMP_LE_U64_e32_gfx10:
    case AMDGPU::V_CMP_LE_U64_e32_gfx11:
    case AMDGPU::V_CMP_LE_U64_e32_gfx12:
    case AMDGPU::V_CMP_LE_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_U64_e32_vi:
    case AMDGPU::V_CMP_LG_F16_e32_gfx10:
    case AMDGPU::V_CMP_LG_F16_e32_vi:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_LG_F32_e32_gfx10:
    case AMDGPU::V_CMP_LG_F32_e32_gfx11:
    case AMDGPU::V_CMP_LG_F32_e32_gfx12:
    case AMDGPU::V_CMP_LG_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LG_F32_e32_vi:
    case AMDGPU::V_CMP_LG_F64_e32_gfx10:
    case AMDGPU::V_CMP_LG_F64_e32_gfx11:
    case AMDGPU::V_CMP_LG_F64_e32_gfx12:
    case AMDGPU::V_CMP_LG_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LG_F64_e32_vi:
    case AMDGPU::V_CMP_LT_F16_e32_gfx10:
    case AMDGPU::V_CMP_LT_F16_e32_vi:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_LT_F32_e32_gfx10:
    case AMDGPU::V_CMP_LT_F32_e32_gfx11:
    case AMDGPU::V_CMP_LT_F32_e32_gfx12:
    case AMDGPU::V_CMP_LT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_F32_e32_vi:
    case AMDGPU::V_CMP_LT_F64_e32_gfx10:
    case AMDGPU::V_CMP_LT_F64_e32_gfx11:
    case AMDGPU::V_CMP_LT_F64_e32_gfx12:
    case AMDGPU::V_CMP_LT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_F64_e32_vi:
    case AMDGPU::V_CMP_LT_I16_e32_gfx10:
    case AMDGPU::V_CMP_LT_I16_e32_vi:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_LT_I32_e32_gfx10:
    case AMDGPU::V_CMP_LT_I32_e32_gfx11:
    case AMDGPU::V_CMP_LT_I32_e32_gfx12:
    case AMDGPU::V_CMP_LT_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_I32_e32_vi:
    case AMDGPU::V_CMP_LT_I64_e32_gfx10:
    case AMDGPU::V_CMP_LT_I64_e32_gfx11:
    case AMDGPU::V_CMP_LT_I64_e32_gfx12:
    case AMDGPU::V_CMP_LT_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_I64_e32_vi:
    case AMDGPU::V_CMP_LT_U16_e32_gfx10:
    case AMDGPU::V_CMP_LT_U16_e32_vi:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_LT_U32_e32_gfx10:
    case AMDGPU::V_CMP_LT_U32_e32_gfx11:
    case AMDGPU::V_CMP_LT_U32_e32_gfx12:
    case AMDGPU::V_CMP_LT_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_U32_e32_vi:
    case AMDGPU::V_CMP_LT_U64_e32_gfx10:
    case AMDGPU::V_CMP_LT_U64_e32_gfx11:
    case AMDGPU::V_CMP_LT_U64_e32_gfx12:
    case AMDGPU::V_CMP_LT_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_U64_e32_vi:
    case AMDGPU::V_CMP_NEQ_F16_e32_gfx10:
    case AMDGPU::V_CMP_NEQ_F16_e32_vi:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e32_gfx10:
    case AMDGPU::V_CMP_NEQ_F32_e32_gfx11:
    case AMDGPU::V_CMP_NEQ_F32_e32_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NEQ_F32_e32_vi:
    case AMDGPU::V_CMP_NEQ_F64_e32_gfx10:
    case AMDGPU::V_CMP_NEQ_F64_e32_gfx11:
    case AMDGPU::V_CMP_NEQ_F64_e32_gfx12:
    case AMDGPU::V_CMP_NEQ_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NEQ_F64_e32_vi:
    case AMDGPU::V_CMP_NE_I16_e32_gfx10:
    case AMDGPU::V_CMP_NE_I16_e32_vi:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_NE_I32_e32_gfx10:
    case AMDGPU::V_CMP_NE_I32_e32_gfx11:
    case AMDGPU::V_CMP_NE_I32_e32_gfx12:
    case AMDGPU::V_CMP_NE_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NE_I32_e32_vi:
    case AMDGPU::V_CMP_NE_I64_e32_gfx10:
    case AMDGPU::V_CMP_NE_I64_e32_gfx11:
    case AMDGPU::V_CMP_NE_I64_e32_gfx12:
    case AMDGPU::V_CMP_NE_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NE_I64_e32_vi:
    case AMDGPU::V_CMP_NE_U16_e32_gfx10:
    case AMDGPU::V_CMP_NE_U16_e32_vi:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_NE_U32_e32_gfx10:
    case AMDGPU::V_CMP_NE_U32_e32_gfx11:
    case AMDGPU::V_CMP_NE_U32_e32_gfx12:
    case AMDGPU::V_CMP_NE_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NE_U32_e32_vi:
    case AMDGPU::V_CMP_NE_U64_e32_gfx10:
    case AMDGPU::V_CMP_NE_U64_e32_gfx11:
    case AMDGPU::V_CMP_NE_U64_e32_gfx12:
    case AMDGPU::V_CMP_NE_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NE_U64_e32_vi:
    case AMDGPU::V_CMP_NGE_F16_e32_gfx10:
    case AMDGPU::V_CMP_NGE_F16_e32_vi:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e32_gfx10:
    case AMDGPU::V_CMP_NGE_F32_e32_gfx11:
    case AMDGPU::V_CMP_NGE_F32_e32_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NGE_F32_e32_vi:
    case AMDGPU::V_CMP_NGE_F64_e32_gfx10:
    case AMDGPU::V_CMP_NGE_F64_e32_gfx11:
    case AMDGPU::V_CMP_NGE_F64_e32_gfx12:
    case AMDGPU::V_CMP_NGE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NGE_F64_e32_vi:
    case AMDGPU::V_CMP_NGT_F16_e32_gfx10:
    case AMDGPU::V_CMP_NGT_F16_e32_vi:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e32_gfx10:
    case AMDGPU::V_CMP_NGT_F32_e32_gfx11:
    case AMDGPU::V_CMP_NGT_F32_e32_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NGT_F32_e32_vi:
    case AMDGPU::V_CMP_NGT_F64_e32_gfx10:
    case AMDGPU::V_CMP_NGT_F64_e32_gfx11:
    case AMDGPU::V_CMP_NGT_F64_e32_gfx12:
    case AMDGPU::V_CMP_NGT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NGT_F64_e32_vi:
    case AMDGPU::V_CMP_NLE_F16_e32_gfx10:
    case AMDGPU::V_CMP_NLE_F16_e32_vi:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e32_gfx10:
    case AMDGPU::V_CMP_NLE_F32_e32_gfx11:
    case AMDGPU::V_CMP_NLE_F32_e32_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NLE_F32_e32_vi:
    case AMDGPU::V_CMP_NLE_F64_e32_gfx10:
    case AMDGPU::V_CMP_NLE_F64_e32_gfx11:
    case AMDGPU::V_CMP_NLE_F64_e32_gfx12:
    case AMDGPU::V_CMP_NLE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NLE_F64_e32_vi:
    case AMDGPU::V_CMP_NLG_F16_e32_gfx10:
    case AMDGPU::V_CMP_NLG_F16_e32_vi:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e32_gfx10:
    case AMDGPU::V_CMP_NLG_F32_e32_gfx11:
    case AMDGPU::V_CMP_NLG_F32_e32_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NLG_F32_e32_vi:
    case AMDGPU::V_CMP_NLG_F64_e32_gfx10:
    case AMDGPU::V_CMP_NLG_F64_e32_gfx11:
    case AMDGPU::V_CMP_NLG_F64_e32_gfx12:
    case AMDGPU::V_CMP_NLG_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NLG_F64_e32_vi:
    case AMDGPU::V_CMP_NLT_F16_e32_gfx10:
    case AMDGPU::V_CMP_NLT_F16_e32_vi:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e32_gfx10:
    case AMDGPU::V_CMP_NLT_F32_e32_gfx11:
    case AMDGPU::V_CMP_NLT_F32_e32_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NLT_F32_e32_vi:
    case AMDGPU::V_CMP_NLT_F64_e32_gfx10:
    case AMDGPU::V_CMP_NLT_F64_e32_gfx11:
    case AMDGPU::V_CMP_NLT_F64_e32_gfx12:
    case AMDGPU::V_CMP_NLT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NLT_F64_e32_vi:
    case AMDGPU::V_CMP_O_F16_e32_gfx10:
    case AMDGPU::V_CMP_O_F16_e32_vi:
    case AMDGPU::V_CMP_O_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_O_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_O_F32_e32_gfx10:
    case AMDGPU::V_CMP_O_F32_e32_gfx11:
    case AMDGPU::V_CMP_O_F32_e32_gfx12:
    case AMDGPU::V_CMP_O_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_O_F32_e32_vi:
    case AMDGPU::V_CMP_O_F64_e32_gfx10:
    case AMDGPU::V_CMP_O_F64_e32_gfx11:
    case AMDGPU::V_CMP_O_F64_e32_gfx12:
    case AMDGPU::V_CMP_O_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_O_F64_e32_vi:
    case AMDGPU::V_CMP_TRU_F16_e32_gfx10:
    case AMDGPU::V_CMP_TRU_F16_e32_vi:
    case AMDGPU::V_CMP_TRU_F32_e32_gfx10:
    case AMDGPU::V_CMP_TRU_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_TRU_F32_e32_vi:
    case AMDGPU::V_CMP_TRU_F64_e32_gfx10:
    case AMDGPU::V_CMP_TRU_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_TRU_F64_e32_vi:
    case AMDGPU::V_CMP_T_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_T_F32_e32_gfx11:
    case AMDGPU::V_CMP_T_F64_e32_gfx11:
    case AMDGPU::V_CMP_T_I16_e32_vi:
    case AMDGPU::V_CMP_T_I32_e32_gfx10:
    case AMDGPU::V_CMP_T_I32_e32_gfx11:
    case AMDGPU::V_CMP_T_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_T_I32_e32_vi:
    case AMDGPU::V_CMP_T_I64_e32_gfx10:
    case AMDGPU::V_CMP_T_I64_e32_gfx11:
    case AMDGPU::V_CMP_T_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_T_I64_e32_vi:
    case AMDGPU::V_CMP_T_U16_e32_vi:
    case AMDGPU::V_CMP_T_U32_e32_gfx10:
    case AMDGPU::V_CMP_T_U32_e32_gfx11:
    case AMDGPU::V_CMP_T_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_T_U32_e32_vi:
    case AMDGPU::V_CMP_T_U64_e32_gfx10:
    case AMDGPU::V_CMP_T_U64_e32_gfx11:
    case AMDGPU::V_CMP_T_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_T_U64_e32_vi:
    case AMDGPU::V_CMP_U_F16_e32_gfx10:
    case AMDGPU::V_CMP_U_F16_e32_vi:
    case AMDGPU::V_CMP_U_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_U_F32_e32_gfx10:
    case AMDGPU::V_CMP_U_F32_e32_gfx11:
    case AMDGPU::V_CMP_U_F32_e32_gfx12:
    case AMDGPU::V_CMP_U_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_U_F32_e32_vi:
    case AMDGPU::V_CMP_U_F64_e32_gfx10:
    case AMDGPU::V_CMP_U_F64_e32_gfx11:
    case AMDGPU::V_CMP_U_F64_e32_gfx12:
    case AMDGPU::V_CMP_U_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_U_F64_e32_vi: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_WMMA_LD_SCALE16_PAIRED_B64_gfx1250:
    case AMDGPU::V_WMMA_LD_SCALE_PAIRED_B32_gfx1250: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: matrix_a_scale
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      // op: matrix_b_scale
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 59, 1);
      // op: matrix_a_scale_fmt
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 61, 2);
      // op: matrix_b_scale_fmt
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 8, 2);
      // op: matrix_a_reuse
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: matrix_b_reuse
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      break;
    }
    case AMDGPU::V_CMPX_EQ_I16_e64_gfx10:
    case AMDGPU::V_CMPX_EQ_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_EQ_I32_e64_gfx10:
    case AMDGPU::V_CMPX_EQ_I32_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_I32_e64_gfx12:
    case AMDGPU::V_CMPX_EQ_I64_e64_gfx10:
    case AMDGPU::V_CMPX_EQ_I64_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_I64_e64_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_e64_gfx10:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_EQ_U32_e64_gfx10:
    case AMDGPU::V_CMPX_EQ_U32_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_U32_e64_gfx12:
    case AMDGPU::V_CMPX_EQ_U64_e64_gfx10:
    case AMDGPU::V_CMPX_EQ_U64_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_U64_e64_gfx12:
    case AMDGPU::V_CMPX_F_I32_e64_gfx10:
    case AMDGPU::V_CMPX_F_I32_e64_gfx11:
    case AMDGPU::V_CMPX_F_I64_e64_gfx10:
    case AMDGPU::V_CMPX_F_I64_e64_gfx11:
    case AMDGPU::V_CMPX_F_U32_e64_gfx10:
    case AMDGPU::V_CMPX_F_U32_e64_gfx11:
    case AMDGPU::V_CMPX_F_U64_e64_gfx10:
    case AMDGPU::V_CMPX_F_U64_e64_gfx11:
    case AMDGPU::V_CMPX_GE_I16_e64_gfx10:
    case AMDGPU::V_CMPX_GE_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_GE_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_GE_I32_e64_gfx10:
    case AMDGPU::V_CMPX_GE_I32_e64_gfx11:
    case AMDGPU::V_CMPX_GE_I32_e64_gfx12:
    case AMDGPU::V_CMPX_GE_I64_e64_gfx10:
    case AMDGPU::V_CMPX_GE_I64_e64_gfx11:
    case AMDGPU::V_CMPX_GE_I64_e64_gfx12:
    case AMDGPU::V_CMPX_GE_U16_e64_gfx10:
    case AMDGPU::V_CMPX_GE_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_GE_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_GE_U32_e64_gfx10:
    case AMDGPU::V_CMPX_GE_U32_e64_gfx11:
    case AMDGPU::V_CMPX_GE_U32_e64_gfx12:
    case AMDGPU::V_CMPX_GE_U64_e64_gfx10:
    case AMDGPU::V_CMPX_GE_U64_e64_gfx11:
    case AMDGPU::V_CMPX_GE_U64_e64_gfx12:
    case AMDGPU::V_CMPX_GT_I16_e64_gfx10:
    case AMDGPU::V_CMPX_GT_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_GT_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_GT_I32_e64_gfx10:
    case AMDGPU::V_CMPX_GT_I32_e64_gfx11:
    case AMDGPU::V_CMPX_GT_I32_e64_gfx12:
    case AMDGPU::V_CMPX_GT_I64_e64_gfx10:
    case AMDGPU::V_CMPX_GT_I64_e64_gfx11:
    case AMDGPU::V_CMPX_GT_I64_e64_gfx12:
    case AMDGPU::V_CMPX_GT_U16_e64_gfx10:
    case AMDGPU::V_CMPX_GT_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_GT_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_GT_U32_e64_gfx10:
    case AMDGPU::V_CMPX_GT_U32_e64_gfx11:
    case AMDGPU::V_CMPX_GT_U32_e64_gfx12:
    case AMDGPU::V_CMPX_GT_U64_e64_gfx10:
    case AMDGPU::V_CMPX_GT_U64_e64_gfx11:
    case AMDGPU::V_CMPX_GT_U64_e64_gfx12:
    case AMDGPU::V_CMPX_LE_I16_e64_gfx10:
    case AMDGPU::V_CMPX_LE_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_LE_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_LE_I32_e64_gfx10:
    case AMDGPU::V_CMPX_LE_I32_e64_gfx11:
    case AMDGPU::V_CMPX_LE_I32_e64_gfx12:
    case AMDGPU::V_CMPX_LE_I64_e64_gfx10:
    case AMDGPU::V_CMPX_LE_I64_e64_gfx11:
    case AMDGPU::V_CMPX_LE_I64_e64_gfx12:
    case AMDGPU::V_CMPX_LE_U16_e64_gfx10:
    case AMDGPU::V_CMPX_LE_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_LE_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_LE_U32_e64_gfx10:
    case AMDGPU::V_CMPX_LE_U32_e64_gfx11:
    case AMDGPU::V_CMPX_LE_U32_e64_gfx12:
    case AMDGPU::V_CMPX_LE_U64_e64_gfx10:
    case AMDGPU::V_CMPX_LE_U64_e64_gfx11:
    case AMDGPU::V_CMPX_LE_U64_e64_gfx12:
    case AMDGPU::V_CMPX_LT_I16_e64_gfx10:
    case AMDGPU::V_CMPX_LT_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_LT_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_LT_I32_e64_gfx10:
    case AMDGPU::V_CMPX_LT_I32_e64_gfx11:
    case AMDGPU::V_CMPX_LT_I32_e64_gfx12:
    case AMDGPU::V_CMPX_LT_I64_e64_gfx10:
    case AMDGPU::V_CMPX_LT_I64_e64_gfx11:
    case AMDGPU::V_CMPX_LT_I64_e64_gfx12:
    case AMDGPU::V_CMPX_LT_U16_e64_gfx10:
    case AMDGPU::V_CMPX_LT_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_LT_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_LT_U32_e64_gfx10:
    case AMDGPU::V_CMPX_LT_U32_e64_gfx11:
    case AMDGPU::V_CMPX_LT_U32_e64_gfx12:
    case AMDGPU::V_CMPX_LT_U64_e64_gfx10:
    case AMDGPU::V_CMPX_LT_U64_e64_gfx11:
    case AMDGPU::V_CMPX_LT_U64_e64_gfx12:
    case AMDGPU::V_CMPX_NE_I16_e64_gfx10:
    case AMDGPU::V_CMPX_NE_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_NE_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_NE_I32_e64_gfx10:
    case AMDGPU::V_CMPX_NE_I32_e64_gfx11:
    case AMDGPU::V_CMPX_NE_I32_e64_gfx12:
    case AMDGPU::V_CMPX_NE_I64_e64_gfx10:
    case AMDGPU::V_CMPX_NE_I64_e64_gfx11:
    case AMDGPU::V_CMPX_NE_I64_e64_gfx12:
    case AMDGPU::V_CMPX_NE_U16_e64_gfx10:
    case AMDGPU::V_CMPX_NE_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_NE_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_NE_U32_e64_gfx10:
    case AMDGPU::V_CMPX_NE_U32_e64_gfx11:
    case AMDGPU::V_CMPX_NE_U32_e64_gfx12:
    case AMDGPU::V_CMPX_NE_U64_e64_gfx10:
    case AMDGPU::V_CMPX_NE_U64_e64_gfx11:
    case AMDGPU::V_CMPX_NE_U64_e64_gfx12:
    case AMDGPU::V_CMPX_T_I32_e64_gfx10:
    case AMDGPU::V_CMPX_T_I32_e64_gfx11:
    case AMDGPU::V_CMPX_T_I64_e64_gfx10:
    case AMDGPU::V_CMPX_T_I64_e64_gfx11:
    case AMDGPU::V_CMPX_T_U32_e64_gfx10:
    case AMDGPU::V_CMPX_T_U32_e64_gfx11:
    case AMDGPU::V_CMPX_T_U64_e64_gfx10:
    case AMDGPU::V_CMPX_T_U64_e64_gfx11: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_CVT_F32_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_UBYTE0_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_UBYTE1_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_UBYTE2_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_UBYTE3_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F64_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F64_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_OFF_F32_I4_e64_gfx6_gfx7: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_F16_I16_e64_gfx10:
    case AMDGPU::V_CVT_F16_I16_e64_vi:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_F16_U16_e64_gfx10:
    case AMDGPU::V_CVT_F16_U16_e64_vi:
    case AMDGPU::V_CVT_F32_BF8_e64_vi:
    case AMDGPU::V_CVT_F32_FP8_e64_vi:
    case AMDGPU::V_CVT_F32_I32_e64_gfx10:
    case AMDGPU::V_CVT_F32_I32_e64_gfx11:
    case AMDGPU::V_CVT_F32_I32_e64_gfx12:
    case AMDGPU::V_CVT_F32_I32_e64_vi:
    case AMDGPU::V_CVT_F32_U32_e64_gfx10:
    case AMDGPU::V_CVT_F32_U32_e64_gfx11:
    case AMDGPU::V_CVT_F32_U32_e64_gfx12:
    case AMDGPU::V_CVT_F32_U32_e64_vi:
    case AMDGPU::V_CVT_F32_UBYTE0_e64_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE0_e64_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE0_e64_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE0_e64_vi:
    case AMDGPU::V_CVT_F32_UBYTE1_e64_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE1_e64_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE1_e64_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE1_e64_vi:
    case AMDGPU::V_CVT_F32_UBYTE2_e64_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE2_e64_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE2_e64_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE2_e64_vi:
    case AMDGPU::V_CVT_F32_UBYTE3_e64_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE3_e64_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE3_e64_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE3_e64_vi:
    case AMDGPU::V_CVT_F64_I32_e64_gfx10:
    case AMDGPU::V_CVT_F64_I32_e64_gfx11:
    case AMDGPU::V_CVT_F64_I32_e64_gfx12:
    case AMDGPU::V_CVT_F64_I32_e64_vi:
    case AMDGPU::V_CVT_F64_U32_e64_gfx10:
    case AMDGPU::V_CVT_F64_U32_e64_gfx11:
    case AMDGPU::V_CVT_F64_U32_e64_gfx12:
    case AMDGPU::V_CVT_F64_U32_e64_vi:
    case AMDGPU::V_CVT_OFF_F32_I4_e64_gfx10:
    case AMDGPU::V_CVT_OFF_F32_I4_e64_gfx11:
    case AMDGPU::V_CVT_OFF_F32_I4_e64_gfx12:
    case AMDGPU::V_CVT_OFF_F32_I4_e64_vi:
    case AMDGPU::V_CVT_PK_F32_BF8_e64_vi:
    case AMDGPU::V_CVT_PK_F32_FP8_e64_vi: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_F32_FP8_e64_gfx1250: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 11, 1);
      break;
    }
    case AMDGPU::V_MUL_I32_I24_e64_gfx6_gfx7:
    case AMDGPU::V_MUL_U32_U24_e64_gfx6_gfx7: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_ADD_I32_vi:
    case AMDGPU::V_ADD_NC_I32_e64_gfx11:
    case AMDGPU::V_ADD_NC_I32_e64_gfx12:
    case AMDGPU::V_ADD_NC_I32_gfx10:
    case AMDGPU::V_ADD_NC_U32_e64_gfx10:
    case AMDGPU::V_ADD_NC_U32_e64_gfx11:
    case AMDGPU::V_ADD_NC_U32_e64_gfx12:
    case AMDGPU::V_ADD_U16_e64_vi:
    case AMDGPU::V_ADD_U32_e64_gfx9:
    case AMDGPU::V_ADD_U64_e64_gfx1250:
    case AMDGPU::V_MUL_I32_I24_e64_gfx10:
    case AMDGPU::V_MUL_I32_I24_e64_gfx11:
    case AMDGPU::V_MUL_I32_I24_e64_gfx12:
    case AMDGPU::V_MUL_I32_I24_e64_vi:
    case AMDGPU::V_MUL_U32_U24_e64_gfx10:
    case AMDGPU::V_MUL_U32_U24_e64_gfx11:
    case AMDGPU::V_MUL_U32_U24_e64_gfx12:
    case AMDGPU::V_MUL_U32_U24_e64_vi:
    case AMDGPU::V_SUBREV_NC_U32_e64_gfx10:
    case AMDGPU::V_SUBREV_NC_U32_e64_gfx11:
    case AMDGPU::V_SUBREV_NC_U32_e64_gfx12:
    case AMDGPU::V_SUBREV_U16_e64_vi:
    case AMDGPU::V_SUBREV_U32_e64_gfx9:
    case AMDGPU::V_SUB_I32_vi:
    case AMDGPU::V_SUB_NC_I32_e64_gfx11:
    case AMDGPU::V_SUB_NC_I32_e64_gfx12:
    case AMDGPU::V_SUB_NC_I32_gfx10:
    case AMDGPU::V_SUB_NC_U32_e64_gfx10:
    case AMDGPU::V_SUB_NC_U32_e64_gfx11:
    case AMDGPU::V_SUB_NC_U32_e64_gfx12:
    case AMDGPU::V_SUB_U16_e64_vi:
    case AMDGPU::V_SUB_U32_e64_gfx9:
    case AMDGPU::V_SUB_U64_e64_gfx1250: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CMPX_EQ_I16_e64_vi:
    case AMDGPU::V_CMPX_EQ_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_I32_e64_vi:
    case AMDGPU::V_CMPX_EQ_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_I64_e64_vi:
    case AMDGPU::V_CMPX_EQ_U16_e64_vi:
    case AMDGPU::V_CMPX_EQ_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_U32_e64_vi:
    case AMDGPU::V_CMPX_EQ_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_U64_e64_vi:
    case AMDGPU::V_CMPX_F_I16_e64_vi:
    case AMDGPU::V_CMPX_F_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_I32_e64_vi:
    case AMDGPU::V_CMPX_F_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_I64_e64_vi:
    case AMDGPU::V_CMPX_F_U16_e64_vi:
    case AMDGPU::V_CMPX_F_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_U32_e64_vi:
    case AMDGPU::V_CMPX_F_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_U64_e64_vi:
    case AMDGPU::V_CMPX_GE_I16_e64_vi:
    case AMDGPU::V_CMPX_GE_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_I32_e64_vi:
    case AMDGPU::V_CMPX_GE_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_I64_e64_vi:
    case AMDGPU::V_CMPX_GE_U16_e64_vi:
    case AMDGPU::V_CMPX_GE_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_U32_e64_vi:
    case AMDGPU::V_CMPX_GE_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_U64_e64_vi:
    case AMDGPU::V_CMPX_GT_I16_e64_vi:
    case AMDGPU::V_CMPX_GT_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_I32_e64_vi:
    case AMDGPU::V_CMPX_GT_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_I64_e64_vi:
    case AMDGPU::V_CMPX_GT_U16_e64_vi:
    case AMDGPU::V_CMPX_GT_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_U32_e64_vi:
    case AMDGPU::V_CMPX_GT_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_U64_e64_vi:
    case AMDGPU::V_CMPX_LE_I16_e64_vi:
    case AMDGPU::V_CMPX_LE_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_I32_e64_vi:
    case AMDGPU::V_CMPX_LE_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_I64_e64_vi:
    case AMDGPU::V_CMPX_LE_U16_e64_vi:
    case AMDGPU::V_CMPX_LE_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_U32_e64_vi:
    case AMDGPU::V_CMPX_LE_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_U64_e64_vi:
    case AMDGPU::V_CMPX_LT_I16_e64_vi:
    case AMDGPU::V_CMPX_LT_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_I32_e64_vi:
    case AMDGPU::V_CMPX_LT_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_I64_e64_vi:
    case AMDGPU::V_CMPX_LT_U16_e64_vi:
    case AMDGPU::V_CMPX_LT_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_U32_e64_vi:
    case AMDGPU::V_CMPX_LT_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_U64_e64_vi:
    case AMDGPU::V_CMPX_NE_I16_e64_vi:
    case AMDGPU::V_CMPX_NE_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NE_I32_e64_vi:
    case AMDGPU::V_CMPX_NE_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NE_I64_e64_vi:
    case AMDGPU::V_CMPX_NE_U16_e64_vi:
    case AMDGPU::V_CMPX_NE_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NE_U32_e64_vi:
    case AMDGPU::V_CMPX_NE_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NE_U64_e64_vi:
    case AMDGPU::V_CMPX_T_I16_e64_vi:
    case AMDGPU::V_CMPX_T_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_T_I32_e64_vi:
    case AMDGPU::V_CMPX_T_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_T_I64_e64_vi:
    case AMDGPU::V_CMPX_T_U16_e64_vi:
    case AMDGPU::V_CMPX_T_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_T_U32_e64_vi:
    case AMDGPU::V_CMPX_T_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_T_U64_e64_vi:
    case AMDGPU::V_CMP_EQ_I16_e64_gfx10:
    case AMDGPU::V_CMP_EQ_I16_e64_vi:
    case AMDGPU::V_CMP_EQ_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e64_gfx10:
    case AMDGPU::V_CMP_EQ_I32_e64_gfx11:
    case AMDGPU::V_CMP_EQ_I32_e64_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_I32_e64_vi:
    case AMDGPU::V_CMP_EQ_I64_e64_gfx10:
    case AMDGPU::V_CMP_EQ_I64_e64_gfx11:
    case AMDGPU::V_CMP_EQ_I64_e64_gfx12:
    case AMDGPU::V_CMP_EQ_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_I64_e64_vi:
    case AMDGPU::V_CMP_EQ_U16_e64_gfx10:
    case AMDGPU::V_CMP_EQ_U16_e64_vi:
    case AMDGPU::V_CMP_EQ_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_EQ_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e64_gfx10:
    case AMDGPU::V_CMP_EQ_U32_e64_gfx11:
    case AMDGPU::V_CMP_EQ_U32_e64_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_U32_e64_vi:
    case AMDGPU::V_CMP_EQ_U64_e64_gfx10:
    case AMDGPU::V_CMP_EQ_U64_e64_gfx11:
    case AMDGPU::V_CMP_EQ_U64_e64_gfx12:
    case AMDGPU::V_CMP_EQ_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_U64_e64_vi:
    case AMDGPU::V_CMP_F_I16_e64_vi:
    case AMDGPU::V_CMP_F_I32_e64_gfx10:
    case AMDGPU::V_CMP_F_I32_e64_gfx11:
    case AMDGPU::V_CMP_F_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_F_I32_e64_vi:
    case AMDGPU::V_CMP_F_I64_e64_gfx10:
    case AMDGPU::V_CMP_F_I64_e64_gfx11:
    case AMDGPU::V_CMP_F_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_F_I64_e64_vi:
    case AMDGPU::V_CMP_F_U16_e64_vi:
    case AMDGPU::V_CMP_F_U32_e64_gfx10:
    case AMDGPU::V_CMP_F_U32_e64_gfx11:
    case AMDGPU::V_CMP_F_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_F_U32_e64_vi:
    case AMDGPU::V_CMP_F_U64_e64_gfx10:
    case AMDGPU::V_CMP_F_U64_e64_gfx11:
    case AMDGPU::V_CMP_F_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_F_U64_e64_vi:
    case AMDGPU::V_CMP_GE_I16_e64_gfx10:
    case AMDGPU::V_CMP_GE_I16_e64_vi:
    case AMDGPU::V_CMP_GE_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_GE_I32_e64_gfx10:
    case AMDGPU::V_CMP_GE_I32_e64_gfx11:
    case AMDGPU::V_CMP_GE_I32_e64_gfx12:
    case AMDGPU::V_CMP_GE_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_I32_e64_vi:
    case AMDGPU::V_CMP_GE_I64_e64_gfx10:
    case AMDGPU::V_CMP_GE_I64_e64_gfx11:
    case AMDGPU::V_CMP_GE_I64_e64_gfx12:
    case AMDGPU::V_CMP_GE_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_I64_e64_vi:
    case AMDGPU::V_CMP_GE_U16_e64_gfx10:
    case AMDGPU::V_CMP_GE_U16_e64_vi:
    case AMDGPU::V_CMP_GE_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_GE_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_GE_U32_e64_gfx10:
    case AMDGPU::V_CMP_GE_U32_e64_gfx11:
    case AMDGPU::V_CMP_GE_U32_e64_gfx12:
    case AMDGPU::V_CMP_GE_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_U32_e64_vi:
    case AMDGPU::V_CMP_GE_U64_e64_gfx10:
    case AMDGPU::V_CMP_GE_U64_e64_gfx11:
    case AMDGPU::V_CMP_GE_U64_e64_gfx12:
    case AMDGPU::V_CMP_GE_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_U64_e64_vi:
    case AMDGPU::V_CMP_GT_I16_e64_gfx10:
    case AMDGPU::V_CMP_GT_I16_e64_vi:
    case AMDGPU::V_CMP_GT_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_GT_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_GT_I32_e64_gfx10:
    case AMDGPU::V_CMP_GT_I32_e64_gfx11:
    case AMDGPU::V_CMP_GT_I32_e64_gfx12:
    case AMDGPU::V_CMP_GT_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_I32_e64_vi:
    case AMDGPU::V_CMP_GT_I64_e64_gfx10:
    case AMDGPU::V_CMP_GT_I64_e64_gfx11:
    case AMDGPU::V_CMP_GT_I64_e64_gfx12:
    case AMDGPU::V_CMP_GT_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_I64_e64_vi:
    case AMDGPU::V_CMP_GT_U16_e64_gfx10:
    case AMDGPU::V_CMP_GT_U16_e64_vi:
    case AMDGPU::V_CMP_GT_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_GT_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_GT_U32_e64_gfx10:
    case AMDGPU::V_CMP_GT_U32_e64_gfx11:
    case AMDGPU::V_CMP_GT_U32_e64_gfx12:
    case AMDGPU::V_CMP_GT_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_U32_e64_vi:
    case AMDGPU::V_CMP_GT_U64_e64_gfx10:
    case AMDGPU::V_CMP_GT_U64_e64_gfx11:
    case AMDGPU::V_CMP_GT_U64_e64_gfx12:
    case AMDGPU::V_CMP_GT_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_U64_e64_vi:
    case AMDGPU::V_CMP_LE_I16_e64_gfx10:
    case AMDGPU::V_CMP_LE_I16_e64_vi:
    case AMDGPU::V_CMP_LE_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_LE_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_LE_I32_e64_gfx10:
    case AMDGPU::V_CMP_LE_I32_e64_gfx11:
    case AMDGPU::V_CMP_LE_I32_e64_gfx12:
    case AMDGPU::V_CMP_LE_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_I32_e64_vi:
    case AMDGPU::V_CMP_LE_I64_e64_gfx10:
    case AMDGPU::V_CMP_LE_I64_e64_gfx11:
    case AMDGPU::V_CMP_LE_I64_e64_gfx12:
    case AMDGPU::V_CMP_LE_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_I64_e64_vi:
    case AMDGPU::V_CMP_LE_U16_e64_gfx10:
    case AMDGPU::V_CMP_LE_U16_e64_vi:
    case AMDGPU::V_CMP_LE_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_LE_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_LE_U32_e64_gfx10:
    case AMDGPU::V_CMP_LE_U32_e64_gfx11:
    case AMDGPU::V_CMP_LE_U32_e64_gfx12:
    case AMDGPU::V_CMP_LE_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_U32_e64_vi:
    case AMDGPU::V_CMP_LE_U64_e64_gfx10:
    case AMDGPU::V_CMP_LE_U64_e64_gfx11:
    case AMDGPU::V_CMP_LE_U64_e64_gfx12:
    case AMDGPU::V_CMP_LE_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_U64_e64_vi:
    case AMDGPU::V_CMP_LT_I16_e64_gfx10:
    case AMDGPU::V_CMP_LT_I16_e64_vi:
    case AMDGPU::V_CMP_LT_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_LT_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_LT_I32_e64_gfx10:
    case AMDGPU::V_CMP_LT_I32_e64_gfx11:
    case AMDGPU::V_CMP_LT_I32_e64_gfx12:
    case AMDGPU::V_CMP_LT_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_I32_e64_vi:
    case AMDGPU::V_CMP_LT_I64_e64_gfx10:
    case AMDGPU::V_CMP_LT_I64_e64_gfx11:
    case AMDGPU::V_CMP_LT_I64_e64_gfx12:
    case AMDGPU::V_CMP_LT_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_I64_e64_vi:
    case AMDGPU::V_CMP_LT_U16_e64_gfx10:
    case AMDGPU::V_CMP_LT_U16_e64_vi:
    case AMDGPU::V_CMP_LT_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_LT_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_LT_U32_e64_gfx10:
    case AMDGPU::V_CMP_LT_U32_e64_gfx11:
    case AMDGPU::V_CMP_LT_U32_e64_gfx12:
    case AMDGPU::V_CMP_LT_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_U32_e64_vi:
    case AMDGPU::V_CMP_LT_U64_e64_gfx10:
    case AMDGPU::V_CMP_LT_U64_e64_gfx11:
    case AMDGPU::V_CMP_LT_U64_e64_gfx12:
    case AMDGPU::V_CMP_LT_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_U64_e64_vi:
    case AMDGPU::V_CMP_NE_I16_e64_gfx10:
    case AMDGPU::V_CMP_NE_I16_e64_vi:
    case AMDGPU::V_CMP_NE_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_NE_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_NE_I32_e64_gfx10:
    case AMDGPU::V_CMP_NE_I32_e64_gfx11:
    case AMDGPU::V_CMP_NE_I32_e64_gfx12:
    case AMDGPU::V_CMP_NE_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NE_I32_e64_vi:
    case AMDGPU::V_CMP_NE_I64_e64_gfx10:
    case AMDGPU::V_CMP_NE_I64_e64_gfx11:
    case AMDGPU::V_CMP_NE_I64_e64_gfx12:
    case AMDGPU::V_CMP_NE_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NE_I64_e64_vi:
    case AMDGPU::V_CMP_NE_U16_e64_gfx10:
    case AMDGPU::V_CMP_NE_U16_e64_vi:
    case AMDGPU::V_CMP_NE_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_NE_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_NE_U32_e64_gfx10:
    case AMDGPU::V_CMP_NE_U32_e64_gfx11:
    case AMDGPU::V_CMP_NE_U32_e64_gfx12:
    case AMDGPU::V_CMP_NE_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NE_U32_e64_vi:
    case AMDGPU::V_CMP_NE_U64_e64_gfx10:
    case AMDGPU::V_CMP_NE_U64_e64_gfx11:
    case AMDGPU::V_CMP_NE_U64_e64_gfx12:
    case AMDGPU::V_CMP_NE_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NE_U64_e64_vi:
    case AMDGPU::V_CMP_T_I16_e64_vi:
    case AMDGPU::V_CMP_T_I32_e64_gfx10:
    case AMDGPU::V_CMP_T_I32_e64_gfx11:
    case AMDGPU::V_CMP_T_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_T_I32_e64_vi:
    case AMDGPU::V_CMP_T_I64_e64_gfx10:
    case AMDGPU::V_CMP_T_I64_e64_gfx11:
    case AMDGPU::V_CMP_T_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_T_I64_e64_vi:
    case AMDGPU::V_CMP_T_U16_e64_vi:
    case AMDGPU::V_CMP_T_U32_e64_gfx10:
    case AMDGPU::V_CMP_T_U32_e64_gfx11:
    case AMDGPU::V_CMP_T_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_T_U32_e64_vi:
    case AMDGPU::V_CMP_T_U64_e64_gfx10:
    case AMDGPU::V_CMP_T_U64_e64_gfx11:
    case AMDGPU::V_CMP_T_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_T_U64_e64_vi: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_MAD_I32_I24_gfx6_gfx7:
    case AMDGPU::V_MAD_U32_U24_gfx6_gfx7:
    case AMDGPU::V_MQSAD_PK_U16_U8_gfx6_gfx7:
    case AMDGPU::V_MQSAD_U32_U8_gfx7:
    case AMDGPU::V_MSAD_U8_gfx6_gfx7:
    case AMDGPU::V_QSAD_PK_U16_U8_gfx7:
    case AMDGPU::V_SAD_HI_U8_gfx6_gfx7:
    case AMDGPU::V_SAD_U16_gfx6_gfx7:
    case AMDGPU::V_SAD_U32_gfx6_gfx7:
    case AMDGPU::V_SAD_U8_gfx6_gfx7: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_ADD_MAX_I32_e64_gfx1250:
    case AMDGPU::V_ADD_MAX_U32_e64_gfx1250:
    case AMDGPU::V_ADD_MIN_I32_e64_gfx1250:
    case AMDGPU::V_ADD_MIN_U32_e64_gfx1250:
    case AMDGPU::V_MAD_I16_vi:
    case AMDGPU::V_MAD_I32_I24_e64_gfx11:
    case AMDGPU::V_MAD_I32_I24_e64_gfx12:
    case AMDGPU::V_MAD_I32_I24_gfx10:
    case AMDGPU::V_MAD_I32_I24_vi:
    case AMDGPU::V_MAD_LEGACY_I16_gfx9:
    case AMDGPU::V_MAD_LEGACY_U16_gfx9:
    case AMDGPU::V_MAD_NC_I64_I32_e64_gfx1250:
    case AMDGPU::V_MAD_NC_U64_U32_e64_gfx1250:
    case AMDGPU::V_MAD_U16_vi:
    case AMDGPU::V_MAD_U32_U24_e64_gfx11:
    case AMDGPU::V_MAD_U32_U24_e64_gfx12:
    case AMDGPU::V_MAD_U32_U24_gfx10:
    case AMDGPU::V_MAD_U32_U24_vi:
    case AMDGPU::V_MQSAD_PK_U16_U8_e64_gfx11:
    case AMDGPU::V_MQSAD_PK_U16_U8_e64_gfx12:
    case AMDGPU::V_MQSAD_PK_U16_U8_gfx10:
    case AMDGPU::V_MQSAD_PK_U16_U8_vi:
    case AMDGPU::V_MQSAD_U32_U8_e64_gfx11:
    case AMDGPU::V_MQSAD_U32_U8_e64_gfx12:
    case AMDGPU::V_MQSAD_U32_U8_gfx10:
    case AMDGPU::V_MQSAD_U32_U8_vi:
    case AMDGPU::V_MSAD_U8_e64_gfx11:
    case AMDGPU::V_MSAD_U8_e64_gfx12:
    case AMDGPU::V_MSAD_U8_gfx10:
    case AMDGPU::V_MSAD_U8_vi:
    case AMDGPU::V_QSAD_PK_U16_U8_e64_gfx11:
    case AMDGPU::V_QSAD_PK_U16_U8_e64_gfx12:
    case AMDGPU::V_QSAD_PK_U16_U8_gfx10:
    case AMDGPU::V_QSAD_PK_U16_U8_vi:
    case AMDGPU::V_SAD_HI_U8_e64_gfx11:
    case AMDGPU::V_SAD_HI_U8_e64_gfx12:
    case AMDGPU::V_SAD_HI_U8_gfx10:
    case AMDGPU::V_SAD_HI_U8_vi:
    case AMDGPU::V_SAD_U16_e64_gfx11:
    case AMDGPU::V_SAD_U16_e64_gfx12:
    case AMDGPU::V_SAD_U16_gfx10:
    case AMDGPU::V_SAD_U16_vi:
    case AMDGPU::V_SAD_U32_e64_gfx11:
    case AMDGPU::V_SAD_U32_e64_gfx12:
    case AMDGPU::V_SAD_U32_gfx10:
    case AMDGPU::V_SAD_U32_vi:
    case AMDGPU::V_SAD_U8_e64_gfx11:
    case AMDGPU::V_SAD_U8_e64_gfx12:
    case AMDGPU::V_SAD_U8_gfx10:
    case AMDGPU::V_SAD_U8_vi: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_ADD3_U32_e64_gfx11:
    case AMDGPU::V_ADD3_U32_e64_gfx12:
    case AMDGPU::V_ADD3_U32_gfx10:
    case AMDGPU::V_ADD3_U32_vi:
    case AMDGPU::V_ADD_LSHL_U32_e64_gfx11:
    case AMDGPU::V_ADD_LSHL_U32_e64_gfx12:
    case AMDGPU::V_ADD_LSHL_U32_gfx10:
    case AMDGPU::V_ADD_LSHL_U32_vi:
    case AMDGPU::V_ALIGNBIT_B32_gfx6_gfx7:
    case AMDGPU::V_ALIGNBIT_B32_vi:
    case AMDGPU::V_ALIGNBYTE_B32_gfx6_gfx7:
    case AMDGPU::V_ALIGNBYTE_B32_vi:
    case AMDGPU::V_AND_OR_B32_e64_gfx11:
    case AMDGPU::V_AND_OR_B32_e64_gfx12:
    case AMDGPU::V_AND_OR_B32_gfx10:
    case AMDGPU::V_AND_OR_B32_vi:
    case AMDGPU::V_BFE_I32_e64_gfx11:
    case AMDGPU::V_BFE_I32_e64_gfx12:
    case AMDGPU::V_BFE_I32_gfx10:
    case AMDGPU::V_BFE_I32_gfx6_gfx7:
    case AMDGPU::V_BFE_I32_vi:
    case AMDGPU::V_BFE_U32_e64_gfx11:
    case AMDGPU::V_BFE_U32_e64_gfx12:
    case AMDGPU::V_BFE_U32_gfx10:
    case AMDGPU::V_BFE_U32_gfx6_gfx7:
    case AMDGPU::V_BFE_U32_vi:
    case AMDGPU::V_BFI_B32_e64_gfx11:
    case AMDGPU::V_BFI_B32_e64_gfx12:
    case AMDGPU::V_BFI_B32_gfx10:
    case AMDGPU::V_BFI_B32_gfx6_gfx7:
    case AMDGPU::V_BFI_B32_vi:
    case AMDGPU::V_CVT_SCALEF32_2XPK16_BF6_F32_gfx9:
    case AMDGPU::V_CVT_SCALEF32_2XPK16_FP6_F32_gfx9:
    case AMDGPU::V_CVT_SCALEF32_SR_PK16_BF6_BF16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK16_BF6_F16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK16_BF6_F32_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK16_FP6_BF16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK16_FP6_F16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK16_FP6_F32_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK32_BF6_BF16_gfx9:
    case AMDGPU::V_CVT_SCALEF32_SR_PK32_BF6_F16_gfx9:
    case AMDGPU::V_CVT_SCALEF32_SR_PK32_BF6_F32_gfx9:
    case AMDGPU::V_CVT_SCALEF32_SR_PK32_FP6_BF16_gfx9:
    case AMDGPU::V_CVT_SCALEF32_SR_PK32_FP6_F16_gfx9:
    case AMDGPU::V_CVT_SCALEF32_SR_PK32_FP6_F32_gfx9:
    case AMDGPU::V_CVT_SCALEF32_SR_PK8_BF8_BF16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK8_BF8_F16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK8_BF8_F32_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK8_FP4_BF16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK8_FP4_F16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK8_FP4_F32_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK8_FP8_BF16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK8_FP8_F16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK8_FP8_F32_e64_gfx1250:
    case AMDGPU::V_LERP_U8_e64_gfx11:
    case AMDGPU::V_LERP_U8_e64_gfx12:
    case AMDGPU::V_LERP_U8_gfx10:
    case AMDGPU::V_LERP_U8_gfx6_gfx7:
    case AMDGPU::V_LERP_U8_vi:
    case AMDGPU::V_LSHL_ADD_U32_e64_gfx11:
    case AMDGPU::V_LSHL_ADD_U32_e64_gfx12:
    case AMDGPU::V_LSHL_ADD_U32_gfx10:
    case AMDGPU::V_LSHL_ADD_U32_vi:
    case AMDGPU::V_LSHL_ADD_U64_e64_gfx1250:
    case AMDGPU::V_LSHL_ADD_U64_vi:
    case AMDGPU::V_LSHL_OR_B32_e64_gfx11:
    case AMDGPU::V_LSHL_OR_B32_e64_gfx12:
    case AMDGPU::V_LSHL_OR_B32_gfx10:
    case AMDGPU::V_LSHL_OR_B32_vi:
    case AMDGPU::V_MAD_U32_e64_gfx1250:
    case AMDGPU::V_MAX3_I32_e64_gfx11:
    case AMDGPU::V_MAX3_I32_e64_gfx12:
    case AMDGPU::V_MAX3_I32_gfx10:
    case AMDGPU::V_MAX3_I32_gfx6_gfx7:
    case AMDGPU::V_MAX3_I32_vi:
    case AMDGPU::V_MAX3_U32_e64_gfx11:
    case AMDGPU::V_MAX3_U32_e64_gfx12:
    case AMDGPU::V_MAX3_U32_gfx10:
    case AMDGPU::V_MAX3_U32_gfx6_gfx7:
    case AMDGPU::V_MAX3_U32_vi:
    case AMDGPU::V_MAXMIN_I32_e64_gfx11:
    case AMDGPU::V_MAXMIN_I32_e64_gfx12:
    case AMDGPU::V_MAXMIN_U32_e64_gfx11:
    case AMDGPU::V_MAXMIN_U32_e64_gfx12:
    case AMDGPU::V_MED3_I32_e64_gfx11:
    case AMDGPU::V_MED3_I32_e64_gfx12:
    case AMDGPU::V_MED3_I32_gfx10:
    case AMDGPU::V_MED3_I32_gfx6_gfx7:
    case AMDGPU::V_MED3_I32_vi:
    case AMDGPU::V_MED3_U32_e64_gfx11:
    case AMDGPU::V_MED3_U32_e64_gfx12:
    case AMDGPU::V_MED3_U32_gfx10:
    case AMDGPU::V_MED3_U32_gfx6_gfx7:
    case AMDGPU::V_MED3_U32_vi:
    case AMDGPU::V_MIN3_I32_e64_gfx11:
    case AMDGPU::V_MIN3_I32_e64_gfx12:
    case AMDGPU::V_MIN3_I32_gfx10:
    case AMDGPU::V_MIN3_I32_gfx6_gfx7:
    case AMDGPU::V_MIN3_I32_vi:
    case AMDGPU::V_MIN3_U32_e64_gfx11:
    case AMDGPU::V_MIN3_U32_e64_gfx12:
    case AMDGPU::V_MIN3_U32_gfx10:
    case AMDGPU::V_MIN3_U32_gfx6_gfx7:
    case AMDGPU::V_MIN3_U32_vi:
    case AMDGPU::V_MINMAX_I32_e64_gfx11:
    case AMDGPU::V_MINMAX_I32_e64_gfx12:
    case AMDGPU::V_MINMAX_U32_e64_gfx11:
    case AMDGPU::V_MINMAX_U32_e64_gfx12:
    case AMDGPU::V_OR3_B32_e64_gfx11:
    case AMDGPU::V_OR3_B32_e64_gfx12:
    case AMDGPU::V_OR3_B32_gfx10:
    case AMDGPU::V_OR3_B32_vi:
    case AMDGPU::V_PERMLANE_BCAST_B32_e64_gfx12:
    case AMDGPU::V_PERMLANE_DOWN_B32_e64_gfx12:
    case AMDGPU::V_PERMLANE_UP_B32_e64_gfx12:
    case AMDGPU::V_PERMLANE_XOR_B32_e64_gfx12:
    case AMDGPU::V_PERM_B32_e64_gfx11:
    case AMDGPU::V_PERM_B32_e64_gfx12:
    case AMDGPU::V_PERM_B32_gfx10:
    case AMDGPU::V_PERM_B32_vi:
    case AMDGPU::V_PERM_PK16_B4_U4_e64_gfx1250:
    case AMDGPU::V_PERM_PK16_B6_U4_e64_gfx1250:
    case AMDGPU::V_PERM_PK16_B8_U4_e64_gfx1250:
    case AMDGPU::V_XAD_U32_e64_gfx11:
    case AMDGPU::V_XAD_U32_e64_gfx12:
    case AMDGPU::V_XAD_U32_gfx10:
    case AMDGPU::V_XAD_U32_vi:
    case AMDGPU::V_XOR3_B32_e64_gfx11:
    case AMDGPU::V_XOR3_B32_e64_gfx12:
    case AMDGPU::V_XOR3_B32_gfx10: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_BITOP3_B32_e64_gfx1250:
    case AMDGPU::V_BITOP3_B32_gfx9: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: bitop3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 61, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 6), 59, 2);
      Value.insertBits(op.extractBitsAsZExtValue(3, 3), 8, 3);
      break;
    }
    case AMDGPU::V_AND_B16_fake16_e64_gfx11:
    case AMDGPU::V_AND_B16_fake16_e64_gfx12:
    case AMDGPU::V_AND_B32_e64_gfx10:
    case AMDGPU::V_AND_B32_e64_gfx11:
    case AMDGPU::V_AND_B32_e64_gfx12:
    case AMDGPU::V_AND_B32_e64_gfx6_gfx7:
    case AMDGPU::V_AND_B32_e64_vi:
    case AMDGPU::V_ASHRREV_I16_e64_vi:
    case AMDGPU::V_ASHRREV_I16_fake16_e64_gfx11:
    case AMDGPU::V_ASHRREV_I16_fake16_e64_gfx12:
    case AMDGPU::V_ASHRREV_I32_e64_gfx10:
    case AMDGPU::V_ASHRREV_I32_e64_gfx11:
    case AMDGPU::V_ASHRREV_I32_e64_gfx12:
    case AMDGPU::V_ASHRREV_I32_e64_gfx6_gfx7:
    case AMDGPU::V_ASHRREV_I32_e64_vi:
    case AMDGPU::V_ASHRREV_I64_e64_gfx11:
    case AMDGPU::V_ASHRREV_I64_e64_gfx12:
    case AMDGPU::V_ASHRREV_I64_e64_gfx1250:
    case AMDGPU::V_ASHRREV_I64_gfx10:
    case AMDGPU::V_ASHRREV_I64_vi:
    case AMDGPU::V_ASHR_I32_e64_gfx6_gfx7:
    case AMDGPU::V_ASHR_I64_gfx6_gfx7:
    case AMDGPU::V_BCNT_U32_B32_e64_gfx10:
    case AMDGPU::V_BCNT_U32_B32_e64_gfx11:
    case AMDGPU::V_BCNT_U32_B32_e64_gfx12:
    case AMDGPU::V_BCNT_U32_B32_e64_gfx6_gfx7:
    case AMDGPU::V_BCNT_U32_B32_e64_vi:
    case AMDGPU::V_BFM_B32_e64_gfx10:
    case AMDGPU::V_BFM_B32_e64_gfx11:
    case AMDGPU::V_BFM_B32_e64_gfx12:
    case AMDGPU::V_BFM_B32_e64_gfx6_gfx7:
    case AMDGPU::V_BFM_B32_e64_vi:
    case AMDGPU::V_CVT_PK_I16_I32_e64_gfx10:
    case AMDGPU::V_CVT_PK_I16_I32_e64_gfx11:
    case AMDGPU::V_CVT_PK_I16_I32_e64_gfx12:
    case AMDGPU::V_CVT_PK_I16_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_PK_I16_I32_e64_vi:
    case AMDGPU::V_CVT_PK_U16_U32_e64_gfx10:
    case AMDGPU::V_CVT_PK_U16_U32_e64_gfx11:
    case AMDGPU::V_CVT_PK_U16_U32_e64_gfx12:
    case AMDGPU::V_CVT_PK_U16_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_PK_U16_U32_e64_vi:
    case AMDGPU::V_CVT_SCALEF32_PK16_BF6_BF16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK16_BF6_F16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK16_BF6_F32_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK16_FP6_BF16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK16_FP6_F16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK16_FP6_F32_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK32_BF16_BF6_gfx9:
    case AMDGPU::V_CVT_SCALEF32_PK32_BF16_FP6_gfx9:
    case AMDGPU::V_CVT_SCALEF32_PK32_BF6_BF16_gfx9:
    case AMDGPU::V_CVT_SCALEF32_PK32_BF6_F16_gfx9:
    case AMDGPU::V_CVT_SCALEF32_PK32_F16_BF6_gfx9:
    case AMDGPU::V_CVT_SCALEF32_PK32_F16_FP6_gfx9:
    case AMDGPU::V_CVT_SCALEF32_PK32_F32_BF6_gfx9:
    case AMDGPU::V_CVT_SCALEF32_PK32_F32_FP6_gfx9:
    case AMDGPU::V_CVT_SCALEF32_PK32_FP6_BF16_gfx9:
    case AMDGPU::V_CVT_SCALEF32_PK32_FP6_F16_gfx9:
    case AMDGPU::V_CVT_SCALEF32_PK8_BF8_BF16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK8_BF8_F16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK8_BF8_F32_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK8_FP4_BF16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK8_FP4_F16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK8_FP4_F32_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK8_FP8_BF16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK8_FP8_F16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK8_FP8_F32_e64_gfx1250:
    case AMDGPU::V_LSHLREV_B16_e64_vi:
    case AMDGPU::V_LSHLREV_B16_fake16_e64_gfx11:
    case AMDGPU::V_LSHLREV_B16_fake16_e64_gfx12:
    case AMDGPU::V_LSHLREV_B32_e64_gfx10:
    case AMDGPU::V_LSHLREV_B32_e64_gfx11:
    case AMDGPU::V_LSHLREV_B32_e64_gfx12:
    case AMDGPU::V_LSHLREV_B32_e64_gfx6_gfx7:
    case AMDGPU::V_LSHLREV_B32_e64_vi:
    case AMDGPU::V_LSHLREV_B64_e64_gfx11:
    case AMDGPU::V_LSHLREV_B64_e64_gfx12:
    case AMDGPU::V_LSHLREV_B64_gfx10:
    case AMDGPU::V_LSHLREV_B64_vi:
    case AMDGPU::V_LSHL_B32_e64_gfx6_gfx7:
    case AMDGPU::V_LSHL_B64_gfx6_gfx7:
    case AMDGPU::V_LSHRREV_B16_e64_vi:
    case AMDGPU::V_LSHRREV_B16_fake16_e64_gfx11:
    case AMDGPU::V_LSHRREV_B16_fake16_e64_gfx12:
    case AMDGPU::V_LSHRREV_B32_e64_gfx10:
    case AMDGPU::V_LSHRREV_B32_e64_gfx11:
    case AMDGPU::V_LSHRREV_B32_e64_gfx12:
    case AMDGPU::V_LSHRREV_B32_e64_gfx6_gfx7:
    case AMDGPU::V_LSHRREV_B32_e64_vi:
    case AMDGPU::V_LSHRREV_B64_e64_gfx11:
    case AMDGPU::V_LSHRREV_B64_e64_gfx12:
    case AMDGPU::V_LSHRREV_B64_e64_gfx1250:
    case AMDGPU::V_LSHRREV_B64_gfx10:
    case AMDGPU::V_LSHRREV_B64_vi:
    case AMDGPU::V_LSHR_B32_e64_gfx6_gfx7:
    case AMDGPU::V_LSHR_B64_gfx6_gfx7:
    case AMDGPU::V_MAX_I16_e64_vi:
    case AMDGPU::V_MAX_I16_fake16_e64_gfx11:
    case AMDGPU::V_MAX_I16_fake16_e64_gfx12:
    case AMDGPU::V_MAX_I32_e64_gfx10:
    case AMDGPU::V_MAX_I32_e64_gfx11:
    case AMDGPU::V_MAX_I32_e64_gfx12:
    case AMDGPU::V_MAX_I32_e64_gfx6_gfx7:
    case AMDGPU::V_MAX_I32_e64_vi:
    case AMDGPU::V_MAX_I64_e64_gfx1250:
    case AMDGPU::V_MAX_U16_e64_vi:
    case AMDGPU::V_MAX_U16_fake16_e64_gfx11:
    case AMDGPU::V_MAX_U16_fake16_e64_gfx12:
    case AMDGPU::V_MAX_U32_e64_gfx10:
    case AMDGPU::V_MAX_U32_e64_gfx11:
    case AMDGPU::V_MAX_U32_e64_gfx12:
    case AMDGPU::V_MAX_U32_e64_gfx6_gfx7:
    case AMDGPU::V_MAX_U32_e64_vi:
    case AMDGPU::V_MAX_U64_e64_gfx1250:
    case AMDGPU::V_MBCNT_HI_U32_B32_e64_gfx10:
    case AMDGPU::V_MBCNT_HI_U32_B32_e64_gfx11:
    case AMDGPU::V_MBCNT_HI_U32_B32_e64_gfx12:
    case AMDGPU::V_MBCNT_HI_U32_B32_e64_gfx6_gfx7:
    case AMDGPU::V_MBCNT_HI_U32_B32_e64_vi:
    case AMDGPU::V_MBCNT_LO_U32_B32_e64_gfx10:
    case AMDGPU::V_MBCNT_LO_U32_B32_e64_gfx11:
    case AMDGPU::V_MBCNT_LO_U32_B32_e64_gfx12:
    case AMDGPU::V_MBCNT_LO_U32_B32_e64_gfx6_gfx7:
    case AMDGPU::V_MBCNT_LO_U32_B32_e64_vi:
    case AMDGPU::V_MIN_I16_e64_vi:
    case AMDGPU::V_MIN_I16_fake16_e64_gfx11:
    case AMDGPU::V_MIN_I16_fake16_e64_gfx12:
    case AMDGPU::V_MIN_I32_e64_gfx10:
    case AMDGPU::V_MIN_I32_e64_gfx11:
    case AMDGPU::V_MIN_I32_e64_gfx12:
    case AMDGPU::V_MIN_I32_e64_gfx6_gfx7:
    case AMDGPU::V_MIN_I32_e64_vi:
    case AMDGPU::V_MIN_I64_e64_gfx1250:
    case AMDGPU::V_MIN_U16_e64_vi:
    case AMDGPU::V_MIN_U16_fake16_e64_gfx11:
    case AMDGPU::V_MIN_U16_fake16_e64_gfx12:
    case AMDGPU::V_MIN_U32_e64_gfx10:
    case AMDGPU::V_MIN_U32_e64_gfx11:
    case AMDGPU::V_MIN_U32_e64_gfx12:
    case AMDGPU::V_MIN_U32_e64_gfx6_gfx7:
    case AMDGPU::V_MIN_U32_e64_vi:
    case AMDGPU::V_MIN_U64_e64_gfx1250:
    case AMDGPU::V_MUL_HI_I32_I24_e64_gfx10:
    case AMDGPU::V_MUL_HI_I32_I24_e64_gfx11:
    case AMDGPU::V_MUL_HI_I32_I24_e64_gfx12:
    case AMDGPU::V_MUL_HI_I32_I24_e64_gfx6_gfx7:
    case AMDGPU::V_MUL_HI_I32_I24_e64_vi:
    case AMDGPU::V_MUL_HI_I32_e64_gfx11:
    case AMDGPU::V_MUL_HI_I32_e64_gfx12:
    case AMDGPU::V_MUL_HI_I32_e64_gfx1250:
    case AMDGPU::V_MUL_HI_I32_gfx10:
    case AMDGPU::V_MUL_HI_I32_gfx6_gfx7:
    case AMDGPU::V_MUL_HI_I32_vi:
    case AMDGPU::V_MUL_HI_U32_U24_e64_gfx10:
    case AMDGPU::V_MUL_HI_U32_U24_e64_gfx11:
    case AMDGPU::V_MUL_HI_U32_U24_e64_gfx12:
    case AMDGPU::V_MUL_HI_U32_U24_e64_gfx6_gfx7:
    case AMDGPU::V_MUL_HI_U32_U24_e64_vi:
    case AMDGPU::V_MUL_HI_U32_e64_gfx11:
    case AMDGPU::V_MUL_HI_U32_e64_gfx12:
    case AMDGPU::V_MUL_HI_U32_e64_gfx1250:
    case AMDGPU::V_MUL_HI_U32_gfx10:
    case AMDGPU::V_MUL_HI_U32_gfx6_gfx7:
    case AMDGPU::V_MUL_HI_U32_vi:
    case AMDGPU::V_MUL_LO_I32_gfx10:
    case AMDGPU::V_MUL_LO_I32_gfx6_gfx7:
    case AMDGPU::V_MUL_LO_I32_vi:
    case AMDGPU::V_MUL_LO_U16_e64_vi:
    case AMDGPU::V_MUL_LO_U16_fake16_e64_gfx11:
    case AMDGPU::V_MUL_LO_U16_fake16_e64_gfx12:
    case AMDGPU::V_MUL_LO_U32_e64_gfx11:
    case AMDGPU::V_MUL_LO_U32_e64_gfx12:
    case AMDGPU::V_MUL_LO_U32_e64_gfx1250:
    case AMDGPU::V_MUL_LO_U32_gfx10:
    case AMDGPU::V_MUL_LO_U32_gfx6_gfx7:
    case AMDGPU::V_MUL_LO_U32_vi:
    case AMDGPU::V_MUL_U64_e64_gfx1250:
    case AMDGPU::V_OR_B16_fake16_e64_gfx11:
    case AMDGPU::V_OR_B16_fake16_e64_gfx12:
    case AMDGPU::V_OR_B32_e64_gfx10:
    case AMDGPU::V_OR_B32_e64_gfx11:
    case AMDGPU::V_OR_B32_e64_gfx12:
    case AMDGPU::V_OR_B32_e64_gfx6_gfx7:
    case AMDGPU::V_OR_B32_e64_vi:
    case AMDGPU::V_PERMLANE_IDX_GEN_B32_e64_gfx12:
    case AMDGPU::V_READLANE_B32_e64_gfx11:
    case AMDGPU::V_READLANE_B32_e64_gfx12:
    case AMDGPU::V_READLANE_B32_gfx10:
    case AMDGPU::V_READLANE_B32_vi:
    case AMDGPU::V_WRITELANE_B32_e64_gfx11:
    case AMDGPU::V_WRITELANE_B32_e64_gfx12:
    case AMDGPU::V_WRITELANE_B32_gfx10:
    case AMDGPU::V_WRITELANE_B32_vi:
    case AMDGPU::V_XNOR_B32_e64_gfx10:
    case AMDGPU::V_XNOR_B32_e64_gfx11:
    case AMDGPU::V_XNOR_B32_e64_gfx12:
    case AMDGPU::V_XNOR_B32_e64_vi:
    case AMDGPU::V_XOR_B16_fake16_e64_gfx11:
    case AMDGPU::V_XOR_B16_fake16_e64_gfx12:
    case AMDGPU::V_XOR_B32_e64_gfx10:
    case AMDGPU::V_XOR_B32_e64_gfx11:
    case AMDGPU::V_XOR_B32_e64_gfx12:
    case AMDGPU::V_XOR_B32_e64_gfx6_gfx7:
    case AMDGPU::V_XOR_B32_e64_vi: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_SCALE_PK16_BF16_BF6_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK16_BF16_FP6_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK16_F16_BF6_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK16_F16_FP6_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK16_F32_BF6_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK16_F32_FP6_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK8_BF16_BF8_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK8_BF16_FP4_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK8_BF16_FP8_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK8_F16_BF8_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK8_F16_FP4_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK8_F16_FP8_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK8_F32_BF8_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK8_F32_FP4_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK8_F32_FP8_e64_gfx1250: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: scale_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 11, 4);
      break;
    }
    case AMDGPU::V_BFREV_B32_e64_gfx10:
    case AMDGPU::V_BFREV_B32_e64_gfx11:
    case AMDGPU::V_BFREV_B32_e64_gfx12:
    case AMDGPU::V_BFREV_B32_e64_gfx6_gfx7:
    case AMDGPU::V_BFREV_B32_e64_vi:
    case AMDGPU::V_CLS_I32_e64_gfx11:
    case AMDGPU::V_CLS_I32_e64_gfx12:
    case AMDGPU::V_CLZ_I32_U32_e64_gfx11:
    case AMDGPU::V_CLZ_I32_U32_e64_gfx12:
    case AMDGPU::V_CTZ_I32_B32_e64_gfx11:
    case AMDGPU::V_CTZ_I32_B32_e64_gfx12:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_e64_gfx12:
    case AMDGPU::V_FFBH_I32_e64_gfx10:
    case AMDGPU::V_FFBH_I32_e64_gfx6_gfx7:
    case AMDGPU::V_FFBH_I32_e64_vi:
    case AMDGPU::V_FFBH_U32_e64_gfx10:
    case AMDGPU::V_FFBH_U32_e64_gfx6_gfx7:
    case AMDGPU::V_FFBH_U32_e64_vi:
    case AMDGPU::V_FFBL_B32_e64_gfx10:
    case AMDGPU::V_FFBL_B32_e64_gfx6_gfx7:
    case AMDGPU::V_FFBL_B32_e64_vi:
    case AMDGPU::V_MOVRELD_B32_e64_gfx10:
    case AMDGPU::V_MOVRELD_B32_e64_gfx11:
    case AMDGPU::V_MOVRELD_B32_e64_gfx12:
    case AMDGPU::V_MOVRELD_B32_e64_gfx6_gfx7:
    case AMDGPU::V_MOVRELD_B32_e64_vi:
    case AMDGPU::V_MOVRELSD_2_B32_e64_gfx10:
    case AMDGPU::V_MOVRELSD_2_B32_e64_gfx11:
    case AMDGPU::V_MOVRELSD_2_B32_e64_gfx12:
    case AMDGPU::V_MOVRELSD_B32_e64_gfx10:
    case AMDGPU::V_MOVRELSD_B32_e64_gfx11:
    case AMDGPU::V_MOVRELSD_B32_e64_gfx12:
    case AMDGPU::V_MOVRELSD_B32_e64_gfx6_gfx7:
    case AMDGPU::V_MOVRELSD_B32_e64_vi:
    case AMDGPU::V_MOVRELS_B32_e64_gfx10:
    case AMDGPU::V_MOVRELS_B32_e64_gfx11:
    case AMDGPU::V_MOVRELS_B32_e64_gfx12:
    case AMDGPU::V_MOVRELS_B32_e64_gfx6_gfx7:
    case AMDGPU::V_MOVRELS_B32_e64_vi:
    case AMDGPU::V_MOV_B32_e64_gfx10:
    case AMDGPU::V_MOV_B32_e64_gfx11:
    case AMDGPU::V_MOV_B32_e64_gfx12:
    case AMDGPU::V_MOV_B32_e64_gfx6_gfx7:
    case AMDGPU::V_MOV_B32_e64_vi:
    case AMDGPU::V_MOV_B64_e64_gfx1250:
    case AMDGPU::V_MOV_B64_e64_vi:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_e64_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_e64_gfx12:
    case AMDGPU::V_NOT_B32_e64_gfx10:
    case AMDGPU::V_NOT_B32_e64_gfx11:
    case AMDGPU::V_NOT_B32_e64_gfx12:
    case AMDGPU::V_NOT_B32_e64_gfx6_gfx7:
    case AMDGPU::V_NOT_B32_e64_vi:
    case AMDGPU::V_PRNG_B32_e64_gfx1250:
    case AMDGPU::V_PRNG_B32_e64_vi:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_fake16_e64_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_fake16_e64_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e64_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e64_gfx12:
    case AMDGPU::V_SAT_PK_U8_I16_e64_gfx10:
    case AMDGPU::V_SAT_PK_U8_I16_e64_vi:
    case AMDGPU::V_SCREEN_PARTITION_4SE_B32_e64_vi: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_F32_BF8_e64_gfx12:
    case AMDGPU::V_CVT_F32_FP8_e64_gfx11:
    case AMDGPU::V_CVT_F32_FP8_e64_gfx12: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 11, 1);
      break;
    }
    case AMDGPU::V_INTERP_MOV_F32_e64_gfx10: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: attr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 0), 32, 6);
      // op: attrchan
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 38, 2);
      break;
    }
    case AMDGPU::V_INTERP_MOV_F32_e64_vi: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: attrchan
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 38, 2);
      // op: attr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 0), 32, 6);
      break;
    }
    case AMDGPU::V_BFREV_B32_dpp8_gfx10:
    case AMDGPU::V_BFREV_B32_dpp8_gfx11:
    case AMDGPU::V_BFREV_B32_dpp8_gfx12:
    case AMDGPU::V_CLS_I32_dpp8_gfx11:
    case AMDGPU::V_CLS_I32_dpp8_gfx12:
    case AMDGPU::V_CLZ_I32_U32_dpp8_gfx11:
    case AMDGPU::V_CLZ_I32_U32_dpp8_gfx12:
    case AMDGPU::V_CTZ_I32_B32_dpp8_gfx11:
    case AMDGPU::V_CTZ_I32_B32_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_I16_dpp8_gfx10:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_U16_dpp8_gfx10:
    case AMDGPU::V_CVT_F32_BF8_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_FP8_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_FP8_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_FP8_dpp8_gfx1250:
    case AMDGPU::V_CVT_F32_I32_dpp8_gfx10:
    case AMDGPU::V_CVT_F32_I32_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_I32_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_U32_dpp8_gfx10:
    case AMDGPU::V_CVT_F32_U32_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_U32_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE0_dpp8_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE0_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE0_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE1_dpp8_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE1_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE1_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE2_dpp8_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE2_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE2_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE3_dpp8_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE3_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE3_dpp8_gfx12:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_dpp8_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_dpp8_gfx12:
    case AMDGPU::V_CVT_OFF_F32_I4_dpp8_gfx10:
    case AMDGPU::V_CVT_OFF_F32_I4_dpp8_gfx11:
    case AMDGPU::V_CVT_OFF_F32_I4_dpp8_gfx12:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_dpp8_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_dpp8_gfx12:
    case AMDGPU::V_FFBH_I32_dpp8_gfx10:
    case AMDGPU::V_FFBH_U32_dpp8_gfx10:
    case AMDGPU::V_FFBL_B32_dpp8_gfx10:
    case AMDGPU::V_MOVRELD_B32_dpp8_gfx10:
    case AMDGPU::V_MOVRELD_B32_dpp8_gfx11:
    case AMDGPU::V_MOVRELD_B32_dpp8_gfx12:
    case AMDGPU::V_MOVRELSD_2_B32_dpp8_gfx10:
    case AMDGPU::V_MOVRELSD_2_B32_dpp8_gfx11:
    case AMDGPU::V_MOVRELSD_2_B32_dpp8_gfx12:
    case AMDGPU::V_MOVRELSD_B32_dpp8_gfx10:
    case AMDGPU::V_MOVRELSD_B32_dpp8_gfx11:
    case AMDGPU::V_MOVRELSD_B32_dpp8_gfx12:
    case AMDGPU::V_MOVRELS_B32_dpp8_gfx10:
    case AMDGPU::V_MOVRELS_B32_dpp8_gfx11:
    case AMDGPU::V_MOVRELS_B32_dpp8_gfx12:
    case AMDGPU::V_MOV_B32_dpp8_gfx10:
    case AMDGPU::V_MOV_B32_dpp8_gfx11:
    case AMDGPU::V_MOV_B32_dpp8_gfx12:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_dpp8_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_dpp8_gfx12:
    case AMDGPU::V_NOT_B32_dpp8_gfx10:
    case AMDGPU::V_NOT_B32_dpp8_gfx11:
    case AMDGPU::V_NOT_B32_dpp8_gfx12:
    case AMDGPU::V_PRNG_B32_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_fake16_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_fake16_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_dpp8_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_dpp8_gfx12:
    case AMDGPU::V_SAT_PK_U8_I16_dpp8_gfx10: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 40, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
    case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
    case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx12:
    case AMDGPU::V_ADD_CO_CI_U32_dpp8_w32_gfx10:
    case AMDGPU::V_ADD_CO_CI_U32_dpp8_w32_gfx11:
    case AMDGPU::V_ADD_CO_CI_U32_dpp8_w32_gfx12:
    case AMDGPU::V_ADD_CO_CI_U32_dpp8_w64_gfx10:
    case AMDGPU::V_ADD_CO_CI_U32_dpp8_w64_gfx11:
    case AMDGPU::V_ADD_CO_CI_U32_dpp8_w64_gfx12:
    case AMDGPU::V_ADD_NC_U32_dpp8_gfx10:
    case AMDGPU::V_ADD_NC_U32_dpp8_gfx11:
    case AMDGPU::V_ADD_NC_U32_dpp8_gfx12:
    case AMDGPU::V_AND_B32_dpp8_gfx10:
    case AMDGPU::V_AND_B32_dpp8_gfx11:
    case AMDGPU::V_AND_B32_dpp8_gfx12:
    case AMDGPU::V_ASHRREV_I32_dpp8_gfx10:
    case AMDGPU::V_ASHRREV_I32_dpp8_gfx11:
    case AMDGPU::V_ASHRREV_I32_dpp8_gfx12:
    case AMDGPU::V_LSHLREV_B32_dpp8_gfx10:
    case AMDGPU::V_LSHLREV_B32_dpp8_gfx11:
    case AMDGPU::V_LSHLREV_B32_dpp8_gfx12:
    case AMDGPU::V_LSHRREV_B32_dpp8_gfx10:
    case AMDGPU::V_LSHRREV_B32_dpp8_gfx11:
    case AMDGPU::V_LSHRREV_B32_dpp8_gfx12:
    case AMDGPU::V_MAX_I32_dpp8_gfx10:
    case AMDGPU::V_MAX_I32_dpp8_gfx11:
    case AMDGPU::V_MAX_I32_dpp8_gfx12:
    case AMDGPU::V_MAX_U32_dpp8_gfx10:
    case AMDGPU::V_MAX_U32_dpp8_gfx11:
    case AMDGPU::V_MAX_U32_dpp8_gfx12:
    case AMDGPU::V_MIN_I32_dpp8_gfx10:
    case AMDGPU::V_MIN_I32_dpp8_gfx11:
    case AMDGPU::V_MIN_I32_dpp8_gfx12:
    case AMDGPU::V_MIN_U32_dpp8_gfx10:
    case AMDGPU::V_MIN_U32_dpp8_gfx11:
    case AMDGPU::V_MIN_U32_dpp8_gfx12:
    case AMDGPU::V_MUL_HI_I32_I24_dpp8_gfx10:
    case AMDGPU::V_MUL_HI_I32_I24_dpp8_gfx11:
    case AMDGPU::V_MUL_HI_I32_I24_dpp8_gfx12:
    case AMDGPU::V_MUL_HI_U32_U24_dpp8_gfx10:
    case AMDGPU::V_MUL_HI_U32_U24_dpp8_gfx11:
    case AMDGPU::V_MUL_HI_U32_U24_dpp8_gfx12:
    case AMDGPU::V_MUL_I32_I24_dpp8_gfx10:
    case AMDGPU::V_MUL_I32_I24_dpp8_gfx11:
    case AMDGPU::V_MUL_I32_I24_dpp8_gfx12:
    case AMDGPU::V_MUL_U32_U24_dpp8_gfx10:
    case AMDGPU::V_MUL_U32_U24_dpp8_gfx11:
    case AMDGPU::V_MUL_U32_U24_dpp8_gfx12:
    case AMDGPU::V_OR_B32_dpp8_gfx10:
    case AMDGPU::V_OR_B32_dpp8_gfx11:
    case AMDGPU::V_OR_B32_dpp8_gfx12:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx12:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_w32_gfx10:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_w32_gfx11:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_w32_gfx12:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_w64_gfx10:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_w64_gfx11:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_w64_gfx12:
    case AMDGPU::V_SUBREV_NC_U32_dpp8_gfx10:
    case AMDGPU::V_SUBREV_NC_U32_dpp8_gfx11:
    case AMDGPU::V_SUBREV_NC_U32_dpp8_gfx12:
    case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
    case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
    case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx12:
    case AMDGPU::V_SUB_CO_CI_U32_dpp8_w32_gfx10:
    case AMDGPU::V_SUB_CO_CI_U32_dpp8_w32_gfx11:
    case AMDGPU::V_SUB_CO_CI_U32_dpp8_w32_gfx12:
    case AMDGPU::V_SUB_CO_CI_U32_dpp8_w64_gfx10:
    case AMDGPU::V_SUB_CO_CI_U32_dpp8_w64_gfx11:
    case AMDGPU::V_SUB_CO_CI_U32_dpp8_w64_gfx12:
    case AMDGPU::V_SUB_NC_U32_dpp8_gfx10:
    case AMDGPU::V_SUB_NC_U32_dpp8_gfx11:
    case AMDGPU::V_SUB_NC_U32_dpp8_gfx12:
    case AMDGPU::V_XNOR_B32_dpp8_gfx10:
    case AMDGPU::V_XNOR_B32_dpp8_gfx11:
    case AMDGPU::V_XNOR_B32_dpp8_gfx12:
    case AMDGPU::V_XOR_B32_dpp8_gfx10:
    case AMDGPU::V_XOR_B32_dpp8_gfx11:
    case AMDGPU::V_XOR_B32_dpp8_gfx12: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 40, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_DOT2ACC_F32_F16_dpp8_gfx11:
    case AMDGPU::V_DOT2C_F32_F16_dpp8_gfx10:
    case AMDGPU::V_DOT4C_I32_I8_dpp8_gfx10:
    case AMDGPU::V_DOT8C_I32_I4_dpp8_gfx10:
    case AMDGPU::V_FMAC_F16_dpp8_gfx10:
    case AMDGPU::V_FMAC_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_FMAC_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_FMAC_F32_dpp8_gfx10:
    case AMDGPU::V_FMAC_F32_dpp8_gfx11:
    case AMDGPU::V_FMAC_F32_dpp8_gfx12:
    case AMDGPU::V_MAC_F32_dpp8_gfx10: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 40, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_BFREV_B32_dpp_gfx10:
    case AMDGPU::V_BFREV_B32_dpp_gfx11:
    case AMDGPU::V_BFREV_B32_dpp_gfx12:
    case AMDGPU::V_CLS_I32_dpp_gfx11:
    case AMDGPU::V_CLS_I32_dpp_gfx12:
    case AMDGPU::V_CLZ_I32_U32_dpp_gfx11:
    case AMDGPU::V_CLZ_I32_U32_dpp_gfx12:
    case AMDGPU::V_CTZ_I32_B32_dpp_gfx11:
    case AMDGPU::V_CTZ_I32_B32_dpp_gfx12:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_dpp_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_dpp_gfx12:
    case AMDGPU::V_CVT_F16_I16_dpp_gfx10:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_dpp_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_dpp_gfx12:
    case AMDGPU::V_CVT_F16_U16_dpp_gfx10:
    case AMDGPU::V_CVT_F32_BF8_dpp_gfx12:
    case AMDGPU::V_CVT_F32_FP8_dpp_gfx11:
    case AMDGPU::V_CVT_F32_FP8_dpp_gfx12:
    case AMDGPU::V_CVT_F32_FP8_dpp_gfx1250:
    case AMDGPU::V_CVT_F32_I32_dpp_gfx10:
    case AMDGPU::V_CVT_F32_I32_dpp_gfx11:
    case AMDGPU::V_CVT_F32_I32_dpp_gfx12:
    case AMDGPU::V_CVT_F32_U32_dpp_gfx10:
    case AMDGPU::V_CVT_F32_U32_dpp_gfx11:
    case AMDGPU::V_CVT_F32_U32_dpp_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE0_dpp_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE0_dpp_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE0_dpp_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE1_dpp_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE1_dpp_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE1_dpp_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE2_dpp_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE2_dpp_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE2_dpp_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE3_dpp_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE3_dpp_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE3_dpp_gfx12:
    case AMDGPU::V_CVT_F64_I32_dpp_gfx12:
    case AMDGPU::V_CVT_F64_U32_dpp_gfx12:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_dpp_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_dpp_gfx12:
    case AMDGPU::V_CVT_OFF_F32_I4_dpp_gfx10:
    case AMDGPU::V_CVT_OFF_F32_I4_dpp_gfx11:
    case AMDGPU::V_CVT_OFF_F32_I4_dpp_gfx12:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_dpp_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_dpp_gfx12:
    case AMDGPU::V_FFBH_I32_dpp_gfx10:
    case AMDGPU::V_FFBH_U32_dpp_gfx10:
    case AMDGPU::V_FFBL_B32_dpp_gfx10:
    case AMDGPU::V_MOVRELD_B32_dpp_gfx10:
    case AMDGPU::V_MOVRELD_B32_dpp_gfx11:
    case AMDGPU::V_MOVRELD_B32_dpp_gfx12:
    case AMDGPU::V_MOVRELSD_2_B32_dpp_gfx10:
    case AMDGPU::V_MOVRELSD_2_B32_dpp_gfx11:
    case AMDGPU::V_MOVRELSD_2_B32_dpp_gfx12:
    case AMDGPU::V_MOVRELSD_B32_dpp_gfx10:
    case AMDGPU::V_MOVRELSD_B32_dpp_gfx11:
    case AMDGPU::V_MOVRELSD_B32_dpp_gfx12:
    case AMDGPU::V_MOVRELS_B32_dpp_gfx10:
    case AMDGPU::V_MOVRELS_B32_dpp_gfx11:
    case AMDGPU::V_MOVRELS_B32_dpp_gfx12:
    case AMDGPU::V_MOV_B32_dpp_gfx10:
    case AMDGPU::V_MOV_B32_dpp_gfx11:
    case AMDGPU::V_MOV_B32_dpp_gfx12:
    case AMDGPU::V_MOV_B64_dpp_gfx1250:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_dpp_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_dpp_gfx12:
    case AMDGPU::V_NOT_B32_dpp_gfx10:
    case AMDGPU::V_NOT_B32_dpp_gfx11:
    case AMDGPU::V_NOT_B32_dpp_gfx12:
    case AMDGPU::V_PRNG_B32_dpp_gfx1250:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_fake16_dpp_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_fake16_dpp_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_dpp_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_dpp_gfx12:
    case AMDGPU::V_SAT_PK_U8_I16_dpp_gfx10: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 50, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_BFREV_B32_dpp_vi:
    case AMDGPU::V_CVT_F16_I16_dpp_vi:
    case AMDGPU::V_CVT_F16_U16_dpp_vi:
    case AMDGPU::V_CVT_F32_BF8_dpp_gfx9:
    case AMDGPU::V_CVT_F32_FP8_dpp_gfx9:
    case AMDGPU::V_CVT_F32_I32_dpp_vi:
    case AMDGPU::V_CVT_F32_U32_dpp_vi:
    case AMDGPU::V_CVT_F32_UBYTE0_dpp_vi:
    case AMDGPU::V_CVT_F32_UBYTE1_dpp_vi:
    case AMDGPU::V_CVT_F32_UBYTE2_dpp_vi:
    case AMDGPU::V_CVT_F32_UBYTE3_dpp_vi:
    case AMDGPU::V_CVT_F64_I32_dpp_vi:
    case AMDGPU::V_CVT_F64_U32_dpp_vi:
    case AMDGPU::V_CVT_OFF_F32_I4_dpp_vi:
    case AMDGPU::V_CVT_PK_F32_BF8_dpp_gfx9:
    case AMDGPU::V_CVT_PK_F32_FP8_dpp_gfx9:
    case AMDGPU::V_FFBH_I32_dpp_vi:
    case AMDGPU::V_FFBH_U32_dpp_vi:
    case AMDGPU::V_FFBL_B32_dpp_vi:
    case AMDGPU::V_MOV_B32_dpp_vi:
    case AMDGPU::V_MOV_B64_dpp_gfx9:
    case AMDGPU::V_NOT_B32_dpp_vi:
    case AMDGPU::V_PRNG_B32_dpp_gfx9:
    case AMDGPU::V_SAT_PK_U8_I16_dpp_vi:
    case AMDGPU::V_SCREEN_PARTITION_4SE_B32_dpp_gfx9: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
    case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
    case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx12:
    case AMDGPU::V_ADD_CO_CI_U32_dpp_w32_gfx10:
    case AMDGPU::V_ADD_CO_CI_U32_dpp_w32_gfx11:
    case AMDGPU::V_ADD_CO_CI_U32_dpp_w32_gfx12:
    case AMDGPU::V_ADD_CO_CI_U32_dpp_w64_gfx10:
    case AMDGPU::V_ADD_CO_CI_U32_dpp_w64_gfx11:
    case AMDGPU::V_ADD_CO_CI_U32_dpp_w64_gfx12:
    case AMDGPU::V_ADD_NC_U32_dpp_gfx10:
    case AMDGPU::V_ADD_NC_U32_dpp_gfx11:
    case AMDGPU::V_ADD_NC_U32_dpp_gfx12:
    case AMDGPU::V_ADD_U64_dpp_gfx1250:
    case AMDGPU::V_AND_B32_dpp_gfx10:
    case AMDGPU::V_AND_B32_dpp_gfx11:
    case AMDGPU::V_AND_B32_dpp_gfx12:
    case AMDGPU::V_ASHRREV_I32_dpp_gfx10:
    case AMDGPU::V_ASHRREV_I32_dpp_gfx11:
    case AMDGPU::V_ASHRREV_I32_dpp_gfx12:
    case AMDGPU::V_LSHLREV_B32_dpp_gfx10:
    case AMDGPU::V_LSHLREV_B32_dpp_gfx11:
    case AMDGPU::V_LSHLREV_B32_dpp_gfx12:
    case AMDGPU::V_LSHLREV_B64_dpp_gfx12:
    case AMDGPU::V_LSHRREV_B32_dpp_gfx10:
    case AMDGPU::V_LSHRREV_B32_dpp_gfx11:
    case AMDGPU::V_LSHRREV_B32_dpp_gfx12:
    case AMDGPU::V_MAX_I32_dpp_gfx10:
    case AMDGPU::V_MAX_I32_dpp_gfx11:
    case AMDGPU::V_MAX_I32_dpp_gfx12:
    case AMDGPU::V_MAX_U32_dpp_gfx10:
    case AMDGPU::V_MAX_U32_dpp_gfx11:
    case AMDGPU::V_MAX_U32_dpp_gfx12:
    case AMDGPU::V_MIN_I32_dpp_gfx10:
    case AMDGPU::V_MIN_I32_dpp_gfx11:
    case AMDGPU::V_MIN_I32_dpp_gfx12:
    case AMDGPU::V_MIN_U32_dpp_gfx10:
    case AMDGPU::V_MIN_U32_dpp_gfx11:
    case AMDGPU::V_MIN_U32_dpp_gfx12:
    case AMDGPU::V_MUL_HI_I32_I24_dpp_gfx10:
    case AMDGPU::V_MUL_HI_I32_I24_dpp_gfx11:
    case AMDGPU::V_MUL_HI_I32_I24_dpp_gfx12:
    case AMDGPU::V_MUL_HI_U32_U24_dpp_gfx10:
    case AMDGPU::V_MUL_HI_U32_U24_dpp_gfx11:
    case AMDGPU::V_MUL_HI_U32_U24_dpp_gfx12:
    case AMDGPU::V_MUL_I32_I24_dpp_gfx10:
    case AMDGPU::V_MUL_I32_I24_dpp_gfx11:
    case AMDGPU::V_MUL_I32_I24_dpp_gfx12:
    case AMDGPU::V_MUL_U32_U24_dpp_gfx10:
    case AMDGPU::V_MUL_U32_U24_dpp_gfx11:
    case AMDGPU::V_MUL_U32_U24_dpp_gfx12:
    case AMDGPU::V_OR_B32_dpp_gfx10:
    case AMDGPU::V_OR_B32_dpp_gfx11:
    case AMDGPU::V_OR_B32_dpp_gfx12:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx12:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp_w32_gfx10:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp_w32_gfx11:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp_w32_gfx12:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp_w64_gfx10:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp_w64_gfx11:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp_w64_gfx12:
    case AMDGPU::V_SUBREV_NC_U32_dpp_gfx10:
    case AMDGPU::V_SUBREV_NC_U32_dpp_gfx11:
    case AMDGPU::V_SUBREV_NC_U32_dpp_gfx12:
    case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
    case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
    case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx12:
    case AMDGPU::V_SUB_CO_CI_U32_dpp_w32_gfx10:
    case AMDGPU::V_SUB_CO_CI_U32_dpp_w32_gfx11:
    case AMDGPU::V_SUB_CO_CI_U32_dpp_w32_gfx12:
    case AMDGPU::V_SUB_CO_CI_U32_dpp_w64_gfx10:
    case AMDGPU::V_SUB_CO_CI_U32_dpp_w64_gfx11:
    case AMDGPU::V_SUB_CO_CI_U32_dpp_w64_gfx12:
    case AMDGPU::V_SUB_NC_U32_dpp_gfx10:
    case AMDGPU::V_SUB_NC_U32_dpp_gfx11:
    case AMDGPU::V_SUB_NC_U32_dpp_gfx12:
    case AMDGPU::V_SUB_U64_dpp_gfx1250:
    case AMDGPU::V_XNOR_B32_dpp_gfx10:
    case AMDGPU::V_XNOR_B32_dpp_gfx11:
    case AMDGPU::V_XNOR_B32_dpp_gfx12:
    case AMDGPU::V_XOR_B32_dpp_gfx10:
    case AMDGPU::V_XOR_B32_dpp_gfx11:
    case AMDGPU::V_XOR_B32_dpp_gfx12: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 50, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_ADDC_CO_U32_dpp_gfx9:
    case AMDGPU::V_ADDC_U32_dpp_vi:
    case AMDGPU::V_ADD_CO_U32_dpp_gfx9:
    case AMDGPU::V_ADD_U16_dpp_vi:
    case AMDGPU::V_ADD_U32_dpp_gfx9:
    case AMDGPU::V_ADD_U32_dpp_vi:
    case AMDGPU::V_AND_B32_dpp_vi:
    case AMDGPU::V_ASHRREV_I16_dpp_vi:
    case AMDGPU::V_ASHRREV_I32_dpp_vi:
    case AMDGPU::V_LSHLREV_B16_dpp_vi:
    case AMDGPU::V_LSHLREV_B32_dpp_vi:
    case AMDGPU::V_LSHRREV_B16_dpp_vi:
    case AMDGPU::V_LSHRREV_B32_dpp_vi:
    case AMDGPU::V_MAX_I16_dpp_vi:
    case AMDGPU::V_MAX_I32_dpp_vi:
    case AMDGPU::V_MAX_U16_dpp_vi:
    case AMDGPU::V_MAX_U32_dpp_vi:
    case AMDGPU::V_MIN_I16_dpp_vi:
    case AMDGPU::V_MIN_I32_dpp_vi:
    case AMDGPU::V_MIN_U16_dpp_vi:
    case AMDGPU::V_MIN_U32_dpp_vi:
    case AMDGPU::V_MUL_HI_I32_I24_dpp_vi:
    case AMDGPU::V_MUL_HI_U32_U24_dpp_vi:
    case AMDGPU::V_MUL_I32_I24_dpp_vi:
    case AMDGPU::V_MUL_LO_U16_dpp_vi:
    case AMDGPU::V_MUL_U32_U24_dpp_vi:
    case AMDGPU::V_OR_B32_dpp_vi:
    case AMDGPU::V_SUBBREV_CO_U32_dpp_gfx9:
    case AMDGPU::V_SUBBREV_U32_dpp_vi:
    case AMDGPU::V_SUBB_CO_U32_dpp_gfx9:
    case AMDGPU::V_SUBB_U32_dpp_vi:
    case AMDGPU::V_SUBREV_CO_U32_dpp_gfx9:
    case AMDGPU::V_SUBREV_U16_dpp_vi:
    case AMDGPU::V_SUBREV_U32_dpp_gfx9:
    case AMDGPU::V_SUBREV_U32_dpp_vi:
    case AMDGPU::V_SUB_CO_U32_dpp_gfx9:
    case AMDGPU::V_SUB_U16_dpp_vi:
    case AMDGPU::V_SUB_U32_dpp_gfx9:
    case AMDGPU::V_SUB_U32_dpp_vi:
    case AMDGPU::V_XNOR_B32_dpp_vi:
    case AMDGPU::V_XOR_B32_dpp_vi: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_CEIL_F16_dpp8_gfx10:
    case AMDGPU::V_CEIL_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_CEIL_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_CEIL_F32_dpp8_gfx10:
    case AMDGPU::V_CEIL_F32_dpp8_gfx11:
    case AMDGPU::V_CEIL_F32_dpp8_gfx12:
    case AMDGPU::V_COS_BF16V_COS_BF16_fake16_dpp8_gfx1250:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_COS_F16_dpp8_gfx10:
    case AMDGPU::V_COS_F32_dpp8_gfx10:
    case AMDGPU::V_COS_F32_dpp8_gfx11:
    case AMDGPU::V_COS_F32_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_fake16_dpp8_gfx1250:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_F32_dpp8_gfx10:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_fake16_dpp8_gfx1250:
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_fake16_dpp8_gfx1250:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_F16_dpp8_gfx10:
    case AMDGPU::V_CVT_FLOOR_I32_F32_dpp8_gfx11:
    case AMDGPU::V_CVT_FLOOR_I32_F32_dpp8_gfx12:
    case AMDGPU::V_CVT_FLR_I32_F32_dpp8_gfx10:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_CVT_I16_F16_dpp8_gfx10:
    case AMDGPU::V_CVT_I32_F32_dpp8_gfx10:
    case AMDGPU::V_CVT_I32_F32_dpp8_gfx11:
    case AMDGPU::V_CVT_I32_F32_dpp8_gfx12:
    case AMDGPU::V_CVT_NEAREST_I32_F32_dpp8_gfx11:
    case AMDGPU::V_CVT_NEAREST_I32_F32_dpp8_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16_dpp8_gfx10:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16_dpp8_gfx10:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_fake16_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_fake16_dpp8_gfx1250:
    case AMDGPU::V_CVT_RPI_I32_F32_dpp8_gfx10:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_CVT_U16_F16_dpp8_gfx10:
    case AMDGPU::V_CVT_U32_F32_dpp8_gfx10:
    case AMDGPU::V_CVT_U32_F32_dpp8_gfx11:
    case AMDGPU::V_CVT_U32_F32_dpp8_gfx12:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_fake16_dpp8_gfx1250:
    case AMDGPU::V_EXP_F16_dpp8_gfx10:
    case AMDGPU::V_EXP_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_EXP_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_EXP_F32_dpp8_gfx10:
    case AMDGPU::V_EXP_F32_dpp8_gfx11:
    case AMDGPU::V_EXP_F32_dpp8_gfx12:
    case AMDGPU::V_FLOOR_F16_dpp8_gfx10:
    case AMDGPU::V_FLOOR_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_FLOOR_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_FLOOR_F32_dpp8_gfx10:
    case AMDGPU::V_FLOOR_F32_dpp8_gfx11:
    case AMDGPU::V_FLOOR_F32_dpp8_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_FRACT_F16_dpp8_gfx10:
    case AMDGPU::V_FRACT_F32_dpp8_gfx10:
    case AMDGPU::V_FRACT_F32_dpp8_gfx11:
    case AMDGPU::V_FRACT_F32_dpp8_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16_dpp8_gfx10:
    case AMDGPU::V_FREXP_EXP_I32_F32_dpp8_gfx10:
    case AMDGPU::V_FREXP_EXP_I32_F32_dpp8_gfx11:
    case AMDGPU::V_FREXP_EXP_I32_F32_dpp8_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_FREXP_MANT_F16_dpp8_gfx10:
    case AMDGPU::V_FREXP_MANT_F32_dpp8_gfx10:
    case AMDGPU::V_FREXP_MANT_F32_dpp8_gfx11:
    case AMDGPU::V_FREXP_MANT_F32_dpp8_gfx12:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_fake16_dpp8_gfx1250:
    case AMDGPU::V_LOG_F16_dpp8_gfx10:
    case AMDGPU::V_LOG_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_LOG_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_LOG_F32_dpp8_gfx10:
    case AMDGPU::V_LOG_F32_dpp8_gfx11:
    case AMDGPU::V_LOG_F32_dpp8_gfx12:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_fake16_dpp8_gfx1250:
    case AMDGPU::V_RCP_F16_dpp8_gfx10:
    case AMDGPU::V_RCP_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_RCP_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_RCP_F32_dpp8_gfx10:
    case AMDGPU::V_RCP_F32_dpp8_gfx11:
    case AMDGPU::V_RCP_F32_dpp8_gfx12:
    case AMDGPU::V_RCP_IFLAG_F32_dpp8_gfx10:
    case AMDGPU::V_RCP_IFLAG_F32_dpp8_gfx11:
    case AMDGPU::V_RCP_IFLAG_F32_dpp8_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_RNDNE_F16_dpp8_gfx10:
    case AMDGPU::V_RNDNE_F32_dpp8_gfx10:
    case AMDGPU::V_RNDNE_F32_dpp8_gfx11:
    case AMDGPU::V_RNDNE_F32_dpp8_gfx12:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_fake16_dpp8_gfx1250:
    case AMDGPU::V_RSQ_F16_dpp8_gfx10:
    case AMDGPU::V_RSQ_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_RSQ_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_RSQ_F32_dpp8_gfx10:
    case AMDGPU::V_RSQ_F32_dpp8_gfx11:
    case AMDGPU::V_RSQ_F32_dpp8_gfx12:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_fake16_dpp8_gfx1250:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_SIN_F16_dpp8_gfx10:
    case AMDGPU::V_SIN_F32_dpp8_gfx10:
    case AMDGPU::V_SIN_F32_dpp8_gfx11:
    case AMDGPU::V_SIN_F32_dpp8_gfx12:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_fake16_dpp8_gfx1250:
    case AMDGPU::V_SQRT_F16_dpp8_gfx10:
    case AMDGPU::V_SQRT_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_SQRT_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_SQRT_F32_dpp8_gfx10:
    case AMDGPU::V_SQRT_F32_dpp8_gfx11:
    case AMDGPU::V_SQRT_F32_dpp8_gfx12:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_fake16_dpp8_gfx1250:
    case AMDGPU::V_TANH_F16V_TANH_F16_fake16_dpp8_gfx1250:
    case AMDGPU::V_TANH_F32_dpp8_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_TRUNC_F16_dpp8_gfx10:
    case AMDGPU::V_TRUNC_F32_dpp8_gfx10:
    case AMDGPU::V_TRUNC_F32_dpp8_gfx11:
    case AMDGPU::V_TRUNC_F32_dpp8_gfx12: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 40, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_t16_dpp8_gfx1250:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_t16_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_t16_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_t16_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_dpp8_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_dpp8_gfx12: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 40, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_ADD_F16_dpp8_gfx10:
    case AMDGPU::V_ADD_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_ADD_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_ADD_F32_dpp8_gfx10:
    case AMDGPU::V_ADD_F32_dpp8_gfx11:
    case AMDGPU::V_ADD_F32_dpp8_gfx12:
    case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
    case AMDGPU::V_CNDMASK_B32_dpp8_gfx11:
    case AMDGPU::V_CNDMASK_B32_dpp8_gfx12:
    case AMDGPU::V_CNDMASK_B32_dpp8_w32_gfx10:
    case AMDGPU::V_CNDMASK_B32_dpp8_w32_gfx11:
    case AMDGPU::V_CNDMASK_B32_dpp8_w32_gfx12:
    case AMDGPU::V_CNDMASK_B32_dpp8_w64_gfx10:
    case AMDGPU::V_CNDMASK_B32_dpp8_w64_gfx11:
    case AMDGPU::V_CNDMASK_B32_dpp8_w64_gfx12:
    case AMDGPU::V_CVT_PKRTZ_F16_F32_dpp8_gfx10:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_dpp8_gfx12:
    case AMDGPU::V_LDEXP_F16_dpp8_gfx10:
    case AMDGPU::V_LDEXP_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_LDEXP_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_MAX_F16V_MAX_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_MAX_F16_dpp8_gfx10:
    case AMDGPU::V_MAX_F32_dpp8_gfx10:
    case AMDGPU::V_MAX_F32_dpp8_gfx11:
    case AMDGPU::V_MAX_NUM_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_MAX_NUM_F32_dpp8_gfx12:
    case AMDGPU::V_MIN_F16V_MIN_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_MIN_F16_dpp8_gfx10:
    case AMDGPU::V_MIN_F32_dpp8_gfx10:
    case AMDGPU::V_MIN_F32_dpp8_gfx11:
    case AMDGPU::V_MIN_NUM_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_MIN_NUM_F32_dpp8_gfx12:
    case AMDGPU::V_MUL_DX9_ZERO_F32_dpp8_gfx11:
    case AMDGPU::V_MUL_DX9_ZERO_F32_dpp8_gfx12:
    case AMDGPU::V_MUL_F16_dpp8_gfx10:
    case AMDGPU::V_MUL_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_MUL_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_MUL_F32_dpp8_gfx10:
    case AMDGPU::V_MUL_F32_dpp8_gfx11:
    case AMDGPU::V_MUL_F32_dpp8_gfx12:
    case AMDGPU::V_MUL_LEGACY_F32_dpp8_gfx10:
    case AMDGPU::V_PK_FMAC_F16_dpp8_gfx10:
    case AMDGPU::V_SUBREV_F16_dpp8_gfx10:
    case AMDGPU::V_SUBREV_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_SUBREV_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_SUBREV_F32_dpp8_gfx10:
    case AMDGPU::V_SUBREV_F32_dpp8_gfx11:
    case AMDGPU::V_SUBREV_F32_dpp8_gfx12:
    case AMDGPU::V_SUB_F16_dpp8_gfx10:
    case AMDGPU::V_SUB_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_SUB_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_SUB_F32_dpp8_gfx10:
    case AMDGPU::V_SUB_F32_dpp8_gfx11:
    case AMDGPU::V_SUB_F32_dpp8_gfx12: {
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 40, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_I16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_F_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_GE_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_GE_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_GE_I16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_GE_I16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_GE_U16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_GE_U16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_GT_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_GT_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_GT_I16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_GT_I16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_GT_U16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_GT_U16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_LE_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_LE_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_LE_I16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_LE_I16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_LE_U16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_LE_U16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_LG_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_LG_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_LT_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_LT_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_LT_I16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_LT_I16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_LT_U16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_LT_U16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_NE_I16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_NE_I16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_NE_U16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_NE_U16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_O_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_O_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_T_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_U_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_U_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_gfx11:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_gfx12:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_gfx11:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_gfx12:
    case AMDGPU::V_CMP_F_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_GE_I16_t16_e32_gfx11:
    case AMDGPU::V_CMP_GE_I16_t16_e32_gfx12:
    case AMDGPU::V_CMP_GE_U16_t16_e32_gfx11:
    case AMDGPU::V_CMP_GE_U16_t16_e32_gfx12:
    case AMDGPU::V_CMP_GT_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_GT_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_GT_I16_t16_e32_gfx11:
    case AMDGPU::V_CMP_GT_I16_t16_e32_gfx12:
    case AMDGPU::V_CMP_GT_U16_t16_e32_gfx11:
    case AMDGPU::V_CMP_GT_U16_t16_e32_gfx12:
    case AMDGPU::V_CMP_LE_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_LE_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_LE_I16_t16_e32_gfx11:
    case AMDGPU::V_CMP_LE_I16_t16_e32_gfx12:
    case AMDGPU::V_CMP_LE_U16_t16_e32_gfx11:
    case AMDGPU::V_CMP_LE_U16_t16_e32_gfx12:
    case AMDGPU::V_CMP_LG_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_LG_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_LT_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_LT_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_LT_I16_t16_e32_gfx11:
    case AMDGPU::V_CMP_LT_I16_t16_e32_gfx12:
    case AMDGPU::V_CMP_LT_U16_t16_e32_gfx11:
    case AMDGPU::V_CMP_LT_U16_t16_e32_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_NE_I16_t16_e32_gfx11:
    case AMDGPU::V_CMP_NE_I16_t16_e32_gfx12:
    case AMDGPU::V_CMP_NE_U16_t16_e32_gfx11:
    case AMDGPU::V_CMP_NE_U16_t16_e32_gfx12:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_O_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_O_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_T_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e32_gfx12: {
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_FMAC_F16_t16_dpp8_gfx11:
    case AMDGPU::V_FMAC_F16_t16_dpp8_gfx12: {
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 40, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_t16_dpp8_gfx1250:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_dpp8_gfx12:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_dpp8_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_t16_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_t16_dpp8_gfx1250:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_dpp8_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_dpp8_gfx12: {
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 40, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_CEIL_F16_t16_dpp8_gfx11:
    case AMDGPU::V_CEIL_F16_t16_dpp8_gfx12:
    case AMDGPU::V_COS_BF16V_COS_BF16_t16_dpp8_gfx1250:
    case AMDGPU::V_COS_F16V_COS_F16_t16_dpp8_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_t16_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_dpp8_gfx12:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_dpp8_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_dpp8_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_dpp8_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_dpp8_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_dpp8_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_dpp8_gfx12:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_dpp8_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_dpp8_gfx12:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_t16_dpp8_gfx1250:
    case AMDGPU::V_EXP_F16_t16_dpp8_gfx11:
    case AMDGPU::V_EXP_F16_t16_dpp8_gfx12:
    case AMDGPU::V_FLOOR_F16_t16_dpp8_gfx11:
    case AMDGPU::V_FLOOR_F16_t16_dpp8_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_dpp8_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_dpp8_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_dpp8_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_dpp8_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_dpp8_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_dpp8_gfx12:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_t16_dpp8_gfx1250:
    case AMDGPU::V_LOG_F16_t16_dpp8_gfx11:
    case AMDGPU::V_LOG_F16_t16_dpp8_gfx12:
    case AMDGPU::V_MOV_B16_t16_dpp8_gfx11:
    case AMDGPU::V_MOV_B16_t16_dpp8_gfx12:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_dpp8_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_dpp8_gfx12:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_t16_dpp8_gfx1250:
    case AMDGPU::V_RCP_F16_t16_dpp8_gfx11:
    case AMDGPU::V_RCP_F16_t16_dpp8_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_dpp8_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_dpp8_gfx12:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_t16_dpp8_gfx1250:
    case AMDGPU::V_RSQ_F16_t16_dpp8_gfx11:
    case AMDGPU::V_RSQ_F16_t16_dpp8_gfx12:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_t16_dpp8_gfx1250:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_dpp8_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_dpp8_gfx12:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_t16_dpp8_gfx1250:
    case AMDGPU::V_SQRT_F16_t16_dpp8_gfx11:
    case AMDGPU::V_SQRT_F16_t16_dpp8_gfx12:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_t16_dpp8_gfx1250:
    case AMDGPU::V_TANH_F16V_TANH_F16_t16_dpp8_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_dpp8_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_dpp8_gfx12: {
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 40, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_ADD_F16_t16_dpp8_gfx11:
    case AMDGPU::V_ADD_F16_t16_dpp8_gfx12:
    case AMDGPU::V_LDEXP_F16_t16_dpp8_gfx11:
    case AMDGPU::V_LDEXP_F16_t16_dpp8_gfx12:
    case AMDGPU::V_MAX_F16V_MAX_F16_t16_dpp8_gfx11:
    case AMDGPU::V_MAX_NUM_F16_t16_dpp8_gfx12:
    case AMDGPU::V_MIN_F16V_MIN_F16_t16_dpp8_gfx11:
    case AMDGPU::V_MIN_NUM_F16_t16_dpp8_gfx12:
    case AMDGPU::V_MUL_F16_t16_dpp8_gfx11:
    case AMDGPU::V_MUL_F16_t16_dpp8_gfx12:
    case AMDGPU::V_SUBREV_F16_t16_dpp8_gfx11:
    case AMDGPU::V_SUBREV_F16_t16_dpp8_gfx12:
    case AMDGPU::V_SUB_F16_t16_dpp8_gfx11:
    case AMDGPU::V_SUB_F16_t16_dpp8_gfx12: {
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 40, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_CMPX_EQ_I16_sdwa_gfx10:
    case AMDGPU::V_CMPX_EQ_I32_sdwa_gfx10:
    case AMDGPU::V_CMPX_EQ_U16_sdwa_gfx10:
    case AMDGPU::V_CMPX_EQ_U32_sdwa_gfx10:
    case AMDGPU::V_CMPX_F_I32_sdwa_gfx10:
    case AMDGPU::V_CMPX_F_U32_sdwa_gfx10:
    case AMDGPU::V_CMPX_GE_I16_sdwa_gfx10:
    case AMDGPU::V_CMPX_GE_I32_sdwa_gfx10:
    case AMDGPU::V_CMPX_GE_U16_sdwa_gfx10:
    case AMDGPU::V_CMPX_GE_U32_sdwa_gfx10:
    case AMDGPU::V_CMPX_GT_I16_sdwa_gfx10:
    case AMDGPU::V_CMPX_GT_I32_sdwa_gfx10:
    case AMDGPU::V_CMPX_GT_U16_sdwa_gfx10:
    case AMDGPU::V_CMPX_GT_U32_sdwa_gfx10:
    case AMDGPU::V_CMPX_LE_I16_sdwa_gfx10:
    case AMDGPU::V_CMPX_LE_I32_sdwa_gfx10:
    case AMDGPU::V_CMPX_LE_U16_sdwa_gfx10:
    case AMDGPU::V_CMPX_LE_U32_sdwa_gfx10:
    case AMDGPU::V_CMPX_LT_I16_sdwa_gfx10:
    case AMDGPU::V_CMPX_LT_I32_sdwa_gfx10:
    case AMDGPU::V_CMPX_LT_U16_sdwa_gfx10:
    case AMDGPU::V_CMPX_LT_U32_sdwa_gfx10:
    case AMDGPU::V_CMPX_NE_I16_sdwa_gfx10:
    case AMDGPU::V_CMPX_NE_I32_sdwa_gfx10:
    case AMDGPU::V_CMPX_NE_U16_sdwa_gfx10:
    case AMDGPU::V_CMPX_NE_U32_sdwa_gfx10:
    case AMDGPU::V_CMPX_T_I32_sdwa_gfx10:
    case AMDGPU::V_CMPX_T_U32_sdwa_gfx10: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 51, 1);
      // op: src1_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 56, 3);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 59, 1);
      // op: src1
      op.clearAllBits();
      getSDWASrcEncoding(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_CLASS_F32_sdwa_gfx10: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src1_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 56, 3);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 59, 1);
      // op: src1
      op.clearAllBits();
      getSDWASrcEncoding(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_CMPX_EQ_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_EQ_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_F_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_F_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_GE_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_GE_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_GT_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_GT_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_LE_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_LE_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_LG_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_LG_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_LT_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_LT_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_NEQ_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_NEQ_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_NGE_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_NGE_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_NGT_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_NGT_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_NLE_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_NLE_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_NLG_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_NLG_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_NLT_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_NLT_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_O_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_O_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_TRU_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_TRU_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_U_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_U_F32_sdwa_gfx10: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src1_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 56, 3);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 60, 2);
      // op: src1
      op.clearAllBits();
      getSDWASrcEncoding(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_CVT_F32_BF8_sdwa_gfx9:
    case AMDGPU::V_CVT_F32_FP8_sdwa_gfx9:
    case AMDGPU::V_CVT_PK_F32_BF8_sdwa_gfx9:
    case AMDGPU::V_CVT_PK_F32_FP8_sdwa_gfx9: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 51, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 46, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_BFREV_B32_sdwa_gfx10:
    case AMDGPU::V_BFREV_B32_sdwa_gfx9:
    case AMDGPU::V_FFBH_I32_sdwa_gfx10:
    case AMDGPU::V_FFBH_I32_sdwa_gfx9:
    case AMDGPU::V_FFBH_U32_sdwa_gfx10:
    case AMDGPU::V_FFBH_U32_sdwa_gfx9:
    case AMDGPU::V_FFBL_B32_sdwa_gfx10:
    case AMDGPU::V_FFBL_B32_sdwa_gfx9:
    case AMDGPU::V_MOVRELD_B32_sdwa_gfx10:
    case AMDGPU::V_MOVRELSD_2_B32_sdwa_gfx10:
    case AMDGPU::V_MOVRELSD_B32_sdwa_gfx10:
    case AMDGPU::V_MOVRELS_B32_sdwa_gfx10:
    case AMDGPU::V_MOV_B32_sdwa_gfx10:
    case AMDGPU::V_MOV_B32_sdwa_gfx9:
    case AMDGPU::V_NOT_B32_sdwa_gfx10:
    case AMDGPU::V_NOT_B32_sdwa_gfx9:
    case AMDGPU::V_PRNG_B32_sdwa_gfx9:
    case AMDGPU::V_SAT_PK_U8_I16_sdwa_gfx10:
    case AMDGPU::V_SAT_PK_U8_I16_sdwa_gfx9:
    case AMDGPU::V_SCREEN_PARTITION_4SE_B32_sdwa_gfx9: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 51, 1);
      // op: dst_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 40, 3);
      // op: dst_unused
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 43, 2);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_CMPX_EQ_I16_sdwa_gfx9:
    case AMDGPU::V_CMPX_EQ_I32_sdwa_gfx9:
    case AMDGPU::V_CMPX_EQ_U16_sdwa_gfx9:
    case AMDGPU::V_CMPX_EQ_U32_sdwa_gfx9:
    case AMDGPU::V_CMPX_F_I16_sdwa_gfx9:
    case AMDGPU::V_CMPX_F_I32_sdwa_gfx9:
    case AMDGPU::V_CMPX_F_U16_sdwa_gfx9:
    case AMDGPU::V_CMPX_F_U32_sdwa_gfx9:
    case AMDGPU::V_CMPX_GE_I16_sdwa_gfx9:
    case AMDGPU::V_CMPX_GE_I32_sdwa_gfx9:
    case AMDGPU::V_CMPX_GE_U16_sdwa_gfx9:
    case AMDGPU::V_CMPX_GE_U32_sdwa_gfx9:
    case AMDGPU::V_CMPX_GT_I16_sdwa_gfx9:
    case AMDGPU::V_CMPX_GT_I32_sdwa_gfx9:
    case AMDGPU::V_CMPX_GT_U16_sdwa_gfx9:
    case AMDGPU::V_CMPX_GT_U32_sdwa_gfx9:
    case AMDGPU::V_CMPX_LE_I16_sdwa_gfx9:
    case AMDGPU::V_CMPX_LE_I32_sdwa_gfx9:
    case AMDGPU::V_CMPX_LE_U16_sdwa_gfx9:
    case AMDGPU::V_CMPX_LE_U32_sdwa_gfx9:
    case AMDGPU::V_CMPX_LT_I16_sdwa_gfx9:
    case AMDGPU::V_CMPX_LT_I32_sdwa_gfx9:
    case AMDGPU::V_CMPX_LT_U16_sdwa_gfx9:
    case AMDGPU::V_CMPX_LT_U32_sdwa_gfx9:
    case AMDGPU::V_CMPX_NE_I16_sdwa_gfx9:
    case AMDGPU::V_CMPX_NE_I32_sdwa_gfx9:
    case AMDGPU::V_CMPX_NE_U16_sdwa_gfx9:
    case AMDGPU::V_CMPX_NE_U32_sdwa_gfx9:
    case AMDGPU::V_CMPX_T_I16_sdwa_gfx9:
    case AMDGPU::V_CMPX_T_I32_sdwa_gfx9:
    case AMDGPU::V_CMPX_T_U16_sdwa_gfx9:
    case AMDGPU::V_CMPX_T_U32_sdwa_gfx9:
    case AMDGPU::V_CMP_EQ_I16_sdwa_gfx10:
    case AMDGPU::V_CMP_EQ_I16_sdwa_gfx9:
    case AMDGPU::V_CMP_EQ_I32_sdwa_gfx10:
    case AMDGPU::V_CMP_EQ_I32_sdwa_gfx9:
    case AMDGPU::V_CMP_EQ_U16_sdwa_gfx10:
    case AMDGPU::V_CMP_EQ_U16_sdwa_gfx9:
    case AMDGPU::V_CMP_EQ_U32_sdwa_gfx10:
    case AMDGPU::V_CMP_EQ_U32_sdwa_gfx9:
    case AMDGPU::V_CMP_F_I16_sdwa_gfx9:
    case AMDGPU::V_CMP_F_I32_sdwa_gfx10:
    case AMDGPU::V_CMP_F_I32_sdwa_gfx9:
    case AMDGPU::V_CMP_F_U16_sdwa_gfx9:
    case AMDGPU::V_CMP_F_U32_sdwa_gfx10:
    case AMDGPU::V_CMP_F_U32_sdwa_gfx9:
    case AMDGPU::V_CMP_GE_I16_sdwa_gfx10:
    case AMDGPU::V_CMP_GE_I16_sdwa_gfx9:
    case AMDGPU::V_CMP_GE_I32_sdwa_gfx10:
    case AMDGPU::V_CMP_GE_I32_sdwa_gfx9:
    case AMDGPU::V_CMP_GE_U16_sdwa_gfx10:
    case AMDGPU::V_CMP_GE_U16_sdwa_gfx9:
    case AMDGPU::V_CMP_GE_U32_sdwa_gfx10:
    case AMDGPU::V_CMP_GE_U32_sdwa_gfx9:
    case AMDGPU::V_CMP_GT_I16_sdwa_gfx10:
    case AMDGPU::V_CMP_GT_I16_sdwa_gfx9:
    case AMDGPU::V_CMP_GT_I32_sdwa_gfx10:
    case AMDGPU::V_CMP_GT_I32_sdwa_gfx9:
    case AMDGPU::V_CMP_GT_U16_sdwa_gfx10:
    case AMDGPU::V_CMP_GT_U16_sdwa_gfx9:
    case AMDGPU::V_CMP_GT_U32_sdwa_gfx10:
    case AMDGPU::V_CMP_GT_U32_sdwa_gfx9:
    case AMDGPU::V_CMP_LE_I16_sdwa_gfx10:
    case AMDGPU::V_CMP_LE_I16_sdwa_gfx9:
    case AMDGPU::V_CMP_LE_I32_sdwa_gfx10:
    case AMDGPU::V_CMP_LE_I32_sdwa_gfx9:
    case AMDGPU::V_CMP_LE_U16_sdwa_gfx10:
    case AMDGPU::V_CMP_LE_U16_sdwa_gfx9:
    case AMDGPU::V_CMP_LE_U32_sdwa_gfx10:
    case AMDGPU::V_CMP_LE_U32_sdwa_gfx9:
    case AMDGPU::V_CMP_LT_I16_sdwa_gfx10:
    case AMDGPU::V_CMP_LT_I16_sdwa_gfx9:
    case AMDGPU::V_CMP_LT_I32_sdwa_gfx10:
    case AMDGPU::V_CMP_LT_I32_sdwa_gfx9:
    case AMDGPU::V_CMP_LT_U16_sdwa_gfx10:
    case AMDGPU::V_CMP_LT_U16_sdwa_gfx9:
    case AMDGPU::V_CMP_LT_U32_sdwa_gfx10:
    case AMDGPU::V_CMP_LT_U32_sdwa_gfx9:
    case AMDGPU::V_CMP_NE_I16_sdwa_gfx10:
    case AMDGPU::V_CMP_NE_I16_sdwa_gfx9:
    case AMDGPU::V_CMP_NE_I32_sdwa_gfx10:
    case AMDGPU::V_CMP_NE_I32_sdwa_gfx9:
    case AMDGPU::V_CMP_NE_U16_sdwa_gfx10:
    case AMDGPU::V_CMP_NE_U16_sdwa_gfx9:
    case AMDGPU::V_CMP_NE_U32_sdwa_gfx10:
    case AMDGPU::V_CMP_NE_U32_sdwa_gfx9:
    case AMDGPU::V_CMP_T_I16_sdwa_gfx9:
    case AMDGPU::V_CMP_T_I32_sdwa_gfx10:
    case AMDGPU::V_CMP_T_I32_sdwa_gfx9:
    case AMDGPU::V_CMP_T_U16_sdwa_gfx9:
    case AMDGPU::V_CMP_T_U32_sdwa_gfx10:
    case AMDGPU::V_CMP_T_U32_sdwa_gfx9: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 51, 1);
      // op: src1_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 56, 3);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 59, 1);
      // op: sdst
      op.clearAllBits();
      getSDWAVopcDstEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: src1
      op.clearAllBits();
      getSDWASrcEncoding(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_CVT_FLR_I32_F32_sdwa_gfx10:
    case AMDGPU::V_CVT_FLR_I32_F32_sdwa_gfx9:
    case AMDGPU::V_CVT_I16_F16_sdwa_gfx10:
    case AMDGPU::V_CVT_I16_F16_sdwa_gfx9:
    case AMDGPU::V_CVT_I32_F32_sdwa_gfx10:
    case AMDGPU::V_CVT_I32_F32_sdwa_gfx9:
    case AMDGPU::V_CVT_NORM_I16_F16_sdwa_gfx10:
    case AMDGPU::V_CVT_NORM_I16_F16_sdwa_gfx9:
    case AMDGPU::V_CVT_NORM_U16_F16_sdwa_gfx10:
    case AMDGPU::V_CVT_NORM_U16_F16_sdwa_gfx9:
    case AMDGPU::V_CVT_RPI_I32_F32_sdwa_gfx10:
    case AMDGPU::V_CVT_RPI_I32_F32_sdwa_gfx9:
    case AMDGPU::V_CVT_U16_F16_sdwa_gfx10:
    case AMDGPU::V_CVT_U16_F16_sdwa_gfx9:
    case AMDGPU::V_CVT_U32_F32_sdwa_gfx10:
    case AMDGPU::V_CVT_U32_F32_sdwa_gfx9:
    case AMDGPU::V_FREXP_EXP_I16_F16_sdwa_gfx10:
    case AMDGPU::V_FREXP_EXP_I16_F16_sdwa_gfx9:
    case AMDGPU::V_FREXP_EXP_I32_F32_sdwa_gfx10:
    case AMDGPU::V_FREXP_EXP_I32_F32_sdwa_gfx9: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: dst_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 40, 3);
      // op: dst_unused
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 43, 2);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_CLASS_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_CLASS_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_CLASS_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_CLASS_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_CLASS_F32_sdwa_gfx9: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src1_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 56, 3);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 59, 1);
      // op: sdst
      op.clearAllBits();
      getSDWAVopcDstEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: src1
      op.clearAllBits();
      getSDWASrcEncoding(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_CMPX_EQ_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_EQ_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_F_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_F_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_GE_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_GE_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_GT_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_GT_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_LE_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_LE_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_LG_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_LG_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_LT_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_LT_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_NEQ_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_NEQ_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_NGE_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_NGE_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_NGT_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_NGT_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_NLE_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_NLE_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_NLG_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_NLG_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_NLT_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_NLT_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_O_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_O_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_TRU_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_TRU_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_U_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_U_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_EQ_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_EQ_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_EQ_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_EQ_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_F_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_F_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_F_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_F_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_GE_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_GE_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_GE_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_GE_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_GT_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_GT_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_GT_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_GT_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_LE_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_LE_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_LE_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_LE_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_LG_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_LG_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_LG_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_LG_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_LT_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_LT_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_LT_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_LT_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_NEQ_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_NEQ_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_NEQ_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_NEQ_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_NGE_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_NGE_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_NGE_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_NGE_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_NGT_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_NGT_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_NGT_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_NGT_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_NLE_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_NLE_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_NLE_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_NLE_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_NLG_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_NLG_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_NLG_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_NLG_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_NLT_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_NLT_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_NLT_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_NLT_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_O_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_O_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_O_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_O_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_TRU_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_TRU_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_TRU_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_TRU_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_U_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_U_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_U_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_U_F32_sdwa_gfx9: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src1_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 56, 3);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 60, 2);
      // op: sdst
      op.clearAllBits();
      getSDWAVopcDstEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: src1
      op.clearAllBits();
      getSDWASrcEncoding(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_CVT_F16_I16_sdwa_gfx10:
    case AMDGPU::V_CVT_F16_I16_sdwa_gfx9:
    case AMDGPU::V_CVT_F16_U16_sdwa_gfx10:
    case AMDGPU::V_CVT_F16_U16_sdwa_gfx9:
    case AMDGPU::V_CVT_F32_I32_sdwa_gfx10:
    case AMDGPU::V_CVT_F32_I32_sdwa_gfx9:
    case AMDGPU::V_CVT_F32_U32_sdwa_gfx10:
    case AMDGPU::V_CVT_F32_U32_sdwa_gfx9:
    case AMDGPU::V_CVT_F32_UBYTE0_sdwa_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE0_sdwa_gfx9:
    case AMDGPU::V_CVT_F32_UBYTE1_sdwa_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE1_sdwa_gfx9:
    case AMDGPU::V_CVT_F32_UBYTE2_sdwa_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE2_sdwa_gfx9:
    case AMDGPU::V_CVT_F32_UBYTE3_sdwa_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE3_sdwa_gfx9:
    case AMDGPU::V_CVT_OFF_F32_I4_sdwa_gfx10:
    case AMDGPU::V_CVT_OFF_F32_I4_sdwa_gfx9: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 51, 1);
      // op: dst_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 40, 3);
      // op: dst_unused
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 43, 2);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 46, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_CEIL_F16_sdwa_gfx10:
    case AMDGPU::V_CEIL_F16_sdwa_gfx9:
    case AMDGPU::V_CEIL_F32_sdwa_gfx10:
    case AMDGPU::V_CEIL_F32_sdwa_gfx9:
    case AMDGPU::V_COS_F16_sdwa_gfx10:
    case AMDGPU::V_COS_F16_sdwa_gfx9:
    case AMDGPU::V_COS_F32_sdwa_gfx10:
    case AMDGPU::V_COS_F32_sdwa_gfx9:
    case AMDGPU::V_CVT_F16_F32_sdwa_gfx10:
    case AMDGPU::V_CVT_F16_F32_sdwa_gfx9:
    case AMDGPU::V_CVT_F32_BF16_sdwa_gfx9:
    case AMDGPU::V_CVT_F32_F16_sdwa_gfx10:
    case AMDGPU::V_CVT_F32_F16_sdwa_gfx9:
    case AMDGPU::V_EXP_F16_sdwa_gfx10:
    case AMDGPU::V_EXP_F16_sdwa_gfx9:
    case AMDGPU::V_EXP_F32_sdwa_gfx10:
    case AMDGPU::V_EXP_F32_sdwa_gfx9:
    case AMDGPU::V_EXP_LEGACY_F32_sdwa_gfx9:
    case AMDGPU::V_FLOOR_F16_sdwa_gfx10:
    case AMDGPU::V_FLOOR_F16_sdwa_gfx9:
    case AMDGPU::V_FLOOR_F32_sdwa_gfx10:
    case AMDGPU::V_FLOOR_F32_sdwa_gfx9:
    case AMDGPU::V_FRACT_F16_sdwa_gfx10:
    case AMDGPU::V_FRACT_F16_sdwa_gfx9:
    case AMDGPU::V_FRACT_F32_sdwa_gfx10:
    case AMDGPU::V_FRACT_F32_sdwa_gfx9:
    case AMDGPU::V_FREXP_MANT_F16_sdwa_gfx10:
    case AMDGPU::V_FREXP_MANT_F16_sdwa_gfx9:
    case AMDGPU::V_FREXP_MANT_F32_sdwa_gfx10:
    case AMDGPU::V_FREXP_MANT_F32_sdwa_gfx9:
    case AMDGPU::V_LOG_F16_sdwa_gfx10:
    case AMDGPU::V_LOG_F16_sdwa_gfx9:
    case AMDGPU::V_LOG_F32_sdwa_gfx10:
    case AMDGPU::V_LOG_F32_sdwa_gfx9:
    case AMDGPU::V_LOG_LEGACY_F32_sdwa_gfx9:
    case AMDGPU::V_RCP_F16_sdwa_gfx10:
    case AMDGPU::V_RCP_F16_sdwa_gfx9:
    case AMDGPU::V_RCP_F32_sdwa_gfx10:
    case AMDGPU::V_RCP_F32_sdwa_gfx9:
    case AMDGPU::V_RCP_IFLAG_F32_sdwa_gfx10:
    case AMDGPU::V_RCP_IFLAG_F32_sdwa_gfx9:
    case AMDGPU::V_RNDNE_F16_sdwa_gfx10:
    case AMDGPU::V_RNDNE_F16_sdwa_gfx9:
    case AMDGPU::V_RNDNE_F32_sdwa_gfx10:
    case AMDGPU::V_RNDNE_F32_sdwa_gfx9:
    case AMDGPU::V_RSQ_F16_sdwa_gfx10:
    case AMDGPU::V_RSQ_F16_sdwa_gfx9:
    case AMDGPU::V_RSQ_F32_sdwa_gfx10:
    case AMDGPU::V_RSQ_F32_sdwa_gfx9:
    case AMDGPU::V_SIN_F16_sdwa_gfx10:
    case AMDGPU::V_SIN_F16_sdwa_gfx9:
    case AMDGPU::V_SIN_F32_sdwa_gfx10:
    case AMDGPU::V_SIN_F32_sdwa_gfx9:
    case AMDGPU::V_SQRT_F16_sdwa_gfx10:
    case AMDGPU::V_SQRT_F16_sdwa_gfx9:
    case AMDGPU::V_SQRT_F32_sdwa_gfx10:
    case AMDGPU::V_SQRT_F32_sdwa_gfx9:
    case AMDGPU::V_TRUNC_F16_sdwa_gfx10:
    case AMDGPU::V_TRUNC_F16_sdwa_gfx9:
    case AMDGPU::V_TRUNC_F32_sdwa_gfx10:
    case AMDGPU::V_TRUNC_F32_sdwa_gfx9: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: dst_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 40, 3);
      // op: dst_unused
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 43, 2);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 46, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_ADDC_CO_U32_sdwa_gfx9:
    case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
    case AMDGPU::V_ADD_CO_CI_U32_sdwa_w32_gfx10:
    case AMDGPU::V_ADD_CO_CI_U32_sdwa_w64_gfx10:
    case AMDGPU::V_ADD_CO_U32_sdwa_gfx9:
    case AMDGPU::V_ADD_NC_U32_sdwa_gfx10:
    case AMDGPU::V_ADD_U16_sdwa_gfx9:
    case AMDGPU::V_ADD_U32_sdwa_gfx9:
    case AMDGPU::V_AND_B32_sdwa_gfx10:
    case AMDGPU::V_AND_B32_sdwa_gfx9:
    case AMDGPU::V_ASHRREV_I16_sdwa_gfx9:
    case AMDGPU::V_ASHRREV_I32_sdwa_gfx10:
    case AMDGPU::V_ASHRREV_I32_sdwa_gfx9:
    case AMDGPU::V_LSHLREV_B16_sdwa_gfx9:
    case AMDGPU::V_LSHLREV_B32_sdwa_gfx10:
    case AMDGPU::V_LSHLREV_B32_sdwa_gfx9:
    case AMDGPU::V_LSHRREV_B16_sdwa_gfx9:
    case AMDGPU::V_LSHRREV_B32_sdwa_gfx10:
    case AMDGPU::V_LSHRREV_B32_sdwa_gfx9:
    case AMDGPU::V_MAX_I16_sdwa_gfx9:
    case AMDGPU::V_MAX_I32_sdwa_gfx10:
    case AMDGPU::V_MAX_I32_sdwa_gfx9:
    case AMDGPU::V_MAX_U16_sdwa_gfx9:
    case AMDGPU::V_MAX_U32_sdwa_gfx10:
    case AMDGPU::V_MAX_U32_sdwa_gfx9:
    case AMDGPU::V_MIN_I16_sdwa_gfx9:
    case AMDGPU::V_MIN_I32_sdwa_gfx10:
    case AMDGPU::V_MIN_I32_sdwa_gfx9:
    case AMDGPU::V_MIN_U16_sdwa_gfx9:
    case AMDGPU::V_MIN_U32_sdwa_gfx10:
    case AMDGPU::V_MIN_U32_sdwa_gfx9:
    case AMDGPU::V_MUL_HI_I32_I24_sdwa_gfx10:
    case AMDGPU::V_MUL_HI_I32_I24_sdwa_gfx9:
    case AMDGPU::V_MUL_HI_U32_U24_sdwa_gfx10:
    case AMDGPU::V_MUL_HI_U32_U24_sdwa_gfx9:
    case AMDGPU::V_MUL_I32_I24_sdwa_gfx10:
    case AMDGPU::V_MUL_I32_I24_sdwa_gfx9:
    case AMDGPU::V_MUL_LO_U16_sdwa_gfx9:
    case AMDGPU::V_MUL_U32_U24_sdwa_gfx10:
    case AMDGPU::V_MUL_U32_U24_sdwa_gfx9:
    case AMDGPU::V_OR_B32_sdwa_gfx10:
    case AMDGPU::V_OR_B32_sdwa_gfx9:
    case AMDGPU::V_SUBBREV_CO_U32_sdwa_gfx9:
    case AMDGPU::V_SUBB_CO_U32_sdwa_gfx9:
    case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
    case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_w32_gfx10:
    case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_w64_gfx10:
    case AMDGPU::V_SUBREV_CO_U32_sdwa_gfx9:
    case AMDGPU::V_SUBREV_NC_U32_sdwa_gfx10:
    case AMDGPU::V_SUBREV_U16_sdwa_gfx9:
    case AMDGPU::V_SUBREV_U32_sdwa_gfx9:
    case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
    case AMDGPU::V_SUB_CO_CI_U32_sdwa_w32_gfx10:
    case AMDGPU::V_SUB_CO_CI_U32_sdwa_w64_gfx10:
    case AMDGPU::V_SUB_CO_U32_sdwa_gfx9:
    case AMDGPU::V_SUB_NC_U32_sdwa_gfx10:
    case AMDGPU::V_SUB_U16_sdwa_gfx9:
    case AMDGPU::V_SUB_U32_sdwa_gfx9:
    case AMDGPU::V_XNOR_B32_sdwa_gfx10:
    case AMDGPU::V_XNOR_B32_sdwa_gfx9:
    case AMDGPU::V_XOR_B32_sdwa_gfx10:
    case AMDGPU::V_XOR_B32_sdwa_gfx9: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 51, 1);
      // op: src1_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 56, 3);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 59, 1);
      // op: dst_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 40, 3);
      // op: dst_unused
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 43, 2);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getSDWASrcEncoding(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
    case AMDGPU::V_CNDMASK_B32_sdwa_gfx9:
    case AMDGPU::V_CNDMASK_B32_sdwa_w32_gfx10:
    case AMDGPU::V_CNDMASK_B32_sdwa_w64_gfx10: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src1_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 56, 3);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 60, 2);
      // op: dst_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 40, 3);
      // op: dst_unused
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 43, 2);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getSDWASrcEncoding(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_LDEXP_F16_sdwa_gfx10:
    case AMDGPU::V_LDEXP_F16_sdwa_gfx9: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src1_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 56, 3);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 59, 1);
      // op: dst_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 40, 3);
      // op: dst_unused
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 43, 2);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 46, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getSDWASrcEncoding(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_ADD_F16_sdwa_gfx10:
    case AMDGPU::V_ADD_F16_sdwa_gfx9:
    case AMDGPU::V_ADD_F32_sdwa_gfx10:
    case AMDGPU::V_ADD_F32_sdwa_gfx9:
    case AMDGPU::V_CVT_PKRTZ_F16_F32_sdwa_gfx10:
    case AMDGPU::V_MAX_F16_sdwa_gfx10:
    case AMDGPU::V_MAX_F16_sdwa_gfx9:
    case AMDGPU::V_MAX_F32_sdwa_gfx10:
    case AMDGPU::V_MAX_F32_sdwa_gfx9:
    case AMDGPU::V_MIN_F16_sdwa_gfx10:
    case AMDGPU::V_MIN_F16_sdwa_gfx9:
    case AMDGPU::V_MIN_F32_sdwa_gfx10:
    case AMDGPU::V_MIN_F32_sdwa_gfx9:
    case AMDGPU::V_MUL_F16_sdwa_gfx10:
    case AMDGPU::V_MUL_F16_sdwa_gfx9:
    case AMDGPU::V_MUL_F32_sdwa_gfx10:
    case AMDGPU::V_MUL_F32_sdwa_gfx9:
    case AMDGPU::V_MUL_LEGACY_F32_sdwa_gfx10:
    case AMDGPU::V_MUL_LEGACY_F32_sdwa_gfx9:
    case AMDGPU::V_PK_FMAC_F16_sdwa_gfx9:
    case AMDGPU::V_SUBREV_F16_sdwa_gfx10:
    case AMDGPU::V_SUBREV_F16_sdwa_gfx9:
    case AMDGPU::V_SUBREV_F32_sdwa_gfx10:
    case AMDGPU::V_SUBREV_F32_sdwa_gfx9:
    case AMDGPU::V_SUB_F16_sdwa_gfx10:
    case AMDGPU::V_SUB_F16_sdwa_gfx9:
    case AMDGPU::V_SUB_F32_sdwa_gfx10:
    case AMDGPU::V_SUB_F32_sdwa_gfx9: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src1_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 56, 3);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 60, 2);
      // op: dst_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 40, 3);
      // op: dst_unused
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 43, 2);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 46, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getSDWASrcEncoding(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 8), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_FMAC_F32_sdwa_vi:
    case AMDGPU::V_MAC_F16_sdwa_vi:
    case AMDGPU::V_MAC_F32_sdwa_vi: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src1_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 56, 3);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 60, 2);
      // op: dst_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 40, 3);
      // op: dst_unused
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 43, 2);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getSDWASrcEncoding(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_BFREV_B32_sdwa_vi:
    case AMDGPU::V_FFBH_I32_sdwa_vi:
    case AMDGPU::V_FFBH_U32_sdwa_vi:
    case AMDGPU::V_FFBL_B32_sdwa_vi:
    case AMDGPU::V_MOV_B32_sdwa_vi:
    case AMDGPU::V_NOT_B32_sdwa_vi:
    case AMDGPU::V_SAT_PK_U8_I16_sdwa_vi: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 51, 1);
      // op: dst_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 40, 3);
      // op: dst_unused
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 43, 2);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_CMPX_EQ_I16_sdwa_vi:
    case AMDGPU::V_CMPX_EQ_I32_sdwa_vi:
    case AMDGPU::V_CMPX_EQ_U16_sdwa_vi:
    case AMDGPU::V_CMPX_EQ_U32_sdwa_vi:
    case AMDGPU::V_CMPX_F_I16_sdwa_vi:
    case AMDGPU::V_CMPX_F_I32_sdwa_vi:
    case AMDGPU::V_CMPX_F_U16_sdwa_vi:
    case AMDGPU::V_CMPX_F_U32_sdwa_vi:
    case AMDGPU::V_CMPX_GE_I16_sdwa_vi:
    case AMDGPU::V_CMPX_GE_I32_sdwa_vi:
    case AMDGPU::V_CMPX_GE_U16_sdwa_vi:
    case AMDGPU::V_CMPX_GE_U32_sdwa_vi:
    case AMDGPU::V_CMPX_GT_I16_sdwa_vi:
    case AMDGPU::V_CMPX_GT_I32_sdwa_vi:
    case AMDGPU::V_CMPX_GT_U16_sdwa_vi:
    case AMDGPU::V_CMPX_GT_U32_sdwa_vi:
    case AMDGPU::V_CMPX_LE_I16_sdwa_vi:
    case AMDGPU::V_CMPX_LE_I32_sdwa_vi:
    case AMDGPU::V_CMPX_LE_U16_sdwa_vi:
    case AMDGPU::V_CMPX_LE_U32_sdwa_vi:
    case AMDGPU::V_CMPX_LT_I16_sdwa_vi:
    case AMDGPU::V_CMPX_LT_I32_sdwa_vi:
    case AMDGPU::V_CMPX_LT_U16_sdwa_vi:
    case AMDGPU::V_CMPX_LT_U32_sdwa_vi:
    case AMDGPU::V_CMPX_NE_I16_sdwa_vi:
    case AMDGPU::V_CMPX_NE_I32_sdwa_vi:
    case AMDGPU::V_CMPX_NE_U16_sdwa_vi:
    case AMDGPU::V_CMPX_NE_U32_sdwa_vi:
    case AMDGPU::V_CMPX_T_I16_sdwa_vi:
    case AMDGPU::V_CMPX_T_I32_sdwa_vi:
    case AMDGPU::V_CMPX_T_U16_sdwa_vi:
    case AMDGPU::V_CMPX_T_U32_sdwa_vi:
    case AMDGPU::V_CMP_EQ_I16_sdwa_vi:
    case AMDGPU::V_CMP_EQ_I32_sdwa_vi:
    case AMDGPU::V_CMP_EQ_U16_sdwa_vi:
    case AMDGPU::V_CMP_EQ_U32_sdwa_vi:
    case AMDGPU::V_CMP_F_I16_sdwa_vi:
    case AMDGPU::V_CMP_F_I32_sdwa_vi:
    case AMDGPU::V_CMP_F_U16_sdwa_vi:
    case AMDGPU::V_CMP_F_U32_sdwa_vi:
    case AMDGPU::V_CMP_GE_I16_sdwa_vi:
    case AMDGPU::V_CMP_GE_I32_sdwa_vi:
    case AMDGPU::V_CMP_GE_U16_sdwa_vi:
    case AMDGPU::V_CMP_GE_U32_sdwa_vi:
    case AMDGPU::V_CMP_GT_I16_sdwa_vi:
    case AMDGPU::V_CMP_GT_I32_sdwa_vi:
    case AMDGPU::V_CMP_GT_U16_sdwa_vi:
    case AMDGPU::V_CMP_GT_U32_sdwa_vi:
    case AMDGPU::V_CMP_LE_I16_sdwa_vi:
    case AMDGPU::V_CMP_LE_I32_sdwa_vi:
    case AMDGPU::V_CMP_LE_U16_sdwa_vi:
    case AMDGPU::V_CMP_LE_U32_sdwa_vi:
    case AMDGPU::V_CMP_LT_I16_sdwa_vi:
    case AMDGPU::V_CMP_LT_I32_sdwa_vi:
    case AMDGPU::V_CMP_LT_U16_sdwa_vi:
    case AMDGPU::V_CMP_LT_U32_sdwa_vi:
    case AMDGPU::V_CMP_NE_I16_sdwa_vi:
    case AMDGPU::V_CMP_NE_I32_sdwa_vi:
    case AMDGPU::V_CMP_NE_U16_sdwa_vi:
    case AMDGPU::V_CMP_NE_U32_sdwa_vi:
    case AMDGPU::V_CMP_T_I16_sdwa_vi:
    case AMDGPU::V_CMP_T_I32_sdwa_vi:
    case AMDGPU::V_CMP_T_U16_sdwa_vi:
    case AMDGPU::V_CMP_T_U32_sdwa_vi: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 51, 1);
      // op: src1_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 56, 3);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 59, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: src1
      op.clearAllBits();
      getSDWASrcEncoding(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_CVT_FLR_I32_F32_sdwa_vi:
    case AMDGPU::V_CVT_I16_F16_sdwa_vi:
    case AMDGPU::V_CVT_I32_F32_sdwa_vi:
    case AMDGPU::V_CVT_NORM_I16_F16_sdwa_vi:
    case AMDGPU::V_CVT_NORM_U16_F16_sdwa_vi:
    case AMDGPU::V_CVT_RPI_I32_F32_sdwa_vi:
    case AMDGPU::V_CVT_U16_F16_sdwa_vi:
    case AMDGPU::V_CVT_U32_F32_sdwa_vi:
    case AMDGPU::V_FREXP_EXP_I16_F16_sdwa_vi:
    case AMDGPU::V_FREXP_EXP_I32_F32_sdwa_vi: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: dst_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 40, 3);
      // op: dst_unused
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 43, 2);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_sdwa_vi:
    case AMDGPU::V_CMPX_CLASS_F32_sdwa_vi:
    case AMDGPU::V_CMP_CLASS_F16_sdwa_vi:
    case AMDGPU::V_CMP_CLASS_F32_sdwa_vi: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src1_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 56, 3);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 59, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: src1
      op.clearAllBits();
      getSDWASrcEncoding(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_CMPX_EQ_F16_sdwa_vi:
    case AMDGPU::V_CMPX_EQ_F32_sdwa_vi:
    case AMDGPU::V_CMPX_F_F16_sdwa_vi:
    case AMDGPU::V_CMPX_F_F32_sdwa_vi:
    case AMDGPU::V_CMPX_GE_F16_sdwa_vi:
    case AMDGPU::V_CMPX_GE_F32_sdwa_vi:
    case AMDGPU::V_CMPX_GT_F16_sdwa_vi:
    case AMDGPU::V_CMPX_GT_F32_sdwa_vi:
    case AMDGPU::V_CMPX_LE_F16_sdwa_vi:
    case AMDGPU::V_CMPX_LE_F32_sdwa_vi:
    case AMDGPU::V_CMPX_LG_F16_sdwa_vi:
    case AMDGPU::V_CMPX_LG_F32_sdwa_vi:
    case AMDGPU::V_CMPX_LT_F16_sdwa_vi:
    case AMDGPU::V_CMPX_LT_F32_sdwa_vi:
    case AMDGPU::V_CMPX_NEQ_F16_sdwa_vi:
    case AMDGPU::V_CMPX_NEQ_F32_sdwa_vi:
    case AMDGPU::V_CMPX_NGE_F16_sdwa_vi:
    case AMDGPU::V_CMPX_NGE_F32_sdwa_vi:
    case AMDGPU::V_CMPX_NGT_F16_sdwa_vi:
    case AMDGPU::V_CMPX_NGT_F32_sdwa_vi:
    case AMDGPU::V_CMPX_NLE_F16_sdwa_vi:
    case AMDGPU::V_CMPX_NLE_F32_sdwa_vi:
    case AMDGPU::V_CMPX_NLG_F16_sdwa_vi:
    case AMDGPU::V_CMPX_NLG_F32_sdwa_vi:
    case AMDGPU::V_CMPX_NLT_F16_sdwa_vi:
    case AMDGPU::V_CMPX_NLT_F32_sdwa_vi:
    case AMDGPU::V_CMPX_O_F16_sdwa_vi:
    case AMDGPU::V_CMPX_O_F32_sdwa_vi:
    case AMDGPU::V_CMPX_TRU_F16_sdwa_vi:
    case AMDGPU::V_CMPX_TRU_F32_sdwa_vi:
    case AMDGPU::V_CMPX_U_F16_sdwa_vi:
    case AMDGPU::V_CMPX_U_F32_sdwa_vi:
    case AMDGPU::V_CMP_EQ_F16_sdwa_vi:
    case AMDGPU::V_CMP_EQ_F32_sdwa_vi:
    case AMDGPU::V_CMP_F_F16_sdwa_vi:
    case AMDGPU::V_CMP_F_F32_sdwa_vi:
    case AMDGPU::V_CMP_GE_F16_sdwa_vi:
    case AMDGPU::V_CMP_GE_F32_sdwa_vi:
    case AMDGPU::V_CMP_GT_F16_sdwa_vi:
    case AMDGPU::V_CMP_GT_F32_sdwa_vi:
    case AMDGPU::V_CMP_LE_F16_sdwa_vi:
    case AMDGPU::V_CMP_LE_F32_sdwa_vi:
    case AMDGPU::V_CMP_LG_F16_sdwa_vi:
    case AMDGPU::V_CMP_LG_F32_sdwa_vi:
    case AMDGPU::V_CMP_LT_F16_sdwa_vi:
    case AMDGPU::V_CMP_LT_F32_sdwa_vi:
    case AMDGPU::V_CMP_NEQ_F16_sdwa_vi:
    case AMDGPU::V_CMP_NEQ_F32_sdwa_vi:
    case AMDGPU::V_CMP_NGE_F16_sdwa_vi:
    case AMDGPU::V_CMP_NGE_F32_sdwa_vi:
    case AMDGPU::V_CMP_NGT_F16_sdwa_vi:
    case AMDGPU::V_CMP_NGT_F32_sdwa_vi:
    case AMDGPU::V_CMP_NLE_F16_sdwa_vi:
    case AMDGPU::V_CMP_NLE_F32_sdwa_vi:
    case AMDGPU::V_CMP_NLG_F16_sdwa_vi:
    case AMDGPU::V_CMP_NLG_F32_sdwa_vi:
    case AMDGPU::V_CMP_NLT_F16_sdwa_vi:
    case AMDGPU::V_CMP_NLT_F32_sdwa_vi:
    case AMDGPU::V_CMP_O_F16_sdwa_vi:
    case AMDGPU::V_CMP_O_F32_sdwa_vi:
    case AMDGPU::V_CMP_TRU_F16_sdwa_vi:
    case AMDGPU::V_CMP_TRU_F32_sdwa_vi:
    case AMDGPU::V_CMP_U_F16_sdwa_vi:
    case AMDGPU::V_CMP_U_F32_sdwa_vi: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src1_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 56, 3);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 60, 2);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: src1
      op.clearAllBits();
      getSDWASrcEncoding(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_CVT_F16_I16_sdwa_vi:
    case AMDGPU::V_CVT_F16_U16_sdwa_vi:
    case AMDGPU::V_CVT_F32_I32_sdwa_vi:
    case AMDGPU::V_CVT_F32_U32_sdwa_vi:
    case AMDGPU::V_CVT_F32_UBYTE0_sdwa_vi:
    case AMDGPU::V_CVT_F32_UBYTE1_sdwa_vi:
    case AMDGPU::V_CVT_F32_UBYTE2_sdwa_vi:
    case AMDGPU::V_CVT_F32_UBYTE3_sdwa_vi:
    case AMDGPU::V_CVT_OFF_F32_I4_sdwa_vi: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 51, 1);
      // op: dst_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 40, 3);
      // op: dst_unused
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 43, 2);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_CEIL_F16_sdwa_vi:
    case AMDGPU::V_CEIL_F32_sdwa_vi:
    case AMDGPU::V_COS_F16_sdwa_vi:
    case AMDGPU::V_COS_F32_sdwa_vi:
    case AMDGPU::V_CVT_F16_F32_sdwa_vi:
    case AMDGPU::V_CVT_F32_F16_sdwa_vi:
    case AMDGPU::V_EXP_F16_sdwa_vi:
    case AMDGPU::V_EXP_F32_sdwa_vi:
    case AMDGPU::V_EXP_LEGACY_F32_sdwa_vi:
    case AMDGPU::V_FLOOR_F16_sdwa_vi:
    case AMDGPU::V_FLOOR_F32_sdwa_vi:
    case AMDGPU::V_FRACT_F16_sdwa_vi:
    case AMDGPU::V_FRACT_F32_sdwa_vi:
    case AMDGPU::V_FREXP_MANT_F16_sdwa_vi:
    case AMDGPU::V_FREXP_MANT_F32_sdwa_vi:
    case AMDGPU::V_LOG_F16_sdwa_vi:
    case AMDGPU::V_LOG_F32_sdwa_vi:
    case AMDGPU::V_LOG_LEGACY_F32_sdwa_vi:
    case AMDGPU::V_RCP_F16_sdwa_vi:
    case AMDGPU::V_RCP_F32_sdwa_vi:
    case AMDGPU::V_RCP_IFLAG_F32_sdwa_vi:
    case AMDGPU::V_RNDNE_F16_sdwa_vi:
    case AMDGPU::V_RNDNE_F32_sdwa_vi:
    case AMDGPU::V_RSQ_F16_sdwa_vi:
    case AMDGPU::V_RSQ_F32_sdwa_vi:
    case AMDGPU::V_SIN_F16_sdwa_vi:
    case AMDGPU::V_SIN_F32_sdwa_vi:
    case AMDGPU::V_SQRT_F16_sdwa_vi:
    case AMDGPU::V_SQRT_F32_sdwa_vi:
    case AMDGPU::V_TRUNC_F16_sdwa_vi:
    case AMDGPU::V_TRUNC_F32_sdwa_vi: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: dst_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 40, 3);
      // op: dst_unused
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 43, 2);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_ADDC_U32_sdwa_vi:
    case AMDGPU::V_ADD_U16_sdwa_vi:
    case AMDGPU::V_ADD_U32_sdwa_vi:
    case AMDGPU::V_AND_B32_sdwa_vi:
    case AMDGPU::V_ASHRREV_I16_sdwa_vi:
    case AMDGPU::V_ASHRREV_I32_sdwa_vi:
    case AMDGPU::V_LSHLREV_B16_sdwa_vi:
    case AMDGPU::V_LSHLREV_B32_sdwa_vi:
    case AMDGPU::V_LSHRREV_B16_sdwa_vi:
    case AMDGPU::V_LSHRREV_B32_sdwa_vi:
    case AMDGPU::V_MAX_I16_sdwa_vi:
    case AMDGPU::V_MAX_I32_sdwa_vi:
    case AMDGPU::V_MAX_U16_sdwa_vi:
    case AMDGPU::V_MAX_U32_sdwa_vi:
    case AMDGPU::V_MIN_I16_sdwa_vi:
    case AMDGPU::V_MIN_I32_sdwa_vi:
    case AMDGPU::V_MIN_U16_sdwa_vi:
    case AMDGPU::V_MIN_U32_sdwa_vi:
    case AMDGPU::V_MUL_HI_I32_I24_sdwa_vi:
    case AMDGPU::V_MUL_HI_U32_U24_sdwa_vi:
    case AMDGPU::V_MUL_I32_I24_sdwa_vi:
    case AMDGPU::V_MUL_LO_U16_sdwa_vi:
    case AMDGPU::V_MUL_U32_U24_sdwa_vi:
    case AMDGPU::V_OR_B32_sdwa_vi:
    case AMDGPU::V_SUBBREV_U32_sdwa_vi:
    case AMDGPU::V_SUBB_U32_sdwa_vi:
    case AMDGPU::V_SUBREV_U16_sdwa_vi:
    case AMDGPU::V_SUBREV_U32_sdwa_vi:
    case AMDGPU::V_SUB_U16_sdwa_vi:
    case AMDGPU::V_SUB_U32_sdwa_vi:
    case AMDGPU::V_XNOR_B32_sdwa_vi:
    case AMDGPU::V_XOR_B32_sdwa_vi: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 51, 1);
      // op: src1_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 56, 3);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 59, 1);
      // op: dst_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 40, 3);
      // op: dst_unused
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 43, 2);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getSDWASrcEncoding(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_CNDMASK_B32_sdwa_vi: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src1_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 56, 3);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 60, 2);
      // op: dst_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 40, 3);
      // op: dst_unused
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 43, 2);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getSDWASrcEncoding(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_LDEXP_F16_sdwa_vi: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src1_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 56, 3);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 59, 1);
      // op: dst_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 40, 3);
      // op: dst_unused
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 43, 2);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getSDWASrcEncoding(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_ADD_F16_sdwa_vi:
    case AMDGPU::V_ADD_F32_sdwa_vi:
    case AMDGPU::V_MAX_F16_sdwa_vi:
    case AMDGPU::V_MAX_F32_sdwa_vi:
    case AMDGPU::V_MIN_F16_sdwa_vi:
    case AMDGPU::V_MIN_F32_sdwa_vi:
    case AMDGPU::V_MUL_F16_sdwa_vi:
    case AMDGPU::V_MUL_F32_sdwa_vi:
    case AMDGPU::V_MUL_LEGACY_F32_sdwa_vi:
    case AMDGPU::V_SUBREV_F16_sdwa_vi:
    case AMDGPU::V_SUBREV_F32_sdwa_vi:
    case AMDGPU::V_SUB_F16_sdwa_vi:
    case AMDGPU::V_SUB_F32_sdwa_vi: {
      // op: src0
      op.clearAllBits();
      getSDWASrcEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src0_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 48, 3);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src1_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 56, 3);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 60, 2);
      // op: dst_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 40, 3);
      // op: dst_unused
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 43, 2);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getSDWASrcEncoding(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 1), 49, 7);
      break;
    }
    case AMDGPU::V_DUAL_MOV_B32_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_SUB_U32_e32_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 41, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 1), 49, 7);
      break;
    }
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMAAK_F32_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 41, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 1), 49, 7);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(32, 0), 64, 32);
      break;
    }
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMAMK_F32_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 41, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 1), 49, 7);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(32, 0), 64, 32);
      break;
    }
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MOV_B32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      break;
    }
    case AMDGPU::V_DUAL_MOV_B32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_SUB_U32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      break;
    }
    case AMDGPU::V_DUAL_MOV_B32_e32_X_BITOP2_B32_e64_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: bitop3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      break;
    }
    case AMDGPU::V_DUAL_MOV_B32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_SUB_F32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 44, 1);
      // op: vsrc1Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      break;
    }
    case AMDGPU::V_DUAL_MOV_B32_e32_X_CNDMASK_B32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vsrc2Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 44, 1);
      // op: vsrc1Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      break;
    }
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMA_F32_e64_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vsrc2Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 44, 1);
      // op: vsrc1Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vsrc2Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 46, 1);
      break;
    }
    case AMDGPU::V_DUAL_ADD_U32_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_MOV_B32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      break;
    }
    case AMDGPU::V_DUAL_ADD_U32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_SUB_U32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      break;
    }
    case AMDGPU::V_DUAL_ADD_U32_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_BITOP2_B32_e64_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: bitop3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      break;
    }
    case AMDGPU::V_DUAL_ADD_U32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_SUB_F32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 44, 1);
      // op: vsrc1Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      break;
    }
    case AMDGPU::V_DUAL_ADD_U32_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_CNDMASK_B32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vsrc2Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 44, 1);
      // op: vsrc1Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      break;
    }
    case AMDGPU::V_DUAL_ADD_U32_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_FMA_F32_e64_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vsrc2Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 44, 1);
      // op: vsrc1Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vsrc2Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 46, 1);
      break;
    }
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MOV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MOV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MOV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MOV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MOV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MOV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MOV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MOV_B32_e32_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 1), 49, 7);
      break;
    }
    case AMDGPU::V_DUAL_ADD_F32_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_SUB_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_SUB_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_SUB_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_SUB_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_SUB_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_SUB_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_SUB_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_SUB_U32_e32_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 41, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 1), 49, 7);
      break;
    }
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMAAK_F32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMAAK_F32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMAAK_F32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMAAK_F32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMAAK_F32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMAAK_F32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMAAK_F32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMAAK_F32_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 41, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 1), 49, 7);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(32, 0), 64, 32);
      break;
    }
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMAMK_F32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMAMK_F32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMAMK_F32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMAMK_F32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMAMK_F32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMAMK_F32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMAMK_F32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMAMK_F32_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 41, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 1), 49, 7);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(32, 0), 64, 32);
      break;
    }
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MOV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MOV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MOV_B32_e32_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 1), 49, 7);
      break;
    }
    case AMDGPU::V_DUAL_FMAAK_F32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MOV_B32_e32_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 1), 49, 7);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(32, 0), 64, 32);
      break;
    }
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_SUB_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_SUB_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_SUB_U32_e32_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 41, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 1), 49, 7);
      break;
    }
    case AMDGPU::V_DUAL_FMAAK_F32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_SUB_U32_e32_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 41, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 1), 49, 7);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(32, 0), 64, 32);
      break;
    }
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMAAK_F32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMAAK_F32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_FMAAK_F32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMAAK_F32_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 41, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 1), 49, 7);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(32, 0), 64, 32);
      break;
    }
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMAMK_F32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMAMK_F32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_FMAMK_F32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMAMK_F32_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 41, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 1), 49, 7);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(32, 0), 64, 32);
      break;
    }
    case AMDGPU::V_DUAL_FMAMK_F32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MOV_B32_e32_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 1), 49, 7);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(32, 0), 64, 32);
      break;
    }
    case AMDGPU::V_DUAL_FMAMK_F32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_SUB_U32_e32_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 41, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 1), 49, 7);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(32, 0), 64, 32);
      break;
    }
    case AMDGPU::V_DUAL_FMAMK_F32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_FMAAK_F32_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 41, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 1), 49, 7);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(32, 0), 64, 32);
      break;
    }
    case AMDGPU::V_DUAL_FMAMK_F32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_FMAMK_F32_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 41, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 1), 49, 7);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(32, 0), 64, 32);
      break;
    }
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MOV_B32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      break;
    }
    case AMDGPU::V_DUAL_ADD_F32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_SUB_U32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      break;
    }
    case AMDGPU::V_DUAL_ADD_F32_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_BITOP2_B32_e64_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      // op: bitop3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      break;
    }
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MOV_B32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      break;
    }
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_SUB_U32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      break;
    }
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_BITOP2_B32_e64_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      // op: bitop3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      break;
    }
    case AMDGPU::V_DUAL_ADD_F32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_SUB_F32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: src0Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 44, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      // op: vsrc1Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      break;
    }
    case AMDGPU::V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vsrc2Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: src0Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 44, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      // op: vsrc1Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      break;
    }
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMA_F32_e64_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vsrc2Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: src0Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 44, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      // op: vsrc1Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vsrc2Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 46, 1);
      break;
    }
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_SUB_F32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: src0Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 44, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      // op: vsrc1Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      break;
    }
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vsrc2Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: src0Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 44, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      // op: vsrc1Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      break;
    }
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMA_F32_e64_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vsrc2Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: src0Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 44, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      // op: vsrc1Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vsrc2Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 46, 1);
      break;
    }
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MOV_B32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vsrc2X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      break;
    }
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_SUB_U32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vsrc2X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      break;
    }
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_BITOP2_B32_e64_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vsrc2X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      // op: bitop3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      break;
    }
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vsrc2X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: src0Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 44, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      // op: vsrc1Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      break;
    }
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_CNDMASK_B32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vsrc2X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vsrc2Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: src0Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 44, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      // op: vsrc1Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      break;
    }
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMA_F32_e64_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vsrc2X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vsrc2Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: src0Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 44, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      // op: vsrc1Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vsrc2Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 46, 1);
      break;
    }
    case AMDGPU::V_DUAL_FMA_F32_e64_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_MOV_B32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vsrc2X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      // op: vsrc2X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 43, 1);
      break;
    }
    case AMDGPU::V_DUAL_FMA_F32_e64_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_SUB_U32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vsrc2X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      // op: vsrc2X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 43, 1);
      break;
    }
    case AMDGPU::V_DUAL_FMA_F32_e64_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_BITOP2_B32_e64_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vsrc2X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      // op: vsrc2X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 43, 1);
      // op: bitop3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      break;
    }
    case AMDGPU::V_DUAL_FMA_F32_e64_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_SUB_F32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vsrc2X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: src0Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 44, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      // op: vsrc1Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vsrc2X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 43, 1);
      break;
    }
    case AMDGPU::V_DUAL_FMA_F32_e64_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_CNDMASK_B32_e32_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vsrc2X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vsrc2Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: src0Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 44, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      // op: vsrc1Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vsrc2X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 43, 1);
      break;
    }
    case AMDGPU::V_DUAL_FMA_F32_e64_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_FMA_F32_e64_e96_gfx1250: {
      // op: src0X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: vsrc1X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: vsrc2X
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: vdstX
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vsrc1Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vsrc2Y
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vdstY
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: src0X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 41, 1);
      // op: src0Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 44, 1);
      // op: vsrc1X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 42, 1);
      // op: vsrc1Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 45, 1);
      // op: vsrc2X_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 43, 1);
      // op: vsrc2Y_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 46, 1);
      break;
    }
    case AMDGPU::V_CMPX_EQ_F16_e64_gfx10:
    case AMDGPU::V_CMPX_EQ_F32_e64_gfx10:
    case AMDGPU::V_CMPX_EQ_F32_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_F32_e64_gfx12:
    case AMDGPU::V_CMPX_EQ_F64_e64_gfx10:
    case AMDGPU::V_CMPX_EQ_F64_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_F64_e64_gfx12:
    case AMDGPU::V_CMPX_F_F16_e64_gfx10:
    case AMDGPU::V_CMPX_F_F32_e64_gfx10:
    case AMDGPU::V_CMPX_F_F32_e64_gfx11:
    case AMDGPU::V_CMPX_F_F64_e64_gfx10:
    case AMDGPU::V_CMPX_F_F64_e64_gfx11:
    case AMDGPU::V_CMPX_GE_F16_e64_gfx10:
    case AMDGPU::V_CMPX_GE_F32_e64_gfx10:
    case AMDGPU::V_CMPX_GE_F32_e64_gfx11:
    case AMDGPU::V_CMPX_GE_F32_e64_gfx12:
    case AMDGPU::V_CMPX_GE_F64_e64_gfx10:
    case AMDGPU::V_CMPX_GE_F64_e64_gfx11:
    case AMDGPU::V_CMPX_GE_F64_e64_gfx12:
    case AMDGPU::V_CMPX_GT_F16_e64_gfx10:
    case AMDGPU::V_CMPX_GT_F32_e64_gfx10:
    case AMDGPU::V_CMPX_GT_F32_e64_gfx11:
    case AMDGPU::V_CMPX_GT_F32_e64_gfx12:
    case AMDGPU::V_CMPX_GT_F64_e64_gfx10:
    case AMDGPU::V_CMPX_GT_F64_e64_gfx11:
    case AMDGPU::V_CMPX_GT_F64_e64_gfx12:
    case AMDGPU::V_CMPX_LE_F16_e64_gfx10:
    case AMDGPU::V_CMPX_LE_F32_e64_gfx10:
    case AMDGPU::V_CMPX_LE_F32_e64_gfx11:
    case AMDGPU::V_CMPX_LE_F32_e64_gfx12:
    case AMDGPU::V_CMPX_LE_F64_e64_gfx10:
    case AMDGPU::V_CMPX_LE_F64_e64_gfx11:
    case AMDGPU::V_CMPX_LE_F64_e64_gfx12:
    case AMDGPU::V_CMPX_LG_F16_e64_gfx10:
    case AMDGPU::V_CMPX_LG_F32_e64_gfx10:
    case AMDGPU::V_CMPX_LG_F32_e64_gfx11:
    case AMDGPU::V_CMPX_LG_F32_e64_gfx12:
    case AMDGPU::V_CMPX_LG_F64_e64_gfx10:
    case AMDGPU::V_CMPX_LG_F64_e64_gfx11:
    case AMDGPU::V_CMPX_LG_F64_e64_gfx12:
    case AMDGPU::V_CMPX_LT_F16_e64_gfx10:
    case AMDGPU::V_CMPX_LT_F32_e64_gfx10:
    case AMDGPU::V_CMPX_LT_F32_e64_gfx11:
    case AMDGPU::V_CMPX_LT_F32_e64_gfx12:
    case AMDGPU::V_CMPX_LT_F64_e64_gfx10:
    case AMDGPU::V_CMPX_LT_F64_e64_gfx11:
    case AMDGPU::V_CMPX_LT_F64_e64_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_e64_gfx10:
    case AMDGPU::V_CMPX_NEQ_F32_e64_gfx10:
    case AMDGPU::V_CMPX_NEQ_F32_e64_gfx11:
    case AMDGPU::V_CMPX_NEQ_F32_e64_gfx12:
    case AMDGPU::V_CMPX_NEQ_F64_e64_gfx10:
    case AMDGPU::V_CMPX_NEQ_F64_e64_gfx11:
    case AMDGPU::V_CMPX_NEQ_F64_e64_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_e64_gfx10:
    case AMDGPU::V_CMPX_NGE_F32_e64_gfx10:
    case AMDGPU::V_CMPX_NGE_F32_e64_gfx11:
    case AMDGPU::V_CMPX_NGE_F32_e64_gfx12:
    case AMDGPU::V_CMPX_NGE_F64_e64_gfx10:
    case AMDGPU::V_CMPX_NGE_F64_e64_gfx11:
    case AMDGPU::V_CMPX_NGE_F64_e64_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_e64_gfx10:
    case AMDGPU::V_CMPX_NGT_F32_e64_gfx10:
    case AMDGPU::V_CMPX_NGT_F32_e64_gfx11:
    case AMDGPU::V_CMPX_NGT_F32_e64_gfx12:
    case AMDGPU::V_CMPX_NGT_F64_e64_gfx10:
    case AMDGPU::V_CMPX_NGT_F64_e64_gfx11:
    case AMDGPU::V_CMPX_NGT_F64_e64_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_e64_gfx10:
    case AMDGPU::V_CMPX_NLE_F32_e64_gfx10:
    case AMDGPU::V_CMPX_NLE_F32_e64_gfx11:
    case AMDGPU::V_CMPX_NLE_F32_e64_gfx12:
    case AMDGPU::V_CMPX_NLE_F64_e64_gfx10:
    case AMDGPU::V_CMPX_NLE_F64_e64_gfx11:
    case AMDGPU::V_CMPX_NLE_F64_e64_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_e64_gfx10:
    case AMDGPU::V_CMPX_NLG_F32_e64_gfx10:
    case AMDGPU::V_CMPX_NLG_F32_e64_gfx11:
    case AMDGPU::V_CMPX_NLG_F32_e64_gfx12:
    case AMDGPU::V_CMPX_NLG_F64_e64_gfx10:
    case AMDGPU::V_CMPX_NLG_F64_e64_gfx11:
    case AMDGPU::V_CMPX_NLG_F64_e64_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_e64_gfx10:
    case AMDGPU::V_CMPX_NLT_F32_e64_gfx10:
    case AMDGPU::V_CMPX_NLT_F32_e64_gfx11:
    case AMDGPU::V_CMPX_NLT_F32_e64_gfx12:
    case AMDGPU::V_CMPX_NLT_F64_e64_gfx10:
    case AMDGPU::V_CMPX_NLT_F64_e64_gfx11:
    case AMDGPU::V_CMPX_NLT_F64_e64_gfx12:
    case AMDGPU::V_CMPX_O_F16_e64_gfx10:
    case AMDGPU::V_CMPX_O_F32_e64_gfx10:
    case AMDGPU::V_CMPX_O_F32_e64_gfx11:
    case AMDGPU::V_CMPX_O_F32_e64_gfx12:
    case AMDGPU::V_CMPX_O_F64_e64_gfx10:
    case AMDGPU::V_CMPX_O_F64_e64_gfx11:
    case AMDGPU::V_CMPX_O_F64_e64_gfx12:
    case AMDGPU::V_CMPX_TRU_F16_e64_gfx10:
    case AMDGPU::V_CMPX_TRU_F32_e64_gfx10:
    case AMDGPU::V_CMPX_TRU_F64_e64_gfx10:
    case AMDGPU::V_CMPX_T_F32_e64_gfx11:
    case AMDGPU::V_CMPX_T_F64_e64_gfx11:
    case AMDGPU::V_CMPX_U_F16_e64_gfx10:
    case AMDGPU::V_CMPX_U_F32_e64_gfx10:
    case AMDGPU::V_CMPX_U_F32_e64_gfx11:
    case AMDGPU::V_CMPX_U_F32_e64_gfx12:
    case AMDGPU::V_CMPX_U_F64_e64_gfx10:
    case AMDGPU::V_CMPX_U_F64_e64_gfx11:
    case AMDGPU::V_CMPX_U_F64_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_e64_gfx10:
    case AMDGPU::V_CMPX_CLASS_F32_e64_gfx10:
    case AMDGPU::V_CMPX_CLASS_F32_e64_gfx11:
    case AMDGPU::V_CMPX_CLASS_F32_e64_gfx12:
    case AMDGPU::V_CMPX_CLASS_F64_e64_gfx10:
    case AMDGPU::V_CMPX_CLASS_F64_e64_gfx11:
    case AMDGPU::V_CMPX_CLASS_F64_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_CMPX_EQ_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_F_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LG_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LG_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NEQ_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NEQ_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NGE_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NGE_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NGT_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NGT_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NLE_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NLE_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NLG_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NLG_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NLT_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NLT_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_O_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_O_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_T_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F32_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_CMPX_EQ_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_F_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LG_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LG_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NEQ_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NEQ_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGE_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGE_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLE_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLE_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLG_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLG_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_O_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_O_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_T_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_U_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_U_F32_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_CLASS_F32_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_CLASS_F32_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_MFMA_LD_SCALE_B32_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 59, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 60, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      break;
    }
    case AMDGPU::V_CEIL_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CEIL_F64_e64_gfx7:
    case AMDGPU::V_COS_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F16_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_F16_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F64_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_I32_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_I32_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_U32_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_U32_F64_e64_gfx6_gfx7:
    case AMDGPU::V_EXP_F32_e64_gfx6_gfx7:
    case AMDGPU::V_EXP_LEGACY_F32_e64_gfx7:
    case AMDGPU::V_FLOOR_F32_e64_gfx6_gfx7:
    case AMDGPU::V_FLOOR_F64_e64_gfx7:
    case AMDGPU::V_FRACT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_FRACT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_FREXP_EXP_I32_F64_e64_gfx6_gfx7:
    case AMDGPU::V_FREXP_MANT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_FREXP_MANT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_LOG_CLAMP_F32_e64_gfx6_gfx7:
    case AMDGPU::V_LOG_F32_e64_gfx6_gfx7:
    case AMDGPU::V_LOG_LEGACY_F32_e64_gfx7:
    case AMDGPU::V_RCP_CLAMP_F32_e64_gfx6_gfx7:
    case AMDGPU::V_RCP_CLAMP_F64_e64_gfx6_gfx7:
    case AMDGPU::V_RCP_F32_e64_gfx6_gfx7:
    case AMDGPU::V_RCP_F64_e64_gfx6_gfx7:
    case AMDGPU::V_RCP_IFLAG_F32_e64_gfx6_gfx7:
    case AMDGPU::V_RCP_LEGACY_F32_e64_gfx6_gfx7:
    case AMDGPU::V_RNDNE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_RNDNE_F64_e64_gfx7:
    case AMDGPU::V_RSQ_CLAMP_F32_e64_gfx6_gfx7:
    case AMDGPU::V_RSQ_CLAMP_F64_e64_gfx6_gfx7:
    case AMDGPU::V_RSQ_F32_e64_gfx6_gfx7:
    case AMDGPU::V_RSQ_F64_e64_gfx6_gfx7:
    case AMDGPU::V_RSQ_LEGACY_F32_e64_gfx6_gfx7:
    case AMDGPU::V_SIN_F32_e64_gfx6_gfx7:
    case AMDGPU::V_SQRT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_SQRT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_TRUNC_F32_e64_gfx6_gfx7:
    case AMDGPU::V_TRUNC_F64_e64_gfx7: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_FLR_I32_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_RPI_I32_F32_e64_gfx6_gfx7:
    case AMDGPU::V_FREXP_EXP_I32_F32_e64_gfx6_gfx7: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CEIL_F16_e64_gfx10:
    case AMDGPU::V_CEIL_F16_e64_vi:
    case AMDGPU::V_CEIL_F32_e64_gfx10:
    case AMDGPU::V_CEIL_F32_e64_gfx11:
    case AMDGPU::V_CEIL_F32_e64_gfx12:
    case AMDGPU::V_CEIL_F32_e64_vi:
    case AMDGPU::V_CEIL_F64_e64_gfx10:
    case AMDGPU::V_CEIL_F64_e64_gfx11:
    case AMDGPU::V_CEIL_F64_e64_gfx12:
    case AMDGPU::V_CEIL_F64_e64_vi:
    case AMDGPU::V_COS_F16_e64_gfx10:
    case AMDGPU::V_COS_F16_e64_vi:
    case AMDGPU::V_COS_F32_e64_gfx10:
    case AMDGPU::V_COS_F32_e64_gfx11:
    case AMDGPU::V_COS_F32_e64_gfx12:
    case AMDGPU::V_COS_F32_e64_vi:
    case AMDGPU::V_CVT_F16_F32_e64_gfx10:
    case AMDGPU::V_CVT_F16_F32_e64_vi:
    case AMDGPU::V_CVT_F32_BF16_e64_vi:
    case AMDGPU::V_CVT_F32_F16_e64_gfx10:
    case AMDGPU::V_CVT_F32_F16_e64_vi:
    case AMDGPU::V_CVT_F32_F64_e64_gfx10:
    case AMDGPU::V_CVT_F32_F64_e64_gfx11:
    case AMDGPU::V_CVT_F32_F64_e64_gfx12:
    case AMDGPU::V_CVT_F32_F64_e64_vi:
    case AMDGPU::V_CVT_F64_F32_e64_gfx10:
    case AMDGPU::V_CVT_F64_F32_e64_gfx11:
    case AMDGPU::V_CVT_F64_F32_e64_gfx12:
    case AMDGPU::V_CVT_F64_F32_e64_vi:
    case AMDGPU::V_CVT_I16_F16_e64_gfx10:
    case AMDGPU::V_CVT_I16_F16_e64_vi:
    case AMDGPU::V_CVT_I32_F32_e64_gfx10:
    case AMDGPU::V_CVT_I32_F32_e64_gfx11:
    case AMDGPU::V_CVT_I32_F32_e64_gfx12:
    case AMDGPU::V_CVT_I32_F32_e64_vi:
    case AMDGPU::V_CVT_I32_F64_e64_gfx10:
    case AMDGPU::V_CVT_I32_F64_e64_gfx11:
    case AMDGPU::V_CVT_I32_F64_e64_gfx12:
    case AMDGPU::V_CVT_I32_F64_e64_vi:
    case AMDGPU::V_CVT_NORM_I16_F16_e64_gfx10:
    case AMDGPU::V_CVT_NORM_I16_F16_e64_vi:
    case AMDGPU::V_CVT_NORM_U16_F16_e64_gfx10:
    case AMDGPU::V_CVT_NORM_U16_F16_e64_vi:
    case AMDGPU::V_CVT_U16_F16_e64_gfx10:
    case AMDGPU::V_CVT_U16_F16_e64_vi:
    case AMDGPU::V_CVT_U32_F32_e64_gfx10:
    case AMDGPU::V_CVT_U32_F32_e64_gfx11:
    case AMDGPU::V_CVT_U32_F32_e64_gfx12:
    case AMDGPU::V_CVT_U32_F32_e64_vi:
    case AMDGPU::V_CVT_U32_F64_e64_gfx10:
    case AMDGPU::V_CVT_U32_F64_e64_gfx11:
    case AMDGPU::V_CVT_U32_F64_e64_gfx12:
    case AMDGPU::V_CVT_U32_F64_e64_vi:
    case AMDGPU::V_EXP_F16_e64_gfx10:
    case AMDGPU::V_EXP_F16_e64_vi:
    case AMDGPU::V_EXP_F32_e64_gfx10:
    case AMDGPU::V_EXP_F32_e64_gfx11:
    case AMDGPU::V_EXP_F32_e64_gfx12:
    case AMDGPU::V_EXP_F32_e64_vi:
    case AMDGPU::V_EXP_LEGACY_F32_e64_vi:
    case AMDGPU::V_FLOOR_F16_e64_gfx10:
    case AMDGPU::V_FLOOR_F16_e64_vi:
    case AMDGPU::V_FLOOR_F32_e64_gfx10:
    case AMDGPU::V_FLOOR_F32_e64_gfx11:
    case AMDGPU::V_FLOOR_F32_e64_gfx12:
    case AMDGPU::V_FLOOR_F32_e64_vi:
    case AMDGPU::V_FLOOR_F64_e64_gfx10:
    case AMDGPU::V_FLOOR_F64_e64_gfx11:
    case AMDGPU::V_FLOOR_F64_e64_gfx12:
    case AMDGPU::V_FLOOR_F64_e64_vi:
    case AMDGPU::V_FRACT_F16_e64_gfx10:
    case AMDGPU::V_FRACT_F16_e64_vi:
    case AMDGPU::V_FRACT_F32_e64_gfx10:
    case AMDGPU::V_FRACT_F32_e64_gfx11:
    case AMDGPU::V_FRACT_F32_e64_gfx12:
    case AMDGPU::V_FRACT_F32_e64_vi:
    case AMDGPU::V_FRACT_F64_e64_gfx10:
    case AMDGPU::V_FRACT_F64_e64_gfx11:
    case AMDGPU::V_FRACT_F64_e64_gfx12:
    case AMDGPU::V_FRACT_F64_e64_vi:
    case AMDGPU::V_FREXP_EXP_I16_F16_e64_gfx10:
    case AMDGPU::V_FREXP_EXP_I16_F16_e64_vi:
    case AMDGPU::V_FREXP_EXP_I32_F64_e64_gfx10:
    case AMDGPU::V_FREXP_EXP_I32_F64_e64_gfx11:
    case AMDGPU::V_FREXP_EXP_I32_F64_e64_gfx12:
    case AMDGPU::V_FREXP_EXP_I32_F64_e64_vi:
    case AMDGPU::V_FREXP_MANT_F16_e64_gfx10:
    case AMDGPU::V_FREXP_MANT_F16_e64_vi:
    case AMDGPU::V_FREXP_MANT_F32_e64_gfx10:
    case AMDGPU::V_FREXP_MANT_F32_e64_gfx11:
    case AMDGPU::V_FREXP_MANT_F32_e64_gfx12:
    case AMDGPU::V_FREXP_MANT_F32_e64_vi:
    case AMDGPU::V_FREXP_MANT_F64_e64_gfx10:
    case AMDGPU::V_FREXP_MANT_F64_e64_gfx11:
    case AMDGPU::V_FREXP_MANT_F64_e64_gfx12:
    case AMDGPU::V_FREXP_MANT_F64_e64_vi:
    case AMDGPU::V_LOG_F16_e64_gfx10:
    case AMDGPU::V_LOG_F16_e64_vi:
    case AMDGPU::V_LOG_F32_e64_gfx10:
    case AMDGPU::V_LOG_F32_e64_gfx11:
    case AMDGPU::V_LOG_F32_e64_gfx12:
    case AMDGPU::V_LOG_F32_e64_vi:
    case AMDGPU::V_LOG_LEGACY_F32_e64_vi:
    case AMDGPU::V_RCP_F16_e64_gfx10:
    case AMDGPU::V_RCP_F16_e64_vi:
    case AMDGPU::V_RCP_F32_e64_gfx10:
    case AMDGPU::V_RCP_F32_e64_gfx11:
    case AMDGPU::V_RCP_F32_e64_gfx12:
    case AMDGPU::V_RCP_F32_e64_vi:
    case AMDGPU::V_RCP_F64_e64_gfx10:
    case AMDGPU::V_RCP_F64_e64_gfx11:
    case AMDGPU::V_RCP_F64_e64_gfx12:
    case AMDGPU::V_RCP_F64_e64_vi:
    case AMDGPU::V_RCP_IFLAG_F32_e64_gfx10:
    case AMDGPU::V_RCP_IFLAG_F32_e64_gfx11:
    case AMDGPU::V_RCP_IFLAG_F32_e64_gfx12:
    case AMDGPU::V_RCP_IFLAG_F32_e64_vi:
    case AMDGPU::V_RNDNE_F16_e64_gfx10:
    case AMDGPU::V_RNDNE_F16_e64_vi:
    case AMDGPU::V_RNDNE_F32_e64_gfx10:
    case AMDGPU::V_RNDNE_F32_e64_gfx11:
    case AMDGPU::V_RNDNE_F32_e64_gfx12:
    case AMDGPU::V_RNDNE_F32_e64_vi:
    case AMDGPU::V_RNDNE_F64_e64_gfx10:
    case AMDGPU::V_RNDNE_F64_e64_gfx11:
    case AMDGPU::V_RNDNE_F64_e64_gfx12:
    case AMDGPU::V_RNDNE_F64_e64_vi:
    case AMDGPU::V_RSQ_F16_e64_gfx10:
    case AMDGPU::V_RSQ_F16_e64_vi:
    case AMDGPU::V_RSQ_F32_e64_gfx10:
    case AMDGPU::V_RSQ_F32_e64_gfx11:
    case AMDGPU::V_RSQ_F32_e64_gfx12:
    case AMDGPU::V_RSQ_F32_e64_vi:
    case AMDGPU::V_RSQ_F64_e64_gfx10:
    case AMDGPU::V_RSQ_F64_e64_gfx11:
    case AMDGPU::V_RSQ_F64_e64_gfx12:
    case AMDGPU::V_RSQ_F64_e64_vi:
    case AMDGPU::V_SIN_F16_e64_gfx10:
    case AMDGPU::V_SIN_F16_e64_vi:
    case AMDGPU::V_SIN_F32_e64_gfx10:
    case AMDGPU::V_SIN_F32_e64_gfx11:
    case AMDGPU::V_SIN_F32_e64_gfx12:
    case AMDGPU::V_SIN_F32_e64_vi:
    case AMDGPU::V_SQRT_F16_e64_gfx10:
    case AMDGPU::V_SQRT_F16_e64_vi:
    case AMDGPU::V_SQRT_F32_e64_gfx10:
    case AMDGPU::V_SQRT_F32_e64_gfx11:
    case AMDGPU::V_SQRT_F32_e64_gfx12:
    case AMDGPU::V_SQRT_F32_e64_vi:
    case AMDGPU::V_SQRT_F64_e64_gfx10:
    case AMDGPU::V_SQRT_F64_e64_gfx11:
    case AMDGPU::V_SQRT_F64_e64_gfx12:
    case AMDGPU::V_SQRT_F64_e64_vi:
    case AMDGPU::V_S_EXP_F16_e64_gfx12:
    case AMDGPU::V_S_EXP_F32_e64_gfx12:
    case AMDGPU::V_S_LOG_F16_e64_gfx12:
    case AMDGPU::V_S_LOG_F32_e64_gfx12:
    case AMDGPU::V_S_RCP_F16_e64_gfx12:
    case AMDGPU::V_S_RCP_F32_e64_gfx12:
    case AMDGPU::V_S_RSQ_F16_e64_gfx12:
    case AMDGPU::V_S_RSQ_F32_e64_gfx12:
    case AMDGPU::V_S_SQRT_F16_e64_gfx12:
    case AMDGPU::V_S_SQRT_F32_e64_gfx12:
    case AMDGPU::V_TANH_F32_e64_gfx1250:
    case AMDGPU::V_TRUNC_F16_e64_gfx10:
    case AMDGPU::V_TRUNC_F16_e64_vi:
    case AMDGPU::V_TRUNC_F32_e64_gfx10:
    case AMDGPU::V_TRUNC_F32_e64_gfx11:
    case AMDGPU::V_TRUNC_F32_e64_gfx12:
    case AMDGPU::V_TRUNC_F32_e64_vi:
    case AMDGPU::V_TRUNC_F64_e64_gfx10:
    case AMDGPU::V_TRUNC_F64_e64_gfx11:
    case AMDGPU::V_TRUNC_F64_e64_gfx12:
    case AMDGPU::V_TRUNC_F64_e64_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_FLOOR_I32_F32_e64_gfx11:
    case AMDGPU::V_CVT_FLOOR_I32_F32_e64_gfx12:
    case AMDGPU::V_CVT_FLR_I32_F32_e64_gfx10:
    case AMDGPU::V_CVT_FLR_I32_F32_e64_vi:
    case AMDGPU::V_CVT_NEAREST_I32_F32_e64_gfx11:
    case AMDGPU::V_CVT_NEAREST_I32_F32_e64_gfx12:
    case AMDGPU::V_CVT_RPI_I32_F32_e64_gfx10:
    case AMDGPU::V_CVT_RPI_I32_F32_e64_vi:
    case AMDGPU::V_FREXP_EXP_I32_F32_e64_gfx10:
    case AMDGPU::V_FREXP_EXP_I32_F32_e64_gfx11:
    case AMDGPU::V_FREXP_EXP_I32_F32_e64_gfx12:
    case AMDGPU::V_FREXP_EXP_I32_F32_e64_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_e64_vi:
    case AMDGPU::V_CMPX_CLASS_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_CLASS_F32_e64_vi:
    case AMDGPU::V_CMPX_CLASS_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_CLASS_F64_e64_vi:
    case AMDGPU::V_CMP_CLASS_F16_e64_gfx10:
    case AMDGPU::V_CMP_CLASS_F16_e64_vi:
    case AMDGPU::V_CMP_CLASS_F32_e64_gfx10:
    case AMDGPU::V_CMP_CLASS_F32_e64_gfx11:
    case AMDGPU::V_CMP_CLASS_F32_e64_gfx12:
    case AMDGPU::V_CMP_CLASS_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_CLASS_F32_e64_vi:
    case AMDGPU::V_CMP_CLASS_F64_e64_gfx10:
    case AMDGPU::V_CMP_CLASS_F64_e64_gfx11:
    case AMDGPU::V_CMP_CLASS_F64_e64_gfx12:
    case AMDGPU::V_CMP_CLASS_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_CLASS_F64_e64_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_ADD_F32_e64_gfx6_gfx7:
    case AMDGPU::V_ADD_F64_gfx6_gfx7:
    case AMDGPU::V_CVT_PKRTZ_F16_F32_e64_gfx6_gfx7:
    case AMDGPU::V_LDEXP_F32_e64_gfx6_gfx7:
    case AMDGPU::V_LDEXP_F64_gfx6_gfx7:
    case AMDGPU::V_MAX_F32_e64_gfx6_gfx7:
    case AMDGPU::V_MAX_F64_gfx6_gfx7:
    case AMDGPU::V_MAX_LEGACY_F32_e64_gfx6_gfx7:
    case AMDGPU::V_MIN_F32_e64_gfx6_gfx7:
    case AMDGPU::V_MIN_F64_gfx6_gfx7:
    case AMDGPU::V_MIN_LEGACY_F32_e64_gfx6_gfx7:
    case AMDGPU::V_MUL_F32_e64_gfx6_gfx7:
    case AMDGPU::V_MUL_F64_gfx6_gfx7:
    case AMDGPU::V_MUL_LEGACY_F32_e64_gfx6_gfx7:
    case AMDGPU::V_SUBREV_F32_e64_gfx6_gfx7:
    case AMDGPU::V_SUB_F32_e64_gfx6_gfx7:
    case AMDGPU::V_TRIG_PREOP_F64_gfx6_gfx7: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CMPSX_EQ_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_EQ_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_F_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_F_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_GE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_GE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_GT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_GT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LG_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LG_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NEQ_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NEQ_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NGE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NGE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NGT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NGT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLG_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLG_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_O_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_O_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_TRU_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_TRU_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_U_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_U_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_EQ_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_EQ_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_F_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_F_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_GE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_GE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_GT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_GT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_LE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_LE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_LG_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_LG_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_LT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_LT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NEQ_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NEQ_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NGE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NGE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NGT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NGT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLG_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLG_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_O_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_O_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_TRU_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_TRU_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_U_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_U_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LG_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LG_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NEQ_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NEQ_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NGE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NGE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NGT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NGT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLG_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLG_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_O_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_O_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_TRU_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_TRU_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_U_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_U_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_F_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_F_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LG_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LG_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NEQ_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NEQ_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NGE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NGE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NGT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NGT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NLE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NLE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NLG_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NLG_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NLT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NLT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_O_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_O_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_TRU_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_TRU_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_U_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_U_F64_e64_gfx6_gfx7: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_PKACCUM_U8_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_PKNORM_I16_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_PKNORM_U16_F32_e64_gfx6_gfx7: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_ADD_F16_e64_gfx10:
    case AMDGPU::V_ADD_F16_e64_vi:
    case AMDGPU::V_ADD_F32_e64_gfx10:
    case AMDGPU::V_ADD_F32_e64_gfx11:
    case AMDGPU::V_ADD_F32_e64_gfx12:
    case AMDGPU::V_ADD_F32_e64_vi:
    case AMDGPU::V_ADD_F64_e64_gfx11:
    case AMDGPU::V_ADD_F64_e64_gfx12:
    case AMDGPU::V_ADD_F64_gfx10:
    case AMDGPU::V_ADD_F64_vi:
    case AMDGPU::V_CVT_PKRTZ_F16_F32_e64_gfx10:
    case AMDGPU::V_CVT_PKRTZ_F16_F32_e64_vi:
    case AMDGPU::V_CVT_PK_BF16_F32_e64_gfx1250:
    case AMDGPU::V_CVT_PK_F16_F32_e64_gfx1250:
    case AMDGPU::V_CVT_PK_F16_F32_gfx9:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_e64_gfx11:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_e64_gfx12:
    case AMDGPU::V_LDEXP_F16_e64_gfx10:
    case AMDGPU::V_LDEXP_F16_e64_vi:
    case AMDGPU::V_LDEXP_F32_e64_gfx10:
    case AMDGPU::V_LDEXP_F32_e64_gfx11:
    case AMDGPU::V_LDEXP_F32_e64_gfx12:
    case AMDGPU::V_LDEXP_F32_e64_vi:
    case AMDGPU::V_LDEXP_F64_e64_gfx11:
    case AMDGPU::V_LDEXP_F64_e64_gfx12:
    case AMDGPU::V_LDEXP_F64_e64_gfx1250:
    case AMDGPU::V_LDEXP_F64_gfx10:
    case AMDGPU::V_LDEXP_F64_vi:
    case AMDGPU::V_MAXIMUM_F32_e64_gfx12:
    case AMDGPU::V_MAXIMUM_F64_e64_gfx11:
    case AMDGPU::V_MAXIMUM_F64_e64_gfx12:
    case AMDGPU::V_MAX_F16_e64_gfx10:
    case AMDGPU::V_MAX_F16_e64_vi:
    case AMDGPU::V_MAX_F32_e64_gfx10:
    case AMDGPU::V_MAX_F32_e64_gfx11:
    case AMDGPU::V_MAX_F32_e64_vi:
    case AMDGPU::V_MAX_F64_e64_gfx11:
    case AMDGPU::V_MAX_F64_gfx10:
    case AMDGPU::V_MAX_F64_vi:
    case AMDGPU::V_MAX_NUM_F32_e64_gfx12:
    case AMDGPU::V_MAX_NUM_F64_e64_gfx12:
    case AMDGPU::V_MINIMUM_F32_e64_gfx12:
    case AMDGPU::V_MINIMUM_F64_e64_gfx11:
    case AMDGPU::V_MINIMUM_F64_e64_gfx12:
    case AMDGPU::V_MIN_F16_e64_gfx10:
    case AMDGPU::V_MIN_F16_e64_vi:
    case AMDGPU::V_MIN_F32_e64_gfx10:
    case AMDGPU::V_MIN_F32_e64_gfx11:
    case AMDGPU::V_MIN_F32_e64_vi:
    case AMDGPU::V_MIN_F64_e64_gfx11:
    case AMDGPU::V_MIN_F64_gfx10:
    case AMDGPU::V_MIN_F64_vi:
    case AMDGPU::V_MIN_NUM_F32_e64_gfx12:
    case AMDGPU::V_MIN_NUM_F64_e64_gfx12:
    case AMDGPU::V_MUL_DX9_ZERO_F32_e64_gfx11:
    case AMDGPU::V_MUL_DX9_ZERO_F32_e64_gfx12:
    case AMDGPU::V_MUL_F16_e64_gfx10:
    case AMDGPU::V_MUL_F16_e64_vi:
    case AMDGPU::V_MUL_F32_e64_gfx10:
    case AMDGPU::V_MUL_F32_e64_gfx11:
    case AMDGPU::V_MUL_F32_e64_gfx12:
    case AMDGPU::V_MUL_F32_e64_vi:
    case AMDGPU::V_MUL_F64_e64_gfx11:
    case AMDGPU::V_MUL_F64_e64_gfx12:
    case AMDGPU::V_MUL_F64_gfx10:
    case AMDGPU::V_MUL_F64_vi:
    case AMDGPU::V_MUL_LEGACY_F32_e64_gfx10:
    case AMDGPU::V_MUL_LEGACY_F32_e64_gfx90a:
    case AMDGPU::V_MUL_LEGACY_F32_e64_vi:
    case AMDGPU::V_PK_FMAC_F16_e64_gfx9:
    case AMDGPU::V_SUBREV_F16_e64_gfx10:
    case AMDGPU::V_SUBREV_F16_e64_vi:
    case AMDGPU::V_SUBREV_F32_e64_gfx10:
    case AMDGPU::V_SUBREV_F32_e64_gfx11:
    case AMDGPU::V_SUBREV_F32_e64_gfx12:
    case AMDGPU::V_SUBREV_F32_e64_vi:
    case AMDGPU::V_SUB_F16_e64_gfx10:
    case AMDGPU::V_SUB_F16_e64_vi:
    case AMDGPU::V_SUB_F32_e64_gfx10:
    case AMDGPU::V_SUB_F32_e64_gfx11:
    case AMDGPU::V_SUB_F32_e64_gfx12:
    case AMDGPU::V_SUB_F32_e64_vi:
    case AMDGPU::V_TRIG_PREOP_F64_e64_gfx11:
    case AMDGPU::V_TRIG_PREOP_F64_e64_gfx12:
    case AMDGPU::V_TRIG_PREOP_F64_gfx10:
    case AMDGPU::V_TRIG_PREOP_F64_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CMPX_EQ_F16_e64_vi:
    case AMDGPU::V_CMPX_EQ_F32_e64_vi:
    case AMDGPU::V_CMPX_EQ_F64_e64_vi:
    case AMDGPU::V_CMPX_F_F16_e64_vi:
    case AMDGPU::V_CMPX_F_F32_e64_vi:
    case AMDGPU::V_CMPX_F_F64_e64_vi:
    case AMDGPU::V_CMPX_GE_F16_e64_vi:
    case AMDGPU::V_CMPX_GE_F32_e64_vi:
    case AMDGPU::V_CMPX_GE_F64_e64_vi:
    case AMDGPU::V_CMPX_GT_F16_e64_vi:
    case AMDGPU::V_CMPX_GT_F32_e64_vi:
    case AMDGPU::V_CMPX_GT_F64_e64_vi:
    case AMDGPU::V_CMPX_LE_F16_e64_vi:
    case AMDGPU::V_CMPX_LE_F32_e64_vi:
    case AMDGPU::V_CMPX_LE_F64_e64_vi:
    case AMDGPU::V_CMPX_LG_F16_e64_vi:
    case AMDGPU::V_CMPX_LG_F32_e64_vi:
    case AMDGPU::V_CMPX_LG_F64_e64_vi:
    case AMDGPU::V_CMPX_LT_F16_e64_vi:
    case AMDGPU::V_CMPX_LT_F32_e64_vi:
    case AMDGPU::V_CMPX_LT_F64_e64_vi:
    case AMDGPU::V_CMPX_NEQ_F16_e64_vi:
    case AMDGPU::V_CMPX_NEQ_F32_e64_vi:
    case AMDGPU::V_CMPX_NEQ_F64_e64_vi:
    case AMDGPU::V_CMPX_NGE_F16_e64_vi:
    case AMDGPU::V_CMPX_NGE_F32_e64_vi:
    case AMDGPU::V_CMPX_NGE_F64_e64_vi:
    case AMDGPU::V_CMPX_NGT_F16_e64_vi:
    case AMDGPU::V_CMPX_NGT_F32_e64_vi:
    case AMDGPU::V_CMPX_NGT_F64_e64_vi:
    case AMDGPU::V_CMPX_NLE_F16_e64_vi:
    case AMDGPU::V_CMPX_NLE_F32_e64_vi:
    case AMDGPU::V_CMPX_NLE_F64_e64_vi:
    case AMDGPU::V_CMPX_NLG_F16_e64_vi:
    case AMDGPU::V_CMPX_NLG_F32_e64_vi:
    case AMDGPU::V_CMPX_NLG_F64_e64_vi:
    case AMDGPU::V_CMPX_NLT_F16_e64_vi:
    case AMDGPU::V_CMPX_NLT_F32_e64_vi:
    case AMDGPU::V_CMPX_NLT_F64_e64_vi:
    case AMDGPU::V_CMPX_O_F16_e64_vi:
    case AMDGPU::V_CMPX_O_F32_e64_vi:
    case AMDGPU::V_CMPX_O_F64_e64_vi:
    case AMDGPU::V_CMPX_TRU_F16_e64_vi:
    case AMDGPU::V_CMPX_TRU_F32_e64_vi:
    case AMDGPU::V_CMPX_TRU_F64_e64_vi:
    case AMDGPU::V_CMPX_U_F16_e64_vi:
    case AMDGPU::V_CMPX_U_F32_e64_vi:
    case AMDGPU::V_CMPX_U_F64_e64_vi:
    case AMDGPU::V_CMP_EQ_F16_e64_gfx10:
    case AMDGPU::V_CMP_EQ_F16_e64_vi:
    case AMDGPU::V_CMP_EQ_F32_e64_gfx10:
    case AMDGPU::V_CMP_EQ_F32_e64_gfx11:
    case AMDGPU::V_CMP_EQ_F32_e64_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e64_vi:
    case AMDGPU::V_CMP_EQ_F64_e64_gfx10:
    case AMDGPU::V_CMP_EQ_F64_e64_gfx11:
    case AMDGPU::V_CMP_EQ_F64_e64_gfx12:
    case AMDGPU::V_CMP_EQ_F64_e64_vi:
    case AMDGPU::V_CMP_F_F16_e64_gfx10:
    case AMDGPU::V_CMP_F_F16_e64_vi:
    case AMDGPU::V_CMP_F_F32_e64_gfx10:
    case AMDGPU::V_CMP_F_F32_e64_gfx11:
    case AMDGPU::V_CMP_F_F32_e64_vi:
    case AMDGPU::V_CMP_F_F64_e64_gfx10:
    case AMDGPU::V_CMP_F_F64_e64_gfx11:
    case AMDGPU::V_CMP_F_F64_e64_vi:
    case AMDGPU::V_CMP_GE_F16_e64_gfx10:
    case AMDGPU::V_CMP_GE_F16_e64_vi:
    case AMDGPU::V_CMP_GE_F32_e64_gfx10:
    case AMDGPU::V_CMP_GE_F32_e64_gfx11:
    case AMDGPU::V_CMP_GE_F32_e64_gfx12:
    case AMDGPU::V_CMP_GE_F32_e64_vi:
    case AMDGPU::V_CMP_GE_F64_e64_gfx10:
    case AMDGPU::V_CMP_GE_F64_e64_gfx11:
    case AMDGPU::V_CMP_GE_F64_e64_gfx12:
    case AMDGPU::V_CMP_GE_F64_e64_vi:
    case AMDGPU::V_CMP_GT_F16_e64_gfx10:
    case AMDGPU::V_CMP_GT_F16_e64_vi:
    case AMDGPU::V_CMP_GT_F32_e64_gfx10:
    case AMDGPU::V_CMP_GT_F32_e64_gfx11:
    case AMDGPU::V_CMP_GT_F32_e64_gfx12:
    case AMDGPU::V_CMP_GT_F32_e64_vi:
    case AMDGPU::V_CMP_GT_F64_e64_gfx10:
    case AMDGPU::V_CMP_GT_F64_e64_gfx11:
    case AMDGPU::V_CMP_GT_F64_e64_gfx12:
    case AMDGPU::V_CMP_GT_F64_e64_vi:
    case AMDGPU::V_CMP_LE_F16_e64_gfx10:
    case AMDGPU::V_CMP_LE_F16_e64_vi:
    case AMDGPU::V_CMP_LE_F32_e64_gfx10:
    case AMDGPU::V_CMP_LE_F32_e64_gfx11:
    case AMDGPU::V_CMP_LE_F32_e64_gfx12:
    case AMDGPU::V_CMP_LE_F32_e64_vi:
    case AMDGPU::V_CMP_LE_F64_e64_gfx10:
    case AMDGPU::V_CMP_LE_F64_e64_gfx11:
    case AMDGPU::V_CMP_LE_F64_e64_gfx12:
    case AMDGPU::V_CMP_LE_F64_e64_vi:
    case AMDGPU::V_CMP_LG_F16_e64_gfx10:
    case AMDGPU::V_CMP_LG_F16_e64_vi:
    case AMDGPU::V_CMP_LG_F32_e64_gfx10:
    case AMDGPU::V_CMP_LG_F32_e64_gfx11:
    case AMDGPU::V_CMP_LG_F32_e64_gfx12:
    case AMDGPU::V_CMP_LG_F32_e64_vi:
    case AMDGPU::V_CMP_LG_F64_e64_gfx10:
    case AMDGPU::V_CMP_LG_F64_e64_gfx11:
    case AMDGPU::V_CMP_LG_F64_e64_gfx12:
    case AMDGPU::V_CMP_LG_F64_e64_vi:
    case AMDGPU::V_CMP_LT_F16_e64_gfx10:
    case AMDGPU::V_CMP_LT_F16_e64_vi:
    case AMDGPU::V_CMP_LT_F32_e64_gfx10:
    case AMDGPU::V_CMP_LT_F32_e64_gfx11:
    case AMDGPU::V_CMP_LT_F32_e64_gfx12:
    case AMDGPU::V_CMP_LT_F32_e64_vi:
    case AMDGPU::V_CMP_LT_F64_e64_gfx10:
    case AMDGPU::V_CMP_LT_F64_e64_gfx11:
    case AMDGPU::V_CMP_LT_F64_e64_gfx12:
    case AMDGPU::V_CMP_LT_F64_e64_vi:
    case AMDGPU::V_CMP_NEQ_F16_e64_gfx10:
    case AMDGPU::V_CMP_NEQ_F16_e64_vi:
    case AMDGPU::V_CMP_NEQ_F32_e64_gfx10:
    case AMDGPU::V_CMP_NEQ_F32_e64_gfx11:
    case AMDGPU::V_CMP_NEQ_F32_e64_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e64_vi:
    case AMDGPU::V_CMP_NEQ_F64_e64_gfx10:
    case AMDGPU::V_CMP_NEQ_F64_e64_gfx11:
    case AMDGPU::V_CMP_NEQ_F64_e64_gfx12:
    case AMDGPU::V_CMP_NEQ_F64_e64_vi:
    case AMDGPU::V_CMP_NGE_F16_e64_gfx10:
    case AMDGPU::V_CMP_NGE_F16_e64_vi:
    case AMDGPU::V_CMP_NGE_F32_e64_gfx10:
    case AMDGPU::V_CMP_NGE_F32_e64_gfx11:
    case AMDGPU::V_CMP_NGE_F32_e64_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e64_vi:
    case AMDGPU::V_CMP_NGE_F64_e64_gfx10:
    case AMDGPU::V_CMP_NGE_F64_e64_gfx11:
    case AMDGPU::V_CMP_NGE_F64_e64_gfx12:
    case AMDGPU::V_CMP_NGE_F64_e64_vi:
    case AMDGPU::V_CMP_NGT_F16_e64_gfx10:
    case AMDGPU::V_CMP_NGT_F16_e64_vi:
    case AMDGPU::V_CMP_NGT_F32_e64_gfx10:
    case AMDGPU::V_CMP_NGT_F32_e64_gfx11:
    case AMDGPU::V_CMP_NGT_F32_e64_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e64_vi:
    case AMDGPU::V_CMP_NGT_F64_e64_gfx10:
    case AMDGPU::V_CMP_NGT_F64_e64_gfx11:
    case AMDGPU::V_CMP_NGT_F64_e64_gfx12:
    case AMDGPU::V_CMP_NGT_F64_e64_vi:
    case AMDGPU::V_CMP_NLE_F16_e64_gfx10:
    case AMDGPU::V_CMP_NLE_F16_e64_vi:
    case AMDGPU::V_CMP_NLE_F32_e64_gfx10:
    case AMDGPU::V_CMP_NLE_F32_e64_gfx11:
    case AMDGPU::V_CMP_NLE_F32_e64_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e64_vi:
    case AMDGPU::V_CMP_NLE_F64_e64_gfx10:
    case AMDGPU::V_CMP_NLE_F64_e64_gfx11:
    case AMDGPU::V_CMP_NLE_F64_e64_gfx12:
    case AMDGPU::V_CMP_NLE_F64_e64_vi:
    case AMDGPU::V_CMP_NLG_F16_e64_gfx10:
    case AMDGPU::V_CMP_NLG_F16_e64_vi:
    case AMDGPU::V_CMP_NLG_F32_e64_gfx10:
    case AMDGPU::V_CMP_NLG_F32_e64_gfx11:
    case AMDGPU::V_CMP_NLG_F32_e64_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e64_vi:
    case AMDGPU::V_CMP_NLG_F64_e64_gfx10:
    case AMDGPU::V_CMP_NLG_F64_e64_gfx11:
    case AMDGPU::V_CMP_NLG_F64_e64_gfx12:
    case AMDGPU::V_CMP_NLG_F64_e64_vi:
    case AMDGPU::V_CMP_NLT_F16_e64_gfx10:
    case AMDGPU::V_CMP_NLT_F16_e64_vi:
    case AMDGPU::V_CMP_NLT_F32_e64_gfx10:
    case AMDGPU::V_CMP_NLT_F32_e64_gfx11:
    case AMDGPU::V_CMP_NLT_F32_e64_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e64_vi:
    case AMDGPU::V_CMP_NLT_F64_e64_gfx10:
    case AMDGPU::V_CMP_NLT_F64_e64_gfx11:
    case AMDGPU::V_CMP_NLT_F64_e64_gfx12:
    case AMDGPU::V_CMP_NLT_F64_e64_vi:
    case AMDGPU::V_CMP_O_F16_e64_gfx10:
    case AMDGPU::V_CMP_O_F16_e64_vi:
    case AMDGPU::V_CMP_O_F32_e64_gfx10:
    case AMDGPU::V_CMP_O_F32_e64_gfx11:
    case AMDGPU::V_CMP_O_F32_e64_gfx12:
    case AMDGPU::V_CMP_O_F32_e64_vi:
    case AMDGPU::V_CMP_O_F64_e64_gfx10:
    case AMDGPU::V_CMP_O_F64_e64_gfx11:
    case AMDGPU::V_CMP_O_F64_e64_gfx12:
    case AMDGPU::V_CMP_O_F64_e64_vi:
    case AMDGPU::V_CMP_TRU_F16_e64_gfx10:
    case AMDGPU::V_CMP_TRU_F16_e64_vi:
    case AMDGPU::V_CMP_TRU_F32_e64_gfx10:
    case AMDGPU::V_CMP_TRU_F32_e64_vi:
    case AMDGPU::V_CMP_TRU_F64_e64_gfx10:
    case AMDGPU::V_CMP_TRU_F64_e64_vi:
    case AMDGPU::V_CMP_T_F32_e64_gfx11:
    case AMDGPU::V_CMP_T_F64_e64_gfx11:
    case AMDGPU::V_CMP_U_F16_e64_gfx10:
    case AMDGPU::V_CMP_U_F16_e64_vi:
    case AMDGPU::V_CMP_U_F32_e64_gfx10:
    case AMDGPU::V_CMP_U_F32_e64_gfx11:
    case AMDGPU::V_CMP_U_F32_e64_gfx12:
    case AMDGPU::V_CMP_U_F32_e64_vi:
    case AMDGPU::V_CMP_U_F64_e64_gfx10:
    case AMDGPU::V_CMP_U_F64_e64_gfx11:
    case AMDGPU::V_CMP_U_F64_e64_gfx12:
    case AMDGPU::V_CMP_U_F64_e64_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_PKACCUM_U8_F32_e64_vi:
    case AMDGPU::V_CVT_PKNORM_I16_F32_e64_gfx10:
    case AMDGPU::V_CVT_PKNORM_I16_F32_e64_vi:
    case AMDGPU::V_CVT_PKNORM_U16_F32_e64_gfx10:
    case AMDGPU::V_CVT_PKNORM_U16_F32_e64_vi:
    case AMDGPU::V_CVT_PK_I16_F32_e64_gfx11:
    case AMDGPU::V_CVT_PK_I16_F32_e64_gfx12:
    case AMDGPU::V_CVT_PK_NORM_I16_F32_e64_gfx11:
    case AMDGPU::V_CVT_PK_NORM_I16_F32_e64_gfx12:
    case AMDGPU::V_CVT_PK_NORM_U16_F32_e64_gfx11:
    case AMDGPU::V_CVT_PK_NORM_U16_F32_e64_gfx12:
    case AMDGPU::V_CVT_PK_U16_F32_e64_gfx11:
    case AMDGPU::V_CVT_PK_U16_F32_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_SR_FP8_F32_gfx1250_e64_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 13, 2);
      break;
    }
    case AMDGPU::V_MAC_F32_e64_gfx6_gfx7:
    case AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_DOT2C_F32_BF16_e64_vi:
    case AMDGPU::V_DOT2C_F32_F16_e64_vi:
    case AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11:
    case AMDGPU::V_FMAC_F16_e64_gfx10:
    case AMDGPU::V_FMAC_F32_e64_gfx10:
    case AMDGPU::V_FMAC_F32_e64_gfx11:
    case AMDGPU::V_FMAC_F32_e64_gfx12:
    case AMDGPU::V_FMAC_F32_e64_vi:
    case AMDGPU::V_FMAC_F64_e64_gfx12:
    case AMDGPU::V_FMAC_F64_e64_gfx90a:
    case AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10:
    case AMDGPU::V_MAC_F16_e64_vi:
    case AMDGPU::V_MAC_F32_e64_gfx10:
    case AMDGPU::V_MAC_F32_e64_vi:
    case AMDGPU::V_MAC_LEGACY_F32_e64_gfx10: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_DOT2C_I32_I16_e64_vi:
    case AMDGPU::V_DOT4C_I32_I8_e64_vi:
    case AMDGPU::V_DOT8C_I32_I4_e64_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CNDMASK_B32_e64_gfx10:
    case AMDGPU::V_CNDMASK_B32_e64_gfx11:
    case AMDGPU::V_CNDMASK_B32_e64_gfx12:
    case AMDGPU::V_CNDMASK_B32_e64_gfx6_gfx7:
    case AMDGPU::V_CNDMASK_B32_e64_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CUBEID_F32_gfx6_gfx7:
    case AMDGPU::V_CUBEMA_F32_gfx6_gfx7:
    case AMDGPU::V_CUBESC_F32_gfx6_gfx7:
    case AMDGPU::V_CUBETC_F32_gfx6_gfx7:
    case AMDGPU::V_DIV_FIXUP_F32_gfx6_gfx7:
    case AMDGPU::V_DIV_FIXUP_F64_gfx6_gfx7:
    case AMDGPU::V_DIV_FMAS_F32_gfx6_gfx7:
    case AMDGPU::V_DIV_FMAS_F64_gfx6_gfx7:
    case AMDGPU::V_FMA_F32_gfx6_gfx7:
    case AMDGPU::V_FMA_F64_gfx6_gfx7:
    case AMDGPU::V_MAD_F32_gfx6_gfx7:
    case AMDGPU::V_MAD_LEGACY_F32_gfx6_gfx7:
    case AMDGPU::V_MAX3_F32_gfx6_gfx7:
    case AMDGPU::V_MED3_F32_gfx6_gfx7:
    case AMDGPU::V_MIN3_F32_gfx6_gfx7:
    case AMDGPU::V_MULLIT_F32_gfx6_gfx7: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_PK_U8_F32_gfx6_gfx7: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CUBEID_F32_e64_gfx11:
    case AMDGPU::V_CUBEID_F32_e64_gfx12:
    case AMDGPU::V_CUBEID_F32_gfx10:
    case AMDGPU::V_CUBEID_F32_vi:
    case AMDGPU::V_CUBEMA_F32_e64_gfx11:
    case AMDGPU::V_CUBEMA_F32_e64_gfx12:
    case AMDGPU::V_CUBEMA_F32_gfx10:
    case AMDGPU::V_CUBEMA_F32_vi:
    case AMDGPU::V_CUBESC_F32_e64_gfx11:
    case AMDGPU::V_CUBESC_F32_e64_gfx12:
    case AMDGPU::V_CUBESC_F32_gfx10:
    case AMDGPU::V_CUBESC_F32_vi:
    case AMDGPU::V_CUBETC_F32_e64_gfx11:
    case AMDGPU::V_CUBETC_F32_e64_gfx12:
    case AMDGPU::V_CUBETC_F32_gfx10:
    case AMDGPU::V_CUBETC_F32_vi:
    case AMDGPU::V_CVT_SR_PK_BF16_F32_e64_gfx1250:
    case AMDGPU::V_CVT_SR_PK_F16_F32_e64_gfx1250:
    case AMDGPU::V_DIV_FIXUP_F16_vi:
    case AMDGPU::V_DIV_FIXUP_F32_e64_gfx11:
    case AMDGPU::V_DIV_FIXUP_F32_e64_gfx12:
    case AMDGPU::V_DIV_FIXUP_F32_gfx10:
    case AMDGPU::V_DIV_FIXUP_F32_vi:
    case AMDGPU::V_DIV_FIXUP_F64_e64_gfx11:
    case AMDGPU::V_DIV_FIXUP_F64_e64_gfx12:
    case AMDGPU::V_DIV_FIXUP_F64_e64_gfx1250:
    case AMDGPU::V_DIV_FIXUP_F64_gfx10:
    case AMDGPU::V_DIV_FIXUP_F64_vi:
    case AMDGPU::V_DIV_FIXUP_LEGACY_F16_gfx9:
    case AMDGPU::V_DIV_FMAS_F32_e64_gfx11:
    case AMDGPU::V_DIV_FMAS_F32_e64_gfx12:
    case AMDGPU::V_DIV_FMAS_F32_gfx10:
    case AMDGPU::V_DIV_FMAS_F32_vi:
    case AMDGPU::V_DIV_FMAS_F64_e64_gfx11:
    case AMDGPU::V_DIV_FMAS_F64_e64_gfx12:
    case AMDGPU::V_DIV_FMAS_F64_e64_gfx1250:
    case AMDGPU::V_DIV_FMAS_F64_gfx10:
    case AMDGPU::V_DIV_FMAS_F64_vi:
    case AMDGPU::V_FMA_DX9_ZERO_F32_e64_gfx11:
    case AMDGPU::V_FMA_DX9_ZERO_F32_e64_gfx12:
    case AMDGPU::V_FMA_F16_vi:
    case AMDGPU::V_FMA_F32_e64_gfx11:
    case AMDGPU::V_FMA_F32_e64_gfx12:
    case AMDGPU::V_FMA_F32_gfx10:
    case AMDGPU::V_FMA_F32_vi:
    case AMDGPU::V_FMA_F64_e64_gfx11:
    case AMDGPU::V_FMA_F64_e64_gfx12:
    case AMDGPU::V_FMA_F64_e64_gfx1250:
    case AMDGPU::V_FMA_F64_gfx10:
    case AMDGPU::V_FMA_F64_vi:
    case AMDGPU::V_FMA_LEGACY_F16_gfx9:
    case AMDGPU::V_FMA_LEGACY_F32_gfx10:
    case AMDGPU::V_MAD_F16_vi:
    case AMDGPU::V_MAD_F32_gfx10:
    case AMDGPU::V_MAD_F32_vi:
    case AMDGPU::V_MAD_LEGACY_F16_gfx9:
    case AMDGPU::V_MAD_LEGACY_F32_gfx10:
    case AMDGPU::V_MAD_LEGACY_F32_vi:
    case AMDGPU::V_MAX3_F32_e64_gfx11:
    case AMDGPU::V_MAX3_F32_gfx10:
    case AMDGPU::V_MAX3_F32_vi:
    case AMDGPU::V_MAX3_NUM_F32_e64_gfx12:
    case AMDGPU::V_MAXIMUM3_F32_e64_gfx12:
    case AMDGPU::V_MAXIMUM3_F32_vi:
    case AMDGPU::V_MAXIMUMMINIMUM_F32_e64_gfx12:
    case AMDGPU::V_MAXMIN_F32_e64_gfx11:
    case AMDGPU::V_MAXMIN_NUM_F32_e64_gfx12:
    case AMDGPU::V_MED3_F32_e64_gfx11:
    case AMDGPU::V_MED3_F32_gfx10:
    case AMDGPU::V_MED3_F32_vi:
    case AMDGPU::V_MED3_NUM_F32_e64_gfx12:
    case AMDGPU::V_MIN3_F32_e64_gfx11:
    case AMDGPU::V_MIN3_F32_gfx10:
    case AMDGPU::V_MIN3_F32_vi:
    case AMDGPU::V_MIN3_NUM_F32_e64_gfx12:
    case AMDGPU::V_MINIMUM3_F32_e64_gfx12:
    case AMDGPU::V_MINIMUM3_F32_vi:
    case AMDGPU::V_MINIMUMMAXIMUM_F32_e64_gfx12:
    case AMDGPU::V_MINMAX_F32_e64_gfx11:
    case AMDGPU::V_MINMAX_NUM_F32_e64_gfx12:
    case AMDGPU::V_MULLIT_F32_e64_gfx11:
    case AMDGPU::V_MULLIT_F32_e64_gfx12:
    case AMDGPU::V_MULLIT_F32_gfx10: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_PK_U8_F32_e64_gfx11:
    case AMDGPU::V_CVT_PK_U8_F32_e64_gfx12:
    case AMDGPU::V_CVT_PK_U8_F32_gfx10:
    case AMDGPU::V_CVT_PK_U8_F32_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_gfx11:
    case AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_gfx12:
    case AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_gfx11:
    case AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 13, 2);
      break;
    }
    case AMDGPU::V_CMP_CLASS_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_CLASS_F32_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CMP_CLASS_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_CLASS_F32_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CMP_EQ_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_F_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GT_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GT_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LE_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LE_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LG_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LG_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LT_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LT_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NEQ_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NGE_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NGT_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NLE_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NLG_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NLT_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_O_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_O_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_T_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_U_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_U_F32_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CMP_EQ_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_F_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LG_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LG_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NEQ_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NGE_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NGT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NLE_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NLG_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NLT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_O_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_O_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_T_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_U_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_U_F32_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_PK_BF16_F32_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_PKNORM_I16_F16_gfx10:
    case AMDGPU::V_CVT_PKNORM_I16_F16_vi:
    case AMDGPU::V_CVT_PKNORM_U16_F16_gfx10:
    case AMDGPU::V_CVT_PKNORM_U16_F16_vi:
    case AMDGPU::V_PACK_B32_F16_gfx10:
    case AMDGPU::V_PACK_B32_F16_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_DIV_FIXUP_F16_gfx10:
    case AMDGPU::V_DIV_FIXUP_F16_gfx9_gfx9:
    case AMDGPU::V_FMA_F16_gfx10:
    case AMDGPU::V_FMA_F16_gfx9_gfx9:
    case AMDGPU::V_MAD_F16_gfx9_gfx9:
    case AMDGPU::V_MAX3_F16_gfx10:
    case AMDGPU::V_MAX3_F16_vi:
    case AMDGPU::V_MED3_F16_gfx10:
    case AMDGPU::V_MED3_F16_vi:
    case AMDGPU::V_MIN3_F16_gfx10:
    case AMDGPU::V_MIN3_F16_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_ASHR_PK_I8_I32_e64_gfx1250:
    case AMDGPU::V_ASHR_PK_I8_I32_vi:
    case AMDGPU::V_ASHR_PK_U8_I32_e64_gfx1250:
    case AMDGPU::V_ASHR_PK_U8_I32_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_BF8_F32_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_FP4_F32_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_FP8_F32_vi:
    case AMDGPU::V_CVT_SCALEF32_SR_BF8_BF16_vi:
    case AMDGPU::V_CVT_SCALEF32_SR_BF8_F16_vi:
    case AMDGPU::V_CVT_SCALEF32_SR_BF8_F32_vi:
    case AMDGPU::V_CVT_SCALEF32_SR_FP8_BF16_vi:
    case AMDGPU::V_CVT_SCALEF32_SR_FP8_F16_vi:
    case AMDGPU::V_CVT_SCALEF32_SR_FP8_F32_vi:
    case AMDGPU::V_CVT_SCALEF32_SR_PK_FP4_BF16_vi:
    case AMDGPU::V_CVT_SCALEF32_SR_PK_FP4_F16_vi:
    case AMDGPU::V_CVT_SCALEF32_SR_PK_FP4_F32_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_SCALEF32_PK_FP4_BF16_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_FP4_F16_vi:
    case AMDGPU::V_CVT_SR_BF8_F32_vi:
    case AMDGPU::V_CVT_SR_FP8_F32_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_fake16_e64_gfx11:
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_fake16_e64_gfx12:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_fake16_e64_gfx11:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_fake16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_PK_BF8_F32_vi:
    case AMDGPU::V_CVT_PK_FP8_F32_vi:
    case AMDGPU::V_CVT_SCALEF32_F16_BF8_vi:
    case AMDGPU::V_CVT_SCALEF32_F16_FP8_vi:
    case AMDGPU::V_CVT_SCALEF32_F32_BF8_vi:
    case AMDGPU::V_CVT_SCALEF32_F32_FP8_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_BF16_BF8_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_BF16_FP4_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_BF16_FP8_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_BF8_BF16_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_BF8_F16_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_F16_BF8_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_F16_FP4_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_F16_FP8_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_F32_BF8_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_F32_FP4_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_F32_FP8_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_FP8_BF16_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_FP8_F16_vi:
    case AMDGPU::V_CVT_SR_BF16_F32_vi:
    case AMDGPU::V_CVT_SR_F16_F32_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_INTERP_P1_F32_e64_gfx10:
    case AMDGPU::V_INTERP_P2_F32_e64_gfx10: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: attr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 0), 32, 6);
      // op: attrchan
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 38, 2);
      break;
    }
    case AMDGPU::V_INTERP_P1_F32_e64_vi:
    case AMDGPU::V_INTERP_P2_F32_e64_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: attrchan
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 38, 2);
      // op: attr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 0), 32, 6);
      break;
    }
    case AMDGPU::V_INTERP_P1LL_F16_gfx10: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: attr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 0), 32, 6);
      // op: attrchan
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 38, 2);
      // op: high
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      break;
    }
    case AMDGPU::V_INTERP_P1LL_F16_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: attrchan
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 38, 2);
      // op: attr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 0), 32, 6);
      // op: high
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      break;
    }
    case AMDGPU::V_INTERP_P1LV_F16_gfx10: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: attr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 0), 32, 6);
      // op: attrchan
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 38, 2);
      // op: high
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      break;
    }
    case AMDGPU::V_INTERP_P1LV_F16_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: attrchan
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 38, 2);
      // op: attr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 0), 32, 6);
      // op: high
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      break;
    }
    case AMDGPU::V_INTERP_P2_F16_gfx10: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: attr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 0), 32, 6);
      // op: attrchan
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 38, 2);
      // op: high
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      break;
    }
    case AMDGPU::V_INTERP_P2_F16_vi:
    case AMDGPU::V_INTERP_P2_LEGACY_F16_gfx9: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: attrchan
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 38, 2);
      // op: attr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 0), 32, 6);
      // op: high
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      break;
    }
    case AMDGPU::V_INTERP_P2_F16_opsel_gfx9: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: attrchan
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 38, 2);
      // op: attr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 0), 32, 6);
      // op: high
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 40, 1);
      break;
    }
    case AMDGPU::V_ADD_I16_vi:
    case AMDGPU::V_ADD_NC_I16_gfx10:
    case AMDGPU::V_ADD_NC_U16_gfx10:
    case AMDGPU::V_ASHRREV_I16_gfx10:
    case AMDGPU::V_LSHLREV_B16_gfx10:
    case AMDGPU::V_LSHRREV_B16_gfx10:
    case AMDGPU::V_MAX_I16_gfx10:
    case AMDGPU::V_MAX_U16_gfx10:
    case AMDGPU::V_MIN_I16_gfx10:
    case AMDGPU::V_MIN_U16_gfx10:
    case AMDGPU::V_MUL_LO_U16_gfx10:
    case AMDGPU::V_SUB_I16_vi:
    case AMDGPU::V_SUB_NC_I16_gfx10:
    case AMDGPU::V_SUB_NC_U16_gfx10: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_ALIGNBIT_B32_opsel_gfx10:
    case AMDGPU::V_ALIGNBIT_B32_opsel_gfx9:
    case AMDGPU::V_ALIGNBYTE_B32_opsel_gfx10:
    case AMDGPU::V_ALIGNBYTE_B32_opsel_gfx9:
    case AMDGPU::V_MAD_I16_gfx10:
    case AMDGPU::V_MAD_I16_gfx9_gfx9:
    case AMDGPU::V_MAD_I32_I16_gfx10:
    case AMDGPU::V_MAD_I32_I16_vi:
    case AMDGPU::V_MAD_U16_gfx10:
    case AMDGPU::V_MAD_U16_gfx9_gfx9:
    case AMDGPU::V_MAD_U32_U16_gfx10:
    case AMDGPU::V_MAD_U32_U16_vi:
    case AMDGPU::V_MAX3_I16_gfx10:
    case AMDGPU::V_MAX3_I16_vi:
    case AMDGPU::V_MAX3_U16_gfx10:
    case AMDGPU::V_MAX3_U16_vi:
    case AMDGPU::V_MED3_I16_gfx10:
    case AMDGPU::V_MED3_I16_vi:
    case AMDGPU::V_MED3_U16_gfx10:
    case AMDGPU::V_MED3_U16_vi:
    case AMDGPU::V_MIN3_I16_gfx10:
    case AMDGPU::V_MIN3_I16_vi:
    case AMDGPU::V_MIN3_U16_gfx10:
    case AMDGPU::V_MIN3_U16_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_PERMLANE16_B32_e64_gfx11:
    case AMDGPU::V_PERMLANE16_B32_e64_gfx12:
    case AMDGPU::V_PERMLANE16_B32_gfx10:
    case AMDGPU::V_PERMLANEX16_B32_e64_gfx11:
    case AMDGPU::V_PERMLANEX16_B32_e64_gfx12:
    case AMDGPU::V_PERMLANEX16_B32_gfx10: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_BITOP3_B16_gfx9: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: bitop3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 61, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 6), 59, 2);
      Value.insertBits(op.extractBitsAsZExtValue(3, 3), 8, 3);
      break;
    }
    case AMDGPU::V_PERMLANE16_VAR_B32_e64_gfx12:
    case AMDGPU::V_PERMLANEX16_VAR_B32_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_DOT2ACC_F32_F16_dpp_gfx11:
    case AMDGPU::V_DOT2C_F32_F16_dpp_gfx10:
    case AMDGPU::V_DOT4C_I32_I8_dpp_gfx10:
    case AMDGPU::V_DOT8C_I32_I4_dpp_gfx10:
    case AMDGPU::V_FMAC_F16_dpp_gfx10:
    case AMDGPU::V_FMAC_F32_dpp_gfx10:
    case AMDGPU::V_FMAC_F32_dpp_gfx11:
    case AMDGPU::V_FMAC_F32_dpp_gfx12:
    case AMDGPU::V_FMAC_F64_dpp_gfx12:
    case AMDGPU::V_MAC_F32_dpp_gfx10: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 54, 2);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 50, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_DOT2C_F32_BF16_dpp_vi:
    case AMDGPU::V_DOT2C_F32_F16_dpp_vi:
    case AMDGPU::V_DOT2C_I32_I16_dpp_vi:
    case AMDGPU::V_DOT4C_I32_I8_dpp_vi:
    case AMDGPU::V_DOT8C_I32_I4_dpp_vi:
    case AMDGPU::V_FMAC_F32_dpp_vi:
    case AMDGPU::V_FMAC_F64_dpp_gfx90a:
    case AMDGPU::V_MAC_F16_dpp_vi:
    case AMDGPU::V_MAC_F32_dpp_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 54, 2);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_CEIL_F32_e64_dpp_gfx11:
    case AMDGPU::V_CEIL_F32_e64_dpp_gfx12:
    case AMDGPU::V_CEIL_F64_e64_dpp_gfx12:
    case AMDGPU::V_COS_F32_e64_dpp_gfx11:
    case AMDGPU::V_COS_F32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F32_F64_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F64_F32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_I32_F32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_I32_F32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_I32_F64_e64_dpp_gfx12:
    case AMDGPU::V_CVT_U32_F32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_U32_F32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_U32_F64_e64_dpp_gfx12:
    case AMDGPU::V_EXP_F32_e64_dpp_gfx11:
    case AMDGPU::V_EXP_F32_e64_dpp_gfx12:
    case AMDGPU::V_FLOOR_F32_e64_dpp_gfx11:
    case AMDGPU::V_FLOOR_F32_e64_dpp_gfx12:
    case AMDGPU::V_FLOOR_F64_e64_dpp_gfx12:
    case AMDGPU::V_FRACT_F32_e64_dpp_gfx11:
    case AMDGPU::V_FRACT_F32_e64_dpp_gfx12:
    case AMDGPU::V_FRACT_F64_e64_dpp_gfx12:
    case AMDGPU::V_FREXP_EXP_I32_F64_e64_dpp_gfx12:
    case AMDGPU::V_FREXP_MANT_F32_e64_dpp_gfx11:
    case AMDGPU::V_FREXP_MANT_F32_e64_dpp_gfx12:
    case AMDGPU::V_FREXP_MANT_F64_e64_dpp_gfx12:
    case AMDGPU::V_LOG_F32_e64_dpp_gfx11:
    case AMDGPU::V_LOG_F32_e64_dpp_gfx12:
    case AMDGPU::V_RCP_F32_e64_dpp_gfx11:
    case AMDGPU::V_RCP_F32_e64_dpp_gfx12:
    case AMDGPU::V_RCP_IFLAG_F32_e64_dpp_gfx11:
    case AMDGPU::V_RCP_IFLAG_F32_e64_dpp_gfx12:
    case AMDGPU::V_RNDNE_F32_e64_dpp_gfx11:
    case AMDGPU::V_RNDNE_F32_e64_dpp_gfx12:
    case AMDGPU::V_RNDNE_F64_e64_dpp_gfx12:
    case AMDGPU::V_RSQ_F32_e64_dpp_gfx11:
    case AMDGPU::V_RSQ_F32_e64_dpp_gfx12:
    case AMDGPU::V_SIN_F32_e64_dpp_gfx11:
    case AMDGPU::V_SIN_F32_e64_dpp_gfx12:
    case AMDGPU::V_SQRT_F32_e64_dpp_gfx11:
    case AMDGPU::V_SQRT_F32_e64_dpp_gfx12:
    case AMDGPU::V_TANH_F32_e64_dpp_gfx1250:
    case AMDGPU::V_TRUNC_F32_e64_dpp_gfx11:
    case AMDGPU::V_TRUNC_F32_e64_dpp_gfx12:
    case AMDGPU::V_TRUNC_F64_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CEIL_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CEIL_F32_e64_dpp8_gfx12:
    case AMDGPU::V_COS_F32_e64_dpp8_gfx11:
    case AMDGPU::V_COS_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_I32_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_I32_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_U32_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_U32_F32_e64_dpp8_gfx12:
    case AMDGPU::V_EXP_F32_e64_dpp8_gfx11:
    case AMDGPU::V_EXP_F32_e64_dpp8_gfx12:
    case AMDGPU::V_FLOOR_F32_e64_dpp8_gfx11:
    case AMDGPU::V_FLOOR_F32_e64_dpp8_gfx12:
    case AMDGPU::V_FRACT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_FRACT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_FREXP_MANT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_FREXP_MANT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_LOG_F32_e64_dpp8_gfx11:
    case AMDGPU::V_LOG_F32_e64_dpp8_gfx12:
    case AMDGPU::V_RCP_F32_e64_dpp8_gfx11:
    case AMDGPU::V_RCP_F32_e64_dpp8_gfx12:
    case AMDGPU::V_RCP_IFLAG_F32_e64_dpp8_gfx11:
    case AMDGPU::V_RCP_IFLAG_F32_e64_dpp8_gfx12:
    case AMDGPU::V_RNDNE_F32_e64_dpp8_gfx11:
    case AMDGPU::V_RNDNE_F32_e64_dpp8_gfx12:
    case AMDGPU::V_RSQ_F32_e64_dpp8_gfx11:
    case AMDGPU::V_RSQ_F32_e64_dpp8_gfx12:
    case AMDGPU::V_SIN_F32_e64_dpp8_gfx11:
    case AMDGPU::V_SIN_F32_e64_dpp8_gfx12:
    case AMDGPU::V_SQRT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_SQRT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_TANH_F32_e64_dpp8_gfx1250:
    case AMDGPU::V_TRUNC_F32_e64_dpp8_gfx11:
    case AMDGPU::V_TRUNC_F32_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_FLOOR_I32_F32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_FLOOR_I32_F32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_NEAREST_I32_F32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_NEAREST_I32_F32_e64_dpp_gfx12:
    case AMDGPU::V_FREXP_EXP_I32_F32_e64_dpp_gfx11:
    case AMDGPU::V_FREXP_EXP_I32_F32_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_FLOOR_I32_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_FLOOR_I32_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_NEAREST_I32_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_NEAREST_I32_F32_e64_dpp8_gfx12:
    case AMDGPU::V_FREXP_EXP_I32_F32_e64_dpp8_gfx11:
    case AMDGPU::V_FREXP_EXP_I32_F32_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp_gfx11:
    case AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp_gfx12:
    case AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp_gfx11:
    case AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 13, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 13, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_SR_FP8_F32_gfx1250_e64_dpp_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 13, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_SR_FP8_F32_gfx1250_e64_dpp8_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 13, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_ADD_F32_e64_dpp_gfx11:
    case AMDGPU::V_ADD_F32_e64_dpp_gfx12:
    case AMDGPU::V_ADD_F64_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_BF16_F32_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_F16_F32_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_e64_dpp_gfx12:
    case AMDGPU::V_LDEXP_F32_e64_dpp_gfx11:
    case AMDGPU::V_LDEXP_F32_e64_dpp_gfx12:
    case AMDGPU::V_LDEXP_F64_e64_dpp_gfx1250:
    case AMDGPU::V_MAXIMUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MAXIMUM_F64_e64_dpp_gfx11:
    case AMDGPU::V_MAXIMUM_F64_e64_dpp_gfx12:
    case AMDGPU::V_MAX_F32_e64_dpp_gfx11:
    case AMDGPU::V_MAX_NUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MAX_NUM_F64_e64_dpp_gfx12:
    case AMDGPU::V_MINIMUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MINIMUM_F64_e64_dpp_gfx11:
    case AMDGPU::V_MINIMUM_F64_e64_dpp_gfx12:
    case AMDGPU::V_MIN_F32_e64_dpp_gfx11:
    case AMDGPU::V_MIN_NUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MIN_NUM_F64_e64_dpp_gfx12:
    case AMDGPU::V_MUL_DX9_ZERO_F32_e64_dpp_gfx11:
    case AMDGPU::V_MUL_DX9_ZERO_F32_e64_dpp_gfx12:
    case AMDGPU::V_MUL_F32_e64_dpp_gfx11:
    case AMDGPU::V_MUL_F32_e64_dpp_gfx12:
    case AMDGPU::V_MUL_F64_e64_dpp_gfx12:
    case AMDGPU::V_SUBREV_F32_e64_dpp_gfx11:
    case AMDGPU::V_SUBREV_F32_e64_dpp_gfx12:
    case AMDGPU::V_SUB_F32_e64_dpp_gfx11:
    case AMDGPU::V_SUB_F32_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_ADD_F32_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_BF16_F32_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_F16_F32_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_e64_dpp8_gfx12:
    case AMDGPU::V_LDEXP_F32_e64_dpp8_gfx11:
    case AMDGPU::V_LDEXP_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MAXIMUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MAX_F32_e64_dpp8_gfx11:
    case AMDGPU::V_MAX_NUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MINIMUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MIN_F32_e64_dpp8_gfx11:
    case AMDGPU::V_MIN_NUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MUL_DX9_ZERO_F32_e64_dpp8_gfx11:
    case AMDGPU::V_MUL_DX9_ZERO_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MUL_F32_e64_dpp8_gfx11:
    case AMDGPU::V_MUL_F32_e64_dpp8_gfx12:
    case AMDGPU::V_SUBREV_F32_e64_dpp8_gfx11:
    case AMDGPU::V_SUBREV_F32_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_F32_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_F32_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_PK_I16_F32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_I16_F32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_NORM_I16_F32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_NORM_I16_F32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_NORM_U16_F32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_NORM_U16_F32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_U16_F32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_U16_F32_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_PK_I16_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_I16_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_NORM_I16_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_NORM_I16_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_NORM_U16_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_NORM_U16_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_U16_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_U16_F32_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_FMAC_F32_e64_dpp_gfx11:
    case AMDGPU::V_FMAC_F32_e64_dpp_gfx12:
    case AMDGPU::V_FMAC_F64_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_FMAC_F32_e64_dpp8_gfx11:
    case AMDGPU::V_FMAC_F32_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CUBEID_F32_e64_dpp_gfx11:
    case AMDGPU::V_CUBEID_F32_e64_dpp_gfx12:
    case AMDGPU::V_CUBEMA_F32_e64_dpp_gfx11:
    case AMDGPU::V_CUBEMA_F32_e64_dpp_gfx12:
    case AMDGPU::V_CUBESC_F32_e64_dpp_gfx11:
    case AMDGPU::V_CUBESC_F32_e64_dpp_gfx12:
    case AMDGPU::V_CUBETC_F32_e64_dpp_gfx11:
    case AMDGPU::V_CUBETC_F32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_SR_PK_BF16_F32_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_SR_PK_F16_F32_e64_dpp_gfx1250:
    case AMDGPU::V_DIV_FIXUP_F64_e64_dpp_gfx1250:
    case AMDGPU::V_DIV_FMAS_F64_e64_dpp_gfx1250:
    case AMDGPU::V_FMA_F32_e64_dpp_gfx11:
    case AMDGPU::V_FMA_F32_e64_dpp_gfx12:
    case AMDGPU::V_FMA_F64_e64_dpp_gfx1250:
    case AMDGPU::V_MAX3_F32_e64_dpp_gfx11:
    case AMDGPU::V_MAX3_NUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MAXIMUM3_F32_e64_dpp_gfx12:
    case AMDGPU::V_MAXIMUMMINIMUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MAXMIN_F32_e64_dpp_gfx11:
    case AMDGPU::V_MAXMIN_NUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MED3_F32_e64_dpp_gfx11:
    case AMDGPU::V_MED3_NUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MIN3_F32_e64_dpp_gfx11:
    case AMDGPU::V_MIN3_NUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MINIMUM3_F32_e64_dpp_gfx12:
    case AMDGPU::V_MINIMUMMAXIMUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MINMAX_F32_e64_dpp_gfx11:
    case AMDGPU::V_MINMAX_NUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MULLIT_F32_e64_dpp_gfx11:
    case AMDGPU::V_MULLIT_F32_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CUBEID_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CUBEID_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CUBEMA_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CUBEMA_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CUBESC_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CUBESC_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CUBETC_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CUBETC_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_SR_PK_BF16_F32_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_SR_PK_F16_F32_e64_dpp8_gfx1250:
    case AMDGPU::V_FMA_F32_e64_dpp8_gfx11:
    case AMDGPU::V_FMA_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MAX3_F32_e64_dpp8_gfx11:
    case AMDGPU::V_MAX3_NUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MAXIMUM3_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MAXIMUMMINIMUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MAXMIN_F32_e64_dpp8_gfx11:
    case AMDGPU::V_MAXMIN_NUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MED3_F32_e64_dpp8_gfx11:
    case AMDGPU::V_MED3_NUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MIN3_F32_e64_dpp8_gfx11:
    case AMDGPU::V_MIN3_NUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MINIMUM3_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MINIMUMMAXIMUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MINMAX_F32_e64_dpp8_gfx11:
    case AMDGPU::V_MINMAX_NUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MULLIT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_MULLIT_F32_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_PK_U8_F32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_U8_F32_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_PK_U8_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_U8_F32_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CNDMASK_B32_e64_dpp_gfx11:
    case AMDGPU::V_CNDMASK_B32_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CNDMASK_B32_e64_dpp8_gfx11:
    case AMDGPU::V_CNDMASK_B32_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_fake16_e64_dpp_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 11, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_fake16_e64_dpp8_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 11, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_DOT2_BF16_BF16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_DOT2_BF16_BF16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_DOT2_F16_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_DOT2_F16_F16_fake16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_DOT2_BF16_BF16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_DOT2_BF16_BF16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_DOT2_F16_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_DOT2_F16_F16_fake16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_DOT2_BF16_BF16_t16_e64_dpp_gfx11:
    case AMDGPU::V_DOT2_BF16_BF16_t16_e64_dpp_gfx12:
    case AMDGPU::V_DOT2_F16_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_DOT2_F16_F16_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValueT16(MI, 7, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_DOT2_BF16_BF16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_DOT2_BF16_BF16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_DOT2_F16_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_DOT2_F16_F16_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValueT16(MI, 7, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_PK_BF8_F16_gfx1250_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_FP8_F16_gfx1250_fake16_e64_dpp_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_PK_BF8_F16_gfx1250_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_FP8_F16_gfx1250_fake16_e64_dpp8_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_PK_FP8_F32_gfx1250_fake16_e64_dpp_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_PK_FP8_F32_gfx1250_fake16_e64_dpp8_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_ASHR_PK_I8_I32_e64_dpp_gfx1250:
    case AMDGPU::V_ASHR_PK_U8_I32_e64_dpp_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_ASHR_PK_I8_I32_e64_dpp8_gfx1250:
    case AMDGPU::V_ASHR_PK_U8_I32_e64_dpp8_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_fake16_e64_dpp_gfx11:
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_fake16_e64_dpp_gfx12:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_fake16_e64_dpp_gfx11:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_fake16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_fake16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_t16_e64_dpp_gfx11:
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_t16_e64_dpp_gfx12:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_t16_e64_dpp_gfx11:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValueT16(MI, 7, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_t16_e64_dpp8_gfx11:
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_t16_e64_dpp8_gfx12:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_t16_e64_dpp8_gfx11:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValueT16(MI, 7, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_PK_BF8_F32_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_BF8_F32_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_FP8_F32_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_FP8_F32_fake16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_PK_BF8_F32_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_BF8_F32_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_FP8_F32_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_FP8_F32_fake16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_FMA_MIX_F32_BF16_dpp_gfx1250:
    case AMDGPU::V_FMA_MIX_F32_dpp_gfx11:
    case AMDGPU::V_FMA_MIX_F32_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 59, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 60, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 2), 13, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_FMA_MIXHI_BF16_dpp_gfx1250:
    case AMDGPU::V_FMA_MIXHI_F16_dpp_gfx11:
    case AMDGPU::V_FMA_MIXHI_F16_dpp_gfx12:
    case AMDGPU::V_FMA_MIXLO_BF16_dpp_gfx1250:
    case AMDGPU::V_FMA_MIXLO_F16_dpp_gfx11:
    case AMDGPU::V_FMA_MIXLO_F16_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 59, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 60, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 2), 13, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(16), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_DOT2_F32_BF16_dpp_gfx11:
    case AMDGPU::V_DOT2_F32_BF16_dpp_gfx12:
    case AMDGPU::V_DOT2_F32_F16_dpp_gfx11:
    case AMDGPU::V_DOT2_F32_F16_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 59, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 60, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 2), 13, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(16), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(17), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_FMA_MIX_F32_BF16_dpp8_gfx1250:
    case AMDGPU::V_FMA_MIX_F32_dpp8_gfx11:
    case AMDGPU::V_FMA_MIX_F32_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 59, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 60, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 2), 13, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_FMA_MIXHI_BF16_dpp8_gfx1250:
    case AMDGPU::V_FMA_MIXHI_F16_dpp8_gfx11:
    case AMDGPU::V_FMA_MIXHI_F16_dpp8_gfx12:
    case AMDGPU::V_FMA_MIXLO_BF16_dpp8_gfx1250:
    case AMDGPU::V_FMA_MIXLO_F16_dpp8_gfx11:
    case AMDGPU::V_FMA_MIXLO_F16_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 59, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 60, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 2), 13, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_DOT2_F32_BF16_dpp8_gfx11:
    case AMDGPU::V_DOT2_F32_BF16_dpp8_gfx12:
    case AMDGPU::V_DOT2_F32_F16_dpp8_gfx11:
    case AMDGPU::V_DOT2_F32_F16_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 59, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 60, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 2), 13, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CEIL_F16_dpp_gfx10:
    case AMDGPU::V_CEIL_F32_dpp_gfx10:
    case AMDGPU::V_CEIL_F32_dpp_gfx11:
    case AMDGPU::V_CEIL_F32_dpp_gfx12:
    case AMDGPU::V_CEIL_F64_dpp_gfx12:
    case AMDGPU::V_COS_F16_dpp_gfx10:
    case AMDGPU::V_COS_F32_dpp_gfx10:
    case AMDGPU::V_COS_F32_dpp_gfx11:
    case AMDGPU::V_COS_F32_dpp_gfx12:
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_fake16_dpp_gfx1250:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_dpp_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_dpp_gfx12:
    case AMDGPU::V_CVT_F16_F32_dpp_gfx10:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_fake16_dpp_gfx1250:
    case AMDGPU::V_CVT_F32_F16_dpp_gfx10:
    case AMDGPU::V_CVT_F32_F64_dpp_gfx12:
    case AMDGPU::V_CVT_F64_F32_dpp_gfx12:
    case AMDGPU::V_CVT_FLOOR_I32_F32_dpp_gfx11:
    case AMDGPU::V_CVT_FLOOR_I32_F32_dpp_gfx12:
    case AMDGPU::V_CVT_FLR_I32_F32_dpp_gfx10:
    case AMDGPU::V_CVT_I16_F16_dpp_gfx10:
    case AMDGPU::V_CVT_I32_F32_dpp_gfx10:
    case AMDGPU::V_CVT_I32_F32_dpp_gfx11:
    case AMDGPU::V_CVT_I32_F32_dpp_gfx12:
    case AMDGPU::V_CVT_I32_F64_dpp_gfx12:
    case AMDGPU::V_CVT_NEAREST_I32_F32_dpp_gfx11:
    case AMDGPU::V_CVT_NEAREST_I32_F32_dpp_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16_dpp_gfx10:
    case AMDGPU::V_CVT_NORM_U16_F16_dpp_gfx10:
    case AMDGPU::V_CVT_RPI_I32_F32_dpp_gfx10:
    case AMDGPU::V_CVT_U16_F16_dpp_gfx10:
    case AMDGPU::V_CVT_U32_F32_dpp_gfx10:
    case AMDGPU::V_CVT_U32_F32_dpp_gfx11:
    case AMDGPU::V_CVT_U32_F32_dpp_gfx12:
    case AMDGPU::V_CVT_U32_F64_dpp_gfx12:
    case AMDGPU::V_EXP_F16_dpp_gfx10:
    case AMDGPU::V_EXP_F32_dpp_gfx10:
    case AMDGPU::V_EXP_F32_dpp_gfx11:
    case AMDGPU::V_EXP_F32_dpp_gfx12:
    case AMDGPU::V_FLOOR_F16_dpp_gfx10:
    case AMDGPU::V_FLOOR_F32_dpp_gfx10:
    case AMDGPU::V_FLOOR_F32_dpp_gfx11:
    case AMDGPU::V_FLOOR_F32_dpp_gfx12:
    case AMDGPU::V_FLOOR_F64_dpp_gfx12:
    case AMDGPU::V_FRACT_F16_dpp_gfx10:
    case AMDGPU::V_FRACT_F32_dpp_gfx10:
    case AMDGPU::V_FRACT_F32_dpp_gfx11:
    case AMDGPU::V_FRACT_F32_dpp_gfx12:
    case AMDGPU::V_FRACT_F64_dpp_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16_dpp_gfx10:
    case AMDGPU::V_FREXP_EXP_I32_F32_dpp_gfx10:
    case AMDGPU::V_FREXP_EXP_I32_F32_dpp_gfx11:
    case AMDGPU::V_FREXP_EXP_I32_F32_dpp_gfx12:
    case AMDGPU::V_FREXP_EXP_I32_F64_dpp_gfx12:
    case AMDGPU::V_FREXP_MANT_F16_dpp_gfx10:
    case AMDGPU::V_FREXP_MANT_F32_dpp_gfx10:
    case AMDGPU::V_FREXP_MANT_F32_dpp_gfx11:
    case AMDGPU::V_FREXP_MANT_F32_dpp_gfx12:
    case AMDGPU::V_FREXP_MANT_F64_dpp_gfx12:
    case AMDGPU::V_LOG_F16_dpp_gfx10:
    case AMDGPU::V_LOG_F32_dpp_gfx10:
    case AMDGPU::V_LOG_F32_dpp_gfx11:
    case AMDGPU::V_LOG_F32_dpp_gfx12:
    case AMDGPU::V_RCP_F16_dpp_gfx10:
    case AMDGPU::V_RCP_F32_dpp_gfx10:
    case AMDGPU::V_RCP_F32_dpp_gfx11:
    case AMDGPU::V_RCP_F32_dpp_gfx12:
    case AMDGPU::V_RCP_IFLAG_F32_dpp_gfx10:
    case AMDGPU::V_RCP_IFLAG_F32_dpp_gfx11:
    case AMDGPU::V_RCP_IFLAG_F32_dpp_gfx12:
    case AMDGPU::V_RNDNE_F16_dpp_gfx10:
    case AMDGPU::V_RNDNE_F32_dpp_gfx10:
    case AMDGPU::V_RNDNE_F32_dpp_gfx11:
    case AMDGPU::V_RNDNE_F32_dpp_gfx12:
    case AMDGPU::V_RNDNE_F64_dpp_gfx12:
    case AMDGPU::V_RSQ_F16_dpp_gfx10:
    case AMDGPU::V_RSQ_F32_dpp_gfx10:
    case AMDGPU::V_RSQ_F32_dpp_gfx11:
    case AMDGPU::V_RSQ_F32_dpp_gfx12:
    case AMDGPU::V_SIN_F16_dpp_gfx10:
    case AMDGPU::V_SIN_F32_dpp_gfx10:
    case AMDGPU::V_SIN_F32_dpp_gfx11:
    case AMDGPU::V_SIN_F32_dpp_gfx12:
    case AMDGPU::V_SQRT_F16_dpp_gfx10:
    case AMDGPU::V_SQRT_F32_dpp_gfx10:
    case AMDGPU::V_SQRT_F32_dpp_gfx11:
    case AMDGPU::V_SQRT_F32_dpp_gfx12:
    case AMDGPU::V_TANH_F32_dpp_gfx1250:
    case AMDGPU::V_TRUNC_F16_dpp_gfx10:
    case AMDGPU::V_TRUNC_F32_dpp_gfx10:
    case AMDGPU::V_TRUNC_F32_dpp_gfx11:
    case AMDGPU::V_TRUNC_F32_dpp_gfx12:
    case AMDGPU::V_TRUNC_F64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 50, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_t16_dpp_gfx1250:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_dpp_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_dpp_gfx12:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_t16_dpp_gfx1250:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_t16_dpp_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_t16_dpp_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_dpp_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 50, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_CEIL_F16_dpp_vi:
    case AMDGPU::V_CEIL_F32_dpp_vi:
    case AMDGPU::V_CEIL_F64_dpp_vi:
    case AMDGPU::V_COS_F16_dpp_vi:
    case AMDGPU::V_COS_F32_dpp_vi:
    case AMDGPU::V_CVT_F16_F32_dpp_vi:
    case AMDGPU::V_CVT_F32_BF16_dpp_gfx9:
    case AMDGPU::V_CVT_F32_F16_dpp_vi:
    case AMDGPU::V_CVT_F32_F64_dpp_vi:
    case AMDGPU::V_CVT_F64_F32_dpp_vi:
    case AMDGPU::V_CVT_FLR_I32_F32_dpp_vi:
    case AMDGPU::V_CVT_I16_F16_dpp_vi:
    case AMDGPU::V_CVT_I32_F32_dpp_vi:
    case AMDGPU::V_CVT_I32_F64_dpp_vi:
    case AMDGPU::V_CVT_NORM_I16_F16_dpp_vi:
    case AMDGPU::V_CVT_NORM_U16_F16_dpp_vi:
    case AMDGPU::V_CVT_RPI_I32_F32_dpp_vi:
    case AMDGPU::V_CVT_U16_F16_dpp_vi:
    case AMDGPU::V_CVT_U32_F32_dpp_vi:
    case AMDGPU::V_CVT_U32_F64_dpp_vi:
    case AMDGPU::V_EXP_F16_dpp_vi:
    case AMDGPU::V_EXP_F32_dpp_vi:
    case AMDGPU::V_EXP_LEGACY_F32_dpp_vi:
    case AMDGPU::V_FLOOR_F16_dpp_vi:
    case AMDGPU::V_FLOOR_F32_dpp_vi:
    case AMDGPU::V_FLOOR_F64_dpp_vi:
    case AMDGPU::V_FRACT_F16_dpp_vi:
    case AMDGPU::V_FRACT_F32_dpp_vi:
    case AMDGPU::V_FRACT_F64_dpp_vi:
    case AMDGPU::V_FREXP_EXP_I16_F16_dpp_vi:
    case AMDGPU::V_FREXP_EXP_I32_F32_dpp_vi:
    case AMDGPU::V_FREXP_EXP_I32_F64_dpp_vi:
    case AMDGPU::V_FREXP_MANT_F16_dpp_vi:
    case AMDGPU::V_FREXP_MANT_F32_dpp_vi:
    case AMDGPU::V_FREXP_MANT_F64_dpp_vi:
    case AMDGPU::V_LOG_F16_dpp_vi:
    case AMDGPU::V_LOG_F32_dpp_vi:
    case AMDGPU::V_LOG_LEGACY_F32_dpp_vi:
    case AMDGPU::V_RCP_F16_dpp_vi:
    case AMDGPU::V_RCP_F32_dpp_vi:
    case AMDGPU::V_RCP_F64_dpp_vi:
    case AMDGPU::V_RCP_IFLAG_F32_dpp_vi:
    case AMDGPU::V_RNDNE_F16_dpp_vi:
    case AMDGPU::V_RNDNE_F32_dpp_vi:
    case AMDGPU::V_RNDNE_F64_dpp_vi:
    case AMDGPU::V_RSQ_F16_dpp_vi:
    case AMDGPU::V_RSQ_F32_dpp_vi:
    case AMDGPU::V_RSQ_F64_dpp_vi:
    case AMDGPU::V_SIN_F16_dpp_vi:
    case AMDGPU::V_SIN_F32_dpp_vi:
    case AMDGPU::V_SQRT_F16_dpp_vi:
    case AMDGPU::V_SQRT_F32_dpp_vi:
    case AMDGPU::V_SQRT_F64_dpp_vi:
    case AMDGPU::V_TRUNC_F16_dpp_vi:
    case AMDGPU::V_TRUNC_F32_dpp_vi:
    case AMDGPU::V_TRUNC_F64_dpp_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_ADD_F16_dpp_gfx10:
    case AMDGPU::V_ADD_F32_dpp_gfx10:
    case AMDGPU::V_ADD_F32_dpp_gfx11:
    case AMDGPU::V_ADD_F32_dpp_gfx12:
    case AMDGPU::V_ADD_F64_dpp_gfx12:
    case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
    case AMDGPU::V_CNDMASK_B32_dpp_gfx11:
    case AMDGPU::V_CNDMASK_B32_dpp_gfx12:
    case AMDGPU::V_CNDMASK_B32_dpp_w32_gfx10:
    case AMDGPU::V_CNDMASK_B32_dpp_w32_gfx11:
    case AMDGPU::V_CNDMASK_B32_dpp_w32_gfx12:
    case AMDGPU::V_CNDMASK_B32_dpp_w64_gfx10:
    case AMDGPU::V_CNDMASK_B32_dpp_w64_gfx11:
    case AMDGPU::V_CNDMASK_B32_dpp_w64_gfx12:
    case AMDGPU::V_CVT_PKRTZ_F16_F32_dpp_gfx10:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_dpp_gfx11:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_dpp_gfx12:
    case AMDGPU::V_LDEXP_F16_dpp_gfx10:
    case AMDGPU::V_MAX_F16_dpp_gfx10:
    case AMDGPU::V_MAX_F32_dpp_gfx10:
    case AMDGPU::V_MAX_F32_dpp_gfx11:
    case AMDGPU::V_MAX_NUM_F32_dpp_gfx12:
    case AMDGPU::V_MAX_NUM_F64_dpp_gfx12:
    case AMDGPU::V_MIN_F16_dpp_gfx10:
    case AMDGPU::V_MIN_F32_dpp_gfx10:
    case AMDGPU::V_MIN_F32_dpp_gfx11:
    case AMDGPU::V_MIN_NUM_F32_dpp_gfx12:
    case AMDGPU::V_MIN_NUM_F64_dpp_gfx12:
    case AMDGPU::V_MUL_DX9_ZERO_F32_dpp_gfx11:
    case AMDGPU::V_MUL_DX9_ZERO_F32_dpp_gfx12:
    case AMDGPU::V_MUL_F16_dpp_gfx10:
    case AMDGPU::V_MUL_F32_dpp_gfx10:
    case AMDGPU::V_MUL_F32_dpp_gfx11:
    case AMDGPU::V_MUL_F32_dpp_gfx12:
    case AMDGPU::V_MUL_F64_dpp_gfx12:
    case AMDGPU::V_MUL_LEGACY_F32_dpp_gfx10:
    case AMDGPU::V_PK_FMAC_F16_dpp_gfx10:
    case AMDGPU::V_SUBREV_F16_dpp_gfx10:
    case AMDGPU::V_SUBREV_F32_dpp_gfx10:
    case AMDGPU::V_SUBREV_F32_dpp_gfx11:
    case AMDGPU::V_SUBREV_F32_dpp_gfx12:
    case AMDGPU::V_SUB_F16_dpp_gfx10:
    case AMDGPU::V_SUB_F32_dpp_gfx10:
    case AMDGPU::V_SUB_F32_dpp_gfx11:
    case AMDGPU::V_SUB_F32_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 54, 2);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 50, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_ADD_F16_dpp_vi:
    case AMDGPU::V_ADD_F32_dpp_vi:
    case AMDGPU::V_CNDMASK_B32_dpp_vi:
    case AMDGPU::V_LDEXP_F16_dpp_vi:
    case AMDGPU::V_MAX_F16_dpp_vi:
    case AMDGPU::V_MAX_F32_dpp_vi:
    case AMDGPU::V_MIN_F16_dpp_vi:
    case AMDGPU::V_MIN_F32_dpp_vi:
    case AMDGPU::V_MUL_F16_dpp_vi:
    case AMDGPU::V_MUL_F32_dpp_vi:
    case AMDGPU::V_MUL_LEGACY_F32_dpp_vi:
    case AMDGPU::V_PK_FMAC_F16_dpp_gfx9:
    case AMDGPU::V_SUBREV_F16_dpp_vi:
    case AMDGPU::V_SUBREV_F32_dpp_vi:
    case AMDGPU::V_SUB_F16_dpp_vi:
    case AMDGPU::V_SUB_F32_dpp_vi: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 54, 2);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_DIV_SCALE_F64_e64_dpp_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 8, 7);
      break;
    }
    case AMDGPU::V_CMPX_EQ_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_F_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_GT_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_GT_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_LE_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_LE_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_LG_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_LG_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_LT_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_LT_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_O_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_O_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_T_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_CMPX_EQ_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_F_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LG_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LG_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_O_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_O_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_T_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_CMPX_EQ_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_F_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LG_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LG_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_O_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_O_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_T_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_CMPX_EQ_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_F_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_GE_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_GE_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_GT_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_GT_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_LE_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_LE_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_LG_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_LG_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_LT_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_LT_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_O_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_O_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_T_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_U_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_U_F16_t16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_EQ_I16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_GE_I16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_GE_I16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_GE_U16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_GE_U16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_GT_I16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_GT_I16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_GT_U16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_GT_U16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_LE_I16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_LE_I16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_LE_U16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_LE_U16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_LT_I16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_LT_I16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_LT_U16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_LT_U16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_NE_I16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_NE_I16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_NE_U16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_NE_U16_t16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_CMPX_EQ_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_F_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LG_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LG_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_O_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_O_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_T_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F16_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_CMPX_EQ_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_F_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LG_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LG_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_O_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_O_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_T_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_U_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_U_F16_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_U16_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_U16_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_CEIL_F16_fake16_e64_gfx11:
    case AMDGPU::V_CEIL_F16_fake16_e64_gfx12:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_e64_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_e64_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_e64_gfx12:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_e64_gfx12:
    case AMDGPU::V_EXP_F16_fake16_e64_gfx11:
    case AMDGPU::V_EXP_F16_fake16_e64_gfx12:
    case AMDGPU::V_FLOOR_F16_fake16_e64_gfx11:
    case AMDGPU::V_FLOOR_F16_fake16_e64_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_e64_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_e64_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e64_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e64_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e64_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e64_gfx12:
    case AMDGPU::V_LOG_F16_fake16_e64_gfx11:
    case AMDGPU::V_LOG_F16_fake16_e64_gfx12:
    case AMDGPU::V_RCP_F16_fake16_e64_gfx11:
    case AMDGPU::V_RCP_F16_fake16_e64_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_e64_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_e64_gfx12:
    case AMDGPU::V_RSQ_F16_fake16_e64_gfx11:
    case AMDGPU::V_RSQ_F16_fake16_e64_gfx12:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_e64_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_e64_gfx12:
    case AMDGPU::V_SQRT_F16_fake16_e64_gfx11:
    case AMDGPU::V_SQRT_F16_fake16_e64_gfx12:
    case AMDGPU::V_TANH_F16V_TANH_F16_fake16_e64_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_e64_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_LDEXP_F16_fake16_e64_gfx11:
    case AMDGPU::V_LDEXP_F16_fake16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CMP_EQ_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_EQ_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_F_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_GT_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_GT_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_LE_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_LE_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_LG_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_LG_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_LT_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_LT_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_NGE_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_NGE_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_NGT_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_NGT_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_NLE_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_NLE_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_NLG_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_NLG_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_NLT_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_NLT_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_O_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_O_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_T_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CMP_CLASS_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_ADD_F16_fake16_e64_gfx11:
    case AMDGPU::V_ADD_F16_fake16_e64_gfx12:
    case AMDGPU::V_MAX_F16V_MAX_F16_fake16_e64_gfx11:
    case AMDGPU::V_MAX_NUM_F16_fake16_e64_gfx12:
    case AMDGPU::V_MIN_F16V_MIN_F16_fake16_e64_gfx11:
    case AMDGPU::V_MIN_NUM_F16_fake16_e64_gfx12:
    case AMDGPU::V_MUL_F16_fake16_e64_gfx11:
    case AMDGPU::V_MUL_F16_fake16_e64_gfx12:
    case AMDGPU::V_SUBREV_F16_fake16_e64_gfx11:
    case AMDGPU::V_SUBREV_F16_fake16_e64_gfx12:
    case AMDGPU::V_SUB_F16_fake16_e64_gfx11:
    case AMDGPU::V_SUB_F16_fake16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_FMAC_F16_fake16_e64_gfx11:
    case AMDGPU::V_FMAC_F16_fake16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CNDMASK_B16_fake16_e64_gfx11:
    case AMDGPU::V_CNDMASK_B16_fake16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_COS_BF16V_COS_BF16_fake16_e64_gfx1250:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_fake16_e64_gfx1250:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_fake16_e64_gfx1250:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_fake16_e64_gfx1250:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_fake16_e64_gfx1250:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_fake16_e64_gfx1250:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_fake16_e64_gfx1250:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_fake16_e64_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CMP_EQ_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_F_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LE_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LE_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LG_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LG_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NGE_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NGE_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NGT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NGT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NLE_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NLE_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NLG_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NLG_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NLT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NLT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_O_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_O_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_T_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CMP_EQ_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_F_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LG_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LG_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NGE_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NGE_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NGT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NGT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NLE_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NLE_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NLG_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NLG_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NLT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NLT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_O_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_O_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_T_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CMP_CLASS_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CMP_CLASS_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_SR_BF8_F16_fake16_e64_gfx1250:
    case AMDGPU::V_CVT_SR_FP8_F16_fake16_e64_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 13, 2);
      break;
    }
    case AMDGPU::V_CVT_SR_BF8_F16_t16_e64_gfx1250:
    case AMDGPU::V_CVT_SR_FP8_F16_t16_e64_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 13, 2);
      break;
    }
    case AMDGPU::V_CMP_EQ_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_EQ_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_F_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_GT_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_GT_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_LE_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_LE_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_LG_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_LG_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_LT_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_LT_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_NGE_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_NGE_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_NGT_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_NGT_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_NLE_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_NLE_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_NLG_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_NLG_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_NLT_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_NLT_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_O_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_O_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_T_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CMP_CLASS_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_EQ_I16_t16_e64_gfx11:
    case AMDGPU::V_CMP_EQ_I16_t16_e64_gfx12:
    case AMDGPU::V_CMP_EQ_U16_t16_e64_gfx11:
    case AMDGPU::V_CMP_EQ_U16_t16_e64_gfx12:
    case AMDGPU::V_CMP_GE_I16_t16_e64_gfx11:
    case AMDGPU::V_CMP_GE_I16_t16_e64_gfx12:
    case AMDGPU::V_CMP_GE_U16_t16_e64_gfx11:
    case AMDGPU::V_CMP_GE_U16_t16_e64_gfx12:
    case AMDGPU::V_CMP_GT_I16_t16_e64_gfx11:
    case AMDGPU::V_CMP_GT_I16_t16_e64_gfx12:
    case AMDGPU::V_CMP_GT_U16_t16_e64_gfx11:
    case AMDGPU::V_CMP_GT_U16_t16_e64_gfx12:
    case AMDGPU::V_CMP_LE_I16_t16_e64_gfx11:
    case AMDGPU::V_CMP_LE_I16_t16_e64_gfx12:
    case AMDGPU::V_CMP_LE_U16_t16_e64_gfx11:
    case AMDGPU::V_CMP_LE_U16_t16_e64_gfx12:
    case AMDGPU::V_CMP_LT_I16_t16_e64_gfx11:
    case AMDGPU::V_CMP_LT_I16_t16_e64_gfx12:
    case AMDGPU::V_CMP_LT_U16_t16_e64_gfx11:
    case AMDGPU::V_CMP_LT_U16_t16_e64_gfx12:
    case AMDGPU::V_CMP_NE_I16_t16_e64_gfx11:
    case AMDGPU::V_CMP_NE_I16_t16_e64_gfx12:
    case AMDGPU::V_CMP_NE_U16_t16_e64_gfx11:
    case AMDGPU::V_CMP_NE_U16_t16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CMP_EQ_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_F_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LE_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LE_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LG_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LG_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NGE_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NGE_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NGT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NGT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NLE_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NLE_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NLG_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NLG_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NLT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NLT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_O_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_O_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_T_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CMP_EQ_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_F_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LG_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LG_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NGE_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NGE_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NGT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NGT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NLE_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NLE_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NLG_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NLG_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NLT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NLT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_O_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_O_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_T_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CMP_CLASS_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GE_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GE_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GT_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GT_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GT_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GT_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LE_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LE_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LE_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LE_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LT_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LT_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LT_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LT_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NE_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NE_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NE_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NE_U16_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CMP_CLASS_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_U16_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_fake16_e64_gfx1250:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_fake16_e64_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 11, 1);
      break;
    }
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_t16_e64_gfx1250:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_t16_e64_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 11, 1);
      break;
    }
    case AMDGPU::V_CVT_PK_BF8_F16_gfx1250_fake16_e64_gfx1250:
    case AMDGPU::V_CVT_PK_FP8_F16_gfx1250_fake16_e64_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_PK_FP8_F32_gfx1250_fake16_e64_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_PK_BF8_F32_fake16_e64_gfx11:
    case AMDGPU::V_CVT_PK_BF8_F32_fake16_e64_gfx12:
    case AMDGPU::V_CVT_PK_FP8_F32_fake16_e64_gfx11:
    case AMDGPU::V_CVT_PK_FP8_F32_fake16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_MAXIMUM_F16_fake16_e64_gfx12:
    case AMDGPU::V_MINIMUM_F16_fake16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_fake16_e64_gfx11:
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_fake16_e64_gfx12:
    case AMDGPU::V_ADD_NC_U16_fake16_e64_gfx11:
    case AMDGPU::V_ADD_NC_U16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_fake16_e64_gfx12:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_fake16_e64_gfx11:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_fake16_e64_gfx12:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_fake16_e64_gfx11:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_fake16_e64_gfx12:
    case AMDGPU::V_SUB_NC_U16_fake16_e64_gfx11:
    case AMDGPU::V_SUB_NC_U16_fake16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_fake16_e64_gfx11:
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_fake16_e64_gfx12:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_fake16_e64_gfx11:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_fake16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_fake16_e64_gfx11:
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_fake16_e64_gfx12:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_fake16_e64_gfx11:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_fake16_e64_gfx12:
    case AMDGPU::V_MAX3_F16_fake16_e64_gfx11:
    case AMDGPU::V_MAX3_NUM_F16_fake16_e64_gfx12:
    case AMDGPU::V_MAXIMUM3_F16_fake16_e64_gfx12:
    case AMDGPU::V_MAXIMUMMINIMUM_F16_fake16_e64_gfx12:
    case AMDGPU::V_MAXMIN_F16_fake16_e64_gfx11:
    case AMDGPU::V_MAXMIN_NUM_F16_fake16_e64_gfx12:
    case AMDGPU::V_MED3_F16_fake16_e64_gfx11:
    case AMDGPU::V_MED3_NUM_F16_fake16_e64_gfx12:
    case AMDGPU::V_MIN3_F16_fake16_e64_gfx11:
    case AMDGPU::V_MIN3_NUM_F16_fake16_e64_gfx12:
    case AMDGPU::V_MINIMUM3_F16_fake16_e64_gfx12:
    case AMDGPU::V_MINIMUMMAXIMUM_F16_fake16_e64_gfx12:
    case AMDGPU::V_MINMAX_F16_fake16_e64_gfx11:
    case AMDGPU::V_MINMAX_NUM_F16_fake16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_fake16_e64_gfx11:
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_fake16_e64_gfx12:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_fake16_e64_gfx11:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_fake16_e64_gfx12:
    case AMDGPU::V_MAX3_I16_fake16_e64_gfx11:
    case AMDGPU::V_MAX3_I16_fake16_e64_gfx12:
    case AMDGPU::V_MAX3_U16_fake16_e64_gfx11:
    case AMDGPU::V_MAX3_U16_fake16_e64_gfx12:
    case AMDGPU::V_MED3_I16_fake16_e64_gfx11:
    case AMDGPU::V_MED3_I16_fake16_e64_gfx12:
    case AMDGPU::V_MED3_U16V_MED3_U16_fake16_e64_gfx11:
    case AMDGPU::V_MED3_U16V_MED3_U16_fake16_e64_gfx12:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_fake16_e64_gfx11:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_fake16_e64_gfx12:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_fake16_e64_gfx11:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_fake16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_fake16_e64_gfx1250:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_fake16_e64_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_fake16_e64_gfx1250:
    case AMDGPU::V_CVT_PK_F32_BF8_fake16_e64_gfx12:
    case AMDGPU::V_CVT_PK_F32_FP8_fake16_e64_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_BITOP3_B16_gfx1250_fake16_e64_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: bitop3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 61, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 6), 59, 2);
      Value.insertBits(op.extractBitsAsZExtValue(3, 3), 8, 3);
      break;
    }
    case AMDGPU::V_BITOP3_B16_gfx1250_t16_e64_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: bitop3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 61, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 6), 59, 2);
      Value.insertBits(op.extractBitsAsZExtValue(3, 3), 8, 3);
      break;
    }
    case AMDGPU::V_CEIL_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CEIL_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_EXP_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_EXP_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_FLOOR_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_FLOOR_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_LOG_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_LOG_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_RCP_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_RCP_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_RSQ_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_RSQ_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_SQRT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_SQRT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_TANH_F16V_TANH_F16_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CEIL_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CEIL_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_EXP_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_EXP_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_FLOOR_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_FLOOR_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_LOG_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_LOG_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_RCP_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_RCP_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_RSQ_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_RSQ_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_SQRT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_SQRT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_TANH_F16V_TANH_F16_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_ADD_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_ADD_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_LDEXP_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_LDEXP_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAX_F16V_MAX_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAX_NUM_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MIN_F16V_MIN_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MIN_NUM_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MUL_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MUL_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_SUBREV_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_SUBREV_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_SUB_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_SUB_F16_fake16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_ADD_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_LDEXP_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_LDEXP_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX_F16V_MAX_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX_NUM_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN_F16V_MIN_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN_NUM_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MUL_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MUL_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_SUBREV_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_SUBREV_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_F16_fake16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_FMAC_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_FMAC_F16_fake16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_FMAC_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_FMAC_F16_fake16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CNDMASK_B16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CNDMASK_B16_fake16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CNDMASK_B16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CNDMASK_B16_fake16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_COS_BF16V_COS_BF16_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_fake16_e64_dpp_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_COS_BF16V_COS_BF16_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_fake16_e64_dpp8_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_SR_BF8_F16_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_SR_FP8_F16_fake16_e64_dpp_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 13, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_SR_BF8_F16_t16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_SR_FP8_F16_t16_e64_dpp_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 13, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_SR_BF8_F16_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_SR_FP8_F16_fake16_e64_dpp8_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 13, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_SR_BF8_F16_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_SR_FP8_F16_t16_e64_dpp8_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 13, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_t16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_t16_e64_dpp_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 11, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_t16_e64_dpp8_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: byte_sel
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 11, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CEIL_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CEIL_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_COS_F16V_COS_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_EXP_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_EXP_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_FLOOR_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_FLOOR_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_LOG_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_LOG_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_RCP_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_RCP_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_RSQ_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_RSQ_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_SQRT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_SQRT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_TANH_F16V_TANH_F16_t16_e64_dpp_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CEIL_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CEIL_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_COS_F16V_COS_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_EXP_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_EXP_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_FLOOR_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_FLOOR_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_LOG_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_LOG_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_RCP_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_RCP_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_RSQ_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_RSQ_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_SQRT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_SQRT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_TANH_F16V_TANH_F16_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_PK_BF8_F16_gfx1250_t16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_FP8_F16_gfx1250_t16_e64_dpp_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_PK_BF8_F16_gfx1250_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_FP8_F16_gfx1250_t16_e64_dpp8_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_PK_FP8_F32_gfx1250_t16_e64_dpp_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_PK_FP8_F32_gfx1250_t16_e64_dpp8_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_PK_BF8_F32_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_BF8_F32_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_FP8_F32_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_FP8_F32_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_PK_BF8_F32_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_BF8_F32_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_FP8_F32_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_FP8_F32_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_MAXIMUM_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MINIMUM_F16_fake16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_MAXIMUM_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MINIMUM_F16_fake16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_ADD_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_ADD_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_LDEXP_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_LDEXP_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAXIMUM_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAX_F16V_MAX_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAX_NUM_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MINIMUM_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MIN_F16V_MIN_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MIN_NUM_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MUL_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MUL_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_SUBREV_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_SUBREV_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_SUB_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_SUB_F16_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_ADD_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_LDEXP_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_LDEXP_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAXIMUM_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX_F16V_MAX_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX_NUM_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MINIMUM_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN_F16V_MIN_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN_NUM_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MUL_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MUL_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_SUBREV_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_SUBREV_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_F16_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_ADD_NC_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_ADD_NC_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_SUB_NC_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_SUB_NC_U16_fake16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_ADD_NC_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_NC_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_NC_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_NC_U16_fake16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_ADD_NC_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_ADD_NC_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_SUB_NC_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_SUB_NC_U16_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_ADD_NC_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_NC_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_NC_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_NC_U16_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_FMAC_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_FMAC_F16_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_FMAC_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_FMAC_F16_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_fake16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_fake16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_fake16_e64_dpp_gfx11:
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_fake16_e64_dpp_gfx12:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_fake16_e64_dpp_gfx11:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAX3_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAX3_NUM_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAXIMUM3_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAXIMUMMINIMUM_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAXMIN_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAXMIN_NUM_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MED3_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MED3_NUM_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MIN3_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MIN3_NUM_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MINIMUM3_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MINIMUMMAXIMUM_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MINMAX_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MINMAX_NUM_F16_fake16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX3_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX3_NUM_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAXIMUM3_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAXIMUMMINIMUM_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAXMIN_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAXMIN_NUM_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MED3_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MED3_NUM_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN3_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN3_NUM_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MINIMUM3_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MINIMUMMAXIMUM_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MINMAX_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MINMAX_NUM_F16_fake16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_t16_e64_dpp_gfx11:
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_t16_e64_dpp_gfx12:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_t16_e64_dpp_gfx11:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAX3_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAX3_NUM_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAXIMUM3_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAXIMUMMINIMUM_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAXMIN_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAXMIN_NUM_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MED3_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MED3_NUM_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MIN3_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MIN3_NUM_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MINIMUM3_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MINIMUMMAXIMUM_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MINMAX_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MINMAX_NUM_F16_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValueT16(MI, 7, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_t16_e64_dpp8_gfx11:
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_t16_e64_dpp8_gfx12:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_t16_e64_dpp8_gfx11:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX3_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX3_NUM_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAXIMUM3_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAXIMUMMINIMUM_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAXMIN_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAXMIN_NUM_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MED3_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MED3_NUM_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN3_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN3_NUM_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MINIMUM3_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MINIMUMMAXIMUM_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MINMAX_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MINMAX_NUM_F16_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValueT16(MI, 7, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAX3_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAX3_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAX3_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAX3_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MED3_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MED3_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MED3_U16V_MED3_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MED3_U16V_MED3_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_fake16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX3_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX3_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX3_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX3_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MED3_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MED3_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MED3_U16V_MED3_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MED3_U16V_MED3_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_fake16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAX3_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAX3_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAX3_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAX3_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MED3_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MED3_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MED3_U16V_MED3_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MED3_U16V_MED3_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValueT16(MI, 7, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX3_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX3_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX3_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX3_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MED3_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MED3_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MED3_U16V_MED3_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MED3_U16V_MED3_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValueT16(MI, 7, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_AND_B16_t16_e64_dpp_gfx11:
    case AMDGPU::V_AND_B16_t16_e64_dpp_gfx12:
    case AMDGPU::V_ASHRREV_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_ASHRREV_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_LSHLREV_B16_t16_e64_dpp_gfx11:
    case AMDGPU::V_LSHLREV_B16_t16_e64_dpp_gfx12:
    case AMDGPU::V_LSHRREV_B16_t16_e64_dpp_gfx11:
    case AMDGPU::V_LSHRREV_B16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAX_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAX_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAX_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAX_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MIN_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MIN_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MIN_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MIN_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MUL_LO_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MUL_LO_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_OR_B16_t16_e64_dpp_gfx11:
    case AMDGPU::V_OR_B16_t16_e64_dpp_gfx12:
    case AMDGPU::V_XOR_B16_t16_e64_dpp_gfx11:
    case AMDGPU::V_XOR_B16_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_AND_B16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_AND_B16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_ASHRREV_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_ASHRREV_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_LSHLREV_B16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_LSHLREV_B16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_LSHRREV_B16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_LSHRREV_B16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MUL_LO_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MUL_LO_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_OR_B16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_OR_B16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_XOR_B16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_XOR_B16_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CNDMASK_B16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CNDMASK_B16_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CNDMASK_B16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CNDMASK_B16_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_fake16_e64_dpp_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_t16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_t16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_t16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_fake16_e64_dpp8_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_t16_e64_dpp_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_t16_e64_dpp_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e64_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_COS_BF16V_COS_BF16_t16_e64_dpp_gfx1250:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_t16_e64_dpp_gfx1250:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_t16_e64_dpp_gfx1250:
    case AMDGPU::V_MOV_B16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MOV_B16_t16_e64_dpp_gfx12:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_e64_dpp_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_e64_dpp_gfx12:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_t16_e64_dpp_gfx1250:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_t16_e64_dpp_gfx1250:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_t16_e64_dpp_gfx1250:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_t16_e64_dpp_gfx1250:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_t16_e64_dpp_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e64_dpp8_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_COS_BF16V_COS_BF16_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_MOV_B16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MOV_B16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_t16_e64_dpp8_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_BITOP3_B16_gfx1250_fake16_e64_dpp_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: bitop3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 61, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 6), 59, 2);
      Value.insertBits(op.extractBitsAsZExtValue(3, 3), 8, 3);
      break;
    }
    case AMDGPU::V_BITOP3_B16_gfx1250_fake16_e64_dpp8_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: bitop3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 61, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 6), 59, 2);
      Value.insertBits(op.extractBitsAsZExtValue(3, 3), 8, 3);
      break;
    }
    case AMDGPU::V_BITOP3_B16_gfx1250_t16_e64_dpp_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValueT16(MI, 7, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: bitop3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 61, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 6), 59, 2);
      Value.insertBits(op.extractBitsAsZExtValue(3, 3), 8, 3);
      break;
    }
    case AMDGPU::V_BITOP3_B16_gfx1250_t16_e64_dpp8_gfx1250: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValueT16(MI, 7, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: bitop3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 61, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 6), 59, 2);
      Value.insertBits(op.extractBitsAsZExtValue(3, 3), 8, 3);
      break;
    }
    case AMDGPU::V_FMAC_F16_fake16_dpp_gfx11:
    case AMDGPU::V_FMAC_F16_fake16_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 54, 2);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 50, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_FMAC_F16_t16_dpp_gfx11:
    case AMDGPU::V_FMAC_F16_t16_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 54, 2);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 50, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_CEIL_F16_fake16_dpp_gfx11:
    case AMDGPU::V_CEIL_F16_fake16_dpp_gfx12:
    case AMDGPU::V_COS_BF16V_COS_BF16_fake16_dpp_gfx1250:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_dpp_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_dpp_gfx12:
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_fake16_dpp_gfx1250:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_dpp_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_dpp_gfx12:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_dpp_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_dpp_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_dpp_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_dpp_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_dpp_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_dpp_gfx12:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_fake16_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_fake16_dpp_gfx1250:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_dpp_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_dpp_gfx12:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_fake16_dpp_gfx1250:
    case AMDGPU::V_EXP_F16_fake16_dpp_gfx11:
    case AMDGPU::V_EXP_F16_fake16_dpp_gfx12:
    case AMDGPU::V_FLOOR_F16_fake16_dpp_gfx11:
    case AMDGPU::V_FLOOR_F16_fake16_dpp_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_dpp_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_dpp_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_dpp_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_dpp_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_dpp_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_dpp_gfx12:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_fake16_dpp_gfx1250:
    case AMDGPU::V_LOG_F16_fake16_dpp_gfx11:
    case AMDGPU::V_LOG_F16_fake16_dpp_gfx12:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_fake16_dpp_gfx1250:
    case AMDGPU::V_RCP_F16_fake16_dpp_gfx11:
    case AMDGPU::V_RCP_F16_fake16_dpp_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_dpp_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_dpp_gfx12:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_fake16_dpp_gfx1250:
    case AMDGPU::V_RSQ_F16_fake16_dpp_gfx11:
    case AMDGPU::V_RSQ_F16_fake16_dpp_gfx12:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_fake16_dpp_gfx1250:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_dpp_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_dpp_gfx12:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_fake16_dpp_gfx1250:
    case AMDGPU::V_SQRT_F16_fake16_dpp_gfx11:
    case AMDGPU::V_SQRT_F16_fake16_dpp_gfx12:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_fake16_dpp_gfx1250:
    case AMDGPU::V_TANH_F16V_TANH_F16_fake16_dpp_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_dpp_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 50, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_ADD_F16_fake16_dpp_gfx11:
    case AMDGPU::V_ADD_F16_fake16_dpp_gfx12:
    case AMDGPU::V_LDEXP_F16_fake16_dpp_gfx11:
    case AMDGPU::V_LDEXP_F16_fake16_dpp_gfx12:
    case AMDGPU::V_MAX_F16V_MAX_F16_fake16_dpp_gfx11:
    case AMDGPU::V_MAX_NUM_F16_fake16_dpp_gfx12:
    case AMDGPU::V_MIN_F16V_MIN_F16_fake16_dpp_gfx11:
    case AMDGPU::V_MIN_NUM_F16_fake16_dpp_gfx12:
    case AMDGPU::V_MUL_F16_fake16_dpp_gfx11:
    case AMDGPU::V_MUL_F16_fake16_dpp_gfx12:
    case AMDGPU::V_SUBREV_F16_fake16_dpp_gfx11:
    case AMDGPU::V_SUBREV_F16_fake16_dpp_gfx12:
    case AMDGPU::V_SUB_F16_fake16_dpp_gfx11:
    case AMDGPU::V_SUB_F16_fake16_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 54, 2);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 50, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_t16_dpp_gfx1250:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_dpp_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_dpp_gfx12:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_dpp_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_dpp_gfx12:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_t16_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_t16_dpp_gfx1250:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_dpp_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 50, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_CEIL_F16_t16_dpp_gfx11:
    case AMDGPU::V_CEIL_F16_t16_dpp_gfx12:
    case AMDGPU::V_COS_BF16V_COS_BF16_t16_dpp_gfx1250:
    case AMDGPU::V_COS_F16V_COS_F16_t16_dpp_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_t16_dpp_gfx12:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_dpp_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_dpp_gfx12:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_dpp_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_dpp_gfx12:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_dpp_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_dpp_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_dpp_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_dpp_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_dpp_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_dpp_gfx12:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_dpp_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_dpp_gfx12:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_t16_dpp_gfx1250:
    case AMDGPU::V_EXP_F16_t16_dpp_gfx11:
    case AMDGPU::V_EXP_F16_t16_dpp_gfx12:
    case AMDGPU::V_FLOOR_F16_t16_dpp_gfx11:
    case AMDGPU::V_FLOOR_F16_t16_dpp_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_dpp_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_dpp_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_dpp_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_dpp_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_dpp_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_dpp_gfx12:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_t16_dpp_gfx1250:
    case AMDGPU::V_LOG_F16_t16_dpp_gfx11:
    case AMDGPU::V_LOG_F16_t16_dpp_gfx12:
    case AMDGPU::V_MOV_B16_t16_dpp_gfx11:
    case AMDGPU::V_MOV_B16_t16_dpp_gfx12:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_dpp_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_dpp_gfx12:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_t16_dpp_gfx1250:
    case AMDGPU::V_RCP_F16_t16_dpp_gfx11:
    case AMDGPU::V_RCP_F16_t16_dpp_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_dpp_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_dpp_gfx12:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_t16_dpp_gfx1250:
    case AMDGPU::V_RSQ_F16_t16_dpp_gfx11:
    case AMDGPU::V_RSQ_F16_t16_dpp_gfx12:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_t16_dpp_gfx1250:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_dpp_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_dpp_gfx12:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_t16_dpp_gfx1250:
    case AMDGPU::V_SQRT_F16_t16_dpp_gfx11:
    case AMDGPU::V_SQRT_F16_t16_dpp_gfx12:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_t16_dpp_gfx1250:
    case AMDGPU::V_TANH_F16V_TANH_F16_t16_dpp_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_dpp_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 50, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      break;
    }
    case AMDGPU::V_ADD_F16_t16_dpp_gfx11:
    case AMDGPU::V_ADD_F16_t16_dpp_gfx12:
    case AMDGPU::V_LDEXP_F16_t16_dpp_gfx11:
    case AMDGPU::V_LDEXP_F16_t16_dpp_gfx12:
    case AMDGPU::V_MAX_F16V_MAX_F16_t16_dpp_gfx11:
    case AMDGPU::V_MAX_NUM_F16_t16_dpp_gfx12:
    case AMDGPU::V_MIN_F16V_MIN_F16_t16_dpp_gfx11:
    case AMDGPU::V_MIN_NUM_F16_t16_dpp_gfx12:
    case AMDGPU::V_MUL_F16_t16_dpp_gfx11:
    case AMDGPU::V_MUL_F16_t16_dpp_gfx12:
    case AMDGPU::V_SUBREV_F16_t16_dpp_gfx11:
    case AMDGPU::V_SUBREV_F16_t16_dpp_gfx12:
    case AMDGPU::V_SUB_F16_t16_dpp_gfx11:
    case AMDGPU::V_SUB_F16_t16_dpp_gfx12: {
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 54, 2);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 50, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_CMPX_EQ_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_F_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_F_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_T_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_T_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_F_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_F_I32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_F_I32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_F_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_F_U32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_F_U32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GE_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_I32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GE_I32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GE_I32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_I32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GE_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_U32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GE_U32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GE_U32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_U32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GT_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_I32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GT_I32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GT_I32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GT_I32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GT_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_U32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GT_U32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GT_U32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GT_U32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LE_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_I32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LE_I32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LE_I32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LE_I32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LE_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_U32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LE_U32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LE_U32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LE_U32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LT_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_I32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LT_I32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LT_I32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LT_I32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LT_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_U32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LT_U32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LT_U32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LT_U32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NE_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_I32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NE_I32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NE_I32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NE_I32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NE_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_U32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NE_U32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NE_U32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NE_U32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_T_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_T_I32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_T_I32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_T_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_T_U32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_T_U32_e32_dpp8_w64_gfx11: {
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 40, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      break;
    }
    case AMDGPU::V_CMPX_EQ_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_F_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_F_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_T_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_T_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_F_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_F_I32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_F_I32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_F_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_F_U32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_F_U32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GE_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GE_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GE_I32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GE_I32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GE_I32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_I32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GE_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GE_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GE_U32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GE_U32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GE_U32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_U32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GT_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GT_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GT_I32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GT_I32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GT_I32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GT_I32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GT_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GT_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GT_U32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GT_U32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GT_U32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GT_U32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LE_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LE_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LE_I32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LE_I32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LE_I32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LE_I32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LE_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LE_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LE_U32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LE_U32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LE_U32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LE_U32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LT_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LT_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LT_I32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LT_I32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LT_I32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LT_I32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LT_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LT_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LT_U32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LT_U32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LT_U32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LT_U32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NE_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NE_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NE_I32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NE_I32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NE_I32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NE_I32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NE_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NE_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NE_U32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NE_U32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NE_U32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NE_U32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_T_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_T_I32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_T_I32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_T_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_T_U32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_T_U32_e32_dpp_w64_gfx11: {
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 50, 1);
      break;
    }
    case AMDGPU::V_CMPX_EQ_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_F_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_F_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_T_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_T_U32_e64_dpp_gfx11: {
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_CMPX_EQ_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_F_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_F_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_T_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_T_U32_e64_dpp8_gfx11: {
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      Value = postEncodeVOPCX(MI, Value, STI);
      break;
    }
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp_w64_gfx12: {
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 50, 1);
      break;
    }
    case AMDGPU::V_CMP_EQ_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_F_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_F_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GE_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GE_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GE_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GT_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GT_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GT_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GT_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GT_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GT_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GT_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GT_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LE_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LE_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LE_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LE_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LE_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LE_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LE_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LE_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LT_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LT_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LT_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LT_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LT_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LT_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LT_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LT_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NE_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NE_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NE_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NE_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NE_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NE_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NE_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NE_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_T_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_T_U32_e64_dpp_gfx11: {
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CMP_EQ_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_F_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_F_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_T_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_T_U32_e64_dpp8_gfx11: {
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_CLASS_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_CLASS_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_F_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_F_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LG_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LG_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LG_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LG_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NEQ_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NEQ_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGE_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGE_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGT_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGT_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLE_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLE_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLG_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLG_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLT_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLT_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_O_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_O_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_O_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_O_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_T_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_T_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_U_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_U_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_F_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_F_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_F_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_F_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_F_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_F_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GE_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GE_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GE_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GT_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GT_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GT_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GT_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LE_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LE_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LE_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LE_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LG_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LG_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LG_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LG_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LG_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LG_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LT_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LT_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LT_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LT_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_O_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_O_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_O_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_O_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_O_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_O_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_T_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_T_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_T_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_T_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_T_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_T_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_U_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_U_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_U_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_U_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_U_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_U_F32_e32_dpp8_w64_gfx12: {
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 40, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_CLASS_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_F_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LG_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LG_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NEQ_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NEQ_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NGE_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NGE_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NGT_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NGT_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NLE_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NLE_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NLG_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NLG_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NLT_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NLT_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_O_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_O_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_T_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_F_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_F_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_F_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GE_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GE_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GE_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GE_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GT_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GT_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GT_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GT_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GT_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GT_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LE_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LE_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LE_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LE_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LE_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LE_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LG_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LG_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LG_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LG_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LG_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LG_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LT_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LT_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LT_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LT_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LT_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LT_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_O_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_O_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_O_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_O_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_O_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_O_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_T_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_T_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_T_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_U_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_U_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_U_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_U_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_U_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_U_F32_e32_dpp_w64_gfx12: {
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 54, 2);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 50, 1);
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_F_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LG_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LG_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_O_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_O_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_T_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_F_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_F_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_F_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_T_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_T_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_T_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp_w64_gfx12: {
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 54, 2);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 50, 1);
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_F_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LG_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LG_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_O_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_O_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_T_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_U_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_U_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_F_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_F_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_F_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_T_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_T_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_T_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp8_w64_gfx12: {
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 40, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_F_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LG_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LG_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_O_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_O_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_T_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_F_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_F_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_F_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_T_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_T_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_T_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp_w64_gfx12: {
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 52, 2);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 54, 2);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 40, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 51, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 56, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 60, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 50, 1);
      break;
    }
    case AMDGPU::V_DOT4_F32_BF8_BF8_dpp_gfx12:
    case AMDGPU::V_DOT4_F32_BF8_FP8_dpp_gfx12:
    case AMDGPU::V_DOT4_F32_FP8_BF8_dpp_gfx12:
    case AMDGPU::V_DOT4_F32_FP8_FP8_dpp_gfx12: {
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_DOT4_F32_BF8_BF8_dpp8_gfx12:
    case AMDGPU::V_DOT4_F32_BF8_FP8_dpp8_gfx12:
    case AMDGPU::V_DOT4_F32_FP8_BF8_dpp8_gfx12:
    case AMDGPU::V_DOT4_F32_FP8_FP8_dpp8_gfx12: {
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::GLOBAL_LOAD_LDS_DWORDX3_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_DWORDX3_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_DWORDX4_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_DWORDX4_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_DWORD_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_DWORD_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_SBYTE_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_SBYTE_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_SSHORT_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_SSHORT_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_UBYTE_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_UBYTE_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_USHORT_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_USHORT_vi:
    case AMDGPU::SCRATCH_LOAD_LDS_DWORD_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_DWORD_vi:
    case AMDGPU::SCRATCH_LOAD_LDS_SBYTE_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_SBYTE_vi:
    case AMDGPU::SCRATCH_LOAD_LDS_SSHORT_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_SSHORT_vi:
    case AMDGPU::SCRATCH_LOAD_LDS_UBYTE_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_UBYTE_vi:
    case AMDGPU::SCRATCH_LOAD_LDS_USHORT_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_USHORT_vi: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::GLOBAL_LOAD_LDS_DWORD_gfx10:
    case AMDGPU::GLOBAL_LOAD_LDS_SBYTE_gfx10:
    case AMDGPU::GLOBAL_LOAD_LDS_SSHORT_gfx10:
    case AMDGPU::GLOBAL_LOAD_LDS_UBYTE_gfx10:
    case AMDGPU::GLOBAL_LOAD_LDS_USHORT_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_DWORD_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_SBYTE_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_SSHORT_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_UBYTE_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_USHORT_gfx10: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::SCRATCH_LOAD_LDS_DWORD_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_SBYTE_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_SSHORT_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_UBYTE_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_USHORT_SVS_gfx940: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_F64_vi:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_ci:
    case AMDGPU::FLAT_ATOMIC_ADD_ci:
    case AMDGPU::FLAT_ATOMIC_AND_X2_ci:
    case AMDGPU::FLAT_ATOMIC_AND_ci:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_ci:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_ci:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_ci:
    case AMDGPU::FLAT_ATOMIC_DEC_ci:
    case AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_ci:
    case AMDGPU::FLAT_ATOMIC_FCMPSWAP_ci:
    case AMDGPU::FLAT_ATOMIC_FMAX_X2_ci:
    case AMDGPU::FLAT_ATOMIC_FMAX_ci:
    case AMDGPU::FLAT_ATOMIC_FMIN_X2_ci:
    case AMDGPU::FLAT_ATOMIC_FMIN_ci:
    case AMDGPU::FLAT_ATOMIC_INC_X2_ci:
    case AMDGPU::FLAT_ATOMIC_INC_ci:
    case AMDGPU::FLAT_ATOMIC_MAX_F64_vi:
    case AMDGPU::FLAT_ATOMIC_MIN_F64_vi:
    case AMDGPU::FLAT_ATOMIC_OR_X2_ci:
    case AMDGPU::FLAT_ATOMIC_OR_ci:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_ci:
    case AMDGPU::FLAT_ATOMIC_SMAX_ci:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_ci:
    case AMDGPU::FLAT_ATOMIC_SMIN_ci:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_ci:
    case AMDGPU::FLAT_ATOMIC_SUB_ci:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_ci:
    case AMDGPU::FLAT_ATOMIC_SWAP_ci:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_ci:
    case AMDGPU::FLAT_ATOMIC_UMAX_ci:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_ci:
    case AMDGPU::FLAT_ATOMIC_UMIN_ci:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_ci:
    case AMDGPU::FLAT_ATOMIC_XOR_ci:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_vi:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_vi:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_vi: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_F32_vi:
    case AMDGPU::FLAT_ATOMIC_ADD_F64_gfx940:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_vi:
    case AMDGPU::FLAT_ATOMIC_ADD_vi:
    case AMDGPU::FLAT_ATOMIC_AND_X2_vi:
    case AMDGPU::FLAT_ATOMIC_AND_vi:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_vi:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_vi:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_vi:
    case AMDGPU::FLAT_ATOMIC_DEC_vi:
    case AMDGPU::FLAT_ATOMIC_INC_X2_vi:
    case AMDGPU::FLAT_ATOMIC_INC_vi:
    case AMDGPU::FLAT_ATOMIC_MAX_F64_gfx940:
    case AMDGPU::FLAT_ATOMIC_MIN_F64_gfx940:
    case AMDGPU::FLAT_ATOMIC_OR_X2_vi:
    case AMDGPU::FLAT_ATOMIC_OR_vi:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_BF16_vi:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_F16_vi:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_vi:
    case AMDGPU::FLAT_ATOMIC_SMAX_vi:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_vi:
    case AMDGPU::FLAT_ATOMIC_SMIN_vi:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_vi:
    case AMDGPU::FLAT_ATOMIC_SUB_vi:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_vi:
    case AMDGPU::FLAT_ATOMIC_SWAP_vi:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_vi:
    case AMDGPU::FLAT_ATOMIC_UMAX_vi:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_vi:
    case AMDGPU::FLAT_ATOMIC_UMIN_vi:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_vi:
    case AMDGPU::FLAT_ATOMIC_XOR_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_vi:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_OR_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_vi: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::FLAT_STORE_BYTE_D16_HI_vi:
    case AMDGPU::FLAT_STORE_BYTE_vi:
    case AMDGPU::FLAT_STORE_DWORDX2_vi:
    case AMDGPU::FLAT_STORE_DWORDX3_vi:
    case AMDGPU::FLAT_STORE_DWORDX4_vi:
    case AMDGPU::FLAT_STORE_DWORD_vi:
    case AMDGPU::FLAT_STORE_SHORT_D16_HI_vi:
    case AMDGPU::FLAT_STORE_SHORT_vi:
    case AMDGPU::GLOBAL_STORE_BYTE_D16_HI_vi:
    case AMDGPU::GLOBAL_STORE_BYTE_vi:
    case AMDGPU::GLOBAL_STORE_DWORDX2_vi:
    case AMDGPU::GLOBAL_STORE_DWORDX3_vi:
    case AMDGPU::GLOBAL_STORE_DWORDX4_vi:
    case AMDGPU::GLOBAL_STORE_DWORD_vi:
    case AMDGPU::GLOBAL_STORE_SHORT_D16_HI_vi:
    case AMDGPU::GLOBAL_STORE_SHORT_vi: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::FLAT_STORE_BYTE_ci:
    case AMDGPU::FLAT_STORE_DWORDX2_ci:
    case AMDGPU::FLAT_STORE_DWORDX3_ci:
    case AMDGPU::FLAT_STORE_DWORDX4_ci:
    case AMDGPU::FLAT_STORE_DWORD_ci:
    case AMDGPU::FLAT_STORE_SHORT_ci: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_vi: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_OR_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_vi: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR_vi:
    case AMDGPU::GLOBAL_STORE_BYTE_SADDR_vi:
    case AMDGPU::GLOBAL_STORE_DWORDX2_SADDR_vi:
    case AMDGPU::GLOBAL_STORE_DWORDX3_SADDR_vi:
    case AMDGPU::GLOBAL_STORE_DWORDX4_SADDR_vi:
    case AMDGPU::GLOBAL_STORE_DWORD_SADDR_vi:
    case AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR_vi:
    case AMDGPU::GLOBAL_STORE_SHORT_SADDR_vi: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_F32_gfx11:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_ADD_gfx11:
    case AMDGPU::FLAT_ATOMIC_AND_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_AND_gfx11:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_gfx11:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_DEC_gfx11:
    case AMDGPU::FLAT_ATOMIC_FCMPSWAP_gfx11:
    case AMDGPU::FLAT_ATOMIC_FMAX_gfx11:
    case AMDGPU::FLAT_ATOMIC_FMIN_gfx11:
    case AMDGPU::FLAT_ATOMIC_INC_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_INC_gfx11:
    case AMDGPU::FLAT_ATOMIC_OR_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_OR_gfx11:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_SMAX_gfx11:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_SMIN_gfx11:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_SUB_gfx11:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_SWAP_gfx11:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_UMAX_gfx11:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_UMIN_gfx11:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_XOR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_ADD_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_AND_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_DEC_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_INC_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_OR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SUB_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_XOR_gfx11: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 15, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_ADD_gfx10:
    case AMDGPU::FLAT_ATOMIC_AND_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_AND_gfx10:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_gfx10:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_DEC_gfx10:
    case AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_FCMPSWAP_gfx10:
    case AMDGPU::FLAT_ATOMIC_FMAX_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_FMAX_gfx10:
    case AMDGPU::FLAT_ATOMIC_FMIN_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_FMIN_gfx10:
    case AMDGPU::FLAT_ATOMIC_INC_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_INC_gfx10:
    case AMDGPU::FLAT_ATOMIC_OR_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_OR_gfx10:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_SMAX_gfx10:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_SMIN_gfx10:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_SUB_gfx10:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_SWAP_gfx10:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_UMAX_gfx10:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_UMIN_gfx10:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_XOR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_ADD_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_AND_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_DEC_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_INC_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_OR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SUB_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_XOR_gfx10: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::FLAT_STORE_BYTE_D16_HI_gfx11:
    case AMDGPU::FLAT_STORE_BYTE_gfx11:
    case AMDGPU::FLAT_STORE_DWORDX2_gfx11:
    case AMDGPU::FLAT_STORE_DWORDX3_gfx11:
    case AMDGPU::FLAT_STORE_DWORDX4_gfx11:
    case AMDGPU::FLAT_STORE_DWORD_gfx11:
    case AMDGPU::FLAT_STORE_SHORT_D16_HI_gfx11:
    case AMDGPU::FLAT_STORE_SHORT_gfx11:
    case AMDGPU::GLOBAL_STORE_BYTE_D16_HI_gfx11:
    case AMDGPU::GLOBAL_STORE_BYTE_gfx11:
    case AMDGPU::GLOBAL_STORE_DWORDX2_gfx11:
    case AMDGPU::GLOBAL_STORE_DWORDX3_gfx11:
    case AMDGPU::GLOBAL_STORE_DWORDX4_gfx11:
    case AMDGPU::GLOBAL_STORE_DWORD_gfx11:
    case AMDGPU::GLOBAL_STORE_SHORT_D16_HI_gfx11:
    case AMDGPU::GLOBAL_STORE_SHORT_gfx11: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 14, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::FLAT_STORE_BYTE_D16_HI_gfx10:
    case AMDGPU::FLAT_STORE_BYTE_gfx10:
    case AMDGPU::FLAT_STORE_DWORDX2_gfx10:
    case AMDGPU::FLAT_STORE_DWORDX3_gfx10:
    case AMDGPU::FLAT_STORE_DWORDX4_gfx10:
    case AMDGPU::FLAT_STORE_DWORD_gfx10:
    case AMDGPU::FLAT_STORE_SHORT_D16_HI_gfx10:
    case AMDGPU::FLAT_STORE_SHORT_gfx10:
    case AMDGPU::GLOBAL_STORE_BYTE_D16_HI_gfx10:
    case AMDGPU::GLOBAL_STORE_BYTE_gfx10:
    case AMDGPU::GLOBAL_STORE_DWORDX2_gfx10:
    case AMDGPU::GLOBAL_STORE_DWORDX3_gfx10:
    case AMDGPU::GLOBAL_STORE_DWORDX4_gfx10:
    case AMDGPU::GLOBAL_STORE_DWORD_gfx10:
    case AMDGPU::GLOBAL_STORE_SHORT_D16_HI_gfx10:
    case AMDGPU::GLOBAL_STORE_SHORT_gfx10: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_AND_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_INC_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_OR_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_gfx11: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 15, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_AND_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_INC_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_OR_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_gfx10: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR_gfx11:
    case AMDGPU::GLOBAL_STORE_BYTE_SADDR_gfx11:
    case AMDGPU::GLOBAL_STORE_DWORDX2_SADDR_gfx11:
    case AMDGPU::GLOBAL_STORE_DWORDX3_SADDR_gfx11:
    case AMDGPU::GLOBAL_STORE_DWORDX4_SADDR_gfx11:
    case AMDGPU::GLOBAL_STORE_DWORD_SADDR_gfx11:
    case AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR_gfx11:
    case AMDGPU::GLOBAL_STORE_SHORT_SADDR_gfx11: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 14, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR_gfx10:
    case AMDGPU::GLOBAL_STORE_BYTE_SADDR_gfx10:
    case AMDGPU::GLOBAL_STORE_DWORDX2_SADDR_gfx10:
    case AMDGPU::GLOBAL_STORE_DWORDX3_SADDR_gfx10:
    case AMDGPU::GLOBAL_STORE_DWORDX4_SADDR_gfx10:
    case AMDGPU::GLOBAL_STORE_DWORD_SADDR_gfx10:
    case AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR_gfx10:
    case AMDGPU::GLOBAL_STORE_SHORT_SADDR_gfx10: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::GLOBAL_ATOMIC_CSUB_gfx11: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 15, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::GLOBAL_ATOMIC_CSUB_gfx10: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::GLOBAL_ATOMIC_CSUB_SADDR_gfx11: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 15, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::GLOBAL_ATOMIC_CSUB_SADDR_gfx10: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::GLOBAL_LOAD_LDS_DWORDX3_SADDR_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_DWORDX3_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_DWORDX4_SADDR_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_DWORDX4_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_DWORD_SADDR_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_DWORD_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_SBYTE_SADDR_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_SBYTE_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_SSHORT_SADDR_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_SSHORT_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_UBYTE_SADDR_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_UBYTE_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_USHORT_SADDR_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_USHORT_SADDR_vi: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::GLOBAL_LOAD_LDS_DWORD_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_LDS_SBYTE_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_LDS_SSHORT_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_LDS_UBYTE_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_LDS_USHORT_SADDR_gfx10: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::SCRATCH_LOAD_DWORDX2_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORD_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_SSHORT_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_USHORT_SVS_gfx11: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 14, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::SCRATCH_LOAD_DWORDX2_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_DWORD_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_SBYTE_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_SSHORT_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_UBYTE_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_USHORT_SVS_gfx940: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_VE_gfx940:
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_vi:
    case AMDGPU::SCRATCH_STORE_BYTE_VE_gfx940:
    case AMDGPU::SCRATCH_STORE_BYTE_vi:
    case AMDGPU::SCRATCH_STORE_DWORDX2_VE_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORDX2_vi:
    case AMDGPU::SCRATCH_STORE_DWORDX3_VE_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORDX3_vi:
    case AMDGPU::SCRATCH_STORE_DWORDX4_VE_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORDX4_vi:
    case AMDGPU::SCRATCH_STORE_DWORD_VE_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORD_vi:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_VE_gfx940:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_vi:
    case AMDGPU::SCRATCH_STORE_SHORT_VE_gfx940:
    case AMDGPU::SCRATCH_STORE_SHORT_vi: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SVS_gfx940:
    case AMDGPU::SCRATCH_STORE_BYTE_SVS_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORDX2_SVS_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORDX3_SVS_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORDX4_SVS_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORD_SVS_gfx940:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SVS_gfx940:
    case AMDGPU::SCRATCH_STORE_SHORT_SVS_gfx940: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_gfx11:
    case AMDGPU::SCRATCH_STORE_BYTE_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX2_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX3_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX4_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORD_gfx11:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_gfx11:
    case AMDGPU::SCRATCH_STORE_SHORT_gfx11: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 14, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_gfx10:
    case AMDGPU::SCRATCH_STORE_BYTE_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORDX2_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORDX3_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORDX4_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORD_gfx10:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_gfx10:
    case AMDGPU::SCRATCH_STORE_SHORT_gfx10: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SVS_gfx11:
    case AMDGPU::SCRATCH_STORE_BYTE_SVS_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX2_SVS_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX3_SVS_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX4_SVS_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORD_SVS_gfx11:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SVS_gfx11:
    case AMDGPU::SCRATCH_STORE_SHORT_SVS_gfx11: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 14, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CSUB_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_gfx11: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 15, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN_vi: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CSUB_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_gfx10: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_RTN_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_RTN_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_RTN_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_RTN_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_vi: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_F32_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_ADD_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_AND_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_AND_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_DEC_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_FCMPSWAP_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_FMAX_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_FMIN_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_INC_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_INC_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_OR_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_OR_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_SMAX_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_SMIN_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_SUB_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_SWAP_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_UMAX_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_UMIN_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_XOR_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_ADD_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_AND_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CSUB_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_DEC_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_INC_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_OR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SUB_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_XOR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN_gfx11: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 15, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_F64_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_ADD_F64_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_ADD_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_AND_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_AND_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_DEC_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_FCMPSWAP_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_FMAX_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_FMAX_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_FMIN_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_FMIN_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_INC_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_INC_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_MAX_F64_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_MAX_F64_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_MIN_F64_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_MIN_F64_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_OR_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_OR_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_SMAX_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_SMIN_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_SUB_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_SWAP_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_UMAX_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_UMIN_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_XOR_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_ci:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_RTN_vi: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_AND_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_AND_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_DEC_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_FCMPSWAP_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_FMAX_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_FMAX_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_FMIN_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_FMIN_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_INC_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_INC_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_OR_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_OR_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_SMAX_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_SMIN_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_SUB_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_SWAP_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_UMAX_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_UMIN_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_XOR_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_ADD_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_AND_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CSUB_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_DEC_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_INC_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_OR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SUB_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_XOR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN_gfx10: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_F32_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_ADD_F32_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_ADD_F64_RTN_gfx940:
    case AMDGPU::FLAT_ATOMIC_ADD_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_ADD_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_AND_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_AND_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_AND_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_AND_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_DEC_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_DEC_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_INC_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_INC_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_INC_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_INC_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_MAX_F64_RTN_gfx940:
    case AMDGPU::FLAT_ATOMIC_MIN_F64_RTN_gfx940:
    case AMDGPU::FLAT_ATOMIC_OR_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_OR_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_OR_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_OR_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_BF16_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_BF16_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_F16_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_F16_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_SMAX_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_SMAX_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_SMIN_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_SMIN_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_SUB_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_SUB_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_SWAP_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_SWAP_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_UMAX_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_UMAX_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_UMIN_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_UMIN_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_XOR_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_XOR_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_RTN_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_ADD_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_RTN_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_RTN_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_OR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_OR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_RTN_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN_vi: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 17, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::FLAT_LOAD_DWORDX2_gfx11:
    case AMDGPU::FLAT_LOAD_DWORDX3_gfx11:
    case AMDGPU::FLAT_LOAD_DWORDX4_gfx11:
    case AMDGPU::FLAT_LOAD_DWORD_gfx11:
    case AMDGPU::FLAT_LOAD_SBYTE_D16_HI_gfx11:
    case AMDGPU::FLAT_LOAD_SBYTE_D16_gfx11:
    case AMDGPU::FLAT_LOAD_SBYTE_gfx11:
    case AMDGPU::FLAT_LOAD_SHORT_D16_HI_gfx11:
    case AMDGPU::FLAT_LOAD_SHORT_D16_gfx11:
    case AMDGPU::FLAT_LOAD_SSHORT_gfx11:
    case AMDGPU::FLAT_LOAD_UBYTE_D16_HI_gfx11:
    case AMDGPU::FLAT_LOAD_UBYTE_D16_gfx11:
    case AMDGPU::FLAT_LOAD_UBYTE_gfx11:
    case AMDGPU::FLAT_LOAD_USHORT_gfx11:
    case AMDGPU::GLOBAL_LOAD_DWORDX2_gfx11:
    case AMDGPU::GLOBAL_LOAD_DWORDX3_gfx11:
    case AMDGPU::GLOBAL_LOAD_DWORDX4_gfx11:
    case AMDGPU::GLOBAL_LOAD_DWORD_gfx11:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_gfx11:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_gfx11:
    case AMDGPU::GLOBAL_LOAD_SBYTE_gfx11:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_gfx11:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_gfx11:
    case AMDGPU::GLOBAL_LOAD_SSHORT_gfx11:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_gfx11:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_gfx11:
    case AMDGPU::GLOBAL_LOAD_UBYTE_gfx11:
    case AMDGPU::GLOBAL_LOAD_USHORT_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORDX2_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORD_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_gfx11:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_gfx11:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_gfx11:
    case AMDGPU::SCRATCH_LOAD_SSHORT_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_gfx11:
    case AMDGPU::SCRATCH_LOAD_USHORT_gfx11: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 14, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::FLAT_LOAD_DWORDX2_gfx10:
    case AMDGPU::FLAT_LOAD_DWORDX3_gfx10:
    case AMDGPU::FLAT_LOAD_DWORDX4_gfx10:
    case AMDGPU::FLAT_LOAD_DWORD_gfx10:
    case AMDGPU::FLAT_LOAD_SBYTE_D16_HI_gfx10:
    case AMDGPU::FLAT_LOAD_SBYTE_D16_gfx10:
    case AMDGPU::FLAT_LOAD_SBYTE_gfx10:
    case AMDGPU::FLAT_LOAD_SHORT_D16_HI_gfx10:
    case AMDGPU::FLAT_LOAD_SHORT_D16_gfx10:
    case AMDGPU::FLAT_LOAD_SSHORT_gfx10:
    case AMDGPU::FLAT_LOAD_UBYTE_D16_HI_gfx10:
    case AMDGPU::FLAT_LOAD_UBYTE_D16_gfx10:
    case AMDGPU::FLAT_LOAD_UBYTE_gfx10:
    case AMDGPU::FLAT_LOAD_USHORT_gfx10:
    case AMDGPU::GLOBAL_LOAD_DWORDX2_gfx10:
    case AMDGPU::GLOBAL_LOAD_DWORDX3_gfx10:
    case AMDGPU::GLOBAL_LOAD_DWORDX4_gfx10:
    case AMDGPU::GLOBAL_LOAD_DWORD_gfx10:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_gfx10:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_gfx10:
    case AMDGPU::GLOBAL_LOAD_SBYTE_gfx10:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_gfx10:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_gfx10:
    case AMDGPU::GLOBAL_LOAD_SSHORT_gfx10:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_gfx10:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_gfx10:
    case AMDGPU::GLOBAL_LOAD_UBYTE_gfx10:
    case AMDGPU::GLOBAL_LOAD_USHORT_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORDX2_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORD_gfx10:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_gfx10:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_gfx10:
    case AMDGPU::SCRATCH_LOAD_SBYTE_gfx10:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_gfx10:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_gfx10:
    case AMDGPU::SCRATCH_LOAD_SSHORT_gfx10:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_gfx10:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_gfx10:
    case AMDGPU::SCRATCH_LOAD_UBYTE_gfx10:
    case AMDGPU::SCRATCH_LOAD_USHORT_gfx10: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::FLAT_LOAD_DWORDX2_vi:
    case AMDGPU::FLAT_LOAD_DWORDX3_vi:
    case AMDGPU::FLAT_LOAD_DWORDX4_vi:
    case AMDGPU::FLAT_LOAD_DWORD_vi:
    case AMDGPU::FLAT_LOAD_SBYTE_D16_HI_vi:
    case AMDGPU::FLAT_LOAD_SBYTE_D16_vi:
    case AMDGPU::FLAT_LOAD_SBYTE_vi:
    case AMDGPU::FLAT_LOAD_SHORT_D16_HI_vi:
    case AMDGPU::FLAT_LOAD_SHORT_D16_vi:
    case AMDGPU::FLAT_LOAD_SSHORT_vi:
    case AMDGPU::FLAT_LOAD_UBYTE_D16_HI_vi:
    case AMDGPU::FLAT_LOAD_UBYTE_D16_vi:
    case AMDGPU::FLAT_LOAD_UBYTE_vi:
    case AMDGPU::FLAT_LOAD_USHORT_vi:
    case AMDGPU::GLOBAL_LOAD_DWORDX2_vi:
    case AMDGPU::GLOBAL_LOAD_DWORDX3_vi:
    case AMDGPU::GLOBAL_LOAD_DWORDX4_vi:
    case AMDGPU::GLOBAL_LOAD_DWORD_vi:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_vi:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_vi:
    case AMDGPU::GLOBAL_LOAD_SBYTE_vi:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_vi:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_vi:
    case AMDGPU::GLOBAL_LOAD_SSHORT_vi:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_vi:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_vi:
    case AMDGPU::GLOBAL_LOAD_UBYTE_vi:
    case AMDGPU::GLOBAL_LOAD_USHORT_vi:
    case AMDGPU::SCRATCH_LOAD_DWORDX2_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_DWORDX2_vi:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_vi:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_vi:
    case AMDGPU::SCRATCH_LOAD_DWORD_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_DWORD_vi:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_vi:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_vi:
    case AMDGPU::SCRATCH_LOAD_SBYTE_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_SBYTE_vi:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_vi:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_vi:
    case AMDGPU::SCRATCH_LOAD_SSHORT_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_SSHORT_vi:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_vi:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_vi:
    case AMDGPU::SCRATCH_LOAD_UBYTE_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_UBYTE_vi:
    case AMDGPU::SCRATCH_LOAD_USHORT_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_USHORT_vi: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::FLAT_LOAD_DWORDX2_ci:
    case AMDGPU::FLAT_LOAD_DWORDX3_ci:
    case AMDGPU::FLAT_LOAD_DWORDX4_ci:
    case AMDGPU::FLAT_LOAD_DWORD_ci:
    case AMDGPU::FLAT_LOAD_SBYTE_ci:
    case AMDGPU::FLAT_LOAD_SSHORT_ci:
    case AMDGPU::FLAT_LOAD_UBYTE_ci:
    case AMDGPU::FLAT_LOAD_USHORT_ci: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_DWORD_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_SBYTE_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_SSHORT_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_UBYTE_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_USHORT_SADDR_gfx11: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 14, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_DWORD_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_SBYTE_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_SSHORT_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_UBYTE_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_USHORT_SADDR_gfx10: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_DWORD_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_SBYTE_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_SSHORT_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_UBYTE_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_USHORT_SADDR_vi: {
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_ST_gfx940:
    case AMDGPU::SCRATCH_STORE_BYTE_ST_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORDX2_ST_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORDX3_ST_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORDX4_ST_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORD_ST_gfx940:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_ST_gfx940:
    case AMDGPU::SCRATCH_STORE_SHORT_ST_gfx940: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR_vi:
    case AMDGPU::SCRATCH_STORE_BYTE_SADDR_vi:
    case AMDGPU::SCRATCH_STORE_DWORDX2_SADDR_vi:
    case AMDGPU::SCRATCH_STORE_DWORDX3_SADDR_vi:
    case AMDGPU::SCRATCH_STORE_DWORDX4_SADDR_vi:
    case AMDGPU::SCRATCH_STORE_DWORD_SADDR_vi:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR_vi:
    case AMDGPU::SCRATCH_STORE_SHORT_SADDR_vi: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_ST_gfx11:
    case AMDGPU::SCRATCH_STORE_BYTE_ST_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX2_ST_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX3_ST_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX4_ST_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORD_ST_gfx11:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_ST_gfx11:
    case AMDGPU::SCRATCH_STORE_SHORT_ST_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 14, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_ST_gfx10:
    case AMDGPU::SCRATCH_STORE_BYTE_ST_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORDX2_ST_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORDX3_ST_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORDX4_ST_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORD_ST_gfx10:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_ST_gfx10:
    case AMDGPU::SCRATCH_STORE_SHORT_ST_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V7_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(16), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(17), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(18), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V8_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(17), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(18), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(19), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(16), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V9_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(16), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(18), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(19), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(20), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(17), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V10_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(16), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(17), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(19), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(20), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(21), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(18), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V11_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(16), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(17), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(18), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(20), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(21), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(22), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(19), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V12_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V12_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V12_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V12_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V12_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V12_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V12_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V12_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V12_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V12_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(17), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(18), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(19), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(21), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(22), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(23), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(16), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(20), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V1:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V2:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V3:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V4:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V1:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V2:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V3:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V4:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V1:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V2:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V3:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V4:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V1:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V2:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V3:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V4:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V1:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V2:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V3:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V4:
    case AMDGPU::IMAGE_LOAD_V1_V1:
    case AMDGPU::IMAGE_LOAD_V1_V2:
    case AMDGPU::IMAGE_LOAD_V1_V3:
    case AMDGPU::IMAGE_LOAD_V1_V4:
    case AMDGPU::IMAGE_LOAD_V2_V1:
    case AMDGPU::IMAGE_LOAD_V2_V2:
    case AMDGPU::IMAGE_LOAD_V2_V3:
    case AMDGPU::IMAGE_LOAD_V2_V4:
    case AMDGPU::IMAGE_LOAD_V3_V1:
    case AMDGPU::IMAGE_LOAD_V3_V2:
    case AMDGPU::IMAGE_LOAD_V3_V3:
    case AMDGPU::IMAGE_LOAD_V3_V4:
    case AMDGPU::IMAGE_LOAD_V4_V1:
    case AMDGPU::IMAGE_LOAD_V4_V2:
    case AMDGPU::IMAGE_LOAD_V4_V3:
    case AMDGPU::IMAGE_LOAD_V4_V4:
    case AMDGPU::IMAGE_LOAD_V5_V1:
    case AMDGPU::IMAGE_LOAD_V5_V2:
    case AMDGPU::IMAGE_LOAD_V5_V3:
    case AMDGPU::IMAGE_LOAD_V5_V4:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V1:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V2:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V3:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V4:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V1:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V2:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V3:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V4:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V1:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V2:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V3:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V4:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V1:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V2:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V3:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V4:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V1:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V2:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V3:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V4:
    case AMDGPU::IMAGE_STORE_MIP_V1_V1:
    case AMDGPU::IMAGE_STORE_MIP_V1_V2:
    case AMDGPU::IMAGE_STORE_MIP_V1_V3:
    case AMDGPU::IMAGE_STORE_MIP_V1_V4:
    case AMDGPU::IMAGE_STORE_MIP_V2_V1:
    case AMDGPU::IMAGE_STORE_MIP_V2_V2:
    case AMDGPU::IMAGE_STORE_MIP_V2_V3:
    case AMDGPU::IMAGE_STORE_MIP_V2_V4:
    case AMDGPU::IMAGE_STORE_MIP_V3_V1:
    case AMDGPU::IMAGE_STORE_MIP_V3_V2:
    case AMDGPU::IMAGE_STORE_MIP_V3_V3:
    case AMDGPU::IMAGE_STORE_MIP_V3_V4:
    case AMDGPU::IMAGE_STORE_MIP_V4_V1:
    case AMDGPU::IMAGE_STORE_MIP_V4_V2:
    case AMDGPU::IMAGE_STORE_MIP_V4_V3:
    case AMDGPU::IMAGE_STORE_MIP_V4_V4:
    case AMDGPU::IMAGE_STORE_MIP_V5_V1:
    case AMDGPU::IMAGE_STORE_MIP_V5_V2:
    case AMDGPU::IMAGE_STORE_MIP_V5_V3:
    case AMDGPU::IMAGE_STORE_MIP_V5_V4:
    case AMDGPU::IMAGE_STORE_V1_V1:
    case AMDGPU::IMAGE_STORE_V1_V2:
    case AMDGPU::IMAGE_STORE_V1_V3:
    case AMDGPU::IMAGE_STORE_V1_V4:
    case AMDGPU::IMAGE_STORE_V2_V1:
    case AMDGPU::IMAGE_STORE_V2_V2:
    case AMDGPU::IMAGE_STORE_V2_V3:
    case AMDGPU::IMAGE_STORE_V2_V4:
    case AMDGPU::IMAGE_STORE_V3_V1:
    case AMDGPU::IMAGE_STORE_V3_V2:
    case AMDGPU::IMAGE_STORE_V3_V3:
    case AMDGPU::IMAGE_STORE_V3_V4:
    case AMDGPU::IMAGE_STORE_V4_V1:
    case AMDGPU::IMAGE_STORE_V4_V2:
    case AMDGPU::IMAGE_STORE_V4_V3:
    case AMDGPU::IMAGE_STORE_V4_V4:
    case AMDGPU::IMAGE_STORE_V5_V1:
    case AMDGPU::IMAGE_STORE_V5_V2:
    case AMDGPU::IMAGE_STORE_V5_V3:
    case AMDGPU::IMAGE_STORE_V5_V4: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: da
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V1_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V1_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V1:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V2:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V3:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V4:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V1:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V2:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V3:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V4:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V1:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V2:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V3:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V4:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V1:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V2:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V3:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V4:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V1:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V2:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V3:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V4:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V1:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V1:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V1:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V1:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V1:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V2:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V3:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V4:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V1:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V1:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V1:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V1:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V1:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V2:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V3:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V4:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V1:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V1:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V1:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V1:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V1:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V2:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V3:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V4:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V1:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V2:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V3:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V4:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V1:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V2:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V3:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V4:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V1:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V2:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V3:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V4:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V1:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V2:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V3:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V4:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V1:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V2:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V3:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V4:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V1:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V1:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V1:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V1:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V1:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V2:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V3:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V4:
    case AMDGPU::IMAGE_STORE_PCK_V1_V1:
    case AMDGPU::IMAGE_STORE_PCK_V1_V2:
    case AMDGPU::IMAGE_STORE_PCK_V1_V3:
    case AMDGPU::IMAGE_STORE_PCK_V1_V4:
    case AMDGPU::IMAGE_STORE_PCK_V2_V1:
    case AMDGPU::IMAGE_STORE_PCK_V2_V2:
    case AMDGPU::IMAGE_STORE_PCK_V2_V3:
    case AMDGPU::IMAGE_STORE_PCK_V2_V4:
    case AMDGPU::IMAGE_STORE_PCK_V3_V1:
    case AMDGPU::IMAGE_STORE_PCK_V3_V2:
    case AMDGPU::IMAGE_STORE_PCK_V3_V3:
    case AMDGPU::IMAGE_STORE_PCK_V3_V4:
    case AMDGPU::IMAGE_STORE_PCK_V4_V1:
    case AMDGPU::IMAGE_STORE_PCK_V4_V2:
    case AMDGPU::IMAGE_STORE_PCK_V4_V3:
    case AMDGPU::IMAGE_STORE_PCK_V4_V4:
    case AMDGPU::IMAGE_STORE_PCK_V5_V1:
    case AMDGPU::IMAGE_STORE_PCK_V5_V2:
    case AMDGPU::IMAGE_STORE_PCK_V5_V3:
    case AMDGPU::IMAGE_STORE_PCK_V5_V4: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: da
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_V1_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_V1_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_V1_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_V1_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_V2_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_V2_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_V2_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_V2_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_V3_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_V3_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_V3_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_V3_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_V4_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_V4_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_V4_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_V4_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_V5_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_V5_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_V5_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_V5_V4_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V1_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V2_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V3_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V4_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V1_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V2_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V3_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V4_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V1_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V2_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V3_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V4_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V1_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V2_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V3_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V4_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V1_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V2_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V3_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V4_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V1_V1_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V1_V2_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V1_V3_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V1_V4_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V2_V1_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V2_V2_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V2_V3_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V2_V4_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V3_V1_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V3_V2_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V3_V3_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V3_V4_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V4_V1_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V4_V2_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V4_V3_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V4_V4_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V5_V1_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V5_V2_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V5_V3_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V5_V4_gfx10:
    case AMDGPU::IMAGE_STORE_V1_V1_gfx10:
    case AMDGPU::IMAGE_STORE_V1_V2_gfx10:
    case AMDGPU::IMAGE_STORE_V1_V3_gfx10:
    case AMDGPU::IMAGE_STORE_V1_V4_gfx10:
    case AMDGPU::IMAGE_STORE_V2_V1_gfx10:
    case AMDGPU::IMAGE_STORE_V2_V2_gfx10:
    case AMDGPU::IMAGE_STORE_V2_V3_gfx10:
    case AMDGPU::IMAGE_STORE_V2_V4_gfx10:
    case AMDGPU::IMAGE_STORE_V3_V1_gfx10:
    case AMDGPU::IMAGE_STORE_V3_V2_gfx10:
    case AMDGPU::IMAGE_STORE_V3_V3_gfx10:
    case AMDGPU::IMAGE_STORE_V3_V4_gfx10:
    case AMDGPU::IMAGE_STORE_V4_V1_gfx10:
    case AMDGPU::IMAGE_STORE_V4_V2_gfx10:
    case AMDGPU::IMAGE_STORE_V4_V3_gfx10:
    case AMDGPU::IMAGE_STORE_V4_V4_gfx10:
    case AMDGPU::IMAGE_STORE_V5_V1_gfx10:
    case AMDGPU::IMAGE_STORE_V5_V2_gfx10:
    case AMDGPU::IMAGE_STORE_V5_V3_gfx10:
    case AMDGPU::IMAGE_STORE_V5_V4_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V1_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V2_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V3_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V4_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V1_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V2_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V3_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V4_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V1_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V2_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V3_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V4_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V1_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V2_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V3_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V4_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V1_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V2_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V3_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V4_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V1_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V1_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V1_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V1_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V1_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V2_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V3_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V4_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V1_V1_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V1_V2_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V1_V3_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V1_V4_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V2_V1_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V2_V2_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V2_V3_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V2_V4_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V3_V1_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V3_V2_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V3_V3_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V3_V4_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V4_V1_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V4_V2_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V4_V3_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V4_V4_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V5_V1_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V5_V2_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V5_V3_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V5_V4_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V1_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V2_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V3_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V4_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V1_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V2_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V3_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V4_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V1_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V2_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V3_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V4_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V1_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V2_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V3_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V4_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V1_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V2_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V3_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V4_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V1_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V1_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V1_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V1_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V1_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V2_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V3_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V4_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V1_V1_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V1_V2_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V1_V3_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V1_V4_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V2_V1_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V2_V2_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V2_V3_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V2_V4_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V3_V1_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V3_V2_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V3_V3_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V3_V4_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V4_V1_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V4_V2_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V4_V3_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V4_V4_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V5_V1_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V5_V2_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V5_V3_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V5_V4_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_V1_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_V1_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_V1_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_V1_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_V2_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_V2_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_V2_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_V2_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_V3_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_V3_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_V3_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_V3_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_V4_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_V4_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_V4_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_V4_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_V5_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_V5_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_V5_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_V5_V4_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V1_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V2_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V3_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V4_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V1_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V2_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V3_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V4_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V1_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V2_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V3_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V4_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V1_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V2_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V3_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V4_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V1_V1_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V1_V2_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V1_V3_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V1_V4_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V2_V1_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V2_V2_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V2_V3_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V2_V4_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V3_V1_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V3_V2_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V3_V3_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V3_V4_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V4_V1_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V4_V2_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V4_V3_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V4_V4_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V5_V1_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V5_V2_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V5_V3_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V5_V4_gfx11:
    case AMDGPU::IMAGE_STORE_V1_V1_gfx11:
    case AMDGPU::IMAGE_STORE_V1_V2_gfx11:
    case AMDGPU::IMAGE_STORE_V1_V3_gfx11:
    case AMDGPU::IMAGE_STORE_V1_V4_gfx11:
    case AMDGPU::IMAGE_STORE_V2_V1_gfx11:
    case AMDGPU::IMAGE_STORE_V2_V2_gfx11:
    case AMDGPU::IMAGE_STORE_V2_V3_gfx11:
    case AMDGPU::IMAGE_STORE_V2_V4_gfx11:
    case AMDGPU::IMAGE_STORE_V3_V1_gfx11:
    case AMDGPU::IMAGE_STORE_V3_V2_gfx11:
    case AMDGPU::IMAGE_STORE_V3_V3_gfx11:
    case AMDGPU::IMAGE_STORE_V3_V4_gfx11:
    case AMDGPU::IMAGE_STORE_V4_V1_gfx11:
    case AMDGPU::IMAGE_STORE_V4_V2_gfx11:
    case AMDGPU::IMAGE_STORE_V4_V3_gfx11:
    case AMDGPU::IMAGE_STORE_V4_V4_gfx11:
    case AMDGPU::IMAGE_STORE_V5_V1_gfx11:
    case AMDGPU::IMAGE_STORE_V5_V2_gfx11:
    case AMDGPU::IMAGE_STORE_V5_V3_gfx11:
    case AMDGPU::IMAGE_STORE_V5_V4_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_GATHER4H_V2_V1:
    case AMDGPU::IMAGE_GATHER4H_V2_V2:
    case AMDGPU::IMAGE_GATHER4H_V2_V3:
    case AMDGPU::IMAGE_GATHER4H_V2_V4:
    case AMDGPU::IMAGE_GATHER4H_V4_V1:
    case AMDGPU::IMAGE_GATHER4H_V4_V2:
    case AMDGPU::IMAGE_GATHER4H_V4_V3:
    case AMDGPU::IMAGE_GATHER4H_V4_V4:
    case AMDGPU::IMAGE_GATHER4H_V5_V1:
    case AMDGPU::IMAGE_GATHER4H_V5_V2:
    case AMDGPU::IMAGE_GATHER4H_V5_V3:
    case AMDGPU::IMAGE_GATHER4H_V5_V4:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V3:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V5:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V6:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V8:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V3:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V5:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V6:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V8:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V3:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V5:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V6:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V8:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V2:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V3:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V4:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V5:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V8:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V2:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V3:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V4:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V5:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V8:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V2:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V3:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V4:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V5:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V8:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V3:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V5:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V8:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V3:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V5:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V8:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V3:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V5:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V8:
    case AMDGPU::IMAGE_GATHER4_B_V2_V2:
    case AMDGPU::IMAGE_GATHER4_B_V2_V3:
    case AMDGPU::IMAGE_GATHER4_B_V2_V4:
    case AMDGPU::IMAGE_GATHER4_B_V4_V2:
    case AMDGPU::IMAGE_GATHER4_B_V4_V3:
    case AMDGPU::IMAGE_GATHER4_B_V4_V4:
    case AMDGPU::IMAGE_GATHER4_B_V5_V2:
    case AMDGPU::IMAGE_GATHER4_B_V5_V3:
    case AMDGPU::IMAGE_GATHER4_B_V5_V4:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V2:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V3:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V5:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V8:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V2:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V3:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V5:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V8:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V2:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V3:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V5:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V8:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V1:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V2:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V3:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V4:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V1:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V2:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V3:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V4:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V1:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V2:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V3:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V6:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V7:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V6:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V7:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V6:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V7:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V3:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V6:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V3:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V6:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V3:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V6:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V6:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V6:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V6:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V3:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V3:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V3:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V8:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V3:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V5:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V6:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V8:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V3:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V5:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V6:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V8:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V3:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V5:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V6:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V8:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V2:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V3:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V5:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V8:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V2:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V3:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V5:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V8:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V2:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V3:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V5:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V8:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V3:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V5:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V8:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V3:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V5:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V8:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V3:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V5:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V8:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V2:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V3:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V2:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V3:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V2:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V3:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V3:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V5:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V6:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V8:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V3:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V5:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V6:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V8:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V3:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V5:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V6:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V8:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V2:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V3:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V5:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V8:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V2:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V3:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V5:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V8:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V2:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V3:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V5:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V8:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V3:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V5:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V8:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V3:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V5:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V8:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V3:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V5:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V8:
    case AMDGPU::IMAGE_GATHER4_C_V2_V2:
    case AMDGPU::IMAGE_GATHER4_C_V2_V3:
    case AMDGPU::IMAGE_GATHER4_C_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_V4_V2:
    case AMDGPU::IMAGE_GATHER4_C_V4_V3:
    case AMDGPU::IMAGE_GATHER4_C_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_V5_V2:
    case AMDGPU::IMAGE_GATHER4_C_V5_V3:
    case AMDGPU::IMAGE_GATHER4_C_V5_V4:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V2:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V3:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V2:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V3:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V2:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V3:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V1:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V2:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V3:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V4:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V1:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V2:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V3:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V4:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V1:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V2:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V3:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V4:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V2:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V3:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V5:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V8:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V2:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V3:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V5:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V8:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V2:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V3:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V5:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V8:
    case AMDGPU::IMAGE_GATHER4_L_V2_V1:
    case AMDGPU::IMAGE_GATHER4_L_V2_V2:
    case AMDGPU::IMAGE_GATHER4_L_V2_V3:
    case AMDGPU::IMAGE_GATHER4_L_V2_V4:
    case AMDGPU::IMAGE_GATHER4_L_V4_V1:
    case AMDGPU::IMAGE_GATHER4_L_V4_V2:
    case AMDGPU::IMAGE_GATHER4_L_V4_V3:
    case AMDGPU::IMAGE_GATHER4_L_V4_V4:
    case AMDGPU::IMAGE_GATHER4_L_V5_V1:
    case AMDGPU::IMAGE_GATHER4_L_V5_V2:
    case AMDGPU::IMAGE_GATHER4_L_V5_V3:
    case AMDGPU::IMAGE_GATHER4_L_V5_V4:
    case AMDGPU::IMAGE_GATHER4_O_V2_V2:
    case AMDGPU::IMAGE_GATHER4_O_V2_V3:
    case AMDGPU::IMAGE_GATHER4_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_O_V4_V2:
    case AMDGPU::IMAGE_GATHER4_O_V4_V3:
    case AMDGPU::IMAGE_GATHER4_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_O_V5_V2:
    case AMDGPU::IMAGE_GATHER4_O_V5_V3:
    case AMDGPU::IMAGE_GATHER4_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_V2_V1:
    case AMDGPU::IMAGE_GATHER4_V2_V2:
    case AMDGPU::IMAGE_GATHER4_V2_V3:
    case AMDGPU::IMAGE_GATHER4_V2_V4:
    case AMDGPU::IMAGE_GATHER4_V4_V1:
    case AMDGPU::IMAGE_GATHER4_V4_V2:
    case AMDGPU::IMAGE_GATHER4_V4_V3:
    case AMDGPU::IMAGE_GATHER4_V4_V4:
    case AMDGPU::IMAGE_GATHER4_V5_V1:
    case AMDGPU::IMAGE_GATHER4_V5_V2:
    case AMDGPU::IMAGE_GATHER4_V5_V3:
    case AMDGPU::IMAGE_GATHER4_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V11:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V11:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V11:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V11:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V11:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V1:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V1:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V1:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V1:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V1:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V12:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V12:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V12:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V12:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V12:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V1:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V1:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V1:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V1:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V1:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V1:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V1:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V1:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V1:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V1:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_V1_V1:
    case AMDGPU::IMAGE_SAMPLE_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_V2_V1:
    case AMDGPU::IMAGE_SAMPLE_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_V3_V1:
    case AMDGPU::IMAGE_SAMPLE_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_V4_V1:
    case AMDGPU::IMAGE_SAMPLE_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_V5_V1:
    case AMDGPU::IMAGE_SAMPLE_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_V5_V4: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: da
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V1:
    case AMDGPU::IMAGE_GET_LOD_V1_V2:
    case AMDGPU::IMAGE_GET_LOD_V1_V3:
    case AMDGPU::IMAGE_GET_LOD_V1_V4:
    case AMDGPU::IMAGE_GET_LOD_V2_V1:
    case AMDGPU::IMAGE_GET_LOD_V2_V2:
    case AMDGPU::IMAGE_GET_LOD_V2_V3:
    case AMDGPU::IMAGE_GET_LOD_V2_V4:
    case AMDGPU::IMAGE_GET_LOD_V3_V1:
    case AMDGPU::IMAGE_GET_LOD_V3_V2:
    case AMDGPU::IMAGE_GET_LOD_V3_V3:
    case AMDGPU::IMAGE_GET_LOD_V3_V4:
    case AMDGPU::IMAGE_GET_LOD_V4_V1:
    case AMDGPU::IMAGE_GET_LOD_V4_V2:
    case AMDGPU::IMAGE_GET_LOD_V4_V3:
    case AMDGPU::IMAGE_GET_LOD_V4_V4:
    case AMDGPU::IMAGE_GET_LOD_V5_V1:
    case AMDGPU::IMAGE_GET_LOD_V5_V2:
    case AMDGPU::IMAGE_GET_LOD_V5_V3:
    case AMDGPU::IMAGE_GET_LOD_V5_V4: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: da
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      break;
    }
    case AMDGPU::IMAGE_GATHER4H_V2_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V4_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V5_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V7_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V7_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V7_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V2_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V4_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V5_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_V2_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_V4_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_V5_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V1_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V2_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V3_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V4_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V5_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V5_V4_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V5_V2_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V1_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V1_V2_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V1_V3_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V1_V4_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V2_V1_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V2_V2_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V2_V3_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V2_V4_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V3_V1_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V3_V2_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V3_V3_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V3_V4_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V4_V1_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V4_V2_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V4_V3_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V4_V4_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V5_V1_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V5_V2_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V5_V3_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V5_V4_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V5_V2_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V1_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V1_V2_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V1_V3_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V1_V4_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V2_V1_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V2_V2_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V2_V3_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V2_V4_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V3_V1_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V3_V2_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V3_V3_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V3_V4_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V4_V1_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V4_V2_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V4_V3_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V4_V4_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V5_V1_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V5_V2_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V5_V3_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V5_V4_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 58, 5);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_GATHER4H_V2_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V4_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V5_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V6_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V6_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V6_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V2_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V4_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V5_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_V2_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_V4_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_V5_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V12_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V12_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V12_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V12_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V12_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V1_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V2_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V3_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V4_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V5_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V5_V4_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 58, 5);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V5_V2_nsa_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V5_V2_nsa_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_GATHER4H_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V5_V2_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V5_V3_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V5_V2_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V5_V3_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V5_V2_nsa_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 58, 5);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_GATHER4H_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V5_V2_nsa_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 58, 5);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V5_V3_nsa_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V5_V3_nsa_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_GATHER4H_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V5_V3_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V5_V4_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V5_V3_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V5_V4_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V5_V3_nsa_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 58, 5);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_GATHER4H_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V5_V3_nsa_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 58, 5);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V5_V4_nsa_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V5_V4_nsa_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V4_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V4_nsa_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 58, 5);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V5_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(16), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V12_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V12_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V12_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V12_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V12_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V5_nsa_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 58, 5);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(16), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V6_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(15), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(16), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(17), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR_gfx11:
    case AMDGPU::SCRATCH_STORE_BYTE_SADDR_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX2_SADDR_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX3_SADDR_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX4_SADDR_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORD_SADDR_gfx11:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR_gfx11:
    case AMDGPU::SCRATCH_STORE_SHORT_SADDR_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 14, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR_gfx10:
    case AMDGPU::SCRATCH_STORE_BYTE_SADDR_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORDX2_SADDR_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORDX3_SADDR_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORDX4_SADDR_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORD_SADDR_gfx10:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR_gfx10:
    case AMDGPU::SCRATCH_STORE_SHORT_SADDR_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_V1_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_V1_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_V1_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_V1_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_V2_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_V2_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_V2_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_V2_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_V3_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_V3_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_V3_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_V3_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_V4_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_V4_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_V4_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_V4_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_V5_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_V5_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_V5_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_V5_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V1_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V1_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V1_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V1_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V2_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V2_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V2_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V2_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V3_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V3_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V3_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V3_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V4_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V4_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V4_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V4_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V5_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V5_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V5_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V5_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_V1_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_V1_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_V1_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_V1_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_V2_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_V2_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_V2_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_V2_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_V3_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_V3_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_V3_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_V3_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_V4_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_V4_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_V4_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_V4_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_V5_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_V5_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_V5_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_V5_V4_gfx90a: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 16, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: da
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V1_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V2_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V3_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V4_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V1_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V2_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V3_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V4_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V1_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V2_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V3_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V4_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V1_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V2_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V3_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V4_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V1_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V2_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V3_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V1_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V1_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V1_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V1_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V2_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V2_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V2_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V2_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V3_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V3_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V3_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V3_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V4_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V4_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V4_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V4_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V5_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V5_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V5_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V5_V4_gfx90a: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 16, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: da
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_V1_V1_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V1_V2_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V1_V3_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V1_V4_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V2_V1_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V2_V2_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V2_V3_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V2_V4_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V3_V1_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V3_V2_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V3_V3_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V3_V4_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V4_V1_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V4_V2_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V4_V3_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V4_V4_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V5_V1_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V5_V2_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V5_V3_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V5_V4_gfx90a: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 16, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: d16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: da
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V1_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V1_V2_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V1_V3_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V1_V4_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V2_V1_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V2_V2_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V2_V3_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V2_V4_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V3_V1_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V3_V2_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V3_V3_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V3_V4_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V4_V1_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V4_V2_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V4_V3_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V4_V4_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V5_V1_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V5_V2_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V5_V3_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V5_V4_gfx90a: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 16, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: ssamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 53, 5);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: da
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V1_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V2_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V3_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V4_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V1_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V2_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V3_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V4_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V4_vi: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: da
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V4_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V4_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V2_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V2_nsa_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V3_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V3_nsa_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V4_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 3, 3);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V4_nsa_gfx11: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 7, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 12, 2);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: tfe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 53, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 54, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: a16
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: dim
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 2, 3);
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V4_gfx90a: {
      // op: vdata
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 16, 1);
      // op: dmask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 8, 4);
      // op: unorm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 12, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 7, 1);
      // op: r128
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: lwe
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: da
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      break;
    }
    case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_gfx12:
    case AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_gfx12: {
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vaddr2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vaddr3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      break;
    }
    case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_gfx12:
    case AMDGPU::IMAGE_BVH_INTERSECT_RAY_gfx12: {
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vaddr2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vaddr3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: vaddr4
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::IMAGE_BVH8_INTERSECT_RAY_gfx12:
    case AMDGPU::IMAGE_BVH_DUAL_INTERSECT_RAY_gfx12: {
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: rsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: vaddr1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 72, 8);
      // op: vaddr2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 80, 8);
      // op: vaddr3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 88, 8);
      // op: vaddr4
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      break;
    }
    case AMDGPU::GLOBAL_STORE_DWORD_ADDTID_gfx11: {
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 14, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::GLOBAL_STORE_DWORD_ADDTID_gfx10: {
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::GLOBAL_STORE_DWORD_ADDTID_SADDR_gfx11: {
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 14, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::GLOBAL_STORE_DWORD_ADDTID_SADDR_gfx10: {
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: saddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 48, 7);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      break;
    }
    case AMDGPU::IMAGE_BVH_INTERSECT_RAY_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      break;
    }
    case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      break;
    }
    case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_sa_gfx10:
    case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_sa_gfx11:
    case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_sa_gfx10:
    case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_sa_gfx11:
    case AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_sa_gfx10:
    case AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_sa_gfx11:
    case AMDGPU::IMAGE_BVH_INTERSECT_RAY_sa_gfx10:
    case AMDGPU::IMAGE_BVH_INTERSECT_RAY_sa_gfx11: {
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      break;
    }
    case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_nsa_gfx11:
    case AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_nsa_gfx11: {
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      break;
    }
    case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_nsa_gfx11:
    case AMDGPU::IMAGE_BVH_INTERSECT_RAY_nsa_gfx11: {
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      break;
    }
    case AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_nsa_gfx10: {
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: srsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(5, 2), 48, 5);
      // op: vaddr0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      break;
    }
    case AMDGPU::V_SMFMAC_F32_16X16X128_BF8_BF8_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X128_BF8_FP8_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X128_FP8_BF8_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X128_FP8_FP8_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X32_BF16_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X32_F16_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X64_BF16_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X64_F16_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X16_BF16_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X16_F16_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X32_BF16_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X32_F16_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X64_BF8_BF8_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X64_BF8_FP8_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X64_FP8_BF8_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X64_FP8_FP8_gfx940:
    case AMDGPU::V_SMFMAC_I32_16X16X128_I8_gfx940:
    case AMDGPU::V_SMFMAC_I32_16X16X64_I8_gfx940:
    case AMDGPU::V_SMFMAC_I32_32X32X32_I8_gfx940:
    case AMDGPU::V_SMFMAC_I32_32X32X64_I8_gfx940: {
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 15, 1);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 59, 1);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getAVOperandEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 60, 1);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: idx
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: cbsz
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 8, 3);
      // op: abid
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 11, 4);
      break;
    }
    case AMDGPU::SCRATCH_LOAD_DWORDX2_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORD_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_SSHORT_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_USHORT_ST_gfx12: {
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::FLAT_LOAD_DWORDX2_gfx12:
    case AMDGPU::FLAT_LOAD_DWORDX3_gfx12:
    case AMDGPU::FLAT_LOAD_DWORDX4_gfx12:
    case AMDGPU::FLAT_LOAD_DWORD_gfx12:
    case AMDGPU::FLAT_LOAD_SBYTE_D16_HI_gfx12:
    case AMDGPU::FLAT_LOAD_SBYTE_D16_gfx12:
    case AMDGPU::FLAT_LOAD_SBYTE_gfx12:
    case AMDGPU::FLAT_LOAD_SHORT_D16_HI_gfx12:
    case AMDGPU::FLAT_LOAD_SHORT_D16_gfx12:
    case AMDGPU::FLAT_LOAD_SSHORT_gfx12:
    case AMDGPU::FLAT_LOAD_UBYTE_D16_HI_gfx12:
    case AMDGPU::FLAT_LOAD_UBYTE_D16_gfx12:
    case AMDGPU::FLAT_LOAD_UBYTE_gfx12:
    case AMDGPU::FLAT_LOAD_USHORT_gfx12:
    case AMDGPU::GLOBAL_LOAD_DWORDX2_gfx12:
    case AMDGPU::GLOBAL_LOAD_DWORDX3_gfx12:
    case AMDGPU::GLOBAL_LOAD_DWORDX4_gfx12:
    case AMDGPU::GLOBAL_LOAD_DWORD_gfx12:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_gfx12:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_gfx12:
    case AMDGPU::GLOBAL_LOAD_SBYTE_gfx12:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_gfx12:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_gfx12:
    case AMDGPU::GLOBAL_LOAD_SSHORT_gfx12:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_gfx12:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_gfx12:
    case AMDGPU::GLOBAL_LOAD_UBYTE_gfx12:
    case AMDGPU::GLOBAL_LOAD_USHORT_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX2_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORD_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_gfx12:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_gfx12:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_gfx12:
    case AMDGPU::SCRATCH_LOAD_SSHORT_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_gfx12:
    case AMDGPU::SCRATCH_LOAD_USHORT_gfx12: {
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::DS_BPERMUTE_FI_B32_gfx12: {
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: data0
      op.clearAllBits();
      getAVOperandEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_ORDERED_COUNT_gfx10:
    case AMDGPU::DS_ORDERED_COUNT_gfx11:
    case AMDGPU::DS_ORDERED_COUNT_gfx6_gfx7:
    case AMDGPU::DS_READ_B128_gfx12:
    case AMDGPU::DS_READ_B32_gfx12:
    case AMDGPU::DS_READ_B64_gfx12:
    case AMDGPU::DS_READ_B96_gfx12:
    case AMDGPU::DS_READ_I16_gfx12:
    case AMDGPU::DS_READ_I8_D16_HI_gfx12:
    case AMDGPU::DS_READ_I8_D16_gfx12:
    case AMDGPU::DS_READ_I8_gfx12:
    case AMDGPU::DS_READ_U16_D16_HI_gfx12:
    case AMDGPU::DS_READ_U16_D16_gfx12:
    case AMDGPU::DS_READ_U16_gfx12:
    case AMDGPU::DS_READ_U8_D16_HI_gfx12:
    case AMDGPU::DS_READ_U8_D16_gfx12:
    case AMDGPU::DS_READ_U8_gfx12:
    case AMDGPU::DS_SWIZZLE_B32_gfx12: {
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_READ2ST64_B32_gfx12:
    case AMDGPU::DS_READ2ST64_B64_gfx12:
    case AMDGPU::DS_READ2_B32_gfx12:
    case AMDGPU::DS_READ2_B64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: offset0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: offset1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 8, 8);
      break;
    }
    case AMDGPU::SCRATCH_LOAD_DWORDX2_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORD_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_SSHORT_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_USHORT_ST_gfx11: {
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 14, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::SCRATCH_LOAD_DWORDX2_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORD_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_SBYTE_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_SSHORT_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_UBYTE_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_USHORT_ST_gfx10: {
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::DS_APPEND_gfx10:
    case AMDGPU::DS_APPEND_gfx11:
    case AMDGPU::DS_APPEND_gfx6_gfx7:
    case AMDGPU::DS_CONSUME_gfx10:
    case AMDGPU::DS_CONSUME_gfx11:
    case AMDGPU::DS_CONSUME_gfx6_gfx7:
    case AMDGPU::DS_READ_ADDTID_B32_gfx10:
    case AMDGPU::DS_READ_ADDTID_B32_gfx11: {
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_READ_B128_gfx10:
    case AMDGPU::DS_READ_B128_gfx11:
    case AMDGPU::DS_READ_B128_gfx7:
    case AMDGPU::DS_READ_B32_gfx10:
    case AMDGPU::DS_READ_B32_gfx11:
    case AMDGPU::DS_READ_B32_gfx6_gfx7:
    case AMDGPU::DS_READ_B64_gfx10:
    case AMDGPU::DS_READ_B64_gfx11:
    case AMDGPU::DS_READ_B64_gfx6_gfx7:
    case AMDGPU::DS_READ_B96_gfx10:
    case AMDGPU::DS_READ_B96_gfx11:
    case AMDGPU::DS_READ_B96_gfx7:
    case AMDGPU::DS_READ_I16_gfx10:
    case AMDGPU::DS_READ_I16_gfx11:
    case AMDGPU::DS_READ_I16_gfx6_gfx7:
    case AMDGPU::DS_READ_I8_D16_HI_gfx10:
    case AMDGPU::DS_READ_I8_D16_HI_gfx11:
    case AMDGPU::DS_READ_I8_D16_gfx10:
    case AMDGPU::DS_READ_I8_D16_gfx11:
    case AMDGPU::DS_READ_I8_gfx10:
    case AMDGPU::DS_READ_I8_gfx11:
    case AMDGPU::DS_READ_I8_gfx6_gfx7:
    case AMDGPU::DS_READ_U16_D16_HI_gfx10:
    case AMDGPU::DS_READ_U16_D16_HI_gfx11:
    case AMDGPU::DS_READ_U16_D16_gfx10:
    case AMDGPU::DS_READ_U16_D16_gfx11:
    case AMDGPU::DS_READ_U16_gfx10:
    case AMDGPU::DS_READ_U16_gfx11:
    case AMDGPU::DS_READ_U16_gfx6_gfx7:
    case AMDGPU::DS_READ_U8_D16_HI_gfx10:
    case AMDGPU::DS_READ_U8_D16_HI_gfx11:
    case AMDGPU::DS_READ_U8_D16_gfx10:
    case AMDGPU::DS_READ_U8_D16_gfx11:
    case AMDGPU::DS_READ_U8_gfx10:
    case AMDGPU::DS_READ_U8_gfx11:
    case AMDGPU::DS_READ_U8_gfx6_gfx7:
    case AMDGPU::DS_SWIZZLE_B32_gfx10:
    case AMDGPU::DS_SWIZZLE_B32_gfx11:
    case AMDGPU::DS_SWIZZLE_B32_gfx6_gfx7: {
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_READ2ST64_B32_gfx10:
    case AMDGPU::DS_READ2ST64_B32_gfx11:
    case AMDGPU::DS_READ2ST64_B32_gfx6_gfx7:
    case AMDGPU::DS_READ2ST64_B64_gfx10:
    case AMDGPU::DS_READ2ST64_B64_gfx11:
    case AMDGPU::DS_READ2ST64_B64_gfx6_gfx7:
    case AMDGPU::DS_READ2_B32_gfx10:
    case AMDGPU::DS_READ2_B32_gfx11:
    case AMDGPU::DS_READ2_B32_gfx6_gfx7:
    case AMDGPU::DS_READ2_B64_gfx10:
    case AMDGPU::DS_READ2_B64_gfx11:
    case AMDGPU::DS_READ2_B64_gfx6_gfx7: {
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: offset0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: offset1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 8, 8);
      break;
    }
    case AMDGPU::DS_APPEND_gfx12:
    case AMDGPU::DS_CONSUME_gfx12:
    case AMDGPU::DS_READ_ADDTID_B32_gfx12: {
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_ORDERED_COUNT_vi: {
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 25, 1);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_APPEND_vi:
    case AMDGPU::DS_CONSUME_vi:
    case AMDGPU::DS_READ_ADDTID_B32_vi: {
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 25, 1);
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_READ_B128_vi:
    case AMDGPU::DS_READ_B128_vi_gfx9:
    case AMDGPU::DS_READ_B32_vi:
    case AMDGPU::DS_READ_B32_vi_gfx9:
    case AMDGPU::DS_READ_B64_TR_B16_vi:
    case AMDGPU::DS_READ_B64_TR_B4_vi:
    case AMDGPU::DS_READ_B64_TR_B8_vi:
    case AMDGPU::DS_READ_B64_vi:
    case AMDGPU::DS_READ_B64_vi_gfx9:
    case AMDGPU::DS_READ_B96_TR_B6_vi:
    case AMDGPU::DS_READ_B96_vi:
    case AMDGPU::DS_READ_B96_vi_gfx9:
    case AMDGPU::DS_READ_I16_vi:
    case AMDGPU::DS_READ_I16_vi_gfx9:
    case AMDGPU::DS_READ_I8_D16_HI_vi:
    case AMDGPU::DS_READ_I8_D16_vi:
    case AMDGPU::DS_READ_I8_vi:
    case AMDGPU::DS_READ_I8_vi_gfx9:
    case AMDGPU::DS_READ_U16_D16_HI_vi:
    case AMDGPU::DS_READ_U16_D16_vi:
    case AMDGPU::DS_READ_U16_vi:
    case AMDGPU::DS_READ_U16_vi_gfx9:
    case AMDGPU::DS_READ_U8_D16_HI_vi:
    case AMDGPU::DS_READ_U8_D16_vi:
    case AMDGPU::DS_READ_U8_vi:
    case AMDGPU::DS_READ_U8_vi_gfx9:
    case AMDGPU::DS_SWIZZLE_B32_vi: {
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 25, 1);
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_READ2ST64_B32_vi:
    case AMDGPU::DS_READ2ST64_B32_vi_gfx9:
    case AMDGPU::DS_READ2ST64_B64_vi:
    case AMDGPU::DS_READ2ST64_B64_vi_gfx9:
    case AMDGPU::DS_READ2_B32_vi:
    case AMDGPU::DS_READ2_B32_vi_gfx9:
    case AMDGPU::DS_READ2_B64_vi:
    case AMDGPU::DS_READ2_B64_vi_gfx9: {
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 25, 1);
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: offset0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: offset1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 8, 8);
      break;
    }
    case AMDGPU::SCRATCH_LOAD_DWORDX2_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_DWORD_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_SBYTE_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_SSHORT_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_UBYTE_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_USHORT_ST_gfx940: {
      // op: vdst
      op.clearAllBits();
      getAVOperandEncoding(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 55, 1);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 4), 25, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::V_BFREV_B32_e64_dpp_gfx11:
    case AMDGPU::V_BFREV_B32_e64_dpp_gfx12:
    case AMDGPU::V_CLS_I32_e64_dpp_gfx11:
    case AMDGPU::V_CLS_I32_e64_dpp_gfx12:
    case AMDGPU::V_CLZ_I32_U32_e64_dpp_gfx11:
    case AMDGPU::V_CLZ_I32_U32_e64_dpp_gfx12:
    case AMDGPU::V_CTZ_I32_B32_e64_dpp_gfx11:
    case AMDGPU::V_CTZ_I32_B32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MOVRELD_B32_e64_dpp_gfx11:
    case AMDGPU::V_MOVRELD_B32_e64_dpp_gfx12:
    case AMDGPU::V_MOVRELSD_2_B32_e64_dpp_gfx11:
    case AMDGPU::V_MOVRELSD_2_B32_e64_dpp_gfx12:
    case AMDGPU::V_MOVRELSD_B32_e64_dpp_gfx11:
    case AMDGPU::V_MOVRELSD_B32_e64_dpp_gfx12:
    case AMDGPU::V_MOVRELS_B32_e64_dpp_gfx11:
    case AMDGPU::V_MOVRELS_B32_e64_dpp_gfx12:
    case AMDGPU::V_MOV_B32_e64_dpp_gfx11:
    case AMDGPU::V_MOV_B32_e64_dpp_gfx12:
    case AMDGPU::V_MOV_B64_e64_dpp_gfx1250:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_NOT_B32_e64_dpp_gfx11:
    case AMDGPU::V_NOT_B32_e64_dpp_gfx12:
    case AMDGPU::V_PRNG_B32_e64_dpp_gfx1250:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e64_dpp_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 59, 1);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getAVOperandEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 60, 1);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: blgp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 61, 3);
      // op: cbsz
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 8, 3);
      break;
    }
    case AMDGPU::V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_16X16X16BF16_1K_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X16F16_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_16X16X16F16_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_16X16X16F16_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X16F16_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X16F16_vi:
    case AMDGPU::V_MFMA_F32_16X16X1F32_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_16X16X1F32_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_16X16X1F32_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X1F32_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X1F32_vi:
    case AMDGPU::V_MFMA_F32_16X16X2BF16_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_16X16X2BF16_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_16X16X2BF16_vi:
    case AMDGPU::V_MFMA_F32_16X16X32_BF16_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X32_BF16_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X32_F16_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X32_F16_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_16X16X4BF16_1K_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X4F16_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_16X16X4F16_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_16X16X4F16_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X4F16_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X4F16_vi:
    case AMDGPU::V_MFMA_F32_16X16X4F32_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_16X16X4F32_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_16X16X4F32_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X4F32_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X4F32_vi:
    case AMDGPU::V_MFMA_F32_16X16X8BF16_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_16X16X8BF16_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_16X16X8BF16_vi:
    case AMDGPU::V_MFMA_F32_16X16X8XF32_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X8XF32_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X16_BF16_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X16_BF16_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X16_F16_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X16_F16_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X1F32_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_32X32X1F32_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_32X32X1F32_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X1F32_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X1F32_vi:
    case AMDGPU::V_MFMA_F32_32X32X2BF16_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_32X32X2BF16_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_32X32X2BF16_vi:
    case AMDGPU::V_MFMA_F32_32X32X2F32_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_32X32X2F32_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_32X32X2F32_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X2F32_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X2F32_vi:
    case AMDGPU::V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_32X32X4BF16_1K_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X4BF16_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_32X32X4BF16_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_32X32X4BF16_vi:
    case AMDGPU::V_MFMA_F32_32X32X4F16_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_32X32X4F16_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_32X32X4F16_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X4F16_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X4F16_vi:
    case AMDGPU::V_MFMA_F32_32X32X4XF32_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X4XF32_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_32X32X8BF16_1K_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X8F16_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_32X32X8F16_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_32X32X8F16_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X8F16_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X8F16_vi:
    case AMDGPU::V_MFMA_F32_4X4X1F32_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_4X4X1F32_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_4X4X1F32_gfx940_acd:
    case AMDGPU::V_MFMA_F32_4X4X1F32_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_4X4X1F32_vi:
    case AMDGPU::V_MFMA_F32_4X4X2BF16_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_4X4X2BF16_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_4X4X2BF16_vi:
    case AMDGPU::V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_4X4X4BF16_1K_gfx940_acd:
    case AMDGPU::V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_4X4X4F16_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_4X4X4F16_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_4X4X4F16_gfx940_acd:
    case AMDGPU::V_MFMA_F32_4X4X4F16_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_4X4X4F16_vi:
    case AMDGPU::V_MFMA_F64_16X16X4F64_gfx90a_acd:
    case AMDGPU::V_MFMA_F64_16X16X4F64_gfx90a_vcd:
    case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:
    case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:
    case AMDGPU::V_MFMA_F64_4X4X4F64_gfx90a_acd:
    case AMDGPU::V_MFMA_F64_4X4X4F64_gfx90a_vcd:
    case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:
    case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:
    case AMDGPU::V_MFMA_I32_16X16X16I8_gfx90a_acd:
    case AMDGPU::V_MFMA_I32_16X16X16I8_gfx90a_vcd:
    case AMDGPU::V_MFMA_I32_16X16X16I8_vi:
    case AMDGPU::V_MFMA_I32_16X16X32I8_gfx940_acd:
    case AMDGPU::V_MFMA_I32_16X16X32I8_gfx940_vcd:
    case AMDGPU::V_MFMA_I32_16X16X4I8_gfx90a_acd:
    case AMDGPU::V_MFMA_I32_16X16X4I8_gfx90a_vcd:
    case AMDGPU::V_MFMA_I32_16X16X4I8_gfx940_acd:
    case AMDGPU::V_MFMA_I32_16X16X4I8_gfx940_vcd:
    case AMDGPU::V_MFMA_I32_16X16X4I8_vi:
    case AMDGPU::V_MFMA_I32_16X16X64_I8_gfx940_acd:
    case AMDGPU::V_MFMA_I32_16X16X64_I8_gfx940_vcd:
    case AMDGPU::V_MFMA_I32_32X32X16I8_gfx940_acd:
    case AMDGPU::V_MFMA_I32_32X32X16I8_gfx940_vcd:
    case AMDGPU::V_MFMA_I32_32X32X32_I8_gfx940_acd:
    case AMDGPU::V_MFMA_I32_32X32X32_I8_gfx940_vcd:
    case AMDGPU::V_MFMA_I32_32X32X4I8_gfx90a_acd:
    case AMDGPU::V_MFMA_I32_32X32X4I8_gfx90a_vcd:
    case AMDGPU::V_MFMA_I32_32X32X4I8_gfx940_acd:
    case AMDGPU::V_MFMA_I32_32X32X4I8_gfx940_vcd:
    case AMDGPU::V_MFMA_I32_32X32X4I8_vi:
    case AMDGPU::V_MFMA_I32_32X32X8I8_gfx90a_acd:
    case AMDGPU::V_MFMA_I32_32X32X8I8_gfx90a_vcd:
    case AMDGPU::V_MFMA_I32_32X32X8I8_vi:
    case AMDGPU::V_MFMA_I32_4X4X4I8_gfx90a_acd:
    case AMDGPU::V_MFMA_I32_4X4X4I8_gfx90a_vcd:
    case AMDGPU::V_MFMA_I32_4X4X4I8_gfx940_acd:
    case AMDGPU::V_MFMA_I32_4X4X4I8_gfx940_vcd:
    case AMDGPU::V_MFMA_I32_4X4X4I8_vi: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 59, 1);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getAVOperandEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 60, 1);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: blgp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 61, 3);
      // op: cbsz
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 8, 3);
      // op: abid
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 11, 4);
      break;
    }
    case AMDGPU::V_ACCVGPR_READ_B32_vi: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_ACCVGPR_WRITE_B32_vi: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: index_key_16bit
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      break;
    }
    case AMDGPU::V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: index_key_32bit
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      // op: matrix_a_reuse
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: matrix_b_reuse
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      break;
    }
    case AMDGPU::V_SWMMAC_F32_16X16X32_BF8_BF8_w64_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F32_16X16X32_BF8_FP8_w64_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F32_16X16X32_FP8_BF8_w64_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F32_16X16X32_FP8_FP8_w64_twoaddr_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: index_key_8bit
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 11, 2);
      break;
    }
    case AMDGPU::V_DOT4_F32_BF8_BF8_gfx12:
    case AMDGPU::V_DOT4_F32_BF8_FP8_gfx12:
    case AMDGPU::V_DOT4_F32_FP8_BF8_gfx12:
    case AMDGPU::V_DOT4_F32_FP8_FP8_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w64_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w64_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w64_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w64_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_32X16X128_F4_w32_twoaddr_gfx1250: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      break;
    }
    case AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_gfx1250: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: matrix_a_fmt
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 11, 3);
      // op: matrix_b_fmt
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 14, 1);
      break;
    }
    case AMDGPU::V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_gfx1250: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: matrix_a_reuse
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: matrix_b_reuse
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      break;
    }
    case AMDGPU::V_BFREV_B32_e64_dpp8_gfx11:
    case AMDGPU::V_BFREV_B32_e64_dpp8_gfx12:
    case AMDGPU::V_CLS_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CLS_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CLZ_I32_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CLZ_I32_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CTZ_I32_B32_e64_dpp8_gfx11:
    case AMDGPU::V_CTZ_I32_B32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MOVRELD_B32_e64_dpp8_gfx11:
    case AMDGPU::V_MOVRELD_B32_e64_dpp8_gfx12:
    case AMDGPU::V_MOVRELSD_2_B32_e64_dpp8_gfx11:
    case AMDGPU::V_MOVRELSD_2_B32_e64_dpp8_gfx12:
    case AMDGPU::V_MOVRELSD_B32_e64_dpp8_gfx11:
    case AMDGPU::V_MOVRELSD_B32_e64_dpp8_gfx12:
    case AMDGPU::V_MOVRELS_B32_e64_dpp8_gfx11:
    case AMDGPU::V_MOVRELS_B32_e64_dpp8_gfx12:
    case AMDGPU::V_MOV_B32_e64_dpp8_gfx11:
    case AMDGPU::V_MOV_B32_e64_dpp8_gfx12:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_NOT_B32_e64_dpp8_gfx11:
    case AMDGPU::V_NOT_B32_e64_dpp8_gfx12:
    case AMDGPU::V_PRNG_B32_e64_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e64_dpp8_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_ADD_I32_e64_gfx6_gfx7:
    case AMDGPU::V_SUBREV_I32_e64_gfx6_gfx7:
    case AMDGPU::V_SUB_I32_e64_gfx6_gfx7: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 8, 7);
      break;
    }
    case AMDGPU::V_ADD_CO_U32_e64_gfx10:
    case AMDGPU::V_ADD_CO_U32_e64_gfx11:
    case AMDGPU::V_ADD_CO_U32_e64_gfx12:
    case AMDGPU::V_ADD_CO_U32_e64_gfx9:
    case AMDGPU::V_ADD_U32_e64_vi:
    case AMDGPU::V_SUBREV_CO_U32_e64_gfx10:
    case AMDGPU::V_SUBREV_CO_U32_e64_gfx11:
    case AMDGPU::V_SUBREV_CO_U32_e64_gfx12:
    case AMDGPU::V_SUBREV_CO_U32_e64_gfx9:
    case AMDGPU::V_SUBREV_U32_e64_vi:
    case AMDGPU::V_SUB_CO_U32_e64_gfx10:
    case AMDGPU::V_SUB_CO_U32_e64_gfx11:
    case AMDGPU::V_SUB_CO_U32_e64_gfx12:
    case AMDGPU::V_SUB_CO_U32_e64_gfx9:
    case AMDGPU::V_SUB_U32_e64_vi: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 8, 7);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      break;
    }
    case AMDGPU::V_ADDC_U32_e64_gfx6_gfx7:
    case AMDGPU::V_MAD_I64_I32_gfx7:
    case AMDGPU::V_MAD_U64_U32_gfx7:
    case AMDGPU::V_SUBBREV_U32_e64_gfx6_gfx7:
    case AMDGPU::V_SUBB_U32_e64_gfx6_gfx7: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 8, 7);
      break;
    }
    case AMDGPU::V_ADDC_CO_U32_e64_gfx9:
    case AMDGPU::V_ADDC_U32_e64_vi:
    case AMDGPU::V_ADD_CO_CI_U32_e64_gfx10:
    case AMDGPU::V_ADD_CO_CI_U32_e64_gfx11:
    case AMDGPU::V_ADD_CO_CI_U32_e64_gfx12:
    case AMDGPU::V_MAD_CO_I64_I32_e64_gfx12:
    case AMDGPU::V_MAD_CO_U64_U32_e64_gfx12:
    case AMDGPU::V_MAD_I64_I32_gfx10:
    case AMDGPU::V_MAD_I64_I32_gfx11_e64_gfx11:
    case AMDGPU::V_MAD_I64_I32_vi:
    case AMDGPU::V_MAD_U64_U32_gfx10:
    case AMDGPU::V_MAD_U64_U32_gfx11_e64_gfx11:
    case AMDGPU::V_MAD_U64_U32_vi:
    case AMDGPU::V_SUBBREV_CO_U32_e64_gfx9:
    case AMDGPU::V_SUBBREV_U32_e64_vi:
    case AMDGPU::V_SUBB_CO_U32_e64_gfx9:
    case AMDGPU::V_SUBB_U32_e64_vi:
    case AMDGPU::V_SUBREV_CO_CI_U32_e64_gfx10:
    case AMDGPU::V_SUBREV_CO_CI_U32_e64_gfx11:
    case AMDGPU::V_SUBREV_CO_CI_U32_e64_gfx12:
    case AMDGPU::V_SUB_CO_CI_U32_e64_gfx10:
    case AMDGPU::V_SUB_CO_CI_U32_e64_gfx11:
    case AMDGPU::V_SUB_CO_CI_U32_e64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 8, 7);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      break;
    }
    case AMDGPU::V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx12:
    case AMDGPU::V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx12:
    case AMDGPU::V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      break;
    }
    case AMDGPU::V_WMMA_I32_16X16X64_IU8_w32_twoaddr_gfx1250: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: matrix_a_reuse
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: matrix_b_reuse
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      break;
    }
    case AMDGPU::V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      break;
    }
    case AMDGPU::V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: index_key_16bit
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      break;
    }
    case AMDGPU::V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_gfx1250: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: index_key_32bit
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      // op: matrix_a_reuse
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: matrix_b_reuse
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      break;
    }
    case AMDGPU::V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: index_key_8bit
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 11, 2);
      break;
    }
    case AMDGPU::V_WMMA_F32_16X16X4_F32_w32_twoaddr_gfx1250: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: matrix_a_reuse
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: matrix_b_reuse
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      break;
    }
    case AMDGPU::V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: index_key_16bit
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      break;
    }
    case AMDGPU::V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: index_key_16bit
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      // op: matrix_a_reuse
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: matrix_b_reuse
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      break;
    }
    case AMDGPU::V_SWMMAC_BF16_16X16X32_BF16_w64_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F16_16X16X32_F16_w64_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F32_16X16X32_BF16_w64_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F32_16X16X32_F16_w64_twoaddr_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: index_key_8bit
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 11, 2);
      break;
    }
    case AMDGPU::V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_BF16_16X16X16_BF16_w64_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F16_16X16X16_F16_w64_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_BF16_twoaddr_w32_gfx11:
    case AMDGPU::V_WMMA_F32_16X16X16_BF16_twoaddr_w64_gfx11:
    case AMDGPU::V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_BF16_w64_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_F16_twoaddr_w32_gfx11:
    case AMDGPU::V_WMMA_F32_16X16X16_F16_twoaddr_w64_gfx11:
    case AMDGPU::V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_F16_w64_twoaddr_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      break;
    }
    case AMDGPU::V_DOT4_I32_I8_gfx10:
    case AMDGPU::V_DOT4_I32_I8_vi:
    case AMDGPU::V_DOT4_I32_IU8_gfx11:
    case AMDGPU::V_DOT4_I32_IU8_gfx12:
    case AMDGPU::V_DOT4_U32_U8_gfx10:
    case AMDGPU::V_DOT4_U32_U8_gfx11:
    case AMDGPU::V_DOT4_U32_U8_gfx12:
    case AMDGPU::V_DOT4_U32_U8_vi:
    case AMDGPU::V_DOT8_I32_I4_gfx10:
    case AMDGPU::V_DOT8_I32_I4_vi:
    case AMDGPU::V_DOT8_I32_IU4_gfx11:
    case AMDGPU::V_DOT8_I32_IU4_gfx12:
    case AMDGPU::V_DOT8_U32_U4_gfx10:
    case AMDGPU::V_DOT8_U32_U4_gfx11:
    case AMDGPU::V_DOT8_U32_U4_gfx12:
    case AMDGPU::V_DOT8_U32_U4_vi:
    case AMDGPU::V_WMMA_I32_16X16X16_IU4_twoaddr_w32_gfx11:
    case AMDGPU::V_WMMA_I32_16X16X16_IU4_twoaddr_w64_gfx11:
    case AMDGPU::V_WMMA_I32_16X16X16_IU8_twoaddr_w32_gfx11:
    case AMDGPU::V_WMMA_I32_16X16X16_IU8_twoaddr_w64_gfx11: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      break;
    }
    case AMDGPU::V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: matrix_a_reuse
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: matrix_b_reuse
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      break;
    }
    case AMDGPU::V_INTERP_P10_F32_inreg_gfx11:
    case AMDGPU::V_INTERP_P10_F32_inreg_gfx12:
    case AMDGPU::V_INTERP_P2_F32_inreg_gfx11:
    case AMDGPU::V_INTERP_P2_F32_inreg_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: waitexp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 8, 3);
      break;
    }
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_t16_e64_gfx11:
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_t16_e64_gfx12:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_t16_e64_gfx11:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_t16_e64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      break;
    }
    case AMDGPU::V_PK_ADD_BF16_gfx1250:
    case AMDGPU::V_PK_ADD_F16_gfx10:
    case AMDGPU::V_PK_ADD_F16_gfx11:
    case AMDGPU::V_PK_ADD_F16_gfx12:
    case AMDGPU::V_PK_ADD_F16_vi:
    case AMDGPU::V_PK_ADD_F32_gfx12:
    case AMDGPU::V_PK_ADD_F32_vi:
    case AMDGPU::V_PK_ADD_I16_gfx10:
    case AMDGPU::V_PK_ADD_I16_gfx11:
    case AMDGPU::V_PK_ADD_I16_gfx12:
    case AMDGPU::V_PK_ADD_I16_vi:
    case AMDGPU::V_PK_ADD_U16_gfx10:
    case AMDGPU::V_PK_ADD_U16_gfx11:
    case AMDGPU::V_PK_ADD_U16_gfx12:
    case AMDGPU::V_PK_ADD_U16_vi:
    case AMDGPU::V_PK_ASHRREV_I16_gfx10:
    case AMDGPU::V_PK_ASHRREV_I16_gfx11:
    case AMDGPU::V_PK_ASHRREV_I16_gfx12:
    case AMDGPU::V_PK_ASHRREV_I16_vi:
    case AMDGPU::V_PK_LSHLREV_B16_gfx10:
    case AMDGPU::V_PK_LSHLREV_B16_gfx11:
    case AMDGPU::V_PK_LSHLREV_B16_gfx12:
    case AMDGPU::V_PK_LSHLREV_B16_vi:
    case AMDGPU::V_PK_LSHRREV_B16_gfx10:
    case AMDGPU::V_PK_LSHRREV_B16_gfx11:
    case AMDGPU::V_PK_LSHRREV_B16_gfx12:
    case AMDGPU::V_PK_LSHRREV_B16_vi:
    case AMDGPU::V_PK_MAXIMUM_F16_gfx12:
    case AMDGPU::V_PK_MAX_F16_gfx10:
    case AMDGPU::V_PK_MAX_F16_gfx11:
    case AMDGPU::V_PK_MAX_F16_vi:
    case AMDGPU::V_PK_MAX_I16_gfx10:
    case AMDGPU::V_PK_MAX_I16_gfx11:
    case AMDGPU::V_PK_MAX_I16_gfx12:
    case AMDGPU::V_PK_MAX_I16_vi:
    case AMDGPU::V_PK_MAX_NUM_BF16_gfx1250:
    case AMDGPU::V_PK_MAX_NUM_F16_gfx12:
    case AMDGPU::V_PK_MAX_U16_gfx10:
    case AMDGPU::V_PK_MAX_U16_gfx11:
    case AMDGPU::V_PK_MAX_U16_gfx12:
    case AMDGPU::V_PK_MAX_U16_vi:
    case AMDGPU::V_PK_MINIMUM_F16_gfx12:
    case AMDGPU::V_PK_MIN_F16_gfx10:
    case AMDGPU::V_PK_MIN_F16_gfx11:
    case AMDGPU::V_PK_MIN_F16_vi:
    case AMDGPU::V_PK_MIN_I16_gfx10:
    case AMDGPU::V_PK_MIN_I16_gfx11:
    case AMDGPU::V_PK_MIN_I16_gfx12:
    case AMDGPU::V_PK_MIN_I16_vi:
    case AMDGPU::V_PK_MIN_NUM_BF16_gfx1250:
    case AMDGPU::V_PK_MIN_NUM_F16_gfx12:
    case AMDGPU::V_PK_MIN_U16_gfx10:
    case AMDGPU::V_PK_MIN_U16_gfx11:
    case AMDGPU::V_PK_MIN_U16_gfx12:
    case AMDGPU::V_PK_MIN_U16_vi:
    case AMDGPU::V_PK_MOV_B32_vi:
    case AMDGPU::V_PK_MUL_BF16_gfx1250:
    case AMDGPU::V_PK_MUL_F16_gfx10:
    case AMDGPU::V_PK_MUL_F16_gfx11:
    case AMDGPU::V_PK_MUL_F16_gfx12:
    case AMDGPU::V_PK_MUL_F16_vi:
    case AMDGPU::V_PK_MUL_F32_gfx12:
    case AMDGPU::V_PK_MUL_F32_vi:
    case AMDGPU::V_PK_MUL_LO_U16_gfx10:
    case AMDGPU::V_PK_MUL_LO_U16_gfx11:
    case AMDGPU::V_PK_MUL_LO_U16_gfx12:
    case AMDGPU::V_PK_MUL_LO_U16_vi:
    case AMDGPU::V_PK_SUB_I16_gfx10:
    case AMDGPU::V_PK_SUB_I16_gfx11:
    case AMDGPU::V_PK_SUB_I16_gfx12:
    case AMDGPU::V_PK_SUB_I16_vi:
    case AMDGPU::V_PK_SUB_U16_gfx10:
    case AMDGPU::V_PK_SUB_U16_gfx11:
    case AMDGPU::V_PK_SUB_U16_gfx12:
    case AMDGPU::V_PK_SUB_U16_vi: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 59, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 60, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      break;
    }
    case AMDGPU::V_WMMA_BF16_16X16X16_BF16_twoaddr_w32_gfx11:
    case AMDGPU::V_WMMA_BF16_16X16X16_BF16_twoaddr_w64_gfx11:
    case AMDGPU::V_WMMA_F16_16X16X16_F16_twoaddr_w32_gfx11:
    case AMDGPU::V_WMMA_F16_16X16X16_F16_twoaddr_w64_gfx11: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 59, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 60, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 2), 13, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      break;
    }
    case AMDGPU::V_DOT2_F32_BF16_gfx11:
    case AMDGPU::V_DOT2_F32_BF16_gfx12:
    case AMDGPU::V_DOT2_F32_BF16_vi:
    case AMDGPU::V_DOT2_F32_F16_gfx10:
    case AMDGPU::V_DOT2_F32_F16_gfx11:
    case AMDGPU::V_DOT2_F32_F16_gfx12:
    case AMDGPU::V_DOT2_F32_F16_vi:
    case AMDGPU::V_DOT2_I32_I16_gfx10:
    case AMDGPU::V_DOT2_I32_I16_vi:
    case AMDGPU::V_DOT2_U32_U16_gfx10:
    case AMDGPU::V_DOT2_U32_U16_vi:
    case AMDGPU::V_FMA_MIXHI_BF16_gfx1250:
    case AMDGPU::V_FMA_MIXHI_F16_gfx10:
    case AMDGPU::V_FMA_MIXHI_F16_gfx11:
    case AMDGPU::V_FMA_MIXHI_F16_gfx12:
    case AMDGPU::V_FMA_MIXHI_F16_vi:
    case AMDGPU::V_FMA_MIXLO_BF16_gfx1250:
    case AMDGPU::V_FMA_MIXLO_F16_gfx10:
    case AMDGPU::V_FMA_MIXLO_F16_gfx11:
    case AMDGPU::V_FMA_MIXLO_F16_gfx12:
    case AMDGPU::V_FMA_MIXLO_F16_vi:
    case AMDGPU::V_FMA_MIX_F32_BF16_gfx1250:
    case AMDGPU::V_FMA_MIX_F32_gfx10:
    case AMDGPU::V_FMA_MIX_F32_gfx11:
    case AMDGPU::V_FMA_MIX_F32_gfx12:
    case AMDGPU::V_FMA_MIX_F32_vi:
    case AMDGPU::V_MAD_MIXHI_F16_vi:
    case AMDGPU::V_MAD_MIXLO_F16_vi:
    case AMDGPU::V_MAD_MIX_F32_vi:
    case AMDGPU::V_PK_ADD_MAX_I16_gfx1250:
    case AMDGPU::V_PK_ADD_MAX_U16_gfx1250:
    case AMDGPU::V_PK_ADD_MIN_I16_gfx1250:
    case AMDGPU::V_PK_ADD_MIN_U16_gfx1250:
    case AMDGPU::V_PK_FMA_BF16_gfx1250:
    case AMDGPU::V_PK_FMA_F16_gfx10:
    case AMDGPU::V_PK_FMA_F16_gfx11:
    case AMDGPU::V_PK_FMA_F16_gfx12:
    case AMDGPU::V_PK_FMA_F16_vi:
    case AMDGPU::V_PK_FMA_F32_gfx12:
    case AMDGPU::V_PK_FMA_F32_vi:
    case AMDGPU::V_PK_MAD_I16_gfx10:
    case AMDGPU::V_PK_MAD_I16_gfx11:
    case AMDGPU::V_PK_MAD_I16_gfx12:
    case AMDGPU::V_PK_MAD_I16_vi:
    case AMDGPU::V_PK_MAD_U16_gfx10:
    case AMDGPU::V_PK_MAD_U16_gfx11:
    case AMDGPU::V_PK_MAD_U16_gfx12:
    case AMDGPU::V_PK_MAD_U16_vi:
    case AMDGPU::V_PK_MAX3_I16_gfx1250:
    case AMDGPU::V_PK_MAX3_NUM_F16_gfx1250:
    case AMDGPU::V_PK_MAX3_U16_gfx1250:
    case AMDGPU::V_PK_MAXIMUM3_F16_gfx1250:
    case AMDGPU::V_PK_MAXIMUM3_F16_vi:
    case AMDGPU::V_PK_MIN3_I16_gfx1250:
    case AMDGPU::V_PK_MIN3_NUM_F16_gfx1250:
    case AMDGPU::V_PK_MIN3_U16_gfx1250:
    case AMDGPU::V_PK_MINIMUM3_F16_gfx1250:
    case AMDGPU::V_PK_MINIMUM3_F16_vi: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 59, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 60, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(2, 2), 13, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      break;
    }
    case AMDGPU::V_DIV_SCALE_F32_gfx6_gfx7:
    case AMDGPU::V_DIV_SCALE_F64_gfx6_gfx7: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 8, 7);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      break;
    }
    case AMDGPU::V_DIV_SCALE_F32_e64_gfx11:
    case AMDGPU::V_DIV_SCALE_F32_e64_gfx12:
    case AMDGPU::V_DIV_SCALE_F32_gfx10:
    case AMDGPU::V_DIV_SCALE_F32_vi:
    case AMDGPU::V_DIV_SCALE_F64_e64_gfx11:
    case AMDGPU::V_DIV_SCALE_F64_e64_gfx12:
    case AMDGPU::V_DIV_SCALE_F64_e64_gfx1250:
    case AMDGPU::V_DIV_SCALE_F64_gfx10:
    case AMDGPU::V_DIV_SCALE_F64_vi: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: sdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(7, 0), 8, 7);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      break;
    }
    case AMDGPU::V_DOT2_BF16_BF16_fake16_e64_gfx11:
    case AMDGPU::V_DOT2_BF16_BF16_fake16_e64_gfx12:
    case AMDGPU::V_DOT2_F16_F16_fake16_e64_gfx11:
    case AMDGPU::V_DOT2_F16_F16_fake16_e64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      break;
    }
    case AMDGPU::V_INTERP_P2_F16_F32_inreg_fake16_gfx11:
    case AMDGPU::V_INTERP_P2_F16_F32_inreg_fake16_gfx12:
    case AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_fake16_gfx11:
    case AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_fake16_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: waitexp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 8, 3);
      break;
    }
    case AMDGPU::V_INTERP_P10_F16_F32_inreg_fake16_gfx11:
    case AMDGPU::V_INTERP_P10_F16_F32_inreg_fake16_gfx12:
    case AMDGPU::V_INTERP_P10_F16_F32_inreg_t16_gfx11:
    case AMDGPU::V_INTERP_P10_F16_F32_inreg_t16_gfx12:
    case AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_fake16_gfx11:
    case AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_fake16_gfx12:
    case AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_t16_gfx11:
    case AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_t16_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: waitexp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 8, 3);
      break;
    }
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_t16_e64_gfx1250:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_e64_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_e64_gfx12:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_t16_e64_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_t16_e64_gfx1250:
    case AMDGPU::V_CVT_PK_F32_BF8_t16_e64_gfx12:
    case AMDGPU::V_CVT_PK_F32_FP8_t16_e64_gfx12:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_e64_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_e64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_e64_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_e64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      break;
    }
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_t16_e64_gfx11:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_t16_e64_gfx12:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_t16_e64_gfx11:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_t16_e64_gfx12:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_t16_e64_gfx11:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_t16_e64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      break;
    }
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_t16_e64_gfx11:
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_t16_e64_gfx12:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_t16_e64_gfx11:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_t16_e64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      break;
    }
    case AMDGPU::V_AND_B16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_AND_B16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_AND_B32_e64_dpp_gfx11:
    case AMDGPU::V_AND_B32_e64_dpp_gfx12:
    case AMDGPU::V_ASHRREV_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_ASHRREV_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_ASHRREV_I32_e64_dpp_gfx11:
    case AMDGPU::V_ASHRREV_I32_e64_dpp_gfx12:
    case AMDGPU::V_ASHRREV_I64_e64_dpp_gfx1250:
    case AMDGPU::V_BCNT_U32_B32_e64_dpp_gfx11:
    case AMDGPU::V_BCNT_U32_B32_e64_dpp_gfx12:
    case AMDGPU::V_BFM_B32_e64_dpp_gfx11:
    case AMDGPU::V_BFM_B32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_I16_I32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_I16_I32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_U16_U32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_U16_U32_e64_dpp_gfx12:
    case AMDGPU::V_LSHLREV_B16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_LSHLREV_B16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_LSHLREV_B32_e64_dpp_gfx11:
    case AMDGPU::V_LSHLREV_B32_e64_dpp_gfx12:
    case AMDGPU::V_LSHLREV_B64_e64_dpp_gfx12:
    case AMDGPU::V_LSHRREV_B16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_LSHRREV_B16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_LSHRREV_B32_e64_dpp_gfx11:
    case AMDGPU::V_LSHRREV_B32_e64_dpp_gfx12:
    case AMDGPU::V_LSHRREV_B64_e64_dpp_gfx1250:
    case AMDGPU::V_MAX_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAX_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAX_I32_e64_dpp_gfx11:
    case AMDGPU::V_MAX_I32_e64_dpp_gfx12:
    case AMDGPU::V_MAX_I64_e64_dpp_gfx1250:
    case AMDGPU::V_MAX_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAX_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAX_U32_e64_dpp_gfx11:
    case AMDGPU::V_MAX_U32_e64_dpp_gfx12:
    case AMDGPU::V_MAX_U64_e64_dpp_gfx1250:
    case AMDGPU::V_MBCNT_HI_U32_B32_e64_dpp_gfx11:
    case AMDGPU::V_MBCNT_HI_U32_B32_e64_dpp_gfx12:
    case AMDGPU::V_MBCNT_LO_U32_B32_e64_dpp_gfx11:
    case AMDGPU::V_MBCNT_LO_U32_B32_e64_dpp_gfx12:
    case AMDGPU::V_MIN_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MIN_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MIN_I32_e64_dpp_gfx11:
    case AMDGPU::V_MIN_I32_e64_dpp_gfx12:
    case AMDGPU::V_MIN_I64_e64_dpp_gfx1250:
    case AMDGPU::V_MIN_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MIN_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MIN_U32_e64_dpp_gfx11:
    case AMDGPU::V_MIN_U32_e64_dpp_gfx12:
    case AMDGPU::V_MIN_U64_e64_dpp_gfx1250:
    case AMDGPU::V_MUL_HI_I32_I24_e64_dpp_gfx11:
    case AMDGPU::V_MUL_HI_I32_I24_e64_dpp_gfx12:
    case AMDGPU::V_MUL_HI_I32_e64_dpp_gfx1250:
    case AMDGPU::V_MUL_HI_U32_U24_e64_dpp_gfx11:
    case AMDGPU::V_MUL_HI_U32_U24_e64_dpp_gfx12:
    case AMDGPU::V_MUL_HI_U32_e64_dpp_gfx1250:
    case AMDGPU::V_MUL_LO_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MUL_LO_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MUL_LO_U32_e64_dpp_gfx1250:
    case AMDGPU::V_OR_B16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_OR_B16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_OR_B32_e64_dpp_gfx11:
    case AMDGPU::V_OR_B32_e64_dpp_gfx12:
    case AMDGPU::V_XNOR_B32_e64_dpp_gfx11:
    case AMDGPU::V_XNOR_B32_e64_dpp_gfx12:
    case AMDGPU::V_XOR_B16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_XOR_B16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_XOR_B32_e64_dpp_gfx11:
    case AMDGPU::V_XOR_B32_e64_dpp_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_AND_B16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_AND_B16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_AND_B32_e64_dpp8_gfx11:
    case AMDGPU::V_AND_B32_e64_dpp8_gfx12:
    case AMDGPU::V_ASHRREV_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_ASHRREV_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_ASHRREV_I32_e64_dpp8_gfx11:
    case AMDGPU::V_ASHRREV_I32_e64_dpp8_gfx12:
    case AMDGPU::V_BCNT_U32_B32_e64_dpp8_gfx11:
    case AMDGPU::V_BCNT_U32_B32_e64_dpp8_gfx12:
    case AMDGPU::V_BFM_B32_e64_dpp8_gfx11:
    case AMDGPU::V_BFM_B32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_I16_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_I16_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_U16_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_U16_U32_e64_dpp8_gfx12:
    case AMDGPU::V_LSHLREV_B16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_LSHLREV_B16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_LSHLREV_B32_e64_dpp8_gfx11:
    case AMDGPU::V_LSHLREV_B32_e64_dpp8_gfx12:
    case AMDGPU::V_LSHRREV_B16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_LSHRREV_B16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_LSHRREV_B32_e64_dpp8_gfx11:
    case AMDGPU::V_LSHRREV_B32_e64_dpp8_gfx12:
    case AMDGPU::V_MAX_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX_I32_e64_dpp8_gfx11:
    case AMDGPU::V_MAX_I32_e64_dpp8_gfx12:
    case AMDGPU::V_MAX_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX_U32_e64_dpp8_gfx11:
    case AMDGPU::V_MAX_U32_e64_dpp8_gfx12:
    case AMDGPU::V_MBCNT_HI_U32_B32_e64_dpp8_gfx11:
    case AMDGPU::V_MBCNT_HI_U32_B32_e64_dpp8_gfx12:
    case AMDGPU::V_MBCNT_LO_U32_B32_e64_dpp8_gfx11:
    case AMDGPU::V_MBCNT_LO_U32_B32_e64_dpp8_gfx12:
    case AMDGPU::V_MIN_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN_I32_e64_dpp8_gfx11:
    case AMDGPU::V_MIN_I32_e64_dpp8_gfx12:
    case AMDGPU::V_MIN_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN_U32_e64_dpp8_gfx11:
    case AMDGPU::V_MIN_U32_e64_dpp8_gfx12:
    case AMDGPU::V_MUL_HI_I32_I24_e64_dpp8_gfx11:
    case AMDGPU::V_MUL_HI_I32_I24_e64_dpp8_gfx12:
    case AMDGPU::V_MUL_HI_U32_U24_e64_dpp8_gfx11:
    case AMDGPU::V_MUL_HI_U32_U24_e64_dpp8_gfx12:
    case AMDGPU::V_MUL_LO_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MUL_LO_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_OR_B16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_OR_B16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_OR_B32_e64_dpp8_gfx11:
    case AMDGPU::V_OR_B32_e64_dpp8_gfx12:
    case AMDGPU::V_XNOR_B32_e64_dpp8_gfx11:
    case AMDGPU::V_XNOR_B32_e64_dpp8_gfx12:
    case AMDGPU::V_XOR_B16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_XOR_B16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_XOR_B32_e64_dpp8_gfx11:
    case AMDGPU::V_XOR_B32_e64_dpp8_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_ADD3_U32_e64_dpp_gfx11:
    case AMDGPU::V_ADD3_U32_e64_dpp_gfx12:
    case AMDGPU::V_ADD_LSHL_U32_e64_dpp_gfx11:
    case AMDGPU::V_ADD_LSHL_U32_e64_dpp_gfx12:
    case AMDGPU::V_AND_OR_B32_e64_dpp_gfx11:
    case AMDGPU::V_AND_OR_B32_e64_dpp_gfx12:
    case AMDGPU::V_BFE_I32_e64_dpp_gfx11:
    case AMDGPU::V_BFE_I32_e64_dpp_gfx12:
    case AMDGPU::V_BFE_U32_e64_dpp_gfx11:
    case AMDGPU::V_BFE_U32_e64_dpp_gfx12:
    case AMDGPU::V_BFI_B32_e64_dpp_gfx11:
    case AMDGPU::V_BFI_B32_e64_dpp_gfx12:
    case AMDGPU::V_LERP_U8_e64_dpp_gfx11:
    case AMDGPU::V_LERP_U8_e64_dpp_gfx12:
    case AMDGPU::V_LSHL_ADD_U32_e64_dpp_gfx11:
    case AMDGPU::V_LSHL_ADD_U32_e64_dpp_gfx12:
    case AMDGPU::V_LSHL_ADD_U64_e64_dpp_gfx1250:
    case AMDGPU::V_LSHL_OR_B32_e64_dpp_gfx11:
    case AMDGPU::V_LSHL_OR_B32_e64_dpp_gfx12:
    case AMDGPU::V_MAD_U32_e64_dpp_gfx1250:
    case AMDGPU::V_MAX3_I32_e64_dpp_gfx11:
    case AMDGPU::V_MAX3_I32_e64_dpp_gfx12:
    case AMDGPU::V_MAX3_U32_e64_dpp_gfx11:
    case AMDGPU::V_MAX3_U32_e64_dpp_gfx12:
    case AMDGPU::V_MAXMIN_I32_e64_dpp_gfx11:
    case AMDGPU::V_MAXMIN_I32_e64_dpp_gfx12:
    case AMDGPU::V_MAXMIN_U32_e64_dpp_gfx11:
    case AMDGPU::V_MAXMIN_U32_e64_dpp_gfx12:
    case AMDGPU::V_MED3_I32_e64_dpp_gfx11:
    case AMDGPU::V_MED3_I32_e64_dpp_gfx12:
    case AMDGPU::V_MED3_U32_e64_dpp_gfx11:
    case AMDGPU::V_MED3_U32_e64_dpp_gfx12:
    case AMDGPU::V_MIN3_I32_e64_dpp_gfx11:
    case AMDGPU::V_MIN3_I32_e64_dpp_gfx12:
    case AMDGPU::V_MIN3_U32_e64_dpp_gfx11:
    case AMDGPU::V_MIN3_U32_e64_dpp_gfx12:
    case AMDGPU::V_MINMAX_I32_e64_dpp_gfx11:
    case AMDGPU::V_MINMAX_I32_e64_dpp_gfx12:
    case AMDGPU::V_MINMAX_U32_e64_dpp_gfx11:
    case AMDGPU::V_MINMAX_U32_e64_dpp_gfx12:
    case AMDGPU::V_OR3_B32_e64_dpp_gfx11:
    case AMDGPU::V_OR3_B32_e64_dpp_gfx12:
    case AMDGPU::V_PERM_B32_e64_dpp_gfx11:
    case AMDGPU::V_PERM_B32_e64_dpp_gfx12:
    case AMDGPU::V_XAD_U32_e64_dpp_gfx11:
    case AMDGPU::V_XAD_U32_e64_dpp_gfx12:
    case AMDGPU::V_XOR3_B32_e64_dpp_gfx11:
    case AMDGPU::V_XOR3_B32_e64_dpp_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      break;
    }
    case AMDGPU::V_BITOP3_B32_e64_dpp_gfx1250: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: dpp_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 72, 9);
      // op: bound_ctrl
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 83, 1);
      // op: bank_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 88, 4);
      // op: row_mask
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 92, 4);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 82, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: bitop3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 61, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 6), 59, 2);
      Value.insertBits(op.extractBitsAsZExtValue(3, 3), 8, 3);
      break;
    }
    case AMDGPU::V_ADD3_U32_e64_dpp8_gfx11:
    case AMDGPU::V_ADD3_U32_e64_dpp8_gfx12:
    case AMDGPU::V_ADD_LSHL_U32_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_LSHL_U32_e64_dpp8_gfx12:
    case AMDGPU::V_AND_OR_B32_e64_dpp8_gfx11:
    case AMDGPU::V_AND_OR_B32_e64_dpp8_gfx12:
    case AMDGPU::V_BFE_I32_e64_dpp8_gfx11:
    case AMDGPU::V_BFE_I32_e64_dpp8_gfx12:
    case AMDGPU::V_BFE_U32_e64_dpp8_gfx11:
    case AMDGPU::V_BFE_U32_e64_dpp8_gfx12:
    case AMDGPU::V_BFI_B32_e64_dpp8_gfx11:
    case AMDGPU::V_BFI_B32_e64_dpp8_gfx12:
    case AMDGPU::V_LERP_U8_e64_dpp8_gfx11:
    case AMDGPU::V_LERP_U8_e64_dpp8_gfx12:
    case AMDGPU::V_LSHL_ADD_U32_e64_dpp8_gfx11:
    case AMDGPU::V_LSHL_ADD_U32_e64_dpp8_gfx12:
    case AMDGPU::V_LSHL_OR_B32_e64_dpp8_gfx11:
    case AMDGPU::V_LSHL_OR_B32_e64_dpp8_gfx12:
    case AMDGPU::V_MAX3_I32_e64_dpp8_gfx11:
    case AMDGPU::V_MAX3_I32_e64_dpp8_gfx12:
    case AMDGPU::V_MAX3_U32_e64_dpp8_gfx11:
    case AMDGPU::V_MAX3_U32_e64_dpp8_gfx12:
    case AMDGPU::V_MAXMIN_I32_e64_dpp8_gfx11:
    case AMDGPU::V_MAXMIN_I32_e64_dpp8_gfx12:
    case AMDGPU::V_MAXMIN_U32_e64_dpp8_gfx11:
    case AMDGPU::V_MAXMIN_U32_e64_dpp8_gfx12:
    case AMDGPU::V_MED3_I32_e64_dpp8_gfx11:
    case AMDGPU::V_MED3_I32_e64_dpp8_gfx12:
    case AMDGPU::V_MED3_U32_e64_dpp8_gfx11:
    case AMDGPU::V_MED3_U32_e64_dpp8_gfx12:
    case AMDGPU::V_MIN3_I32_e64_dpp8_gfx11:
    case AMDGPU::V_MIN3_I32_e64_dpp8_gfx12:
    case AMDGPU::V_MIN3_U32_e64_dpp8_gfx11:
    case AMDGPU::V_MIN3_U32_e64_dpp8_gfx12:
    case AMDGPU::V_MINMAX_I32_e64_dpp8_gfx11:
    case AMDGPU::V_MINMAX_I32_e64_dpp8_gfx12:
    case AMDGPU::V_MINMAX_U32_e64_dpp8_gfx11:
    case AMDGPU::V_MINMAX_U32_e64_dpp8_gfx12:
    case AMDGPU::V_OR3_B32_e64_dpp8_gfx11:
    case AMDGPU::V_OR3_B32_e64_dpp8_gfx12:
    case AMDGPU::V_PERM_B32_e64_dpp8_gfx11:
    case AMDGPU::V_PERM_B32_e64_dpp8_gfx12:
    case AMDGPU::V_XAD_U32_e64_dpp8_gfx11:
    case AMDGPU::V_XAD_U32_e64_dpp8_gfx12:
    case AMDGPU::V_XOR3_B32_e64_dpp8_gfx11:
    case AMDGPU::V_XOR3_B32_e64_dpp8_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_BITOP3_B32_e64_dpp8_gfx1250: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: dpp8
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      // op: fi
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: bitop3
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 61, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 6), 59, 2);
      Value.insertBits(op.extractBitsAsZExtValue(3, 3), 8, 3);
      break;
    }
    case AMDGPU::V_ACCVGPR_MOV_B32_vi: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src0
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      break;
    }
    case AMDGPU::V_BFREV_B32_e32_gfx10:
    case AMDGPU::V_BFREV_B32_e32_gfx11:
    case AMDGPU::V_BFREV_B32_e32_gfx12:
    case AMDGPU::V_BFREV_B32_e32_gfx6_gfx7:
    case AMDGPU::V_BFREV_B32_e32_vi:
    case AMDGPU::V_CEIL_F16_e32_gfx10:
    case AMDGPU::V_CEIL_F16_e32_vi:
    case AMDGPU::V_CEIL_F16_fake16_e32_gfx11:
    case AMDGPU::V_CEIL_F16_fake16_e32_gfx12:
    case AMDGPU::V_CEIL_F32_e32_gfx10:
    case AMDGPU::V_CEIL_F32_e32_gfx11:
    case AMDGPU::V_CEIL_F32_e32_gfx12:
    case AMDGPU::V_CEIL_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CEIL_F32_e32_vi:
    case AMDGPU::V_CEIL_F64_e32_gfx10:
    case AMDGPU::V_CEIL_F64_e32_gfx11:
    case AMDGPU::V_CEIL_F64_e32_gfx12:
    case AMDGPU::V_CEIL_F64_e32_gfx7:
    case AMDGPU::V_CEIL_F64_e32_vi:
    case AMDGPU::V_CLS_I32_e32_gfx11:
    case AMDGPU::V_CLS_I32_e32_gfx12:
    case AMDGPU::V_CLZ_I32_U32_e32_gfx11:
    case AMDGPU::V_CLZ_I32_U32_e32_gfx12:
    case AMDGPU::V_COS_BF16V_COS_BF16_fake16_e32_gfx1250:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_e32_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_e32_gfx12:
    case AMDGPU::V_COS_F16_e32_gfx10:
    case AMDGPU::V_COS_F16_e32_vi:
    case AMDGPU::V_COS_F32_e32_gfx10:
    case AMDGPU::V_COS_F32_e32_gfx11:
    case AMDGPU::V_COS_F32_e32_gfx12:
    case AMDGPU::V_COS_F32_e32_gfx6_gfx7:
    case AMDGPU::V_COS_F32_e32_vi:
    case AMDGPU::V_CTZ_I32_B32_e32_gfx11:
    case AMDGPU::V_CTZ_I32_B32_e32_gfx12:
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_fake16_e32_gfx1250:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_e32_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_e32_gfx12:
    case AMDGPU::V_CVT_F16_F32_e32_gfx10:
    case AMDGPU::V_CVT_F16_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F16_F32_e32_vi:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_fake16_e32_gfx1250:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_e32_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_e32_gfx12:
    case AMDGPU::V_CVT_F16_I16_e32_gfx10:
    case AMDGPU::V_CVT_F16_I16_e32_vi:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_e32_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_e32_gfx12:
    case AMDGPU::V_CVT_F16_U16_e32_gfx10:
    case AMDGPU::V_CVT_F16_U16_e32_vi:
    case AMDGPU::V_CVT_F32_BF16_e32_vi:
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_fake16_e32_gfx1250:
    case AMDGPU::V_CVT_F32_BF8_e32_gfx12:
    case AMDGPU::V_CVT_F32_BF8_e32_vi:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_e32_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_e32_gfx12:
    case AMDGPU::V_CVT_F32_F16_e32_gfx10:
    case AMDGPU::V_CVT_F32_F16_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_F16_e32_vi:
    case AMDGPU::V_CVT_F32_F64_e32_gfx10:
    case AMDGPU::V_CVT_F32_F64_e32_gfx11:
    case AMDGPU::V_CVT_F32_F64_e32_gfx12:
    case AMDGPU::V_CVT_F32_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_F64_e32_vi:
    case AMDGPU::V_CVT_F32_FP8_e32_gfx11:
    case AMDGPU::V_CVT_F32_FP8_e32_gfx12:
    case AMDGPU::V_CVT_F32_FP8_e32_gfx1250:
    case AMDGPU::V_CVT_F32_FP8_e32_vi:
    case AMDGPU::V_CVT_F32_I32_e32_gfx10:
    case AMDGPU::V_CVT_F32_I32_e32_gfx11:
    case AMDGPU::V_CVT_F32_I32_e32_gfx12:
    case AMDGPU::V_CVT_F32_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_I32_e32_vi:
    case AMDGPU::V_CVT_F32_U32_e32_gfx10:
    case AMDGPU::V_CVT_F32_U32_e32_gfx11:
    case AMDGPU::V_CVT_F32_U32_e32_gfx12:
    case AMDGPU::V_CVT_F32_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_U32_e32_vi:
    case AMDGPU::V_CVT_F32_UBYTE0_e32_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE0_e32_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE0_e32_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE0_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_UBYTE0_e32_vi:
    case AMDGPU::V_CVT_F32_UBYTE1_e32_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE1_e32_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE1_e32_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE1_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_UBYTE1_e32_vi:
    case AMDGPU::V_CVT_F32_UBYTE2_e32_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE2_e32_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE2_e32_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE2_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_UBYTE2_e32_vi:
    case AMDGPU::V_CVT_F32_UBYTE3_e32_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE3_e32_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE3_e32_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE3_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_UBYTE3_e32_vi:
    case AMDGPU::V_CVT_F64_F32_e32_gfx10:
    case AMDGPU::V_CVT_F64_F32_e32_gfx11:
    case AMDGPU::V_CVT_F64_F32_e32_gfx12:
    case AMDGPU::V_CVT_F64_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F64_F32_e32_vi:
    case AMDGPU::V_CVT_F64_I32_e32_gfx10:
    case AMDGPU::V_CVT_F64_I32_e32_gfx11:
    case AMDGPU::V_CVT_F64_I32_e32_gfx12:
    case AMDGPU::V_CVT_F64_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F64_I32_e32_vi:
    case AMDGPU::V_CVT_F64_U32_e32_gfx10:
    case AMDGPU::V_CVT_F64_U32_e32_gfx11:
    case AMDGPU::V_CVT_F64_U32_e32_gfx12:
    case AMDGPU::V_CVT_F64_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F64_U32_e32_vi:
    case AMDGPU::V_CVT_FLOOR_I32_F32_e32_gfx11:
    case AMDGPU::V_CVT_FLOOR_I32_F32_e32_gfx12:
    case AMDGPU::V_CVT_FLR_I32_F32_e32_gfx10:
    case AMDGPU::V_CVT_FLR_I32_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_FLR_I32_F32_e32_vi:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_e32_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_e32_gfx12:
    case AMDGPU::V_CVT_I16_F16_e32_gfx10:
    case AMDGPU::V_CVT_I16_F16_e32_vi:
    case AMDGPU::V_CVT_I32_F32_e32_gfx10:
    case AMDGPU::V_CVT_I32_F32_e32_gfx11:
    case AMDGPU::V_CVT_I32_F32_e32_gfx12:
    case AMDGPU::V_CVT_I32_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_I32_F32_e32_vi:
    case AMDGPU::V_CVT_I32_F64_e32_gfx10:
    case AMDGPU::V_CVT_I32_F64_e32_gfx11:
    case AMDGPU::V_CVT_I32_F64_e32_gfx12:
    case AMDGPU::V_CVT_I32_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_I32_F64_e32_vi:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_e32_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_e32_gfx12:
    case AMDGPU::V_CVT_NEAREST_I32_F32_e32_gfx11:
    case AMDGPU::V_CVT_NEAREST_I32_F32_e32_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e32_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e32_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16_e32_gfx10:
    case AMDGPU::V_CVT_NORM_I16_F16_e32_vi:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e32_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e32_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16_e32_gfx10:
    case AMDGPU::V_CVT_NORM_U16_F16_e32_vi:
    case AMDGPU::V_CVT_OFF_F32_I4_e32_gfx10:
    case AMDGPU::V_CVT_OFF_F32_I4_e32_gfx11:
    case AMDGPU::V_CVT_OFF_F32_I4_e32_gfx12:
    case AMDGPU::V_CVT_OFF_F32_I4_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_OFF_F32_I4_e32_vi:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_fake16_e32_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_fake16_e32_gfx1250:
    case AMDGPU::V_CVT_PK_F32_BF8_e32_vi:
    case AMDGPU::V_CVT_PK_F32_BF8_fake16_e32_gfx12:
    case AMDGPU::V_CVT_PK_F32_FP8_e32_vi:
    case AMDGPU::V_CVT_PK_F32_FP8_fake16_e32_gfx12:
    case AMDGPU::V_CVT_RPI_I32_F32_e32_gfx10:
    case AMDGPU::V_CVT_RPI_I32_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_RPI_I32_F32_e32_vi:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_e32_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_e32_gfx12:
    case AMDGPU::V_CVT_U16_F16_e32_gfx10:
    case AMDGPU::V_CVT_U16_F16_e32_vi:
    case AMDGPU::V_CVT_U32_F32_e32_gfx10:
    case AMDGPU::V_CVT_U32_F32_e32_gfx11:
    case AMDGPU::V_CVT_U32_F32_e32_gfx12:
    case AMDGPU::V_CVT_U32_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_U32_F32_e32_vi:
    case AMDGPU::V_CVT_U32_F64_e32_gfx10:
    case AMDGPU::V_CVT_U32_F64_e32_gfx11:
    case AMDGPU::V_CVT_U32_F64_e32_gfx12:
    case AMDGPU::V_CVT_U32_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_U32_F64_e32_vi:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_e32_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_e32_gfx12:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_fake16_e32_gfx1250:
    case AMDGPU::V_EXP_F16_e32_gfx10:
    case AMDGPU::V_EXP_F16_e32_vi:
    case AMDGPU::V_EXP_F16_fake16_e32_gfx11:
    case AMDGPU::V_EXP_F16_fake16_e32_gfx12:
    case AMDGPU::V_EXP_F32_e32_gfx10:
    case AMDGPU::V_EXP_F32_e32_gfx11:
    case AMDGPU::V_EXP_F32_e32_gfx12:
    case AMDGPU::V_EXP_F32_e32_gfx6_gfx7:
    case AMDGPU::V_EXP_F32_e32_vi:
    case AMDGPU::V_EXP_LEGACY_F32_e32_gfx7:
    case AMDGPU::V_EXP_LEGACY_F32_e32_vi:
    case AMDGPU::V_FFBH_I32_e32_gfx10:
    case AMDGPU::V_FFBH_I32_e32_gfx6_gfx7:
    case AMDGPU::V_FFBH_I32_e32_vi:
    case AMDGPU::V_FFBH_U32_e32_gfx10:
    case AMDGPU::V_FFBH_U32_e32_gfx6_gfx7:
    case AMDGPU::V_FFBH_U32_e32_vi:
    case AMDGPU::V_FFBL_B32_e32_gfx10:
    case AMDGPU::V_FFBL_B32_e32_gfx6_gfx7:
    case AMDGPU::V_FFBL_B32_e32_vi:
    case AMDGPU::V_FLOOR_F16_e32_gfx10:
    case AMDGPU::V_FLOOR_F16_e32_vi:
    case AMDGPU::V_FLOOR_F16_fake16_e32_gfx11:
    case AMDGPU::V_FLOOR_F16_fake16_e32_gfx12:
    case AMDGPU::V_FLOOR_F32_e32_gfx10:
    case AMDGPU::V_FLOOR_F32_e32_gfx11:
    case AMDGPU::V_FLOOR_F32_e32_gfx12:
    case AMDGPU::V_FLOOR_F32_e32_gfx6_gfx7:
    case AMDGPU::V_FLOOR_F32_e32_vi:
    case AMDGPU::V_FLOOR_F64_e32_gfx10:
    case AMDGPU::V_FLOOR_F64_e32_gfx11:
    case AMDGPU::V_FLOOR_F64_e32_gfx12:
    case AMDGPU::V_FLOOR_F64_e32_gfx7:
    case AMDGPU::V_FLOOR_F64_e32_vi:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_e32_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_e32_gfx12:
    case AMDGPU::V_FRACT_F16_e32_gfx10:
    case AMDGPU::V_FRACT_F16_e32_vi:
    case AMDGPU::V_FRACT_F32_e32_gfx10:
    case AMDGPU::V_FRACT_F32_e32_gfx11:
    case AMDGPU::V_FRACT_F32_e32_gfx12:
    case AMDGPU::V_FRACT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_FRACT_F32_e32_vi:
    case AMDGPU::V_FRACT_F64_e32_gfx10:
    case AMDGPU::V_FRACT_F64_e32_gfx11:
    case AMDGPU::V_FRACT_F64_e32_gfx12:
    case AMDGPU::V_FRACT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_FRACT_F64_e32_vi:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e32_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e32_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16_e32_gfx10:
    case AMDGPU::V_FREXP_EXP_I16_F16_e32_vi:
    case AMDGPU::V_FREXP_EXP_I32_F32_e32_gfx10:
    case AMDGPU::V_FREXP_EXP_I32_F32_e32_gfx11:
    case AMDGPU::V_FREXP_EXP_I32_F32_e32_gfx12:
    case AMDGPU::V_FREXP_EXP_I32_F32_e32_gfx6_gfx7:
    case AMDGPU::V_FREXP_EXP_I32_F32_e32_vi:
    case AMDGPU::V_FREXP_EXP_I32_F64_e32_gfx10:
    case AMDGPU::V_FREXP_EXP_I32_F64_e32_gfx11:
    case AMDGPU::V_FREXP_EXP_I32_F64_e32_gfx12:
    case AMDGPU::V_FREXP_EXP_I32_F64_e32_gfx6_gfx7:
    case AMDGPU::V_FREXP_EXP_I32_F64_e32_vi:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e32_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e32_gfx12:
    case AMDGPU::V_FREXP_MANT_F16_e32_gfx10:
    case AMDGPU::V_FREXP_MANT_F16_e32_vi:
    case AMDGPU::V_FREXP_MANT_F32_e32_gfx10:
    case AMDGPU::V_FREXP_MANT_F32_e32_gfx11:
    case AMDGPU::V_FREXP_MANT_F32_e32_gfx12:
    case AMDGPU::V_FREXP_MANT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_FREXP_MANT_F32_e32_vi:
    case AMDGPU::V_FREXP_MANT_F64_e32_gfx10:
    case AMDGPU::V_FREXP_MANT_F64_e32_gfx11:
    case AMDGPU::V_FREXP_MANT_F64_e32_gfx12:
    case AMDGPU::V_FREXP_MANT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_FREXP_MANT_F64_e32_vi:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_fake16_e32_gfx1250:
    case AMDGPU::V_LOG_CLAMP_F32_e32_gfx6_gfx7:
    case AMDGPU::V_LOG_F16_e32_gfx10:
    case AMDGPU::V_LOG_F16_e32_vi:
    case AMDGPU::V_LOG_F16_fake16_e32_gfx11:
    case AMDGPU::V_LOG_F16_fake16_e32_gfx12:
    case AMDGPU::V_LOG_F32_e32_gfx10:
    case AMDGPU::V_LOG_F32_e32_gfx11:
    case AMDGPU::V_LOG_F32_e32_gfx12:
    case AMDGPU::V_LOG_F32_e32_gfx6_gfx7:
    case AMDGPU::V_LOG_F32_e32_vi:
    case AMDGPU::V_LOG_LEGACY_F32_e32_gfx7:
    case AMDGPU::V_LOG_LEGACY_F32_e32_vi:
    case AMDGPU::V_MOVRELD_B32_e32_gfx10:
    case AMDGPU::V_MOVRELD_B32_e32_gfx11:
    case AMDGPU::V_MOVRELD_B32_e32_gfx12:
    case AMDGPU::V_MOVRELD_B32_e32_gfx6_gfx7:
    case AMDGPU::V_MOVRELD_B32_e32_vi:
    case AMDGPU::V_MOVRELSD_2_B32_e32_gfx10:
    case AMDGPU::V_MOVRELSD_2_B32_e32_gfx11:
    case AMDGPU::V_MOVRELSD_2_B32_e32_gfx12:
    case AMDGPU::V_MOVRELSD_B32_e32_gfx10:
    case AMDGPU::V_MOVRELSD_B32_e32_gfx11:
    case AMDGPU::V_MOVRELSD_B32_e32_gfx12:
    case AMDGPU::V_MOVRELSD_B32_e32_gfx6_gfx7:
    case AMDGPU::V_MOVRELSD_B32_e32_vi:
    case AMDGPU::V_MOVRELS_B32_e32_gfx10:
    case AMDGPU::V_MOVRELS_B32_e32_gfx11:
    case AMDGPU::V_MOVRELS_B32_e32_gfx12:
    case AMDGPU::V_MOVRELS_B32_e32_gfx6_gfx7:
    case AMDGPU::V_MOVRELS_B32_e32_vi:
    case AMDGPU::V_MOV_B32_e32_gfx10:
    case AMDGPU::V_MOV_B32_e32_gfx11:
    case AMDGPU::V_MOV_B32_e32_gfx12:
    case AMDGPU::V_MOV_B32_e32_gfx6_gfx7:
    case AMDGPU::V_MOV_B32_e32_vi:
    case AMDGPU::V_MOV_B64_e32_gfx1250:
    case AMDGPU::V_MOV_B64_e32_vi:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_e32_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_e32_gfx12:
    case AMDGPU::V_NOT_B32_e32_gfx10:
    case AMDGPU::V_NOT_B32_e32_gfx11:
    case AMDGPU::V_NOT_B32_e32_gfx12:
    case AMDGPU::V_NOT_B32_e32_gfx6_gfx7:
    case AMDGPU::V_NOT_B32_e32_vi:
    case AMDGPU::V_PERMLANE64_B32_gfx11:
    case AMDGPU::V_PERMLANE64_B32_gfx12:
    case AMDGPU::V_PRNG_B32_e32_gfx1250:
    case AMDGPU::V_PRNG_B32_e32_vi:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_fake16_e32_gfx1250:
    case AMDGPU::V_RCP_CLAMP_F32_e32_gfx6_gfx7:
    case AMDGPU::V_RCP_CLAMP_F64_e32_gfx6_gfx7:
    case AMDGPU::V_RCP_F16_e32_gfx10:
    case AMDGPU::V_RCP_F16_e32_vi:
    case AMDGPU::V_RCP_F16_fake16_e32_gfx11:
    case AMDGPU::V_RCP_F16_fake16_e32_gfx12:
    case AMDGPU::V_RCP_F32_e32_gfx10:
    case AMDGPU::V_RCP_F32_e32_gfx11:
    case AMDGPU::V_RCP_F32_e32_gfx12:
    case AMDGPU::V_RCP_F32_e32_gfx6_gfx7:
    case AMDGPU::V_RCP_F32_e32_vi:
    case AMDGPU::V_RCP_F64_e32_gfx10:
    case AMDGPU::V_RCP_F64_e32_gfx11:
    case AMDGPU::V_RCP_F64_e32_gfx12:
    case AMDGPU::V_RCP_F64_e32_gfx6_gfx7:
    case AMDGPU::V_RCP_F64_e32_vi:
    case AMDGPU::V_RCP_IFLAG_F32_e32_gfx10:
    case AMDGPU::V_RCP_IFLAG_F32_e32_gfx11:
    case AMDGPU::V_RCP_IFLAG_F32_e32_gfx12:
    case AMDGPU::V_RCP_IFLAG_F32_e32_gfx6_gfx7:
    case AMDGPU::V_RCP_IFLAG_F32_e32_vi:
    case AMDGPU::V_RCP_LEGACY_F32_e32_gfx6_gfx7:
    case AMDGPU::V_READFIRSTLANE_B32_gfx10:
    case AMDGPU::V_READFIRSTLANE_B32_gfx11:
    case AMDGPU::V_READFIRSTLANE_B32_gfx12:
    case AMDGPU::V_READFIRSTLANE_B32_gfx6_gfx7:
    case AMDGPU::V_READFIRSTLANE_B32_vi:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_e32_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_e32_gfx12:
    case AMDGPU::V_RNDNE_F16_e32_gfx10:
    case AMDGPU::V_RNDNE_F16_e32_vi:
    case AMDGPU::V_RNDNE_F32_e32_gfx10:
    case AMDGPU::V_RNDNE_F32_e32_gfx11:
    case AMDGPU::V_RNDNE_F32_e32_gfx12:
    case AMDGPU::V_RNDNE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_RNDNE_F32_e32_vi:
    case AMDGPU::V_RNDNE_F64_e32_gfx10:
    case AMDGPU::V_RNDNE_F64_e32_gfx11:
    case AMDGPU::V_RNDNE_F64_e32_gfx12:
    case AMDGPU::V_RNDNE_F64_e32_gfx7:
    case AMDGPU::V_RNDNE_F64_e32_vi:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_fake16_e32_gfx1250:
    case AMDGPU::V_RSQ_CLAMP_F32_e32_gfx6_gfx7:
    case AMDGPU::V_RSQ_CLAMP_F64_e32_gfx6_gfx7:
    case AMDGPU::V_RSQ_F16_e32_gfx10:
    case AMDGPU::V_RSQ_F16_e32_vi:
    case AMDGPU::V_RSQ_F16_fake16_e32_gfx11:
    case AMDGPU::V_RSQ_F16_fake16_e32_gfx12:
    case AMDGPU::V_RSQ_F32_e32_gfx10:
    case AMDGPU::V_RSQ_F32_e32_gfx11:
    case AMDGPU::V_RSQ_F32_e32_gfx12:
    case AMDGPU::V_RSQ_F32_e32_gfx6_gfx7:
    case AMDGPU::V_RSQ_F32_e32_vi:
    case AMDGPU::V_RSQ_F64_e32_gfx10:
    case AMDGPU::V_RSQ_F64_e32_gfx11:
    case AMDGPU::V_RSQ_F64_e32_gfx12:
    case AMDGPU::V_RSQ_F64_e32_gfx6_gfx7:
    case AMDGPU::V_RSQ_F64_e32_vi:
    case AMDGPU::V_RSQ_LEGACY_F32_e32_gfx6_gfx7:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_fake16_e32_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_fake16_e32_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e32_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e32_gfx12:
    case AMDGPU::V_SAT_PK_U8_I16_e32_gfx10:
    case AMDGPU::V_SAT_PK_U8_I16_e32_vi:
    case AMDGPU::V_SCREEN_PARTITION_4SE_B32_e32_vi:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_fake16_e32_gfx1250:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_e32_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_e32_gfx12:
    case AMDGPU::V_SIN_F16_e32_gfx10:
    case AMDGPU::V_SIN_F16_e32_vi:
    case AMDGPU::V_SIN_F32_e32_gfx10:
    case AMDGPU::V_SIN_F32_e32_gfx11:
    case AMDGPU::V_SIN_F32_e32_gfx12:
    case AMDGPU::V_SIN_F32_e32_gfx6_gfx7:
    case AMDGPU::V_SIN_F32_e32_vi:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_fake16_e32_gfx1250:
    case AMDGPU::V_SQRT_F16_e32_gfx10:
    case AMDGPU::V_SQRT_F16_e32_vi:
    case AMDGPU::V_SQRT_F16_fake16_e32_gfx11:
    case AMDGPU::V_SQRT_F16_fake16_e32_gfx12:
    case AMDGPU::V_SQRT_F32_e32_gfx10:
    case AMDGPU::V_SQRT_F32_e32_gfx11:
    case AMDGPU::V_SQRT_F32_e32_gfx12:
    case AMDGPU::V_SQRT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_SQRT_F32_e32_vi:
    case AMDGPU::V_SQRT_F64_e32_gfx10:
    case AMDGPU::V_SQRT_F64_e32_gfx11:
    case AMDGPU::V_SQRT_F64_e32_gfx12:
    case AMDGPU::V_SQRT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_SQRT_F64_e32_vi:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_fake16_e32_gfx1250:
    case AMDGPU::V_TANH_F16V_TANH_F16_fake16_e32_gfx1250:
    case AMDGPU::V_TANH_F32_e32_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_e32_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_e32_gfx12:
    case AMDGPU::V_TRUNC_F16_e32_gfx10:
    case AMDGPU::V_TRUNC_F16_e32_vi:
    case AMDGPU::V_TRUNC_F32_e32_gfx10:
    case AMDGPU::V_TRUNC_F32_e32_gfx11:
    case AMDGPU::V_TRUNC_F32_e32_gfx12:
    case AMDGPU::V_TRUNC_F32_e32_gfx6_gfx7:
    case AMDGPU::V_TRUNC_F32_e32_vi:
    case AMDGPU::V_TRUNC_F64_e32_gfx10:
    case AMDGPU::V_TRUNC_F64_e32_gfx11:
    case AMDGPU::V_TRUNC_F64_e32_gfx12:
    case AMDGPU::V_TRUNC_F64_e32_gfx7:
    case AMDGPU::V_TRUNC_F64_e32_vi: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      break;
    }
    case AMDGPU::V_ADDC_CO_U32_e32_gfx9:
    case AMDGPU::V_ADDC_U32_e32_gfx6_gfx7:
    case AMDGPU::V_ADDC_U32_e32_vi:
    case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
    case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
    case AMDGPU::V_ADD_CO_CI_U32_e32_gfx12:
    case AMDGPU::V_ADD_CO_U32_e32_gfx9:
    case AMDGPU::V_ADD_F16_e32_gfx10:
    case AMDGPU::V_ADD_F16_e32_vi:
    case AMDGPU::V_ADD_F16_fake16_e32_gfx11:
    case AMDGPU::V_ADD_F16_fake16_e32_gfx12:
    case AMDGPU::V_ADD_F32_e32_gfx10:
    case AMDGPU::V_ADD_F32_e32_gfx11:
    case AMDGPU::V_ADD_F32_e32_gfx12:
    case AMDGPU::V_ADD_F32_e32_gfx6_gfx7:
    case AMDGPU::V_ADD_F32_e32_vi:
    case AMDGPU::V_ADD_F64_e32_gfx12:
    case AMDGPU::V_ADD_I32_e32_gfx6_gfx7:
    case AMDGPU::V_ADD_NC_U32_e32_gfx10:
    case AMDGPU::V_ADD_NC_U32_e32_gfx11:
    case AMDGPU::V_ADD_NC_U32_e32_gfx12:
    case AMDGPU::V_ADD_U16_e32_vi:
    case AMDGPU::V_ADD_U32_e32_gfx9:
    case AMDGPU::V_ADD_U32_e32_vi:
    case AMDGPU::V_ADD_U64_e32_gfx1250:
    case AMDGPU::V_AND_B32_e32_gfx10:
    case AMDGPU::V_AND_B32_e32_gfx11:
    case AMDGPU::V_AND_B32_e32_gfx12:
    case AMDGPU::V_AND_B32_e32_gfx6_gfx7:
    case AMDGPU::V_AND_B32_e32_vi:
    case AMDGPU::V_ASHRREV_I16_e32_vi:
    case AMDGPU::V_ASHRREV_I32_e32_gfx10:
    case AMDGPU::V_ASHRREV_I32_e32_gfx11:
    case AMDGPU::V_ASHRREV_I32_e32_gfx12:
    case AMDGPU::V_ASHRREV_I32_e32_gfx6_gfx7:
    case AMDGPU::V_ASHRREV_I32_e32_vi:
    case AMDGPU::V_ASHR_I32_e32_gfx6_gfx7:
    case AMDGPU::V_BCNT_U32_B32_e32_gfx6_gfx7:
    case AMDGPU::V_BFM_B32_e32_gfx6_gfx7:
    case AMDGPU::V_CNDMASK_B32_e32_gfx10:
    case AMDGPU::V_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
    case AMDGPU::V_CNDMASK_B32_e32_vi:
    case AMDGPU::V_CVT_PKACCUM_U8_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_PKNORM_I16_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_PKNORM_U16_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_PKRTZ_F16_F32_e32_gfx10:
    case AMDGPU::V_CVT_PKRTZ_F16_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_PK_I16_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_e32_gfx11:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_e32_gfx12:
    case AMDGPU::V_CVT_PK_U16_U32_e32_gfx6_gfx7:
    case AMDGPU::V_DOT2ACC_F32_F16_e32_gfx11:
    case AMDGPU::V_DOT2C_F32_BF16_e32_vi:
    case AMDGPU::V_DOT2C_F32_F16_e32_gfx10:
    case AMDGPU::V_DOT2C_F32_F16_e32_vi:
    case AMDGPU::V_DOT2C_I32_I16_e32_vi:
    case AMDGPU::V_DOT4C_I32_I8_e32_gfx10:
    case AMDGPU::V_DOT4C_I32_I8_e32_vi:
    case AMDGPU::V_DOT8C_I32_I4_e32_gfx10:
    case AMDGPU::V_DOT8C_I32_I4_e32_vi:
    case AMDGPU::V_FMAC_DX9_ZERO_F32_e32_gfx11:
    case AMDGPU::V_FMAC_F16_e32_gfx10:
    case AMDGPU::V_FMAC_F16_fake16_e32_gfx11:
    case AMDGPU::V_FMAC_F16_fake16_e32_gfx12:
    case AMDGPU::V_FMAC_F32_e32_gfx10:
    case AMDGPU::V_FMAC_F32_e32_gfx11:
    case AMDGPU::V_FMAC_F32_e32_gfx12:
    case AMDGPU::V_FMAC_F32_e32_vi:
    case AMDGPU::V_FMAC_F64_e32_gfx12:
    case AMDGPU::V_FMAC_F64_e32_gfx90a:
    case AMDGPU::V_FMAC_LEGACY_F32_e32_gfx10:
    case AMDGPU::V_LDEXP_F16_e32_gfx10:
    case AMDGPU::V_LDEXP_F16_e32_vi:
    case AMDGPU::V_LDEXP_F16_fake16_e32_gfx11:
    case AMDGPU::V_LDEXP_F16_fake16_e32_gfx12:
    case AMDGPU::V_LDEXP_F32_e32_gfx6_gfx7:
    case AMDGPU::V_LSHLREV_B16_e32_vi:
    case AMDGPU::V_LSHLREV_B32_e32_gfx10:
    case AMDGPU::V_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_LSHLREV_B32_e32_gfx6_gfx7:
    case AMDGPU::V_LSHLREV_B32_e32_vi:
    case AMDGPU::V_LSHLREV_B64_e32_gfx12:
    case AMDGPU::V_LSHL_B32_e32_gfx6_gfx7:
    case AMDGPU::V_LSHRREV_B16_e32_vi:
    case AMDGPU::V_LSHRREV_B32_e32_gfx10:
    case AMDGPU::V_LSHRREV_B32_e32_gfx11:
    case AMDGPU::V_LSHRREV_B32_e32_gfx12:
    case AMDGPU::V_LSHRREV_B32_e32_gfx6_gfx7:
    case AMDGPU::V_LSHRREV_B32_e32_vi:
    case AMDGPU::V_LSHR_B32_e32_gfx6_gfx7:
    case AMDGPU::V_MAC_F16_e32_vi:
    case AMDGPU::V_MAC_F32_e32_gfx10:
    case AMDGPU::V_MAC_F32_e32_gfx6_gfx7:
    case AMDGPU::V_MAC_F32_e32_vi:
    case AMDGPU::V_MAC_LEGACY_F32_e32_gfx10:
    case AMDGPU::V_MAC_LEGACY_F32_e32_gfx6_gfx7:
    case AMDGPU::V_MAX_F16V_MAX_F16_fake16_e32_gfx11:
    case AMDGPU::V_MAX_F16_e32_gfx10:
    case AMDGPU::V_MAX_F16_e32_vi:
    case AMDGPU::V_MAX_F32_e32_gfx10:
    case AMDGPU::V_MAX_F32_e32_gfx11:
    case AMDGPU::V_MAX_F32_e32_gfx6_gfx7:
    case AMDGPU::V_MAX_F32_e32_vi:
    case AMDGPU::V_MAX_I16_e32_vi:
    case AMDGPU::V_MAX_I32_e32_gfx10:
    case AMDGPU::V_MAX_I32_e32_gfx11:
    case AMDGPU::V_MAX_I32_e32_gfx12:
    case AMDGPU::V_MAX_I32_e32_gfx6_gfx7:
    case AMDGPU::V_MAX_I32_e32_vi:
    case AMDGPU::V_MAX_LEGACY_F32_e32_gfx6_gfx7:
    case AMDGPU::V_MAX_NUM_F16_fake16_e32_gfx12:
    case AMDGPU::V_MAX_NUM_F32_e32_gfx12:
    case AMDGPU::V_MAX_NUM_F64_e32_gfx12:
    case AMDGPU::V_MAX_U16_e32_vi:
    case AMDGPU::V_MAX_U32_e32_gfx10:
    case AMDGPU::V_MAX_U32_e32_gfx11:
    case AMDGPU::V_MAX_U32_e32_gfx12:
    case AMDGPU::V_MAX_U32_e32_gfx6_gfx7:
    case AMDGPU::V_MAX_U32_e32_vi:
    case AMDGPU::V_MBCNT_HI_U32_B32_e32_gfx6_gfx7:
    case AMDGPU::V_MBCNT_LO_U32_B32_e32_gfx6_gfx7:
    case AMDGPU::V_MIN_F16V_MIN_F16_fake16_e32_gfx11:
    case AMDGPU::V_MIN_F16_e32_gfx10:
    case AMDGPU::V_MIN_F16_e32_vi:
    case AMDGPU::V_MIN_F32_e32_gfx10:
    case AMDGPU::V_MIN_F32_e32_gfx11:
    case AMDGPU::V_MIN_F32_e32_gfx6_gfx7:
    case AMDGPU::V_MIN_F32_e32_vi:
    case AMDGPU::V_MIN_I16_e32_vi:
    case AMDGPU::V_MIN_I32_e32_gfx10:
    case AMDGPU::V_MIN_I32_e32_gfx11:
    case AMDGPU::V_MIN_I32_e32_gfx12:
    case AMDGPU::V_MIN_I32_e32_gfx6_gfx7:
    case AMDGPU::V_MIN_I32_e32_vi:
    case AMDGPU::V_MIN_LEGACY_F32_e32_gfx6_gfx7:
    case AMDGPU::V_MIN_NUM_F16_fake16_e32_gfx12:
    case AMDGPU::V_MIN_NUM_F32_e32_gfx12:
    case AMDGPU::V_MIN_NUM_F64_e32_gfx12:
    case AMDGPU::V_MIN_U16_e32_vi:
    case AMDGPU::V_MIN_U32_e32_gfx10:
    case AMDGPU::V_MIN_U32_e32_gfx11:
    case AMDGPU::V_MIN_U32_e32_gfx12:
    case AMDGPU::V_MIN_U32_e32_gfx6_gfx7:
    case AMDGPU::V_MIN_U32_e32_vi:
    case AMDGPU::V_MUL_DX9_ZERO_F32_e32_gfx11:
    case AMDGPU::V_MUL_DX9_ZERO_F32_e32_gfx12:
    case AMDGPU::V_MUL_F16_e32_gfx10:
    case AMDGPU::V_MUL_F16_e32_vi:
    case AMDGPU::V_MUL_F16_fake16_e32_gfx11:
    case AMDGPU::V_MUL_F16_fake16_e32_gfx12:
    case AMDGPU::V_MUL_F32_e32_gfx10:
    case AMDGPU::V_MUL_F32_e32_gfx11:
    case AMDGPU::V_MUL_F32_e32_gfx12:
    case AMDGPU::V_MUL_F32_e32_gfx6_gfx7:
    case AMDGPU::V_MUL_F32_e32_vi:
    case AMDGPU::V_MUL_F64_e32_gfx12:
    case AMDGPU::V_MUL_HI_I32_I24_e32_gfx10:
    case AMDGPU::V_MUL_HI_I32_I24_e32_gfx11:
    case AMDGPU::V_MUL_HI_I32_I24_e32_gfx12:
    case AMDGPU::V_MUL_HI_I32_I24_e32_gfx6_gfx7:
    case AMDGPU::V_MUL_HI_I32_I24_e32_vi:
    case AMDGPU::V_MUL_HI_U32_U24_e32_gfx10:
    case AMDGPU::V_MUL_HI_U32_U24_e32_gfx11:
    case AMDGPU::V_MUL_HI_U32_U24_e32_gfx12:
    case AMDGPU::V_MUL_HI_U32_U24_e32_gfx6_gfx7:
    case AMDGPU::V_MUL_HI_U32_U24_e32_vi:
    case AMDGPU::V_MUL_I32_I24_e32_gfx10:
    case AMDGPU::V_MUL_I32_I24_e32_gfx11:
    case AMDGPU::V_MUL_I32_I24_e32_gfx12:
    case AMDGPU::V_MUL_I32_I24_e32_gfx6_gfx7:
    case AMDGPU::V_MUL_I32_I24_e32_vi:
    case AMDGPU::V_MUL_LEGACY_F32_e32_gfx10:
    case AMDGPU::V_MUL_LEGACY_F32_e32_gfx6_gfx7:
    case AMDGPU::V_MUL_LEGACY_F32_e32_vi:
    case AMDGPU::V_MUL_LO_U16_e32_vi:
    case AMDGPU::V_MUL_U32_U24_e32_gfx10:
    case AMDGPU::V_MUL_U32_U24_e32_gfx11:
    case AMDGPU::V_MUL_U32_U24_e32_gfx12:
    case AMDGPU::V_MUL_U32_U24_e32_gfx6_gfx7:
    case AMDGPU::V_MUL_U32_U24_e32_vi:
    case AMDGPU::V_MUL_U64_e32_gfx1250:
    case AMDGPU::V_OR_B32_e32_gfx10:
    case AMDGPU::V_OR_B32_e32_gfx11:
    case AMDGPU::V_OR_B32_e32_gfx12:
    case AMDGPU::V_OR_B32_e32_gfx6_gfx7:
    case AMDGPU::V_OR_B32_e32_vi:
    case AMDGPU::V_PK_FMAC_F16_e32_gfx10:
    case AMDGPU::V_PK_FMAC_F16_e32_gfx11:
    case AMDGPU::V_PK_FMAC_F16_e32_gfx12:
    case AMDGPU::V_PK_FMAC_F16_e32_gfx9:
    case AMDGPU::V_PK_FMAC_F16_e32_vi:
    case AMDGPU::V_READLANE_B32_gfx6_gfx7:
    case AMDGPU::V_SUBBREV_CO_U32_e32_gfx9:
    case AMDGPU::V_SUBBREV_U32_e32_gfx6_gfx7:
    case AMDGPU::V_SUBBREV_U32_e32_vi:
    case AMDGPU::V_SUBB_CO_U32_e32_gfx9:
    case AMDGPU::V_SUBB_U32_e32_gfx6_gfx7:
    case AMDGPU::V_SUBB_U32_e32_vi:
    case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
    case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
    case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx12:
    case AMDGPU::V_SUBREV_CO_U32_e32_gfx9:
    case AMDGPU::V_SUBREV_F16_e32_gfx10:
    case AMDGPU::V_SUBREV_F16_e32_vi:
    case AMDGPU::V_SUBREV_F16_fake16_e32_gfx11:
    case AMDGPU::V_SUBREV_F16_fake16_e32_gfx12:
    case AMDGPU::V_SUBREV_F32_e32_gfx10:
    case AMDGPU::V_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_SUBREV_F32_e32_gfx6_gfx7:
    case AMDGPU::V_SUBREV_F32_e32_vi:
    case AMDGPU::V_SUBREV_I32_e32_gfx6_gfx7:
    case AMDGPU::V_SUBREV_NC_U32_e32_gfx10:
    case AMDGPU::V_SUBREV_NC_U32_e32_gfx11:
    case AMDGPU::V_SUBREV_NC_U32_e32_gfx12:
    case AMDGPU::V_SUBREV_U16_e32_vi:
    case AMDGPU::V_SUBREV_U32_e32_gfx9:
    case AMDGPU::V_SUBREV_U32_e32_vi:
    case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
    case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
    case AMDGPU::V_SUB_CO_CI_U32_e32_gfx12:
    case AMDGPU::V_SUB_CO_U32_e32_gfx9:
    case AMDGPU::V_SUB_F16_e32_gfx10:
    case AMDGPU::V_SUB_F16_e32_vi:
    case AMDGPU::V_SUB_F16_fake16_e32_gfx11:
    case AMDGPU::V_SUB_F16_fake16_e32_gfx12:
    case AMDGPU::V_SUB_F32_e32_gfx10:
    case AMDGPU::V_SUB_F32_e32_gfx11:
    case AMDGPU::V_SUB_F32_e32_gfx12:
    case AMDGPU::V_SUB_F32_e32_gfx6_gfx7:
    case AMDGPU::V_SUB_F32_e32_vi:
    case AMDGPU::V_SUB_I32_e32_gfx6_gfx7:
    case AMDGPU::V_SUB_NC_U32_e32_gfx10:
    case AMDGPU::V_SUB_NC_U32_e32_gfx11:
    case AMDGPU::V_SUB_NC_U32_e32_gfx12:
    case AMDGPU::V_SUB_U16_e32_vi:
    case AMDGPU::V_SUB_U32_e32_gfx9:
    case AMDGPU::V_SUB_U32_e32_vi:
    case AMDGPU::V_SUB_U64_e32_gfx1250:
    case AMDGPU::V_WRITELANE_B32_gfx6_gfx7:
    case AMDGPU::V_XNOR_B32_e32_gfx10:
    case AMDGPU::V_XNOR_B32_e32_gfx11:
    case AMDGPU::V_XNOR_B32_e32_gfx12:
    case AMDGPU::V_XNOR_B32_e32_vi:
    case AMDGPU::V_XOR_B32_e32_gfx10:
    case AMDGPU::V_XOR_B32_e32_gfx11:
    case AMDGPU::V_XOR_B32_e32_gfx12:
    case AMDGPU::V_XOR_B32_e32_gfx6_gfx7:
    case AMDGPU::V_XOR_B32_e32_vi: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_FMAAK_F16_fake16_gfx11:
    case AMDGPU::V_FMAAK_F16_fake16_gfx12:
    case AMDGPU::V_FMAAK_F16_gfx10:
    case AMDGPU::V_FMAAK_F32_gfx10:
    case AMDGPU::V_FMAAK_F32_gfx11:
    case AMDGPU::V_FMAAK_F32_gfx12:
    case AMDGPU::V_FMAAK_F32_gfx940:
    case AMDGPU::V_MADAK_F16_vi:
    case AMDGPU::V_MADAK_F32_gfx10:
    case AMDGPU::V_MADAK_F32_gfx6_gfx7:
    case AMDGPU::V_MADAK_F32_vi: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(32, 0), 32, 32);
      break;
    }
    case AMDGPU::V_FMAAK_F64_gfx1250: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(64, 0), 32, 64);
      break;
    }
    case AMDGPU::V_FMAMK_F16_fake16_gfx11:
    case AMDGPU::V_FMAMK_F16_fake16_gfx12:
    case AMDGPU::V_FMAMK_F16_gfx10:
    case AMDGPU::V_FMAMK_F32_gfx10:
    case AMDGPU::V_FMAMK_F32_gfx11:
    case AMDGPU::V_FMAMK_F32_gfx12:
    case AMDGPU::V_FMAMK_F32_gfx940:
    case AMDGPU::V_MADMK_F16_vi:
    case AMDGPU::V_MADMK_F32_gfx10:
    case AMDGPU::V_MADMK_F32_gfx6_gfx7:
    case AMDGPU::V_MADMK_F32_vi: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(32, 0), 32, 32);
      break;
    }
    case AMDGPU::V_FMAMK_F64_gfx1250: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(64, 0), 32, 64);
      break;
    }
    case AMDGPU::V_SWAPREL_B32_gfx10:
    case AMDGPU::V_SWAPREL_B32_gfx11:
    case AMDGPU::V_SWAPREL_B32_gfx12:
    case AMDGPU::V_SWAP_B32_gfx10:
    case AMDGPU::V_SWAP_B32_gfx11:
    case AMDGPU::V_SWAP_B32_gfx12:
    case AMDGPU::V_SWAP_B32_vi: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      break;
    }
    case AMDGPU::V_PERMLANE16_SWAP_B32_e32_gfx1250:
    case AMDGPU::V_PERMLANE16_SWAP_B32_e32_gfx9:
    case AMDGPU::V_PERMLANE32_SWAP_B32_e32_gfx9: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      break;
    }
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_t16_e32_gfx1250:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_e32_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_e32_gfx12:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_e32_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_e32_gfx12:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_t16_e32_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_t16_e32_gfx1250:
    case AMDGPU::V_CVT_PK_F32_BF8_t16_e32_gfx12:
    case AMDGPU::V_CVT_PK_F32_FP8_t16_e32_gfx12:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_e32_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_e32_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      break;
    }
    case AMDGPU::V_INTERP_MOV_F32_gfx10:
    case AMDGPU::V_INTERP_MOV_F32_si:
    case AMDGPU::V_INTERP_MOV_F32_vi:
    case AMDGPU::V_INTERP_P1_F32_16bank_gfx10:
    case AMDGPU::V_INTERP_P1_F32_16bank_si:
    case AMDGPU::V_INTERP_P1_F32_16bank_vi:
    case AMDGPU::V_INTERP_P1_F32_gfx10:
    case AMDGPU::V_INTERP_P1_F32_si:
    case AMDGPU::V_INTERP_P1_F32_vi: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 18, 8);
      // op: vsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: attrchan
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 8, 2);
      // op: attr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 0), 10, 6);
      break;
    }
    case AMDGPU::V_INTERP_P2_F32_gfx10:
    case AMDGPU::V_INTERP_P2_F32_si:
    case AMDGPU::V_INTERP_P2_F32_vi: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 18, 8);
      // op: vsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: attrchan
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 8, 2);
      // op: attr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(6, 0), 10, 6);
      break;
    }
    case AMDGPU::GLOBAL_LOAD_DWORD_ADDTID_gfx12:
    case AMDGPU::SCRATCH_LOAD_BLOCK_ST_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B128_gfx1250:
    case AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B32_gfx1250:
    case AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B64_gfx1250:
    case AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B8_gfx1250:
    case AMDGPU::CLUSTER_LOAD_B128_gfx1250:
    case AMDGPU::CLUSTER_LOAD_B32_gfx1250:
    case AMDGPU::CLUSTER_LOAD_B64_gfx1250:
    case AMDGPU::FLAT_LOAD_MONITOR_B128_gfx1250:
    case AMDGPU::FLAT_LOAD_MONITOR_B32_gfx1250:
    case AMDGPU::FLAT_LOAD_MONITOR_B64_gfx1250:
    case AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B128_gfx1250:
    case AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B32_gfx1250:
    case AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B64_gfx1250:
    case AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B8_gfx1250:
    case AMDGPU::GLOBAL_LOAD_BLOCK_gfx12:
    case AMDGPU::GLOBAL_LOAD_MONITOR_B128_gfx1250:
    case AMDGPU::GLOBAL_LOAD_MONITOR_B32_gfx1250:
    case AMDGPU::GLOBAL_LOAD_MONITOR_B64_gfx1250:
    case AMDGPU::GLOBAL_LOAD_TR4_B64_gfx1250:
    case AMDGPU::GLOBAL_LOAD_TR6_B96_gfx1250:
    case AMDGPU::GLOBAL_LOAD_TR_B128_w32_gfx12:
    case AMDGPU::GLOBAL_LOAD_TR_B128_w32_gfx1250:
    case AMDGPU::GLOBAL_LOAD_TR_B128_w64_gfx12:
    case AMDGPU::GLOBAL_LOAD_TR_B64_w32_gfx12:
    case AMDGPU::GLOBAL_LOAD_TR_B64_w32_gfx1250:
    case AMDGPU::GLOBAL_LOAD_TR_B64_w64_gfx12:
    case AMDGPU::SCRATCH_LOAD_BLOCK_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 52, 3);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_F32_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_ADD_F64_RTN_gfx1250:
    case AMDGPU::FLAT_ATOMIC_ADD_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_AND_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_AND_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_COND_SUB_U32_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_CSUB_U32_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_DEC_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_FMAX_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_FMIN_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_INC_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_INC_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_MAX_F64_RTN_gfx1250:
    case AMDGPU::FLAT_ATOMIC_MIN_F64_RTN_gfx1250:
    case AMDGPU::FLAT_ATOMIC_OR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_OR_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_BF16_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_F16_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMAX_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMIN_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SUB_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SWAP_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMAX_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMIN_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_XOR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_RTN_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_ADD_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_AND_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CSUB_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_DEC_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_INC_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_RTN_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_RTN_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_OR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SUB_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_XOR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 1), 53, 2);
      Value.insertBits(op.extractBitsAsZExtValue(2, 3), 50, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 11), 48, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 5), 7, 1);
      // op: vdata
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 55, 8);
      // op: vaddr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(24, 0), 72, 24);
      break;
    }
    case AMDGPU::DS_CMPSTORE_RTN_B32_gfx12:
    case AMDGPU::DS_CMPSTORE_RTN_B64_gfx12:
    case AMDGPU::DS_MSKOR_RTN_B32_gfx12:
    case AMDGPU::DS_MSKOR_RTN_B64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: data0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: data1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_WRXCHG2ST64_RTN_B32_gfx12:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B64_gfx12:
    case AMDGPU::DS_WRXCHG2_RTN_B32_gfx12:
    case AMDGPU::DS_WRXCHG2_RTN_B64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: data0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: data1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: offset0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: offset1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 8, 8);
      break;
    }
    case AMDGPU::DS_ADD_RTN_F32_gfx12:
    case AMDGPU::DS_ADD_RTN_F64_gfx12:
    case AMDGPU::DS_ADD_RTN_U32_gfx12:
    case AMDGPU::DS_ADD_RTN_U64_gfx12:
    case AMDGPU::DS_AND_RTN_B32_gfx12:
    case AMDGPU::DS_AND_RTN_B64_gfx12:
    case AMDGPU::DS_ATOMIC_BARRIER_ARRIVE_RTN_B64_gfx12:
    case AMDGPU::DS_BPERMUTE_B32_gfx10:
    case AMDGPU::DS_BPERMUTE_B32_gfx11:
    case AMDGPU::DS_BPERMUTE_B32_gfx12:
    case AMDGPU::DS_BPERMUTE_B32_vi:
    case AMDGPU::DS_BPERMUTE_B32_vi_agpr:
    case AMDGPU::DS_CONDXCHG32_RTN_B64_gfx12:
    case AMDGPU::DS_COND_SUB_RTN_U32_gfx12:
    case AMDGPU::DS_DEC_RTN_U32_gfx12:
    case AMDGPU::DS_DEC_RTN_U64_gfx12:
    case AMDGPU::DS_INC_RTN_U32_gfx12:
    case AMDGPU::DS_INC_RTN_U64_gfx12:
    case AMDGPU::DS_MAX_RTN_F32_gfx12:
    case AMDGPU::DS_MAX_RTN_F64_gfx12:
    case AMDGPU::DS_MAX_RTN_I32_gfx12:
    case AMDGPU::DS_MAX_RTN_I64_gfx12:
    case AMDGPU::DS_MAX_RTN_U32_gfx12:
    case AMDGPU::DS_MAX_RTN_U64_gfx12:
    case AMDGPU::DS_MIN_RTN_F32_gfx12:
    case AMDGPU::DS_MIN_RTN_F64_gfx12:
    case AMDGPU::DS_MIN_RTN_I32_gfx12:
    case AMDGPU::DS_MIN_RTN_I64_gfx12:
    case AMDGPU::DS_MIN_RTN_U32_gfx12:
    case AMDGPU::DS_MIN_RTN_U64_gfx12:
    case AMDGPU::DS_OR_RTN_B32_gfx12:
    case AMDGPU::DS_OR_RTN_B64_gfx12:
    case AMDGPU::DS_PERMUTE_B32_gfx10:
    case AMDGPU::DS_PERMUTE_B32_gfx11:
    case AMDGPU::DS_PERMUTE_B32_gfx12:
    case AMDGPU::DS_PERMUTE_B32_vi:
    case AMDGPU::DS_PERMUTE_B32_vi_agpr:
    case AMDGPU::DS_PK_ADD_RTN_BF16_gfx12:
    case AMDGPU::DS_PK_ADD_RTN_F16_gfx12:
    case AMDGPU::DS_RSUB_RTN_U32_gfx12:
    case AMDGPU::DS_RSUB_RTN_U64_gfx12:
    case AMDGPU::DS_SUB_CLAMP_RTN_U32_gfx12:
    case AMDGPU::DS_SUB_RTN_U32_gfx12:
    case AMDGPU::DS_SUB_RTN_U64_gfx12:
    case AMDGPU::DS_WRXCHG_RTN_B32_gfx12:
    case AMDGPU::DS_WRXCHG_RTN_B64_gfx12:
    case AMDGPU::DS_XOR_RTN_B32_gfx12:
    case AMDGPU::DS_XOR_RTN_B64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: data0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_BVH_STACK_PUSH8_POP1_RTN_B32_gfx12:
    case AMDGPU::DS_BVH_STACK_PUSH8_POP2_RTN_B64_gfx12:
    case AMDGPU::DS_BVH_STACK_RTN_B32_gfx11:
    case AMDGPU::DS_BVH_STACK_RTN_B32_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: data0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: data1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_LOAD_TR16_B128_gfx12:
    case AMDGPU::DS_LOAD_TR4_B64_gfx12:
    case AMDGPU::DS_LOAD_TR6_B96_gfx12:
    case AMDGPU::DS_LOAD_TR8_B64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::GLOBAL_LOAD_DWORD_ADDTID_gfx11: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 14, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(13, 0), 0, 13);
      break;
    }
    case AMDGPU::GLOBAL_LOAD_DWORD_ADDTID_gfx10: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: cpol
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 16, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(12, 0), 0, 12);
      break;
    }
    case AMDGPU::DS_ADD_GS_REG_RTN_gfx11:
    case AMDGPU::DS_SUB_GS_REG_RTN_gfx11: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: data0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_ADD_RTN_F32_vi:
    case AMDGPU::DS_ADD_RTN_F32_vi_agpr:
    case AMDGPU::DS_ADD_RTN_F32_vi_gfx9:
    case AMDGPU::DS_ADD_RTN_F64_vi:
    case AMDGPU::DS_ADD_RTN_F64_vi_agpr:
    case AMDGPU::DS_ADD_RTN_U32_vi:
    case AMDGPU::DS_ADD_RTN_U32_vi_agpr:
    case AMDGPU::DS_ADD_RTN_U32_vi_gfx9:
    case AMDGPU::DS_ADD_RTN_U64_vi:
    case AMDGPU::DS_ADD_RTN_U64_vi_agpr:
    case AMDGPU::DS_ADD_RTN_U64_vi_gfx9:
    case AMDGPU::DS_AND_RTN_B32_vi:
    case AMDGPU::DS_AND_RTN_B32_vi_agpr:
    case AMDGPU::DS_AND_RTN_B32_vi_gfx9:
    case AMDGPU::DS_AND_RTN_B64_vi:
    case AMDGPU::DS_AND_RTN_B64_vi_agpr:
    case AMDGPU::DS_AND_RTN_B64_vi_gfx9:
    case AMDGPU::DS_CONDXCHG32_RTN_B64_vi:
    case AMDGPU::DS_CONDXCHG32_RTN_B64_vi_agpr:
    case AMDGPU::DS_CONDXCHG32_RTN_B64_vi_gfx9:
    case AMDGPU::DS_DEC_RTN_U32_vi:
    case AMDGPU::DS_DEC_RTN_U32_vi_agpr:
    case AMDGPU::DS_DEC_RTN_U32_vi_gfx9:
    case AMDGPU::DS_DEC_RTN_U64_vi:
    case AMDGPU::DS_DEC_RTN_U64_vi_agpr:
    case AMDGPU::DS_DEC_RTN_U64_vi_gfx9:
    case AMDGPU::DS_INC_RTN_U32_vi:
    case AMDGPU::DS_INC_RTN_U32_vi_agpr:
    case AMDGPU::DS_INC_RTN_U32_vi_gfx9:
    case AMDGPU::DS_INC_RTN_U64_vi:
    case AMDGPU::DS_INC_RTN_U64_vi_agpr:
    case AMDGPU::DS_INC_RTN_U64_vi_gfx9:
    case AMDGPU::DS_MAX_RTN_F32_vi:
    case AMDGPU::DS_MAX_RTN_F32_vi_agpr:
    case AMDGPU::DS_MAX_RTN_F32_vi_gfx9:
    case AMDGPU::DS_MAX_RTN_F64_vi:
    case AMDGPU::DS_MAX_RTN_F64_vi_agpr:
    case AMDGPU::DS_MAX_RTN_F64_vi_gfx9:
    case AMDGPU::DS_MAX_RTN_I32_vi:
    case AMDGPU::DS_MAX_RTN_I32_vi_agpr:
    case AMDGPU::DS_MAX_RTN_I32_vi_gfx9:
    case AMDGPU::DS_MAX_RTN_I64_vi:
    case AMDGPU::DS_MAX_RTN_I64_vi_agpr:
    case AMDGPU::DS_MAX_RTN_I64_vi_gfx9:
    case AMDGPU::DS_MAX_RTN_U32_vi:
    case AMDGPU::DS_MAX_RTN_U32_vi_agpr:
    case AMDGPU::DS_MAX_RTN_U32_vi_gfx9:
    case AMDGPU::DS_MAX_RTN_U64_vi:
    case AMDGPU::DS_MAX_RTN_U64_vi_agpr:
    case AMDGPU::DS_MAX_RTN_U64_vi_gfx9:
    case AMDGPU::DS_MIN_RTN_F32_vi:
    case AMDGPU::DS_MIN_RTN_F32_vi_agpr:
    case AMDGPU::DS_MIN_RTN_F32_vi_gfx9:
    case AMDGPU::DS_MIN_RTN_F64_vi:
    case AMDGPU::DS_MIN_RTN_F64_vi_agpr:
    case AMDGPU::DS_MIN_RTN_F64_vi_gfx9:
    case AMDGPU::DS_MIN_RTN_I32_vi:
    case AMDGPU::DS_MIN_RTN_I32_vi_agpr:
    case AMDGPU::DS_MIN_RTN_I32_vi_gfx9:
    case AMDGPU::DS_MIN_RTN_I64_vi:
    case AMDGPU::DS_MIN_RTN_I64_vi_agpr:
    case AMDGPU::DS_MIN_RTN_I64_vi_gfx9:
    case AMDGPU::DS_MIN_RTN_U32_vi:
    case AMDGPU::DS_MIN_RTN_U32_vi_agpr:
    case AMDGPU::DS_MIN_RTN_U32_vi_gfx9:
    case AMDGPU::DS_MIN_RTN_U64_vi:
    case AMDGPU::DS_MIN_RTN_U64_vi_agpr:
    case AMDGPU::DS_MIN_RTN_U64_vi_gfx9:
    case AMDGPU::DS_OR_RTN_B32_vi:
    case AMDGPU::DS_OR_RTN_B32_vi_agpr:
    case AMDGPU::DS_OR_RTN_B32_vi_gfx9:
    case AMDGPU::DS_OR_RTN_B64_vi:
    case AMDGPU::DS_OR_RTN_B64_vi_agpr:
    case AMDGPU::DS_OR_RTN_B64_vi_gfx9:
    case AMDGPU::DS_PK_ADD_RTN_BF16_vi:
    case AMDGPU::DS_PK_ADD_RTN_BF16_vi_agpr:
    case AMDGPU::DS_PK_ADD_RTN_F16_vi:
    case AMDGPU::DS_PK_ADD_RTN_F16_vi_agpr:
    case AMDGPU::DS_RSUB_RTN_U32_vi:
    case AMDGPU::DS_RSUB_RTN_U32_vi_agpr:
    case AMDGPU::DS_RSUB_RTN_U32_vi_gfx9:
    case AMDGPU::DS_RSUB_RTN_U64_vi:
    case AMDGPU::DS_RSUB_RTN_U64_vi_agpr:
    case AMDGPU::DS_RSUB_RTN_U64_vi_gfx9:
    case AMDGPU::DS_SUB_RTN_U32_vi:
    case AMDGPU::DS_SUB_RTN_U32_vi_agpr:
    case AMDGPU::DS_SUB_RTN_U32_vi_gfx9:
    case AMDGPU::DS_SUB_RTN_U64_vi:
    case AMDGPU::DS_SUB_RTN_U64_vi_agpr:
    case AMDGPU::DS_SUB_RTN_U64_vi_gfx9:
    case AMDGPU::DS_WRXCHG_RTN_B32_vi:
    case AMDGPU::DS_WRXCHG_RTN_B32_vi_agpr:
    case AMDGPU::DS_WRXCHG_RTN_B32_vi_gfx9:
    case AMDGPU::DS_WRXCHG_RTN_B64_vi:
    case AMDGPU::DS_WRXCHG_RTN_B64_vi_agpr:
    case AMDGPU::DS_WRXCHG_RTN_B64_vi_gfx9:
    case AMDGPU::DS_XOR_RTN_B32_vi:
    case AMDGPU::DS_XOR_RTN_B32_vi_agpr:
    case AMDGPU::DS_XOR_RTN_B32_vi_gfx9:
    case AMDGPU::DS_XOR_RTN_B64_vi:
    case AMDGPU::DS_XOR_RTN_B64_vi_agpr:
    case AMDGPU::DS_XOR_RTN_B64_vi_gfx9: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: data0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_ADD_RTN_F32_gfx10:
    case AMDGPU::DS_ADD_RTN_F32_gfx11:
    case AMDGPU::DS_ADD_RTN_U32_gfx10:
    case AMDGPU::DS_ADD_RTN_U32_gfx11:
    case AMDGPU::DS_ADD_RTN_U32_gfx6_gfx7:
    case AMDGPU::DS_ADD_RTN_U64_gfx10:
    case AMDGPU::DS_ADD_RTN_U64_gfx11:
    case AMDGPU::DS_ADD_RTN_U64_gfx6_gfx7:
    case AMDGPU::DS_AND_RTN_B32_gfx10:
    case AMDGPU::DS_AND_RTN_B32_gfx11:
    case AMDGPU::DS_AND_RTN_B32_gfx6_gfx7:
    case AMDGPU::DS_AND_RTN_B64_gfx10:
    case AMDGPU::DS_AND_RTN_B64_gfx11:
    case AMDGPU::DS_AND_RTN_B64_gfx6_gfx7:
    case AMDGPU::DS_CONDXCHG32_RTN_B64_gfx10:
    case AMDGPU::DS_CONDXCHG32_RTN_B64_gfx11:
    case AMDGPU::DS_CONDXCHG32_RTN_B64_gfx7:
    case AMDGPU::DS_DEC_RTN_U32_gfx10:
    case AMDGPU::DS_DEC_RTN_U32_gfx11:
    case AMDGPU::DS_DEC_RTN_U32_gfx6_gfx7:
    case AMDGPU::DS_DEC_RTN_U64_gfx10:
    case AMDGPU::DS_DEC_RTN_U64_gfx11:
    case AMDGPU::DS_DEC_RTN_U64_gfx6_gfx7:
    case AMDGPU::DS_INC_RTN_U32_gfx10:
    case AMDGPU::DS_INC_RTN_U32_gfx11:
    case AMDGPU::DS_INC_RTN_U32_gfx6_gfx7:
    case AMDGPU::DS_INC_RTN_U64_gfx10:
    case AMDGPU::DS_INC_RTN_U64_gfx11:
    case AMDGPU::DS_INC_RTN_U64_gfx6_gfx7:
    case AMDGPU::DS_MAX_RTN_F32_gfx10:
    case AMDGPU::DS_MAX_RTN_F32_gfx11:
    case AMDGPU::DS_MAX_RTN_F32_gfx6_gfx7:
    case AMDGPU::DS_MAX_RTN_F64_gfx10:
    case AMDGPU::DS_MAX_RTN_F64_gfx11:
    case AMDGPU::DS_MAX_RTN_F64_gfx6_gfx7:
    case AMDGPU::DS_MAX_RTN_I32_gfx10:
    case AMDGPU::DS_MAX_RTN_I32_gfx11:
    case AMDGPU::DS_MAX_RTN_I32_gfx6_gfx7:
    case AMDGPU::DS_MAX_RTN_I64_gfx10:
    case AMDGPU::DS_MAX_RTN_I64_gfx11:
    case AMDGPU::DS_MAX_RTN_I64_gfx6_gfx7:
    case AMDGPU::DS_MAX_RTN_U32_gfx10:
    case AMDGPU::DS_MAX_RTN_U32_gfx11:
    case AMDGPU::DS_MAX_RTN_U32_gfx6_gfx7:
    case AMDGPU::DS_MAX_RTN_U64_gfx10:
    case AMDGPU::DS_MAX_RTN_U64_gfx11:
    case AMDGPU::DS_MAX_RTN_U64_gfx6_gfx7:
    case AMDGPU::DS_MIN_RTN_F32_gfx10:
    case AMDGPU::DS_MIN_RTN_F32_gfx11:
    case AMDGPU::DS_MIN_RTN_F32_gfx6_gfx7:
    case AMDGPU::DS_MIN_RTN_F64_gfx10:
    case AMDGPU::DS_MIN_RTN_F64_gfx11:
    case AMDGPU::DS_MIN_RTN_F64_gfx6_gfx7:
    case AMDGPU::DS_MIN_RTN_I32_gfx10:
    case AMDGPU::DS_MIN_RTN_I32_gfx11:
    case AMDGPU::DS_MIN_RTN_I32_gfx6_gfx7:
    case AMDGPU::DS_MIN_RTN_I64_gfx10:
    case AMDGPU::DS_MIN_RTN_I64_gfx11:
    case AMDGPU::DS_MIN_RTN_I64_gfx6_gfx7:
    case AMDGPU::DS_MIN_RTN_U32_gfx10:
    case AMDGPU::DS_MIN_RTN_U32_gfx11:
    case AMDGPU::DS_MIN_RTN_U32_gfx6_gfx7:
    case AMDGPU::DS_MIN_RTN_U64_gfx10:
    case AMDGPU::DS_MIN_RTN_U64_gfx11:
    case AMDGPU::DS_MIN_RTN_U64_gfx6_gfx7:
    case AMDGPU::DS_OR_RTN_B32_gfx10:
    case AMDGPU::DS_OR_RTN_B32_gfx11:
    case AMDGPU::DS_OR_RTN_B32_gfx6_gfx7:
    case AMDGPU::DS_OR_RTN_B64_gfx10:
    case AMDGPU::DS_OR_RTN_B64_gfx11:
    case AMDGPU::DS_OR_RTN_B64_gfx6_gfx7:
    case AMDGPU::DS_RSUB_RTN_U32_gfx10:
    case AMDGPU::DS_RSUB_RTN_U32_gfx11:
    case AMDGPU::DS_RSUB_RTN_U32_gfx6_gfx7:
    case AMDGPU::DS_RSUB_RTN_U64_gfx10:
    case AMDGPU::DS_RSUB_RTN_U64_gfx11:
    case AMDGPU::DS_RSUB_RTN_U64_gfx6_gfx7:
    case AMDGPU::DS_SUB_RTN_U32_gfx10:
    case AMDGPU::DS_SUB_RTN_U32_gfx11:
    case AMDGPU::DS_SUB_RTN_U32_gfx6_gfx7:
    case AMDGPU::DS_SUB_RTN_U64_gfx10:
    case AMDGPU::DS_SUB_RTN_U64_gfx11:
    case AMDGPU::DS_SUB_RTN_U64_gfx6_gfx7:
    case AMDGPU::DS_WRXCHG_RTN_B32_gfx10:
    case AMDGPU::DS_WRXCHG_RTN_B32_gfx11:
    case AMDGPU::DS_WRXCHG_RTN_B32_gfx6_gfx7:
    case AMDGPU::DS_WRXCHG_RTN_B64_gfx10:
    case AMDGPU::DS_WRXCHG_RTN_B64_gfx11:
    case AMDGPU::DS_WRXCHG_RTN_B64_gfx6_gfx7:
    case AMDGPU::DS_XOR_RTN_B32_gfx10:
    case AMDGPU::DS_XOR_RTN_B32_gfx11:
    case AMDGPU::DS_XOR_RTN_B32_gfx6_gfx7:
    case AMDGPU::DS_XOR_RTN_B64_gfx10:
    case AMDGPU::DS_XOR_RTN_B64_gfx11:
    case AMDGPU::DS_XOR_RTN_B64_gfx6_gfx7: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: data0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_CMPST_RTN_B32_vi:
    case AMDGPU::DS_CMPST_RTN_B32_vi_agpr:
    case AMDGPU::DS_CMPST_RTN_B32_vi_gfx9:
    case AMDGPU::DS_CMPST_RTN_B64_vi:
    case AMDGPU::DS_CMPST_RTN_B64_vi_agpr:
    case AMDGPU::DS_CMPST_RTN_B64_vi_gfx9:
    case AMDGPU::DS_CMPST_RTN_F32_vi:
    case AMDGPU::DS_CMPST_RTN_F32_vi_agpr:
    case AMDGPU::DS_CMPST_RTN_F32_vi_gfx9:
    case AMDGPU::DS_CMPST_RTN_F64_vi:
    case AMDGPU::DS_CMPST_RTN_F64_vi_agpr:
    case AMDGPU::DS_CMPST_RTN_F64_vi_gfx9:
    case AMDGPU::DS_MSKOR_RTN_B32_vi:
    case AMDGPU::DS_MSKOR_RTN_B32_vi_agpr:
    case AMDGPU::DS_MSKOR_RTN_B32_vi_gfx9:
    case AMDGPU::DS_MSKOR_RTN_B64_vi:
    case AMDGPU::DS_MSKOR_RTN_B64_vi_agpr:
    case AMDGPU::DS_MSKOR_RTN_B64_vi_gfx9:
    case AMDGPU::DS_WRAP_RTN_B32_vi:
    case AMDGPU::DS_WRAP_RTN_B32_vi_agpr:
    case AMDGPU::DS_WRAP_RTN_B32_vi_gfx9: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: data0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: data1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_CMPSTORE_RTN_B32_gfx11:
    case AMDGPU::DS_CMPSTORE_RTN_B64_gfx11:
    case AMDGPU::DS_CMPSTORE_RTN_F32_gfx11:
    case AMDGPU::DS_CMPSTORE_RTN_F64_gfx11:
    case AMDGPU::DS_CMPST_RTN_B32_gfx10:
    case AMDGPU::DS_CMPST_RTN_B32_gfx6_gfx7:
    case AMDGPU::DS_CMPST_RTN_B64_gfx10:
    case AMDGPU::DS_CMPST_RTN_B64_gfx6_gfx7:
    case AMDGPU::DS_CMPST_RTN_F32_gfx10:
    case AMDGPU::DS_CMPST_RTN_F32_gfx6_gfx7:
    case AMDGPU::DS_CMPST_RTN_F64_gfx10:
    case AMDGPU::DS_CMPST_RTN_F64_gfx6_gfx7:
    case AMDGPU::DS_MSKOR_RTN_B32_gfx10:
    case AMDGPU::DS_MSKOR_RTN_B32_gfx11:
    case AMDGPU::DS_MSKOR_RTN_B32_gfx6_gfx7:
    case AMDGPU::DS_MSKOR_RTN_B64_gfx10:
    case AMDGPU::DS_MSKOR_RTN_B64_gfx11:
    case AMDGPU::DS_MSKOR_RTN_B64_gfx6_gfx7:
    case AMDGPU::DS_WRAP_RTN_B32_gfx10:
    case AMDGPU::DS_WRAP_RTN_B32_gfx11:
    case AMDGPU::DS_WRAP_RTN_B32_gfx7: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: data0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: data1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: offset
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(16, 0), 0, 16);
      break;
    }
    case AMDGPU::DS_WRXCHG2ST64_RTN_B32_vi:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B32_vi_agpr:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B32_vi_gfx9:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B64_vi:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B64_vi_agpr:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B64_vi_gfx9:
    case AMDGPU::DS_WRXCHG2_RTN_B32_vi:
    case AMDGPU::DS_WRXCHG2_RTN_B32_vi_agpr:
    case AMDGPU::DS_WRXCHG2_RTN_B32_vi_gfx9:
    case AMDGPU::DS_WRXCHG2_RTN_B64_vi:
    case AMDGPU::DS_WRXCHG2_RTN_B64_vi_agpr:
    case AMDGPU::DS_WRXCHG2_RTN_B64_vi_gfx9: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 16, 1);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: data0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: data1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: offset0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: offset1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 8, 8);
      break;
    }
    case AMDGPU::DS_WRXCHG2ST64_RTN_B32_gfx10:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B32_gfx11:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B32_gfx6_gfx7:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B64_gfx10:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B64_gfx11:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B64_gfx6_gfx7:
    case AMDGPU::DS_WRXCHG2_RTN_B32_gfx10:
    case AMDGPU::DS_WRXCHG2_RTN_B32_gfx11:
    case AMDGPU::DS_WRXCHG2_RTN_B32_gfx6_gfx7:
    case AMDGPU::DS_WRXCHG2_RTN_B64_gfx10:
    case AMDGPU::DS_WRXCHG2_RTN_B64_gfx11:
    case AMDGPU::DS_WRXCHG2_RTN_B64_gfx6_gfx7: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 56, 8);
      // op: gds
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 17, 1);
      // op: addr
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 32, 8);
      // op: data0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 40, 8);
      // op: data1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 48, 8);
      // op: offset0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: offset1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 8, 8);
      break;
    }
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0
      op.clearAllBits();
      getAVOperandEncoding(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 123, 1);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 96, 9);
      // op: src1
      op.clearAllBits();
      getAVOperandEncoding(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 9), 124, 1);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 105, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 114, 9);
      // op: blgp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 125, 3);
      // op: cbsz
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 72, 3);
      // op: scale_src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: scale_src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 59, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 60, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      break;
    }
    case AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 96, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 105, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 127, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 74, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 114, 9);
      // op: matrix_a_fmt
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 75, 3);
      // op: matrix_b_fmt
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 123, 2);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 78, 1);
      // op: matrix_a_scale
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      // op: matrix_b_scale
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 59, 1);
      // op: matrix_a_scale_fmt
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 61, 2);
      // op: matrix_b_scale_fmt
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 8, 2);
      // op: matrix_a_reuse
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(13), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: matrix_b_reuse
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(14), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: scale_src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: scale_src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      break;
    }
    case AMDGPU::V_WMMA_SCALE16_F32_32X16X128_F4_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE_F32_32X16X128_F4_w32_gfx1250: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 64, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 96, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 105, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 127, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 74, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 114, 9);
      // op: matrix_a_scale
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 11, 1);
      // op: matrix_b_scale
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 59, 1);
      // op: matrix_a_scale_fmt
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 61, 2);
      // op: matrix_b_scale_fmt
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(10), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 8, 2);
      // op: matrix_a_reuse
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(11), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 13, 1);
      // op: matrix_b_reuse
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(12), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 14, 1);
      // op: scale_src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: scale_src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      break;
    }
    case AMDGPU::V_DOT2_BF16_BF16_t16_e64_gfx11:
    case AMDGPU::V_DOT2_BF16_BF16_t16_e64_gfx12:
    case AMDGPU::V_DOT2_F16_F16_t16_e64_gfx11:
    case AMDGPU::V_DOT2_F16_F16_t16_e64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      break;
    }
    case AMDGPU::V_INTERP_P2_F16_F32_inreg_t16_gfx11:
    case AMDGPU::V_INTERP_P2_F16_F32_inreg_t16_gfx12:
    case AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_t16_gfx11:
    case AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_t16_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: waitexp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(9), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(3, 0), 8, 3);
      break;
    }
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_t16_e64_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_t16_e64_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e64_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CVT_PK_BF8_F16_gfx1250_t16_e64_gfx1250:
    case AMDGPU::V_CVT_PK_FP8_F16_gfx1250_t16_e64_gfx1250: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      break;
    }
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_e64_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_e64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      break;
    }
    case AMDGPU::V_CVT_PK_BF8_F32_t16_e64_gfx11:
    case AMDGPU::V_CVT_PK_BF8_F32_t16_e64_gfx12:
    case AMDGPU::V_CVT_PK_FP8_F32_t16_e64_gfx11:
    case AMDGPU::V_CVT_PK_FP8_F32_t16_e64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      break;
    }
    case AMDGPU::V_CVT_PK_FP8_F32_gfx1250_t16_e64_gfx1250: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      break;
    }
    case AMDGPU::V_COS_BF16V_COS_BF16_t16_e64_gfx1250:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_t16_e64_gfx1250:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_t16_e64_gfx1250:
    case AMDGPU::V_MOV_B16_t16_e64_gfx11:
    case AMDGPU::V_MOV_B16_t16_e64_gfx12:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_e64_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_e64_gfx12:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_t16_e64_gfx1250:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_t16_e64_gfx1250:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_t16_e64_gfx1250:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_t16_e64_gfx1250:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_t16_e64_gfx1250: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      break;
    }
    case AMDGPU::V_CEIL_F16_t16_e64_gfx11:
    case AMDGPU::V_CEIL_F16_t16_e64_gfx12:
    case AMDGPU::V_COS_F16V_COS_F16_t16_e64_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_t16_e64_gfx12:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_e64_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_e64_gfx12:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_e64_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_e64_gfx12:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_e64_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_e64_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e64_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e64_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e64_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e64_gfx12:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_e64_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_e64_gfx12:
    case AMDGPU::V_EXP_F16_t16_e64_gfx11:
    case AMDGPU::V_EXP_F16_t16_e64_gfx12:
    case AMDGPU::V_FLOOR_F16_t16_e64_gfx11:
    case AMDGPU::V_FLOOR_F16_t16_e64_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_e64_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_e64_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e64_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e64_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e64_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e64_gfx12:
    case AMDGPU::V_LOG_F16_t16_e64_gfx11:
    case AMDGPU::V_LOG_F16_t16_e64_gfx12:
    case AMDGPU::V_RCP_F16_t16_e64_gfx11:
    case AMDGPU::V_RCP_F16_t16_e64_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_e64_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_e64_gfx12:
    case AMDGPU::V_RSQ_F16_t16_e64_gfx11:
    case AMDGPU::V_RSQ_F16_t16_e64_gfx12:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_e64_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_e64_gfx12:
    case AMDGPU::V_SQRT_F16_t16_e64_gfx11:
    case AMDGPU::V_SQRT_F16_t16_e64_gfx12:
    case AMDGPU::V_TANH_F16V_TANH_F16_t16_e64_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_e64_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_e64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(4), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      break;
    }
    case AMDGPU::V_AND_B16_t16_e64_gfx11:
    case AMDGPU::V_AND_B16_t16_e64_gfx12:
    case AMDGPU::V_ASHRREV_I16_t16_e64_gfx11:
    case AMDGPU::V_ASHRREV_I16_t16_e64_gfx12:
    case AMDGPU::V_LSHLREV_B16_t16_e64_gfx11:
    case AMDGPU::V_LSHLREV_B16_t16_e64_gfx12:
    case AMDGPU::V_LSHRREV_B16_t16_e64_gfx11:
    case AMDGPU::V_LSHRREV_B16_t16_e64_gfx12:
    case AMDGPU::V_MAX_I16_t16_e64_gfx11:
    case AMDGPU::V_MAX_I16_t16_e64_gfx12:
    case AMDGPU::V_MAX_U16_t16_e64_gfx11:
    case AMDGPU::V_MAX_U16_t16_e64_gfx12:
    case AMDGPU::V_MIN_I16_t16_e64_gfx11:
    case AMDGPU::V_MIN_I16_t16_e64_gfx12:
    case AMDGPU::V_MIN_U16_t16_e64_gfx11:
    case AMDGPU::V_MIN_U16_t16_e64_gfx12:
    case AMDGPU::V_MUL_LO_U16_t16_e64_gfx11:
    case AMDGPU::V_MUL_LO_U16_t16_e64_gfx12:
    case AMDGPU::V_OR_B16_t16_e64_gfx11:
    case AMDGPU::V_OR_B16_t16_e64_gfx12:
    case AMDGPU::V_XOR_B16_t16_e64_gfx11:
    case AMDGPU::V_XOR_B16_t16_e64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      break;
    }
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_t16_e64_gfx11:
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_t16_e64_gfx12:
    case AMDGPU::V_ADD_NC_U16_t16_e64_gfx11:
    case AMDGPU::V_ADD_NC_U16_t16_e64_gfx12:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_t16_e64_gfx11:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_t16_e64_gfx12:
    case AMDGPU::V_SUB_NC_U16_t16_e64_gfx11:
    case AMDGPU::V_SUB_NC_U16_t16_e64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      break;
    }
    case AMDGPU::V_ADD_F16_t16_e64_gfx11:
    case AMDGPU::V_ADD_F16_t16_e64_gfx12:
    case AMDGPU::V_LDEXP_F16_t16_e64_gfx11:
    case AMDGPU::V_LDEXP_F16_t16_e64_gfx12:
    case AMDGPU::V_MAXIMUM_F16_t16_e64_gfx12:
    case AMDGPU::V_MAX_F16V_MAX_F16_t16_e64_gfx11:
    case AMDGPU::V_MAX_NUM_F16_t16_e64_gfx12:
    case AMDGPU::V_MINIMUM_F16_t16_e64_gfx12:
    case AMDGPU::V_MIN_F16V_MIN_F16_t16_e64_gfx11:
    case AMDGPU::V_MIN_NUM_F16_t16_e64_gfx12:
    case AMDGPU::V_MUL_F16_t16_e64_gfx11:
    case AMDGPU::V_MUL_F16_t16_e64_gfx12:
    case AMDGPU::V_SUBREV_F16_t16_e64_gfx11:
    case AMDGPU::V_SUBREV_F16_t16_e64_gfx12:
    case AMDGPU::V_SUB_F16_t16_e64_gfx11:
    case AMDGPU::V_SUB_F16_t16_e64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(6), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      break;
    }
    case AMDGPU::V_FMAC_F16_t16_e64_gfx11:
    case AMDGPU::V_FMAC_F16_t16_e64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      break;
    }
    case AMDGPU::V_CNDMASK_B16_t16_e64_gfx11:
    case AMDGPU::V_CNDMASK_B16_t16_e64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(5), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      break;
    }
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_t16_e64_gfx11:
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_t16_e64_gfx12:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_t16_e64_gfx11:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_t16_e64_gfx12:
    case AMDGPU::V_MAX3_I16_t16_e64_gfx11:
    case AMDGPU::V_MAX3_I16_t16_e64_gfx12:
    case AMDGPU::V_MAX3_U16_t16_e64_gfx11:
    case AMDGPU::V_MAX3_U16_t16_e64_gfx12:
    case AMDGPU::V_MED3_I16_t16_e64_gfx11:
    case AMDGPU::V_MED3_I16_t16_e64_gfx12:
    case AMDGPU::V_MED3_U16V_MED3_U16_t16_e64_gfx11:
    case AMDGPU::V_MED3_U16V_MED3_U16_t16_e64_gfx12:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_t16_e64_gfx11:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_t16_e64_gfx12:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_t16_e64_gfx11:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_t16_e64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      break;
    }
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_t16_e64_gfx11:
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_t16_e64_gfx12:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_t16_e64_gfx11:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_t16_e64_gfx12:
    case AMDGPU::V_MAX3_F16_t16_e64_gfx11:
    case AMDGPU::V_MAX3_NUM_F16_t16_e64_gfx12:
    case AMDGPU::V_MAXIMUM3_F16_t16_e64_gfx12:
    case AMDGPU::V_MAXIMUMMINIMUM_F16_t16_e64_gfx12:
    case AMDGPU::V_MAXMIN_F16_t16_e64_gfx11:
    case AMDGPU::V_MAXMIN_NUM_F16_t16_e64_gfx12:
    case AMDGPU::V_MED3_F16_t16_e64_gfx11:
    case AMDGPU::V_MED3_NUM_F16_t16_e64_gfx12:
    case AMDGPU::V_MIN3_F16_t16_e64_gfx11:
    case AMDGPU::V_MIN3_NUM_F16_t16_e64_gfx12:
    case AMDGPU::V_MINIMUM3_F16_t16_e64_gfx12:
    case AMDGPU::V_MINIMUMMAXIMUM_F16_t16_e64_gfx12:
    case AMDGPU::V_MINMAX_F16_t16_e64_gfx11:
    case AMDGPU::V_MINMAX_NUM_F16_t16_e64_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: src0_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 61, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 3), 14, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 11, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 8, 1);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 32, 9);
      // op: src1_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 62, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 12, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 9, 1);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16(MI, 4, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 41, 9);
      // op: src2_modifiers
      op.clearAllBits();
      getMachineOpValueT16(MI, 5, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 63, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 2), 13, 1);
      Value.insertBits(op.extractBitsAsZExtValue(1, 1), 10, 1);
      // op: src2
      op.clearAllBits();
      getMachineOpValueT16(MI, 6, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 50, 9);
      // op: clamp
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(7), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 15, 1);
      // op: omod
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(8), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(2, 0), 59, 2);
      break;
    }
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_t16_e32_gfx1250:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_e32_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_e32_gfx12:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_t16_e32_gfx1250:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_t16_e32_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_t16_e32_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e32_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e32_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      break;
    }
    case AMDGPU::V_CEIL_F16_t16_e32_gfx11:
    case AMDGPU::V_CEIL_F16_t16_e32_gfx12:
    case AMDGPU::V_COS_BF16V_COS_BF16_t16_e32_gfx1250:
    case AMDGPU::V_COS_F16V_COS_F16_t16_e32_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_t16_e32_gfx12:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_e32_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_e32_gfx12:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_e32_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_e32_gfx12:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_e32_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_e32_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e32_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e32_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e32_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e32_gfx12:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_e32_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_e32_gfx12:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_t16_e32_gfx1250:
    case AMDGPU::V_EXP_F16_t16_e32_gfx11:
    case AMDGPU::V_EXP_F16_t16_e32_gfx12:
    case AMDGPU::V_FLOOR_F16_t16_e32_gfx11:
    case AMDGPU::V_FLOOR_F16_t16_e32_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_e32_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_e32_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e32_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e32_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e32_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e32_gfx12:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_t16_e32_gfx1250:
    case AMDGPU::V_LOG_F16_t16_e32_gfx11:
    case AMDGPU::V_LOG_F16_t16_e32_gfx12:
    case AMDGPU::V_MOV_B16_t16_e32_gfx11:
    case AMDGPU::V_MOV_B16_t16_e32_gfx12:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_e32_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_e32_gfx12:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_t16_e32_gfx1250:
    case AMDGPU::V_RCP_F16_t16_e32_gfx11:
    case AMDGPU::V_RCP_F16_t16_e32_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_e32_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_e32_gfx12:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_t16_e32_gfx1250:
    case AMDGPU::V_RSQ_F16_t16_e32_gfx11:
    case AMDGPU::V_RSQ_F16_t16_e32_gfx12:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_t16_e32_gfx1250:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_e32_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_e32_gfx12:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_t16_e32_gfx1250:
    case AMDGPU::V_SQRT_F16_t16_e32_gfx11:
    case AMDGPU::V_SQRT_F16_t16_e32_gfx12:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_t16_e32_gfx1250:
    case AMDGPU::V_TANH_F16V_TANH_F16_t16_e32_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_e32_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_e32_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      break;
    }
    case AMDGPU::V_ADD_F16_t16_e32_gfx11:
    case AMDGPU::V_ADD_F16_t16_e32_gfx12:
    case AMDGPU::V_FMAC_F16_t16_e32_gfx11:
    case AMDGPU::V_FMAC_F16_t16_e32_gfx12:
    case AMDGPU::V_LDEXP_F16_t16_e32_gfx11:
    case AMDGPU::V_LDEXP_F16_t16_e32_gfx12:
    case AMDGPU::V_MAX_F16V_MAX_F16_t16_e32_gfx11:
    case AMDGPU::V_MAX_NUM_F16_t16_e32_gfx12:
    case AMDGPU::V_MIN_F16V_MIN_F16_t16_e32_gfx11:
    case AMDGPU::V_MIN_NUM_F16_t16_e32_gfx12:
    case AMDGPU::V_MUL_F16_t16_e32_gfx11:
    case AMDGPU::V_MUL_F16_t16_e32_gfx12:
    case AMDGPU::V_SUBREV_F16_t16_e32_gfx11:
    case AMDGPU::V_SUBREV_F16_t16_e32_gfx12:
    case AMDGPU::V_SUB_F16_t16_e32_gfx11:
    case AMDGPU::V_SUB_F16_t16_e32_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      break;
    }
    case AMDGPU::V_FMAAK_F16_t16_gfx11:
    case AMDGPU::V_FMAAK_F16_t16_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(3), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(32, 0), 32, 32);
      break;
    }
    case AMDGPU::V_FMAMK_F16_t16_gfx11:
    case AMDGPU::V_FMAMK_F16_t16_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 1, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      // op: src1
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 3, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 9, 8);
      // op: imm
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(32, 0), 32, 32);
      break;
    }
    case AMDGPU::V_SWAP_B16_gfx11:
    case AMDGPU::V_SWAP_B16_gfx12: {
      // op: vdst
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 0, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 17, 8);
      // op: src0
      op.clearAllBits();
      getMachineOpValueT16Lo128(MI, 2, op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(9, 0), 0, 9);
      break;
    }
    case AMDGPU::LDS_DIRECT_LOAD_gfx11: {
      // op: waitvdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 16, 4);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      break;
    }
    case AMDGPU::DS_DIRECT_LOAD_gfx12: {
      // op: waitvdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(1), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(4, 0), 16, 4);
      // op: vdst
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(0), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(8, 0), 0, 8);
      // op: waitvsrc
      op.clearAllBits();
      getMachineOpValue(MI, MI.getOperand(2), op, Fixups, STI);
      Value.insertBits(op.extractBitsAsZExtValue(1, 0), 23, 1);
      break;
    }
  default:
    reportUnsupportedInst(MI);
  }
  Inst = Value;
}

#ifdef GET_OPERAND_BIT_OFFSET
#undef GET_OPERAND_BIT_OFFSET

uint32_t AMDGPUMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
    unsigned OpNum,
    const MCSubtargetInfo &STI) const {
  switch (MI.getOpcode()) {
    case AMDGPU::BUFFER_GL0_INV_gfx10:
    case AMDGPU::BUFFER_GL0_INV_gfx11:
    case AMDGPU::BUFFER_GL1_INV_gfx10:
    case AMDGPU::BUFFER_GL1_INV_gfx11:
    case AMDGPU::BUFFER_INVL2_gfx90a:
    case AMDGPU::BUFFER_WBINVL1_SC_gfx6:
    case AMDGPU::BUFFER_WBINVL1_VOL_gfx7:
    case AMDGPU::BUFFER_WBINVL1_VOL_vi:
    case AMDGPU::BUFFER_WBINVL1_gfx6_gfx7:
    case AMDGPU::BUFFER_WBINVL1_vi:
    case AMDGPU::DS_NOP_gfx10:
    case AMDGPU::DS_NOP_gfx11:
    case AMDGPU::DS_NOP_gfx12:
    case AMDGPU::DS_NOP_gfx6_gfx7:
    case AMDGPU::DS_NOP_vi:
    case AMDGPU::S_BARRIER_INIT_M0_gfx12:
    case AMDGPU::S_BARRIER_JOIN_M0_gfx12:
    case AMDGPU::S_BARRIER_LEAVE_gfx12:
    case AMDGPU::S_BARRIER_SIGNAL_ISFIRST_M0_gfx12:
    case AMDGPU::S_BARRIER_SIGNAL_M0_gfx12:
    case AMDGPU::S_BARRIER_gfx10:
    case AMDGPU::S_BARRIER_gfx11:
    case AMDGPU::S_BARRIER_gfx6_gfx7:
    case AMDGPU::S_BARRIER_vi:
    case AMDGPU::S_CODE_END_gfx10:
    case AMDGPU::S_CODE_END_gfx11:
    case AMDGPU::S_CODE_END_gfx12:
    case AMDGPU::S_DCACHE_INV_VOL_ci:
    case AMDGPU::S_DCACHE_INV_VOL_vi:
    case AMDGPU::S_DCACHE_INV_gfx10:
    case AMDGPU::S_DCACHE_INV_gfx11:
    case AMDGPU::S_DCACHE_INV_gfx12:
    case AMDGPU::S_DCACHE_INV_si:
    case AMDGPU::S_DCACHE_INV_vi:
    case AMDGPU::S_DCACHE_WB_VOL_vi:
    case AMDGPU::S_DCACHE_WB_gfx10:
    case AMDGPU::S_DCACHE_WB_vi:
    case AMDGPU::S_ENDPGM_ORDERED_PS_DONE_gfx10:
    case AMDGPU::S_ENDPGM_ORDERED_PS_DONE_gfx11:
    case AMDGPU::S_ENDPGM_ORDERED_PS_DONE_vi:
    case AMDGPU::S_ENDPGM_SAVED_gfx10:
    case AMDGPU::S_ENDPGM_SAVED_gfx11:
    case AMDGPU::S_ENDPGM_SAVED_gfx12:
    case AMDGPU::S_ENDPGM_SAVED_gfx6_gfx7:
    case AMDGPU::S_ENDPGM_SAVED_vi:
    case AMDGPU::S_GL1_INV_gfx10:
    case AMDGPU::S_GL1_INV_gfx11:
    case AMDGPU::S_ICACHE_INV_gfx10:
    case AMDGPU::S_ICACHE_INV_gfx11:
    case AMDGPU::S_ICACHE_INV_gfx12:
    case AMDGPU::S_ICACHE_INV_gfx6_gfx7:
    case AMDGPU::S_ICACHE_INV_vi:
    case AMDGPU::S_SET_GPR_IDX_OFF_vi:
    case AMDGPU::S_TTRACEDATA_gfx10:
    case AMDGPU::S_TTRACEDATA_gfx11:
    case AMDGPU::S_TTRACEDATA_gfx12:
    case AMDGPU::S_TTRACEDATA_gfx6_gfx7:
    case AMDGPU::S_TTRACEDATA_vi:
    case AMDGPU::S_WAIT_IDLE_gfx10:
    case AMDGPU::S_WAIT_IDLE_gfx11:
    case AMDGPU::S_WAIT_IDLE_gfx12:
    case AMDGPU::S_WAKEUP_BARRIER_M0_gfx12:
    case AMDGPU::S_WAKEUP_gfx10:
    case AMDGPU::S_WAKEUP_gfx11:
    case AMDGPU::S_WAKEUP_gfx12:
    case AMDGPU::S_WAKEUP_vi:
    case AMDGPU::V_CLREXCP_e32_gfx10:
    case AMDGPU::V_CLREXCP_e32_gfx6_gfx7:
    case AMDGPU::V_CLREXCP_e32_vi:
    case AMDGPU::V_CLREXCP_e64_gfx10:
    case AMDGPU::V_CLREXCP_e64_gfx6_gfx7:
    case AMDGPU::V_CLREXCP_e64_vi:
    case AMDGPU::V_ILLEGAL:
    case AMDGPU::V_NOP_e32_gfx10:
    case AMDGPU::V_NOP_e32_gfx11:
    case AMDGPU::V_NOP_e32_gfx12:
    case AMDGPU::V_NOP_e32_gfx6_gfx7:
    case AMDGPU::V_NOP_e32_vi:
    case AMDGPU::V_NOP_e64_gfx10:
    case AMDGPU::V_NOP_e64_gfx11:
    case AMDGPU::V_NOP_e64_gfx12:
    case AMDGPU::V_NOP_e64_gfx6_gfx7:
    case AMDGPU::V_NOP_e64_vi:
    case AMDGPU::V_NOP_sdwa_gfx10:
    case AMDGPU::V_NOP_sdwa_gfx9:
    case AMDGPU::V_NOP_sdwa_vi:
    case AMDGPU::V_PIPEFLUSH_e32_gfx10:
    case AMDGPU::V_PIPEFLUSH_e32_gfx11:
    case AMDGPU::V_PIPEFLUSH_e32_gfx12:
    case AMDGPU::V_PIPEFLUSH_e64_gfx10:
    case AMDGPU::V_PIPEFLUSH_e64_gfx11:
    case AMDGPU::V_PIPEFLUSH_e64_gfx12: {
      break;
    }
    case AMDGPU::DS_CMPSTORE_B32_gfx12:
    case AMDGPU::DS_CMPSTORE_B64_gfx12:
    case AMDGPU::DS_MSKOR_B32_gfx12:
    case AMDGPU::DS_MSKOR_B64_gfx12: {
      switch (OpNum) {
      case 0:
        // op: addr
        return 32;
      case 1:
        // op: data0
        return 40;
      case 2:
        // op: data1
        return 48;
      case 3:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_WRITE2ST64_B32_gfx12:
    case AMDGPU::DS_WRITE2ST64_B64_gfx12:
    case AMDGPU::DS_WRITE2_B32_gfx12:
    case AMDGPU::DS_WRITE2_B64_gfx12: {
      switch (OpNum) {
      case 0:
        // op: addr
        return 32;
      case 1:
        // op: data0
        return 40;
      case 2:
        // op: data1
        return 48;
      case 3:
        // op: offset0
        return 0;
      case 4:
        // op: offset1
        return 8;
      }
      break;
    }
    case AMDGPU::DS_ADD_F32_gfx12:
    case AMDGPU::DS_ADD_F64_gfx12:
    case AMDGPU::DS_ADD_U32_gfx12:
    case AMDGPU::DS_ADD_U64_gfx12:
    case AMDGPU::DS_AND_B32_gfx12:
    case AMDGPU::DS_AND_B64_gfx12:
    case AMDGPU::DS_COND_SUB_U32_gfx12:
    case AMDGPU::DS_DEC_U32_gfx12:
    case AMDGPU::DS_DEC_U64_gfx12:
    case AMDGPU::DS_INC_U32_gfx12:
    case AMDGPU::DS_INC_U64_gfx12:
    case AMDGPU::DS_MAX_F32_gfx12:
    case AMDGPU::DS_MAX_F64_gfx12:
    case AMDGPU::DS_MAX_I32_gfx12:
    case AMDGPU::DS_MAX_I64_gfx12:
    case AMDGPU::DS_MAX_U32_gfx12:
    case AMDGPU::DS_MAX_U64_gfx12:
    case AMDGPU::DS_MIN_F32_gfx12:
    case AMDGPU::DS_MIN_F64_gfx12:
    case AMDGPU::DS_MIN_I32_gfx12:
    case AMDGPU::DS_MIN_I64_gfx12:
    case AMDGPU::DS_MIN_U32_gfx12:
    case AMDGPU::DS_MIN_U64_gfx12:
    case AMDGPU::DS_OR_B32_gfx12:
    case AMDGPU::DS_OR_B64_gfx12:
    case AMDGPU::DS_PK_ADD_BF16_gfx12:
    case AMDGPU::DS_PK_ADD_F16_gfx12:
    case AMDGPU::DS_RSUB_U32_gfx12:
    case AMDGPU::DS_RSUB_U64_gfx12:
    case AMDGPU::DS_SUB_CLAMP_U32_gfx12:
    case AMDGPU::DS_SUB_U32_gfx12:
    case AMDGPU::DS_SUB_U64_gfx12:
    case AMDGPU::DS_WRITE_B128_gfx12:
    case AMDGPU::DS_WRITE_B16_D16_HI_gfx12:
    case AMDGPU::DS_WRITE_B16_gfx12:
    case AMDGPU::DS_WRITE_B32_gfx12:
    case AMDGPU::DS_WRITE_B64_gfx12:
    case AMDGPU::DS_WRITE_B8_D16_HI_gfx12:
    case AMDGPU::DS_WRITE_B8_gfx12:
    case AMDGPU::DS_WRITE_B96_gfx12:
    case AMDGPU::DS_XOR_B32_gfx12:
    case AMDGPU::DS_XOR_B64_gfx12: {
      switch (OpNum) {
      case 0:
        // op: addr
        return 32;
      case 1:
        // op: data0
        return 40;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_ATOMIC_ASYNC_BARRIER_ARRIVE_B64_gfx12: {
      switch (OpNum) {
      case 0:
        // op: addr
        return 32;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::BUFFER_INV_gfx940:
    case AMDGPU::BUFFER_WBL2_gfx90a:
    case AMDGPU::BUFFER_WBL2_gfx940: {
      switch (OpNum) {
      case 0:
        // op: cpol
        return 14;
      }
      break;
    }
    case AMDGPU::GLOBAL_INV_gfx12:
    case AMDGPU::GLOBAL_WBINV_gfx12:
    case AMDGPU::GLOBAL_WB_gfx12:
    case AMDGPU::TENSOR_STOP_gfx1250: {
      switch (OpNum) {
      case 0:
        // op: cpol
        return 7;
      }
      break;
    }
    case AMDGPU::DS_GWS_BARRIER_vi:
    case AMDGPU::DS_GWS_INIT_vi:
    case AMDGPU::DS_GWS_SEMA_BR_vi: {
      switch (OpNum) {
      case 0:
        // op: data0
        return 25;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_GWS_BARRIER_gfx10:
    case AMDGPU::DS_GWS_BARRIER_gfx11:
    case AMDGPU::DS_GWS_BARRIER_gfx6_gfx7:
    case AMDGPU::DS_GWS_INIT_gfx10:
    case AMDGPU::DS_GWS_INIT_gfx11:
    case AMDGPU::DS_GWS_INIT_gfx6_gfx7:
    case AMDGPU::DS_GWS_SEMA_BR_gfx10:
    case AMDGPU::DS_GWS_SEMA_BR_gfx11:
    case AMDGPU::DS_GWS_SEMA_BR_gfx6_gfx7: {
      switch (OpNum) {
      case 0:
        // op: data0
        return 32;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_WRITE_ADDTID_B32_gfx12: {
      switch (OpNum) {
      case 0:
        // op: data0
        return 40;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::V_NOP_dpp8_gfx10: {
      switch (OpNum) {
      case 0:
        // op: dpp8
        return 40;
      case 1:
        // op: fi
        return 0;
      }
      break;
    }
    case AMDGPU::V_NOP_dpp_gfx10: {
      switch (OpNum) {
      case 0:
        // op: dpp_ctrl
        return 40;
      case 3:
        // op: bound_ctrl
        return 51;
      case 2:
        // op: bank_mask
        return 56;
      case 1:
        // op: row_mask
        return 60;
      case 4:
        // op: fi
        return 50;
      }
      break;
    }
    case AMDGPU::V_NOP_dpp_vi: {
      switch (OpNum) {
      case 0:
        // op: dpp_ctrl
        return 40;
      case 3:
        // op: bound_ctrl
        return 51;
      case 2:
        // op: bank_mask
        return 56;
      case 1:
        // op: row_mask
        return 60;
      }
      break;
    }
    case AMDGPU::DS_GWS_SEMA_P_gfx10:
    case AMDGPU::DS_GWS_SEMA_P_gfx11:
    case AMDGPU::DS_GWS_SEMA_P_gfx6_gfx7:
    case AMDGPU::DS_GWS_SEMA_P_vi:
    case AMDGPU::DS_GWS_SEMA_RELEASE_ALL_gfx10:
    case AMDGPU::DS_GWS_SEMA_RELEASE_ALL_gfx11:
    case AMDGPU::DS_GWS_SEMA_RELEASE_ALL_gfx7:
    case AMDGPU::DS_GWS_SEMA_RELEASE_ALL_vi:
    case AMDGPU::DS_GWS_SEMA_V_gfx10:
    case AMDGPU::DS_GWS_SEMA_V_gfx11:
    case AMDGPU::DS_GWS_SEMA_V_gfx6_gfx7:
    case AMDGPU::DS_GWS_SEMA_V_vi: {
      switch (OpNum) {
      case 0:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::S_PREFETCH_DATA_PC_REL_gfx12:
    case AMDGPU::S_PREFETCH_INST_PC_REL_gfx12: {
      switch (OpNum) {
      case 0:
        // op: offset
        return 32;
      case 1:
        // op: soffset
        return 57;
      case 2:
        // op: sdata
        return 6;
      }
      break;
    }
    case AMDGPU::TENSOR_SAVE_gfx1250: {
      switch (OpNum) {
      case 0:
        // op: saddr
        return 0;
      case 2:
        // op: cpol
        return 7;
      case 1:
        // op: offset
        return 72;
      }
      break;
    }
    case AMDGPU::FLAT_PREFETCH_B8_SADDR_gfx1250:
    case AMDGPU::GLOBAL_PREFETCH_B8_SADDR_gfx1250: {
      switch (OpNum) {
      case 0:
        // op: saddr
        return 0;
      case 3:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr
        return 64;
      case 2:
        // op: offset
        return 72;
      }
      break;
    }
    case AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B128_SADDR_gfx1250:
    case AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B32_SADDR_gfx1250:
    case AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B64_SADDR_gfx1250:
    case AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B8_SADDR_gfx1250: {
      switch (OpNum) {
      case 0:
        // op: saddr
        return 0;
      case 4:
        // op: cpol
        return 7;
      case 2:
        // op: vdata
        return 55;
      case 1:
        // op: vaddr
        return 64;
      case 3:
        // op: offset
        return 72;
      }
      break;
    }
    case AMDGPU::SCRATCH_LOAD_LDS_DWORD_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_SBYTE_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_SSHORT_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_UBYTE_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_USHORT_SADDR_gfx10: {
      switch (OpNum) {
      case 0:
        // op: saddr
        return 48;
      case 2:
        // op: cpol
        return 12;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::SCRATCH_LOAD_LDS_DWORD_SADDR_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_DWORD_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_LDS_SBYTE_SADDR_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_SBYTE_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_LDS_SSHORT_SADDR_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_SSHORT_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_LDS_UBYTE_SADDR_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_UBYTE_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_LDS_USHORT_SADDR_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_USHORT_SADDR_vi: {
      switch (OpNum) {
      case 0:
        // op: saddr
        return 48;
      case 2:
        // op: cpol
        return 16;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::S_BUFFER_PREFETCH_DATA_gfx12:
    case AMDGPU::S_PREFETCH_DATA_gfx12:
    case AMDGPU::S_PREFETCH_INST_gfx12: {
      switch (OpNum) {
      case 0:
        // op: sbase
        return 0;
      case 1:
        // op: offset
        return 32;
      case 2:
        // op: soffset
        return 57;
      case 3:
        // op: sdata
        return 6;
      }
      break;
    }
    case AMDGPU::S_DCACHE_DISCARD_IMM_gfx10:
    case AMDGPU::S_DCACHE_DISCARD_IMM_vi:
    case AMDGPU::S_DCACHE_DISCARD_X2_IMM_gfx10:
    case AMDGPU::S_DCACHE_DISCARD_X2_IMM_vi: {
      switch (OpNum) {
      case 0:
        // op: sbase
        return 0;
      case 1:
        // op: offset
        return 32;
      }
      break;
    }
    case AMDGPU::S_DCACHE_DISCARD_SGPR_vi:
    case AMDGPU::S_DCACHE_DISCARD_X2_SGPR_vi: {
      switch (OpNum) {
      case 0:
        // op: sbase
        return 0;
      case 1:
        // op: soffset
        return 32;
      }
      break;
    }
    case AMDGPU::S_DCACHE_DISCARD_SGPR_alt_gfx9:
    case AMDGPU::S_DCACHE_DISCARD_SGPR_gfx10:
    case AMDGPU::S_DCACHE_DISCARD_X2_SGPR_alt_gfx9:
    case AMDGPU::S_DCACHE_DISCARD_X2_SGPR_gfx10: {
      switch (OpNum) {
      case 0:
        // op: sbase
        return 0;
      case 1:
        // op: soffset
        return 57;
      }
      break;
    }
    case AMDGPU::S_DCACHE_DISCARD_SGPR_IMM_gfx10:
    case AMDGPU::S_DCACHE_DISCARD_SGPR_IMM_gfx9:
    case AMDGPU::S_DCACHE_DISCARD_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_DCACHE_DISCARD_X2_SGPR_IMM_gfx9: {
      switch (OpNum) {
      case 0:
        // op: sbase
        return 0;
      case 2:
        // op: offset
        return 32;
      case 1:
        // op: soffset
        return 57;
      }
      break;
    }
    case AMDGPU::S_MEMTIME_si: {
      switch (OpNum) {
      case 0:
        // op: sdst
        return 15;
      }
      break;
    }
    case AMDGPU::S_CALL_B64_gfx10:
    case AMDGPU::S_CALL_B64_gfx11:
    case AMDGPU::S_CALL_B64_gfx12:
    case AMDGPU::S_CALL_B64_gfx1250:
    case AMDGPU::S_CALL_B64_vi:
    case AMDGPU::S_CBRANCH_I_FORK_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_I_FORK_vi:
    case AMDGPU::S_CMOVK_I32_gfx10:
    case AMDGPU::S_CMOVK_I32_gfx11:
    case AMDGPU::S_CMOVK_I32_gfx12:
    case AMDGPU::S_CMOVK_I32_gfx6_gfx7:
    case AMDGPU::S_CMOVK_I32_vi:
    case AMDGPU::S_CMPK_EQ_I32_gfx10:
    case AMDGPU::S_CMPK_EQ_I32_gfx11:
    case AMDGPU::S_CMPK_EQ_I32_gfx6_gfx7:
    case AMDGPU::S_CMPK_EQ_I32_vi:
    case AMDGPU::S_CMPK_EQ_U32_gfx10:
    case AMDGPU::S_CMPK_EQ_U32_gfx11:
    case AMDGPU::S_CMPK_EQ_U32_gfx6_gfx7:
    case AMDGPU::S_CMPK_EQ_U32_vi:
    case AMDGPU::S_CMPK_GE_I32_gfx10:
    case AMDGPU::S_CMPK_GE_I32_gfx11:
    case AMDGPU::S_CMPK_GE_I32_gfx6_gfx7:
    case AMDGPU::S_CMPK_GE_I32_vi:
    case AMDGPU::S_CMPK_GE_U32_gfx10:
    case AMDGPU::S_CMPK_GE_U32_gfx11:
    case AMDGPU::S_CMPK_GE_U32_gfx6_gfx7:
    case AMDGPU::S_CMPK_GE_U32_vi:
    case AMDGPU::S_CMPK_GT_I32_gfx10:
    case AMDGPU::S_CMPK_GT_I32_gfx11:
    case AMDGPU::S_CMPK_GT_I32_gfx6_gfx7:
    case AMDGPU::S_CMPK_GT_I32_vi:
    case AMDGPU::S_CMPK_GT_U32_gfx10:
    case AMDGPU::S_CMPK_GT_U32_gfx11:
    case AMDGPU::S_CMPK_GT_U32_gfx6_gfx7:
    case AMDGPU::S_CMPK_GT_U32_vi:
    case AMDGPU::S_CMPK_LE_I32_gfx10:
    case AMDGPU::S_CMPK_LE_I32_gfx11:
    case AMDGPU::S_CMPK_LE_I32_gfx6_gfx7:
    case AMDGPU::S_CMPK_LE_I32_vi:
    case AMDGPU::S_CMPK_LE_U32_gfx10:
    case AMDGPU::S_CMPK_LE_U32_gfx11:
    case AMDGPU::S_CMPK_LE_U32_gfx6_gfx7:
    case AMDGPU::S_CMPK_LE_U32_vi:
    case AMDGPU::S_CMPK_LG_I32_gfx10:
    case AMDGPU::S_CMPK_LG_I32_gfx11:
    case AMDGPU::S_CMPK_LG_I32_gfx6_gfx7:
    case AMDGPU::S_CMPK_LG_I32_vi:
    case AMDGPU::S_CMPK_LG_U32_gfx10:
    case AMDGPU::S_CMPK_LG_U32_gfx11:
    case AMDGPU::S_CMPK_LG_U32_gfx6_gfx7:
    case AMDGPU::S_CMPK_LG_U32_vi:
    case AMDGPU::S_CMPK_LT_I32_gfx10:
    case AMDGPU::S_CMPK_LT_I32_gfx11:
    case AMDGPU::S_CMPK_LT_I32_gfx6_gfx7:
    case AMDGPU::S_CMPK_LT_I32_vi:
    case AMDGPU::S_CMPK_LT_U32_gfx10:
    case AMDGPU::S_CMPK_LT_U32_gfx11:
    case AMDGPU::S_CMPK_LT_U32_gfx6_gfx7:
    case AMDGPU::S_CMPK_LT_U32_vi:
    case AMDGPU::S_GETREG_B32_gfx10:
    case AMDGPU::S_GETREG_B32_gfx11:
    case AMDGPU::S_GETREG_B32_gfx12:
    case AMDGPU::S_GETREG_B32_gfx6_gfx7:
    case AMDGPU::S_GETREG_B32_vi:
    case AMDGPU::S_MOVK_I32_gfx10:
    case AMDGPU::S_MOVK_I32_gfx11:
    case AMDGPU::S_MOVK_I32_gfx12:
    case AMDGPU::S_MOVK_I32_gfx6_gfx7:
    case AMDGPU::S_MOVK_I32_vi:
    case AMDGPU::S_SETREG_B32_gfx10:
    case AMDGPU::S_SETREG_B32_gfx11:
    case AMDGPU::S_SETREG_B32_gfx12:
    case AMDGPU::S_SETREG_B32_gfx6_gfx7:
    case AMDGPU::S_SETREG_B32_vi:
    case AMDGPU::S_WAITCNT_EXPCNT_gfx10:
    case AMDGPU::S_WAITCNT_EXPCNT_gfx11:
    case AMDGPU::S_WAITCNT_LGKMCNT_gfx10:
    case AMDGPU::S_WAITCNT_LGKMCNT_gfx11:
    case AMDGPU::S_WAITCNT_VMCNT_gfx10:
    case AMDGPU::S_WAITCNT_VMCNT_gfx11:
    case AMDGPU::S_WAITCNT_VSCNT_gfx10:
    case AMDGPU::S_WAITCNT_VSCNT_gfx11: {
      switch (OpNum) {
      case 0:
        // op: sdst
        return 16;
      case 1:
        // op: simm16
        return 0;
      }
      break;
    }
    case AMDGPU::S_FMAAK_F32_gfx11:
    case AMDGPU::S_FMAAK_F32_gfx12: {
      switch (OpNum) {
      case 0:
        // op: sdst
        return 16;
      case 1:
        // op: src0
        return 0;
      case 2:
        // op: src1
        return 8;
      case 3:
        // op: imm
        return 32;
      }
      break;
    }
    case AMDGPU::S_ABSDIFF_I32_gfx10:
    case AMDGPU::S_ABSDIFF_I32_gfx11:
    case AMDGPU::S_ABSDIFF_I32_gfx12:
    case AMDGPU::S_ABSDIFF_I32_gfx6_gfx7:
    case AMDGPU::S_ABSDIFF_I32_vi:
    case AMDGPU::S_ADDC_U32_gfx10:
    case AMDGPU::S_ADDC_U32_gfx11:
    case AMDGPU::S_ADDC_U32_gfx12:
    case AMDGPU::S_ADDC_U32_gfx6_gfx7:
    case AMDGPU::S_ADDC_U32_vi:
    case AMDGPU::S_ADD_F16_gfx11:
    case AMDGPU::S_ADD_F16_gfx12:
    case AMDGPU::S_ADD_F32_gfx11:
    case AMDGPU::S_ADD_F32_gfx12:
    case AMDGPU::S_ADD_I32_gfx10:
    case AMDGPU::S_ADD_I32_gfx11:
    case AMDGPU::S_ADD_I32_gfx12:
    case AMDGPU::S_ADD_I32_gfx6_gfx7:
    case AMDGPU::S_ADD_I32_vi:
    case AMDGPU::S_ADD_U32_gfx10:
    case AMDGPU::S_ADD_U32_gfx11:
    case AMDGPU::S_ADD_U32_gfx12:
    case AMDGPU::S_ADD_U32_gfx6_gfx7:
    case AMDGPU::S_ADD_U32_vi:
    case AMDGPU::S_ADD_U64_gfx12:
    case AMDGPU::S_ANDN2_B32_gfx10:
    case AMDGPU::S_ANDN2_B32_gfx11:
    case AMDGPU::S_ANDN2_B32_gfx12:
    case AMDGPU::S_ANDN2_B32_gfx6_gfx7:
    case AMDGPU::S_ANDN2_B32_vi:
    case AMDGPU::S_ANDN2_B64_gfx10:
    case AMDGPU::S_ANDN2_B64_gfx11:
    case AMDGPU::S_ANDN2_B64_gfx12:
    case AMDGPU::S_ANDN2_B64_gfx6_gfx7:
    case AMDGPU::S_ANDN2_B64_vi:
    case AMDGPU::S_AND_B32_gfx10:
    case AMDGPU::S_AND_B32_gfx11:
    case AMDGPU::S_AND_B32_gfx12:
    case AMDGPU::S_AND_B32_gfx6_gfx7:
    case AMDGPU::S_AND_B32_vi:
    case AMDGPU::S_AND_B64_gfx10:
    case AMDGPU::S_AND_B64_gfx11:
    case AMDGPU::S_AND_B64_gfx12:
    case AMDGPU::S_AND_B64_gfx6_gfx7:
    case AMDGPU::S_AND_B64_vi:
    case AMDGPU::S_ASHR_I32_gfx10:
    case AMDGPU::S_ASHR_I32_gfx11:
    case AMDGPU::S_ASHR_I32_gfx12:
    case AMDGPU::S_ASHR_I32_gfx6_gfx7:
    case AMDGPU::S_ASHR_I32_vi:
    case AMDGPU::S_ASHR_I64_gfx10:
    case AMDGPU::S_ASHR_I64_gfx11:
    case AMDGPU::S_ASHR_I64_gfx12:
    case AMDGPU::S_ASHR_I64_gfx6_gfx7:
    case AMDGPU::S_ASHR_I64_vi:
    case AMDGPU::S_BFE_I32_gfx10:
    case AMDGPU::S_BFE_I32_gfx11:
    case AMDGPU::S_BFE_I32_gfx12:
    case AMDGPU::S_BFE_I32_gfx6_gfx7:
    case AMDGPU::S_BFE_I32_vi:
    case AMDGPU::S_BFE_I64_gfx10:
    case AMDGPU::S_BFE_I64_gfx11:
    case AMDGPU::S_BFE_I64_gfx12:
    case AMDGPU::S_BFE_I64_gfx6_gfx7:
    case AMDGPU::S_BFE_I64_vi:
    case AMDGPU::S_BFE_U32_gfx10:
    case AMDGPU::S_BFE_U32_gfx11:
    case AMDGPU::S_BFE_U32_gfx12:
    case AMDGPU::S_BFE_U32_gfx6_gfx7:
    case AMDGPU::S_BFE_U32_vi:
    case AMDGPU::S_BFE_U64_gfx10:
    case AMDGPU::S_BFE_U64_gfx11:
    case AMDGPU::S_BFE_U64_gfx12:
    case AMDGPU::S_BFE_U64_gfx6_gfx7:
    case AMDGPU::S_BFE_U64_vi:
    case AMDGPU::S_BFM_B32_gfx10:
    case AMDGPU::S_BFM_B32_gfx11:
    case AMDGPU::S_BFM_B32_gfx12:
    case AMDGPU::S_BFM_B32_gfx6_gfx7:
    case AMDGPU::S_BFM_B32_vi:
    case AMDGPU::S_BFM_B64_gfx10:
    case AMDGPU::S_BFM_B64_gfx11:
    case AMDGPU::S_BFM_B64_gfx12:
    case AMDGPU::S_BFM_B64_gfx6_gfx7:
    case AMDGPU::S_BFM_B64_vi:
    case AMDGPU::S_CSELECT_B32_gfx10:
    case AMDGPU::S_CSELECT_B32_gfx11:
    case AMDGPU::S_CSELECT_B32_gfx12:
    case AMDGPU::S_CSELECT_B32_gfx6_gfx7:
    case AMDGPU::S_CSELECT_B32_vi:
    case AMDGPU::S_CSELECT_B64_gfx10:
    case AMDGPU::S_CSELECT_B64_gfx11:
    case AMDGPU::S_CSELECT_B64_gfx12:
    case AMDGPU::S_CSELECT_B64_gfx6_gfx7:
    case AMDGPU::S_CSELECT_B64_vi:
    case AMDGPU::S_CVT_PK_RTZ_F16_F32_gfx11:
    case AMDGPU::S_CVT_PK_RTZ_F16_F32_gfx12:
    case AMDGPU::S_FMAC_F16_gfx11:
    case AMDGPU::S_FMAC_F16_gfx12:
    case AMDGPU::S_FMAC_F32_gfx11:
    case AMDGPU::S_FMAC_F32_gfx12:
    case AMDGPU::S_LSHL1_ADD_U32_gfx10:
    case AMDGPU::S_LSHL1_ADD_U32_gfx11:
    case AMDGPU::S_LSHL1_ADD_U32_gfx12:
    case AMDGPU::S_LSHL1_ADD_U32_vi:
    case AMDGPU::S_LSHL2_ADD_U32_gfx10:
    case AMDGPU::S_LSHL2_ADD_U32_gfx11:
    case AMDGPU::S_LSHL2_ADD_U32_gfx12:
    case AMDGPU::S_LSHL2_ADD_U32_vi:
    case AMDGPU::S_LSHL3_ADD_U32_gfx10:
    case AMDGPU::S_LSHL3_ADD_U32_gfx11:
    case AMDGPU::S_LSHL3_ADD_U32_gfx12:
    case AMDGPU::S_LSHL3_ADD_U32_vi:
    case AMDGPU::S_LSHL4_ADD_U32_gfx10:
    case AMDGPU::S_LSHL4_ADD_U32_gfx11:
    case AMDGPU::S_LSHL4_ADD_U32_gfx12:
    case AMDGPU::S_LSHL4_ADD_U32_vi:
    case AMDGPU::S_LSHL_B32_gfx10:
    case AMDGPU::S_LSHL_B32_gfx11:
    case AMDGPU::S_LSHL_B32_gfx12:
    case AMDGPU::S_LSHL_B32_gfx6_gfx7:
    case AMDGPU::S_LSHL_B32_vi:
    case AMDGPU::S_LSHL_B64_gfx10:
    case AMDGPU::S_LSHL_B64_gfx11:
    case AMDGPU::S_LSHL_B64_gfx12:
    case AMDGPU::S_LSHL_B64_gfx6_gfx7:
    case AMDGPU::S_LSHL_B64_vi:
    case AMDGPU::S_LSHR_B32_gfx10:
    case AMDGPU::S_LSHR_B32_gfx11:
    case AMDGPU::S_LSHR_B32_gfx12:
    case AMDGPU::S_LSHR_B32_gfx6_gfx7:
    case AMDGPU::S_LSHR_B32_vi:
    case AMDGPU::S_LSHR_B64_gfx10:
    case AMDGPU::S_LSHR_B64_gfx11:
    case AMDGPU::S_LSHR_B64_gfx12:
    case AMDGPU::S_LSHR_B64_gfx6_gfx7:
    case AMDGPU::S_LSHR_B64_vi:
    case AMDGPU::S_MAXIMUM_F16_gfx12:
    case AMDGPU::S_MAXIMUM_F32_gfx12:
    case AMDGPU::S_MAX_F16_gfx11:
    case AMDGPU::S_MAX_F16_gfx12:
    case AMDGPU::S_MAX_F32_gfx11:
    case AMDGPU::S_MAX_F32_gfx12:
    case AMDGPU::S_MAX_I32_gfx10:
    case AMDGPU::S_MAX_I32_gfx11:
    case AMDGPU::S_MAX_I32_gfx12:
    case AMDGPU::S_MAX_I32_gfx6_gfx7:
    case AMDGPU::S_MAX_I32_vi:
    case AMDGPU::S_MAX_U32_gfx10:
    case AMDGPU::S_MAX_U32_gfx11:
    case AMDGPU::S_MAX_U32_gfx12:
    case AMDGPU::S_MAX_U32_gfx6_gfx7:
    case AMDGPU::S_MAX_U32_vi:
    case AMDGPU::S_MINIMUM_F16_gfx12:
    case AMDGPU::S_MINIMUM_F32_gfx12:
    case AMDGPU::S_MIN_F16_gfx11:
    case AMDGPU::S_MIN_F16_gfx12:
    case AMDGPU::S_MIN_F32_gfx11:
    case AMDGPU::S_MIN_F32_gfx12:
    case AMDGPU::S_MIN_I32_gfx10:
    case AMDGPU::S_MIN_I32_gfx11:
    case AMDGPU::S_MIN_I32_gfx12:
    case AMDGPU::S_MIN_I32_gfx6_gfx7:
    case AMDGPU::S_MIN_I32_vi:
    case AMDGPU::S_MIN_U32_gfx10:
    case AMDGPU::S_MIN_U32_gfx11:
    case AMDGPU::S_MIN_U32_gfx12:
    case AMDGPU::S_MIN_U32_gfx6_gfx7:
    case AMDGPU::S_MIN_U32_vi:
    case AMDGPU::S_MUL_F16_gfx11:
    case AMDGPU::S_MUL_F16_gfx12:
    case AMDGPU::S_MUL_F32_gfx11:
    case AMDGPU::S_MUL_F32_gfx12:
    case AMDGPU::S_MUL_HI_I32_gfx10:
    case AMDGPU::S_MUL_HI_I32_gfx11:
    case AMDGPU::S_MUL_HI_I32_gfx12:
    case AMDGPU::S_MUL_HI_I32_vi:
    case AMDGPU::S_MUL_HI_U32_gfx10:
    case AMDGPU::S_MUL_HI_U32_gfx11:
    case AMDGPU::S_MUL_HI_U32_gfx12:
    case AMDGPU::S_MUL_HI_U32_vi:
    case AMDGPU::S_MUL_I32_gfx10:
    case AMDGPU::S_MUL_I32_gfx11:
    case AMDGPU::S_MUL_I32_gfx12:
    case AMDGPU::S_MUL_I32_gfx6_gfx7:
    case AMDGPU::S_MUL_I32_vi:
    case AMDGPU::S_MUL_U64_gfx12:
    case AMDGPU::S_NAND_B32_gfx10:
    case AMDGPU::S_NAND_B32_gfx11:
    case AMDGPU::S_NAND_B32_gfx12:
    case AMDGPU::S_NAND_B32_gfx6_gfx7:
    case AMDGPU::S_NAND_B32_vi:
    case AMDGPU::S_NAND_B64_gfx10:
    case AMDGPU::S_NAND_B64_gfx11:
    case AMDGPU::S_NAND_B64_gfx12:
    case AMDGPU::S_NAND_B64_gfx6_gfx7:
    case AMDGPU::S_NAND_B64_vi:
    case AMDGPU::S_NOR_B32_gfx10:
    case AMDGPU::S_NOR_B32_gfx11:
    case AMDGPU::S_NOR_B32_gfx12:
    case AMDGPU::S_NOR_B32_gfx6_gfx7:
    case AMDGPU::S_NOR_B32_vi:
    case AMDGPU::S_NOR_B64_gfx10:
    case AMDGPU::S_NOR_B64_gfx11:
    case AMDGPU::S_NOR_B64_gfx12:
    case AMDGPU::S_NOR_B64_gfx6_gfx7:
    case AMDGPU::S_NOR_B64_vi:
    case AMDGPU::S_ORN2_B32_gfx10:
    case AMDGPU::S_ORN2_B32_gfx11:
    case AMDGPU::S_ORN2_B32_gfx12:
    case AMDGPU::S_ORN2_B32_gfx6_gfx7:
    case AMDGPU::S_ORN2_B32_vi:
    case AMDGPU::S_ORN2_B64_gfx10:
    case AMDGPU::S_ORN2_B64_gfx11:
    case AMDGPU::S_ORN2_B64_gfx12:
    case AMDGPU::S_ORN2_B64_gfx6_gfx7:
    case AMDGPU::S_ORN2_B64_vi:
    case AMDGPU::S_OR_B32_gfx10:
    case AMDGPU::S_OR_B32_gfx11:
    case AMDGPU::S_OR_B32_gfx12:
    case AMDGPU::S_OR_B32_gfx6_gfx7:
    case AMDGPU::S_OR_B32_vi:
    case AMDGPU::S_OR_B64_gfx10:
    case AMDGPU::S_OR_B64_gfx11:
    case AMDGPU::S_OR_B64_gfx12:
    case AMDGPU::S_OR_B64_gfx6_gfx7:
    case AMDGPU::S_OR_B64_vi:
    case AMDGPU::S_PACK_HH_B32_B16_gfx10:
    case AMDGPU::S_PACK_HH_B32_B16_gfx11:
    case AMDGPU::S_PACK_HH_B32_B16_gfx12:
    case AMDGPU::S_PACK_HH_B32_B16_vi:
    case AMDGPU::S_PACK_HL_B32_B16_gfx11:
    case AMDGPU::S_PACK_HL_B32_B16_gfx12:
    case AMDGPU::S_PACK_LH_B32_B16_gfx10:
    case AMDGPU::S_PACK_LH_B32_B16_gfx11:
    case AMDGPU::S_PACK_LH_B32_B16_gfx12:
    case AMDGPU::S_PACK_LH_B32_B16_vi:
    case AMDGPU::S_PACK_LL_B32_B16_gfx10:
    case AMDGPU::S_PACK_LL_B32_B16_gfx11:
    case AMDGPU::S_PACK_LL_B32_B16_gfx12:
    case AMDGPU::S_PACK_LL_B32_B16_vi:
    case AMDGPU::S_SUBB_U32_gfx10:
    case AMDGPU::S_SUBB_U32_gfx11:
    case AMDGPU::S_SUBB_U32_gfx12:
    case AMDGPU::S_SUBB_U32_gfx6_gfx7:
    case AMDGPU::S_SUBB_U32_vi:
    case AMDGPU::S_SUB_F16_gfx11:
    case AMDGPU::S_SUB_F16_gfx12:
    case AMDGPU::S_SUB_F32_gfx11:
    case AMDGPU::S_SUB_F32_gfx12:
    case AMDGPU::S_SUB_I32_gfx10:
    case AMDGPU::S_SUB_I32_gfx11:
    case AMDGPU::S_SUB_I32_gfx12:
    case AMDGPU::S_SUB_I32_gfx6_gfx7:
    case AMDGPU::S_SUB_I32_vi:
    case AMDGPU::S_SUB_U32_gfx10:
    case AMDGPU::S_SUB_U32_gfx11:
    case AMDGPU::S_SUB_U32_gfx12:
    case AMDGPU::S_SUB_U32_gfx6_gfx7:
    case AMDGPU::S_SUB_U32_vi:
    case AMDGPU::S_SUB_U64_gfx12:
    case AMDGPU::S_XNOR_B32_gfx10:
    case AMDGPU::S_XNOR_B32_gfx11:
    case AMDGPU::S_XNOR_B32_gfx12:
    case AMDGPU::S_XNOR_B32_gfx6_gfx7:
    case AMDGPU::S_XNOR_B32_vi:
    case AMDGPU::S_XNOR_B64_gfx10:
    case AMDGPU::S_XNOR_B64_gfx11:
    case AMDGPU::S_XNOR_B64_gfx12:
    case AMDGPU::S_XNOR_B64_gfx6_gfx7:
    case AMDGPU::S_XNOR_B64_vi:
    case AMDGPU::S_XOR_B32_gfx10:
    case AMDGPU::S_XOR_B32_gfx11:
    case AMDGPU::S_XOR_B32_gfx12:
    case AMDGPU::S_XOR_B32_gfx6_gfx7:
    case AMDGPU::S_XOR_B32_vi:
    case AMDGPU::S_XOR_B64_gfx10:
    case AMDGPU::S_XOR_B64_gfx11:
    case AMDGPU::S_XOR_B64_gfx12:
    case AMDGPU::S_XOR_B64_gfx6_gfx7:
    case AMDGPU::S_XOR_B64_vi: {
      switch (OpNum) {
      case 0:
        // op: sdst
        return 16;
      case 1:
        // op: src0
        return 0;
      case 2:
        // op: src1
        return 8;
      }
      break;
    }
    case AMDGPU::S_FMAMK_F32_gfx11:
    case AMDGPU::S_FMAMK_F32_gfx12: {
      switch (OpNum) {
      case 0:
        // op: sdst
        return 16;
      case 1:
        // op: src0
        return 0;
      case 3:
        // op: src1
        return 8;
      case 2:
        // op: imm
        return 32;
      }
      break;
    }
    case AMDGPU::S_ABS_I32_gfx10:
    case AMDGPU::S_ABS_I32_gfx11:
    case AMDGPU::S_ABS_I32_gfx12:
    case AMDGPU::S_ABS_I32_gfx6_gfx7:
    case AMDGPU::S_ABS_I32_vi:
    case AMDGPU::S_ANDN1_SAVEEXEC_B32_gfx10:
    case AMDGPU::S_ANDN1_SAVEEXEC_B32_gfx11:
    case AMDGPU::S_ANDN1_SAVEEXEC_B32_gfx12:
    case AMDGPU::S_ANDN1_SAVEEXEC_B64_gfx10:
    case AMDGPU::S_ANDN1_SAVEEXEC_B64_gfx11:
    case AMDGPU::S_ANDN1_SAVEEXEC_B64_gfx12:
    case AMDGPU::S_ANDN1_SAVEEXEC_B64_vi:
    case AMDGPU::S_ANDN1_WREXEC_B32_gfx10:
    case AMDGPU::S_ANDN1_WREXEC_B32_gfx11:
    case AMDGPU::S_ANDN1_WREXEC_B32_gfx12:
    case AMDGPU::S_ANDN1_WREXEC_B64_gfx10:
    case AMDGPU::S_ANDN1_WREXEC_B64_gfx11:
    case AMDGPU::S_ANDN1_WREXEC_B64_gfx12:
    case AMDGPU::S_ANDN1_WREXEC_B64_vi:
    case AMDGPU::S_ANDN2_SAVEEXEC_B32_gfx10:
    case AMDGPU::S_ANDN2_SAVEEXEC_B32_gfx11:
    case AMDGPU::S_ANDN2_SAVEEXEC_B32_gfx12:
    case AMDGPU::S_ANDN2_SAVEEXEC_B64_gfx10:
    case AMDGPU::S_ANDN2_SAVEEXEC_B64_gfx11:
    case AMDGPU::S_ANDN2_SAVEEXEC_B64_gfx12:
    case AMDGPU::S_ANDN2_SAVEEXEC_B64_gfx6_gfx7:
    case AMDGPU::S_ANDN2_SAVEEXEC_B64_vi:
    case AMDGPU::S_ANDN2_WREXEC_B32_gfx10:
    case AMDGPU::S_ANDN2_WREXEC_B32_gfx11:
    case AMDGPU::S_ANDN2_WREXEC_B32_gfx12:
    case AMDGPU::S_ANDN2_WREXEC_B64_gfx10:
    case AMDGPU::S_ANDN2_WREXEC_B64_gfx11:
    case AMDGPU::S_ANDN2_WREXEC_B64_gfx12:
    case AMDGPU::S_ANDN2_WREXEC_B64_vi:
    case AMDGPU::S_AND_SAVEEXEC_B32_gfx10:
    case AMDGPU::S_AND_SAVEEXEC_B32_gfx11:
    case AMDGPU::S_AND_SAVEEXEC_B32_gfx12:
    case AMDGPU::S_AND_SAVEEXEC_B64_gfx10:
    case AMDGPU::S_AND_SAVEEXEC_B64_gfx11:
    case AMDGPU::S_AND_SAVEEXEC_B64_gfx12:
    case AMDGPU::S_AND_SAVEEXEC_B64_gfx6_gfx7:
    case AMDGPU::S_AND_SAVEEXEC_B64_vi:
    case AMDGPU::S_BCNT0_I32_B32_gfx10:
    case AMDGPU::S_BCNT0_I32_B32_gfx11:
    case AMDGPU::S_BCNT0_I32_B32_gfx12:
    case AMDGPU::S_BCNT0_I32_B32_gfx6_gfx7:
    case AMDGPU::S_BCNT0_I32_B32_vi:
    case AMDGPU::S_BCNT0_I32_B64_gfx10:
    case AMDGPU::S_BCNT0_I32_B64_gfx11:
    case AMDGPU::S_BCNT0_I32_B64_gfx12:
    case AMDGPU::S_BCNT0_I32_B64_gfx6_gfx7:
    case AMDGPU::S_BCNT0_I32_B64_vi:
    case AMDGPU::S_BCNT1_I32_B32_gfx10:
    case AMDGPU::S_BCNT1_I32_B32_gfx11:
    case AMDGPU::S_BCNT1_I32_B32_gfx12:
    case AMDGPU::S_BCNT1_I32_B32_gfx6_gfx7:
    case AMDGPU::S_BCNT1_I32_B32_vi:
    case AMDGPU::S_BCNT1_I32_B64_gfx10:
    case AMDGPU::S_BCNT1_I32_B64_gfx11:
    case AMDGPU::S_BCNT1_I32_B64_gfx12:
    case AMDGPU::S_BCNT1_I32_B64_gfx6_gfx7:
    case AMDGPU::S_BCNT1_I32_B64_vi:
    case AMDGPU::S_BITREPLICATE_B64_B32_gfx10:
    case AMDGPU::S_BITREPLICATE_B64_B32_gfx11:
    case AMDGPU::S_BITREPLICATE_B64_B32_gfx12:
    case AMDGPU::S_BITREPLICATE_B64_B32_vi:
    case AMDGPU::S_BITSET0_B32_gfx10:
    case AMDGPU::S_BITSET0_B32_gfx11:
    case AMDGPU::S_BITSET0_B32_gfx12:
    case AMDGPU::S_BITSET0_B32_gfx6_gfx7:
    case AMDGPU::S_BITSET0_B32_vi:
    case AMDGPU::S_BITSET0_B64_gfx10:
    case AMDGPU::S_BITSET0_B64_gfx11:
    case AMDGPU::S_BITSET0_B64_gfx12:
    case AMDGPU::S_BITSET0_B64_gfx6_gfx7:
    case AMDGPU::S_BITSET0_B64_vi:
    case AMDGPU::S_BITSET1_B32_gfx10:
    case AMDGPU::S_BITSET1_B32_gfx11:
    case AMDGPU::S_BITSET1_B32_gfx12:
    case AMDGPU::S_BITSET1_B32_gfx6_gfx7:
    case AMDGPU::S_BITSET1_B32_vi:
    case AMDGPU::S_BITSET1_B64_gfx10:
    case AMDGPU::S_BITSET1_B64_gfx11:
    case AMDGPU::S_BITSET1_B64_gfx12:
    case AMDGPU::S_BITSET1_B64_gfx6_gfx7:
    case AMDGPU::S_BITSET1_B64_vi:
    case AMDGPU::S_BREV_B32_gfx10:
    case AMDGPU::S_BREV_B32_gfx11:
    case AMDGPU::S_BREV_B32_gfx12:
    case AMDGPU::S_BREV_B32_gfx6_gfx7:
    case AMDGPU::S_BREV_B32_vi:
    case AMDGPU::S_BREV_B64_gfx10:
    case AMDGPU::S_BREV_B64_gfx11:
    case AMDGPU::S_BREV_B64_gfx12:
    case AMDGPU::S_BREV_B64_gfx6_gfx7:
    case AMDGPU::S_BREV_B64_vi:
    case AMDGPU::S_CEIL_F16_gfx11:
    case AMDGPU::S_CEIL_F16_gfx12:
    case AMDGPU::S_CEIL_F32_gfx11:
    case AMDGPU::S_CEIL_F32_gfx12:
    case AMDGPU::S_CMOV_B32_gfx10:
    case AMDGPU::S_CMOV_B32_gfx11:
    case AMDGPU::S_CMOV_B32_gfx12:
    case AMDGPU::S_CMOV_B32_gfx6_gfx7:
    case AMDGPU::S_CMOV_B32_vi:
    case AMDGPU::S_CMOV_B64_gfx10:
    case AMDGPU::S_CMOV_B64_gfx11:
    case AMDGPU::S_CMOV_B64_gfx12:
    case AMDGPU::S_CMOV_B64_gfx6_gfx7:
    case AMDGPU::S_CMOV_B64_vi:
    case AMDGPU::S_CVT_F16_F32_gfx11:
    case AMDGPU::S_CVT_F16_F32_gfx12:
    case AMDGPU::S_CVT_F32_F16_gfx11:
    case AMDGPU::S_CVT_F32_F16_gfx12:
    case AMDGPU::S_CVT_F32_I32_gfx11:
    case AMDGPU::S_CVT_F32_I32_gfx12:
    case AMDGPU::S_CVT_F32_U32_gfx11:
    case AMDGPU::S_CVT_F32_U32_gfx12:
    case AMDGPU::S_CVT_HI_F32_F16_gfx11:
    case AMDGPU::S_CVT_HI_F32_F16_gfx12:
    case AMDGPU::S_CVT_I32_F32_gfx11:
    case AMDGPU::S_CVT_I32_F32_gfx12:
    case AMDGPU::S_CVT_U32_F32_gfx11:
    case AMDGPU::S_CVT_U32_F32_gfx12:
    case AMDGPU::S_FF0_I32_B32_gfx10:
    case AMDGPU::S_FF0_I32_B32_gfx6_gfx7:
    case AMDGPU::S_FF0_I32_B32_vi:
    case AMDGPU::S_FF0_I32_B64_gfx10:
    case AMDGPU::S_FF0_I32_B64_gfx6_gfx7:
    case AMDGPU::S_FF0_I32_B64_vi:
    case AMDGPU::S_FF1_I32_B32_gfx10:
    case AMDGPU::S_FF1_I32_B32_gfx11:
    case AMDGPU::S_FF1_I32_B32_gfx12:
    case AMDGPU::S_FF1_I32_B32_gfx6_gfx7:
    case AMDGPU::S_FF1_I32_B32_vi:
    case AMDGPU::S_FF1_I32_B64_gfx10:
    case AMDGPU::S_FF1_I32_B64_gfx11:
    case AMDGPU::S_FF1_I32_B64_gfx12:
    case AMDGPU::S_FF1_I32_B64_gfx6_gfx7:
    case AMDGPU::S_FF1_I32_B64_vi:
    case AMDGPU::S_FLBIT_I32_B32_gfx10:
    case AMDGPU::S_FLBIT_I32_B32_gfx11:
    case AMDGPU::S_FLBIT_I32_B32_gfx12:
    case AMDGPU::S_FLBIT_I32_B32_gfx6_gfx7:
    case AMDGPU::S_FLBIT_I32_B32_vi:
    case AMDGPU::S_FLBIT_I32_B64_gfx10:
    case AMDGPU::S_FLBIT_I32_B64_gfx11:
    case AMDGPU::S_FLBIT_I32_B64_gfx12:
    case AMDGPU::S_FLBIT_I32_B64_gfx6_gfx7:
    case AMDGPU::S_FLBIT_I32_B64_vi:
    case AMDGPU::S_FLBIT_I32_I64_gfx10:
    case AMDGPU::S_FLBIT_I32_I64_gfx11:
    case AMDGPU::S_FLBIT_I32_I64_gfx12:
    case AMDGPU::S_FLBIT_I32_I64_gfx6_gfx7:
    case AMDGPU::S_FLBIT_I32_I64_vi:
    case AMDGPU::S_FLBIT_I32_gfx10:
    case AMDGPU::S_FLBIT_I32_gfx11:
    case AMDGPU::S_FLBIT_I32_gfx12:
    case AMDGPU::S_FLBIT_I32_gfx6_gfx7:
    case AMDGPU::S_FLBIT_I32_vi:
    case AMDGPU::S_FLOOR_F16_gfx11:
    case AMDGPU::S_FLOOR_F16_gfx12:
    case AMDGPU::S_FLOOR_F32_gfx11:
    case AMDGPU::S_FLOOR_F32_gfx12:
    case AMDGPU::S_GET_BARRIER_STATE_IMM_gfx12:
    case AMDGPU::S_MOVRELD_B32_gfx10:
    case AMDGPU::S_MOVRELD_B32_gfx11:
    case AMDGPU::S_MOVRELD_B32_gfx12:
    case AMDGPU::S_MOVRELD_B32_gfx6_gfx7:
    case AMDGPU::S_MOVRELD_B32_vi:
    case AMDGPU::S_MOVRELD_B64_gfx10:
    case AMDGPU::S_MOVRELD_B64_gfx11:
    case AMDGPU::S_MOVRELD_B64_gfx12:
    case AMDGPU::S_MOVRELD_B64_gfx6_gfx7:
    case AMDGPU::S_MOVRELD_B64_vi:
    case AMDGPU::S_MOVRELSD_2_B32_gfx10:
    case AMDGPU::S_MOVRELSD_2_B32_gfx11:
    case AMDGPU::S_MOVRELSD_2_B32_gfx12:
    case AMDGPU::S_MOVRELS_B32_gfx10:
    case AMDGPU::S_MOVRELS_B32_gfx11:
    case AMDGPU::S_MOVRELS_B32_gfx12:
    case AMDGPU::S_MOVRELS_B32_gfx6_gfx7:
    case AMDGPU::S_MOVRELS_B32_vi:
    case AMDGPU::S_MOVRELS_B64_gfx10:
    case AMDGPU::S_MOVRELS_B64_gfx11:
    case AMDGPU::S_MOVRELS_B64_gfx12:
    case AMDGPU::S_MOVRELS_B64_gfx6_gfx7:
    case AMDGPU::S_MOVRELS_B64_vi:
    case AMDGPU::S_MOV_B32_gfx10:
    case AMDGPU::S_MOV_B32_gfx11:
    case AMDGPU::S_MOV_B32_gfx12:
    case AMDGPU::S_MOV_B32_gfx6_gfx7:
    case AMDGPU::S_MOV_B32_vi:
    case AMDGPU::S_MOV_B64_gfx10:
    case AMDGPU::S_MOV_B64_gfx11:
    case AMDGPU::S_MOV_B64_gfx12:
    case AMDGPU::S_MOV_B64_gfx6_gfx7:
    case AMDGPU::S_MOV_B64_vi:
    case AMDGPU::S_NAND_SAVEEXEC_B32_gfx10:
    case AMDGPU::S_NAND_SAVEEXEC_B32_gfx11:
    case AMDGPU::S_NAND_SAVEEXEC_B32_gfx12:
    case AMDGPU::S_NAND_SAVEEXEC_B64_gfx10:
    case AMDGPU::S_NAND_SAVEEXEC_B64_gfx11:
    case AMDGPU::S_NAND_SAVEEXEC_B64_gfx12:
    case AMDGPU::S_NAND_SAVEEXEC_B64_gfx6_gfx7:
    case AMDGPU::S_NAND_SAVEEXEC_B64_vi:
    case AMDGPU::S_NOR_SAVEEXEC_B32_gfx10:
    case AMDGPU::S_NOR_SAVEEXEC_B32_gfx11:
    case AMDGPU::S_NOR_SAVEEXEC_B32_gfx12:
    case AMDGPU::S_NOR_SAVEEXEC_B64_gfx10:
    case AMDGPU::S_NOR_SAVEEXEC_B64_gfx11:
    case AMDGPU::S_NOR_SAVEEXEC_B64_gfx12:
    case AMDGPU::S_NOR_SAVEEXEC_B64_gfx6_gfx7:
    case AMDGPU::S_NOR_SAVEEXEC_B64_vi:
    case AMDGPU::S_NOT_B32_gfx10:
    case AMDGPU::S_NOT_B32_gfx11:
    case AMDGPU::S_NOT_B32_gfx12:
    case AMDGPU::S_NOT_B32_gfx6_gfx7:
    case AMDGPU::S_NOT_B32_vi:
    case AMDGPU::S_NOT_B64_gfx10:
    case AMDGPU::S_NOT_B64_gfx11:
    case AMDGPU::S_NOT_B64_gfx12:
    case AMDGPU::S_NOT_B64_gfx6_gfx7:
    case AMDGPU::S_NOT_B64_vi:
    case AMDGPU::S_ORN1_SAVEEXEC_B32_gfx10:
    case AMDGPU::S_ORN1_SAVEEXEC_B32_gfx11:
    case AMDGPU::S_ORN1_SAVEEXEC_B32_gfx12:
    case AMDGPU::S_ORN1_SAVEEXEC_B64_gfx10:
    case AMDGPU::S_ORN1_SAVEEXEC_B64_gfx11:
    case AMDGPU::S_ORN1_SAVEEXEC_B64_gfx12:
    case AMDGPU::S_ORN1_SAVEEXEC_B64_vi:
    case AMDGPU::S_ORN2_SAVEEXEC_B32_gfx10:
    case AMDGPU::S_ORN2_SAVEEXEC_B32_gfx11:
    case AMDGPU::S_ORN2_SAVEEXEC_B32_gfx12:
    case AMDGPU::S_ORN2_SAVEEXEC_B64_gfx10:
    case AMDGPU::S_ORN2_SAVEEXEC_B64_gfx11:
    case AMDGPU::S_ORN2_SAVEEXEC_B64_gfx12:
    case AMDGPU::S_ORN2_SAVEEXEC_B64_gfx6_gfx7:
    case AMDGPU::S_ORN2_SAVEEXEC_B64_vi:
    case AMDGPU::S_OR_SAVEEXEC_B32_gfx10:
    case AMDGPU::S_OR_SAVEEXEC_B32_gfx11:
    case AMDGPU::S_OR_SAVEEXEC_B32_gfx12:
    case AMDGPU::S_OR_SAVEEXEC_B64_gfx10:
    case AMDGPU::S_OR_SAVEEXEC_B64_gfx11:
    case AMDGPU::S_OR_SAVEEXEC_B64_gfx12:
    case AMDGPU::S_OR_SAVEEXEC_B64_gfx6_gfx7:
    case AMDGPU::S_OR_SAVEEXEC_B64_vi:
    case AMDGPU::S_QUADMASK_B32_gfx10:
    case AMDGPU::S_QUADMASK_B32_gfx11:
    case AMDGPU::S_QUADMASK_B32_gfx12:
    case AMDGPU::S_QUADMASK_B32_gfx6_gfx7:
    case AMDGPU::S_QUADMASK_B32_vi:
    case AMDGPU::S_QUADMASK_B64_gfx10:
    case AMDGPU::S_QUADMASK_B64_gfx11:
    case AMDGPU::S_QUADMASK_B64_gfx12:
    case AMDGPU::S_QUADMASK_B64_gfx6_gfx7:
    case AMDGPU::S_QUADMASK_B64_vi:
    case AMDGPU::S_RNDNE_F16_gfx11:
    case AMDGPU::S_RNDNE_F16_gfx12:
    case AMDGPU::S_RNDNE_F32_gfx11:
    case AMDGPU::S_RNDNE_F32_gfx12:
    case AMDGPU::S_SENDMSG_RTN_B32_gfx11:
    case AMDGPU::S_SENDMSG_RTN_B32_gfx12:
    case AMDGPU::S_SENDMSG_RTN_B64_gfx11:
    case AMDGPU::S_SENDMSG_RTN_B64_gfx12:
    case AMDGPU::S_SEXT_I32_I16_gfx10:
    case AMDGPU::S_SEXT_I32_I16_gfx11:
    case AMDGPU::S_SEXT_I32_I16_gfx12:
    case AMDGPU::S_SEXT_I32_I16_gfx6_gfx7:
    case AMDGPU::S_SEXT_I32_I16_vi:
    case AMDGPU::S_SEXT_I32_I8_gfx10:
    case AMDGPU::S_SEXT_I32_I8_gfx11:
    case AMDGPU::S_SEXT_I32_I8_gfx12:
    case AMDGPU::S_SEXT_I32_I8_gfx6_gfx7:
    case AMDGPU::S_SEXT_I32_I8_vi:
    case AMDGPU::S_SWAPPC_B64_gfx10:
    case AMDGPU::S_SWAPPC_B64_gfx11:
    case AMDGPU::S_SWAPPC_B64_gfx12:
    case AMDGPU::S_SWAPPC_B64_gfx1250:
    case AMDGPU::S_SWAPPC_B64_gfx6_gfx7:
    case AMDGPU::S_SWAPPC_B64_vi:
    case AMDGPU::S_TRUNC_F16_gfx11:
    case AMDGPU::S_TRUNC_F16_gfx12:
    case AMDGPU::S_TRUNC_F32_gfx11:
    case AMDGPU::S_TRUNC_F32_gfx12:
    case AMDGPU::S_WQM_B32_gfx10:
    case AMDGPU::S_WQM_B32_gfx11:
    case AMDGPU::S_WQM_B32_gfx12:
    case AMDGPU::S_WQM_B32_gfx6_gfx7:
    case AMDGPU::S_WQM_B32_vi:
    case AMDGPU::S_WQM_B64_gfx10:
    case AMDGPU::S_WQM_B64_gfx11:
    case AMDGPU::S_WQM_B64_gfx12:
    case AMDGPU::S_WQM_B64_gfx6_gfx7:
    case AMDGPU::S_WQM_B64_vi:
    case AMDGPU::S_XNOR_SAVEEXEC_B32_gfx10:
    case AMDGPU::S_XNOR_SAVEEXEC_B32_gfx11:
    case AMDGPU::S_XNOR_SAVEEXEC_B32_gfx12:
    case AMDGPU::S_XNOR_SAVEEXEC_B64_gfx10:
    case AMDGPU::S_XNOR_SAVEEXEC_B64_gfx11:
    case AMDGPU::S_XNOR_SAVEEXEC_B64_gfx12:
    case AMDGPU::S_XNOR_SAVEEXEC_B64_gfx6_gfx7:
    case AMDGPU::S_XNOR_SAVEEXEC_B64_vi:
    case AMDGPU::S_XOR_SAVEEXEC_B32_gfx10:
    case AMDGPU::S_XOR_SAVEEXEC_B32_gfx11:
    case AMDGPU::S_XOR_SAVEEXEC_B32_gfx12:
    case AMDGPU::S_XOR_SAVEEXEC_B64_gfx10:
    case AMDGPU::S_XOR_SAVEEXEC_B64_gfx11:
    case AMDGPU::S_XOR_SAVEEXEC_B64_gfx12:
    case AMDGPU::S_XOR_SAVEEXEC_B64_gfx6_gfx7:
    case AMDGPU::S_XOR_SAVEEXEC_B64_vi: {
      switch (OpNum) {
      case 0:
        // op: sdst
        return 16;
      case 1:
        // op: src0
        return 0;
      }
      break;
    }
    case AMDGPU::S_ADDK_I32_gfx10:
    case AMDGPU::S_ADDK_I32_gfx11:
    case AMDGPU::S_ADDK_I32_gfx12:
    case AMDGPU::S_ADDK_I32_gfx6_gfx7:
    case AMDGPU::S_ADDK_I32_vi:
    case AMDGPU::S_MULK_I32_gfx10:
    case AMDGPU::S_MULK_I32_gfx11:
    case AMDGPU::S_MULK_I32_gfx12:
    case AMDGPU::S_MULK_I32_gfx6_gfx7:
    case AMDGPU::S_MULK_I32_vi: {
      switch (OpNum) {
      case 0:
        // op: sdst
        return 16;
      case 2:
        // op: simm16
        return 0;
      }
      break;
    }
    case AMDGPU::S_GETPC_B64_gfx10:
    case AMDGPU::S_GETPC_B64_gfx11:
    case AMDGPU::S_GETPC_B64_gfx12:
    case AMDGPU::S_GETPC_B64_gfx1250:
    case AMDGPU::S_GETPC_B64_gfx6_gfx7:
    case AMDGPU::S_GETPC_B64_vi:
    case AMDGPU::S_GET_BARRIER_STATE_M0_gfx12:
    case AMDGPU::S_GET_SHADER_CYCLES_U64_gfx12: {
      switch (OpNum) {
      case 0:
        // op: sdst
        return 16;
      }
      break;
    }
    case AMDGPU::S_GET_WAVEID_IN_WORKGROUP_gfx10:
    case AMDGPU::S_MEMREALTIME_gfx10:
    case AMDGPU::S_MEMREALTIME_vi:
    case AMDGPU::S_MEMTIME_gfx10:
    case AMDGPU::S_MEMTIME_vi: {
      switch (OpNum) {
      case 0:
        // op: sdst
        return 6;
      }
      break;
    }
    case AMDGPU::S_BARRIER_WAIT_gfx12:
    case AMDGPU::S_BRANCH_gfx10:
    case AMDGPU::S_BRANCH_gfx11:
    case AMDGPU::S_BRANCH_gfx12:
    case AMDGPU::S_BRANCH_gfx6_gfx7:
    case AMDGPU::S_BRANCH_pad_s_nop_gfx10:
    case AMDGPU::S_BRANCH_pad_s_nop_gfx11:
    case AMDGPU::S_BRANCH_pad_s_nop_gfx12:
    case AMDGPU::S_BRANCH_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_BRANCH_pad_s_nop_vi:
    case AMDGPU::S_BRANCH_vi:
    case AMDGPU::S_CBRANCH_CDBGSYS_AND_USER_gfx10:
    case AMDGPU::S_CBRANCH_CDBGSYS_AND_USER_gfx11:
    case AMDGPU::S_CBRANCH_CDBGSYS_AND_USER_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_CDBGSYS_AND_USER_pad_s_nop_gfx10:
    case AMDGPU::S_CBRANCH_CDBGSYS_AND_USER_pad_s_nop_gfx11:
    case AMDGPU::S_CBRANCH_CDBGSYS_AND_USER_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_CDBGSYS_AND_USER_pad_s_nop_vi:
    case AMDGPU::S_CBRANCH_CDBGSYS_AND_USER_vi:
    case AMDGPU::S_CBRANCH_CDBGSYS_OR_USER_gfx10:
    case AMDGPU::S_CBRANCH_CDBGSYS_OR_USER_gfx11:
    case AMDGPU::S_CBRANCH_CDBGSYS_OR_USER_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_CDBGSYS_OR_USER_pad_s_nop_gfx10:
    case AMDGPU::S_CBRANCH_CDBGSYS_OR_USER_pad_s_nop_gfx11:
    case AMDGPU::S_CBRANCH_CDBGSYS_OR_USER_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_CDBGSYS_OR_USER_pad_s_nop_vi:
    case AMDGPU::S_CBRANCH_CDBGSYS_OR_USER_vi:
    case AMDGPU::S_CBRANCH_CDBGSYS_gfx10:
    case AMDGPU::S_CBRANCH_CDBGSYS_gfx11:
    case AMDGPU::S_CBRANCH_CDBGSYS_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_CDBGSYS_pad_s_nop_gfx10:
    case AMDGPU::S_CBRANCH_CDBGSYS_pad_s_nop_gfx11:
    case AMDGPU::S_CBRANCH_CDBGSYS_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_CDBGSYS_pad_s_nop_vi:
    case AMDGPU::S_CBRANCH_CDBGSYS_vi:
    case AMDGPU::S_CBRANCH_CDBGUSER_gfx10:
    case AMDGPU::S_CBRANCH_CDBGUSER_gfx11:
    case AMDGPU::S_CBRANCH_CDBGUSER_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_CDBGUSER_pad_s_nop_gfx10:
    case AMDGPU::S_CBRANCH_CDBGUSER_pad_s_nop_gfx11:
    case AMDGPU::S_CBRANCH_CDBGUSER_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_CDBGUSER_pad_s_nop_vi:
    case AMDGPU::S_CBRANCH_CDBGUSER_vi:
    case AMDGPU::S_CBRANCH_EXECNZ_gfx10:
    case AMDGPU::S_CBRANCH_EXECNZ_gfx11:
    case AMDGPU::S_CBRANCH_EXECNZ_gfx12:
    case AMDGPU::S_CBRANCH_EXECNZ_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_EXECNZ_pad_s_nop_gfx10:
    case AMDGPU::S_CBRANCH_EXECNZ_pad_s_nop_gfx11:
    case AMDGPU::S_CBRANCH_EXECNZ_pad_s_nop_gfx12:
    case AMDGPU::S_CBRANCH_EXECNZ_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_EXECNZ_pad_s_nop_vi:
    case AMDGPU::S_CBRANCH_EXECNZ_vi:
    case AMDGPU::S_CBRANCH_EXECZ_gfx10:
    case AMDGPU::S_CBRANCH_EXECZ_gfx11:
    case AMDGPU::S_CBRANCH_EXECZ_gfx12:
    case AMDGPU::S_CBRANCH_EXECZ_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_EXECZ_pad_s_nop_gfx10:
    case AMDGPU::S_CBRANCH_EXECZ_pad_s_nop_gfx11:
    case AMDGPU::S_CBRANCH_EXECZ_pad_s_nop_gfx12:
    case AMDGPU::S_CBRANCH_EXECZ_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_EXECZ_pad_s_nop_vi:
    case AMDGPU::S_CBRANCH_EXECZ_vi:
    case AMDGPU::S_CBRANCH_SCC0_gfx10:
    case AMDGPU::S_CBRANCH_SCC0_gfx11:
    case AMDGPU::S_CBRANCH_SCC0_gfx12:
    case AMDGPU::S_CBRANCH_SCC0_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_SCC0_pad_s_nop_gfx10:
    case AMDGPU::S_CBRANCH_SCC0_pad_s_nop_gfx11:
    case AMDGPU::S_CBRANCH_SCC0_pad_s_nop_gfx12:
    case AMDGPU::S_CBRANCH_SCC0_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_SCC0_pad_s_nop_vi:
    case AMDGPU::S_CBRANCH_SCC0_vi:
    case AMDGPU::S_CBRANCH_SCC1_gfx10:
    case AMDGPU::S_CBRANCH_SCC1_gfx11:
    case AMDGPU::S_CBRANCH_SCC1_gfx12:
    case AMDGPU::S_CBRANCH_SCC1_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_SCC1_pad_s_nop_gfx10:
    case AMDGPU::S_CBRANCH_SCC1_pad_s_nop_gfx11:
    case AMDGPU::S_CBRANCH_SCC1_pad_s_nop_gfx12:
    case AMDGPU::S_CBRANCH_SCC1_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_SCC1_pad_s_nop_vi:
    case AMDGPU::S_CBRANCH_SCC1_vi:
    case AMDGPU::S_CBRANCH_VCCNZ_gfx10:
    case AMDGPU::S_CBRANCH_VCCNZ_gfx11:
    case AMDGPU::S_CBRANCH_VCCNZ_gfx12:
    case AMDGPU::S_CBRANCH_VCCNZ_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_VCCNZ_pad_s_nop_gfx10:
    case AMDGPU::S_CBRANCH_VCCNZ_pad_s_nop_gfx11:
    case AMDGPU::S_CBRANCH_VCCNZ_pad_s_nop_gfx12:
    case AMDGPU::S_CBRANCH_VCCNZ_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_VCCNZ_pad_s_nop_vi:
    case AMDGPU::S_CBRANCH_VCCNZ_vi:
    case AMDGPU::S_CBRANCH_VCCZ_gfx10:
    case AMDGPU::S_CBRANCH_VCCZ_gfx11:
    case AMDGPU::S_CBRANCH_VCCZ_gfx12:
    case AMDGPU::S_CBRANCH_VCCZ_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_VCCZ_pad_s_nop_gfx10:
    case AMDGPU::S_CBRANCH_VCCZ_pad_s_nop_gfx11:
    case AMDGPU::S_CBRANCH_VCCZ_pad_s_nop_gfx12:
    case AMDGPU::S_CBRANCH_VCCZ_pad_s_nop_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_VCCZ_pad_s_nop_vi:
    case AMDGPU::S_CBRANCH_VCCZ_vi:
    case AMDGPU::S_CLAUSE_gfx10:
    case AMDGPU::S_CLAUSE_gfx11:
    case AMDGPU::S_CLAUSE_gfx12:
    case AMDGPU::S_DECPERFLEVEL_gfx10:
    case AMDGPU::S_DECPERFLEVEL_gfx11:
    case AMDGPU::S_DECPERFLEVEL_gfx12:
    case AMDGPU::S_DECPERFLEVEL_gfx6_gfx7:
    case AMDGPU::S_DECPERFLEVEL_vi:
    case AMDGPU::S_DELAY_ALU_gfx11:
    case AMDGPU::S_DELAY_ALU_gfx12:
    case AMDGPU::S_DENORM_MODE_gfx10:
    case AMDGPU::S_DENORM_MODE_gfx11:
    case AMDGPU::S_DENORM_MODE_gfx12:
    case AMDGPU::S_ENDPGM_gfx10:
    case AMDGPU::S_ENDPGM_gfx11:
    case AMDGPU::S_ENDPGM_gfx12:
    case AMDGPU::S_ENDPGM_gfx6_gfx7:
    case AMDGPU::S_ENDPGM_vi:
    case AMDGPU::S_INCPERFLEVEL_gfx10:
    case AMDGPU::S_INCPERFLEVEL_gfx11:
    case AMDGPU::S_INCPERFLEVEL_gfx12:
    case AMDGPU::S_INCPERFLEVEL_gfx6_gfx7:
    case AMDGPU::S_INCPERFLEVEL_vi:
    case AMDGPU::S_INST_PREFETCH_gfx10:
    case AMDGPU::S_INST_PREFETCH_gfx11:
    case AMDGPU::S_MONITOR_SLEEP_gfx12:
    case AMDGPU::S_NOP_gfx10:
    case AMDGPU::S_NOP_gfx11:
    case AMDGPU::S_NOP_gfx12:
    case AMDGPU::S_NOP_gfx6_gfx7:
    case AMDGPU::S_NOP_vi:
    case AMDGPU::S_ROUND_MODE_gfx10:
    case AMDGPU::S_ROUND_MODE_gfx11:
    case AMDGPU::S_ROUND_MODE_gfx12:
    case AMDGPU::S_SENDMSGHALT_gfx10:
    case AMDGPU::S_SENDMSGHALT_gfx11:
    case AMDGPU::S_SENDMSGHALT_gfx12:
    case AMDGPU::S_SENDMSGHALT_gfx6_gfx7:
    case AMDGPU::S_SENDMSGHALT_vi:
    case AMDGPU::S_SENDMSG_gfx10:
    case AMDGPU::S_SENDMSG_gfx11:
    case AMDGPU::S_SENDMSG_gfx12:
    case AMDGPU::S_SENDMSG_gfx6_gfx7:
    case AMDGPU::S_SENDMSG_vi:
    case AMDGPU::S_SETHALT_gfx10:
    case AMDGPU::S_SETHALT_gfx11:
    case AMDGPU::S_SETHALT_gfx12:
    case AMDGPU::S_SETHALT_gfx6_gfx7:
    case AMDGPU::S_SETHALT_vi:
    case AMDGPU::S_SETKILL_gfx10:
    case AMDGPU::S_SETKILL_gfx11:
    case AMDGPU::S_SETKILL_gfx12:
    case AMDGPU::S_SETKILL_gfx6_gfx7:
    case AMDGPU::S_SETKILL_vi:
    case AMDGPU::S_SETPRIO_INC_WG_gfx12:
    case AMDGPU::S_SETPRIO_gfx10:
    case AMDGPU::S_SETPRIO_gfx11:
    case AMDGPU::S_SETPRIO_gfx12:
    case AMDGPU::S_SETPRIO_gfx6_gfx7:
    case AMDGPU::S_SETPRIO_vi:
    case AMDGPU::S_SET_GPR_IDX_MODE_vi:
    case AMDGPU::S_SET_VGPR_MSB_gfx12:
    case AMDGPU::S_SLEEP_gfx10:
    case AMDGPU::S_SLEEP_gfx11:
    case AMDGPU::S_SLEEP_gfx12:
    case AMDGPU::S_SLEEP_gfx6_gfx7:
    case AMDGPU::S_SLEEP_vi:
    case AMDGPU::S_TRAP_gfx10:
    case AMDGPU::S_TRAP_gfx11:
    case AMDGPU::S_TRAP_gfx12:
    case AMDGPU::S_TRAP_gfx6_gfx7:
    case AMDGPU::S_TRAP_vi:
    case AMDGPU::S_TTRACEDATA_IMM_gfx10:
    case AMDGPU::S_TTRACEDATA_IMM_gfx11:
    case AMDGPU::S_TTRACEDATA_IMM_gfx12:
    case AMDGPU::S_VERSION_gfx10:
    case AMDGPU::S_VERSION_gfx11:
    case AMDGPU::S_VERSION_gfx12:
    case AMDGPU::S_WAITCNT_DEPCTR_gfx10:
    case AMDGPU::S_WAITCNT_DEPCTR_gfx11:
    case AMDGPU::S_WAITCNT_DEPCTR_gfx12:
    case AMDGPU::S_WAITCNT_gfx10:
    case AMDGPU::S_WAITCNT_gfx11:
    case AMDGPU::S_WAITCNT_gfx12:
    case AMDGPU::S_WAITCNT_gfx6_gfx7:
    case AMDGPU::S_WAITCNT_vi:
    case AMDGPU::S_WAIT_ASYNCCNT_gfx12:
    case AMDGPU::S_WAIT_BVHCNT_gfx12:
    case AMDGPU::S_WAIT_DSCNT_gfx12:
    case AMDGPU::S_WAIT_EVENT_gfx11:
    case AMDGPU::S_WAIT_EVENT_gfx12:
    case AMDGPU::S_WAIT_EXPCNT_gfx12:
    case AMDGPU::S_WAIT_KMCNT_gfx12:
    case AMDGPU::S_WAIT_LOADCNT_DSCNT_gfx12:
    case AMDGPU::S_WAIT_LOADCNT_gfx12:
    case AMDGPU::S_WAIT_SAMPLECNT_gfx12:
    case AMDGPU::S_WAIT_STORECNT_DSCNT_gfx12:
    case AMDGPU::S_WAIT_STORECNT_gfx12:
    case AMDGPU::S_WAIT_TENSORCNT_gfx12:
    case AMDGPU::S_WAIT_XCNT_gfx12: {
      switch (OpNum) {
      case 0:
        // op: simm16
        return 0;
      }
      break;
    }
    case AMDGPU::S_BITCMP0_B32_gfx10:
    case AMDGPU::S_BITCMP0_B32_gfx11:
    case AMDGPU::S_BITCMP0_B32_gfx12:
    case AMDGPU::S_BITCMP0_B32_gfx6_gfx7:
    case AMDGPU::S_BITCMP0_B32_vi:
    case AMDGPU::S_BITCMP0_B64_gfx10:
    case AMDGPU::S_BITCMP0_B64_gfx11:
    case AMDGPU::S_BITCMP0_B64_gfx12:
    case AMDGPU::S_BITCMP0_B64_gfx6_gfx7:
    case AMDGPU::S_BITCMP0_B64_vi:
    case AMDGPU::S_BITCMP1_B32_gfx10:
    case AMDGPU::S_BITCMP1_B32_gfx11:
    case AMDGPU::S_BITCMP1_B32_gfx12:
    case AMDGPU::S_BITCMP1_B32_gfx6_gfx7:
    case AMDGPU::S_BITCMP1_B32_vi:
    case AMDGPU::S_BITCMP1_B64_gfx10:
    case AMDGPU::S_BITCMP1_B64_gfx11:
    case AMDGPU::S_BITCMP1_B64_gfx12:
    case AMDGPU::S_BITCMP1_B64_gfx6_gfx7:
    case AMDGPU::S_BITCMP1_B64_vi:
    case AMDGPU::S_CBRANCH_G_FORK_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_G_FORK_vi:
    case AMDGPU::S_CMP_EQ_F16_gfx11:
    case AMDGPU::S_CMP_EQ_F16_gfx12:
    case AMDGPU::S_CMP_EQ_F32_gfx11:
    case AMDGPU::S_CMP_EQ_F32_gfx12:
    case AMDGPU::S_CMP_EQ_I32_gfx10:
    case AMDGPU::S_CMP_EQ_I32_gfx11:
    case AMDGPU::S_CMP_EQ_I32_gfx12:
    case AMDGPU::S_CMP_EQ_I32_gfx6_gfx7:
    case AMDGPU::S_CMP_EQ_I32_vi:
    case AMDGPU::S_CMP_EQ_U32_gfx10:
    case AMDGPU::S_CMP_EQ_U32_gfx11:
    case AMDGPU::S_CMP_EQ_U32_gfx12:
    case AMDGPU::S_CMP_EQ_U32_gfx6_gfx7:
    case AMDGPU::S_CMP_EQ_U32_vi:
    case AMDGPU::S_CMP_EQ_U64_gfx10:
    case AMDGPU::S_CMP_EQ_U64_gfx11:
    case AMDGPU::S_CMP_EQ_U64_gfx12:
    case AMDGPU::S_CMP_EQ_U64_vi:
    case AMDGPU::S_CMP_GE_F16_gfx11:
    case AMDGPU::S_CMP_GE_F16_gfx12:
    case AMDGPU::S_CMP_GE_F32_gfx11:
    case AMDGPU::S_CMP_GE_F32_gfx12:
    case AMDGPU::S_CMP_GE_I32_gfx10:
    case AMDGPU::S_CMP_GE_I32_gfx11:
    case AMDGPU::S_CMP_GE_I32_gfx12:
    case AMDGPU::S_CMP_GE_I32_gfx6_gfx7:
    case AMDGPU::S_CMP_GE_I32_vi:
    case AMDGPU::S_CMP_GE_U32_gfx10:
    case AMDGPU::S_CMP_GE_U32_gfx11:
    case AMDGPU::S_CMP_GE_U32_gfx12:
    case AMDGPU::S_CMP_GE_U32_gfx6_gfx7:
    case AMDGPU::S_CMP_GE_U32_vi:
    case AMDGPU::S_CMP_GT_F16_gfx11:
    case AMDGPU::S_CMP_GT_F16_gfx12:
    case AMDGPU::S_CMP_GT_F32_gfx11:
    case AMDGPU::S_CMP_GT_F32_gfx12:
    case AMDGPU::S_CMP_GT_I32_gfx10:
    case AMDGPU::S_CMP_GT_I32_gfx11:
    case AMDGPU::S_CMP_GT_I32_gfx12:
    case AMDGPU::S_CMP_GT_I32_gfx6_gfx7:
    case AMDGPU::S_CMP_GT_I32_vi:
    case AMDGPU::S_CMP_GT_U32_gfx10:
    case AMDGPU::S_CMP_GT_U32_gfx11:
    case AMDGPU::S_CMP_GT_U32_gfx12:
    case AMDGPU::S_CMP_GT_U32_gfx6_gfx7:
    case AMDGPU::S_CMP_GT_U32_vi:
    case AMDGPU::S_CMP_LE_F16_gfx11:
    case AMDGPU::S_CMP_LE_F16_gfx12:
    case AMDGPU::S_CMP_LE_F32_gfx11:
    case AMDGPU::S_CMP_LE_F32_gfx12:
    case AMDGPU::S_CMP_LE_I32_gfx10:
    case AMDGPU::S_CMP_LE_I32_gfx11:
    case AMDGPU::S_CMP_LE_I32_gfx12:
    case AMDGPU::S_CMP_LE_I32_gfx6_gfx7:
    case AMDGPU::S_CMP_LE_I32_vi:
    case AMDGPU::S_CMP_LE_U32_gfx10:
    case AMDGPU::S_CMP_LE_U32_gfx11:
    case AMDGPU::S_CMP_LE_U32_gfx12:
    case AMDGPU::S_CMP_LE_U32_gfx6_gfx7:
    case AMDGPU::S_CMP_LE_U32_vi:
    case AMDGPU::S_CMP_LG_F16_gfx11:
    case AMDGPU::S_CMP_LG_F16_gfx12:
    case AMDGPU::S_CMP_LG_F32_gfx11:
    case AMDGPU::S_CMP_LG_F32_gfx12:
    case AMDGPU::S_CMP_LG_I32_gfx10:
    case AMDGPU::S_CMP_LG_I32_gfx11:
    case AMDGPU::S_CMP_LG_I32_gfx12:
    case AMDGPU::S_CMP_LG_I32_gfx6_gfx7:
    case AMDGPU::S_CMP_LG_I32_vi:
    case AMDGPU::S_CMP_LG_U32_gfx10:
    case AMDGPU::S_CMP_LG_U32_gfx11:
    case AMDGPU::S_CMP_LG_U32_gfx12:
    case AMDGPU::S_CMP_LG_U32_gfx6_gfx7:
    case AMDGPU::S_CMP_LG_U32_vi:
    case AMDGPU::S_CMP_LG_U64_gfx10:
    case AMDGPU::S_CMP_LG_U64_gfx11:
    case AMDGPU::S_CMP_LG_U64_gfx12:
    case AMDGPU::S_CMP_LG_U64_vi:
    case AMDGPU::S_CMP_LT_F16_gfx11:
    case AMDGPU::S_CMP_LT_F16_gfx12:
    case AMDGPU::S_CMP_LT_F32_gfx11:
    case AMDGPU::S_CMP_LT_F32_gfx12:
    case AMDGPU::S_CMP_LT_I32_gfx10:
    case AMDGPU::S_CMP_LT_I32_gfx11:
    case AMDGPU::S_CMP_LT_I32_gfx12:
    case AMDGPU::S_CMP_LT_I32_gfx6_gfx7:
    case AMDGPU::S_CMP_LT_I32_vi:
    case AMDGPU::S_CMP_LT_U32_gfx10:
    case AMDGPU::S_CMP_LT_U32_gfx11:
    case AMDGPU::S_CMP_LT_U32_gfx12:
    case AMDGPU::S_CMP_LT_U32_gfx6_gfx7:
    case AMDGPU::S_CMP_LT_U32_vi:
    case AMDGPU::S_CMP_NEQ_F16_gfx11:
    case AMDGPU::S_CMP_NEQ_F16_gfx12:
    case AMDGPU::S_CMP_NEQ_F32_gfx11:
    case AMDGPU::S_CMP_NEQ_F32_gfx12:
    case AMDGPU::S_CMP_NGE_F16_gfx11:
    case AMDGPU::S_CMP_NGE_F16_gfx12:
    case AMDGPU::S_CMP_NGE_F32_gfx11:
    case AMDGPU::S_CMP_NGE_F32_gfx12:
    case AMDGPU::S_CMP_NGT_F16_gfx11:
    case AMDGPU::S_CMP_NGT_F16_gfx12:
    case AMDGPU::S_CMP_NGT_F32_gfx11:
    case AMDGPU::S_CMP_NGT_F32_gfx12:
    case AMDGPU::S_CMP_NLE_F16_gfx11:
    case AMDGPU::S_CMP_NLE_F16_gfx12:
    case AMDGPU::S_CMP_NLE_F32_gfx11:
    case AMDGPU::S_CMP_NLE_F32_gfx12:
    case AMDGPU::S_CMP_NLG_F16_gfx11:
    case AMDGPU::S_CMP_NLG_F16_gfx12:
    case AMDGPU::S_CMP_NLG_F32_gfx11:
    case AMDGPU::S_CMP_NLG_F32_gfx12:
    case AMDGPU::S_CMP_NLT_F16_gfx11:
    case AMDGPU::S_CMP_NLT_F16_gfx12:
    case AMDGPU::S_CMP_NLT_F32_gfx11:
    case AMDGPU::S_CMP_NLT_F32_gfx12:
    case AMDGPU::S_CMP_O_F16_gfx11:
    case AMDGPU::S_CMP_O_F16_gfx12:
    case AMDGPU::S_CMP_O_F32_gfx11:
    case AMDGPU::S_CMP_O_F32_gfx12:
    case AMDGPU::S_CMP_U_F16_gfx11:
    case AMDGPU::S_CMP_U_F16_gfx12:
    case AMDGPU::S_CMP_U_F32_gfx11:
    case AMDGPU::S_CMP_U_F32_gfx12:
    case AMDGPU::S_RFE_RESTORE_B64_vi:
    case AMDGPU::S_SETVSKIP_gfx6_gfx7:
    case AMDGPU::S_SETVSKIP_vi:
    case AMDGPU::S_SET_GPR_IDX_ON_vi: {
      switch (OpNum) {
      case 0:
        // op: src0
        return 0;
      case 1:
        // op: src1
        return 8;
      }
      break;
    }
    case AMDGPU::V_CMPSX_EQ_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_EQ_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_F_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_F_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_GE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_GE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_GT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_GT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LG_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LG_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NEQ_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NEQ_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NGE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NGE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NGT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NGT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLG_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLG_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_O_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_O_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_TRU_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_TRU_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_U_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPSX_U_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_EQ_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_EQ_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_F_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_F_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_GE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_GE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_GT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_GT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_LE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_LE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_LG_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_LG_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_LT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_LT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NEQ_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NEQ_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NGE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NGE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NGT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NGT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLG_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLG_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_O_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_O_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_TRU_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_TRU_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_U_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPS_U_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_CLASS_F16_e32_gfx10:
    case AMDGPU::V_CMPX_CLASS_F16_e32_vi:
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_CLASS_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_CLASS_F32_e32_gfx10:
    case AMDGPU::V_CMPX_CLASS_F32_e32_gfx11:
    case AMDGPU::V_CMPX_CLASS_F32_e32_gfx12:
    case AMDGPU::V_CMPX_CLASS_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_CLASS_F32_e32_vi:
    case AMDGPU::V_CMPX_CLASS_F64_e32_gfx10:
    case AMDGPU::V_CMPX_CLASS_F64_e32_gfx11:
    case AMDGPU::V_CMPX_CLASS_F64_e32_gfx12:
    case AMDGPU::V_CMPX_CLASS_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_CLASS_F64_e32_vi:
    case AMDGPU::V_CMPX_EQ_F16_e32_gfx10:
    case AMDGPU::V_CMPX_EQ_F16_e32_vi:
    case AMDGPU::V_CMPX_EQ_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_F32_e32_gfx10:
    case AMDGPU::V_CMPX_EQ_F32_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_F32_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_F32_e32_vi:
    case AMDGPU::V_CMPX_EQ_F64_e32_gfx10:
    case AMDGPU::V_CMPX_EQ_F64_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_F64_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_F64_e32_vi:
    case AMDGPU::V_CMPX_EQ_I16_e32_gfx10:
    case AMDGPU::V_CMPX_EQ_I16_e32_vi:
    case AMDGPU::V_CMPX_EQ_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_I16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_I32_e32_gfx10:
    case AMDGPU::V_CMPX_EQ_I32_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_I32_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_I32_e32_vi:
    case AMDGPU::V_CMPX_EQ_I64_e32_gfx10:
    case AMDGPU::V_CMPX_EQ_I64_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_I64_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_I64_e32_vi:
    case AMDGPU::V_CMPX_EQ_U16_e32_gfx10:
    case AMDGPU::V_CMPX_EQ_U16_e32_vi:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_U32_e32_gfx10:
    case AMDGPU::V_CMPX_EQ_U32_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_U32_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_U32_e32_vi:
    case AMDGPU::V_CMPX_EQ_U64_e32_gfx10:
    case AMDGPU::V_CMPX_EQ_U64_e32_gfx11:
    case AMDGPU::V_CMPX_EQ_U64_e32_gfx12:
    case AMDGPU::V_CMPX_EQ_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_U64_e32_vi:
    case AMDGPU::V_CMPX_F_F16_e32_gfx10:
    case AMDGPU::V_CMPX_F_F16_e32_vi:
    case AMDGPU::V_CMPX_F_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_F_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_F_F32_e32_gfx10:
    case AMDGPU::V_CMPX_F_F32_e32_gfx11:
    case AMDGPU::V_CMPX_F_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_F32_e32_vi:
    case AMDGPU::V_CMPX_F_F64_e32_gfx10:
    case AMDGPU::V_CMPX_F_F64_e32_gfx11:
    case AMDGPU::V_CMPX_F_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_F64_e32_vi:
    case AMDGPU::V_CMPX_F_I16_e32_vi:
    case AMDGPU::V_CMPX_F_I32_e32_gfx10:
    case AMDGPU::V_CMPX_F_I32_e32_gfx11:
    case AMDGPU::V_CMPX_F_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_I32_e32_vi:
    case AMDGPU::V_CMPX_F_I64_e32_gfx10:
    case AMDGPU::V_CMPX_F_I64_e32_gfx11:
    case AMDGPU::V_CMPX_F_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_I64_e32_vi:
    case AMDGPU::V_CMPX_F_U16_e32_vi:
    case AMDGPU::V_CMPX_F_U32_e32_gfx10:
    case AMDGPU::V_CMPX_F_U32_e32_gfx11:
    case AMDGPU::V_CMPX_F_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_U32_e32_vi:
    case AMDGPU::V_CMPX_F_U64_e32_gfx10:
    case AMDGPU::V_CMPX_F_U64_e32_gfx11:
    case AMDGPU::V_CMPX_F_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_U64_e32_vi:
    case AMDGPU::V_CMPX_GE_F16_e32_gfx10:
    case AMDGPU::V_CMPX_GE_F16_e32_vi:
    case AMDGPU::V_CMPX_GE_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_GE_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_GE_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_GE_F32_e32_gfx10:
    case AMDGPU::V_CMPX_GE_F32_e32_gfx11:
    case AMDGPU::V_CMPX_GE_F32_e32_gfx12:
    case AMDGPU::V_CMPX_GE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_F32_e32_vi:
    case AMDGPU::V_CMPX_GE_F64_e32_gfx10:
    case AMDGPU::V_CMPX_GE_F64_e32_gfx11:
    case AMDGPU::V_CMPX_GE_F64_e32_gfx12:
    case AMDGPU::V_CMPX_GE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_F64_e32_vi:
    case AMDGPU::V_CMPX_GE_I16_e32_gfx10:
    case AMDGPU::V_CMPX_GE_I16_e32_vi:
    case AMDGPU::V_CMPX_GE_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_GE_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_GE_I16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_GE_I16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_GE_I32_e32_gfx10:
    case AMDGPU::V_CMPX_GE_I32_e32_gfx11:
    case AMDGPU::V_CMPX_GE_I32_e32_gfx12:
    case AMDGPU::V_CMPX_GE_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_I32_e32_vi:
    case AMDGPU::V_CMPX_GE_I64_e32_gfx10:
    case AMDGPU::V_CMPX_GE_I64_e32_gfx11:
    case AMDGPU::V_CMPX_GE_I64_e32_gfx12:
    case AMDGPU::V_CMPX_GE_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_I64_e32_vi:
    case AMDGPU::V_CMPX_GE_U16_e32_gfx10:
    case AMDGPU::V_CMPX_GE_U16_e32_vi:
    case AMDGPU::V_CMPX_GE_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_GE_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_GE_U16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_GE_U16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_GE_U32_e32_gfx10:
    case AMDGPU::V_CMPX_GE_U32_e32_gfx11:
    case AMDGPU::V_CMPX_GE_U32_e32_gfx12:
    case AMDGPU::V_CMPX_GE_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_U32_e32_vi:
    case AMDGPU::V_CMPX_GE_U64_e32_gfx10:
    case AMDGPU::V_CMPX_GE_U64_e32_gfx11:
    case AMDGPU::V_CMPX_GE_U64_e32_gfx12:
    case AMDGPU::V_CMPX_GE_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_U64_e32_vi:
    case AMDGPU::V_CMPX_GT_F16_e32_gfx10:
    case AMDGPU::V_CMPX_GT_F16_e32_vi:
    case AMDGPU::V_CMPX_GT_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_GT_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_GT_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_GT_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_GT_F32_e32_gfx10:
    case AMDGPU::V_CMPX_GT_F32_e32_gfx11:
    case AMDGPU::V_CMPX_GT_F32_e32_gfx12:
    case AMDGPU::V_CMPX_GT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_F32_e32_vi:
    case AMDGPU::V_CMPX_GT_F64_e32_gfx10:
    case AMDGPU::V_CMPX_GT_F64_e32_gfx11:
    case AMDGPU::V_CMPX_GT_F64_e32_gfx12:
    case AMDGPU::V_CMPX_GT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_F64_e32_vi:
    case AMDGPU::V_CMPX_GT_I16_e32_gfx10:
    case AMDGPU::V_CMPX_GT_I16_e32_vi:
    case AMDGPU::V_CMPX_GT_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_GT_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_GT_I16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_GT_I16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_GT_I32_e32_gfx10:
    case AMDGPU::V_CMPX_GT_I32_e32_gfx11:
    case AMDGPU::V_CMPX_GT_I32_e32_gfx12:
    case AMDGPU::V_CMPX_GT_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_I32_e32_vi:
    case AMDGPU::V_CMPX_GT_I64_e32_gfx10:
    case AMDGPU::V_CMPX_GT_I64_e32_gfx11:
    case AMDGPU::V_CMPX_GT_I64_e32_gfx12:
    case AMDGPU::V_CMPX_GT_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_I64_e32_vi:
    case AMDGPU::V_CMPX_GT_U16_e32_gfx10:
    case AMDGPU::V_CMPX_GT_U16_e32_vi:
    case AMDGPU::V_CMPX_GT_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_GT_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_GT_U16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_GT_U16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_GT_U32_e32_gfx10:
    case AMDGPU::V_CMPX_GT_U32_e32_gfx11:
    case AMDGPU::V_CMPX_GT_U32_e32_gfx12:
    case AMDGPU::V_CMPX_GT_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_U32_e32_vi:
    case AMDGPU::V_CMPX_GT_U64_e32_gfx10:
    case AMDGPU::V_CMPX_GT_U64_e32_gfx11:
    case AMDGPU::V_CMPX_GT_U64_e32_gfx12:
    case AMDGPU::V_CMPX_GT_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_U64_e32_vi:
    case AMDGPU::V_CMPX_LE_F16_e32_gfx10:
    case AMDGPU::V_CMPX_LE_F16_e32_vi:
    case AMDGPU::V_CMPX_LE_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_LE_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_LE_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_LE_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_LE_F32_e32_gfx10:
    case AMDGPU::V_CMPX_LE_F32_e32_gfx11:
    case AMDGPU::V_CMPX_LE_F32_e32_gfx12:
    case AMDGPU::V_CMPX_LE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_F32_e32_vi:
    case AMDGPU::V_CMPX_LE_F64_e32_gfx10:
    case AMDGPU::V_CMPX_LE_F64_e32_gfx11:
    case AMDGPU::V_CMPX_LE_F64_e32_gfx12:
    case AMDGPU::V_CMPX_LE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_F64_e32_vi:
    case AMDGPU::V_CMPX_LE_I16_e32_gfx10:
    case AMDGPU::V_CMPX_LE_I16_e32_vi:
    case AMDGPU::V_CMPX_LE_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_LE_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_LE_I16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_LE_I16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_LE_I32_e32_gfx10:
    case AMDGPU::V_CMPX_LE_I32_e32_gfx11:
    case AMDGPU::V_CMPX_LE_I32_e32_gfx12:
    case AMDGPU::V_CMPX_LE_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_I32_e32_vi:
    case AMDGPU::V_CMPX_LE_I64_e32_gfx10:
    case AMDGPU::V_CMPX_LE_I64_e32_gfx11:
    case AMDGPU::V_CMPX_LE_I64_e32_gfx12:
    case AMDGPU::V_CMPX_LE_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_I64_e32_vi:
    case AMDGPU::V_CMPX_LE_U16_e32_gfx10:
    case AMDGPU::V_CMPX_LE_U16_e32_vi:
    case AMDGPU::V_CMPX_LE_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_LE_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_LE_U16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_LE_U16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_LE_U32_e32_gfx10:
    case AMDGPU::V_CMPX_LE_U32_e32_gfx11:
    case AMDGPU::V_CMPX_LE_U32_e32_gfx12:
    case AMDGPU::V_CMPX_LE_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_U32_e32_vi:
    case AMDGPU::V_CMPX_LE_U64_e32_gfx10:
    case AMDGPU::V_CMPX_LE_U64_e32_gfx11:
    case AMDGPU::V_CMPX_LE_U64_e32_gfx12:
    case AMDGPU::V_CMPX_LE_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_U64_e32_vi:
    case AMDGPU::V_CMPX_LG_F16_e32_gfx10:
    case AMDGPU::V_CMPX_LG_F16_e32_vi:
    case AMDGPU::V_CMPX_LG_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_LG_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_LG_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_LG_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_LG_F32_e32_gfx10:
    case AMDGPU::V_CMPX_LG_F32_e32_gfx11:
    case AMDGPU::V_CMPX_LG_F32_e32_gfx12:
    case AMDGPU::V_CMPX_LG_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LG_F32_e32_vi:
    case AMDGPU::V_CMPX_LG_F64_e32_gfx10:
    case AMDGPU::V_CMPX_LG_F64_e32_gfx11:
    case AMDGPU::V_CMPX_LG_F64_e32_gfx12:
    case AMDGPU::V_CMPX_LG_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LG_F64_e32_vi:
    case AMDGPU::V_CMPX_LT_F16_e32_gfx10:
    case AMDGPU::V_CMPX_LT_F16_e32_vi:
    case AMDGPU::V_CMPX_LT_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_LT_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_LT_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_LT_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_LT_F32_e32_gfx10:
    case AMDGPU::V_CMPX_LT_F32_e32_gfx11:
    case AMDGPU::V_CMPX_LT_F32_e32_gfx12:
    case AMDGPU::V_CMPX_LT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_F32_e32_vi:
    case AMDGPU::V_CMPX_LT_F64_e32_gfx10:
    case AMDGPU::V_CMPX_LT_F64_e32_gfx11:
    case AMDGPU::V_CMPX_LT_F64_e32_gfx12:
    case AMDGPU::V_CMPX_LT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_F64_e32_vi:
    case AMDGPU::V_CMPX_LT_I16_e32_gfx10:
    case AMDGPU::V_CMPX_LT_I16_e32_vi:
    case AMDGPU::V_CMPX_LT_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_LT_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_LT_I16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_LT_I16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_LT_I32_e32_gfx10:
    case AMDGPU::V_CMPX_LT_I32_e32_gfx11:
    case AMDGPU::V_CMPX_LT_I32_e32_gfx12:
    case AMDGPU::V_CMPX_LT_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_I32_e32_vi:
    case AMDGPU::V_CMPX_LT_I64_e32_gfx10:
    case AMDGPU::V_CMPX_LT_I64_e32_gfx11:
    case AMDGPU::V_CMPX_LT_I64_e32_gfx12:
    case AMDGPU::V_CMPX_LT_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_I64_e32_vi:
    case AMDGPU::V_CMPX_LT_U16_e32_gfx10:
    case AMDGPU::V_CMPX_LT_U16_e32_vi:
    case AMDGPU::V_CMPX_LT_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_LT_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_LT_U16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_LT_U16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_LT_U32_e32_gfx10:
    case AMDGPU::V_CMPX_LT_U32_e32_gfx11:
    case AMDGPU::V_CMPX_LT_U32_e32_gfx12:
    case AMDGPU::V_CMPX_LT_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_U32_e32_vi:
    case AMDGPU::V_CMPX_LT_U64_e32_gfx10:
    case AMDGPU::V_CMPX_LT_U64_e32_gfx11:
    case AMDGPU::V_CMPX_LT_U64_e32_gfx12:
    case AMDGPU::V_CMPX_LT_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_U64_e32_vi:
    case AMDGPU::V_CMPX_NEQ_F16_e32_gfx10:
    case AMDGPU::V_CMPX_NEQ_F16_e32_vi:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_NEQ_F32_e32_gfx10:
    case AMDGPU::V_CMPX_NEQ_F32_e32_gfx11:
    case AMDGPU::V_CMPX_NEQ_F32_e32_gfx12:
    case AMDGPU::V_CMPX_NEQ_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NEQ_F32_e32_vi:
    case AMDGPU::V_CMPX_NEQ_F64_e32_gfx10:
    case AMDGPU::V_CMPX_NEQ_F64_e32_gfx11:
    case AMDGPU::V_CMPX_NEQ_F64_e32_gfx12:
    case AMDGPU::V_CMPX_NEQ_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NEQ_F64_e32_vi:
    case AMDGPU::V_CMPX_NE_I16_e32_gfx10:
    case AMDGPU::V_CMPX_NE_I16_e32_vi:
    case AMDGPU::V_CMPX_NE_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_NE_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_NE_I16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_NE_I16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_NE_I32_e32_gfx10:
    case AMDGPU::V_CMPX_NE_I32_e32_gfx11:
    case AMDGPU::V_CMPX_NE_I32_e32_gfx12:
    case AMDGPU::V_CMPX_NE_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NE_I32_e32_vi:
    case AMDGPU::V_CMPX_NE_I64_e32_gfx10:
    case AMDGPU::V_CMPX_NE_I64_e32_gfx11:
    case AMDGPU::V_CMPX_NE_I64_e32_gfx12:
    case AMDGPU::V_CMPX_NE_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NE_I64_e32_vi:
    case AMDGPU::V_CMPX_NE_U16_e32_gfx10:
    case AMDGPU::V_CMPX_NE_U16_e32_vi:
    case AMDGPU::V_CMPX_NE_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_NE_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_NE_U16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_NE_U16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_NE_U32_e32_gfx10:
    case AMDGPU::V_CMPX_NE_U32_e32_gfx11:
    case AMDGPU::V_CMPX_NE_U32_e32_gfx12:
    case AMDGPU::V_CMPX_NE_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NE_U32_e32_vi:
    case AMDGPU::V_CMPX_NE_U64_e32_gfx10:
    case AMDGPU::V_CMPX_NE_U64_e32_gfx11:
    case AMDGPU::V_CMPX_NE_U64_e32_gfx12:
    case AMDGPU::V_CMPX_NE_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NE_U64_e32_vi:
    case AMDGPU::V_CMPX_NGE_F16_e32_gfx10:
    case AMDGPU::V_CMPX_NGE_F16_e32_vi:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_NGE_F32_e32_gfx10:
    case AMDGPU::V_CMPX_NGE_F32_e32_gfx11:
    case AMDGPU::V_CMPX_NGE_F32_e32_gfx12:
    case AMDGPU::V_CMPX_NGE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NGE_F32_e32_vi:
    case AMDGPU::V_CMPX_NGE_F64_e32_gfx10:
    case AMDGPU::V_CMPX_NGE_F64_e32_gfx11:
    case AMDGPU::V_CMPX_NGE_F64_e32_gfx12:
    case AMDGPU::V_CMPX_NGE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NGE_F64_e32_vi:
    case AMDGPU::V_CMPX_NGT_F16_e32_gfx10:
    case AMDGPU::V_CMPX_NGT_F16_e32_vi:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_NGT_F32_e32_gfx10:
    case AMDGPU::V_CMPX_NGT_F32_e32_gfx11:
    case AMDGPU::V_CMPX_NGT_F32_e32_gfx12:
    case AMDGPU::V_CMPX_NGT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NGT_F32_e32_vi:
    case AMDGPU::V_CMPX_NGT_F64_e32_gfx10:
    case AMDGPU::V_CMPX_NGT_F64_e32_gfx11:
    case AMDGPU::V_CMPX_NGT_F64_e32_gfx12:
    case AMDGPU::V_CMPX_NGT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NGT_F64_e32_vi:
    case AMDGPU::V_CMPX_NLE_F16_e32_gfx10:
    case AMDGPU::V_CMPX_NLE_F16_e32_vi:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_NLE_F32_e32_gfx10:
    case AMDGPU::V_CMPX_NLE_F32_e32_gfx11:
    case AMDGPU::V_CMPX_NLE_F32_e32_gfx12:
    case AMDGPU::V_CMPX_NLE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLE_F32_e32_vi:
    case AMDGPU::V_CMPX_NLE_F64_e32_gfx10:
    case AMDGPU::V_CMPX_NLE_F64_e32_gfx11:
    case AMDGPU::V_CMPX_NLE_F64_e32_gfx12:
    case AMDGPU::V_CMPX_NLE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLE_F64_e32_vi:
    case AMDGPU::V_CMPX_NLG_F16_e32_gfx10:
    case AMDGPU::V_CMPX_NLG_F16_e32_vi:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_NLG_F32_e32_gfx10:
    case AMDGPU::V_CMPX_NLG_F32_e32_gfx11:
    case AMDGPU::V_CMPX_NLG_F32_e32_gfx12:
    case AMDGPU::V_CMPX_NLG_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLG_F32_e32_vi:
    case AMDGPU::V_CMPX_NLG_F64_e32_gfx10:
    case AMDGPU::V_CMPX_NLG_F64_e32_gfx11:
    case AMDGPU::V_CMPX_NLG_F64_e32_gfx12:
    case AMDGPU::V_CMPX_NLG_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLG_F64_e32_vi:
    case AMDGPU::V_CMPX_NLT_F16_e32_gfx10:
    case AMDGPU::V_CMPX_NLT_F16_e32_vi:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_NLT_F32_e32_gfx10:
    case AMDGPU::V_CMPX_NLT_F32_e32_gfx11:
    case AMDGPU::V_CMPX_NLT_F32_e32_gfx12:
    case AMDGPU::V_CMPX_NLT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLT_F32_e32_vi:
    case AMDGPU::V_CMPX_NLT_F64_e32_gfx10:
    case AMDGPU::V_CMPX_NLT_F64_e32_gfx11:
    case AMDGPU::V_CMPX_NLT_F64_e32_gfx12:
    case AMDGPU::V_CMPX_NLT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLT_F64_e32_vi:
    case AMDGPU::V_CMPX_O_F16_e32_gfx10:
    case AMDGPU::V_CMPX_O_F16_e32_vi:
    case AMDGPU::V_CMPX_O_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_O_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_O_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_O_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_O_F32_e32_gfx10:
    case AMDGPU::V_CMPX_O_F32_e32_gfx11:
    case AMDGPU::V_CMPX_O_F32_e32_gfx12:
    case AMDGPU::V_CMPX_O_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_O_F32_e32_vi:
    case AMDGPU::V_CMPX_O_F64_e32_gfx10:
    case AMDGPU::V_CMPX_O_F64_e32_gfx11:
    case AMDGPU::V_CMPX_O_F64_e32_gfx12:
    case AMDGPU::V_CMPX_O_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_O_F64_e32_vi:
    case AMDGPU::V_CMPX_TRU_F16_e32_gfx10:
    case AMDGPU::V_CMPX_TRU_F16_e32_vi:
    case AMDGPU::V_CMPX_TRU_F32_e32_gfx10:
    case AMDGPU::V_CMPX_TRU_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_TRU_F32_e32_vi:
    case AMDGPU::V_CMPX_TRU_F64_e32_gfx10:
    case AMDGPU::V_CMPX_TRU_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_TRU_F64_e32_vi:
    case AMDGPU::V_CMPX_T_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_T_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_T_F32_e32_gfx11:
    case AMDGPU::V_CMPX_T_F64_e32_gfx11:
    case AMDGPU::V_CMPX_T_I16_e32_vi:
    case AMDGPU::V_CMPX_T_I32_e32_gfx10:
    case AMDGPU::V_CMPX_T_I32_e32_gfx11:
    case AMDGPU::V_CMPX_T_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_T_I32_e32_vi:
    case AMDGPU::V_CMPX_T_I64_e32_gfx10:
    case AMDGPU::V_CMPX_T_I64_e32_gfx11:
    case AMDGPU::V_CMPX_T_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_T_I64_e32_vi:
    case AMDGPU::V_CMPX_T_U16_e32_vi:
    case AMDGPU::V_CMPX_T_U32_e32_gfx10:
    case AMDGPU::V_CMPX_T_U32_e32_gfx11:
    case AMDGPU::V_CMPX_T_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_T_U32_e32_vi:
    case AMDGPU::V_CMPX_T_U64_e32_gfx10:
    case AMDGPU::V_CMPX_T_U64_e32_gfx11:
    case AMDGPU::V_CMPX_T_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_T_U64_e32_vi:
    case AMDGPU::V_CMPX_U_F16_e32_gfx10:
    case AMDGPU::V_CMPX_U_F16_e32_vi:
    case AMDGPU::V_CMPX_U_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMPX_U_F16_t16_e32_gfx11:
    case AMDGPU::V_CMPX_U_F16_t16_e32_gfx12:
    case AMDGPU::V_CMPX_U_F32_e32_gfx10:
    case AMDGPU::V_CMPX_U_F32_e32_gfx11:
    case AMDGPU::V_CMPX_U_F32_e32_gfx12:
    case AMDGPU::V_CMPX_U_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_U_F32_e32_vi:
    case AMDGPU::V_CMPX_U_F64_e32_gfx10:
    case AMDGPU::V_CMPX_U_F64_e32_gfx11:
    case AMDGPU::V_CMPX_U_F64_e32_gfx12:
    case AMDGPU::V_CMPX_U_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMPX_U_F64_e32_vi:
    case AMDGPU::V_CMP_CLASS_F16_e32_gfx10:
    case AMDGPU::V_CMP_CLASS_F16_e32_vi:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_CLASS_F32_e32_gfx10:
    case AMDGPU::V_CMP_CLASS_F32_e32_gfx11:
    case AMDGPU::V_CMP_CLASS_F32_e32_gfx12:
    case AMDGPU::V_CMP_CLASS_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_CLASS_F32_e32_vi:
    case AMDGPU::V_CMP_CLASS_F64_e32_gfx10:
    case AMDGPU::V_CMP_CLASS_F64_e32_gfx11:
    case AMDGPU::V_CMP_CLASS_F64_e32_gfx12:
    case AMDGPU::V_CMP_CLASS_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_CLASS_F64_e32_vi:
    case AMDGPU::V_CMP_EQ_F16_e32_gfx10:
    case AMDGPU::V_CMP_EQ_F16_e32_vi:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e32_gfx10:
    case AMDGPU::V_CMP_EQ_F32_e32_gfx11:
    case AMDGPU::V_CMP_EQ_F32_e32_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_F32_e32_vi:
    case AMDGPU::V_CMP_EQ_F64_e32_gfx10:
    case AMDGPU::V_CMP_EQ_F64_e32_gfx11:
    case AMDGPU::V_CMP_EQ_F64_e32_gfx12:
    case AMDGPU::V_CMP_EQ_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_F64_e32_vi:
    case AMDGPU::V_CMP_EQ_I16_e32_gfx10:
    case AMDGPU::V_CMP_EQ_I16_e32_vi:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_gfx11:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e32_gfx10:
    case AMDGPU::V_CMP_EQ_I32_e32_gfx11:
    case AMDGPU::V_CMP_EQ_I32_e32_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_I32_e32_vi:
    case AMDGPU::V_CMP_EQ_I64_e32_gfx10:
    case AMDGPU::V_CMP_EQ_I64_e32_gfx11:
    case AMDGPU::V_CMP_EQ_I64_e32_gfx12:
    case AMDGPU::V_CMP_EQ_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_I64_e32_vi:
    case AMDGPU::V_CMP_EQ_U16_e32_gfx10:
    case AMDGPU::V_CMP_EQ_U16_e32_vi:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_gfx11:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e32_gfx10:
    case AMDGPU::V_CMP_EQ_U32_e32_gfx11:
    case AMDGPU::V_CMP_EQ_U32_e32_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_U32_e32_vi:
    case AMDGPU::V_CMP_EQ_U64_e32_gfx10:
    case AMDGPU::V_CMP_EQ_U64_e32_gfx11:
    case AMDGPU::V_CMP_EQ_U64_e32_gfx12:
    case AMDGPU::V_CMP_EQ_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_U64_e32_vi:
    case AMDGPU::V_CMP_F_F16_e32_gfx10:
    case AMDGPU::V_CMP_F_F16_e32_vi:
    case AMDGPU::V_CMP_F_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_F_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_F_F32_e32_gfx10:
    case AMDGPU::V_CMP_F_F32_e32_gfx11:
    case AMDGPU::V_CMP_F_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_F_F32_e32_vi:
    case AMDGPU::V_CMP_F_F64_e32_gfx10:
    case AMDGPU::V_CMP_F_F64_e32_gfx11:
    case AMDGPU::V_CMP_F_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_F_F64_e32_vi:
    case AMDGPU::V_CMP_F_I16_e32_vi:
    case AMDGPU::V_CMP_F_I32_e32_gfx10:
    case AMDGPU::V_CMP_F_I32_e32_gfx11:
    case AMDGPU::V_CMP_F_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_F_I32_e32_vi:
    case AMDGPU::V_CMP_F_I64_e32_gfx10:
    case AMDGPU::V_CMP_F_I64_e32_gfx11:
    case AMDGPU::V_CMP_F_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_F_I64_e32_vi:
    case AMDGPU::V_CMP_F_U16_e32_vi:
    case AMDGPU::V_CMP_F_U32_e32_gfx10:
    case AMDGPU::V_CMP_F_U32_e32_gfx11:
    case AMDGPU::V_CMP_F_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_F_U32_e32_vi:
    case AMDGPU::V_CMP_F_U64_e32_gfx10:
    case AMDGPU::V_CMP_F_U64_e32_gfx11:
    case AMDGPU::V_CMP_F_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_F_U64_e32_vi:
    case AMDGPU::V_CMP_GE_F16_e32_gfx10:
    case AMDGPU::V_CMP_GE_F16_e32_vi:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_GE_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_GE_F32_e32_gfx10:
    case AMDGPU::V_CMP_GE_F32_e32_gfx11:
    case AMDGPU::V_CMP_GE_F32_e32_gfx12:
    case AMDGPU::V_CMP_GE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_F32_e32_vi:
    case AMDGPU::V_CMP_GE_F64_e32_gfx10:
    case AMDGPU::V_CMP_GE_F64_e32_gfx11:
    case AMDGPU::V_CMP_GE_F64_e32_gfx12:
    case AMDGPU::V_CMP_GE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_F64_e32_vi:
    case AMDGPU::V_CMP_GE_I16_e32_gfx10:
    case AMDGPU::V_CMP_GE_I16_e32_vi:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_GE_I16_t16_e32_gfx11:
    case AMDGPU::V_CMP_GE_I16_t16_e32_gfx12:
    case AMDGPU::V_CMP_GE_I32_e32_gfx10:
    case AMDGPU::V_CMP_GE_I32_e32_gfx11:
    case AMDGPU::V_CMP_GE_I32_e32_gfx12:
    case AMDGPU::V_CMP_GE_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_I32_e32_vi:
    case AMDGPU::V_CMP_GE_I64_e32_gfx10:
    case AMDGPU::V_CMP_GE_I64_e32_gfx11:
    case AMDGPU::V_CMP_GE_I64_e32_gfx12:
    case AMDGPU::V_CMP_GE_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_I64_e32_vi:
    case AMDGPU::V_CMP_GE_U16_e32_gfx10:
    case AMDGPU::V_CMP_GE_U16_e32_vi:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_GE_U16_t16_e32_gfx11:
    case AMDGPU::V_CMP_GE_U16_t16_e32_gfx12:
    case AMDGPU::V_CMP_GE_U32_e32_gfx10:
    case AMDGPU::V_CMP_GE_U32_e32_gfx11:
    case AMDGPU::V_CMP_GE_U32_e32_gfx12:
    case AMDGPU::V_CMP_GE_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_U32_e32_vi:
    case AMDGPU::V_CMP_GE_U64_e32_gfx10:
    case AMDGPU::V_CMP_GE_U64_e32_gfx11:
    case AMDGPU::V_CMP_GE_U64_e32_gfx12:
    case AMDGPU::V_CMP_GE_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_U64_e32_vi:
    case AMDGPU::V_CMP_GT_F16_e32_gfx10:
    case AMDGPU::V_CMP_GT_F16_e32_vi:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_GT_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_GT_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_GT_F32_e32_gfx10:
    case AMDGPU::V_CMP_GT_F32_e32_gfx11:
    case AMDGPU::V_CMP_GT_F32_e32_gfx12:
    case AMDGPU::V_CMP_GT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_F32_e32_vi:
    case AMDGPU::V_CMP_GT_F64_e32_gfx10:
    case AMDGPU::V_CMP_GT_F64_e32_gfx11:
    case AMDGPU::V_CMP_GT_F64_e32_gfx12:
    case AMDGPU::V_CMP_GT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_F64_e32_vi:
    case AMDGPU::V_CMP_GT_I16_e32_gfx10:
    case AMDGPU::V_CMP_GT_I16_e32_vi:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_GT_I16_t16_e32_gfx11:
    case AMDGPU::V_CMP_GT_I16_t16_e32_gfx12:
    case AMDGPU::V_CMP_GT_I32_e32_gfx10:
    case AMDGPU::V_CMP_GT_I32_e32_gfx11:
    case AMDGPU::V_CMP_GT_I32_e32_gfx12:
    case AMDGPU::V_CMP_GT_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_I32_e32_vi:
    case AMDGPU::V_CMP_GT_I64_e32_gfx10:
    case AMDGPU::V_CMP_GT_I64_e32_gfx11:
    case AMDGPU::V_CMP_GT_I64_e32_gfx12:
    case AMDGPU::V_CMP_GT_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_I64_e32_vi:
    case AMDGPU::V_CMP_GT_U16_e32_gfx10:
    case AMDGPU::V_CMP_GT_U16_e32_vi:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_GT_U16_t16_e32_gfx11:
    case AMDGPU::V_CMP_GT_U16_t16_e32_gfx12:
    case AMDGPU::V_CMP_GT_U32_e32_gfx10:
    case AMDGPU::V_CMP_GT_U32_e32_gfx11:
    case AMDGPU::V_CMP_GT_U32_e32_gfx12:
    case AMDGPU::V_CMP_GT_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_U32_e32_vi:
    case AMDGPU::V_CMP_GT_U64_e32_gfx10:
    case AMDGPU::V_CMP_GT_U64_e32_gfx11:
    case AMDGPU::V_CMP_GT_U64_e32_gfx12:
    case AMDGPU::V_CMP_GT_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_U64_e32_vi:
    case AMDGPU::V_CMP_LE_F16_e32_gfx10:
    case AMDGPU::V_CMP_LE_F16_e32_vi:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_LE_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_LE_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_LE_F32_e32_gfx10:
    case AMDGPU::V_CMP_LE_F32_e32_gfx11:
    case AMDGPU::V_CMP_LE_F32_e32_gfx12:
    case AMDGPU::V_CMP_LE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_F32_e32_vi:
    case AMDGPU::V_CMP_LE_F64_e32_gfx10:
    case AMDGPU::V_CMP_LE_F64_e32_gfx11:
    case AMDGPU::V_CMP_LE_F64_e32_gfx12:
    case AMDGPU::V_CMP_LE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_F64_e32_vi:
    case AMDGPU::V_CMP_LE_I16_e32_gfx10:
    case AMDGPU::V_CMP_LE_I16_e32_vi:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_LE_I16_t16_e32_gfx11:
    case AMDGPU::V_CMP_LE_I16_t16_e32_gfx12:
    case AMDGPU::V_CMP_LE_I32_e32_gfx10:
    case AMDGPU::V_CMP_LE_I32_e32_gfx11:
    case AMDGPU::V_CMP_LE_I32_e32_gfx12:
    case AMDGPU::V_CMP_LE_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_I32_e32_vi:
    case AMDGPU::V_CMP_LE_I64_e32_gfx10:
    case AMDGPU::V_CMP_LE_I64_e32_gfx11:
    case AMDGPU::V_CMP_LE_I64_e32_gfx12:
    case AMDGPU::V_CMP_LE_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_I64_e32_vi:
    case AMDGPU::V_CMP_LE_U16_e32_gfx10:
    case AMDGPU::V_CMP_LE_U16_e32_vi:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_LE_U16_t16_e32_gfx11:
    case AMDGPU::V_CMP_LE_U16_t16_e32_gfx12:
    case AMDGPU::V_CMP_LE_U32_e32_gfx10:
    case AMDGPU::V_CMP_LE_U32_e32_gfx11:
    case AMDGPU::V_CMP_LE_U32_e32_gfx12:
    case AMDGPU::V_CMP_LE_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_U32_e32_vi:
    case AMDGPU::V_CMP_LE_U64_e32_gfx10:
    case AMDGPU::V_CMP_LE_U64_e32_gfx11:
    case AMDGPU::V_CMP_LE_U64_e32_gfx12:
    case AMDGPU::V_CMP_LE_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_U64_e32_vi:
    case AMDGPU::V_CMP_LG_F16_e32_gfx10:
    case AMDGPU::V_CMP_LG_F16_e32_vi:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_LG_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_LG_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_LG_F32_e32_gfx10:
    case AMDGPU::V_CMP_LG_F32_e32_gfx11:
    case AMDGPU::V_CMP_LG_F32_e32_gfx12:
    case AMDGPU::V_CMP_LG_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LG_F32_e32_vi:
    case AMDGPU::V_CMP_LG_F64_e32_gfx10:
    case AMDGPU::V_CMP_LG_F64_e32_gfx11:
    case AMDGPU::V_CMP_LG_F64_e32_gfx12:
    case AMDGPU::V_CMP_LG_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LG_F64_e32_vi:
    case AMDGPU::V_CMP_LT_F16_e32_gfx10:
    case AMDGPU::V_CMP_LT_F16_e32_vi:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_LT_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_LT_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_LT_F32_e32_gfx10:
    case AMDGPU::V_CMP_LT_F32_e32_gfx11:
    case AMDGPU::V_CMP_LT_F32_e32_gfx12:
    case AMDGPU::V_CMP_LT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_F32_e32_vi:
    case AMDGPU::V_CMP_LT_F64_e32_gfx10:
    case AMDGPU::V_CMP_LT_F64_e32_gfx11:
    case AMDGPU::V_CMP_LT_F64_e32_gfx12:
    case AMDGPU::V_CMP_LT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_F64_e32_vi:
    case AMDGPU::V_CMP_LT_I16_e32_gfx10:
    case AMDGPU::V_CMP_LT_I16_e32_vi:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_LT_I16_t16_e32_gfx11:
    case AMDGPU::V_CMP_LT_I16_t16_e32_gfx12:
    case AMDGPU::V_CMP_LT_I32_e32_gfx10:
    case AMDGPU::V_CMP_LT_I32_e32_gfx11:
    case AMDGPU::V_CMP_LT_I32_e32_gfx12:
    case AMDGPU::V_CMP_LT_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_I32_e32_vi:
    case AMDGPU::V_CMP_LT_I64_e32_gfx10:
    case AMDGPU::V_CMP_LT_I64_e32_gfx11:
    case AMDGPU::V_CMP_LT_I64_e32_gfx12:
    case AMDGPU::V_CMP_LT_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_I64_e32_vi:
    case AMDGPU::V_CMP_LT_U16_e32_gfx10:
    case AMDGPU::V_CMP_LT_U16_e32_vi:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_LT_U16_t16_e32_gfx11:
    case AMDGPU::V_CMP_LT_U16_t16_e32_gfx12:
    case AMDGPU::V_CMP_LT_U32_e32_gfx10:
    case AMDGPU::V_CMP_LT_U32_e32_gfx11:
    case AMDGPU::V_CMP_LT_U32_e32_gfx12:
    case AMDGPU::V_CMP_LT_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_U32_e32_vi:
    case AMDGPU::V_CMP_LT_U64_e32_gfx10:
    case AMDGPU::V_CMP_LT_U64_e32_gfx11:
    case AMDGPU::V_CMP_LT_U64_e32_gfx12:
    case AMDGPU::V_CMP_LT_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_U64_e32_vi:
    case AMDGPU::V_CMP_NEQ_F16_e32_gfx10:
    case AMDGPU::V_CMP_NEQ_F16_e32_vi:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e32_gfx10:
    case AMDGPU::V_CMP_NEQ_F32_e32_gfx11:
    case AMDGPU::V_CMP_NEQ_F32_e32_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NEQ_F32_e32_vi:
    case AMDGPU::V_CMP_NEQ_F64_e32_gfx10:
    case AMDGPU::V_CMP_NEQ_F64_e32_gfx11:
    case AMDGPU::V_CMP_NEQ_F64_e32_gfx12:
    case AMDGPU::V_CMP_NEQ_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NEQ_F64_e32_vi:
    case AMDGPU::V_CMP_NE_I16_e32_gfx10:
    case AMDGPU::V_CMP_NE_I16_e32_vi:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_NE_I16_t16_e32_gfx11:
    case AMDGPU::V_CMP_NE_I16_t16_e32_gfx12:
    case AMDGPU::V_CMP_NE_I32_e32_gfx10:
    case AMDGPU::V_CMP_NE_I32_e32_gfx11:
    case AMDGPU::V_CMP_NE_I32_e32_gfx12:
    case AMDGPU::V_CMP_NE_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NE_I32_e32_vi:
    case AMDGPU::V_CMP_NE_I64_e32_gfx10:
    case AMDGPU::V_CMP_NE_I64_e32_gfx11:
    case AMDGPU::V_CMP_NE_I64_e32_gfx12:
    case AMDGPU::V_CMP_NE_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NE_I64_e32_vi:
    case AMDGPU::V_CMP_NE_U16_e32_gfx10:
    case AMDGPU::V_CMP_NE_U16_e32_vi:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_NE_U16_t16_e32_gfx11:
    case AMDGPU::V_CMP_NE_U16_t16_e32_gfx12:
    case AMDGPU::V_CMP_NE_U32_e32_gfx10:
    case AMDGPU::V_CMP_NE_U32_e32_gfx11:
    case AMDGPU::V_CMP_NE_U32_e32_gfx12:
    case AMDGPU::V_CMP_NE_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NE_U32_e32_vi:
    case AMDGPU::V_CMP_NE_U64_e32_gfx10:
    case AMDGPU::V_CMP_NE_U64_e32_gfx11:
    case AMDGPU::V_CMP_NE_U64_e32_gfx12:
    case AMDGPU::V_CMP_NE_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NE_U64_e32_vi:
    case AMDGPU::V_CMP_NGE_F16_e32_gfx10:
    case AMDGPU::V_CMP_NGE_F16_e32_vi:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e32_gfx10:
    case AMDGPU::V_CMP_NGE_F32_e32_gfx11:
    case AMDGPU::V_CMP_NGE_F32_e32_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NGE_F32_e32_vi:
    case AMDGPU::V_CMP_NGE_F64_e32_gfx10:
    case AMDGPU::V_CMP_NGE_F64_e32_gfx11:
    case AMDGPU::V_CMP_NGE_F64_e32_gfx12:
    case AMDGPU::V_CMP_NGE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NGE_F64_e32_vi:
    case AMDGPU::V_CMP_NGT_F16_e32_gfx10:
    case AMDGPU::V_CMP_NGT_F16_e32_vi:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e32_gfx10:
    case AMDGPU::V_CMP_NGT_F32_e32_gfx11:
    case AMDGPU::V_CMP_NGT_F32_e32_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NGT_F32_e32_vi:
    case AMDGPU::V_CMP_NGT_F64_e32_gfx10:
    case AMDGPU::V_CMP_NGT_F64_e32_gfx11:
    case AMDGPU::V_CMP_NGT_F64_e32_gfx12:
    case AMDGPU::V_CMP_NGT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NGT_F64_e32_vi:
    case AMDGPU::V_CMP_NLE_F16_e32_gfx10:
    case AMDGPU::V_CMP_NLE_F16_e32_vi:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e32_gfx10:
    case AMDGPU::V_CMP_NLE_F32_e32_gfx11:
    case AMDGPU::V_CMP_NLE_F32_e32_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NLE_F32_e32_vi:
    case AMDGPU::V_CMP_NLE_F64_e32_gfx10:
    case AMDGPU::V_CMP_NLE_F64_e32_gfx11:
    case AMDGPU::V_CMP_NLE_F64_e32_gfx12:
    case AMDGPU::V_CMP_NLE_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NLE_F64_e32_vi:
    case AMDGPU::V_CMP_NLG_F16_e32_gfx10:
    case AMDGPU::V_CMP_NLG_F16_e32_vi:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e32_gfx10:
    case AMDGPU::V_CMP_NLG_F32_e32_gfx11:
    case AMDGPU::V_CMP_NLG_F32_e32_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NLG_F32_e32_vi:
    case AMDGPU::V_CMP_NLG_F64_e32_gfx10:
    case AMDGPU::V_CMP_NLG_F64_e32_gfx11:
    case AMDGPU::V_CMP_NLG_F64_e32_gfx12:
    case AMDGPU::V_CMP_NLG_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NLG_F64_e32_vi:
    case AMDGPU::V_CMP_NLT_F16_e32_gfx10:
    case AMDGPU::V_CMP_NLT_F16_e32_vi:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e32_gfx10:
    case AMDGPU::V_CMP_NLT_F32_e32_gfx11:
    case AMDGPU::V_CMP_NLT_F32_e32_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NLT_F32_e32_vi:
    case AMDGPU::V_CMP_NLT_F64_e32_gfx10:
    case AMDGPU::V_CMP_NLT_F64_e32_gfx11:
    case AMDGPU::V_CMP_NLT_F64_e32_gfx12:
    case AMDGPU::V_CMP_NLT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_NLT_F64_e32_vi:
    case AMDGPU::V_CMP_O_F16_e32_gfx10:
    case AMDGPU::V_CMP_O_F16_e32_vi:
    case AMDGPU::V_CMP_O_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_O_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_O_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_O_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_O_F32_e32_gfx10:
    case AMDGPU::V_CMP_O_F32_e32_gfx11:
    case AMDGPU::V_CMP_O_F32_e32_gfx12:
    case AMDGPU::V_CMP_O_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_O_F32_e32_vi:
    case AMDGPU::V_CMP_O_F64_e32_gfx10:
    case AMDGPU::V_CMP_O_F64_e32_gfx11:
    case AMDGPU::V_CMP_O_F64_e32_gfx12:
    case AMDGPU::V_CMP_O_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_O_F64_e32_vi:
    case AMDGPU::V_CMP_TRU_F16_e32_gfx10:
    case AMDGPU::V_CMP_TRU_F16_e32_vi:
    case AMDGPU::V_CMP_TRU_F32_e32_gfx10:
    case AMDGPU::V_CMP_TRU_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_TRU_F32_e32_vi:
    case AMDGPU::V_CMP_TRU_F64_e32_gfx10:
    case AMDGPU::V_CMP_TRU_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_TRU_F64_e32_vi:
    case AMDGPU::V_CMP_T_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_T_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_T_F32_e32_gfx11:
    case AMDGPU::V_CMP_T_F64_e32_gfx11:
    case AMDGPU::V_CMP_T_I16_e32_vi:
    case AMDGPU::V_CMP_T_I32_e32_gfx10:
    case AMDGPU::V_CMP_T_I32_e32_gfx11:
    case AMDGPU::V_CMP_T_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_T_I32_e32_vi:
    case AMDGPU::V_CMP_T_I64_e32_gfx10:
    case AMDGPU::V_CMP_T_I64_e32_gfx11:
    case AMDGPU::V_CMP_T_I64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_T_I64_e32_vi:
    case AMDGPU::V_CMP_T_U16_e32_vi:
    case AMDGPU::V_CMP_T_U32_e32_gfx10:
    case AMDGPU::V_CMP_T_U32_e32_gfx11:
    case AMDGPU::V_CMP_T_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_T_U32_e32_vi:
    case AMDGPU::V_CMP_T_U64_e32_gfx10:
    case AMDGPU::V_CMP_T_U64_e32_gfx11:
    case AMDGPU::V_CMP_T_U64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_T_U64_e32_vi:
    case AMDGPU::V_CMP_U_F16_e32_gfx10:
    case AMDGPU::V_CMP_U_F16_e32_vi:
    case AMDGPU::V_CMP_U_F16_fake16_e32_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e32_gfx12:
    case AMDGPU::V_CMP_U_F16_t16_e32_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e32_gfx12:
    case AMDGPU::V_CMP_U_F32_e32_gfx10:
    case AMDGPU::V_CMP_U_F32_e32_gfx11:
    case AMDGPU::V_CMP_U_F32_e32_gfx12:
    case AMDGPU::V_CMP_U_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_U_F32_e32_vi:
    case AMDGPU::V_CMP_U_F64_e32_gfx10:
    case AMDGPU::V_CMP_U_F64_e32_gfx11:
    case AMDGPU::V_CMP_U_F64_e32_gfx12:
    case AMDGPU::V_CMP_U_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CMP_U_F64_e32_vi: {
      switch (OpNum) {
      case 0:
        // op: src0
        return 0;
      case 1:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::S_ADD_PC_I64_gfx12:
    case AMDGPU::S_ALLOC_VGPR_gfx12:
    case AMDGPU::S_BARRIER_INIT_IMM_gfx12:
    case AMDGPU::S_BARRIER_JOIN_IMM_gfx12:
    case AMDGPU::S_BARRIER_SIGNAL_IMM_gfx12:
    case AMDGPU::S_BARRIER_SIGNAL_ISFIRST_IMM_gfx12:
    case AMDGPU::S_CBRANCH_JOIN_gfx6_gfx7:
    case AMDGPU::S_CBRANCH_JOIN_vi:
    case AMDGPU::S_RFE_B64_gfx10:
    case AMDGPU::S_RFE_B64_gfx11:
    case AMDGPU::S_RFE_B64_gfx12:
    case AMDGPU::S_RFE_B64_gfx1250:
    case AMDGPU::S_RFE_B64_gfx6_gfx7:
    case AMDGPU::S_RFE_B64_vi:
    case AMDGPU::S_SETPC_B64_gfx10:
    case AMDGPU::S_SETPC_B64_gfx11:
    case AMDGPU::S_SETPC_B64_gfx12:
    case AMDGPU::S_SETPC_B64_gfx1250:
    case AMDGPU::S_SETPC_B64_gfx6_gfx7:
    case AMDGPU::S_SETPC_B64_vi:
    case AMDGPU::S_SET_GPR_IDX_IDX_vi:
    case AMDGPU::S_SLEEP_VAR_gfx12:
    case AMDGPU::S_WAKEUP_BARRIER_IMM_gfx12: {
      switch (OpNum) {
      case 0:
        // op: src0
        return 0;
      }
      break;
    }
    case AMDGPU::V_WMMA_LD_SCALE16_PAIRED_B64_gfx1250:
    case AMDGPU::V_WMMA_LD_SCALE_PAIRED_B32_gfx1250: {
      switch (OpNum) {
      case 0:
        // op: src0
        return 32;
      case 1:
        // op: src1
        return 41;
      case 2:
        // op: matrix_a_scale
        return 11;
      case 3:
        // op: matrix_b_scale
        return 59;
      case 4:
        // op: matrix_a_scale_fmt
        return 61;
      case 5:
        // op: matrix_b_scale_fmt
        return 8;
      case 6:
        // op: matrix_a_reuse
        return 13;
      case 7:
        // op: matrix_b_reuse
        return 14;
      }
      break;
    }
    case AMDGPU::V_CMPX_EQ_I16_e64_gfx10:
    case AMDGPU::V_CMPX_EQ_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_EQ_I32_e64_gfx10:
    case AMDGPU::V_CMPX_EQ_I32_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_I32_e64_gfx12:
    case AMDGPU::V_CMPX_EQ_I64_e64_gfx10:
    case AMDGPU::V_CMPX_EQ_I64_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_I64_e64_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_e64_gfx10:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_EQ_U32_e64_gfx10:
    case AMDGPU::V_CMPX_EQ_U32_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_U32_e64_gfx12:
    case AMDGPU::V_CMPX_EQ_U64_e64_gfx10:
    case AMDGPU::V_CMPX_EQ_U64_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_U64_e64_gfx12:
    case AMDGPU::V_CMPX_F_I32_e64_gfx10:
    case AMDGPU::V_CMPX_F_I32_e64_gfx11:
    case AMDGPU::V_CMPX_F_I64_e64_gfx10:
    case AMDGPU::V_CMPX_F_I64_e64_gfx11:
    case AMDGPU::V_CMPX_F_U32_e64_gfx10:
    case AMDGPU::V_CMPX_F_U32_e64_gfx11:
    case AMDGPU::V_CMPX_F_U64_e64_gfx10:
    case AMDGPU::V_CMPX_F_U64_e64_gfx11:
    case AMDGPU::V_CMPX_GE_I16_e64_gfx10:
    case AMDGPU::V_CMPX_GE_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_GE_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_GE_I32_e64_gfx10:
    case AMDGPU::V_CMPX_GE_I32_e64_gfx11:
    case AMDGPU::V_CMPX_GE_I32_e64_gfx12:
    case AMDGPU::V_CMPX_GE_I64_e64_gfx10:
    case AMDGPU::V_CMPX_GE_I64_e64_gfx11:
    case AMDGPU::V_CMPX_GE_I64_e64_gfx12:
    case AMDGPU::V_CMPX_GE_U16_e64_gfx10:
    case AMDGPU::V_CMPX_GE_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_GE_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_GE_U32_e64_gfx10:
    case AMDGPU::V_CMPX_GE_U32_e64_gfx11:
    case AMDGPU::V_CMPX_GE_U32_e64_gfx12:
    case AMDGPU::V_CMPX_GE_U64_e64_gfx10:
    case AMDGPU::V_CMPX_GE_U64_e64_gfx11:
    case AMDGPU::V_CMPX_GE_U64_e64_gfx12:
    case AMDGPU::V_CMPX_GT_I16_e64_gfx10:
    case AMDGPU::V_CMPX_GT_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_GT_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_GT_I32_e64_gfx10:
    case AMDGPU::V_CMPX_GT_I32_e64_gfx11:
    case AMDGPU::V_CMPX_GT_I32_e64_gfx12:
    case AMDGPU::V_CMPX_GT_I64_e64_gfx10:
    case AMDGPU::V_CMPX_GT_I64_e64_gfx11:
    case AMDGPU::V_CMPX_GT_I64_e64_gfx12:
    case AMDGPU::V_CMPX_GT_U16_e64_gfx10:
    case AMDGPU::V_CMPX_GT_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_GT_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_GT_U32_e64_gfx10:
    case AMDGPU::V_CMPX_GT_U32_e64_gfx11:
    case AMDGPU::V_CMPX_GT_U32_e64_gfx12:
    case AMDGPU::V_CMPX_GT_U64_e64_gfx10:
    case AMDGPU::V_CMPX_GT_U64_e64_gfx11:
    case AMDGPU::V_CMPX_GT_U64_e64_gfx12:
    case AMDGPU::V_CMPX_LE_I16_e64_gfx10:
    case AMDGPU::V_CMPX_LE_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_LE_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_LE_I32_e64_gfx10:
    case AMDGPU::V_CMPX_LE_I32_e64_gfx11:
    case AMDGPU::V_CMPX_LE_I32_e64_gfx12:
    case AMDGPU::V_CMPX_LE_I64_e64_gfx10:
    case AMDGPU::V_CMPX_LE_I64_e64_gfx11:
    case AMDGPU::V_CMPX_LE_I64_e64_gfx12:
    case AMDGPU::V_CMPX_LE_U16_e64_gfx10:
    case AMDGPU::V_CMPX_LE_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_LE_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_LE_U32_e64_gfx10:
    case AMDGPU::V_CMPX_LE_U32_e64_gfx11:
    case AMDGPU::V_CMPX_LE_U32_e64_gfx12:
    case AMDGPU::V_CMPX_LE_U64_e64_gfx10:
    case AMDGPU::V_CMPX_LE_U64_e64_gfx11:
    case AMDGPU::V_CMPX_LE_U64_e64_gfx12:
    case AMDGPU::V_CMPX_LT_I16_e64_gfx10:
    case AMDGPU::V_CMPX_LT_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_LT_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_LT_I32_e64_gfx10:
    case AMDGPU::V_CMPX_LT_I32_e64_gfx11:
    case AMDGPU::V_CMPX_LT_I32_e64_gfx12:
    case AMDGPU::V_CMPX_LT_I64_e64_gfx10:
    case AMDGPU::V_CMPX_LT_I64_e64_gfx11:
    case AMDGPU::V_CMPX_LT_I64_e64_gfx12:
    case AMDGPU::V_CMPX_LT_U16_e64_gfx10:
    case AMDGPU::V_CMPX_LT_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_LT_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_LT_U32_e64_gfx10:
    case AMDGPU::V_CMPX_LT_U32_e64_gfx11:
    case AMDGPU::V_CMPX_LT_U32_e64_gfx12:
    case AMDGPU::V_CMPX_LT_U64_e64_gfx10:
    case AMDGPU::V_CMPX_LT_U64_e64_gfx11:
    case AMDGPU::V_CMPX_LT_U64_e64_gfx12:
    case AMDGPU::V_CMPX_NE_I16_e64_gfx10:
    case AMDGPU::V_CMPX_NE_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_NE_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_NE_I32_e64_gfx10:
    case AMDGPU::V_CMPX_NE_I32_e64_gfx11:
    case AMDGPU::V_CMPX_NE_I32_e64_gfx12:
    case AMDGPU::V_CMPX_NE_I64_e64_gfx10:
    case AMDGPU::V_CMPX_NE_I64_e64_gfx11:
    case AMDGPU::V_CMPX_NE_I64_e64_gfx12:
    case AMDGPU::V_CMPX_NE_U16_e64_gfx10:
    case AMDGPU::V_CMPX_NE_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_NE_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_NE_U32_e64_gfx10:
    case AMDGPU::V_CMPX_NE_U32_e64_gfx11:
    case AMDGPU::V_CMPX_NE_U32_e64_gfx12:
    case AMDGPU::V_CMPX_NE_U64_e64_gfx10:
    case AMDGPU::V_CMPX_NE_U64_e64_gfx11:
    case AMDGPU::V_CMPX_NE_U64_e64_gfx12:
    case AMDGPU::V_CMPX_T_I32_e64_gfx10:
    case AMDGPU::V_CMPX_T_I32_e64_gfx11:
    case AMDGPU::V_CMPX_T_I64_e64_gfx10:
    case AMDGPU::V_CMPX_T_I64_e64_gfx11:
    case AMDGPU::V_CMPX_T_U32_e64_gfx10:
    case AMDGPU::V_CMPX_T_U32_e64_gfx11:
    case AMDGPU::V_CMPX_T_U64_e64_gfx10:
    case AMDGPU::V_CMPX_T_U64_e64_gfx11: {
      switch (OpNum) {
      case 0:
        // op: src0
        return 32;
      case 1:
        // op: src1
        return 41;
      }
      break;
    }
    case AMDGPU::V_CMPX_EQ_F16_e64_gfx10:
    case AMDGPU::V_CMPX_EQ_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_EQ_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_EQ_F32_e64_gfx10:
    case AMDGPU::V_CMPX_EQ_F32_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_F32_e64_gfx12:
    case AMDGPU::V_CMPX_EQ_F64_e64_gfx10:
    case AMDGPU::V_CMPX_EQ_F64_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_F64_e64_gfx12:
    case AMDGPU::V_CMPX_F_F16_e64_gfx10:
    case AMDGPU::V_CMPX_F_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_F_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_F_F32_e64_gfx10:
    case AMDGPU::V_CMPX_F_F32_e64_gfx11:
    case AMDGPU::V_CMPX_F_F64_e64_gfx10:
    case AMDGPU::V_CMPX_F_F64_e64_gfx11:
    case AMDGPU::V_CMPX_GE_F16_e64_gfx10:
    case AMDGPU::V_CMPX_GE_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_GE_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_GE_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_GE_F32_e64_gfx10:
    case AMDGPU::V_CMPX_GE_F32_e64_gfx11:
    case AMDGPU::V_CMPX_GE_F32_e64_gfx12:
    case AMDGPU::V_CMPX_GE_F64_e64_gfx10:
    case AMDGPU::V_CMPX_GE_F64_e64_gfx11:
    case AMDGPU::V_CMPX_GE_F64_e64_gfx12:
    case AMDGPU::V_CMPX_GT_F16_e64_gfx10:
    case AMDGPU::V_CMPX_GT_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_GT_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_GT_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_GT_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_GT_F32_e64_gfx10:
    case AMDGPU::V_CMPX_GT_F32_e64_gfx11:
    case AMDGPU::V_CMPX_GT_F32_e64_gfx12:
    case AMDGPU::V_CMPX_GT_F64_e64_gfx10:
    case AMDGPU::V_CMPX_GT_F64_e64_gfx11:
    case AMDGPU::V_CMPX_GT_F64_e64_gfx12:
    case AMDGPU::V_CMPX_LE_F16_e64_gfx10:
    case AMDGPU::V_CMPX_LE_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_LE_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_LE_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_LE_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_LE_F32_e64_gfx10:
    case AMDGPU::V_CMPX_LE_F32_e64_gfx11:
    case AMDGPU::V_CMPX_LE_F32_e64_gfx12:
    case AMDGPU::V_CMPX_LE_F64_e64_gfx10:
    case AMDGPU::V_CMPX_LE_F64_e64_gfx11:
    case AMDGPU::V_CMPX_LE_F64_e64_gfx12:
    case AMDGPU::V_CMPX_LG_F16_e64_gfx10:
    case AMDGPU::V_CMPX_LG_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_LG_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_LG_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_LG_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_LG_F32_e64_gfx10:
    case AMDGPU::V_CMPX_LG_F32_e64_gfx11:
    case AMDGPU::V_CMPX_LG_F32_e64_gfx12:
    case AMDGPU::V_CMPX_LG_F64_e64_gfx10:
    case AMDGPU::V_CMPX_LG_F64_e64_gfx11:
    case AMDGPU::V_CMPX_LG_F64_e64_gfx12:
    case AMDGPU::V_CMPX_LT_F16_e64_gfx10:
    case AMDGPU::V_CMPX_LT_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_LT_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_LT_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_LT_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_LT_F32_e64_gfx10:
    case AMDGPU::V_CMPX_LT_F32_e64_gfx11:
    case AMDGPU::V_CMPX_LT_F32_e64_gfx12:
    case AMDGPU::V_CMPX_LT_F64_e64_gfx10:
    case AMDGPU::V_CMPX_LT_F64_e64_gfx11:
    case AMDGPU::V_CMPX_LT_F64_e64_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_e64_gfx10:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_NEQ_F32_e64_gfx10:
    case AMDGPU::V_CMPX_NEQ_F32_e64_gfx11:
    case AMDGPU::V_CMPX_NEQ_F32_e64_gfx12:
    case AMDGPU::V_CMPX_NEQ_F64_e64_gfx10:
    case AMDGPU::V_CMPX_NEQ_F64_e64_gfx11:
    case AMDGPU::V_CMPX_NEQ_F64_e64_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_e64_gfx10:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_NGE_F32_e64_gfx10:
    case AMDGPU::V_CMPX_NGE_F32_e64_gfx11:
    case AMDGPU::V_CMPX_NGE_F32_e64_gfx12:
    case AMDGPU::V_CMPX_NGE_F64_e64_gfx10:
    case AMDGPU::V_CMPX_NGE_F64_e64_gfx11:
    case AMDGPU::V_CMPX_NGE_F64_e64_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_e64_gfx10:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_NGT_F32_e64_gfx10:
    case AMDGPU::V_CMPX_NGT_F32_e64_gfx11:
    case AMDGPU::V_CMPX_NGT_F32_e64_gfx12:
    case AMDGPU::V_CMPX_NGT_F64_e64_gfx10:
    case AMDGPU::V_CMPX_NGT_F64_e64_gfx11:
    case AMDGPU::V_CMPX_NGT_F64_e64_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_e64_gfx10:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_NLE_F32_e64_gfx10:
    case AMDGPU::V_CMPX_NLE_F32_e64_gfx11:
    case AMDGPU::V_CMPX_NLE_F32_e64_gfx12:
    case AMDGPU::V_CMPX_NLE_F64_e64_gfx10:
    case AMDGPU::V_CMPX_NLE_F64_e64_gfx11:
    case AMDGPU::V_CMPX_NLE_F64_e64_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_e64_gfx10:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_NLG_F32_e64_gfx10:
    case AMDGPU::V_CMPX_NLG_F32_e64_gfx11:
    case AMDGPU::V_CMPX_NLG_F32_e64_gfx12:
    case AMDGPU::V_CMPX_NLG_F64_e64_gfx10:
    case AMDGPU::V_CMPX_NLG_F64_e64_gfx11:
    case AMDGPU::V_CMPX_NLG_F64_e64_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_e64_gfx10:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_NLT_F32_e64_gfx10:
    case AMDGPU::V_CMPX_NLT_F32_e64_gfx11:
    case AMDGPU::V_CMPX_NLT_F32_e64_gfx12:
    case AMDGPU::V_CMPX_NLT_F64_e64_gfx10:
    case AMDGPU::V_CMPX_NLT_F64_e64_gfx11:
    case AMDGPU::V_CMPX_NLT_F64_e64_gfx12:
    case AMDGPU::V_CMPX_O_F16_e64_gfx10:
    case AMDGPU::V_CMPX_O_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_O_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_O_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_O_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_O_F32_e64_gfx10:
    case AMDGPU::V_CMPX_O_F32_e64_gfx11:
    case AMDGPU::V_CMPX_O_F32_e64_gfx12:
    case AMDGPU::V_CMPX_O_F64_e64_gfx10:
    case AMDGPU::V_CMPX_O_F64_e64_gfx11:
    case AMDGPU::V_CMPX_O_F64_e64_gfx12:
    case AMDGPU::V_CMPX_TRU_F16_e64_gfx10:
    case AMDGPU::V_CMPX_TRU_F32_e64_gfx10:
    case AMDGPU::V_CMPX_TRU_F64_e64_gfx10:
    case AMDGPU::V_CMPX_T_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_T_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_T_F32_e64_gfx11:
    case AMDGPU::V_CMPX_T_F64_e64_gfx11:
    case AMDGPU::V_CMPX_U_F16_e64_gfx10:
    case AMDGPU::V_CMPX_U_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_U_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_U_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_U_F32_e64_gfx10:
    case AMDGPU::V_CMPX_U_F32_e64_gfx11:
    case AMDGPU::V_CMPX_U_F32_e64_gfx12:
    case AMDGPU::V_CMPX_U_F64_e64_gfx10:
    case AMDGPU::V_CMPX_U_F64_e64_gfx11:
    case AMDGPU::V_CMPX_U_F64_e64_gfx12: {
      switch (OpNum) {
      case 0:
        // op: src0_modifiers
        return 8;
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1_modifiers
        return 9;
      case 3:
        // op: src1
        return 41;
      case 4:
        // op: clamp
        return 15;
      }
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_e64_gfx10:
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMPX_CLASS_F16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_CLASS_F32_e64_gfx10:
    case AMDGPU::V_CMPX_CLASS_F32_e64_gfx11:
    case AMDGPU::V_CMPX_CLASS_F32_e64_gfx12:
    case AMDGPU::V_CMPX_CLASS_F64_e64_gfx10:
    case AMDGPU::V_CMPX_CLASS_F64_e64_gfx11:
    case AMDGPU::V_CMPX_CLASS_F64_e64_gfx12:
    case AMDGPU::V_CMPX_EQ_I16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_GE_I16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_GE_I16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_GE_U16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_GE_U16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_GT_I16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_GT_I16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_GT_U16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_GT_U16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_LE_I16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_LE_I16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_LE_U16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_LE_U16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_LT_I16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_LT_I16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_LT_U16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_LT_U16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_NE_I16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_NE_I16_t16_e64_gfx12:
    case AMDGPU::V_CMPX_NE_U16_t16_e64_gfx11:
    case AMDGPU::V_CMPX_NE_U16_t16_e64_gfx12:
    case AMDGPU::V_MFMA_LD_SCALE_B32_vi: {
      switch (OpNum) {
      case 0:
        // op: src0_modifiers
        return 8;
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1_modifiers
        return 9;
      case 3:
        // op: src1
        return 41;
      }
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_CLASS_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_CLASS_F32_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 0:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src1_modifiers
        return 9;
      case 3:
        // op: src1
        return 41;
      case 1:
        // op: src0
        return 64;
      case 4:
        // op: dpp8
        return 72;
      case 5:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_U16_t16_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 0:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src1_modifiers
        return 9;
      case 3:
        // op: src1
        return 41;
      case 1:
        // op: src0
        return 64;
      case 5:
        // op: dpp8
        return 72;
      case 6:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_CLASS_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_CLASS_F32_e64_dpp_gfx12: {
      switch (OpNum) {
      case 0:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src1_modifiers
        return 9;
      case 3:
        // op: src1
        return 41;
      case 4:
        // op: dpp_ctrl
        return 72;
      case 7:
        // op: bound_ctrl
        return 83;
      case 6:
        // op: bank_mask
        return 88;
      case 5:
        // op: row_mask
        return 92;
      case 8:
        // op: fi
        return 82;
      case 1:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_U16_t16_e64_dpp_gfx12: {
      switch (OpNum) {
      case 0:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src1_modifiers
        return 9;
      case 3:
        // op: src1
        return 41;
      case 5:
        // op: dpp_ctrl
        return 72;
      case 8:
        // op: bound_ctrl
        return 83;
      case 7:
        // op: bank_mask
        return 88;
      case 6:
        // op: row_mask
        return 92;
      case 9:
        // op: fi
        return 82;
      case 1:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_CMPX_EQ_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_F_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_F_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LG_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LG_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LG_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LG_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NEQ_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NEQ_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGE_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGE_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLE_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLE_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLG_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLG_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_O_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_O_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_O_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_O_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_T_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_T_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_U_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_U_F32_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 0:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: clamp
        return 15;
      case 3:
        // op: src1
        return 41;
      case 1:
        // op: src0
        return 64;
      case 5:
        // op: dpp8
        return 72;
      case 6:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CMPX_EQ_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_F_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LG_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LG_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_O_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_O_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_T_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_U_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_U_F16_t16_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 0:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: clamp
        return 15;
      case 3:
        // op: src1
        return 41;
      case 1:
        // op: src0
        return 64;
      case 6:
        // op: dpp8
        return 72;
      case 7:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CMPX_EQ_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_F_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_F_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LG_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LG_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LG_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LG_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NEQ_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NEQ_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NGE_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NGE_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NGT_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NGT_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NLE_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NLE_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NLG_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NLG_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NLT_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NLT_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_O_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_O_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_O_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_O_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_T_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_T_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_U_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F32_e64_dpp_gfx12: {
      switch (OpNum) {
      case 0:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: clamp
        return 15;
      case 3:
        // op: src1
        return 41;
      case 5:
        // op: dpp_ctrl
        return 72;
      case 8:
        // op: bound_ctrl
        return 83;
      case 7:
        // op: bank_mask
        return 88;
      case 6:
        // op: row_mask
        return 92;
      case 9:
        // op: fi
        return 82;
      case 1:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_CMPX_EQ_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_F_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LG_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LG_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_O_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_O_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_T_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F16_t16_e64_dpp_gfx12: {
      switch (OpNum) {
      case 0:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: clamp
        return 15;
      case 3:
        // op: src1
        return 41;
      case 6:
        // op: dpp_ctrl
        return 72;
      case 9:
        // op: bound_ctrl
        return 83;
      case 8:
        // op: bank_mask
        return 88;
      case 7:
        // op: row_mask
        return 92;
      case 10:
        // op: fi
        return 82;
      case 1:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::SCRATCH_LOAD_LDS_DWORD_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_SBYTE_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_SSHORT_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_UBYTE_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_USHORT_SVS_gfx940: {
      switch (OpNum) {
      case 0:
        // op: vaddr
        return 32;
      case 1:
        // op: saddr
        return 48;
      case 3:
        // op: cpol
        return 16;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_AND_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CSUB_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_INC_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_OR_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_gfx10:
    case AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR_gfx10:
    case AMDGPU::GLOBAL_STORE_BYTE_SADDR_gfx10:
    case AMDGPU::GLOBAL_STORE_DWORDX2_SADDR_gfx10:
    case AMDGPU::GLOBAL_STORE_DWORDX3_SADDR_gfx10:
    case AMDGPU::GLOBAL_STORE_DWORDX4_SADDR_gfx10:
    case AMDGPU::GLOBAL_STORE_DWORD_SADDR_gfx10:
    case AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR_gfx10:
    case AMDGPU::GLOBAL_STORE_SHORT_SADDR_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vaddr
        return 32;
      case 1:
        // op: vdata
        return 40;
      case 2:
        // op: saddr
        return 48;
      case 4:
        // op: cpol
        return 12;
      case 3:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_AND_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CSUB_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_INC_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_OR_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_gfx11:
    case AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR_gfx11:
    case AMDGPU::GLOBAL_STORE_BYTE_SADDR_gfx11:
    case AMDGPU::GLOBAL_STORE_DWORDX2_SADDR_gfx11:
    case AMDGPU::GLOBAL_STORE_DWORDX3_SADDR_gfx11:
    case AMDGPU::GLOBAL_STORE_DWORDX4_SADDR_gfx11:
    case AMDGPU::GLOBAL_STORE_DWORD_SADDR_gfx11:
    case AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR_gfx11:
    case AMDGPU::GLOBAL_STORE_SHORT_SADDR_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vaddr
        return 32;
      case 1:
        // op: vdata
        return 40;
      case 2:
        // op: saddr
        return 48;
      case 4:
        // op: cpol
        return 13;
      case 3:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR_vi:
    case AMDGPU::GLOBAL_STORE_BYTE_SADDR_vi:
    case AMDGPU::GLOBAL_STORE_DWORDX2_SADDR_vi:
    case AMDGPU::GLOBAL_STORE_DWORDX3_SADDR_vi:
    case AMDGPU::GLOBAL_STORE_DWORDX4_SADDR_vi:
    case AMDGPU::GLOBAL_STORE_DWORD_SADDR_vi:
    case AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR_vi:
    case AMDGPU::GLOBAL_STORE_SHORT_SADDR_vi: {
      switch (OpNum) {
      case 0:
        // op: vaddr
        return 32;
      case 1:
        // op: vdata
        return 40;
      case 2:
        // op: saddr
        return 48;
      case 4:
        // op: cpol
        return 16;
      case 3:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_OR_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_vi: {
      switch (OpNum) {
      case 0:
        // op: vaddr
        return 32;
      case 1:
        // op: vdata
        return 40;
      case 2:
        // op: saddr
        return 48;
      case 4:
        // op: cpol
        return 17;
      case 3:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_ADD_gfx10:
    case AMDGPU::FLAT_ATOMIC_AND_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_AND_gfx10:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_gfx10:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_DEC_gfx10:
    case AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_FCMPSWAP_gfx10:
    case AMDGPU::FLAT_ATOMIC_FMAX_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_FMAX_gfx10:
    case AMDGPU::FLAT_ATOMIC_FMIN_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_FMIN_gfx10:
    case AMDGPU::FLAT_ATOMIC_INC_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_INC_gfx10:
    case AMDGPU::FLAT_ATOMIC_OR_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_OR_gfx10:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_SMAX_gfx10:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_SMIN_gfx10:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_SUB_gfx10:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_SWAP_gfx10:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_UMAX_gfx10:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_UMIN_gfx10:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_gfx10:
    case AMDGPU::FLAT_ATOMIC_XOR_gfx10:
    case AMDGPU::FLAT_STORE_BYTE_D16_HI_gfx10:
    case AMDGPU::FLAT_STORE_BYTE_gfx10:
    case AMDGPU::FLAT_STORE_DWORDX2_gfx10:
    case AMDGPU::FLAT_STORE_DWORDX3_gfx10:
    case AMDGPU::FLAT_STORE_DWORDX4_gfx10:
    case AMDGPU::FLAT_STORE_DWORD_gfx10:
    case AMDGPU::FLAT_STORE_SHORT_D16_HI_gfx10:
    case AMDGPU::FLAT_STORE_SHORT_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_ADD_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_AND_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CSUB_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_DEC_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_INC_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_OR_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SUB_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_XOR_gfx10:
    case AMDGPU::GLOBAL_STORE_BYTE_D16_HI_gfx10:
    case AMDGPU::GLOBAL_STORE_BYTE_gfx10:
    case AMDGPU::GLOBAL_STORE_DWORDX2_gfx10:
    case AMDGPU::GLOBAL_STORE_DWORDX3_gfx10:
    case AMDGPU::GLOBAL_STORE_DWORDX4_gfx10:
    case AMDGPU::GLOBAL_STORE_DWORD_gfx10:
    case AMDGPU::GLOBAL_STORE_SHORT_D16_HI_gfx10:
    case AMDGPU::GLOBAL_STORE_SHORT_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vaddr
        return 32;
      case 1:
        // op: vdata
        return 40;
      case 3:
        // op: cpol
        return 12;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_F32_gfx11:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_ADD_gfx11:
    case AMDGPU::FLAT_ATOMIC_AND_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_AND_gfx11:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_gfx11:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_DEC_gfx11:
    case AMDGPU::FLAT_ATOMIC_FCMPSWAP_gfx11:
    case AMDGPU::FLAT_ATOMIC_FMAX_gfx11:
    case AMDGPU::FLAT_ATOMIC_FMIN_gfx11:
    case AMDGPU::FLAT_ATOMIC_INC_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_INC_gfx11:
    case AMDGPU::FLAT_ATOMIC_OR_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_OR_gfx11:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_SMAX_gfx11:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_SMIN_gfx11:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_SUB_gfx11:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_SWAP_gfx11:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_UMAX_gfx11:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_UMIN_gfx11:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_gfx11:
    case AMDGPU::FLAT_ATOMIC_XOR_gfx11:
    case AMDGPU::FLAT_STORE_BYTE_D16_HI_gfx11:
    case AMDGPU::FLAT_STORE_BYTE_gfx11:
    case AMDGPU::FLAT_STORE_DWORDX2_gfx11:
    case AMDGPU::FLAT_STORE_DWORDX3_gfx11:
    case AMDGPU::FLAT_STORE_DWORDX4_gfx11:
    case AMDGPU::FLAT_STORE_DWORD_gfx11:
    case AMDGPU::FLAT_STORE_SHORT_D16_HI_gfx11:
    case AMDGPU::FLAT_STORE_SHORT_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_ADD_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_AND_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CSUB_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_DEC_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_INC_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_OR_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SUB_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_XOR_gfx11:
    case AMDGPU::GLOBAL_STORE_BYTE_D16_HI_gfx11:
    case AMDGPU::GLOBAL_STORE_BYTE_gfx11:
    case AMDGPU::GLOBAL_STORE_DWORDX2_gfx11:
    case AMDGPU::GLOBAL_STORE_DWORDX3_gfx11:
    case AMDGPU::GLOBAL_STORE_DWORDX4_gfx11:
    case AMDGPU::GLOBAL_STORE_DWORD_gfx11:
    case AMDGPU::GLOBAL_STORE_SHORT_D16_HI_gfx11:
    case AMDGPU::GLOBAL_STORE_SHORT_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vaddr
        return 32;
      case 1:
        // op: vdata
        return 40;
      case 3:
        // op: cpol
        return 13;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::FLAT_STORE_BYTE_D16_HI_vi:
    case AMDGPU::FLAT_STORE_BYTE_ci:
    case AMDGPU::FLAT_STORE_BYTE_vi:
    case AMDGPU::FLAT_STORE_DWORDX2_ci:
    case AMDGPU::FLAT_STORE_DWORDX2_vi:
    case AMDGPU::FLAT_STORE_DWORDX3_ci:
    case AMDGPU::FLAT_STORE_DWORDX3_vi:
    case AMDGPU::FLAT_STORE_DWORDX4_ci:
    case AMDGPU::FLAT_STORE_DWORDX4_vi:
    case AMDGPU::FLAT_STORE_DWORD_ci:
    case AMDGPU::FLAT_STORE_DWORD_vi:
    case AMDGPU::FLAT_STORE_SHORT_D16_HI_vi:
    case AMDGPU::FLAT_STORE_SHORT_ci:
    case AMDGPU::FLAT_STORE_SHORT_vi:
    case AMDGPU::GLOBAL_STORE_BYTE_D16_HI_vi:
    case AMDGPU::GLOBAL_STORE_BYTE_vi:
    case AMDGPU::GLOBAL_STORE_DWORDX2_vi:
    case AMDGPU::GLOBAL_STORE_DWORDX3_vi:
    case AMDGPU::GLOBAL_STORE_DWORDX4_vi:
    case AMDGPU::GLOBAL_STORE_DWORD_vi:
    case AMDGPU::GLOBAL_STORE_SHORT_D16_HI_vi:
    case AMDGPU::GLOBAL_STORE_SHORT_vi: {
      switch (OpNum) {
      case 0:
        // op: vaddr
        return 32;
      case 1:
        // op: vdata
        return 40;
      case 3:
        // op: cpol
        return 16;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_F32_vi:
    case AMDGPU::FLAT_ATOMIC_ADD_F64_gfx940:
    case AMDGPU::FLAT_ATOMIC_ADD_F64_vi:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_ci:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_vi:
    case AMDGPU::FLAT_ATOMIC_ADD_ci:
    case AMDGPU::FLAT_ATOMIC_ADD_vi:
    case AMDGPU::FLAT_ATOMIC_AND_X2_ci:
    case AMDGPU::FLAT_ATOMIC_AND_X2_vi:
    case AMDGPU::FLAT_ATOMIC_AND_ci:
    case AMDGPU::FLAT_ATOMIC_AND_vi:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_ci:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_vi:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_ci:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_vi:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_ci:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_vi:
    case AMDGPU::FLAT_ATOMIC_DEC_ci:
    case AMDGPU::FLAT_ATOMIC_DEC_vi:
    case AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_ci:
    case AMDGPU::FLAT_ATOMIC_FCMPSWAP_ci:
    case AMDGPU::FLAT_ATOMIC_FMAX_X2_ci:
    case AMDGPU::FLAT_ATOMIC_FMAX_ci:
    case AMDGPU::FLAT_ATOMIC_FMIN_X2_ci:
    case AMDGPU::FLAT_ATOMIC_FMIN_ci:
    case AMDGPU::FLAT_ATOMIC_INC_X2_ci:
    case AMDGPU::FLAT_ATOMIC_INC_X2_vi:
    case AMDGPU::FLAT_ATOMIC_INC_ci:
    case AMDGPU::FLAT_ATOMIC_INC_vi:
    case AMDGPU::FLAT_ATOMIC_MAX_F64_gfx940:
    case AMDGPU::FLAT_ATOMIC_MAX_F64_vi:
    case AMDGPU::FLAT_ATOMIC_MIN_F64_gfx940:
    case AMDGPU::FLAT_ATOMIC_MIN_F64_vi:
    case AMDGPU::FLAT_ATOMIC_OR_X2_ci:
    case AMDGPU::FLAT_ATOMIC_OR_X2_vi:
    case AMDGPU::FLAT_ATOMIC_OR_ci:
    case AMDGPU::FLAT_ATOMIC_OR_vi:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_BF16_vi:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_F16_vi:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_ci:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_vi:
    case AMDGPU::FLAT_ATOMIC_SMAX_ci:
    case AMDGPU::FLAT_ATOMIC_SMAX_vi:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_ci:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_vi:
    case AMDGPU::FLAT_ATOMIC_SMIN_ci:
    case AMDGPU::FLAT_ATOMIC_SMIN_vi:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_ci:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_vi:
    case AMDGPU::FLAT_ATOMIC_SUB_ci:
    case AMDGPU::FLAT_ATOMIC_SUB_vi:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_ci:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_vi:
    case AMDGPU::FLAT_ATOMIC_SWAP_ci:
    case AMDGPU::FLAT_ATOMIC_SWAP_vi:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_ci:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_vi:
    case AMDGPU::FLAT_ATOMIC_UMAX_ci:
    case AMDGPU::FLAT_ATOMIC_UMAX_vi:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_ci:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_vi:
    case AMDGPU::FLAT_ATOMIC_UMIN_ci:
    case AMDGPU::FLAT_ATOMIC_UMIN_vi:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_ci:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_vi:
    case AMDGPU::FLAT_ATOMIC_XOR_ci:
    case AMDGPU::FLAT_ATOMIC_XOR_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_vi:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_vi:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_vi:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_OR_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_vi: {
      switch (OpNum) {
      case 0:
        // op: vaddr
        return 32;
      case 1:
        // op: vdata
        return 40;
      case 3:
        // op: cpol
        return 17;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::GLOBAL_LOAD_LDS_DWORD_gfx10:
    case AMDGPU::GLOBAL_LOAD_LDS_SBYTE_gfx10:
    case AMDGPU::GLOBAL_LOAD_LDS_SSHORT_gfx10:
    case AMDGPU::GLOBAL_LOAD_LDS_UBYTE_gfx10:
    case AMDGPU::GLOBAL_LOAD_LDS_USHORT_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_DWORD_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_SBYTE_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_SSHORT_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_UBYTE_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_USHORT_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vaddr
        return 32;
      case 2:
        // op: cpol
        return 12;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::GLOBAL_LOAD_LDS_DWORDX3_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_DWORDX3_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_DWORDX4_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_DWORDX4_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_DWORD_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_DWORD_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_SBYTE_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_SBYTE_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_SSHORT_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_SSHORT_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_UBYTE_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_UBYTE_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_USHORT_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_USHORT_vi:
    case AMDGPU::SCRATCH_LOAD_LDS_DWORD_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_DWORD_vi:
    case AMDGPU::SCRATCH_LOAD_LDS_SBYTE_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_SBYTE_vi:
    case AMDGPU::SCRATCH_LOAD_LDS_SSHORT_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_SSHORT_vi:
    case AMDGPU::SCRATCH_LOAD_LDS_UBYTE_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_UBYTE_vi:
    case AMDGPU::SCRATCH_LOAD_LDS_USHORT_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_USHORT_vi: {
      switch (OpNum) {
      case 0:
        // op: vaddr
        return 32;
      case 2:
        // op: cpol
        return 16;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V1_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V2_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V3_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V4_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V1_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V2_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V3_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V4_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V1_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V2_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V3_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V4_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V1_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V2_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V3_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V4_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V1_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V2_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V3_gfx90a:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V1_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V1_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V1_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V1_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V2_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V2_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V2_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V2_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V3_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V3_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V3_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V3_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V4_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V4_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V4_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V4_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V5_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V5_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V5_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_PCK_V5_V4_gfx90a: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 16;
      case 3:
        // op: dmask
        return 8;
      case 4:
        // op: unorm
        return 12;
      case 5:
        // op: cpol
        return 7;
      case 6:
        // op: r128
        return 15;
      case 7:
        // op: lwe
        return 17;
      case 2:
        // op: srsrc
        return 48;
      case 1:
        // op: vaddr
        return 32;
      case 8:
        // op: da
        return 14;
      }
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_V1_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_V1_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_V1_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_V1_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_V2_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_V2_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_V2_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_V2_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_V3_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_V3_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_V3_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_V3_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_V4_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_V4_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_V4_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_V4_V4_gfx90a:
    case AMDGPU::IMAGE_LOAD_V5_V1_gfx90a:
    case AMDGPU::IMAGE_LOAD_V5_V2_gfx90a:
    case AMDGPU::IMAGE_LOAD_V5_V3_gfx90a:
    case AMDGPU::IMAGE_LOAD_V5_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V1_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V1_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V1_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V1_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V2_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V2_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V2_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V2_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V3_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V3_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V3_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V3_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V4_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V4_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V4_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V4_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V5_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V5_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V5_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_MIP_V5_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_V1_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_V1_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_V1_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_V1_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_V2_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_V2_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_V2_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_V2_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_V3_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_V3_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_V3_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_V3_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_V4_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_V4_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_V4_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_V4_V4_gfx90a:
    case AMDGPU::IMAGE_STORE_V5_V1_gfx90a:
    case AMDGPU::IMAGE_STORE_V5_V2_gfx90a:
    case AMDGPU::IMAGE_STORE_V5_V3_gfx90a:
    case AMDGPU::IMAGE_STORE_V5_V4_gfx90a: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 16;
      case 3:
        // op: dmask
        return 8;
      case 4:
        // op: unorm
        return 12;
      case 5:
        // op: cpol
        return 7;
      case 6:
        // op: r128
        return 15;
      case 7:
        // op: lwe
        return 17;
      case 9:
        // op: d16
        return 63;
      case 2:
        // op: srsrc
        return 48;
      case 1:
        // op: vaddr
        return 32;
      case 8:
        // op: da
        return 14;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_V1_V1_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V1_V2_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V1_V3_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V1_V4_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V2_V1_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V2_V2_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V2_V3_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V2_V4_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V3_V1_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V3_V2_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V3_V3_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V3_V4_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V4_V1_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V4_V2_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V4_V3_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V4_V4_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V5_V1_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V5_V2_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V5_V3_gfx90a:
    case AMDGPU::IMAGE_SAMPLE_V5_V4_gfx90a: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 16;
      case 4:
        // op: dmask
        return 8;
      case 5:
        // op: unorm
        return 12;
      case 6:
        // op: cpol
        return 7;
      case 7:
        // op: r128
        return 15;
      case 8:
        // op: lwe
        return 17;
      case 10:
        // op: d16
        return 63;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: ssamp
        return 53;
      case 1:
        // op: vaddr
        return 32;
      case 9:
        // op: da
        return 14;
      }
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V1_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V1_V2_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V1_V3_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V1_V4_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V2_V1_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V2_V2_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V2_V3_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V2_V4_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V3_V1_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V3_V2_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V3_V3_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V3_V4_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V4_V1_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V4_V2_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V4_V3_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V4_V4_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V5_V1_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V5_V2_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V5_V3_gfx90a:
    case AMDGPU::IMAGE_GET_LOD_V5_V4_gfx90a: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 16;
      case 4:
        // op: dmask
        return 8;
      case 5:
        // op: unorm
        return 12;
      case 6:
        // op: cpol
        return 7;
      case 7:
        // op: r128
        return 15;
      case 8:
        // op: lwe
        return 17;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: ssamp
        return 53;
      case 1:
        // op: vaddr
        return 32;
      case 9:
        // op: da
        return 14;
      }
      break;
    }
    case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_gfx12:
    case AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 32;
      case 5:
        // op: rsrc
        return 41;
      case 1:
        // op: vaddr0
        return 64;
      case 2:
        // op: vaddr1
        return 72;
      case 3:
        // op: vaddr2
        return 80;
      case 4:
        // op: vaddr3
        return 88;
      }
      break;
    }
    case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_gfx12:
    case AMDGPU::IMAGE_BVH_INTERSECT_RAY_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 32;
      case 6:
        // op: rsrc
        return 41;
      case 1:
        // op: vaddr0
        return 64;
      case 2:
        // op: vaddr1
        return 72;
      case 3:
        // op: vaddr2
        return 80;
      case 4:
        // op: vaddr3
        return 88;
      case 5:
        // op: vaddr4
        return 56;
      }
      break;
    }
    case AMDGPU::IMAGE_BVH8_INTERSECT_RAY_gfx12:
    case AMDGPU::IMAGE_BVH_DUAL_INTERSECT_RAY_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 32;
      case 8:
        // op: rsrc
        return 41;
      case 3:
        // op: vaddr0
        return 64;
      case 4:
        // op: vaddr1
        return 72;
      case 5:
        // op: vaddr2
        return 80;
      case 6:
        // op: vaddr3
        return 88;
      case 7:
        // op: vaddr4
        return 56;
      }
      break;
    }
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V7_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 10:
        // op: dmask
        return 8;
      case 12:
        // op: unorm
        return 12;
      case 13:
        // op: cpol
        return 7;
      case 14:
        // op: r128
        return 15;
      case 16:
        // op: tfe
        return 16;
      case 17:
        // op: lwe
        return 17;
      case 18:
        // op: d16
        return 63;
      case 8:
        // op: srsrc
        return 48;
      case 9:
        // op: ssamp
        return 53;
      case 1:
        // op: vaddr0
        return 32;
      case 11:
        // op: dim
        return 3;
      case 15:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 10:
        // op: srsrc
        return 48;
      case 1:
        // op: vaddr0
        return 32;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V8_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 11:
        // op: dmask
        return 8;
      case 13:
        // op: unorm
        return 12;
      case 14:
        // op: cpol
        return 7;
      case 15:
        // op: r128
        return 15;
      case 17:
        // op: tfe
        return 16;
      case 18:
        // op: lwe
        return 17;
      case 19:
        // op: d16
        return 63;
      case 9:
        // op: srsrc
        return 48;
      case 10:
        // op: ssamp
        return 53;
      case 1:
        // op: vaddr0
        return 32;
      case 12:
        // op: dim
        return 3;
      case 16:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V9_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 12:
        // op: dmask
        return 8;
      case 14:
        // op: unorm
        return 12;
      case 15:
        // op: cpol
        return 7;
      case 16:
        // op: r128
        return 15;
      case 18:
        // op: tfe
        return 16;
      case 19:
        // op: lwe
        return 17;
      case 20:
        // op: d16
        return 63;
      case 10:
        // op: srsrc
        return 48;
      case 11:
        // op: ssamp
        return 53;
      case 1:
        // op: vaddr0
        return 32;
      case 13:
        // op: dim
        return 3;
      case 17:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_BVH_INTERSECT_RAY_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 12:
        // op: srsrc
        return 48;
      case 1:
        // op: vaddr0
        return 32;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V10_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 13:
        // op: dmask
        return 8;
      case 15:
        // op: unorm
        return 12;
      case 16:
        // op: cpol
        return 7;
      case 17:
        // op: r128
        return 15;
      case 19:
        // op: tfe
        return 16;
      case 20:
        // op: lwe
        return 17;
      case 21:
        // op: d16
        return 63;
      case 11:
        // op: srsrc
        return 48;
      case 12:
        // op: ssamp
        return 53;
      case 1:
        // op: vaddr0
        return 32;
      case 14:
        // op: dim
        return 3;
      case 18:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 13:
        // op: srsrc
        return 48;
      case 1:
        // op: vaddr0
        return 32;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V11_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 14:
        // op: dmask
        return 8;
      case 16:
        // op: unorm
        return 12;
      case 17:
        // op: cpol
        return 7;
      case 18:
        // op: r128
        return 15;
      case 20:
        // op: tfe
        return 16;
      case 21:
        // op: lwe
        return 17;
      case 22:
        // op: d16
        return 63;
      case 12:
        // op: srsrc
        return 48;
      case 13:
        // op: ssamp
        return 53;
      case 1:
        // op: vaddr0
        return 32;
      case 15:
        // op: dim
        return 3;
      case 19:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V12_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V12_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V12_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V12_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V12_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V12_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V12_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V12_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V12_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V12_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 15:
        // op: dmask
        return 8;
      case 17:
        // op: unorm
        return 12;
      case 18:
        // op: cpol
        return 7;
      case 19:
        // op: r128
        return 15;
      case 21:
        // op: tfe
        return 16;
      case 22:
        // op: lwe
        return 17;
      case 23:
        // op: d16
        return 63;
      case 13:
        // op: srsrc
        return 48;
      case 14:
        // op: ssamp
        return 53;
      case 1:
        // op: vaddr0
        return 32;
      case 16:
        // op: dim
        return 3;
      case 20:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::GLOBAL_STORE_DWORD_ADDTID_SADDR_gfx10:
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR_gfx10:
    case AMDGPU::SCRATCH_STORE_BYTE_SADDR_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORDX2_SADDR_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORDX3_SADDR_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORDX4_SADDR_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORD_SADDR_gfx10:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR_gfx10:
    case AMDGPU::SCRATCH_STORE_SHORT_SADDR_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 1:
        // op: saddr
        return 48;
      case 3:
        // op: cpol
        return 12;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::GLOBAL_STORE_DWORD_ADDTID_SADDR_gfx11:
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR_gfx11:
    case AMDGPU::SCRATCH_STORE_BYTE_SADDR_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX2_SADDR_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX3_SADDR_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX4_SADDR_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORD_SADDR_gfx11:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR_gfx11:
    case AMDGPU::SCRATCH_STORE_SHORT_SADDR_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 1:
        // op: saddr
        return 48;
      case 3:
        // op: cpol
        return 13;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR_vi:
    case AMDGPU::SCRATCH_STORE_BYTE_SADDR_vi:
    case AMDGPU::SCRATCH_STORE_DWORDX2_SADDR_vi:
    case AMDGPU::SCRATCH_STORE_DWORDX3_SADDR_vi:
    case AMDGPU::SCRATCH_STORE_DWORDX4_SADDR_vi:
    case AMDGPU::SCRATCH_STORE_DWORD_SADDR_vi:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR_vi:
    case AMDGPU::SCRATCH_STORE_SHORT_SADDR_vi: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 1:
        // op: saddr
        return 48;
      case 3:
        // op: cpol
        return 16;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::GLOBAL_STORE_DWORD_ADDTID_gfx10:
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_ST_gfx10:
    case AMDGPU::SCRATCH_STORE_BYTE_ST_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORDX2_ST_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORDX3_ST_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORDX4_ST_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORD_ST_gfx10:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_ST_gfx10:
    case AMDGPU::SCRATCH_STORE_SHORT_ST_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 2:
        // op: cpol
        return 12;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::GLOBAL_STORE_DWORD_ADDTID_gfx11:
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_ST_gfx11:
    case AMDGPU::SCRATCH_STORE_BYTE_ST_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX2_ST_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX3_ST_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX4_ST_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORD_ST_gfx11:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_ST_gfx11:
    case AMDGPU::SCRATCH_STORE_SHORT_ST_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 2:
        // op: cpol
        return 13;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_ST_gfx940:
    case AMDGPU::SCRATCH_STORE_BYTE_ST_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORDX2_ST_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORDX3_ST_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORDX4_ST_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORD_ST_gfx940:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_ST_gfx940:
    case AMDGPU::SCRATCH_STORE_SHORT_ST_gfx940: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 2:
        // op: cpol
        return 16;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_sa_gfx10:
    case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_sa_gfx11:
    case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_sa_gfx10:
    case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_sa_gfx11:
    case AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_sa_gfx10:
    case AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_sa_gfx11:
    case AMDGPU::IMAGE_BVH_INTERSECT_RAY_sa_gfx10:
    case AMDGPU::IMAGE_BVH_INTERSECT_RAY_sa_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 2:
        // op: srsrc
        return 48;
      case 1:
        // op: vaddr0
        return 32;
      }
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V1:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V2:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V3:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V4:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V1:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V2:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V3:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V4:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V1:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V2:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V3:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V4:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V1:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V2:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V3:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V4:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V1:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V2:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V3:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V4:
    case AMDGPU::IMAGE_LOAD_V1_V1:
    case AMDGPU::IMAGE_LOAD_V1_V2:
    case AMDGPU::IMAGE_LOAD_V1_V3:
    case AMDGPU::IMAGE_LOAD_V1_V4:
    case AMDGPU::IMAGE_LOAD_V2_V1:
    case AMDGPU::IMAGE_LOAD_V2_V2:
    case AMDGPU::IMAGE_LOAD_V2_V3:
    case AMDGPU::IMAGE_LOAD_V2_V4:
    case AMDGPU::IMAGE_LOAD_V3_V1:
    case AMDGPU::IMAGE_LOAD_V3_V2:
    case AMDGPU::IMAGE_LOAD_V3_V3:
    case AMDGPU::IMAGE_LOAD_V3_V4:
    case AMDGPU::IMAGE_LOAD_V4_V1:
    case AMDGPU::IMAGE_LOAD_V4_V2:
    case AMDGPU::IMAGE_LOAD_V4_V3:
    case AMDGPU::IMAGE_LOAD_V4_V4:
    case AMDGPU::IMAGE_LOAD_V5_V1:
    case AMDGPU::IMAGE_LOAD_V5_V2:
    case AMDGPU::IMAGE_LOAD_V5_V3:
    case AMDGPU::IMAGE_LOAD_V5_V4:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V1:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V2:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V3:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V4:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V1:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V2:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V3:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V4:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V1:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V2:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V3:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V4:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V1:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V2:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V3:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V4:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V1:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V2:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V3:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V4:
    case AMDGPU::IMAGE_STORE_MIP_V1_V1:
    case AMDGPU::IMAGE_STORE_MIP_V1_V2:
    case AMDGPU::IMAGE_STORE_MIP_V1_V3:
    case AMDGPU::IMAGE_STORE_MIP_V1_V4:
    case AMDGPU::IMAGE_STORE_MIP_V2_V1:
    case AMDGPU::IMAGE_STORE_MIP_V2_V2:
    case AMDGPU::IMAGE_STORE_MIP_V2_V3:
    case AMDGPU::IMAGE_STORE_MIP_V2_V4:
    case AMDGPU::IMAGE_STORE_MIP_V3_V1:
    case AMDGPU::IMAGE_STORE_MIP_V3_V2:
    case AMDGPU::IMAGE_STORE_MIP_V3_V3:
    case AMDGPU::IMAGE_STORE_MIP_V3_V4:
    case AMDGPU::IMAGE_STORE_MIP_V4_V1:
    case AMDGPU::IMAGE_STORE_MIP_V4_V2:
    case AMDGPU::IMAGE_STORE_MIP_V4_V3:
    case AMDGPU::IMAGE_STORE_MIP_V4_V4:
    case AMDGPU::IMAGE_STORE_MIP_V5_V1:
    case AMDGPU::IMAGE_STORE_MIP_V5_V2:
    case AMDGPU::IMAGE_STORE_MIP_V5_V3:
    case AMDGPU::IMAGE_STORE_MIP_V5_V4:
    case AMDGPU::IMAGE_STORE_V1_V1:
    case AMDGPU::IMAGE_STORE_V1_V2:
    case AMDGPU::IMAGE_STORE_V1_V3:
    case AMDGPU::IMAGE_STORE_V1_V4:
    case AMDGPU::IMAGE_STORE_V2_V1:
    case AMDGPU::IMAGE_STORE_V2_V2:
    case AMDGPU::IMAGE_STORE_V2_V3:
    case AMDGPU::IMAGE_STORE_V2_V4:
    case AMDGPU::IMAGE_STORE_V3_V1:
    case AMDGPU::IMAGE_STORE_V3_V2:
    case AMDGPU::IMAGE_STORE_V3_V3:
    case AMDGPU::IMAGE_STORE_V3_V4:
    case AMDGPU::IMAGE_STORE_V4_V1:
    case AMDGPU::IMAGE_STORE_V4_V2:
    case AMDGPU::IMAGE_STORE_V4_V3:
    case AMDGPU::IMAGE_STORE_V4_V4:
    case AMDGPU::IMAGE_STORE_V5_V1:
    case AMDGPU::IMAGE_STORE_V5_V2:
    case AMDGPU::IMAGE_STORE_V5_V3:
    case AMDGPU::IMAGE_STORE_V5_V4: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 3:
        // op: dmask
        return 8;
      case 4:
        // op: unorm
        return 12;
      case 5:
        // op: cpol
        return 7;
      case 6:
        // op: r128
        return 15;
      case 7:
        // op: tfe
        return 16;
      case 8:
        // op: lwe
        return 17;
      case 10:
        // op: d16
        return 63;
      case 2:
        // op: srsrc
        return 48;
      case 1:
        // op: vaddr
        return 32;
      case 9:
        // op: da
        return 14;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V1_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V1_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V4_vi:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V1:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V2:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V3:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V4:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V1:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V2:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V3:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V4:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V1:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V2:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V3:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V4:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V1:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V2:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V3:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V4:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V1:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V2:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V3:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V4:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V1:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V1:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V1:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V1:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V1:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V2:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V3:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V4:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V1:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V1:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V1:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V1:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V1:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V2:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V3:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V4:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V1:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V1:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V1:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V1:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V1:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V2:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V3:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V4:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V1:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V2:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V3:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V4:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V1:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V2:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V3:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V4:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V1:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V2:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V3:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V4:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V1:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V2:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V3:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V4:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V1:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V2:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V3:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V4:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V1:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V1:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V1:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V1:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V1:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V2:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V3:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V4:
    case AMDGPU::IMAGE_STORE_PCK_V1_V1:
    case AMDGPU::IMAGE_STORE_PCK_V1_V2:
    case AMDGPU::IMAGE_STORE_PCK_V1_V3:
    case AMDGPU::IMAGE_STORE_PCK_V1_V4:
    case AMDGPU::IMAGE_STORE_PCK_V2_V1:
    case AMDGPU::IMAGE_STORE_PCK_V2_V2:
    case AMDGPU::IMAGE_STORE_PCK_V2_V3:
    case AMDGPU::IMAGE_STORE_PCK_V2_V4:
    case AMDGPU::IMAGE_STORE_PCK_V3_V1:
    case AMDGPU::IMAGE_STORE_PCK_V3_V2:
    case AMDGPU::IMAGE_STORE_PCK_V3_V3:
    case AMDGPU::IMAGE_STORE_PCK_V3_V4:
    case AMDGPU::IMAGE_STORE_PCK_V4_V1:
    case AMDGPU::IMAGE_STORE_PCK_V4_V2:
    case AMDGPU::IMAGE_STORE_PCK_V4_V3:
    case AMDGPU::IMAGE_STORE_PCK_V4_V4:
    case AMDGPU::IMAGE_STORE_PCK_V5_V1:
    case AMDGPU::IMAGE_STORE_PCK_V5_V2:
    case AMDGPU::IMAGE_STORE_PCK_V5_V3:
    case AMDGPU::IMAGE_STORE_PCK_V5_V4: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 3:
        // op: dmask
        return 8;
      case 4:
        // op: unorm
        return 12;
      case 5:
        // op: cpol
        return 7;
      case 6:
        // op: r128
        return 15;
      case 7:
        // op: tfe
        return 16;
      case 8:
        // op: lwe
        return 17;
      case 2:
        // op: srsrc
        return 48;
      case 1:
        // op: vaddr
        return 32;
      case 9:
        // op: da
        return 14;
      }
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_V1_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_V1_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_V1_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_V1_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_V2_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_V2_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_V2_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_V2_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_V3_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_V3_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_V3_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_V3_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_V4_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_V4_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_V4_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_V4_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_V5_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_V5_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_V5_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_V5_V4_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V1_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V2_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V3_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V4_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V1_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V2_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V3_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V4_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V1_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V2_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V3_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V4_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V1_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V2_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V3_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V4_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V1_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V2_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V3_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V4_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V1_V1_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V1_V2_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V1_V3_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V1_V4_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V2_V1_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V2_V2_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V2_V3_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V2_V4_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V3_V1_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V3_V2_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V3_V3_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V3_V4_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V4_V1_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V4_V2_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V4_V3_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V4_V4_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V5_V1_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V5_V2_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V5_V3_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V5_V4_gfx10:
    case AMDGPU::IMAGE_STORE_V1_V1_gfx10:
    case AMDGPU::IMAGE_STORE_V1_V2_gfx10:
    case AMDGPU::IMAGE_STORE_V1_V3_gfx10:
    case AMDGPU::IMAGE_STORE_V1_V4_gfx10:
    case AMDGPU::IMAGE_STORE_V2_V1_gfx10:
    case AMDGPU::IMAGE_STORE_V2_V2_gfx10:
    case AMDGPU::IMAGE_STORE_V2_V3_gfx10:
    case AMDGPU::IMAGE_STORE_V2_V4_gfx10:
    case AMDGPU::IMAGE_STORE_V3_V1_gfx10:
    case AMDGPU::IMAGE_STORE_V3_V2_gfx10:
    case AMDGPU::IMAGE_STORE_V3_V3_gfx10:
    case AMDGPU::IMAGE_STORE_V3_V4_gfx10:
    case AMDGPU::IMAGE_STORE_V4_V1_gfx10:
    case AMDGPU::IMAGE_STORE_V4_V2_gfx10:
    case AMDGPU::IMAGE_STORE_V4_V3_gfx10:
    case AMDGPU::IMAGE_STORE_V4_V4_gfx10:
    case AMDGPU::IMAGE_STORE_V5_V1_gfx10:
    case AMDGPU::IMAGE_STORE_V5_V2_gfx10:
    case AMDGPU::IMAGE_STORE_V5_V3_gfx10:
    case AMDGPU::IMAGE_STORE_V5_V4_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 3:
        // op: dmask
        return 8;
      case 5:
        // op: unorm
        return 12;
      case 6:
        // op: cpol
        return 7;
      case 7:
        // op: r128
        return 15;
      case 9:
        // op: tfe
        return 16;
      case 10:
        // op: lwe
        return 17;
      case 11:
        // op: d16
        return 63;
      case 2:
        // op: srsrc
        return 48;
      case 1:
        // op: vaddr0
        return 32;
      case 4:
        // op: dim
        return 3;
      case 8:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V4_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V1_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V2_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V3_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V4_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V1_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V2_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V3_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V4_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V1_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V2_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V3_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V4_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V1_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V2_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V3_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V4_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V1_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V2_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V3_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V4_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V1_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V2_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V3_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V4_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V1_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V1_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V1_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V1_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V1_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V2_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V3_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V4_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V1_V1_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V1_V2_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V1_V3_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V1_V4_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V2_V1_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V2_V2_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V2_V3_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V2_V4_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V3_V1_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V3_V2_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V3_V3_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V3_V4_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V4_V1_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V4_V2_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V4_V3_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V4_V4_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V5_V1_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V5_V2_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V5_V3_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V5_V4_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 3:
        // op: dmask
        return 8;
      case 5:
        // op: unorm
        return 12;
      case 6:
        // op: cpol
        return 7;
      case 7:
        // op: r128
        return 15;
      case 9:
        // op: tfe
        return 16;
      case 10:
        // op: lwe
        return 17;
      case 2:
        // op: srsrc
        return 48;
      case 1:
        // op: vaddr0
        return 32;
      case 4:
        // op: dim
        return 3;
      case 8:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V1_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_V1_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_V1_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_V1_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_V1_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_V2_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_V2_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_V2_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_V2_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_V3_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_V3_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_V3_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_V3_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_V4_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_V4_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_V4_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_V4_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_V5_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_V5_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_V5_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_V5_V4_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V1_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V2_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V3_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V4_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V1_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V2_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V3_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V4_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V1_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V2_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V3_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V4_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V1_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V2_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V3_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V4_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V1_V1_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V1_V2_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V1_V3_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V1_V4_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V2_V1_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V2_V2_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V2_V3_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V2_V4_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V3_V1_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V3_V2_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V3_V3_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V3_V4_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V4_V1_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V4_V2_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V4_V3_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V4_V4_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V5_V1_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V5_V2_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V5_V3_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V5_V4_gfx11:
    case AMDGPU::IMAGE_STORE_V1_V1_gfx11:
    case AMDGPU::IMAGE_STORE_V1_V2_gfx11:
    case AMDGPU::IMAGE_STORE_V1_V3_gfx11:
    case AMDGPU::IMAGE_STORE_V1_V4_gfx11:
    case AMDGPU::IMAGE_STORE_V2_V1_gfx11:
    case AMDGPU::IMAGE_STORE_V2_V2_gfx11:
    case AMDGPU::IMAGE_STORE_V2_V3_gfx11:
    case AMDGPU::IMAGE_STORE_V2_V4_gfx11:
    case AMDGPU::IMAGE_STORE_V3_V1_gfx11:
    case AMDGPU::IMAGE_STORE_V3_V2_gfx11:
    case AMDGPU::IMAGE_STORE_V3_V3_gfx11:
    case AMDGPU::IMAGE_STORE_V3_V4_gfx11:
    case AMDGPU::IMAGE_STORE_V4_V1_gfx11:
    case AMDGPU::IMAGE_STORE_V4_V2_gfx11:
    case AMDGPU::IMAGE_STORE_V4_V3_gfx11:
    case AMDGPU::IMAGE_STORE_V4_V4_gfx11:
    case AMDGPU::IMAGE_STORE_V5_V1_gfx11:
    case AMDGPU::IMAGE_STORE_V5_V2_gfx11:
    case AMDGPU::IMAGE_STORE_V5_V3_gfx11:
    case AMDGPU::IMAGE_STORE_V5_V4_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 3:
        // op: dmask
        return 8;
      case 5:
        // op: unorm
        return 7;
      case 6:
        // op: cpol
        return 12;
      case 7:
        // op: r128
        return 15;
      case 9:
        // op: tfe
        return 53;
      case 10:
        // op: lwe
        return 54;
      case 2:
        // op: srsrc
        return 48;
      case 11:
        // op: d16
        return 17;
      case 8:
        // op: a16
        return 16;
      case 1:
        // op: vaddr0
        return 32;
      case 4:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V4_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V1_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V2_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V3_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V4_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V1_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V2_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V3_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V4_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V1_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V2_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V3_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V4_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V1_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V2_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V3_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V4_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V1_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V2_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V3_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V4_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V1_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V2_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V3_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V4_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V1_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V1_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V1_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V1_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V1_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V2_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V3_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V4_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V1_V1_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V1_V2_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V1_V3_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V1_V4_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V2_V1_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V2_V2_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V2_V3_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V2_V4_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V3_V1_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V3_V2_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V3_V3_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V3_V4_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V4_V1_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V4_V2_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V4_V3_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V4_V4_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V5_V1_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V5_V2_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V5_V3_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V5_V4_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 3:
        // op: dmask
        return 8;
      case 5:
        // op: unorm
        return 7;
      case 6:
        // op: cpol
        return 12;
      case 7:
        // op: r128
        return 15;
      case 9:
        // op: tfe
        return 53;
      case 10:
        // op: lwe
        return 54;
      case 2:
        // op: srsrc
        return 48;
      case 8:
        // op: a16
        return 16;
      case 1:
        // op: vaddr0
        return 32;
      case 4:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::IMAGE_GATHER4H_V2_V1:
    case AMDGPU::IMAGE_GATHER4H_V2_V2:
    case AMDGPU::IMAGE_GATHER4H_V2_V3:
    case AMDGPU::IMAGE_GATHER4H_V2_V4:
    case AMDGPU::IMAGE_GATHER4H_V4_V1:
    case AMDGPU::IMAGE_GATHER4H_V4_V2:
    case AMDGPU::IMAGE_GATHER4H_V4_V3:
    case AMDGPU::IMAGE_GATHER4H_V4_V4:
    case AMDGPU::IMAGE_GATHER4H_V5_V1:
    case AMDGPU::IMAGE_GATHER4H_V5_V2:
    case AMDGPU::IMAGE_GATHER4H_V5_V3:
    case AMDGPU::IMAGE_GATHER4H_V5_V4:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V3:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V5:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V6:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V8:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V3:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V5:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V6:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V8:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V3:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V5:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V6:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V8:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V2:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V3:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V4:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V5:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V8:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V2:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V3:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V4:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V5:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V8:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V2:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V3:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V4:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V5:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V8:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V3:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V5:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V8:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V3:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V5:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V8:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V3:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V5:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V8:
    case AMDGPU::IMAGE_GATHER4_B_V2_V2:
    case AMDGPU::IMAGE_GATHER4_B_V2_V3:
    case AMDGPU::IMAGE_GATHER4_B_V2_V4:
    case AMDGPU::IMAGE_GATHER4_B_V4_V2:
    case AMDGPU::IMAGE_GATHER4_B_V4_V3:
    case AMDGPU::IMAGE_GATHER4_B_V4_V4:
    case AMDGPU::IMAGE_GATHER4_B_V5_V2:
    case AMDGPU::IMAGE_GATHER4_B_V5_V3:
    case AMDGPU::IMAGE_GATHER4_B_V5_V4:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V2:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V3:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V5:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V8:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V2:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V3:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V5:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V8:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V2:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V3:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V5:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V8:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V1:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V2:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V3:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V4:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V1:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V2:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V3:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V4:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V1:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V2:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V3:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V6:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V7:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V6:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V7:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V6:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V7:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V3:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V6:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V3:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V6:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V3:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V6:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V6:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V6:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V6:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V3:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V3:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V8:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V3:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V5:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V8:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V3:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V5:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V6:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V8:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V3:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V5:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V6:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V8:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V3:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V5:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V6:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V8:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V2:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V3:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V5:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V8:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V2:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V3:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V5:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V8:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V2:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V3:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V5:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V8:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V3:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V5:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V8:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V3:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V5:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V8:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V3:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V5:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V8:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V2:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V3:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V2:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V3:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V2:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V3:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V3:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V5:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V6:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V8:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V3:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V5:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V6:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V8:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V3:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V5:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V6:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V8:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V2:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V3:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V5:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V8:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V2:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V3:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V5:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V8:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V2:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V3:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V5:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V8:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V3:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V5:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V8:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V3:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V5:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V8:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V3:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V5:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V8:
    case AMDGPU::IMAGE_GATHER4_C_V2_V2:
    case AMDGPU::IMAGE_GATHER4_C_V2_V3:
    case AMDGPU::IMAGE_GATHER4_C_V2_V4:
    case AMDGPU::IMAGE_GATHER4_C_V4_V2:
    case AMDGPU::IMAGE_GATHER4_C_V4_V3:
    case AMDGPU::IMAGE_GATHER4_C_V4_V4:
    case AMDGPU::IMAGE_GATHER4_C_V5_V2:
    case AMDGPU::IMAGE_GATHER4_C_V5_V3:
    case AMDGPU::IMAGE_GATHER4_C_V5_V4:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V2:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V3:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V2:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V3:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V2:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V3:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V1:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V2:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V3:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V4:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V1:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V2:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V3:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V4:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V1:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V2:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V3:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V4:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V2:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V3:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V5:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V8:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V2:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V3:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V5:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V8:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V2:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V3:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V5:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V8:
    case AMDGPU::IMAGE_GATHER4_L_V2_V1:
    case AMDGPU::IMAGE_GATHER4_L_V2_V2:
    case AMDGPU::IMAGE_GATHER4_L_V2_V3:
    case AMDGPU::IMAGE_GATHER4_L_V2_V4:
    case AMDGPU::IMAGE_GATHER4_L_V4_V1:
    case AMDGPU::IMAGE_GATHER4_L_V4_V2:
    case AMDGPU::IMAGE_GATHER4_L_V4_V3:
    case AMDGPU::IMAGE_GATHER4_L_V4_V4:
    case AMDGPU::IMAGE_GATHER4_L_V5_V1:
    case AMDGPU::IMAGE_GATHER4_L_V5_V2:
    case AMDGPU::IMAGE_GATHER4_L_V5_V3:
    case AMDGPU::IMAGE_GATHER4_L_V5_V4:
    case AMDGPU::IMAGE_GATHER4_O_V2_V2:
    case AMDGPU::IMAGE_GATHER4_O_V2_V3:
    case AMDGPU::IMAGE_GATHER4_O_V2_V4:
    case AMDGPU::IMAGE_GATHER4_O_V4_V2:
    case AMDGPU::IMAGE_GATHER4_O_V4_V3:
    case AMDGPU::IMAGE_GATHER4_O_V4_V4:
    case AMDGPU::IMAGE_GATHER4_O_V5_V2:
    case AMDGPU::IMAGE_GATHER4_O_V5_V3:
    case AMDGPU::IMAGE_GATHER4_O_V5_V4:
    case AMDGPU::IMAGE_GATHER4_V2_V1:
    case AMDGPU::IMAGE_GATHER4_V2_V2:
    case AMDGPU::IMAGE_GATHER4_V2_V3:
    case AMDGPU::IMAGE_GATHER4_V2_V4:
    case AMDGPU::IMAGE_GATHER4_V4_V1:
    case AMDGPU::IMAGE_GATHER4_V4_V2:
    case AMDGPU::IMAGE_GATHER4_V4_V3:
    case AMDGPU::IMAGE_GATHER4_V4_V4:
    case AMDGPU::IMAGE_GATHER4_V5_V1:
    case AMDGPU::IMAGE_GATHER4_V5_V2:
    case AMDGPU::IMAGE_GATHER4_V5_V3:
    case AMDGPU::IMAGE_GATHER4_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V11:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V11:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V11:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V11:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V11:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V1:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V1:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V1:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V1:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V1:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V12:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V12:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V12:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V12:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V12:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V11:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V6:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V7:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V9:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V6:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V7:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V9:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V6:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V7:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V9:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V6:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V7:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V9:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V6:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V7:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V9:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V1:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V1:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V1:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V1:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V1:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V5:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V8:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V5:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V8:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V5:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V8:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V5:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V8:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V5:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V8:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V1:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V1:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V1:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V1:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V1:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V4:
    case AMDGPU::IMAGE_SAMPLE_V1_V1:
    case AMDGPU::IMAGE_SAMPLE_V1_V2:
    case AMDGPU::IMAGE_SAMPLE_V1_V3:
    case AMDGPU::IMAGE_SAMPLE_V1_V4:
    case AMDGPU::IMAGE_SAMPLE_V2_V1:
    case AMDGPU::IMAGE_SAMPLE_V2_V2:
    case AMDGPU::IMAGE_SAMPLE_V2_V3:
    case AMDGPU::IMAGE_SAMPLE_V2_V4:
    case AMDGPU::IMAGE_SAMPLE_V3_V1:
    case AMDGPU::IMAGE_SAMPLE_V3_V2:
    case AMDGPU::IMAGE_SAMPLE_V3_V3:
    case AMDGPU::IMAGE_SAMPLE_V3_V4:
    case AMDGPU::IMAGE_SAMPLE_V4_V1:
    case AMDGPU::IMAGE_SAMPLE_V4_V2:
    case AMDGPU::IMAGE_SAMPLE_V4_V3:
    case AMDGPU::IMAGE_SAMPLE_V4_V4:
    case AMDGPU::IMAGE_SAMPLE_V5_V1:
    case AMDGPU::IMAGE_SAMPLE_V5_V2:
    case AMDGPU::IMAGE_SAMPLE_V5_V3:
    case AMDGPU::IMAGE_SAMPLE_V5_V4: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 4:
        // op: dmask
        return 8;
      case 5:
        // op: unorm
        return 12;
      case 6:
        // op: cpol
        return 7;
      case 7:
        // op: r128
        return 15;
      case 8:
        // op: tfe
        return 16;
      case 9:
        // op: lwe
        return 17;
      case 11:
        // op: d16
        return 63;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: ssamp
        return 53;
      case 1:
        // op: vaddr
        return 32;
      case 10:
        // op: da
        return 14;
      }
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V1:
    case AMDGPU::IMAGE_GET_LOD_V1_V2:
    case AMDGPU::IMAGE_GET_LOD_V1_V3:
    case AMDGPU::IMAGE_GET_LOD_V1_V4:
    case AMDGPU::IMAGE_GET_LOD_V2_V1:
    case AMDGPU::IMAGE_GET_LOD_V2_V2:
    case AMDGPU::IMAGE_GET_LOD_V2_V3:
    case AMDGPU::IMAGE_GET_LOD_V2_V4:
    case AMDGPU::IMAGE_GET_LOD_V3_V1:
    case AMDGPU::IMAGE_GET_LOD_V3_V2:
    case AMDGPU::IMAGE_GET_LOD_V3_V3:
    case AMDGPU::IMAGE_GET_LOD_V3_V4:
    case AMDGPU::IMAGE_GET_LOD_V4_V1:
    case AMDGPU::IMAGE_GET_LOD_V4_V2:
    case AMDGPU::IMAGE_GET_LOD_V4_V3:
    case AMDGPU::IMAGE_GET_LOD_V4_V4:
    case AMDGPU::IMAGE_GET_LOD_V5_V1:
    case AMDGPU::IMAGE_GET_LOD_V5_V2:
    case AMDGPU::IMAGE_GET_LOD_V5_V3:
    case AMDGPU::IMAGE_GET_LOD_V5_V4: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 4:
        // op: dmask
        return 8;
      case 5:
        // op: unorm
        return 12;
      case 6:
        // op: cpol
        return 7;
      case 7:
        // op: r128
        return 15;
      case 8:
        // op: tfe
        return 16;
      case 9:
        // op: lwe
        return 17;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: ssamp
        return 53;
      case 1:
        // op: vaddr
        return 32;
      case 10:
        // op: da
        return 14;
      }
      break;
    }
    case AMDGPU::IMAGE_GATHER4H_V2_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V4_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V5_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V7_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V7_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V7_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V2_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V4_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V5_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_V2_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_V2_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_V2_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_V2_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_V4_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_V4_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_V4_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_V4_V4_gfx10:
    case AMDGPU::IMAGE_GATHER4_V5_V1_gfx10:
    case AMDGPU::IMAGE_GATHER4_V5_V2_gfx10:
    case AMDGPU::IMAGE_GATHER4_V5_V3_gfx10:
    case AMDGPU::IMAGE_GATHER4_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V1_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V1_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V1_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V1_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V2_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V2_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V2_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V2_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V3_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V3_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V3_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V3_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V4_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V4_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V4_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V4_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V5_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V5_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V5_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V5_V4_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 4:
        // op: dmask
        return 8;
      case 6:
        // op: unorm
        return 12;
      case 7:
        // op: cpol
        return 7;
      case 8:
        // op: r128
        return 15;
      case 10:
        // op: tfe
        return 16;
      case 11:
        // op: lwe
        return 17;
      case 12:
        // op: d16
        return 63;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: ssamp
        return 53;
      case 1:
        // op: vaddr0
        return 32;
      case 5:
        // op: dim
        return 3;
      case 9:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V5_V2_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 4:
        // op: dmask
        return 8;
      case 6:
        // op: unorm
        return 12;
      case 7:
        // op: cpol
        return 7;
      case 8:
        // op: r128
        return 15;
      case 10:
        // op: tfe
        return 16;
      case 11:
        // op: lwe
        return 17;
      case 12:
        // op: d16
        return 63;
      case 3:
        // op: srsrc
        return 48;
      case 1:
        // op: vaddr0
        return 32;
      case 5:
        // op: dim
        return 3;
      case 9:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V1_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V1_V2_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V1_V3_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V1_V4_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V2_V1_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V2_V2_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V2_V3_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V2_V4_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V3_V1_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V3_V2_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V3_V3_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V3_V4_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V4_V1_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V4_V2_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V4_V3_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V4_V4_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V5_V1_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V5_V2_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V5_V3_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V5_V4_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 4:
        // op: dmask
        return 8;
      case 6:
        // op: unorm
        return 12;
      case 7:
        // op: cpol
        return 7;
      case 8:
        // op: r128
        return 15;
      case 10:
        // op: tfe
        return 16;
      case 11:
        // op: lwe
        return 17;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: ssamp
        return 53;
      case 1:
        // op: vaddr0
        return 32;
      case 5:
        // op: dim
        return 3;
      case 9:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V5_V2_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 4:
        // op: dmask
        return 8;
      case 6:
        // op: unorm
        return 12;
      case 7:
        // op: cpol
        return 7;
      case 8:
        // op: r128
        return 15;
      case 10:
        // op: tfe
        return 16;
      case 11:
        // op: lwe
        return 17;
      case 3:
        // op: srsrc
        return 48;
      case 1:
        // op: vaddr0
        return 32;
      case 5:
        // op: dim
        return 3;
      case 9:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_GATHER4H_V2_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V4_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V5_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V6_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V6_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V6_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V5_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V8_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V2_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V4_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V5_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_V2_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_V2_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_V2_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_V2_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_V4_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_V4_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_V4_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_V4_V4_gfx11:
    case AMDGPU::IMAGE_GATHER4_V5_V1_gfx11:
    case AMDGPU::IMAGE_GATHER4_V5_V2_gfx11:
    case AMDGPU::IMAGE_GATHER4_V5_V3_gfx11:
    case AMDGPU::IMAGE_GATHER4_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V12_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V12_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V12_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V12_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V12_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V1_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V1_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V1_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V1_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V2_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V2_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V2_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V2_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V3_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V3_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V3_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V3_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V4_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V4_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V4_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V4_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V5_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V5_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V5_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V5_V4_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 4:
        // op: dmask
        return 8;
      case 6:
        // op: unorm
        return 7;
      case 7:
        // op: cpol
        return 12;
      case 8:
        // op: r128
        return 15;
      case 10:
        // op: tfe
        return 53;
      case 11:
        // op: lwe
        return 54;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: ssamp
        return 58;
      case 12:
        // op: d16
        return 17;
      case 9:
        // op: a16
        return 16;
      case 1:
        // op: vaddr0
        return 32;
      case 5:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V1_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V1_V2_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V1_V3_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V1_V4_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V2_V1_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V2_V2_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V2_V3_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V2_V4_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V3_V1_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V3_V2_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V3_V3_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V3_V4_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V4_V1_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V4_V2_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V4_V3_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V4_V4_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V5_V1_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V5_V2_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V5_V3_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V5_V4_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 4:
        // op: dmask
        return 8;
      case 6:
        // op: unorm
        return 7;
      case 7:
        // op: cpol
        return 12;
      case 8:
        // op: r128
        return 15;
      case 10:
        // op: tfe
        return 53;
      case 11:
        // op: lwe
        return 54;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: ssamp
        return 58;
      case 9:
        // op: a16
        return 16;
      case 1:
        // op: vaddr0
        return 32;
      case 5:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V5_V2_nsa_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 4:
        // op: dmask
        return 8;
      case 6:
        // op: unorm
        return 7;
      case 7:
        // op: cpol
        return 12;
      case 8:
        // op: r128
        return 15;
      case 10:
        // op: tfe
        return 53;
      case 11:
        // op: lwe
        return 54;
      case 3:
        // op: srsrc
        return 48;
      case 12:
        // op: d16
        return 17;
      case 9:
        // op: a16
        return 16;
      case 1:
        // op: vaddr0
        return 32;
      case 5:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V5_V2_nsa_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 4:
        // op: dmask
        return 8;
      case 6:
        // op: unorm
        return 7;
      case 7:
        // op: cpol
        return 12;
      case 8:
        // op: r128
        return 15;
      case 10:
        // op: tfe
        return 53;
      case 11:
        // op: lwe
        return 54;
      case 3:
        // op: srsrc
        return 48;
      case 9:
        // op: a16
        return 16;
      case 1:
        // op: vaddr0
        return 32;
      case 5:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::IMAGE_GATHER4H_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V5_V2_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 5:
        // op: dmask
        return 8;
      case 7:
        // op: unorm
        return 12;
      case 8:
        // op: cpol
        return 7;
      case 9:
        // op: r128
        return 15;
      case 11:
        // op: tfe
        return 16;
      case 12:
        // op: lwe
        return 17;
      case 13:
        // op: d16
        return 63;
      case 3:
        // op: srsrc
        return 48;
      case 4:
        // op: ssamp
        return 53;
      case 1:
        // op: vaddr0
        return 32;
      case 6:
        // op: dim
        return 3;
      case 10:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V5_V3_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 5:
        // op: dmask
        return 8;
      case 7:
        // op: unorm
        return 12;
      case 8:
        // op: cpol
        return 7;
      case 9:
        // op: r128
        return 15;
      case 11:
        // op: tfe
        return 16;
      case 12:
        // op: lwe
        return 17;
      case 13:
        // op: d16
        return 63;
      case 4:
        // op: srsrc
        return 48;
      case 1:
        // op: vaddr0
        return 32;
      case 6:
        // op: dim
        return 3;
      case 10:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V5_V2_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 5:
        // op: dmask
        return 8;
      case 7:
        // op: unorm
        return 12;
      case 8:
        // op: cpol
        return 7;
      case 9:
        // op: r128
        return 15;
      case 11:
        // op: tfe
        return 16;
      case 12:
        // op: lwe
        return 17;
      case 3:
        // op: srsrc
        return 48;
      case 4:
        // op: ssamp
        return 53;
      case 1:
        // op: vaddr0
        return 32;
      case 6:
        // op: dim
        return 3;
      case 10:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V5_V3_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 5:
        // op: dmask
        return 8;
      case 7:
        // op: unorm
        return 12;
      case 8:
        // op: cpol
        return 7;
      case 9:
        // op: r128
        return 15;
      case 11:
        // op: tfe
        return 16;
      case 12:
        // op: lwe
        return 17;
      case 4:
        // op: srsrc
        return 48;
      case 1:
        // op: vaddr0
        return 32;
      case 6:
        // op: dim
        return 3;
      case 10:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V5_V2_nsa_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 5:
        // op: dmask
        return 8;
      case 7:
        // op: unorm
        return 7;
      case 8:
        // op: cpol
        return 12;
      case 9:
        // op: r128
        return 15;
      case 11:
        // op: tfe
        return 53;
      case 12:
        // op: lwe
        return 54;
      case 3:
        // op: srsrc
        return 48;
      case 4:
        // op: ssamp
        return 58;
      case 10:
        // op: a16
        return 16;
      case 1:
        // op: vaddr0
        return 32;
      case 6:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::IMAGE_GATHER4H_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V5_V2_nsa_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 5:
        // op: dmask
        return 8;
      case 7:
        // op: unorm
        return 7;
      case 8:
        // op: cpol
        return 12;
      case 9:
        // op: r128
        return 15;
      case 11:
        // op: tfe
        return 53;
      case 12:
        // op: lwe
        return 54;
      case 3:
        // op: srsrc
        return 48;
      case 4:
        // op: ssamp
        return 58;
      case 13:
        // op: d16
        return 17;
      case 10:
        // op: a16
        return 16;
      case 1:
        // op: vaddr0
        return 32;
      case 6:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V5_V3_nsa_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 5:
        // op: dmask
        return 8;
      case 7:
        // op: unorm
        return 7;
      case 8:
        // op: cpol
        return 12;
      case 9:
        // op: r128
        return 15;
      case 11:
        // op: tfe
        return 53;
      case 12:
        // op: lwe
        return 54;
      case 4:
        // op: srsrc
        return 48;
      case 10:
        // op: a16
        return 16;
      case 1:
        // op: vaddr0
        return 32;
      case 6:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V5_V3_nsa_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 5:
        // op: dmask
        return 8;
      case 7:
        // op: unorm
        return 7;
      case 8:
        // op: cpol
        return 12;
      case 9:
        // op: r128
        return 15;
      case 11:
        // op: tfe
        return 53;
      case 12:
        // op: lwe
        return 54;
      case 4:
        // op: srsrc
        return 48;
      case 13:
        // op: d16
        return 17;
      case 10:
        // op: a16
        return 16;
      case 1:
        // op: vaddr0
        return 32;
      case 6:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_nsa_gfx11:
    case AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_nsa_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 5:
        // op: srsrc
        return 48;
      case 1:
        // op: vaddr0
        return 32;
      }
      break;
    }
    case AMDGPU::IMAGE_GATHER4H_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4H_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_V5_V3_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 6:
        // op: dmask
        return 8;
      case 8:
        // op: unorm
        return 12;
      case 9:
        // op: cpol
        return 7;
      case 10:
        // op: r128
        return 15;
      case 12:
        // op: tfe
        return 16;
      case 13:
        // op: lwe
        return 17;
      case 14:
        // op: d16
        return 63;
      case 4:
        // op: srsrc
        return 48;
      case 5:
        // op: ssamp
        return 53;
      case 1:
        // op: vaddr0
        return 32;
      case 7:
        // op: dim
        return 3;
      case 11:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_MSAA_LOAD_X_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_V5_V4_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 6:
        // op: dmask
        return 8;
      case 8:
        // op: unorm
        return 12;
      case 9:
        // op: cpol
        return 7;
      case 10:
        // op: r128
        return 15;
      case 12:
        // op: tfe
        return 16;
      case 13:
        // op: lwe
        return 17;
      case 14:
        // op: d16
        return 63;
      case 5:
        // op: srsrc
        return 48;
      case 1:
        // op: vaddr0
        return 32;
      case 7:
        // op: dim
        return 3;
      case 11:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_GET_LOD_V5_V3_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 6:
        // op: dmask
        return 8;
      case 8:
        // op: unorm
        return 12;
      case 9:
        // op: cpol
        return 7;
      case 10:
        // op: r128
        return 15;
      case 12:
        // op: tfe
        return 16;
      case 13:
        // op: lwe
        return 17;
      case 4:
        // op: srsrc
        return 48;
      case 5:
        // op: ssamp
        return 53;
      case 1:
        // op: vaddr0
        return 32;
      case 7:
        // op: dim
        return 3;
      case 11:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_NORTN_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_STORE_PCK_V5_V4_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 6:
        // op: dmask
        return 8;
      case 8:
        // op: unorm
        return 12;
      case 9:
        // op: cpol
        return 7;
      case 10:
        // op: r128
        return 15;
      case 12:
        // op: tfe
        return 16;
      case 13:
        // op: lwe
        return 17;
      case 5:
        // op: srsrc
        return 48;
      case 1:
        // op: vaddr0
        return 32;
      case 7:
        // op: dim
        return 3;
      case 11:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GET_LOD_V5_V3_nsa_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 6:
        // op: dmask
        return 8;
      case 8:
        // op: unorm
        return 7;
      case 9:
        // op: cpol
        return 12;
      case 10:
        // op: r128
        return 15;
      case 12:
        // op: tfe
        return 53;
      case 13:
        // op: lwe
        return 54;
      case 4:
        // op: srsrc
        return 48;
      case 5:
        // op: ssamp
        return 58;
      case 11:
        // op: a16
        return 16;
      case 1:
        // op: vaddr0
        return 32;
      case 7:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::IMAGE_GATHER4H_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4H_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_V5_V3_nsa_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 6:
        // op: dmask
        return 8;
      case 8:
        // op: unorm
        return 7;
      case 9:
        // op: cpol
        return 12;
      case 10:
        // op: r128
        return 15;
      case 12:
        // op: tfe
        return 53;
      case 13:
        // op: lwe
        return 54;
      case 4:
        // op: srsrc
        return 48;
      case 5:
        // op: ssamp
        return 58;
      case 14:
        // op: d16
        return 17;
      case 11:
        // op: a16
        return 16;
      case 1:
        // op: vaddr0
        return 32;
      case 7:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_PCK_V5_V4_nsa_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 6:
        // op: dmask
        return 8;
      case 8:
        // op: unorm
        return 7;
      case 9:
        // op: cpol
        return 12;
      case 10:
        // op: r128
        return 15;
      case 12:
        // op: tfe
        return 53;
      case 13:
        // op: lwe
        return 54;
      case 5:
        // op: srsrc
        return 48;
      case 11:
        // op: a16
        return 16;
      case 1:
        // op: vaddr0
        return 32;
      case 7:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_LOAD_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_MIP_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_STORE_V5_V4_nsa_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 6:
        // op: dmask
        return 8;
      case 8:
        // op: unorm
        return 7;
      case 9:
        // op: cpol
        return 12;
      case 10:
        // op: r128
        return 15;
      case 12:
        // op: tfe
        return 53;
      case 13:
        // op: lwe
        return 54;
      case 5:
        // op: srsrc
        return 48;
      case 14:
        // op: d16
        return 17;
      case 11:
        // op: a16
        return 16;
      case 1:
        // op: vaddr0
        return 32;
      case 7:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_nsa_gfx11:
    case AMDGPU::IMAGE_BVH_INTERSECT_RAY_nsa_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 6:
        // op: srsrc
        return 48;
      case 1:
        // op: vaddr0
        return 32;
      }
      break;
    }
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V4_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 7:
        // op: dmask
        return 8;
      case 9:
        // op: unorm
        return 12;
      case 10:
        // op: cpol
        return 7;
      case 11:
        // op: r128
        return 15;
      case 13:
        // op: tfe
        return 16;
      case 14:
        // op: lwe
        return 17;
      case 15:
        // op: d16
        return 63;
      case 5:
        // op: srsrc
        return 48;
      case 6:
        // op: ssamp
        return 53;
      case 1:
        // op: vaddr0
        return 32;
      case 8:
        // op: dim
        return 3;
      case 12:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_L_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V4_nsa_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 7:
        // op: dmask
        return 8;
      case 9:
        // op: unorm
        return 7;
      case 10:
        // op: cpol
        return 12;
      case 11:
        // op: r128
        return 15;
      case 13:
        // op: tfe
        return 53;
      case 14:
        // op: lwe
        return 54;
      case 5:
        // op: srsrc
        return 48;
      case 6:
        // op: ssamp
        return 58;
      case 15:
        // op: d16
        return 17;
      case 12:
        // op: a16
        return 16;
      case 1:
        // op: vaddr0
        return 32;
      case 8:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_L_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V5_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 8:
        // op: dmask
        return 8;
      case 10:
        // op: unorm
        return 12;
      case 11:
        // op: cpol
        return 7;
      case 12:
        // op: r128
        return 15;
      case 14:
        // op: tfe
        return 16;
      case 15:
        // op: lwe
        return 17;
      case 16:
        // op: d16
        return 63;
      case 6:
        // op: srsrc
        return 48;
      case 7:
        // op: ssamp
        return 53;
      case 1:
        // op: vaddr0
        return 32;
      case 9:
        // op: dim
        return 3;
      case 13:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V12_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V12_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V12_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V12_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V12_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V5_nsa_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 8:
        // op: dmask
        return 8;
      case 10:
        // op: unorm
        return 7;
      case 11:
        // op: cpol
        return 12;
      case 12:
        // op: r128
        return 15;
      case 14:
        // op: tfe
        return 53;
      case 15:
        // op: lwe
        return 54;
      case 6:
        // op: srsrc
        return 48;
      case 7:
        // op: ssamp
        return 58;
      case 16:
        // op: d16
        return 17;
      case 13:
        // op: a16
        return 16;
      case 1:
        // op: vaddr0
        return 32;
      case 9:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_B_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_GATHER4_C_L_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V6_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 9:
        // op: dmask
        return 8;
      case 11:
        // op: unorm
        return 12;
      case 12:
        // op: cpol
        return 7;
      case 13:
        // op: r128
        return 15;
      case 15:
        // op: tfe
        return 16;
      case 16:
        // op: lwe
        return 17;
      case 17:
        // op: d16
        return 63;
      case 7:
        // op: srsrc
        return 48;
      case 8:
        // op: ssamp
        return 53;
      case 1:
        // op: vaddr0
        return 32;
      case 10:
        // op: dim
        return 3;
      case 14:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_nsa_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdata
        return 40;
      case 9:
        // op: srsrc
        return 48;
      case 1:
        // op: vaddr0
        return 32;
      }
      break;
    }
    case AMDGPU::V_SMFMAC_F32_16X16X128_BF8_BF8_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X128_BF8_FP8_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X128_FP8_BF8_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X128_FP8_FP8_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X32_BF16_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X32_F16_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X64_BF16_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X64_F16_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940:
    case AMDGPU::V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X16_BF16_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X16_F16_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X32_BF16_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X32_F16_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X64_BF8_BF8_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X64_BF8_FP8_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X64_FP8_BF8_gfx940:
    case AMDGPU::V_SMFMAC_F32_32X32X64_FP8_FP8_gfx940:
    case AMDGPU::V_SMFMAC_I32_16X16X128_I8_gfx940:
    case AMDGPU::V_SMFMAC_I32_16X16X64_I8_gfx940:
    case AMDGPU::V_SMFMAC_I32_32X32X32_I8_gfx940:
    case AMDGPU::V_SMFMAC_I32_32X32X64_I8_gfx940: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1
        return 41;
      case 3:
        // op: idx
        return 50;
      case 4:
        // op: cbsz
        return 8;
      case 5:
        // op: abid
        return 11;
      }
      break;
    }
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1
        return 41;
      case 3:
        // op: src2
        return 50;
      case 5:
        // op: blgp
        return 61;
      case 4:
        // op: cbsz
        return 8;
      }
      break;
    }
    case AMDGPU::V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_16X16X16BF16_1K_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X16F16_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_16X16X16F16_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_16X16X16F16_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X16F16_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X16F16_vi:
    case AMDGPU::V_MFMA_F32_16X16X1F32_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_16X16X1F32_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_16X16X1F32_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X1F32_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X1F32_vi:
    case AMDGPU::V_MFMA_F32_16X16X2BF16_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_16X16X2BF16_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_16X16X2BF16_vi:
    case AMDGPU::V_MFMA_F32_16X16X32_BF16_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X32_BF16_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X32_F16_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X32_F16_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_16X16X4BF16_1K_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X4F16_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_16X16X4F16_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_16X16X4F16_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X4F16_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X4F16_vi:
    case AMDGPU::V_MFMA_F32_16X16X4F32_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_16X16X4F32_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_16X16X4F32_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X4F32_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_16X16X4F32_vi:
    case AMDGPU::V_MFMA_F32_16X16X8BF16_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_16X16X8BF16_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_16X16X8BF16_vi:
    case AMDGPU::V_MFMA_F32_16X16X8XF32_gfx940_acd:
    case AMDGPU::V_MFMA_F32_16X16X8XF32_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X16_BF16_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X16_BF16_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X16_F16_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X16_F16_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X1F32_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_32X32X1F32_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_32X32X1F32_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X1F32_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X1F32_vi:
    case AMDGPU::V_MFMA_F32_32X32X2BF16_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_32X32X2BF16_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_32X32X2BF16_vi:
    case AMDGPU::V_MFMA_F32_32X32X2F32_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_32X32X2F32_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_32X32X2F32_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X2F32_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X2F32_vi:
    case AMDGPU::V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_32X32X4BF16_1K_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X4BF16_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_32X32X4BF16_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_32X32X4BF16_vi:
    case AMDGPU::V_MFMA_F32_32X32X4F16_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_32X32X4F16_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_32X32X4F16_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X4F16_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X4F16_vi:
    case AMDGPU::V_MFMA_F32_32X32X4XF32_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X4XF32_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_32X32X8BF16_1K_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X8F16_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_32X32X8F16_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_32X32X8F16_gfx940_acd:
    case AMDGPU::V_MFMA_F32_32X32X8F16_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_32X32X8F16_vi:
    case AMDGPU::V_MFMA_F32_4X4X1F32_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_4X4X1F32_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_4X4X1F32_gfx940_acd:
    case AMDGPU::V_MFMA_F32_4X4X1F32_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_4X4X1F32_vi:
    case AMDGPU::V_MFMA_F32_4X4X2BF16_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_4X4X2BF16_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_4X4X2BF16_vi:
    case AMDGPU::V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_4X4X4BF16_1K_gfx940_acd:
    case AMDGPU::V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_4X4X4F16_gfx90a_acd:
    case AMDGPU::V_MFMA_F32_4X4X4F16_gfx90a_vcd:
    case AMDGPU::V_MFMA_F32_4X4X4F16_gfx940_acd:
    case AMDGPU::V_MFMA_F32_4X4X4F16_gfx940_vcd:
    case AMDGPU::V_MFMA_F32_4X4X4F16_vi:
    case AMDGPU::V_MFMA_F64_16X16X4F64_gfx90a_acd:
    case AMDGPU::V_MFMA_F64_16X16X4F64_gfx90a_vcd:
    case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:
    case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:
    case AMDGPU::V_MFMA_F64_4X4X4F64_gfx90a_acd:
    case AMDGPU::V_MFMA_F64_4X4X4F64_gfx90a_vcd:
    case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:
    case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:
    case AMDGPU::V_MFMA_I32_16X16X16I8_gfx90a_acd:
    case AMDGPU::V_MFMA_I32_16X16X16I8_gfx90a_vcd:
    case AMDGPU::V_MFMA_I32_16X16X16I8_vi:
    case AMDGPU::V_MFMA_I32_16X16X32I8_gfx940_acd:
    case AMDGPU::V_MFMA_I32_16X16X32I8_gfx940_vcd:
    case AMDGPU::V_MFMA_I32_16X16X4I8_gfx90a_acd:
    case AMDGPU::V_MFMA_I32_16X16X4I8_gfx90a_vcd:
    case AMDGPU::V_MFMA_I32_16X16X4I8_gfx940_acd:
    case AMDGPU::V_MFMA_I32_16X16X4I8_gfx940_vcd:
    case AMDGPU::V_MFMA_I32_16X16X4I8_vi:
    case AMDGPU::V_MFMA_I32_16X16X64_I8_gfx940_acd:
    case AMDGPU::V_MFMA_I32_16X16X64_I8_gfx940_vcd:
    case AMDGPU::V_MFMA_I32_32X32X16I8_gfx940_acd:
    case AMDGPU::V_MFMA_I32_32X32X16I8_gfx940_vcd:
    case AMDGPU::V_MFMA_I32_32X32X32_I8_gfx940_acd:
    case AMDGPU::V_MFMA_I32_32X32X32_I8_gfx940_vcd:
    case AMDGPU::V_MFMA_I32_32X32X4I8_gfx90a_acd:
    case AMDGPU::V_MFMA_I32_32X32X4I8_gfx90a_vcd:
    case AMDGPU::V_MFMA_I32_32X32X4I8_gfx940_acd:
    case AMDGPU::V_MFMA_I32_32X32X4I8_gfx940_vcd:
    case AMDGPU::V_MFMA_I32_32X32X4I8_vi:
    case AMDGPU::V_MFMA_I32_32X32X8I8_gfx90a_acd:
    case AMDGPU::V_MFMA_I32_32X32X8I8_gfx90a_vcd:
    case AMDGPU::V_MFMA_I32_32X32X8I8_vi:
    case AMDGPU::V_MFMA_I32_4X4X4I8_gfx90a_acd:
    case AMDGPU::V_MFMA_I32_4X4X4I8_gfx90a_vcd:
    case AMDGPU::V_MFMA_I32_4X4X4I8_gfx940_acd:
    case AMDGPU::V_MFMA_I32_4X4X4I8_gfx940_vcd:
    case AMDGPU::V_MFMA_I32_4X4X4I8_vi: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1
        return 41;
      case 3:
        // op: src2
        return 50;
      case 6:
        // op: blgp
        return 61;
      case 4:
        // op: cbsz
        return 8;
      case 5:
        // op: abid
        return 11;
      }
      break;
    }
    case AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_gfx1250: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1
        return 41;
      case 3:
        // op: src2_modifiers
        return 10;
      case 4:
        // op: src2
        return 50;
      case 5:
        // op: matrix_a_fmt
        return 11;
      case 6:
        // op: matrix_b_fmt
        return 14;
      }
      break;
    }
    case AMDGPU::V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_gfx1250: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1
        return 41;
      case 3:
        // op: src2_modifiers
        return 10;
      case 4:
        // op: src2
        return 50;
      case 5:
        // op: matrix_a_reuse
        return 13;
      case 6:
        // op: matrix_b_reuse
        return 14;
      }
      break;
    }
    case AMDGPU::V_DOT4_F32_BF8_BF8_gfx12:
    case AMDGPU::V_DOT4_F32_BF8_FP8_gfx12:
    case AMDGPU::V_DOT4_F32_FP8_BF8_gfx12:
    case AMDGPU::V_DOT4_F32_FP8_FP8_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w64_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w64_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w64_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w64_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_32X16X128_F4_w32_twoaddr_gfx1250: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1
        return 41;
      case 3:
        // op: src2_modifiers
        return 10;
      case 4:
        // op: src2
        return 50;
      }
      break;
    }
    case AMDGPU::V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1
        return 41;
      case 4:
        // op: src2
        return 50;
      case 5:
        // op: index_key_16bit
        return 11;
      }
      break;
    }
    case AMDGPU::V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1
        return 41;
      case 4:
        // op: src2
        return 50;
      case 5:
        // op: index_key_32bit
        return 11;
      case 6:
        // op: matrix_a_reuse
        return 13;
      case 7:
        // op: matrix_b_reuse
        return 14;
      }
      break;
    }
    case AMDGPU::V_SWMMAC_F32_16X16X32_BF8_BF8_w64_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F32_16X16X32_BF8_FP8_w64_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F32_16X16X32_FP8_BF8_w64_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F32_16X16X32_FP8_FP8_w64_twoaddr_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1
        return 41;
      case 4:
        // op: src2
        return 50;
      case 5:
        // op: index_key_8bit
        return 11;
      }
      break;
    }
    case AMDGPU::V_ACCVGPR_READ_B32_vi:
    case AMDGPU::V_ACCVGPR_WRITE_B32_vi: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0
        return 32;
      }
      break;
    }
    case AMDGPU::V_INTERP_P10_F32_inreg_gfx11:
    case AMDGPU::V_INTERP_P10_F32_inreg_gfx12:
    case AMDGPU::V_INTERP_P2_F32_inreg_gfx11:
    case AMDGPU::V_INTERP_P2_F32_inreg_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 11;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 12;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2_modifiers
        return 13;
      case 6:
        // op: src2
        return 50;
      case 7:
        // op: clamp
        return 15;
      case 8:
        // op: waitexp
        return 8;
      }
      break;
    }
    case AMDGPU::V_INTERP_P10_F16_F32_inreg_fake16_gfx11:
    case AMDGPU::V_INTERP_P10_F16_F32_inreg_fake16_gfx12:
    case AMDGPU::V_INTERP_P10_F16_F32_inreg_t16_gfx11:
    case AMDGPU::V_INTERP_P10_F16_F32_inreg_t16_gfx12:
    case AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_fake16_gfx11:
    case AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_fake16_gfx12:
    case AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_t16_gfx11:
    case AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_t16_gfx12:
    case AMDGPU::V_INTERP_P2_F16_F32_inreg_fake16_gfx11:
    case AMDGPU::V_INTERP_P2_F16_F32_inreg_fake16_gfx12:
    case AMDGPU::V_INTERP_P2_F16_F32_inreg_t16_gfx11:
    case AMDGPU::V_INTERP_P2_F16_F32_inreg_t16_gfx12:
    case AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_fake16_gfx11:
    case AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_fake16_gfx12:
    case AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_t16_gfx11:
    case AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_t16_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 11;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 12;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2_modifiers
        return 13;
      case 6:
        // op: src2
        return 50;
      case 7:
        // op: clamp
        return 15;
      case 9:
        // op: waitexp
        return 8;
      }
      break;
    }
    case AMDGPU::V_WMMA_I32_16X16X64_IU8_w32_twoaddr_gfx1250: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 61;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 62;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2
        return 50;
      case 6:
        // op: clamp
        return 15;
      case 7:
        // op: matrix_a_reuse
        return 13;
      case 8:
        // op: matrix_b_reuse
        return 14;
      }
      break;
    }
    case AMDGPU::V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx12:
    case AMDGPU::V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx12:
    case AMDGPU::V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 61;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 62;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2
        return 50;
      case 6:
        // op: clamp
        return 15;
      }
      break;
    }
    case AMDGPU::V_WMMA_F32_16X16X4_F32_w32_twoaddr_gfx1250: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 61;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 62;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2_modifiers
        return 10;
      case 6:
        // op: src2
        return 50;
      case 7:
        // op: matrix_a_reuse
        return 13;
      case 8:
        // op: matrix_b_reuse
        return 14;
      }
      break;
    }
    case AMDGPU::V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 61;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 62;
      case 4:
        // op: src1
        return 41;
      case 6:
        // op: src2
        return 50;
      case 7:
        // op: clamp
        return 15;
      }
      break;
    }
    case AMDGPU::V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 61;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 62;
      case 4:
        // op: src1
        return 41;
      case 6:
        // op: src2
        return 50;
      case 8:
        // op: clamp
        return 15;
      case 7:
        // op: index_key_16bit
        return 11;
      }
      break;
    }
    case AMDGPU::V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_gfx1250: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 61;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 62;
      case 4:
        // op: src1
        return 41;
      case 6:
        // op: src2
        return 50;
      case 8:
        // op: clamp
        return 15;
      case 7:
        // op: index_key_32bit
        return 11;
      case 9:
        // op: matrix_a_reuse
        return 13;
      case 10:
        // op: matrix_b_reuse
        return 14;
      }
      break;
    }
    case AMDGPU::V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 61;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 62;
      case 4:
        // op: src1
        return 41;
      case 6:
        // op: src2
        return 50;
      case 8:
        // op: clamp
        return 15;
      case 7:
        // op: index_key_8bit
        return 11;
      }
      break;
    }
    case AMDGPU::V_CEIL_F16_t16_e64_gfx11:
    case AMDGPU::V_CEIL_F16_t16_e64_gfx12:
    case AMDGPU::V_COS_F16V_COS_F16_t16_e64_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_t16_e64_gfx12:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_e64_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_e64_gfx12:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_e64_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_e64_gfx12:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_e64_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_e64_gfx12:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_e64_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_e64_gfx12:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_e64_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_e64_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e64_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e64_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e64_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e64_gfx12:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_e64_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_e64_gfx12:
    case AMDGPU::V_EXP_F16_t16_e64_gfx11:
    case AMDGPU::V_EXP_F16_t16_e64_gfx12:
    case AMDGPU::V_FLOOR_F16_t16_e64_gfx11:
    case AMDGPU::V_FLOOR_F16_t16_e64_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_e64_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_e64_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e64_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e64_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e64_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e64_gfx12:
    case AMDGPU::V_LOG_F16_t16_e64_gfx11:
    case AMDGPU::V_LOG_F16_t16_e64_gfx12:
    case AMDGPU::V_RCP_F16_t16_e64_gfx11:
    case AMDGPU::V_RCP_F16_t16_e64_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_e64_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_e64_gfx12:
    case AMDGPU::V_RSQ_F16_t16_e64_gfx11:
    case AMDGPU::V_RSQ_F16_t16_e64_gfx12:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_e64_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_e64_gfx12:
    case AMDGPU::V_SQRT_F16_t16_e64_gfx11:
    case AMDGPU::V_SQRT_F16_t16_e64_gfx12:
    case AMDGPU::V_TANH_F16V_TANH_F16_t16_e64_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_e64_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_e64_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: clamp
        return 15;
      case 4:
        // op: omod
        return 59;
      }
      break;
    }
    case AMDGPU::V_CVT_PK_BF8_F16_gfx1250_t16_e64_gfx1250:
    case AMDGPU::V_CVT_PK_FP8_F16_gfx1250_t16_e64_gfx1250: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: clamp
        return 15;
      }
      break;
    }
    case AMDGPU::V_ADD_F16_t16_e64_gfx11:
    case AMDGPU::V_ADD_F16_t16_e64_gfx12:
    case AMDGPU::V_LDEXP_F16_t16_e64_gfx11:
    case AMDGPU::V_LDEXP_F16_t16_e64_gfx12:
    case AMDGPU::V_MAXIMUM_F16_t16_e64_gfx12:
    case AMDGPU::V_MAX_F16V_MAX_F16_t16_e64_gfx11:
    case AMDGPU::V_MAX_NUM_F16_t16_e64_gfx12:
    case AMDGPU::V_MINIMUM_F16_t16_e64_gfx12:
    case AMDGPU::V_MIN_F16V_MIN_F16_t16_e64_gfx11:
    case AMDGPU::V_MIN_NUM_F16_t16_e64_gfx12:
    case AMDGPU::V_MUL_F16_t16_e64_gfx11:
    case AMDGPU::V_MUL_F16_t16_e64_gfx12:
    case AMDGPU::V_SUBREV_F16_t16_e64_gfx11:
    case AMDGPU::V_SUBREV_F16_t16_e64_gfx12:
    case AMDGPU::V_SUB_F16_t16_e64_gfx11:
    case AMDGPU::V_SUB_F16_t16_e64_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: clamp
        return 15;
      case 6:
        // op: omod
        return 59;
      }
      break;
    }
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_t16_e64_gfx11:
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_t16_e64_gfx12:
    case AMDGPU::V_ADD_NC_U16_t16_e64_gfx11:
    case AMDGPU::V_ADD_NC_U16_t16_e64_gfx12:
    case AMDGPU::V_CVT_PK_FP8_F32_gfx1250_t16_e64_gfx1250:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_t16_e64_gfx11:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_t16_e64_gfx12:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_t16_e64_gfx11:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_t16_e64_gfx12:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_t16_e64_gfx11:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_t16_e64_gfx12:
    case AMDGPU::V_PK_ADD_BF16_gfx1250:
    case AMDGPU::V_PK_ADD_F16_gfx10:
    case AMDGPU::V_PK_ADD_F16_gfx11:
    case AMDGPU::V_PK_ADD_F16_gfx12:
    case AMDGPU::V_PK_ADD_F16_vi:
    case AMDGPU::V_PK_ADD_F32_gfx12:
    case AMDGPU::V_PK_ADD_F32_vi:
    case AMDGPU::V_PK_ADD_I16_gfx10:
    case AMDGPU::V_PK_ADD_I16_gfx11:
    case AMDGPU::V_PK_ADD_I16_gfx12:
    case AMDGPU::V_PK_ADD_I16_vi:
    case AMDGPU::V_PK_ADD_U16_gfx10:
    case AMDGPU::V_PK_ADD_U16_gfx11:
    case AMDGPU::V_PK_ADD_U16_gfx12:
    case AMDGPU::V_PK_ADD_U16_vi:
    case AMDGPU::V_PK_ASHRREV_I16_gfx10:
    case AMDGPU::V_PK_ASHRREV_I16_gfx11:
    case AMDGPU::V_PK_ASHRREV_I16_gfx12:
    case AMDGPU::V_PK_ASHRREV_I16_vi:
    case AMDGPU::V_PK_LSHLREV_B16_gfx10:
    case AMDGPU::V_PK_LSHLREV_B16_gfx11:
    case AMDGPU::V_PK_LSHLREV_B16_gfx12:
    case AMDGPU::V_PK_LSHLREV_B16_vi:
    case AMDGPU::V_PK_LSHRREV_B16_gfx10:
    case AMDGPU::V_PK_LSHRREV_B16_gfx11:
    case AMDGPU::V_PK_LSHRREV_B16_gfx12:
    case AMDGPU::V_PK_LSHRREV_B16_vi:
    case AMDGPU::V_PK_MAXIMUM_F16_gfx12:
    case AMDGPU::V_PK_MAX_F16_gfx10:
    case AMDGPU::V_PK_MAX_F16_gfx11:
    case AMDGPU::V_PK_MAX_F16_vi:
    case AMDGPU::V_PK_MAX_I16_gfx10:
    case AMDGPU::V_PK_MAX_I16_gfx11:
    case AMDGPU::V_PK_MAX_I16_gfx12:
    case AMDGPU::V_PK_MAX_I16_vi:
    case AMDGPU::V_PK_MAX_NUM_BF16_gfx1250:
    case AMDGPU::V_PK_MAX_NUM_F16_gfx12:
    case AMDGPU::V_PK_MAX_U16_gfx10:
    case AMDGPU::V_PK_MAX_U16_gfx11:
    case AMDGPU::V_PK_MAX_U16_gfx12:
    case AMDGPU::V_PK_MAX_U16_vi:
    case AMDGPU::V_PK_MINIMUM_F16_gfx12:
    case AMDGPU::V_PK_MIN_F16_gfx10:
    case AMDGPU::V_PK_MIN_F16_gfx11:
    case AMDGPU::V_PK_MIN_F16_vi:
    case AMDGPU::V_PK_MIN_I16_gfx10:
    case AMDGPU::V_PK_MIN_I16_gfx11:
    case AMDGPU::V_PK_MIN_I16_gfx12:
    case AMDGPU::V_PK_MIN_I16_vi:
    case AMDGPU::V_PK_MIN_NUM_BF16_gfx1250:
    case AMDGPU::V_PK_MIN_NUM_F16_gfx12:
    case AMDGPU::V_PK_MIN_U16_gfx10:
    case AMDGPU::V_PK_MIN_U16_gfx11:
    case AMDGPU::V_PK_MIN_U16_gfx12:
    case AMDGPU::V_PK_MIN_U16_vi:
    case AMDGPU::V_PK_MOV_B32_vi:
    case AMDGPU::V_PK_MUL_BF16_gfx1250:
    case AMDGPU::V_PK_MUL_F16_gfx10:
    case AMDGPU::V_PK_MUL_F16_gfx11:
    case AMDGPU::V_PK_MUL_F16_gfx12:
    case AMDGPU::V_PK_MUL_F16_vi:
    case AMDGPU::V_PK_MUL_F32_gfx12:
    case AMDGPU::V_PK_MUL_F32_vi:
    case AMDGPU::V_PK_MUL_LO_U16_gfx10:
    case AMDGPU::V_PK_MUL_LO_U16_gfx11:
    case AMDGPU::V_PK_MUL_LO_U16_gfx12:
    case AMDGPU::V_PK_MUL_LO_U16_vi:
    case AMDGPU::V_PK_SUB_I16_gfx10:
    case AMDGPU::V_PK_SUB_I16_gfx11:
    case AMDGPU::V_PK_SUB_I16_gfx12:
    case AMDGPU::V_PK_SUB_I16_vi:
    case AMDGPU::V_PK_SUB_U16_gfx10:
    case AMDGPU::V_PK_SUB_U16_gfx11:
    case AMDGPU::V_PK_SUB_U16_gfx12:
    case AMDGPU::V_PK_SUB_U16_vi:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_t16_e64_gfx11:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_t16_e64_gfx12:
    case AMDGPU::V_SUB_NC_U16_t16_e64_gfx11:
    case AMDGPU::V_SUB_NC_U16_t16_e64_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: clamp
        return 15;
      }
      break;
    }
    case AMDGPU::V_CNDMASK_B16_t16_e64_gfx11:
    case AMDGPU::V_CNDMASK_B16_t16_e64_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2
        return 50;
      }
      break;
    }
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_t16_e64_gfx11:
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_t16_e64_gfx12:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_t16_e64_gfx11:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_t16_e64_gfx12:
    case AMDGPU::V_MAX3_F16_t16_e64_gfx11:
    case AMDGPU::V_MAX3_NUM_F16_t16_e64_gfx12:
    case AMDGPU::V_MAXIMUM3_F16_t16_e64_gfx12:
    case AMDGPU::V_MAXIMUMMINIMUM_F16_t16_e64_gfx12:
    case AMDGPU::V_MAXMIN_F16_t16_e64_gfx11:
    case AMDGPU::V_MAXMIN_NUM_F16_t16_e64_gfx12:
    case AMDGPU::V_MED3_F16_t16_e64_gfx11:
    case AMDGPU::V_MED3_NUM_F16_t16_e64_gfx12:
    case AMDGPU::V_MIN3_F16_t16_e64_gfx11:
    case AMDGPU::V_MIN3_NUM_F16_t16_e64_gfx12:
    case AMDGPU::V_MINIMUM3_F16_t16_e64_gfx12:
    case AMDGPU::V_MINIMUMMAXIMUM_F16_t16_e64_gfx12:
    case AMDGPU::V_MINMAX_F16_t16_e64_gfx11:
    case AMDGPU::V_MINMAX_NUM_F16_t16_e64_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2_modifiers
        return 10;
      case 6:
        // op: src2
        return 50;
      case 7:
        // op: clamp
        return 15;
      case 8:
        // op: omod
        return 59;
      }
      break;
    }
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_t16_e64_gfx11:
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_t16_e64_gfx12:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_t16_e64_gfx11:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_t16_e64_gfx12:
    case AMDGPU::V_DOT2_F32_BF16_gfx11:
    case AMDGPU::V_DOT2_F32_BF16_gfx12:
    case AMDGPU::V_DOT2_F32_BF16_vi:
    case AMDGPU::V_DOT2_F32_F16_gfx10:
    case AMDGPU::V_DOT2_F32_F16_gfx11:
    case AMDGPU::V_DOT2_F32_F16_gfx12:
    case AMDGPU::V_DOT2_F32_F16_vi:
    case AMDGPU::V_DOT2_I32_I16_gfx10:
    case AMDGPU::V_DOT2_I32_I16_vi:
    case AMDGPU::V_DOT2_U32_U16_gfx10:
    case AMDGPU::V_DOT2_U32_U16_vi:
    case AMDGPU::V_DOT4_I32_I8_gfx10:
    case AMDGPU::V_DOT4_I32_I8_vi:
    case AMDGPU::V_DOT4_I32_IU8_gfx11:
    case AMDGPU::V_DOT4_I32_IU8_gfx12:
    case AMDGPU::V_DOT4_U32_U8_gfx10:
    case AMDGPU::V_DOT4_U32_U8_gfx11:
    case AMDGPU::V_DOT4_U32_U8_gfx12:
    case AMDGPU::V_DOT4_U32_U8_vi:
    case AMDGPU::V_DOT8_I32_I4_gfx10:
    case AMDGPU::V_DOT8_I32_I4_vi:
    case AMDGPU::V_DOT8_I32_IU4_gfx11:
    case AMDGPU::V_DOT8_I32_IU4_gfx12:
    case AMDGPU::V_DOT8_U32_U4_gfx10:
    case AMDGPU::V_DOT8_U32_U4_gfx11:
    case AMDGPU::V_DOT8_U32_U4_gfx12:
    case AMDGPU::V_DOT8_U32_U4_vi:
    case AMDGPU::V_FMA_MIXHI_BF16_gfx1250:
    case AMDGPU::V_FMA_MIXHI_F16_gfx10:
    case AMDGPU::V_FMA_MIXHI_F16_gfx11:
    case AMDGPU::V_FMA_MIXHI_F16_gfx12:
    case AMDGPU::V_FMA_MIXHI_F16_vi:
    case AMDGPU::V_FMA_MIXLO_BF16_gfx1250:
    case AMDGPU::V_FMA_MIXLO_F16_gfx10:
    case AMDGPU::V_FMA_MIXLO_F16_gfx11:
    case AMDGPU::V_FMA_MIXLO_F16_gfx12:
    case AMDGPU::V_FMA_MIXLO_F16_vi:
    case AMDGPU::V_FMA_MIX_F32_BF16_gfx1250:
    case AMDGPU::V_FMA_MIX_F32_gfx10:
    case AMDGPU::V_FMA_MIX_F32_gfx11:
    case AMDGPU::V_FMA_MIX_F32_gfx12:
    case AMDGPU::V_FMA_MIX_F32_vi:
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_t16_e64_gfx11:
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_t16_e64_gfx12:
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_t16_e64_gfx11:
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_t16_e64_gfx12:
    case AMDGPU::V_MAD_MIXHI_F16_vi:
    case AMDGPU::V_MAD_MIXLO_F16_vi:
    case AMDGPU::V_MAD_MIX_F32_vi:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_t16_e64_gfx11:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_t16_e64_gfx12:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_t16_e64_gfx11:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_t16_e64_gfx12:
    case AMDGPU::V_MAX3_I16_t16_e64_gfx11:
    case AMDGPU::V_MAX3_I16_t16_e64_gfx12:
    case AMDGPU::V_MAX3_U16_t16_e64_gfx11:
    case AMDGPU::V_MAX3_U16_t16_e64_gfx12:
    case AMDGPU::V_MED3_I16_t16_e64_gfx11:
    case AMDGPU::V_MED3_I16_t16_e64_gfx12:
    case AMDGPU::V_MED3_U16V_MED3_U16_t16_e64_gfx11:
    case AMDGPU::V_MED3_U16V_MED3_U16_t16_e64_gfx12:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_t16_e64_gfx11:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_t16_e64_gfx12:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_t16_e64_gfx11:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_t16_e64_gfx12:
    case AMDGPU::V_PK_ADD_MAX_I16_gfx1250:
    case AMDGPU::V_PK_ADD_MAX_U16_gfx1250:
    case AMDGPU::V_PK_ADD_MIN_I16_gfx1250:
    case AMDGPU::V_PK_ADD_MIN_U16_gfx1250:
    case AMDGPU::V_PK_FMA_BF16_gfx1250:
    case AMDGPU::V_PK_FMA_F16_gfx10:
    case AMDGPU::V_PK_FMA_F16_gfx11:
    case AMDGPU::V_PK_FMA_F16_gfx12:
    case AMDGPU::V_PK_FMA_F16_vi:
    case AMDGPU::V_PK_FMA_F32_gfx12:
    case AMDGPU::V_PK_FMA_F32_vi:
    case AMDGPU::V_PK_MAD_I16_gfx10:
    case AMDGPU::V_PK_MAD_I16_gfx11:
    case AMDGPU::V_PK_MAD_I16_gfx12:
    case AMDGPU::V_PK_MAD_I16_vi:
    case AMDGPU::V_PK_MAD_U16_gfx10:
    case AMDGPU::V_PK_MAD_U16_gfx11:
    case AMDGPU::V_PK_MAD_U16_gfx12:
    case AMDGPU::V_PK_MAD_U16_vi:
    case AMDGPU::V_PK_MAX3_I16_gfx1250:
    case AMDGPU::V_PK_MAX3_NUM_F16_gfx1250:
    case AMDGPU::V_PK_MAX3_U16_gfx1250:
    case AMDGPU::V_PK_MAXIMUM3_F16_gfx1250:
    case AMDGPU::V_PK_MAXIMUM3_F16_vi:
    case AMDGPU::V_PK_MIN3_I16_gfx1250:
    case AMDGPU::V_PK_MIN3_NUM_F16_gfx1250:
    case AMDGPU::V_PK_MIN3_U16_gfx1250:
    case AMDGPU::V_PK_MINIMUM3_F16_gfx1250:
    case AMDGPU::V_PK_MINIMUM3_F16_vi:
    case AMDGPU::V_WMMA_I32_16X16X16_IU4_twoaddr_w32_gfx11:
    case AMDGPU::V_WMMA_I32_16X16X16_IU4_twoaddr_w64_gfx11:
    case AMDGPU::V_WMMA_I32_16X16X16_IU8_twoaddr_w32_gfx11:
    case AMDGPU::V_WMMA_I32_16X16X16_IU8_twoaddr_w64_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2_modifiers
        return 10;
      case 6:
        // op: src2
        return 50;
      case 7:
        // op: clamp
        return 15;
      }
      break;
    }
    case AMDGPU::V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250:
    case AMDGPU::V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2_modifiers
        return 10;
      case 6:
        // op: src2
        return 50;
      case 7:
        // op: matrix_a_reuse
        return 13;
      case 8:
        // op: matrix_b_reuse
        return 14;
      }
      break;
    }
    case AMDGPU::V_DOT2_BF16_BF16_fake16_e64_gfx11:
    case AMDGPU::V_DOT2_BF16_BF16_fake16_e64_gfx12:
    case AMDGPU::V_DOT2_BF16_BF16_t16_e64_gfx11:
    case AMDGPU::V_DOT2_BF16_BF16_t16_e64_gfx12:
    case AMDGPU::V_DOT2_F16_F16_fake16_e64_gfx11:
    case AMDGPU::V_DOT2_F16_F16_fake16_e64_gfx12:
    case AMDGPU::V_DOT2_F16_F16_t16_e64_gfx11:
    case AMDGPU::V_DOT2_F16_F16_t16_e64_gfx12:
    case AMDGPU::V_WMMA_BF16_16X16X16_BF16_twoaddr_w32_gfx11:
    case AMDGPU::V_WMMA_BF16_16X16X16_BF16_twoaddr_w64_gfx11:
    case AMDGPU::V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_BF16_16X16X16_BF16_w64_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F16_16X16X16_F16_twoaddr_w32_gfx11:
    case AMDGPU::V_WMMA_F16_16X16X16_F16_twoaddr_w64_gfx11:
    case AMDGPU::V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F16_16X16X16_F16_w64_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_BF16_twoaddr_w32_gfx11:
    case AMDGPU::V_WMMA_F32_16X16X16_BF16_twoaddr_w64_gfx11:
    case AMDGPU::V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_BF16_w64_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_F16_twoaddr_w32_gfx11:
    case AMDGPU::V_WMMA_F32_16X16X16_F16_twoaddr_w64_gfx11:
    case AMDGPU::V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx12:
    case AMDGPU::V_WMMA_F32_16X16X16_F16_w64_twoaddr_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2_modifiers
        return 10;
      case 6:
        // op: src2
        return 50;
      }
      break;
    }
    case AMDGPU::V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250:
    case AMDGPU::V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 6:
        // op: src2
        return 50;
      case 7:
        // op: index_key_16bit
        return 11;
      case 8:
        // op: matrix_a_reuse
        return 13;
      case 9:
        // op: matrix_b_reuse
        return 14;
      }
      break;
    }
    case AMDGPU::V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 6:
        // op: src2
        return 50;
      case 7:
        // op: index_key_16bit
        return 11;
      }
      break;
    }
    case AMDGPU::V_SWMMAC_BF16_16X16X32_BF16_w64_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F16_16X16X32_F16_w64_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F32_16X16X32_BF16_w64_twoaddr_gfx12:
    case AMDGPU::V_SWMMAC_F32_16X16X32_F16_w64_twoaddr_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 6:
        // op: src2
        return 50;
      case 7:
        // op: index_key_8bit
        return 11;
      }
      break;
    }
    case AMDGPU::V_FMAC_F16_t16_e64_gfx11:
    case AMDGPU::V_FMAC_F16_t16_e64_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 7:
        // op: clamp
        return 15;
      case 8:
        // op: omod
        return 59;
      }
      break;
    }
    case AMDGPU::V_AND_B16_t16_e64_gfx11:
    case AMDGPU::V_AND_B16_t16_e64_gfx12:
    case AMDGPU::V_ASHRREV_I16_t16_e64_gfx11:
    case AMDGPU::V_ASHRREV_I16_t16_e64_gfx12:
    case AMDGPU::V_CVT_PK_BF8_F32_t16_e64_gfx11:
    case AMDGPU::V_CVT_PK_BF8_F32_t16_e64_gfx12:
    case AMDGPU::V_CVT_PK_FP8_F32_t16_e64_gfx11:
    case AMDGPU::V_CVT_PK_FP8_F32_t16_e64_gfx12:
    case AMDGPU::V_LSHLREV_B16_t16_e64_gfx11:
    case AMDGPU::V_LSHLREV_B16_t16_e64_gfx12:
    case AMDGPU::V_LSHRREV_B16_t16_e64_gfx11:
    case AMDGPU::V_LSHRREV_B16_t16_e64_gfx12:
    case AMDGPU::V_MAX_I16_t16_e64_gfx11:
    case AMDGPU::V_MAX_I16_t16_e64_gfx12:
    case AMDGPU::V_MAX_U16_t16_e64_gfx11:
    case AMDGPU::V_MAX_U16_t16_e64_gfx12:
    case AMDGPU::V_MIN_I16_t16_e64_gfx11:
    case AMDGPU::V_MIN_I16_t16_e64_gfx12:
    case AMDGPU::V_MIN_U16_t16_e64_gfx11:
    case AMDGPU::V_MIN_U16_t16_e64_gfx12:
    case AMDGPU::V_MUL_LO_U16_t16_e64_gfx11:
    case AMDGPU::V_MUL_LO_U16_t16_e64_gfx12:
    case AMDGPU::V_OR_B16_t16_e64_gfx11:
    case AMDGPU::V_OR_B16_t16_e64_gfx12:
    case AMDGPU::V_XOR_B16_t16_e64_gfx11:
    case AMDGPU::V_XOR_B16_t16_e64_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      }
      break;
    }
    case AMDGPU::V_COS_BF16V_COS_BF16_t16_e64_gfx1250:
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_t16_e64_gfx1250:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_e64_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_e64_gfx12:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_t16_e64_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_t16_e64_gfx1250:
    case AMDGPU::V_CVT_PK_F32_BF8_t16_e64_gfx12:
    case AMDGPU::V_CVT_PK_F32_FP8_t16_e64_gfx12:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_e64_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_e64_gfx12:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_t16_e64_gfx1250:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_t16_e64_gfx1250:
    case AMDGPU::V_MOV_B16_t16_e64_gfx11:
    case AMDGPU::V_MOV_B16_t16_e64_gfx12:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_e64_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_e64_gfx12:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_t16_e64_gfx1250:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_t16_e64_gfx1250:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_t16_e64_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_t16_e64_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e64_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e64_gfx12:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_t16_e64_gfx1250:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_t16_e64_gfx1250:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_t16_e64_gfx1250: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      }
      break;
    }
    case AMDGPU::V_ADD_CO_U32_e64_gfx10:
    case AMDGPU::V_ADD_CO_U32_e64_gfx11:
    case AMDGPU::V_ADD_CO_U32_e64_gfx12:
    case AMDGPU::V_ADD_CO_U32_e64_gfx9:
    case AMDGPU::V_ADD_U32_e64_vi:
    case AMDGPU::V_SUBREV_CO_U32_e64_gfx10:
    case AMDGPU::V_SUBREV_CO_U32_e64_gfx11:
    case AMDGPU::V_SUBREV_CO_U32_e64_gfx12:
    case AMDGPU::V_SUBREV_CO_U32_e64_gfx9:
    case AMDGPU::V_SUBREV_U32_e64_vi:
    case AMDGPU::V_SUB_CO_U32_e64_gfx10:
    case AMDGPU::V_SUB_CO_U32_e64_gfx11:
    case AMDGPU::V_SUB_CO_U32_e64_gfx12:
    case AMDGPU::V_SUB_CO_U32_e64_gfx9:
    case AMDGPU::V_SUB_U32_e64_vi: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1
        return 41;
      case 1:
        // op: sdst
        return 8;
      case 4:
        // op: clamp
        return 15;
      }
      break;
    }
    case AMDGPU::V_ADD_I32_e64_gfx6_gfx7:
    case AMDGPU::V_SUBREV_I32_e64_gfx6_gfx7:
    case AMDGPU::V_SUB_I32_e64_gfx6_gfx7: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1
        return 41;
      case 1:
        // op: sdst
        return 8;
      }
      break;
    }
    case AMDGPU::V_ADDC_CO_U32_e64_gfx9:
    case AMDGPU::V_ADDC_U32_e64_vi:
    case AMDGPU::V_ADD_CO_CI_U32_e64_gfx10:
    case AMDGPU::V_ADD_CO_CI_U32_e64_gfx11:
    case AMDGPU::V_ADD_CO_CI_U32_e64_gfx12:
    case AMDGPU::V_MAD_CO_I64_I32_e64_gfx12:
    case AMDGPU::V_MAD_CO_U64_U32_e64_gfx12:
    case AMDGPU::V_MAD_I64_I32_gfx10:
    case AMDGPU::V_MAD_I64_I32_gfx11_e64_gfx11:
    case AMDGPU::V_MAD_I64_I32_vi:
    case AMDGPU::V_MAD_U64_U32_gfx10:
    case AMDGPU::V_MAD_U64_U32_gfx11_e64_gfx11:
    case AMDGPU::V_MAD_U64_U32_vi:
    case AMDGPU::V_SUBBREV_CO_U32_e64_gfx9:
    case AMDGPU::V_SUBBREV_U32_e64_vi:
    case AMDGPU::V_SUBB_CO_U32_e64_gfx9:
    case AMDGPU::V_SUBB_U32_e64_vi:
    case AMDGPU::V_SUBREV_CO_CI_U32_e64_gfx10:
    case AMDGPU::V_SUBREV_CO_CI_U32_e64_gfx11:
    case AMDGPU::V_SUBREV_CO_CI_U32_e64_gfx12:
    case AMDGPU::V_SUB_CO_CI_U32_e64_gfx10:
    case AMDGPU::V_SUB_CO_CI_U32_e64_gfx11:
    case AMDGPU::V_SUB_CO_CI_U32_e64_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1
        return 41;
      case 4:
        // op: src2
        return 50;
      case 1:
        // op: sdst
        return 8;
      case 5:
        // op: clamp
        return 15;
      }
      break;
    }
    case AMDGPU::V_ADDC_U32_e64_gfx6_gfx7:
    case AMDGPU::V_MAD_I64_I32_gfx7:
    case AMDGPU::V_MAD_U64_U32_gfx7:
    case AMDGPU::V_SUBBREV_U32_e64_gfx6_gfx7:
    case AMDGPU::V_SUBB_U32_e64_gfx6_gfx7: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1
        return 41;
      case 4:
        // op: src2
        return 50;
      case 1:
        // op: sdst
        return 8;
      }
      break;
    }
    case AMDGPU::V_BFREV_B32_e64_dpp8_gfx11:
    case AMDGPU::V_BFREV_B32_e64_dpp8_gfx12:
    case AMDGPU::V_CLS_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CLS_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CLZ_I32_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CLZ_I32_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CTZ_I32_B32_e64_dpp8_gfx11:
    case AMDGPU::V_CTZ_I32_B32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MOVRELD_B32_e64_dpp8_gfx11:
    case AMDGPU::V_MOVRELD_B32_e64_dpp8_gfx12:
    case AMDGPU::V_MOVRELSD_2_B32_e64_dpp8_gfx11:
    case AMDGPU::V_MOVRELSD_2_B32_e64_dpp8_gfx12:
    case AMDGPU::V_MOVRELSD_B32_e64_dpp8_gfx11:
    case AMDGPU::V_MOVRELSD_B32_e64_dpp8_gfx12:
    case AMDGPU::V_MOVRELS_B32_e64_dpp8_gfx11:
    case AMDGPU::V_MOVRELS_B32_e64_dpp8_gfx12:
    case AMDGPU::V_MOV_B32_e64_dpp8_gfx11:
    case AMDGPU::V_MOV_B32_e64_dpp8_gfx12:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_NOT_B32_e64_dpp8_gfx11:
    case AMDGPU::V_NOT_B32_e64_dpp8_gfx12:
    case AMDGPU::V_PRNG_B32_e64_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 2:
        // op: src0
        return 64;
      case 3:
        // op: dpp8
        return 72;
      case 4:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_DIV_SCALE_F32_e64_gfx11:
    case AMDGPU::V_DIV_SCALE_F32_e64_gfx12:
    case AMDGPU::V_DIV_SCALE_F32_gfx10:
    case AMDGPU::V_DIV_SCALE_F32_vi:
    case AMDGPU::V_DIV_SCALE_F64_e64_gfx11:
    case AMDGPU::V_DIV_SCALE_F64_e64_gfx12:
    case AMDGPU::V_DIV_SCALE_F64_e64_gfx1250:
    case AMDGPU::V_DIV_SCALE_F64_gfx10:
    case AMDGPU::V_DIV_SCALE_F64_vi: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 2:
        // op: src0_modifiers
        return 61;
      case 3:
        // op: src0
        return 32;
      case 4:
        // op: src1_modifiers
        return 62;
      case 5:
        // op: src1
        return 41;
      case 6:
        // op: src2_modifiers
        return 63;
      case 7:
        // op: src2
        return 50;
      case 1:
        // op: sdst
        return 8;
      case 9:
        // op: omod
        return 59;
      case 8:
        // op: clamp
        return 15;
      }
      break;
    }
    case AMDGPU::V_DIV_SCALE_F32_gfx6_gfx7:
    case AMDGPU::V_DIV_SCALE_F64_gfx6_gfx7: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 2:
        // op: src0_modifiers
        return 61;
      case 3:
        // op: src0
        return 32;
      case 4:
        // op: src1_modifiers
        return 62;
      case 5:
        // op: src1
        return 41;
      case 6:
        // op: src2_modifiers
        return 63;
      case 7:
        // op: src2
        return 50;
      case 1:
        // op: sdst
        return 8;
      case 9:
        // op: omod
        return 59;
      }
      break;
    }
    case AMDGPU::V_BFREV_B32_e64_dpp_gfx11:
    case AMDGPU::V_BFREV_B32_e64_dpp_gfx12:
    case AMDGPU::V_CLS_I32_e64_dpp_gfx11:
    case AMDGPU::V_CLS_I32_e64_dpp_gfx12:
    case AMDGPU::V_CLZ_I32_U32_e64_dpp_gfx11:
    case AMDGPU::V_CLZ_I32_U32_e64_dpp_gfx12:
    case AMDGPU::V_CTZ_I32_B32_e64_dpp_gfx11:
    case AMDGPU::V_CTZ_I32_B32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MOVRELD_B32_e64_dpp_gfx11:
    case AMDGPU::V_MOVRELD_B32_e64_dpp_gfx12:
    case AMDGPU::V_MOVRELSD_2_B32_e64_dpp_gfx11:
    case AMDGPU::V_MOVRELSD_2_B32_e64_dpp_gfx12:
    case AMDGPU::V_MOVRELSD_B32_e64_dpp_gfx11:
    case AMDGPU::V_MOVRELSD_B32_e64_dpp_gfx12:
    case AMDGPU::V_MOVRELS_B32_e64_dpp_gfx11:
    case AMDGPU::V_MOVRELS_B32_e64_dpp_gfx12:
    case AMDGPU::V_MOV_B32_e64_dpp_gfx11:
    case AMDGPU::V_MOV_B32_e64_dpp_gfx12:
    case AMDGPU::V_MOV_B64_e64_dpp_gfx1250:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_NOT_B32_e64_dpp_gfx11:
    case AMDGPU::V_NOT_B32_e64_dpp_gfx12:
    case AMDGPU::V_PRNG_B32_e64_dpp_gfx1250:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e64_dpp_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: dpp_ctrl
        return 72;
      case 6:
        // op: bound_ctrl
        return 83;
      case 5:
        // op: bank_mask
        return 88;
      case 4:
        // op: row_mask
        return 92;
      case 7:
        // op: fi
        return 82;
      case 2:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_AND_B16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_AND_B16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_AND_B32_e64_dpp8_gfx11:
    case AMDGPU::V_AND_B32_e64_dpp8_gfx12:
    case AMDGPU::V_ASHRREV_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_ASHRREV_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_ASHRREV_I32_e64_dpp8_gfx11:
    case AMDGPU::V_ASHRREV_I32_e64_dpp8_gfx12:
    case AMDGPU::V_BCNT_U32_B32_e64_dpp8_gfx11:
    case AMDGPU::V_BCNT_U32_B32_e64_dpp8_gfx12:
    case AMDGPU::V_BFM_B32_e64_dpp8_gfx11:
    case AMDGPU::V_BFM_B32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_I16_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_I16_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_U16_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_U16_U32_e64_dpp8_gfx12:
    case AMDGPU::V_LSHLREV_B16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_LSHLREV_B16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_LSHLREV_B32_e64_dpp8_gfx11:
    case AMDGPU::V_LSHLREV_B32_e64_dpp8_gfx12:
    case AMDGPU::V_LSHRREV_B16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_LSHRREV_B16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_LSHRREV_B32_e64_dpp8_gfx11:
    case AMDGPU::V_LSHRREV_B32_e64_dpp8_gfx12:
    case AMDGPU::V_MAX_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX_I32_e64_dpp8_gfx11:
    case AMDGPU::V_MAX_I32_e64_dpp8_gfx12:
    case AMDGPU::V_MAX_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX_U32_e64_dpp8_gfx11:
    case AMDGPU::V_MAX_U32_e64_dpp8_gfx12:
    case AMDGPU::V_MBCNT_HI_U32_B32_e64_dpp8_gfx11:
    case AMDGPU::V_MBCNT_HI_U32_B32_e64_dpp8_gfx12:
    case AMDGPU::V_MBCNT_LO_U32_B32_e64_dpp8_gfx11:
    case AMDGPU::V_MBCNT_LO_U32_B32_e64_dpp8_gfx12:
    case AMDGPU::V_MIN_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN_I32_e64_dpp8_gfx11:
    case AMDGPU::V_MIN_I32_e64_dpp8_gfx12:
    case AMDGPU::V_MIN_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN_U32_e64_dpp8_gfx11:
    case AMDGPU::V_MIN_U32_e64_dpp8_gfx12:
    case AMDGPU::V_MUL_HI_I32_I24_e64_dpp8_gfx11:
    case AMDGPU::V_MUL_HI_I32_I24_e64_dpp8_gfx12:
    case AMDGPU::V_MUL_HI_U32_U24_e64_dpp8_gfx11:
    case AMDGPU::V_MUL_HI_U32_U24_e64_dpp8_gfx12:
    case AMDGPU::V_MUL_LO_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MUL_LO_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_OR_B16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_OR_B16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_OR_B32_e64_dpp8_gfx11:
    case AMDGPU::V_OR_B32_e64_dpp8_gfx12:
    case AMDGPU::V_XNOR_B32_e64_dpp8_gfx11:
    case AMDGPU::V_XNOR_B32_e64_dpp8_gfx12:
    case AMDGPU::V_XOR_B16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_XOR_B16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_XOR_B32_e64_dpp8_gfx11:
    case AMDGPU::V_XOR_B32_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: src1
        return 41;
      case 2:
        // op: src0
        return 64;
      case 4:
        // op: dpp8
        return 72;
      case 5:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_AND_B16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_AND_B16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_AND_B32_e64_dpp_gfx11:
    case AMDGPU::V_AND_B32_e64_dpp_gfx12:
    case AMDGPU::V_ASHRREV_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_ASHRREV_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_ASHRREV_I32_e64_dpp_gfx11:
    case AMDGPU::V_ASHRREV_I32_e64_dpp_gfx12:
    case AMDGPU::V_ASHRREV_I64_e64_dpp_gfx1250:
    case AMDGPU::V_BCNT_U32_B32_e64_dpp_gfx11:
    case AMDGPU::V_BCNT_U32_B32_e64_dpp_gfx12:
    case AMDGPU::V_BFM_B32_e64_dpp_gfx11:
    case AMDGPU::V_BFM_B32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_I16_I32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_I16_I32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_U16_U32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_U16_U32_e64_dpp_gfx12:
    case AMDGPU::V_LSHLREV_B16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_LSHLREV_B16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_LSHLREV_B32_e64_dpp_gfx11:
    case AMDGPU::V_LSHLREV_B32_e64_dpp_gfx12:
    case AMDGPU::V_LSHLREV_B64_e64_dpp_gfx12:
    case AMDGPU::V_LSHRREV_B16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_LSHRREV_B16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_LSHRREV_B32_e64_dpp_gfx11:
    case AMDGPU::V_LSHRREV_B32_e64_dpp_gfx12:
    case AMDGPU::V_LSHRREV_B64_e64_dpp_gfx1250:
    case AMDGPU::V_MAX_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAX_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAX_I32_e64_dpp_gfx11:
    case AMDGPU::V_MAX_I32_e64_dpp_gfx12:
    case AMDGPU::V_MAX_I64_e64_dpp_gfx1250:
    case AMDGPU::V_MAX_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAX_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAX_U32_e64_dpp_gfx11:
    case AMDGPU::V_MAX_U32_e64_dpp_gfx12:
    case AMDGPU::V_MAX_U64_e64_dpp_gfx1250:
    case AMDGPU::V_MBCNT_HI_U32_B32_e64_dpp_gfx11:
    case AMDGPU::V_MBCNT_HI_U32_B32_e64_dpp_gfx12:
    case AMDGPU::V_MBCNT_LO_U32_B32_e64_dpp_gfx11:
    case AMDGPU::V_MBCNT_LO_U32_B32_e64_dpp_gfx12:
    case AMDGPU::V_MIN_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MIN_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MIN_I32_e64_dpp_gfx11:
    case AMDGPU::V_MIN_I32_e64_dpp_gfx12:
    case AMDGPU::V_MIN_I64_e64_dpp_gfx1250:
    case AMDGPU::V_MIN_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MIN_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MIN_U32_e64_dpp_gfx11:
    case AMDGPU::V_MIN_U32_e64_dpp_gfx12:
    case AMDGPU::V_MIN_U64_e64_dpp_gfx1250:
    case AMDGPU::V_MUL_HI_I32_I24_e64_dpp_gfx11:
    case AMDGPU::V_MUL_HI_I32_I24_e64_dpp_gfx12:
    case AMDGPU::V_MUL_HI_I32_e64_dpp_gfx1250:
    case AMDGPU::V_MUL_HI_U32_U24_e64_dpp_gfx11:
    case AMDGPU::V_MUL_HI_U32_U24_e64_dpp_gfx12:
    case AMDGPU::V_MUL_HI_U32_e64_dpp_gfx1250:
    case AMDGPU::V_MUL_LO_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MUL_LO_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MUL_LO_U32_e64_dpp_gfx1250:
    case AMDGPU::V_OR_B16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_OR_B16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_OR_B32_e64_dpp_gfx11:
    case AMDGPU::V_OR_B32_e64_dpp_gfx12:
    case AMDGPU::V_XNOR_B32_e64_dpp_gfx11:
    case AMDGPU::V_XNOR_B32_e64_dpp_gfx12:
    case AMDGPU::V_XOR_B16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_XOR_B16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_XOR_B32_e64_dpp_gfx11:
    case AMDGPU::V_XOR_B32_e64_dpp_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: src1
        return 41;
      case 4:
        // op: dpp_ctrl
        return 72;
      case 7:
        // op: bound_ctrl
        return 83;
      case 6:
        // op: bank_mask
        return 88;
      case 5:
        // op: row_mask
        return 92;
      case 8:
        // op: fi
        return 82;
      case 2:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_ADD3_U32_e64_dpp8_gfx11:
    case AMDGPU::V_ADD3_U32_e64_dpp8_gfx12:
    case AMDGPU::V_ADD_LSHL_U32_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_LSHL_U32_e64_dpp8_gfx12:
    case AMDGPU::V_AND_OR_B32_e64_dpp8_gfx11:
    case AMDGPU::V_AND_OR_B32_e64_dpp8_gfx12:
    case AMDGPU::V_BFE_I32_e64_dpp8_gfx11:
    case AMDGPU::V_BFE_I32_e64_dpp8_gfx12:
    case AMDGPU::V_BFE_U32_e64_dpp8_gfx11:
    case AMDGPU::V_BFE_U32_e64_dpp8_gfx12:
    case AMDGPU::V_BFI_B32_e64_dpp8_gfx11:
    case AMDGPU::V_BFI_B32_e64_dpp8_gfx12:
    case AMDGPU::V_LERP_U8_e64_dpp8_gfx11:
    case AMDGPU::V_LERP_U8_e64_dpp8_gfx12:
    case AMDGPU::V_LSHL_ADD_U32_e64_dpp8_gfx11:
    case AMDGPU::V_LSHL_ADD_U32_e64_dpp8_gfx12:
    case AMDGPU::V_LSHL_OR_B32_e64_dpp8_gfx11:
    case AMDGPU::V_LSHL_OR_B32_e64_dpp8_gfx12:
    case AMDGPU::V_MAX3_I32_e64_dpp8_gfx11:
    case AMDGPU::V_MAX3_I32_e64_dpp8_gfx12:
    case AMDGPU::V_MAX3_U32_e64_dpp8_gfx11:
    case AMDGPU::V_MAX3_U32_e64_dpp8_gfx12:
    case AMDGPU::V_MAXMIN_I32_e64_dpp8_gfx11:
    case AMDGPU::V_MAXMIN_I32_e64_dpp8_gfx12:
    case AMDGPU::V_MAXMIN_U32_e64_dpp8_gfx11:
    case AMDGPU::V_MAXMIN_U32_e64_dpp8_gfx12:
    case AMDGPU::V_MED3_I32_e64_dpp8_gfx11:
    case AMDGPU::V_MED3_I32_e64_dpp8_gfx12:
    case AMDGPU::V_MED3_U32_e64_dpp8_gfx11:
    case AMDGPU::V_MED3_U32_e64_dpp8_gfx12:
    case AMDGPU::V_MIN3_I32_e64_dpp8_gfx11:
    case AMDGPU::V_MIN3_I32_e64_dpp8_gfx12:
    case AMDGPU::V_MIN3_U32_e64_dpp8_gfx11:
    case AMDGPU::V_MIN3_U32_e64_dpp8_gfx12:
    case AMDGPU::V_MINMAX_I32_e64_dpp8_gfx11:
    case AMDGPU::V_MINMAX_I32_e64_dpp8_gfx12:
    case AMDGPU::V_MINMAX_U32_e64_dpp8_gfx11:
    case AMDGPU::V_MINMAX_U32_e64_dpp8_gfx12:
    case AMDGPU::V_OR3_B32_e64_dpp8_gfx11:
    case AMDGPU::V_OR3_B32_e64_dpp8_gfx12:
    case AMDGPU::V_PERM_B32_e64_dpp8_gfx11:
    case AMDGPU::V_PERM_B32_e64_dpp8_gfx12:
    case AMDGPU::V_XAD_U32_e64_dpp8_gfx11:
    case AMDGPU::V_XAD_U32_e64_dpp8_gfx12:
    case AMDGPU::V_XOR3_B32_e64_dpp8_gfx11:
    case AMDGPU::V_XOR3_B32_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: src1
        return 41;
      case 4:
        // op: src2
        return 50;
      case 2:
        // op: src0
        return 64;
      case 5:
        // op: dpp8
        return 72;
      case 6:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_BITOP3_B32_e64_dpp8_gfx1250: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: src1
        return 41;
      case 4:
        // op: src2
        return 50;
      case 2:
        // op: src0
        return 64;
      case 6:
        // op: dpp8
        return 72;
      case 7:
        // op: fi
        return 32;
      case 5:
        // op: bitop3
        return 8;
      }
      break;
    }
    case AMDGPU::V_ADD3_U32_e64_dpp_gfx11:
    case AMDGPU::V_ADD3_U32_e64_dpp_gfx12:
    case AMDGPU::V_ADD_LSHL_U32_e64_dpp_gfx11:
    case AMDGPU::V_ADD_LSHL_U32_e64_dpp_gfx12:
    case AMDGPU::V_AND_OR_B32_e64_dpp_gfx11:
    case AMDGPU::V_AND_OR_B32_e64_dpp_gfx12:
    case AMDGPU::V_BFE_I32_e64_dpp_gfx11:
    case AMDGPU::V_BFE_I32_e64_dpp_gfx12:
    case AMDGPU::V_BFE_U32_e64_dpp_gfx11:
    case AMDGPU::V_BFE_U32_e64_dpp_gfx12:
    case AMDGPU::V_BFI_B32_e64_dpp_gfx11:
    case AMDGPU::V_BFI_B32_e64_dpp_gfx12:
    case AMDGPU::V_LERP_U8_e64_dpp_gfx11:
    case AMDGPU::V_LERP_U8_e64_dpp_gfx12:
    case AMDGPU::V_LSHL_ADD_U32_e64_dpp_gfx11:
    case AMDGPU::V_LSHL_ADD_U32_e64_dpp_gfx12:
    case AMDGPU::V_LSHL_ADD_U64_e64_dpp_gfx1250:
    case AMDGPU::V_LSHL_OR_B32_e64_dpp_gfx11:
    case AMDGPU::V_LSHL_OR_B32_e64_dpp_gfx12:
    case AMDGPU::V_MAD_U32_e64_dpp_gfx1250:
    case AMDGPU::V_MAX3_I32_e64_dpp_gfx11:
    case AMDGPU::V_MAX3_I32_e64_dpp_gfx12:
    case AMDGPU::V_MAX3_U32_e64_dpp_gfx11:
    case AMDGPU::V_MAX3_U32_e64_dpp_gfx12:
    case AMDGPU::V_MAXMIN_I32_e64_dpp_gfx11:
    case AMDGPU::V_MAXMIN_I32_e64_dpp_gfx12:
    case AMDGPU::V_MAXMIN_U32_e64_dpp_gfx11:
    case AMDGPU::V_MAXMIN_U32_e64_dpp_gfx12:
    case AMDGPU::V_MED3_I32_e64_dpp_gfx11:
    case AMDGPU::V_MED3_I32_e64_dpp_gfx12:
    case AMDGPU::V_MED3_U32_e64_dpp_gfx11:
    case AMDGPU::V_MED3_U32_e64_dpp_gfx12:
    case AMDGPU::V_MIN3_I32_e64_dpp_gfx11:
    case AMDGPU::V_MIN3_I32_e64_dpp_gfx12:
    case AMDGPU::V_MIN3_U32_e64_dpp_gfx11:
    case AMDGPU::V_MIN3_U32_e64_dpp_gfx12:
    case AMDGPU::V_MINMAX_I32_e64_dpp_gfx11:
    case AMDGPU::V_MINMAX_I32_e64_dpp_gfx12:
    case AMDGPU::V_MINMAX_U32_e64_dpp_gfx11:
    case AMDGPU::V_MINMAX_U32_e64_dpp_gfx12:
    case AMDGPU::V_OR3_B32_e64_dpp_gfx11:
    case AMDGPU::V_OR3_B32_e64_dpp_gfx12:
    case AMDGPU::V_PERM_B32_e64_dpp_gfx11:
    case AMDGPU::V_PERM_B32_e64_dpp_gfx12:
    case AMDGPU::V_XAD_U32_e64_dpp_gfx11:
    case AMDGPU::V_XAD_U32_e64_dpp_gfx12:
    case AMDGPU::V_XOR3_B32_e64_dpp_gfx11:
    case AMDGPU::V_XOR3_B32_e64_dpp_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: src1
        return 41;
      case 4:
        // op: src2
        return 50;
      case 5:
        // op: dpp_ctrl
        return 72;
      case 8:
        // op: bound_ctrl
        return 83;
      case 7:
        // op: bank_mask
        return 88;
      case 6:
        // op: row_mask
        return 92;
      case 9:
        // op: fi
        return 82;
      case 2:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_BITOP3_B32_e64_dpp_gfx1250: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: src1
        return 41;
      case 4:
        // op: src2
        return 50;
      case 6:
        // op: dpp_ctrl
        return 72;
      case 9:
        // op: bound_ctrl
        return 83;
      case 8:
        // op: bank_mask
        return 88;
      case 7:
        // op: row_mask
        return 92;
      case 10:
        // op: fi
        return 82;
      case 2:
        // op: src0
        return 64;
      case 5:
        // op: bitop3
        return 8;
      }
      break;
    }
    case AMDGPU::V_FMAAK_F16_fake16_gfx11:
    case AMDGPU::V_FMAAK_F16_fake16_gfx12:
    case AMDGPU::V_FMAAK_F16_gfx10:
    case AMDGPU::V_FMAAK_F16_t16_gfx11:
    case AMDGPU::V_FMAAK_F16_t16_gfx12:
    case AMDGPU::V_FMAAK_F32_gfx10:
    case AMDGPU::V_FMAAK_F32_gfx11:
    case AMDGPU::V_FMAAK_F32_gfx12:
    case AMDGPU::V_FMAAK_F32_gfx940:
    case AMDGPU::V_FMAAK_F64_gfx1250:
    case AMDGPU::V_MADAK_F16_vi:
    case AMDGPU::V_MADAK_F32_gfx10:
    case AMDGPU::V_MADAK_F32_gfx6_gfx7:
    case AMDGPU::V_MADAK_F32_vi: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 17;
      case 1:
        // op: src0
        return 0;
      case 2:
        // op: src1
        return 9;
      case 3:
        // op: imm
        return 32;
      }
      break;
    }
    case AMDGPU::V_ADDC_CO_U32_e32_gfx9:
    case AMDGPU::V_ADDC_U32_e32_gfx6_gfx7:
    case AMDGPU::V_ADDC_U32_e32_vi:
    case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
    case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
    case AMDGPU::V_ADD_CO_CI_U32_e32_gfx12:
    case AMDGPU::V_ADD_CO_U32_e32_gfx9:
    case AMDGPU::V_ADD_F16_e32_gfx10:
    case AMDGPU::V_ADD_F16_e32_vi:
    case AMDGPU::V_ADD_F16_fake16_e32_gfx11:
    case AMDGPU::V_ADD_F16_fake16_e32_gfx12:
    case AMDGPU::V_ADD_F16_t16_e32_gfx11:
    case AMDGPU::V_ADD_F16_t16_e32_gfx12:
    case AMDGPU::V_ADD_F32_e32_gfx10:
    case AMDGPU::V_ADD_F32_e32_gfx11:
    case AMDGPU::V_ADD_F32_e32_gfx12:
    case AMDGPU::V_ADD_F32_e32_gfx6_gfx7:
    case AMDGPU::V_ADD_F32_e32_vi:
    case AMDGPU::V_ADD_F64_e32_gfx12:
    case AMDGPU::V_ADD_I32_e32_gfx6_gfx7:
    case AMDGPU::V_ADD_NC_U32_e32_gfx10:
    case AMDGPU::V_ADD_NC_U32_e32_gfx11:
    case AMDGPU::V_ADD_NC_U32_e32_gfx12:
    case AMDGPU::V_ADD_U16_e32_vi:
    case AMDGPU::V_ADD_U32_e32_gfx9:
    case AMDGPU::V_ADD_U32_e32_vi:
    case AMDGPU::V_ADD_U64_e32_gfx1250:
    case AMDGPU::V_AND_B32_e32_gfx10:
    case AMDGPU::V_AND_B32_e32_gfx11:
    case AMDGPU::V_AND_B32_e32_gfx12:
    case AMDGPU::V_AND_B32_e32_gfx6_gfx7:
    case AMDGPU::V_AND_B32_e32_vi:
    case AMDGPU::V_ASHRREV_I16_e32_vi:
    case AMDGPU::V_ASHRREV_I32_e32_gfx10:
    case AMDGPU::V_ASHRREV_I32_e32_gfx11:
    case AMDGPU::V_ASHRREV_I32_e32_gfx12:
    case AMDGPU::V_ASHRREV_I32_e32_gfx6_gfx7:
    case AMDGPU::V_ASHRREV_I32_e32_vi:
    case AMDGPU::V_ASHR_I32_e32_gfx6_gfx7:
    case AMDGPU::V_BCNT_U32_B32_e32_gfx6_gfx7:
    case AMDGPU::V_BFM_B32_e32_gfx6_gfx7:
    case AMDGPU::V_CNDMASK_B32_e32_gfx10:
    case AMDGPU::V_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
    case AMDGPU::V_CNDMASK_B32_e32_vi:
    case AMDGPU::V_CVT_PKACCUM_U8_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_PKNORM_I16_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_PKNORM_U16_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_PKRTZ_F16_F32_e32_gfx10:
    case AMDGPU::V_CVT_PKRTZ_F16_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_PK_I16_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_e32_gfx11:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_e32_gfx12:
    case AMDGPU::V_CVT_PK_U16_U32_e32_gfx6_gfx7:
    case AMDGPU::V_DOT2ACC_F32_F16_e32_gfx11:
    case AMDGPU::V_DOT2C_F32_BF16_e32_vi:
    case AMDGPU::V_DOT2C_F32_F16_e32_gfx10:
    case AMDGPU::V_DOT2C_F32_F16_e32_vi:
    case AMDGPU::V_DOT2C_I32_I16_e32_vi:
    case AMDGPU::V_DOT4C_I32_I8_e32_gfx10:
    case AMDGPU::V_DOT4C_I32_I8_e32_vi:
    case AMDGPU::V_DOT8C_I32_I4_e32_gfx10:
    case AMDGPU::V_DOT8C_I32_I4_e32_vi:
    case AMDGPU::V_FMAC_DX9_ZERO_F32_e32_gfx11:
    case AMDGPU::V_FMAC_F16_e32_gfx10:
    case AMDGPU::V_FMAC_F16_fake16_e32_gfx11:
    case AMDGPU::V_FMAC_F16_fake16_e32_gfx12:
    case AMDGPU::V_FMAC_F16_t16_e32_gfx11:
    case AMDGPU::V_FMAC_F16_t16_e32_gfx12:
    case AMDGPU::V_FMAC_F32_e32_gfx10:
    case AMDGPU::V_FMAC_F32_e32_gfx11:
    case AMDGPU::V_FMAC_F32_e32_gfx12:
    case AMDGPU::V_FMAC_F32_e32_vi:
    case AMDGPU::V_FMAC_F64_e32_gfx12:
    case AMDGPU::V_FMAC_F64_e32_gfx90a:
    case AMDGPU::V_FMAC_LEGACY_F32_e32_gfx10:
    case AMDGPU::V_LDEXP_F16_e32_gfx10:
    case AMDGPU::V_LDEXP_F16_e32_vi:
    case AMDGPU::V_LDEXP_F16_fake16_e32_gfx11:
    case AMDGPU::V_LDEXP_F16_fake16_e32_gfx12:
    case AMDGPU::V_LDEXP_F16_t16_e32_gfx11:
    case AMDGPU::V_LDEXP_F16_t16_e32_gfx12:
    case AMDGPU::V_LDEXP_F32_e32_gfx6_gfx7:
    case AMDGPU::V_LSHLREV_B16_e32_vi:
    case AMDGPU::V_LSHLREV_B32_e32_gfx10:
    case AMDGPU::V_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_LSHLREV_B32_e32_gfx6_gfx7:
    case AMDGPU::V_LSHLREV_B32_e32_vi:
    case AMDGPU::V_LSHLREV_B64_e32_gfx12:
    case AMDGPU::V_LSHL_B32_e32_gfx6_gfx7:
    case AMDGPU::V_LSHRREV_B16_e32_vi:
    case AMDGPU::V_LSHRREV_B32_e32_gfx10:
    case AMDGPU::V_LSHRREV_B32_e32_gfx11:
    case AMDGPU::V_LSHRREV_B32_e32_gfx12:
    case AMDGPU::V_LSHRREV_B32_e32_gfx6_gfx7:
    case AMDGPU::V_LSHRREV_B32_e32_vi:
    case AMDGPU::V_LSHR_B32_e32_gfx6_gfx7:
    case AMDGPU::V_MAC_F16_e32_vi:
    case AMDGPU::V_MAC_F32_e32_gfx10:
    case AMDGPU::V_MAC_F32_e32_gfx6_gfx7:
    case AMDGPU::V_MAC_F32_e32_vi:
    case AMDGPU::V_MAC_LEGACY_F32_e32_gfx10:
    case AMDGPU::V_MAC_LEGACY_F32_e32_gfx6_gfx7:
    case AMDGPU::V_MAX_F16V_MAX_F16_fake16_e32_gfx11:
    case AMDGPU::V_MAX_F16V_MAX_F16_t16_e32_gfx11:
    case AMDGPU::V_MAX_F16_e32_gfx10:
    case AMDGPU::V_MAX_F16_e32_vi:
    case AMDGPU::V_MAX_F32_e32_gfx10:
    case AMDGPU::V_MAX_F32_e32_gfx11:
    case AMDGPU::V_MAX_F32_e32_gfx6_gfx7:
    case AMDGPU::V_MAX_F32_e32_vi:
    case AMDGPU::V_MAX_I16_e32_vi:
    case AMDGPU::V_MAX_I32_e32_gfx10:
    case AMDGPU::V_MAX_I32_e32_gfx11:
    case AMDGPU::V_MAX_I32_e32_gfx12:
    case AMDGPU::V_MAX_I32_e32_gfx6_gfx7:
    case AMDGPU::V_MAX_I32_e32_vi:
    case AMDGPU::V_MAX_LEGACY_F32_e32_gfx6_gfx7:
    case AMDGPU::V_MAX_NUM_F16_fake16_e32_gfx12:
    case AMDGPU::V_MAX_NUM_F16_t16_e32_gfx12:
    case AMDGPU::V_MAX_NUM_F32_e32_gfx12:
    case AMDGPU::V_MAX_NUM_F64_e32_gfx12:
    case AMDGPU::V_MAX_U16_e32_vi:
    case AMDGPU::V_MAX_U32_e32_gfx10:
    case AMDGPU::V_MAX_U32_e32_gfx11:
    case AMDGPU::V_MAX_U32_e32_gfx12:
    case AMDGPU::V_MAX_U32_e32_gfx6_gfx7:
    case AMDGPU::V_MAX_U32_e32_vi:
    case AMDGPU::V_MBCNT_HI_U32_B32_e32_gfx6_gfx7:
    case AMDGPU::V_MBCNT_LO_U32_B32_e32_gfx6_gfx7:
    case AMDGPU::V_MIN_F16V_MIN_F16_fake16_e32_gfx11:
    case AMDGPU::V_MIN_F16V_MIN_F16_t16_e32_gfx11:
    case AMDGPU::V_MIN_F16_e32_gfx10:
    case AMDGPU::V_MIN_F16_e32_vi:
    case AMDGPU::V_MIN_F32_e32_gfx10:
    case AMDGPU::V_MIN_F32_e32_gfx11:
    case AMDGPU::V_MIN_F32_e32_gfx6_gfx7:
    case AMDGPU::V_MIN_F32_e32_vi:
    case AMDGPU::V_MIN_I16_e32_vi:
    case AMDGPU::V_MIN_I32_e32_gfx10:
    case AMDGPU::V_MIN_I32_e32_gfx11:
    case AMDGPU::V_MIN_I32_e32_gfx12:
    case AMDGPU::V_MIN_I32_e32_gfx6_gfx7:
    case AMDGPU::V_MIN_I32_e32_vi:
    case AMDGPU::V_MIN_LEGACY_F32_e32_gfx6_gfx7:
    case AMDGPU::V_MIN_NUM_F16_fake16_e32_gfx12:
    case AMDGPU::V_MIN_NUM_F16_t16_e32_gfx12:
    case AMDGPU::V_MIN_NUM_F32_e32_gfx12:
    case AMDGPU::V_MIN_NUM_F64_e32_gfx12:
    case AMDGPU::V_MIN_U16_e32_vi:
    case AMDGPU::V_MIN_U32_e32_gfx10:
    case AMDGPU::V_MIN_U32_e32_gfx11:
    case AMDGPU::V_MIN_U32_e32_gfx12:
    case AMDGPU::V_MIN_U32_e32_gfx6_gfx7:
    case AMDGPU::V_MIN_U32_e32_vi:
    case AMDGPU::V_MUL_DX9_ZERO_F32_e32_gfx11:
    case AMDGPU::V_MUL_DX9_ZERO_F32_e32_gfx12:
    case AMDGPU::V_MUL_F16_e32_gfx10:
    case AMDGPU::V_MUL_F16_e32_vi:
    case AMDGPU::V_MUL_F16_fake16_e32_gfx11:
    case AMDGPU::V_MUL_F16_fake16_e32_gfx12:
    case AMDGPU::V_MUL_F16_t16_e32_gfx11:
    case AMDGPU::V_MUL_F16_t16_e32_gfx12:
    case AMDGPU::V_MUL_F32_e32_gfx10:
    case AMDGPU::V_MUL_F32_e32_gfx11:
    case AMDGPU::V_MUL_F32_e32_gfx12:
    case AMDGPU::V_MUL_F32_e32_gfx6_gfx7:
    case AMDGPU::V_MUL_F32_e32_vi:
    case AMDGPU::V_MUL_F64_e32_gfx12:
    case AMDGPU::V_MUL_HI_I32_I24_e32_gfx10:
    case AMDGPU::V_MUL_HI_I32_I24_e32_gfx11:
    case AMDGPU::V_MUL_HI_I32_I24_e32_gfx12:
    case AMDGPU::V_MUL_HI_I32_I24_e32_gfx6_gfx7:
    case AMDGPU::V_MUL_HI_I32_I24_e32_vi:
    case AMDGPU::V_MUL_HI_U32_U24_e32_gfx10:
    case AMDGPU::V_MUL_HI_U32_U24_e32_gfx11:
    case AMDGPU::V_MUL_HI_U32_U24_e32_gfx12:
    case AMDGPU::V_MUL_HI_U32_U24_e32_gfx6_gfx7:
    case AMDGPU::V_MUL_HI_U32_U24_e32_vi:
    case AMDGPU::V_MUL_I32_I24_e32_gfx10:
    case AMDGPU::V_MUL_I32_I24_e32_gfx11:
    case AMDGPU::V_MUL_I32_I24_e32_gfx12:
    case AMDGPU::V_MUL_I32_I24_e32_gfx6_gfx7:
    case AMDGPU::V_MUL_I32_I24_e32_vi:
    case AMDGPU::V_MUL_LEGACY_F32_e32_gfx10:
    case AMDGPU::V_MUL_LEGACY_F32_e32_gfx6_gfx7:
    case AMDGPU::V_MUL_LEGACY_F32_e32_vi:
    case AMDGPU::V_MUL_LO_U16_e32_vi:
    case AMDGPU::V_MUL_U32_U24_e32_gfx10:
    case AMDGPU::V_MUL_U32_U24_e32_gfx11:
    case AMDGPU::V_MUL_U32_U24_e32_gfx12:
    case AMDGPU::V_MUL_U32_U24_e32_gfx6_gfx7:
    case AMDGPU::V_MUL_U32_U24_e32_vi:
    case AMDGPU::V_MUL_U64_e32_gfx1250:
    case AMDGPU::V_OR_B32_e32_gfx10:
    case AMDGPU::V_OR_B32_e32_gfx11:
    case AMDGPU::V_OR_B32_e32_gfx12:
    case AMDGPU::V_OR_B32_e32_gfx6_gfx7:
    case AMDGPU::V_OR_B32_e32_vi:
    case AMDGPU::V_PK_FMAC_F16_e32_gfx10:
    case AMDGPU::V_PK_FMAC_F16_e32_gfx11:
    case AMDGPU::V_PK_FMAC_F16_e32_gfx12:
    case AMDGPU::V_PK_FMAC_F16_e32_gfx9:
    case AMDGPU::V_PK_FMAC_F16_e32_vi:
    case AMDGPU::V_READLANE_B32_gfx6_gfx7:
    case AMDGPU::V_SUBBREV_CO_U32_e32_gfx9:
    case AMDGPU::V_SUBBREV_U32_e32_gfx6_gfx7:
    case AMDGPU::V_SUBBREV_U32_e32_vi:
    case AMDGPU::V_SUBB_CO_U32_e32_gfx9:
    case AMDGPU::V_SUBB_U32_e32_gfx6_gfx7:
    case AMDGPU::V_SUBB_U32_e32_vi:
    case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
    case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
    case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx12:
    case AMDGPU::V_SUBREV_CO_U32_e32_gfx9:
    case AMDGPU::V_SUBREV_F16_e32_gfx10:
    case AMDGPU::V_SUBREV_F16_e32_vi:
    case AMDGPU::V_SUBREV_F16_fake16_e32_gfx11:
    case AMDGPU::V_SUBREV_F16_fake16_e32_gfx12:
    case AMDGPU::V_SUBREV_F16_t16_e32_gfx11:
    case AMDGPU::V_SUBREV_F16_t16_e32_gfx12:
    case AMDGPU::V_SUBREV_F32_e32_gfx10:
    case AMDGPU::V_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_SUBREV_F32_e32_gfx6_gfx7:
    case AMDGPU::V_SUBREV_F32_e32_vi:
    case AMDGPU::V_SUBREV_I32_e32_gfx6_gfx7:
    case AMDGPU::V_SUBREV_NC_U32_e32_gfx10:
    case AMDGPU::V_SUBREV_NC_U32_e32_gfx11:
    case AMDGPU::V_SUBREV_NC_U32_e32_gfx12:
    case AMDGPU::V_SUBREV_U16_e32_vi:
    case AMDGPU::V_SUBREV_U32_e32_gfx9:
    case AMDGPU::V_SUBREV_U32_e32_vi:
    case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
    case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
    case AMDGPU::V_SUB_CO_CI_U32_e32_gfx12:
    case AMDGPU::V_SUB_CO_U32_e32_gfx9:
    case AMDGPU::V_SUB_F16_e32_gfx10:
    case AMDGPU::V_SUB_F16_e32_vi:
    case AMDGPU::V_SUB_F16_fake16_e32_gfx11:
    case AMDGPU::V_SUB_F16_fake16_e32_gfx12:
    case AMDGPU::V_SUB_F16_t16_e32_gfx11:
    case AMDGPU::V_SUB_F16_t16_e32_gfx12:
    case AMDGPU::V_SUB_F32_e32_gfx10:
    case AMDGPU::V_SUB_F32_e32_gfx11:
    case AMDGPU::V_SUB_F32_e32_gfx12:
    case AMDGPU::V_SUB_F32_e32_gfx6_gfx7:
    case AMDGPU::V_SUB_F32_e32_vi:
    case AMDGPU::V_SUB_I32_e32_gfx6_gfx7:
    case AMDGPU::V_SUB_NC_U32_e32_gfx10:
    case AMDGPU::V_SUB_NC_U32_e32_gfx11:
    case AMDGPU::V_SUB_NC_U32_e32_gfx12:
    case AMDGPU::V_SUB_U16_e32_vi:
    case AMDGPU::V_SUB_U32_e32_gfx9:
    case AMDGPU::V_SUB_U32_e32_vi:
    case AMDGPU::V_SUB_U64_e32_gfx1250:
    case AMDGPU::V_WRITELANE_B32_gfx6_gfx7:
    case AMDGPU::V_XNOR_B32_e32_gfx10:
    case AMDGPU::V_XNOR_B32_e32_gfx11:
    case AMDGPU::V_XNOR_B32_e32_gfx12:
    case AMDGPU::V_XNOR_B32_e32_vi:
    case AMDGPU::V_XOR_B32_e32_gfx10:
    case AMDGPU::V_XOR_B32_e32_gfx11:
    case AMDGPU::V_XOR_B32_e32_gfx12:
    case AMDGPU::V_XOR_B32_e32_gfx6_gfx7:
    case AMDGPU::V_XOR_B32_e32_vi: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 17;
      case 1:
        // op: src0
        return 0;
      case 2:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_FMAMK_F16_fake16_gfx11:
    case AMDGPU::V_FMAMK_F16_fake16_gfx12:
    case AMDGPU::V_FMAMK_F16_gfx10:
    case AMDGPU::V_FMAMK_F16_t16_gfx11:
    case AMDGPU::V_FMAMK_F16_t16_gfx12:
    case AMDGPU::V_FMAMK_F32_gfx10:
    case AMDGPU::V_FMAMK_F32_gfx11:
    case AMDGPU::V_FMAMK_F32_gfx12:
    case AMDGPU::V_FMAMK_F32_gfx940:
    case AMDGPU::V_FMAMK_F64_gfx1250:
    case AMDGPU::V_MADMK_F16_vi:
    case AMDGPU::V_MADMK_F32_gfx10:
    case AMDGPU::V_MADMK_F32_gfx6_gfx7:
    case AMDGPU::V_MADMK_F32_vi: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 17;
      case 1:
        // op: src0
        return 0;
      case 3:
        // op: src1
        return 9;
      case 2:
        // op: imm
        return 32;
      }
      break;
    }
    case AMDGPU::V_ACCVGPR_MOV_B32_vi:
    case AMDGPU::V_BFREV_B32_e32_gfx10:
    case AMDGPU::V_BFREV_B32_e32_gfx11:
    case AMDGPU::V_BFREV_B32_e32_gfx12:
    case AMDGPU::V_BFREV_B32_e32_gfx6_gfx7:
    case AMDGPU::V_BFREV_B32_e32_vi:
    case AMDGPU::V_CEIL_F16_e32_gfx10:
    case AMDGPU::V_CEIL_F16_e32_vi:
    case AMDGPU::V_CEIL_F16_fake16_e32_gfx11:
    case AMDGPU::V_CEIL_F16_fake16_e32_gfx12:
    case AMDGPU::V_CEIL_F16_t16_e32_gfx11:
    case AMDGPU::V_CEIL_F16_t16_e32_gfx12:
    case AMDGPU::V_CEIL_F32_e32_gfx10:
    case AMDGPU::V_CEIL_F32_e32_gfx11:
    case AMDGPU::V_CEIL_F32_e32_gfx12:
    case AMDGPU::V_CEIL_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CEIL_F32_e32_vi:
    case AMDGPU::V_CEIL_F64_e32_gfx10:
    case AMDGPU::V_CEIL_F64_e32_gfx11:
    case AMDGPU::V_CEIL_F64_e32_gfx12:
    case AMDGPU::V_CEIL_F64_e32_gfx7:
    case AMDGPU::V_CEIL_F64_e32_vi:
    case AMDGPU::V_CLS_I32_e32_gfx11:
    case AMDGPU::V_CLS_I32_e32_gfx12:
    case AMDGPU::V_CLZ_I32_U32_e32_gfx11:
    case AMDGPU::V_CLZ_I32_U32_e32_gfx12:
    case AMDGPU::V_COS_BF16V_COS_BF16_fake16_e32_gfx1250:
    case AMDGPU::V_COS_BF16V_COS_BF16_t16_e32_gfx1250:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_e32_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_e32_gfx12:
    case AMDGPU::V_COS_F16V_COS_F16_t16_e32_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_t16_e32_gfx12:
    case AMDGPU::V_COS_F16_e32_gfx10:
    case AMDGPU::V_COS_F16_e32_vi:
    case AMDGPU::V_COS_F32_e32_gfx10:
    case AMDGPU::V_COS_F32_e32_gfx11:
    case AMDGPU::V_COS_F32_e32_gfx12:
    case AMDGPU::V_COS_F32_e32_gfx6_gfx7:
    case AMDGPU::V_COS_F32_e32_vi:
    case AMDGPU::V_CTZ_I32_B32_e32_gfx11:
    case AMDGPU::V_CTZ_I32_B32_e32_gfx12:
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_fake16_e32_gfx1250:
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_t16_e32_gfx1250:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_e32_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_e32_gfx12:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_e32_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_e32_gfx12:
    case AMDGPU::V_CVT_F16_F32_e32_gfx10:
    case AMDGPU::V_CVT_F16_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F16_F32_e32_vi:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_fake16_e32_gfx1250:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_t16_e32_gfx1250:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_e32_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_e32_gfx12:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_e32_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_e32_gfx12:
    case AMDGPU::V_CVT_F16_I16_e32_gfx10:
    case AMDGPU::V_CVT_F16_I16_e32_vi:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_e32_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_e32_gfx12:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_e32_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_e32_gfx12:
    case AMDGPU::V_CVT_F16_U16_e32_gfx10:
    case AMDGPU::V_CVT_F16_U16_e32_vi:
    case AMDGPU::V_CVT_F32_BF16_e32_vi:
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_fake16_e32_gfx1250:
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_t16_e32_gfx1250:
    case AMDGPU::V_CVT_F32_BF8_e32_gfx12:
    case AMDGPU::V_CVT_F32_BF8_e32_vi:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_e32_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_e32_gfx12:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_e32_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_e32_gfx12:
    case AMDGPU::V_CVT_F32_F16_e32_gfx10:
    case AMDGPU::V_CVT_F32_F16_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_F16_e32_vi:
    case AMDGPU::V_CVT_F32_F64_e32_gfx10:
    case AMDGPU::V_CVT_F32_F64_e32_gfx11:
    case AMDGPU::V_CVT_F32_F64_e32_gfx12:
    case AMDGPU::V_CVT_F32_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_F64_e32_vi:
    case AMDGPU::V_CVT_F32_FP8_e32_gfx11:
    case AMDGPU::V_CVT_F32_FP8_e32_gfx12:
    case AMDGPU::V_CVT_F32_FP8_e32_gfx1250:
    case AMDGPU::V_CVT_F32_FP8_e32_vi:
    case AMDGPU::V_CVT_F32_I32_e32_gfx10:
    case AMDGPU::V_CVT_F32_I32_e32_gfx11:
    case AMDGPU::V_CVT_F32_I32_e32_gfx12:
    case AMDGPU::V_CVT_F32_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_I32_e32_vi:
    case AMDGPU::V_CVT_F32_U32_e32_gfx10:
    case AMDGPU::V_CVT_F32_U32_e32_gfx11:
    case AMDGPU::V_CVT_F32_U32_e32_gfx12:
    case AMDGPU::V_CVT_F32_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_U32_e32_vi:
    case AMDGPU::V_CVT_F32_UBYTE0_e32_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE0_e32_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE0_e32_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE0_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_UBYTE0_e32_vi:
    case AMDGPU::V_CVT_F32_UBYTE1_e32_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE1_e32_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE1_e32_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE1_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_UBYTE1_e32_vi:
    case AMDGPU::V_CVT_F32_UBYTE2_e32_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE2_e32_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE2_e32_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE2_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_UBYTE2_e32_vi:
    case AMDGPU::V_CVT_F32_UBYTE3_e32_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE3_e32_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE3_e32_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE3_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_UBYTE3_e32_vi:
    case AMDGPU::V_CVT_F64_F32_e32_gfx10:
    case AMDGPU::V_CVT_F64_F32_e32_gfx11:
    case AMDGPU::V_CVT_F64_F32_e32_gfx12:
    case AMDGPU::V_CVT_F64_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F64_F32_e32_vi:
    case AMDGPU::V_CVT_F64_I32_e32_gfx10:
    case AMDGPU::V_CVT_F64_I32_e32_gfx11:
    case AMDGPU::V_CVT_F64_I32_e32_gfx12:
    case AMDGPU::V_CVT_F64_I32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F64_I32_e32_vi:
    case AMDGPU::V_CVT_F64_U32_e32_gfx10:
    case AMDGPU::V_CVT_F64_U32_e32_gfx11:
    case AMDGPU::V_CVT_F64_U32_e32_gfx12:
    case AMDGPU::V_CVT_F64_U32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_F64_U32_e32_vi:
    case AMDGPU::V_CVT_FLOOR_I32_F32_e32_gfx11:
    case AMDGPU::V_CVT_FLOOR_I32_F32_e32_gfx12:
    case AMDGPU::V_CVT_FLR_I32_F32_e32_gfx10:
    case AMDGPU::V_CVT_FLR_I32_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_FLR_I32_F32_e32_vi:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_e32_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_e32_gfx12:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_e32_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_e32_gfx12:
    case AMDGPU::V_CVT_I16_F16_e32_gfx10:
    case AMDGPU::V_CVT_I16_F16_e32_vi:
    case AMDGPU::V_CVT_I32_F32_e32_gfx10:
    case AMDGPU::V_CVT_I32_F32_e32_gfx11:
    case AMDGPU::V_CVT_I32_F32_e32_gfx12:
    case AMDGPU::V_CVT_I32_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_I32_F32_e32_vi:
    case AMDGPU::V_CVT_I32_F64_e32_gfx10:
    case AMDGPU::V_CVT_I32_F64_e32_gfx11:
    case AMDGPU::V_CVT_I32_F64_e32_gfx12:
    case AMDGPU::V_CVT_I32_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_I32_F64_e32_vi:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_e32_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_e32_gfx12:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_e32_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_e32_gfx12:
    case AMDGPU::V_CVT_NEAREST_I32_F32_e32_gfx11:
    case AMDGPU::V_CVT_NEAREST_I32_F32_e32_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e32_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e32_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e32_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e32_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16_e32_gfx10:
    case AMDGPU::V_CVT_NORM_I16_F16_e32_vi:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e32_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e32_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e32_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e32_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16_e32_gfx10:
    case AMDGPU::V_CVT_NORM_U16_F16_e32_vi:
    case AMDGPU::V_CVT_OFF_F32_I4_e32_gfx10:
    case AMDGPU::V_CVT_OFF_F32_I4_e32_gfx11:
    case AMDGPU::V_CVT_OFF_F32_I4_e32_gfx12:
    case AMDGPU::V_CVT_OFF_F32_I4_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_OFF_F32_I4_e32_vi:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_fake16_e32_gfx1250:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_t16_e32_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_fake16_e32_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_t16_e32_gfx1250:
    case AMDGPU::V_CVT_PK_F32_BF8_e32_vi:
    case AMDGPU::V_CVT_PK_F32_BF8_fake16_e32_gfx12:
    case AMDGPU::V_CVT_PK_F32_BF8_t16_e32_gfx12:
    case AMDGPU::V_CVT_PK_F32_FP8_e32_vi:
    case AMDGPU::V_CVT_PK_F32_FP8_fake16_e32_gfx12:
    case AMDGPU::V_CVT_PK_F32_FP8_t16_e32_gfx12:
    case AMDGPU::V_CVT_RPI_I32_F32_e32_gfx10:
    case AMDGPU::V_CVT_RPI_I32_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_RPI_I32_F32_e32_vi:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_e32_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_e32_gfx12:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_e32_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_e32_gfx12:
    case AMDGPU::V_CVT_U16_F16_e32_gfx10:
    case AMDGPU::V_CVT_U16_F16_e32_vi:
    case AMDGPU::V_CVT_U32_F32_e32_gfx10:
    case AMDGPU::V_CVT_U32_F32_e32_gfx11:
    case AMDGPU::V_CVT_U32_F32_e32_gfx12:
    case AMDGPU::V_CVT_U32_F32_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_U32_F32_e32_vi:
    case AMDGPU::V_CVT_U32_F64_e32_gfx10:
    case AMDGPU::V_CVT_U32_F64_e32_gfx11:
    case AMDGPU::V_CVT_U32_F64_e32_gfx12:
    case AMDGPU::V_CVT_U32_F64_e32_gfx6_gfx7:
    case AMDGPU::V_CVT_U32_F64_e32_vi:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_e32_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_e32_gfx12:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_e32_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_e32_gfx12:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_fake16_e32_gfx1250:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_t16_e32_gfx1250:
    case AMDGPU::V_EXP_F16_e32_gfx10:
    case AMDGPU::V_EXP_F16_e32_vi:
    case AMDGPU::V_EXP_F16_fake16_e32_gfx11:
    case AMDGPU::V_EXP_F16_fake16_e32_gfx12:
    case AMDGPU::V_EXP_F16_t16_e32_gfx11:
    case AMDGPU::V_EXP_F16_t16_e32_gfx12:
    case AMDGPU::V_EXP_F32_e32_gfx10:
    case AMDGPU::V_EXP_F32_e32_gfx11:
    case AMDGPU::V_EXP_F32_e32_gfx12:
    case AMDGPU::V_EXP_F32_e32_gfx6_gfx7:
    case AMDGPU::V_EXP_F32_e32_vi:
    case AMDGPU::V_EXP_LEGACY_F32_e32_gfx7:
    case AMDGPU::V_EXP_LEGACY_F32_e32_vi:
    case AMDGPU::V_FFBH_I32_e32_gfx10:
    case AMDGPU::V_FFBH_I32_e32_gfx6_gfx7:
    case AMDGPU::V_FFBH_I32_e32_vi:
    case AMDGPU::V_FFBH_U32_e32_gfx10:
    case AMDGPU::V_FFBH_U32_e32_gfx6_gfx7:
    case AMDGPU::V_FFBH_U32_e32_vi:
    case AMDGPU::V_FFBL_B32_e32_gfx10:
    case AMDGPU::V_FFBL_B32_e32_gfx6_gfx7:
    case AMDGPU::V_FFBL_B32_e32_vi:
    case AMDGPU::V_FLOOR_F16_e32_gfx10:
    case AMDGPU::V_FLOOR_F16_e32_vi:
    case AMDGPU::V_FLOOR_F16_fake16_e32_gfx11:
    case AMDGPU::V_FLOOR_F16_fake16_e32_gfx12:
    case AMDGPU::V_FLOOR_F16_t16_e32_gfx11:
    case AMDGPU::V_FLOOR_F16_t16_e32_gfx12:
    case AMDGPU::V_FLOOR_F32_e32_gfx10:
    case AMDGPU::V_FLOOR_F32_e32_gfx11:
    case AMDGPU::V_FLOOR_F32_e32_gfx12:
    case AMDGPU::V_FLOOR_F32_e32_gfx6_gfx7:
    case AMDGPU::V_FLOOR_F32_e32_vi:
    case AMDGPU::V_FLOOR_F64_e32_gfx10:
    case AMDGPU::V_FLOOR_F64_e32_gfx11:
    case AMDGPU::V_FLOOR_F64_e32_gfx12:
    case AMDGPU::V_FLOOR_F64_e32_gfx7:
    case AMDGPU::V_FLOOR_F64_e32_vi:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_e32_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_e32_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_e32_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_e32_gfx12:
    case AMDGPU::V_FRACT_F16_e32_gfx10:
    case AMDGPU::V_FRACT_F16_e32_vi:
    case AMDGPU::V_FRACT_F32_e32_gfx10:
    case AMDGPU::V_FRACT_F32_e32_gfx11:
    case AMDGPU::V_FRACT_F32_e32_gfx12:
    case AMDGPU::V_FRACT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_FRACT_F32_e32_vi:
    case AMDGPU::V_FRACT_F64_e32_gfx10:
    case AMDGPU::V_FRACT_F64_e32_gfx11:
    case AMDGPU::V_FRACT_F64_e32_gfx12:
    case AMDGPU::V_FRACT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_FRACT_F64_e32_vi:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e32_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e32_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e32_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e32_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16_e32_gfx10:
    case AMDGPU::V_FREXP_EXP_I16_F16_e32_vi:
    case AMDGPU::V_FREXP_EXP_I32_F32_e32_gfx10:
    case AMDGPU::V_FREXP_EXP_I32_F32_e32_gfx11:
    case AMDGPU::V_FREXP_EXP_I32_F32_e32_gfx12:
    case AMDGPU::V_FREXP_EXP_I32_F32_e32_gfx6_gfx7:
    case AMDGPU::V_FREXP_EXP_I32_F32_e32_vi:
    case AMDGPU::V_FREXP_EXP_I32_F64_e32_gfx10:
    case AMDGPU::V_FREXP_EXP_I32_F64_e32_gfx11:
    case AMDGPU::V_FREXP_EXP_I32_F64_e32_gfx12:
    case AMDGPU::V_FREXP_EXP_I32_F64_e32_gfx6_gfx7:
    case AMDGPU::V_FREXP_EXP_I32_F64_e32_vi:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e32_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e32_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e32_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e32_gfx12:
    case AMDGPU::V_FREXP_MANT_F16_e32_gfx10:
    case AMDGPU::V_FREXP_MANT_F16_e32_vi:
    case AMDGPU::V_FREXP_MANT_F32_e32_gfx10:
    case AMDGPU::V_FREXP_MANT_F32_e32_gfx11:
    case AMDGPU::V_FREXP_MANT_F32_e32_gfx12:
    case AMDGPU::V_FREXP_MANT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_FREXP_MANT_F32_e32_vi:
    case AMDGPU::V_FREXP_MANT_F64_e32_gfx10:
    case AMDGPU::V_FREXP_MANT_F64_e32_gfx11:
    case AMDGPU::V_FREXP_MANT_F64_e32_gfx12:
    case AMDGPU::V_FREXP_MANT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_FREXP_MANT_F64_e32_vi:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_fake16_e32_gfx1250:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_t16_e32_gfx1250:
    case AMDGPU::V_LOG_CLAMP_F32_e32_gfx6_gfx7:
    case AMDGPU::V_LOG_F16_e32_gfx10:
    case AMDGPU::V_LOG_F16_e32_vi:
    case AMDGPU::V_LOG_F16_fake16_e32_gfx11:
    case AMDGPU::V_LOG_F16_fake16_e32_gfx12:
    case AMDGPU::V_LOG_F16_t16_e32_gfx11:
    case AMDGPU::V_LOG_F16_t16_e32_gfx12:
    case AMDGPU::V_LOG_F32_e32_gfx10:
    case AMDGPU::V_LOG_F32_e32_gfx11:
    case AMDGPU::V_LOG_F32_e32_gfx12:
    case AMDGPU::V_LOG_F32_e32_gfx6_gfx7:
    case AMDGPU::V_LOG_F32_e32_vi:
    case AMDGPU::V_LOG_LEGACY_F32_e32_gfx7:
    case AMDGPU::V_LOG_LEGACY_F32_e32_vi:
    case AMDGPU::V_MOVRELD_B32_e32_gfx10:
    case AMDGPU::V_MOVRELD_B32_e32_gfx11:
    case AMDGPU::V_MOVRELD_B32_e32_gfx12:
    case AMDGPU::V_MOVRELD_B32_e32_gfx6_gfx7:
    case AMDGPU::V_MOVRELD_B32_e32_vi:
    case AMDGPU::V_MOVRELSD_2_B32_e32_gfx10:
    case AMDGPU::V_MOVRELSD_2_B32_e32_gfx11:
    case AMDGPU::V_MOVRELSD_2_B32_e32_gfx12:
    case AMDGPU::V_MOVRELSD_B32_e32_gfx10:
    case AMDGPU::V_MOVRELSD_B32_e32_gfx11:
    case AMDGPU::V_MOVRELSD_B32_e32_gfx12:
    case AMDGPU::V_MOVRELSD_B32_e32_gfx6_gfx7:
    case AMDGPU::V_MOVRELSD_B32_e32_vi:
    case AMDGPU::V_MOVRELS_B32_e32_gfx10:
    case AMDGPU::V_MOVRELS_B32_e32_gfx11:
    case AMDGPU::V_MOVRELS_B32_e32_gfx12:
    case AMDGPU::V_MOVRELS_B32_e32_gfx6_gfx7:
    case AMDGPU::V_MOVRELS_B32_e32_vi:
    case AMDGPU::V_MOV_B16_t16_e32_gfx11:
    case AMDGPU::V_MOV_B16_t16_e32_gfx12:
    case AMDGPU::V_MOV_B32_e32_gfx10:
    case AMDGPU::V_MOV_B32_e32_gfx11:
    case AMDGPU::V_MOV_B32_e32_gfx12:
    case AMDGPU::V_MOV_B32_e32_gfx6_gfx7:
    case AMDGPU::V_MOV_B32_e32_vi:
    case AMDGPU::V_MOV_B64_e32_gfx1250:
    case AMDGPU::V_MOV_B64_e32_vi:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_e32_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_e32_gfx12:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_e32_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_e32_gfx12:
    case AMDGPU::V_NOT_B32_e32_gfx10:
    case AMDGPU::V_NOT_B32_e32_gfx11:
    case AMDGPU::V_NOT_B32_e32_gfx12:
    case AMDGPU::V_NOT_B32_e32_gfx6_gfx7:
    case AMDGPU::V_NOT_B32_e32_vi:
    case AMDGPU::V_PERMLANE64_B32_gfx11:
    case AMDGPU::V_PERMLANE64_B32_gfx12:
    case AMDGPU::V_PRNG_B32_e32_gfx1250:
    case AMDGPU::V_PRNG_B32_e32_vi:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_fake16_e32_gfx1250:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_t16_e32_gfx1250:
    case AMDGPU::V_RCP_CLAMP_F32_e32_gfx6_gfx7:
    case AMDGPU::V_RCP_CLAMP_F64_e32_gfx6_gfx7:
    case AMDGPU::V_RCP_F16_e32_gfx10:
    case AMDGPU::V_RCP_F16_e32_vi:
    case AMDGPU::V_RCP_F16_fake16_e32_gfx11:
    case AMDGPU::V_RCP_F16_fake16_e32_gfx12:
    case AMDGPU::V_RCP_F16_t16_e32_gfx11:
    case AMDGPU::V_RCP_F16_t16_e32_gfx12:
    case AMDGPU::V_RCP_F32_e32_gfx10:
    case AMDGPU::V_RCP_F32_e32_gfx11:
    case AMDGPU::V_RCP_F32_e32_gfx12:
    case AMDGPU::V_RCP_F32_e32_gfx6_gfx7:
    case AMDGPU::V_RCP_F32_e32_vi:
    case AMDGPU::V_RCP_F64_e32_gfx10:
    case AMDGPU::V_RCP_F64_e32_gfx11:
    case AMDGPU::V_RCP_F64_e32_gfx12:
    case AMDGPU::V_RCP_F64_e32_gfx6_gfx7:
    case AMDGPU::V_RCP_F64_e32_vi:
    case AMDGPU::V_RCP_IFLAG_F32_e32_gfx10:
    case AMDGPU::V_RCP_IFLAG_F32_e32_gfx11:
    case AMDGPU::V_RCP_IFLAG_F32_e32_gfx12:
    case AMDGPU::V_RCP_IFLAG_F32_e32_gfx6_gfx7:
    case AMDGPU::V_RCP_IFLAG_F32_e32_vi:
    case AMDGPU::V_RCP_LEGACY_F32_e32_gfx6_gfx7:
    case AMDGPU::V_READFIRSTLANE_B32_gfx10:
    case AMDGPU::V_READFIRSTLANE_B32_gfx11:
    case AMDGPU::V_READFIRSTLANE_B32_gfx12:
    case AMDGPU::V_READFIRSTLANE_B32_gfx6_gfx7:
    case AMDGPU::V_READFIRSTLANE_B32_vi:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_e32_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_e32_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_e32_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_e32_gfx12:
    case AMDGPU::V_RNDNE_F16_e32_gfx10:
    case AMDGPU::V_RNDNE_F16_e32_vi:
    case AMDGPU::V_RNDNE_F32_e32_gfx10:
    case AMDGPU::V_RNDNE_F32_e32_gfx11:
    case AMDGPU::V_RNDNE_F32_e32_gfx12:
    case AMDGPU::V_RNDNE_F32_e32_gfx6_gfx7:
    case AMDGPU::V_RNDNE_F32_e32_vi:
    case AMDGPU::V_RNDNE_F64_e32_gfx10:
    case AMDGPU::V_RNDNE_F64_e32_gfx11:
    case AMDGPU::V_RNDNE_F64_e32_gfx12:
    case AMDGPU::V_RNDNE_F64_e32_gfx7:
    case AMDGPU::V_RNDNE_F64_e32_vi:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_fake16_e32_gfx1250:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_t16_e32_gfx1250:
    case AMDGPU::V_RSQ_CLAMP_F32_e32_gfx6_gfx7:
    case AMDGPU::V_RSQ_CLAMP_F64_e32_gfx6_gfx7:
    case AMDGPU::V_RSQ_F16_e32_gfx10:
    case AMDGPU::V_RSQ_F16_e32_vi:
    case AMDGPU::V_RSQ_F16_fake16_e32_gfx11:
    case AMDGPU::V_RSQ_F16_fake16_e32_gfx12:
    case AMDGPU::V_RSQ_F16_t16_e32_gfx11:
    case AMDGPU::V_RSQ_F16_t16_e32_gfx12:
    case AMDGPU::V_RSQ_F32_e32_gfx10:
    case AMDGPU::V_RSQ_F32_e32_gfx11:
    case AMDGPU::V_RSQ_F32_e32_gfx12:
    case AMDGPU::V_RSQ_F32_e32_gfx6_gfx7:
    case AMDGPU::V_RSQ_F32_e32_vi:
    case AMDGPU::V_RSQ_F64_e32_gfx10:
    case AMDGPU::V_RSQ_F64_e32_gfx11:
    case AMDGPU::V_RSQ_F64_e32_gfx12:
    case AMDGPU::V_RSQ_F64_e32_gfx6_gfx7:
    case AMDGPU::V_RSQ_F64_e32_vi:
    case AMDGPU::V_RSQ_LEGACY_F32_e32_gfx6_gfx7:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_fake16_e32_gfx1250:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_t16_e32_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_fake16_e32_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_t16_e32_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e32_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e32_gfx12:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e32_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e32_gfx12:
    case AMDGPU::V_SAT_PK_U8_I16_e32_gfx10:
    case AMDGPU::V_SAT_PK_U8_I16_e32_vi:
    case AMDGPU::V_SCREEN_PARTITION_4SE_B32_e32_vi:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_fake16_e32_gfx1250:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_t16_e32_gfx1250:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_e32_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_e32_gfx12:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_e32_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_e32_gfx12:
    case AMDGPU::V_SIN_F16_e32_gfx10:
    case AMDGPU::V_SIN_F16_e32_vi:
    case AMDGPU::V_SIN_F32_e32_gfx10:
    case AMDGPU::V_SIN_F32_e32_gfx11:
    case AMDGPU::V_SIN_F32_e32_gfx12:
    case AMDGPU::V_SIN_F32_e32_gfx6_gfx7:
    case AMDGPU::V_SIN_F32_e32_vi:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_fake16_e32_gfx1250:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_t16_e32_gfx1250:
    case AMDGPU::V_SQRT_F16_e32_gfx10:
    case AMDGPU::V_SQRT_F16_e32_vi:
    case AMDGPU::V_SQRT_F16_fake16_e32_gfx11:
    case AMDGPU::V_SQRT_F16_fake16_e32_gfx12:
    case AMDGPU::V_SQRT_F16_t16_e32_gfx11:
    case AMDGPU::V_SQRT_F16_t16_e32_gfx12:
    case AMDGPU::V_SQRT_F32_e32_gfx10:
    case AMDGPU::V_SQRT_F32_e32_gfx11:
    case AMDGPU::V_SQRT_F32_e32_gfx12:
    case AMDGPU::V_SQRT_F32_e32_gfx6_gfx7:
    case AMDGPU::V_SQRT_F32_e32_vi:
    case AMDGPU::V_SQRT_F64_e32_gfx10:
    case AMDGPU::V_SQRT_F64_e32_gfx11:
    case AMDGPU::V_SQRT_F64_e32_gfx12:
    case AMDGPU::V_SQRT_F64_e32_gfx6_gfx7:
    case AMDGPU::V_SQRT_F64_e32_vi:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_fake16_e32_gfx1250:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_t16_e32_gfx1250:
    case AMDGPU::V_TANH_F16V_TANH_F16_fake16_e32_gfx1250:
    case AMDGPU::V_TANH_F16V_TANH_F16_t16_e32_gfx1250:
    case AMDGPU::V_TANH_F32_e32_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_e32_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_e32_gfx12:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_e32_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_e32_gfx12:
    case AMDGPU::V_TRUNC_F16_e32_gfx10:
    case AMDGPU::V_TRUNC_F16_e32_vi:
    case AMDGPU::V_TRUNC_F32_e32_gfx10:
    case AMDGPU::V_TRUNC_F32_e32_gfx11:
    case AMDGPU::V_TRUNC_F32_e32_gfx12:
    case AMDGPU::V_TRUNC_F32_e32_gfx6_gfx7:
    case AMDGPU::V_TRUNC_F32_e32_vi:
    case AMDGPU::V_TRUNC_F64_e32_gfx10:
    case AMDGPU::V_TRUNC_F64_e32_gfx11:
    case AMDGPU::V_TRUNC_F64_e32_gfx12:
    case AMDGPU::V_TRUNC_F64_e32_gfx7:
    case AMDGPU::V_TRUNC_F64_e32_vi: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 17;
      case 1:
        // op: src0
        return 0;
      }
      break;
    }
    case AMDGPU::V_SWAPREL_B32_gfx10:
    case AMDGPU::V_SWAPREL_B32_gfx11:
    case AMDGPU::V_SWAPREL_B32_gfx12:
    case AMDGPU::V_SWAP_B16_gfx11:
    case AMDGPU::V_SWAP_B16_gfx12:
    case AMDGPU::V_SWAP_B32_gfx10:
    case AMDGPU::V_SWAP_B32_gfx11:
    case AMDGPU::V_SWAP_B32_gfx12:
    case AMDGPU::V_SWAP_B32_vi: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 17;
      case 2:
        // op: src0
        return 0;
      }
      break;
    }
    case AMDGPU::V_PERMLANE16_SWAP_B32_e32_gfx1250:
    case AMDGPU::V_PERMLANE16_SWAP_B32_e32_gfx9:
    case AMDGPU::V_PERMLANE32_SWAP_B32_e32_gfx9: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 17;
      case 3:
        // op: src0
        return 0;
      }
      break;
    }
    case AMDGPU::V_INTERP_MOV_F32_gfx10:
    case AMDGPU::V_INTERP_MOV_F32_si:
    case AMDGPU::V_INTERP_MOV_F32_vi:
    case AMDGPU::V_INTERP_P1_F32_16bank_gfx10:
    case AMDGPU::V_INTERP_P1_F32_16bank_si:
    case AMDGPU::V_INTERP_P1_F32_16bank_vi:
    case AMDGPU::V_INTERP_P1_F32_gfx10:
    case AMDGPU::V_INTERP_P1_F32_si:
    case AMDGPU::V_INTERP_P1_F32_vi: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 18;
      case 1:
        // op: vsrc
        return 0;
      case 3:
        // op: attrchan
        return 8;
      case 2:
        // op: attr
        return 10;
      }
      break;
    }
    case AMDGPU::V_INTERP_P2_F32_gfx10:
    case AMDGPU::V_INTERP_P2_F32_si:
    case AMDGPU::V_INTERP_P2_F32_vi: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 18;
      case 2:
        // op: vsrc
        return 0;
      case 4:
        // op: attrchan
        return 8;
      case 3:
        // op: attr
        return 10;
      }
      break;
    }
    case AMDGPU::DS_ORDERED_COUNT_vi: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 25;
      case 1:
        // op: addr
        return 32;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_APPEND_vi:
    case AMDGPU::DS_CONSUME_vi:
    case AMDGPU::DS_READ_ADDTID_B32_vi: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 25;
      case 2:
        // op: gds
        return 16;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_READ_B128_vi:
    case AMDGPU::DS_READ_B128_vi_gfx9:
    case AMDGPU::DS_READ_B32_vi:
    case AMDGPU::DS_READ_B32_vi_gfx9:
    case AMDGPU::DS_READ_B64_TR_B16_vi:
    case AMDGPU::DS_READ_B64_TR_B4_vi:
    case AMDGPU::DS_READ_B64_TR_B8_vi:
    case AMDGPU::DS_READ_B64_vi:
    case AMDGPU::DS_READ_B64_vi_gfx9:
    case AMDGPU::DS_READ_B96_TR_B6_vi:
    case AMDGPU::DS_READ_B96_vi:
    case AMDGPU::DS_READ_B96_vi_gfx9:
    case AMDGPU::DS_READ_I16_vi:
    case AMDGPU::DS_READ_I16_vi_gfx9:
    case AMDGPU::DS_READ_I8_D16_HI_vi:
    case AMDGPU::DS_READ_I8_D16_vi:
    case AMDGPU::DS_READ_I8_vi:
    case AMDGPU::DS_READ_I8_vi_gfx9:
    case AMDGPU::DS_READ_U16_D16_HI_vi:
    case AMDGPU::DS_READ_U16_D16_vi:
    case AMDGPU::DS_READ_U16_vi:
    case AMDGPU::DS_READ_U16_vi_gfx9:
    case AMDGPU::DS_READ_U8_D16_HI_vi:
    case AMDGPU::DS_READ_U8_D16_vi:
    case AMDGPU::DS_READ_U8_vi:
    case AMDGPU::DS_READ_U8_vi_gfx9:
    case AMDGPU::DS_SWIZZLE_B32_vi: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 25;
      case 3:
        // op: gds
        return 16;
      case 1:
        // op: addr
        return 32;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_READ2ST64_B32_vi:
    case AMDGPU::DS_READ2ST64_B32_vi_gfx9:
    case AMDGPU::DS_READ2ST64_B64_vi:
    case AMDGPU::DS_READ2ST64_B64_vi_gfx9:
    case AMDGPU::DS_READ2_B32_vi:
    case AMDGPU::DS_READ2_B32_vi_gfx9:
    case AMDGPU::DS_READ2_B64_vi:
    case AMDGPU::DS_READ2_B64_vi_gfx9: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 25;
      case 4:
        // op: gds
        return 16;
      case 1:
        // op: addr
        return 32;
      case 2:
        // op: offset0
        return 0;
      case 3:
        // op: offset1
        return 8;
      }
      break;
    }
    case AMDGPU::GLOBAL_LOAD_DWORD_ADDTID_gfx12:
    case AMDGPU::SCRATCH_LOAD_BLOCK_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX2_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORD_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_SSHORT_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_ST_gfx12:
    case AMDGPU::SCRATCH_LOAD_USHORT_ST_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 32;
      case 2:
        // op: cpol
        return 7;
      case 1:
        // op: offset
        return 72;
      }
      break;
    }
    case AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B128_gfx1250:
    case AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B32_gfx1250:
    case AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B64_gfx1250:
    case AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B8_gfx1250:
    case AMDGPU::CLUSTER_LOAD_B128_gfx1250:
    case AMDGPU::CLUSTER_LOAD_B32_gfx1250:
    case AMDGPU::CLUSTER_LOAD_B64_gfx1250:
    case AMDGPU::FLAT_LOAD_DWORDX2_gfx12:
    case AMDGPU::FLAT_LOAD_DWORDX3_gfx12:
    case AMDGPU::FLAT_LOAD_DWORDX4_gfx12:
    case AMDGPU::FLAT_LOAD_DWORD_gfx12:
    case AMDGPU::FLAT_LOAD_MONITOR_B128_gfx1250:
    case AMDGPU::FLAT_LOAD_MONITOR_B32_gfx1250:
    case AMDGPU::FLAT_LOAD_MONITOR_B64_gfx1250:
    case AMDGPU::FLAT_LOAD_SBYTE_D16_HI_gfx12:
    case AMDGPU::FLAT_LOAD_SBYTE_D16_gfx12:
    case AMDGPU::FLAT_LOAD_SBYTE_gfx12:
    case AMDGPU::FLAT_LOAD_SHORT_D16_HI_gfx12:
    case AMDGPU::FLAT_LOAD_SHORT_D16_gfx12:
    case AMDGPU::FLAT_LOAD_SSHORT_gfx12:
    case AMDGPU::FLAT_LOAD_UBYTE_D16_HI_gfx12:
    case AMDGPU::FLAT_LOAD_UBYTE_D16_gfx12:
    case AMDGPU::FLAT_LOAD_UBYTE_gfx12:
    case AMDGPU::FLAT_LOAD_USHORT_gfx12:
    case AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B128_gfx1250:
    case AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B32_gfx1250:
    case AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B64_gfx1250:
    case AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B8_gfx1250:
    case AMDGPU::GLOBAL_LOAD_BLOCK_gfx12:
    case AMDGPU::GLOBAL_LOAD_DWORDX2_gfx12:
    case AMDGPU::GLOBAL_LOAD_DWORDX3_gfx12:
    case AMDGPU::GLOBAL_LOAD_DWORDX4_gfx12:
    case AMDGPU::GLOBAL_LOAD_DWORD_gfx12:
    case AMDGPU::GLOBAL_LOAD_MONITOR_B128_gfx1250:
    case AMDGPU::GLOBAL_LOAD_MONITOR_B32_gfx1250:
    case AMDGPU::GLOBAL_LOAD_MONITOR_B64_gfx1250:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_gfx12:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_gfx12:
    case AMDGPU::GLOBAL_LOAD_SBYTE_gfx12:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_gfx12:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_gfx12:
    case AMDGPU::GLOBAL_LOAD_SSHORT_gfx12:
    case AMDGPU::GLOBAL_LOAD_TR4_B64_gfx1250:
    case AMDGPU::GLOBAL_LOAD_TR6_B96_gfx1250:
    case AMDGPU::GLOBAL_LOAD_TR_B128_w32_gfx12:
    case AMDGPU::GLOBAL_LOAD_TR_B128_w32_gfx1250:
    case AMDGPU::GLOBAL_LOAD_TR_B128_w64_gfx12:
    case AMDGPU::GLOBAL_LOAD_TR_B64_w32_gfx12:
    case AMDGPU::GLOBAL_LOAD_TR_B64_w32_gfx1250:
    case AMDGPU::GLOBAL_LOAD_TR_B64_w64_gfx12:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_gfx12:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_gfx12:
    case AMDGPU::GLOBAL_LOAD_UBYTE_gfx12:
    case AMDGPU::GLOBAL_LOAD_USHORT_gfx12:
    case AMDGPU::SCRATCH_LOAD_BLOCK_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX2_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORD_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_gfx12:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_gfx12:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_gfx12:
    case AMDGPU::SCRATCH_LOAD_SSHORT_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_gfx12:
    case AMDGPU::SCRATCH_LOAD_USHORT_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 32;
      case 3:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr
        return 64;
      case 2:
        // op: offset
        return 72;
      }
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_F32_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_ADD_F64_RTN_gfx1250:
    case AMDGPU::FLAT_ATOMIC_ADD_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_AND_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_AND_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_COND_SUB_U32_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_CSUB_U32_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_DEC_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_FMAX_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_FMIN_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_INC_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_INC_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_MAX_F64_RTN_gfx1250:
    case AMDGPU::FLAT_ATOMIC_MIN_F64_RTN_gfx1250:
    case AMDGPU::FLAT_ATOMIC_OR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_OR_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_BF16_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_F16_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMAX_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMIN_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SUB_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SWAP_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMAX_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMIN_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_XOR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_RTN_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_ADD_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_AND_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CSUB_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_DEC_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_INC_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_RTN_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_RTN_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_OR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SUB_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_XOR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 32;
      case 4:
        // op: cpol
        return 7;
      case 2:
        // op: vdata
        return 55;
      case 1:
        // op: vaddr
        return 64;
      case 3:
        // op: offset
        return 72;
      }
      break;
    }
    case AMDGPU::SCRATCH_LOAD_DWORDX2_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_DWORD_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_SBYTE_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_SSHORT_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_UBYTE_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_USHORT_ST_gfx940: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 55;
      case 2:
        // op: cpol
        return 16;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_CMPSTORE_RTN_B32_gfx12:
    case AMDGPU::DS_CMPSTORE_RTN_B64_gfx12:
    case AMDGPU::DS_MSKOR_RTN_B32_gfx12:
    case AMDGPU::DS_MSKOR_RTN_B64_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 56;
      case 1:
        // op: addr
        return 32;
      case 2:
        // op: data0
        return 40;
      case 3:
        // op: data1
        return 48;
      case 4:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_WRXCHG2ST64_RTN_B32_gfx12:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B64_gfx12:
    case AMDGPU::DS_WRXCHG2_RTN_B32_gfx12:
    case AMDGPU::DS_WRXCHG2_RTN_B64_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 56;
      case 1:
        // op: addr
        return 32;
      case 2:
        // op: data0
        return 40;
      case 3:
        // op: data1
        return 48;
      case 4:
        // op: offset0
        return 0;
      case 5:
        // op: offset1
        return 8;
      }
      break;
    }
    case AMDGPU::DS_ADD_RTN_F32_gfx12:
    case AMDGPU::DS_ADD_RTN_F64_gfx12:
    case AMDGPU::DS_ADD_RTN_U32_gfx12:
    case AMDGPU::DS_ADD_RTN_U64_gfx12:
    case AMDGPU::DS_AND_RTN_B32_gfx12:
    case AMDGPU::DS_AND_RTN_B64_gfx12:
    case AMDGPU::DS_ATOMIC_BARRIER_ARRIVE_RTN_B64_gfx12:
    case AMDGPU::DS_BPERMUTE_B32_gfx10:
    case AMDGPU::DS_BPERMUTE_B32_gfx11:
    case AMDGPU::DS_BPERMUTE_B32_gfx12:
    case AMDGPU::DS_BPERMUTE_B32_vi:
    case AMDGPU::DS_BPERMUTE_B32_vi_agpr:
    case AMDGPU::DS_BPERMUTE_FI_B32_gfx12:
    case AMDGPU::DS_CONDXCHG32_RTN_B64_gfx12:
    case AMDGPU::DS_COND_SUB_RTN_U32_gfx12:
    case AMDGPU::DS_DEC_RTN_U32_gfx12:
    case AMDGPU::DS_DEC_RTN_U64_gfx12:
    case AMDGPU::DS_INC_RTN_U32_gfx12:
    case AMDGPU::DS_INC_RTN_U64_gfx12:
    case AMDGPU::DS_MAX_RTN_F32_gfx12:
    case AMDGPU::DS_MAX_RTN_F64_gfx12:
    case AMDGPU::DS_MAX_RTN_I32_gfx12:
    case AMDGPU::DS_MAX_RTN_I64_gfx12:
    case AMDGPU::DS_MAX_RTN_U32_gfx12:
    case AMDGPU::DS_MAX_RTN_U64_gfx12:
    case AMDGPU::DS_MIN_RTN_F32_gfx12:
    case AMDGPU::DS_MIN_RTN_F64_gfx12:
    case AMDGPU::DS_MIN_RTN_I32_gfx12:
    case AMDGPU::DS_MIN_RTN_I64_gfx12:
    case AMDGPU::DS_MIN_RTN_U32_gfx12:
    case AMDGPU::DS_MIN_RTN_U64_gfx12:
    case AMDGPU::DS_OR_RTN_B32_gfx12:
    case AMDGPU::DS_OR_RTN_B64_gfx12:
    case AMDGPU::DS_PERMUTE_B32_gfx10:
    case AMDGPU::DS_PERMUTE_B32_gfx11:
    case AMDGPU::DS_PERMUTE_B32_gfx12:
    case AMDGPU::DS_PERMUTE_B32_vi:
    case AMDGPU::DS_PERMUTE_B32_vi_agpr:
    case AMDGPU::DS_PK_ADD_RTN_BF16_gfx12:
    case AMDGPU::DS_PK_ADD_RTN_F16_gfx12:
    case AMDGPU::DS_RSUB_RTN_U32_gfx12:
    case AMDGPU::DS_RSUB_RTN_U64_gfx12:
    case AMDGPU::DS_SUB_CLAMP_RTN_U32_gfx12:
    case AMDGPU::DS_SUB_RTN_U32_gfx12:
    case AMDGPU::DS_SUB_RTN_U64_gfx12:
    case AMDGPU::DS_WRXCHG_RTN_B32_gfx12:
    case AMDGPU::DS_WRXCHG_RTN_B64_gfx12:
    case AMDGPU::DS_XOR_RTN_B32_gfx12:
    case AMDGPU::DS_XOR_RTN_B64_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 56;
      case 1:
        // op: addr
        return 32;
      case 2:
        // op: data0
        return 40;
      case 3:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_LOAD_TR16_B128_gfx12:
    case AMDGPU::DS_LOAD_TR4_B64_gfx12:
    case AMDGPU::DS_LOAD_TR6_B96_gfx12:
    case AMDGPU::DS_LOAD_TR8_B64_gfx12:
    case AMDGPU::DS_ORDERED_COUNT_gfx10:
    case AMDGPU::DS_ORDERED_COUNT_gfx11:
    case AMDGPU::DS_ORDERED_COUNT_gfx6_gfx7:
    case AMDGPU::DS_READ_B128_gfx12:
    case AMDGPU::DS_READ_B32_gfx12:
    case AMDGPU::DS_READ_B64_gfx12:
    case AMDGPU::DS_READ_B96_gfx12:
    case AMDGPU::DS_READ_I16_gfx12:
    case AMDGPU::DS_READ_I8_D16_HI_gfx12:
    case AMDGPU::DS_READ_I8_D16_gfx12:
    case AMDGPU::DS_READ_I8_gfx12:
    case AMDGPU::DS_READ_U16_D16_HI_gfx12:
    case AMDGPU::DS_READ_U16_D16_gfx12:
    case AMDGPU::DS_READ_U16_gfx12:
    case AMDGPU::DS_READ_U8_D16_HI_gfx12:
    case AMDGPU::DS_READ_U8_D16_gfx12:
    case AMDGPU::DS_READ_U8_gfx12:
    case AMDGPU::DS_SWIZZLE_B32_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 56;
      case 1:
        // op: addr
        return 32;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_READ2ST64_B32_gfx12:
    case AMDGPU::DS_READ2ST64_B64_gfx12:
    case AMDGPU::DS_READ2_B32_gfx12:
    case AMDGPU::DS_READ2_B64_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 56;
      case 1:
        // op: addr
        return 32;
      case 2:
        // op: offset0
        return 0;
      case 3:
        // op: offset1
        return 8;
      }
      break;
    }
    case AMDGPU::DS_BVH_STACK_PUSH8_POP1_RTN_B32_gfx12:
    case AMDGPU::DS_BVH_STACK_PUSH8_POP2_RTN_B64_gfx12:
    case AMDGPU::DS_BVH_STACK_RTN_B32_gfx11:
    case AMDGPU::DS_BVH_STACK_RTN_B32_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 56;
      case 1:
        // op: addr
        return 32;
      case 3:
        // op: data0
        return 40;
      case 4:
        // op: data1
        return 48;
      case 5:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_ADD_GS_REG_RTN_gfx11:
    case AMDGPU::DS_SUB_GS_REG_RTN_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 56;
      case 1:
        // op: data0
        return 40;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_APPEND_gfx12:
    case AMDGPU::DS_CONSUME_gfx12:
    case AMDGPU::DS_READ_ADDTID_B32_gfx12: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 56;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::GLOBAL_LOAD_DWORD_ADDTID_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORDX2_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORD_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_SBYTE_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_SSHORT_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_UBYTE_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_USHORT_ST_gfx10: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 56;
      case 2:
        // op: cpol
        return 12;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::GLOBAL_LOAD_DWORD_ADDTID_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORDX2_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORD_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_SSHORT_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_ST_gfx11:
    case AMDGPU::SCRATCH_LOAD_USHORT_ST_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 56;
      case 2:
        // op: cpol
        return 13;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_APPEND_gfx10:
    case AMDGPU::DS_APPEND_gfx11:
    case AMDGPU::DS_APPEND_gfx6_gfx7:
    case AMDGPU::DS_CONSUME_gfx10:
    case AMDGPU::DS_CONSUME_gfx11:
    case AMDGPU::DS_CONSUME_gfx6_gfx7:
    case AMDGPU::DS_READ_ADDTID_B32_gfx10:
    case AMDGPU::DS_READ_ADDTID_B32_gfx11: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 56;
      case 2:
        // op: gds
        return 17;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_READ_B128_gfx10:
    case AMDGPU::DS_READ_B128_gfx11:
    case AMDGPU::DS_READ_B128_gfx7:
    case AMDGPU::DS_READ_B32_gfx10:
    case AMDGPU::DS_READ_B32_gfx11:
    case AMDGPU::DS_READ_B32_gfx6_gfx7:
    case AMDGPU::DS_READ_B64_gfx10:
    case AMDGPU::DS_READ_B64_gfx11:
    case AMDGPU::DS_READ_B64_gfx6_gfx7:
    case AMDGPU::DS_READ_B96_gfx10:
    case AMDGPU::DS_READ_B96_gfx11:
    case AMDGPU::DS_READ_B96_gfx7:
    case AMDGPU::DS_READ_I16_gfx10:
    case AMDGPU::DS_READ_I16_gfx11:
    case AMDGPU::DS_READ_I16_gfx6_gfx7:
    case AMDGPU::DS_READ_I8_D16_HI_gfx10:
    case AMDGPU::DS_READ_I8_D16_HI_gfx11:
    case AMDGPU::DS_READ_I8_D16_gfx10:
    case AMDGPU::DS_READ_I8_D16_gfx11:
    case AMDGPU::DS_READ_I8_gfx10:
    case AMDGPU::DS_READ_I8_gfx11:
    case AMDGPU::DS_READ_I8_gfx6_gfx7:
    case AMDGPU::DS_READ_U16_D16_HI_gfx10:
    case AMDGPU::DS_READ_U16_D16_HI_gfx11:
    case AMDGPU::DS_READ_U16_D16_gfx10:
    case AMDGPU::DS_READ_U16_D16_gfx11:
    case AMDGPU::DS_READ_U16_gfx10:
    case AMDGPU::DS_READ_U16_gfx11:
    case AMDGPU::DS_READ_U16_gfx6_gfx7:
    case AMDGPU::DS_READ_U8_D16_HI_gfx10:
    case AMDGPU::DS_READ_U8_D16_HI_gfx11:
    case AMDGPU::DS_READ_U8_D16_gfx10:
    case AMDGPU::DS_READ_U8_D16_gfx11:
    case AMDGPU::DS_READ_U8_gfx10:
    case AMDGPU::DS_READ_U8_gfx11:
    case AMDGPU::DS_READ_U8_gfx6_gfx7:
    case AMDGPU::DS_SWIZZLE_B32_gfx10:
    case AMDGPU::DS_SWIZZLE_B32_gfx11:
    case AMDGPU::DS_SWIZZLE_B32_gfx6_gfx7: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 56;
      case 3:
        // op: gds
        return 17;
      case 1:
        // op: addr
        return 32;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_ADD_RTN_F32_vi:
    case AMDGPU::DS_ADD_RTN_F32_vi_agpr:
    case AMDGPU::DS_ADD_RTN_F32_vi_gfx9:
    case AMDGPU::DS_ADD_RTN_F64_vi:
    case AMDGPU::DS_ADD_RTN_F64_vi_agpr:
    case AMDGPU::DS_ADD_RTN_U32_vi:
    case AMDGPU::DS_ADD_RTN_U32_vi_agpr:
    case AMDGPU::DS_ADD_RTN_U32_vi_gfx9:
    case AMDGPU::DS_ADD_RTN_U64_vi:
    case AMDGPU::DS_ADD_RTN_U64_vi_agpr:
    case AMDGPU::DS_ADD_RTN_U64_vi_gfx9:
    case AMDGPU::DS_AND_RTN_B32_vi:
    case AMDGPU::DS_AND_RTN_B32_vi_agpr:
    case AMDGPU::DS_AND_RTN_B32_vi_gfx9:
    case AMDGPU::DS_AND_RTN_B64_vi:
    case AMDGPU::DS_AND_RTN_B64_vi_agpr:
    case AMDGPU::DS_AND_RTN_B64_vi_gfx9:
    case AMDGPU::DS_CONDXCHG32_RTN_B64_vi:
    case AMDGPU::DS_CONDXCHG32_RTN_B64_vi_agpr:
    case AMDGPU::DS_CONDXCHG32_RTN_B64_vi_gfx9:
    case AMDGPU::DS_DEC_RTN_U32_vi:
    case AMDGPU::DS_DEC_RTN_U32_vi_agpr:
    case AMDGPU::DS_DEC_RTN_U32_vi_gfx9:
    case AMDGPU::DS_DEC_RTN_U64_vi:
    case AMDGPU::DS_DEC_RTN_U64_vi_agpr:
    case AMDGPU::DS_DEC_RTN_U64_vi_gfx9:
    case AMDGPU::DS_INC_RTN_U32_vi:
    case AMDGPU::DS_INC_RTN_U32_vi_agpr:
    case AMDGPU::DS_INC_RTN_U32_vi_gfx9:
    case AMDGPU::DS_INC_RTN_U64_vi:
    case AMDGPU::DS_INC_RTN_U64_vi_agpr:
    case AMDGPU::DS_INC_RTN_U64_vi_gfx9:
    case AMDGPU::DS_MAX_RTN_F32_vi:
    case AMDGPU::DS_MAX_RTN_F32_vi_agpr:
    case AMDGPU::DS_MAX_RTN_F32_vi_gfx9:
    case AMDGPU::DS_MAX_RTN_F64_vi:
    case AMDGPU::DS_MAX_RTN_F64_vi_agpr:
    case AMDGPU::DS_MAX_RTN_F64_vi_gfx9:
    case AMDGPU::DS_MAX_RTN_I32_vi:
    case AMDGPU::DS_MAX_RTN_I32_vi_agpr:
    case AMDGPU::DS_MAX_RTN_I32_vi_gfx9:
    case AMDGPU::DS_MAX_RTN_I64_vi:
    case AMDGPU::DS_MAX_RTN_I64_vi_agpr:
    case AMDGPU::DS_MAX_RTN_I64_vi_gfx9:
    case AMDGPU::DS_MAX_RTN_U32_vi:
    case AMDGPU::DS_MAX_RTN_U32_vi_agpr:
    case AMDGPU::DS_MAX_RTN_U32_vi_gfx9:
    case AMDGPU::DS_MAX_RTN_U64_vi:
    case AMDGPU::DS_MAX_RTN_U64_vi_agpr:
    case AMDGPU::DS_MAX_RTN_U64_vi_gfx9:
    case AMDGPU::DS_MIN_RTN_F32_vi:
    case AMDGPU::DS_MIN_RTN_F32_vi_agpr:
    case AMDGPU::DS_MIN_RTN_F32_vi_gfx9:
    case AMDGPU::DS_MIN_RTN_F64_vi:
    case AMDGPU::DS_MIN_RTN_F64_vi_agpr:
    case AMDGPU::DS_MIN_RTN_F64_vi_gfx9:
    case AMDGPU::DS_MIN_RTN_I32_vi:
    case AMDGPU::DS_MIN_RTN_I32_vi_agpr:
    case AMDGPU::DS_MIN_RTN_I32_vi_gfx9:
    case AMDGPU::DS_MIN_RTN_I64_vi:
    case AMDGPU::DS_MIN_RTN_I64_vi_agpr:
    case AMDGPU::DS_MIN_RTN_I64_vi_gfx9:
    case AMDGPU::DS_MIN_RTN_U32_vi:
    case AMDGPU::DS_MIN_RTN_U32_vi_agpr:
    case AMDGPU::DS_MIN_RTN_U32_vi_gfx9:
    case AMDGPU::DS_MIN_RTN_U64_vi:
    case AMDGPU::DS_MIN_RTN_U64_vi_agpr:
    case AMDGPU::DS_MIN_RTN_U64_vi_gfx9:
    case AMDGPU::DS_OR_RTN_B32_vi:
    case AMDGPU::DS_OR_RTN_B32_vi_agpr:
    case AMDGPU::DS_OR_RTN_B32_vi_gfx9:
    case AMDGPU::DS_OR_RTN_B64_vi:
    case AMDGPU::DS_OR_RTN_B64_vi_agpr:
    case AMDGPU::DS_OR_RTN_B64_vi_gfx9:
    case AMDGPU::DS_PK_ADD_RTN_BF16_vi:
    case AMDGPU::DS_PK_ADD_RTN_BF16_vi_agpr:
    case AMDGPU::DS_PK_ADD_RTN_F16_vi:
    case AMDGPU::DS_PK_ADD_RTN_F16_vi_agpr:
    case AMDGPU::DS_RSUB_RTN_U32_vi:
    case AMDGPU::DS_RSUB_RTN_U32_vi_agpr:
    case AMDGPU::DS_RSUB_RTN_U32_vi_gfx9:
    case AMDGPU::DS_RSUB_RTN_U64_vi:
    case AMDGPU::DS_RSUB_RTN_U64_vi_agpr:
    case AMDGPU::DS_RSUB_RTN_U64_vi_gfx9:
    case AMDGPU::DS_SUB_RTN_U32_vi:
    case AMDGPU::DS_SUB_RTN_U32_vi_agpr:
    case AMDGPU::DS_SUB_RTN_U32_vi_gfx9:
    case AMDGPU::DS_SUB_RTN_U64_vi:
    case AMDGPU::DS_SUB_RTN_U64_vi_agpr:
    case AMDGPU::DS_SUB_RTN_U64_vi_gfx9:
    case AMDGPU::DS_WRXCHG_RTN_B32_vi:
    case AMDGPU::DS_WRXCHG_RTN_B32_vi_agpr:
    case AMDGPU::DS_WRXCHG_RTN_B32_vi_gfx9:
    case AMDGPU::DS_WRXCHG_RTN_B64_vi:
    case AMDGPU::DS_WRXCHG_RTN_B64_vi_agpr:
    case AMDGPU::DS_WRXCHG_RTN_B64_vi_gfx9:
    case AMDGPU::DS_XOR_RTN_B32_vi:
    case AMDGPU::DS_XOR_RTN_B32_vi_agpr:
    case AMDGPU::DS_XOR_RTN_B32_vi_gfx9:
    case AMDGPU::DS_XOR_RTN_B64_vi:
    case AMDGPU::DS_XOR_RTN_B64_vi_agpr:
    case AMDGPU::DS_XOR_RTN_B64_vi_gfx9: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 56;
      case 4:
        // op: gds
        return 16;
      case 1:
        // op: addr
        return 32;
      case 2:
        // op: data0
        return 40;
      case 3:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_ADD_RTN_F32_gfx10:
    case AMDGPU::DS_ADD_RTN_F32_gfx11:
    case AMDGPU::DS_ADD_RTN_U32_gfx10:
    case AMDGPU::DS_ADD_RTN_U32_gfx11:
    case AMDGPU::DS_ADD_RTN_U32_gfx6_gfx7:
    case AMDGPU::DS_ADD_RTN_U64_gfx10:
    case AMDGPU::DS_ADD_RTN_U64_gfx11:
    case AMDGPU::DS_ADD_RTN_U64_gfx6_gfx7:
    case AMDGPU::DS_AND_RTN_B32_gfx10:
    case AMDGPU::DS_AND_RTN_B32_gfx11:
    case AMDGPU::DS_AND_RTN_B32_gfx6_gfx7:
    case AMDGPU::DS_AND_RTN_B64_gfx10:
    case AMDGPU::DS_AND_RTN_B64_gfx11:
    case AMDGPU::DS_AND_RTN_B64_gfx6_gfx7:
    case AMDGPU::DS_CONDXCHG32_RTN_B64_gfx10:
    case AMDGPU::DS_CONDXCHG32_RTN_B64_gfx11:
    case AMDGPU::DS_CONDXCHG32_RTN_B64_gfx7:
    case AMDGPU::DS_DEC_RTN_U32_gfx10:
    case AMDGPU::DS_DEC_RTN_U32_gfx11:
    case AMDGPU::DS_DEC_RTN_U32_gfx6_gfx7:
    case AMDGPU::DS_DEC_RTN_U64_gfx10:
    case AMDGPU::DS_DEC_RTN_U64_gfx11:
    case AMDGPU::DS_DEC_RTN_U64_gfx6_gfx7:
    case AMDGPU::DS_INC_RTN_U32_gfx10:
    case AMDGPU::DS_INC_RTN_U32_gfx11:
    case AMDGPU::DS_INC_RTN_U32_gfx6_gfx7:
    case AMDGPU::DS_INC_RTN_U64_gfx10:
    case AMDGPU::DS_INC_RTN_U64_gfx11:
    case AMDGPU::DS_INC_RTN_U64_gfx6_gfx7:
    case AMDGPU::DS_MAX_RTN_F32_gfx10:
    case AMDGPU::DS_MAX_RTN_F32_gfx11:
    case AMDGPU::DS_MAX_RTN_F32_gfx6_gfx7:
    case AMDGPU::DS_MAX_RTN_F64_gfx10:
    case AMDGPU::DS_MAX_RTN_F64_gfx11:
    case AMDGPU::DS_MAX_RTN_F64_gfx6_gfx7:
    case AMDGPU::DS_MAX_RTN_I32_gfx10:
    case AMDGPU::DS_MAX_RTN_I32_gfx11:
    case AMDGPU::DS_MAX_RTN_I32_gfx6_gfx7:
    case AMDGPU::DS_MAX_RTN_I64_gfx10:
    case AMDGPU::DS_MAX_RTN_I64_gfx11:
    case AMDGPU::DS_MAX_RTN_I64_gfx6_gfx7:
    case AMDGPU::DS_MAX_RTN_U32_gfx10:
    case AMDGPU::DS_MAX_RTN_U32_gfx11:
    case AMDGPU::DS_MAX_RTN_U32_gfx6_gfx7:
    case AMDGPU::DS_MAX_RTN_U64_gfx10:
    case AMDGPU::DS_MAX_RTN_U64_gfx11:
    case AMDGPU::DS_MAX_RTN_U64_gfx6_gfx7:
    case AMDGPU::DS_MIN_RTN_F32_gfx10:
    case AMDGPU::DS_MIN_RTN_F32_gfx11:
    case AMDGPU::DS_MIN_RTN_F32_gfx6_gfx7:
    case AMDGPU::DS_MIN_RTN_F64_gfx10:
    case AMDGPU::DS_MIN_RTN_F64_gfx11:
    case AMDGPU::DS_MIN_RTN_F64_gfx6_gfx7:
    case AMDGPU::DS_MIN_RTN_I32_gfx10:
    case AMDGPU::DS_MIN_RTN_I32_gfx11:
    case AMDGPU::DS_MIN_RTN_I32_gfx6_gfx7:
    case AMDGPU::DS_MIN_RTN_I64_gfx10:
    case AMDGPU::DS_MIN_RTN_I64_gfx11:
    case AMDGPU::DS_MIN_RTN_I64_gfx6_gfx7:
    case AMDGPU::DS_MIN_RTN_U32_gfx10:
    case AMDGPU::DS_MIN_RTN_U32_gfx11:
    case AMDGPU::DS_MIN_RTN_U32_gfx6_gfx7:
    case AMDGPU::DS_MIN_RTN_U64_gfx10:
    case AMDGPU::DS_MIN_RTN_U64_gfx11:
    case AMDGPU::DS_MIN_RTN_U64_gfx6_gfx7:
    case AMDGPU::DS_OR_RTN_B32_gfx10:
    case AMDGPU::DS_OR_RTN_B32_gfx11:
    case AMDGPU::DS_OR_RTN_B32_gfx6_gfx7:
    case AMDGPU::DS_OR_RTN_B64_gfx10:
    case AMDGPU::DS_OR_RTN_B64_gfx11:
    case AMDGPU::DS_OR_RTN_B64_gfx6_gfx7:
    case AMDGPU::DS_RSUB_RTN_U32_gfx10:
    case AMDGPU::DS_RSUB_RTN_U32_gfx11:
    case AMDGPU::DS_RSUB_RTN_U32_gfx6_gfx7:
    case AMDGPU::DS_RSUB_RTN_U64_gfx10:
    case AMDGPU::DS_RSUB_RTN_U64_gfx11:
    case AMDGPU::DS_RSUB_RTN_U64_gfx6_gfx7:
    case AMDGPU::DS_SUB_RTN_U32_gfx10:
    case AMDGPU::DS_SUB_RTN_U32_gfx11:
    case AMDGPU::DS_SUB_RTN_U32_gfx6_gfx7:
    case AMDGPU::DS_SUB_RTN_U64_gfx10:
    case AMDGPU::DS_SUB_RTN_U64_gfx11:
    case AMDGPU::DS_SUB_RTN_U64_gfx6_gfx7:
    case AMDGPU::DS_WRXCHG_RTN_B32_gfx10:
    case AMDGPU::DS_WRXCHG_RTN_B32_gfx11:
    case AMDGPU::DS_WRXCHG_RTN_B32_gfx6_gfx7:
    case AMDGPU::DS_WRXCHG_RTN_B64_gfx10:
    case AMDGPU::DS_WRXCHG_RTN_B64_gfx11:
    case AMDGPU::DS_WRXCHG_RTN_B64_gfx6_gfx7:
    case AMDGPU::DS_XOR_RTN_B32_gfx10:
    case AMDGPU::DS_XOR_RTN_B32_gfx11:
    case AMDGPU::DS_XOR_RTN_B32_gfx6_gfx7:
    case AMDGPU::DS_XOR_RTN_B64_gfx10:
    case AMDGPU::DS_XOR_RTN_B64_gfx11:
    case AMDGPU::DS_XOR_RTN_B64_gfx6_gfx7: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 56;
      case 4:
        // op: gds
        return 17;
      case 1:
        // op: addr
        return 32;
      case 2:
        // op: data0
        return 40;
      case 3:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_READ2ST64_B32_gfx10:
    case AMDGPU::DS_READ2ST64_B32_gfx11:
    case AMDGPU::DS_READ2ST64_B32_gfx6_gfx7:
    case AMDGPU::DS_READ2ST64_B64_gfx10:
    case AMDGPU::DS_READ2ST64_B64_gfx11:
    case AMDGPU::DS_READ2ST64_B64_gfx6_gfx7:
    case AMDGPU::DS_READ2_B32_gfx10:
    case AMDGPU::DS_READ2_B32_gfx11:
    case AMDGPU::DS_READ2_B32_gfx6_gfx7:
    case AMDGPU::DS_READ2_B64_gfx10:
    case AMDGPU::DS_READ2_B64_gfx11:
    case AMDGPU::DS_READ2_B64_gfx6_gfx7: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 56;
      case 4:
        // op: gds
        return 17;
      case 1:
        // op: addr
        return 32;
      case 2:
        // op: offset0
        return 0;
      case 3:
        // op: offset1
        return 8;
      }
      break;
    }
    case AMDGPU::DS_CMPST_RTN_B32_vi:
    case AMDGPU::DS_CMPST_RTN_B32_vi_agpr:
    case AMDGPU::DS_CMPST_RTN_B32_vi_gfx9:
    case AMDGPU::DS_CMPST_RTN_B64_vi:
    case AMDGPU::DS_CMPST_RTN_B64_vi_agpr:
    case AMDGPU::DS_CMPST_RTN_B64_vi_gfx9:
    case AMDGPU::DS_CMPST_RTN_F32_vi:
    case AMDGPU::DS_CMPST_RTN_F32_vi_agpr:
    case AMDGPU::DS_CMPST_RTN_F32_vi_gfx9:
    case AMDGPU::DS_CMPST_RTN_F64_vi:
    case AMDGPU::DS_CMPST_RTN_F64_vi_agpr:
    case AMDGPU::DS_CMPST_RTN_F64_vi_gfx9:
    case AMDGPU::DS_MSKOR_RTN_B32_vi:
    case AMDGPU::DS_MSKOR_RTN_B32_vi_agpr:
    case AMDGPU::DS_MSKOR_RTN_B32_vi_gfx9:
    case AMDGPU::DS_MSKOR_RTN_B64_vi:
    case AMDGPU::DS_MSKOR_RTN_B64_vi_agpr:
    case AMDGPU::DS_MSKOR_RTN_B64_vi_gfx9:
    case AMDGPU::DS_WRAP_RTN_B32_vi:
    case AMDGPU::DS_WRAP_RTN_B32_vi_agpr:
    case AMDGPU::DS_WRAP_RTN_B32_vi_gfx9: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 56;
      case 5:
        // op: gds
        return 16;
      case 1:
        // op: addr
        return 32;
      case 2:
        // op: data0
        return 40;
      case 3:
        // op: data1
        return 48;
      case 4:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_CMPSTORE_RTN_B32_gfx11:
    case AMDGPU::DS_CMPSTORE_RTN_B64_gfx11:
    case AMDGPU::DS_CMPSTORE_RTN_F32_gfx11:
    case AMDGPU::DS_CMPSTORE_RTN_F64_gfx11:
    case AMDGPU::DS_CMPST_RTN_B32_gfx10:
    case AMDGPU::DS_CMPST_RTN_B32_gfx6_gfx7:
    case AMDGPU::DS_CMPST_RTN_B64_gfx10:
    case AMDGPU::DS_CMPST_RTN_B64_gfx6_gfx7:
    case AMDGPU::DS_CMPST_RTN_F32_gfx10:
    case AMDGPU::DS_CMPST_RTN_F32_gfx6_gfx7:
    case AMDGPU::DS_CMPST_RTN_F64_gfx10:
    case AMDGPU::DS_CMPST_RTN_F64_gfx6_gfx7:
    case AMDGPU::DS_MSKOR_RTN_B32_gfx10:
    case AMDGPU::DS_MSKOR_RTN_B32_gfx11:
    case AMDGPU::DS_MSKOR_RTN_B32_gfx6_gfx7:
    case AMDGPU::DS_MSKOR_RTN_B64_gfx10:
    case AMDGPU::DS_MSKOR_RTN_B64_gfx11:
    case AMDGPU::DS_MSKOR_RTN_B64_gfx6_gfx7:
    case AMDGPU::DS_WRAP_RTN_B32_gfx10:
    case AMDGPU::DS_WRAP_RTN_B32_gfx11:
    case AMDGPU::DS_WRAP_RTN_B32_gfx7: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 56;
      case 5:
        // op: gds
        return 17;
      case 1:
        // op: addr
        return 32;
      case 2:
        // op: data0
        return 40;
      case 3:
        // op: data1
        return 48;
      case 4:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_WRXCHG2ST64_RTN_B32_vi:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B32_vi_agpr:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B32_vi_gfx9:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B64_vi:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B64_vi_agpr:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B64_vi_gfx9:
    case AMDGPU::DS_WRXCHG2_RTN_B32_vi:
    case AMDGPU::DS_WRXCHG2_RTN_B32_vi_agpr:
    case AMDGPU::DS_WRXCHG2_RTN_B32_vi_gfx9:
    case AMDGPU::DS_WRXCHG2_RTN_B64_vi:
    case AMDGPU::DS_WRXCHG2_RTN_B64_vi_agpr:
    case AMDGPU::DS_WRXCHG2_RTN_B64_vi_gfx9: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 56;
      case 6:
        // op: gds
        return 16;
      case 1:
        // op: addr
        return 32;
      case 2:
        // op: data0
        return 40;
      case 3:
        // op: data1
        return 48;
      case 4:
        // op: offset0
        return 0;
      case 5:
        // op: offset1
        return 8;
      }
      break;
    }
    case AMDGPU::DS_WRXCHG2ST64_RTN_B32_gfx10:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B32_gfx11:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B32_gfx6_gfx7:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B64_gfx10:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B64_gfx11:
    case AMDGPU::DS_WRXCHG2ST64_RTN_B64_gfx6_gfx7:
    case AMDGPU::DS_WRXCHG2_RTN_B32_gfx10:
    case AMDGPU::DS_WRXCHG2_RTN_B32_gfx11:
    case AMDGPU::DS_WRXCHG2_RTN_B32_gfx6_gfx7:
    case AMDGPU::DS_WRXCHG2_RTN_B64_gfx10:
    case AMDGPU::DS_WRXCHG2_RTN_B64_gfx11:
    case AMDGPU::DS_WRXCHG2_RTN_B64_gfx6_gfx7: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 56;
      case 6:
        // op: gds
        return 17;
      case 1:
        // op: addr
        return 32;
      case 2:
        // op: data0
        return 40;
      case 3:
        // op: data1
        return 48;
      case 4:
        // op: offset0
        return 0;
      case 5:
        // op: offset1
        return 8;
      }
      break;
    }
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd:
    case AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 64;
      case 1:
        // op: src0
        return 96;
      case 2:
        // op: src1
        return 105;
      case 3:
        // op: src2
        return 114;
      case 5:
        // op: blgp
        return 125;
      case 4:
        // op: cbsz
        return 72;
      case 6:
        // op: scale_src0
        return 32;
      case 7:
        // op: scale_src1
        return 41;
      case 8:
        // op: src0_modifiers
        return 11;
      case 9:
        // op: src1_modifiers
        return 12;
      }
      break;
    }
    case AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 64;
      case 1:
        // op: src0
        return 96;
      case 2:
        // op: src1
        return 105;
      case 3:
        // op: src2_modifiers
        return 74;
      case 4:
        // op: src2
        return 114;
      case 7:
        // op: matrix_a_fmt
        return 75;
      case 8:
        // op: matrix_b_fmt
        return 78;
      case 9:
        // op: matrix_a_scale
        return 11;
      case 10:
        // op: matrix_b_scale
        return 59;
      case 11:
        // op: matrix_a_scale_fmt
        return 61;
      case 12:
        // op: matrix_b_scale_fmt
        return 8;
      case 13:
        // op: matrix_a_reuse
        return 13;
      case 14:
        // op: matrix_b_reuse
        return 14;
      case 5:
        // op: scale_src0
        return 32;
      case 6:
        // op: scale_src1
        return 41;
      }
      break;
    }
    case AMDGPU::V_WMMA_SCALE16_F32_32X16X128_F4_w32_gfx1250:
    case AMDGPU::V_WMMA_SCALE_F32_32X16X128_F4_w32_gfx1250: {
      switch (OpNum) {
      case 0:
        // op: vdst
        return 64;
      case 1:
        // op: src0
        return 96;
      case 2:
        // op: src1
        return 105;
      case 3:
        // op: src2_modifiers
        return 74;
      case 4:
        // op: src2
        return 114;
      case 7:
        // op: matrix_a_scale
        return 11;
      case 8:
        // op: matrix_b_scale
        return 59;
      case 9:
        // op: matrix_a_scale_fmt
        return 61;
      case 10:
        // op: matrix_b_scale_fmt
        return 8;
      case 11:
        // op: matrix_a_reuse
        return 13;
      case 12:
        // op: matrix_b_reuse
        return 14;
      case 5:
        // op: scale_src0
        return 32;
      case 6:
        // op: scale_src1
        return 41;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V8_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V8_nsa_gfx10: {
      switch (OpNum) {
      case 10:
        // op: dmask
        return 8;
      case 12:
        // op: unorm
        return 12;
      case 13:
        // op: cpol
        return 7;
      case 14:
        // op: r128
        return 15;
      case 16:
        // op: tfe
        return 16;
      case 17:
        // op: lwe
        return 17;
      case 18:
        // op: d16
        return 63;
      case 8:
        // op: srsrc
        return 48;
      case 9:
        // op: ssamp
        return 53;
      case 0:
        // op: vaddr0
        return 32;
      case 11:
        // op: dim
        return 3;
      case 15:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V9_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V9_nsa_gfx10: {
      switch (OpNum) {
      case 11:
        // op: dmask
        return 8;
      case 13:
        // op: unorm
        return 12;
      case 14:
        // op: cpol
        return 7;
      case 15:
        // op: r128
        return 15;
      case 17:
        // op: tfe
        return 16;
      case 18:
        // op: lwe
        return 17;
      case 19:
        // op: d16
        return 63;
      case 9:
        // op: srsrc
        return 48;
      case 10:
        // op: ssamp
        return 53;
      case 0:
        // op: vaddr0
        return 32;
      case 12:
        // op: dim
        return 3;
      case 16:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V10_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V10_nsa_gfx10: {
      switch (OpNum) {
      case 12:
        // op: dmask
        return 8;
      case 14:
        // op: unorm
        return 12;
      case 15:
        // op: cpol
        return 7;
      case 16:
        // op: r128
        return 15;
      case 18:
        // op: tfe
        return 16;
      case 19:
        // op: lwe
        return 17;
      case 20:
        // op: d16
        return 63;
      case 10:
        // op: srsrc
        return 48;
      case 11:
        // op: ssamp
        return 53;
      case 0:
        // op: vaddr0
        return 32;
      case 13:
        // op: dim
        return 3;
      case 17:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V11_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V11_nsa_gfx10: {
      switch (OpNum) {
      case 13:
        // op: dmask
        return 8;
      case 15:
        // op: unorm
        return 12;
      case 16:
        // op: cpol
        return 7;
      case 17:
        // op: r128
        return 15;
      case 19:
        // op: tfe
        return 16;
      case 20:
        // op: lwe
        return 17;
      case 21:
        // op: d16
        return 63;
      case 11:
        // op: srsrc
        return 48;
      case 12:
        // op: ssamp
        return 53;
      case 0:
        // op: vaddr0
        return 32;
      case 14:
        // op: dim
        return 3;
      case 18:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V12_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V12_nsa_gfx10: {
      switch (OpNum) {
      case 14:
        // op: dmask
        return 8;
      case 16:
        // op: unorm
        return 12;
      case 17:
        // op: cpol
        return 7;
      case 18:
        // op: r128
        return 15;
      case 20:
        // op: tfe
        return 16;
      case 21:
        // op: lwe
        return 17;
      case 22:
        // op: d16
        return 63;
      case 12:
        // op: srsrc
        return 48;
      case 13:
        // op: ssamp
        return 53;
      case 0:
        // op: vaddr0
        return 32;
      case 15:
        // op: dim
        return 3;
      case 19:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::SCRATCH_LOAD_LDS_DWORD_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_SBYTE_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_SSHORT_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_UBYTE_ST_gfx10:
    case AMDGPU::SCRATCH_LOAD_LDS_USHORT_ST_gfx10: {
      switch (OpNum) {
      case 1:
        // op: cpol
        return 12;
      case 0:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::SCRATCH_LOAD_LDS_DWORD_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_SBYTE_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_SSHORT_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_UBYTE_ST_gfx940:
    case AMDGPU::SCRATCH_LOAD_LDS_USHORT_ST_gfx940: {
      switch (OpNum) {
      case 1:
        // op: cpol
        return 16;
      case 0:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::GLOBAL_LOAD_DWORD_ADDTID_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_BLOCK_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORD_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_SSHORT_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_SADDR_gfx12:
    case AMDGPU::SCRATCH_LOAD_USHORT_SADDR_gfx12: {
      switch (OpNum) {
      case 1:
        // op: saddr
        return 0;
      case 0:
        // op: vdst
        return 32;
      case 3:
        // op: cpol
        return 7;
      case 2:
        // op: offset
        return 72;
      }
      break;
    }
    case AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B128_SADDR_gfx1250:
    case AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B32_SADDR_gfx1250:
    case AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B64_SADDR_gfx1250:
    case AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B8_SADDR_gfx1250:
    case AMDGPU::CLUSTER_LOAD_B128_SADDR_gfx1250:
    case AMDGPU::CLUSTER_LOAD_B32_SADDR_gfx1250:
    case AMDGPU::CLUSTER_LOAD_B64_SADDR_gfx1250:
    case AMDGPU::FLAT_LOAD_DWORDX2_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_DWORDX3_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_DWORDX4_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_DWORD_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_MONITOR_B128_SADDR_gfx1250:
    case AMDGPU::FLAT_LOAD_MONITOR_B32_SADDR_gfx1250:
    case AMDGPU::FLAT_LOAD_MONITOR_B64_SADDR_gfx1250:
    case AMDGPU::FLAT_LOAD_SBYTE_D16_HI_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_SBYTE_D16_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_SBYTE_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_SHORT_D16_HI_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_SHORT_D16_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_SSHORT_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_UBYTE_D16_HI_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_UBYTE_D16_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_UBYTE_SADDR_gfx12:
    case AMDGPU::FLAT_LOAD_USHORT_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B128_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B32_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B64_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B8_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_BLOCK_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_DWORD_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_MONITOR_B128_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_MONITOR_B32_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_MONITOR_B64_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_SBYTE_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_SSHORT_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_TR4_B64_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_TR6_B96_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_TR_B128_w32_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_TR_B128_w32_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_TR_B128_w64_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_TR_B64_w32_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_TR_B64_w32_SADDR_gfx1250:
    case AMDGPU::GLOBAL_LOAD_TR_B64_w64_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_UBYTE_SADDR_gfx12:
    case AMDGPU::GLOBAL_LOAD_USHORT_SADDR_gfx12: {
      switch (OpNum) {
      case 1:
        // op: saddr
        return 0;
      case 0:
        // op: vdst
        return 32;
      case 4:
        // op: cpol
        return 7;
      case 2:
        // op: vaddr
        return 64;
      case 3:
        // op: offset
        return 72;
      }
      break;
    }
    case AMDGPU::GLOBAL_STORE_DWORD_ADDTID_SADDR_gfx12:
    case AMDGPU::SCRATCH_STORE_BLOCK_SADDR_gfx12:
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR_gfx12:
    case AMDGPU::SCRATCH_STORE_BYTE_SADDR_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX2_SADDR_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX3_SADDR_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX4_SADDR_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORD_SADDR_gfx12:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR_gfx12:
    case AMDGPU::SCRATCH_STORE_SHORT_SADDR_gfx12: {
      switch (OpNum) {
      case 1:
        // op: saddr
        return 0;
      case 3:
        // op: cpol
        return 7;
      case 0:
        // op: vdata
        return 55;
      case 2:
        // op: offset
        return 72;
      }
      break;
    }
    case AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_DWORD_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_SBYTE_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_SSHORT_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_UBYTE_SADDR_vi:
    case AMDGPU::SCRATCH_LOAD_USHORT_SADDR_vi: {
      switch (OpNum) {
      case 1:
        // op: saddr
        return 48;
      case 0:
        // op: vdst
        return 55;
      case 3:
        // op: cpol
        return 16;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::GLOBAL_LOAD_DWORD_ADDTID_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORD_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_SBYTE_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_SSHORT_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_UBYTE_SADDR_gfx10:
    case AMDGPU::SCRATCH_LOAD_USHORT_SADDR_gfx10: {
      switch (OpNum) {
      case 1:
        // op: saddr
        return 48;
      case 0:
        // op: vdst
        return 56;
      case 3:
        // op: cpol
        return 12;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::GLOBAL_LOAD_DWORD_ADDTID_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORD_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_SSHORT_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_SADDR_gfx11:
    case AMDGPU::SCRATCH_LOAD_USHORT_SADDR_gfx11: {
      switch (OpNum) {
      case 1:
        // op: saddr
        return 48;
      case 0:
        // op: vdst
        return 56;
      case 3:
        // op: cpol
        return 13;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_B128_IMM_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B256_IMM_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B32_IMM_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B512_IMM_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B64_IMM_gfx11:
    case AMDGPU::S_LOAD_B128_IMM_gfx11:
    case AMDGPU::S_LOAD_B256_IMM_gfx11:
    case AMDGPU::S_LOAD_B32_IMM_gfx11:
    case AMDGPU::S_LOAD_B512_IMM_gfx11:
    case AMDGPU::S_LOAD_B64_IMM_gfx11: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 0:
        // op: sdst
        return 6;
      case 2:
        // op: offset
        return 32;
      case 3:
        // op: cpol
        return 13;
      }
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORD_IMM_gfx10:
    case AMDGPU::S_LOAD_DWORDX16_IMM_gfx10:
    case AMDGPU::S_LOAD_DWORDX2_IMM_gfx10:
    case AMDGPU::S_LOAD_DWORDX4_IMM_gfx10:
    case AMDGPU::S_LOAD_DWORDX8_IMM_gfx10:
    case AMDGPU::S_LOAD_DWORD_IMM_gfx10:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX2_IMM_gfx10:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX4_IMM_gfx10:
    case AMDGPU::S_SCRATCH_LOAD_DWORD_IMM_gfx10: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 0:
        // op: sdst
        return 6;
      case 2:
        // op: offset
        return 32;
      case 3:
        // op: cpol
        return 14;
      }
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_vi:
    case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_vi:
    case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_vi:
    case AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_vi:
    case AMDGPU::S_BUFFER_LOAD_DWORD_IMM_vi:
    case AMDGPU::S_LOAD_DWORDX16_IMM_vi:
    case AMDGPU::S_LOAD_DWORDX2_IMM_vi:
    case AMDGPU::S_LOAD_DWORDX4_IMM_vi:
    case AMDGPU::S_LOAD_DWORDX8_IMM_vi:
    case AMDGPU::S_LOAD_DWORD_IMM_vi:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX2_IMM_vi:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX4_IMM_vi:
    case AMDGPU::S_SCRATCH_LOAD_DWORD_IMM_vi: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 0:
        // op: sdst
        return 6;
      case 2:
        // op: offset
        return 32;
      case 3:
        // op: cpol
        return 16;
      }
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_B128_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_B256_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_B32_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_B512_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_B64_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_B96_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_I16_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_I8_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_U16_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_U8_IMM_gfx12:
    case AMDGPU::S_LOAD_B128_IMM_gfx12:
    case AMDGPU::S_LOAD_B256_IMM_gfx12:
    case AMDGPU::S_LOAD_B32_IMM_gfx12:
    case AMDGPU::S_LOAD_B512_IMM_gfx12:
    case AMDGPU::S_LOAD_B64_IMM_gfx12:
    case AMDGPU::S_LOAD_B96_IMM_gfx12:
    case AMDGPU::S_LOAD_I16_IMM_gfx12:
    case AMDGPU::S_LOAD_I8_IMM_gfx12:
    case AMDGPU::S_LOAD_U16_IMM_gfx12:
    case AMDGPU::S_LOAD_U8_IMM_gfx12: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 0:
        // op: sdst
        return 6;
      case 2:
        // op: offset
        return 32;
      case 3:
        // op: cpol
        return 20;
      }
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_vi:
    case AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_vi:
    case AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_vi:
    case AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_vi:
    case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_vi:
    case AMDGPU::S_LOAD_DWORDX16_SGPR_vi:
    case AMDGPU::S_LOAD_DWORDX2_SGPR_vi:
    case AMDGPU::S_LOAD_DWORDX4_SGPR_vi:
    case AMDGPU::S_LOAD_DWORDX8_SGPR_vi:
    case AMDGPU::S_LOAD_DWORD_SGPR_vi:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX2_SGPR_vi:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX4_SGPR_vi:
    case AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_vi: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 0:
        // op: sdst
        return 6;
      case 2:
        // op: soffset
        return 32;
      case 3:
        // op: cpol
        return 16;
      }
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_B128_SGPR_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B256_SGPR_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B32_SGPR_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B512_SGPR_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B64_SGPR_gfx11:
    case AMDGPU::S_LOAD_B128_SGPR_gfx11:
    case AMDGPU::S_LOAD_B256_SGPR_gfx11:
    case AMDGPU::S_LOAD_B32_SGPR_gfx11:
    case AMDGPU::S_LOAD_B512_SGPR_gfx11:
    case AMDGPU::S_LOAD_B64_SGPR_gfx11: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 0:
        // op: sdst
        return 6;
      case 2:
        // op: soffset
        return 57;
      case 3:
        // op: cpol
        return 13;
      }
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_gfx10:
    case AMDGPU::S_LOAD_DWORDX16_SGPR_gfx10:
    case AMDGPU::S_LOAD_DWORDX2_SGPR_gfx10:
    case AMDGPU::S_LOAD_DWORDX4_SGPR_gfx10:
    case AMDGPU::S_LOAD_DWORDX8_SGPR_gfx10:
    case AMDGPU::S_LOAD_DWORD_SGPR_gfx10:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX2_SGPR_gfx10:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX4_SGPR_gfx10:
    case AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_gfx10: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 0:
        // op: sdst
        return 6;
      case 2:
        // op: soffset
        return 57;
      case 3:
        // op: cpol
        return 14;
      }
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_alt_gfx9:
    case AMDGPU::S_LOAD_DWORDX16_SGPR_alt_gfx9:
    case AMDGPU::S_LOAD_DWORDX2_SGPR_alt_gfx9:
    case AMDGPU::S_LOAD_DWORDX4_SGPR_alt_gfx9:
    case AMDGPU::S_LOAD_DWORDX8_SGPR_alt_gfx9:
    case AMDGPU::S_LOAD_DWORD_SGPR_alt_gfx9:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX2_SGPR_alt_gfx9:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX4_SGPR_alt_gfx9:
    case AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_alt_gfx9: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 0:
        // op: sdst
        return 6;
      case 2:
        // op: soffset
        return 57;
      case 3:
        // op: cpol
        return 16;
      }
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_B128_SGPR_IMM_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B256_SGPR_IMM_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B32_SGPR_IMM_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B512_SGPR_IMM_gfx11:
    case AMDGPU::S_BUFFER_LOAD_B64_SGPR_IMM_gfx11:
    case AMDGPU::S_LOAD_B128_SGPR_IMM_gfx11:
    case AMDGPU::S_LOAD_B256_SGPR_IMM_gfx11:
    case AMDGPU::S_LOAD_B32_SGPR_IMM_gfx11:
    case AMDGPU::S_LOAD_B512_SGPR_IMM_gfx11:
    case AMDGPU::S_LOAD_B64_SGPR_IMM_gfx11: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 0:
        // op: sdst
        return 6;
      case 3:
        // op: offset
        return 32;
      case 2:
        // op: soffset
        return 57;
      case 4:
        // op: cpol
        return 13;
      }
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM_gfx10:
    case AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_gfx10:
    case AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_gfx10:
    case AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_gfx10:
    case AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_gfx10:
    case AMDGPU::S_LOAD_DWORD_SGPR_IMM_gfx10:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX2_SGPR_IMM_gfx10:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX4_SGPR_IMM_gfx10:
    case AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_IMM_gfx10: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 0:
        // op: sdst
        return 6;
      case 3:
        // op: offset
        return 32;
      case 2:
        // op: soffset
        return 57;
      case 4:
        // op: cpol
        return 14;
      }
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM_gfx9:
    case AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_gfx9:
    case AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_gfx9:
    case AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_gfx9:
    case AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_gfx9:
    case AMDGPU::S_LOAD_DWORD_SGPR_IMM_gfx9:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX2_SGPR_IMM_gfx9:
    case AMDGPU::S_SCRATCH_LOAD_DWORDX4_SGPR_IMM_gfx9:
    case AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_IMM_gfx9: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 0:
        // op: sdst
        return 6;
      case 3:
        // op: offset
        return 32;
      case 2:
        // op: soffset
        return 57;
      case 4:
        // op: cpol
        return 16;
      }
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_B128_SGPR_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_B256_SGPR_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_B32_SGPR_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_B512_SGPR_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_B64_SGPR_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_B96_SGPR_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_I16_SGPR_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_I8_SGPR_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_U16_SGPR_IMM_gfx12:
    case AMDGPU::S_BUFFER_LOAD_U8_SGPR_IMM_gfx12:
    case AMDGPU::S_LOAD_B128_SGPR_IMM_gfx12:
    case AMDGPU::S_LOAD_B256_SGPR_IMM_gfx12:
    case AMDGPU::S_LOAD_B32_SGPR_IMM_gfx12:
    case AMDGPU::S_LOAD_B512_SGPR_IMM_gfx12:
    case AMDGPU::S_LOAD_B64_SGPR_IMM_gfx12:
    case AMDGPU::S_LOAD_B96_SGPR_IMM_gfx12:
    case AMDGPU::S_LOAD_I16_SGPR_IMM_gfx12:
    case AMDGPU::S_LOAD_I8_SGPR_IMM_gfx12:
    case AMDGPU::S_LOAD_U16_SGPR_IMM_gfx12:
    case AMDGPU::S_LOAD_U8_SGPR_IMM_gfx12: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 0:
        // op: sdst
        return 6;
      case 3:
        // op: offset
        return 32;
      case 2:
        // op: soffset
        return 57;
      case 4:
        // op: cpol
        return 20;
      }
      break;
    }
    case AMDGPU::S_ATC_PROBE_BUFFER_IMM_gfx10:
    case AMDGPU::S_ATC_PROBE_BUFFER_IMM_gfx11:
    case AMDGPU::S_ATC_PROBE_BUFFER_IMM_gfx12:
    case AMDGPU::S_ATC_PROBE_BUFFER_IMM_vi:
    case AMDGPU::S_ATC_PROBE_IMM_gfx10:
    case AMDGPU::S_ATC_PROBE_IMM_gfx11:
    case AMDGPU::S_ATC_PROBE_IMM_gfx12:
    case AMDGPU::S_ATC_PROBE_IMM_vi:
    case AMDGPU::S_ATOMIC_ADD_IMM_vi:
    case AMDGPU::S_ATOMIC_ADD_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_AND_IMM_vi:
    case AMDGPU::S_ATOMIC_AND_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_CMPSWAP_IMM_vi:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_DEC_IMM_vi:
    case AMDGPU::S_ATOMIC_DEC_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_INC_IMM_vi:
    case AMDGPU::S_ATOMIC_INC_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_OR_IMM_vi:
    case AMDGPU::S_ATOMIC_OR_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_SMAX_IMM_vi:
    case AMDGPU::S_ATOMIC_SMAX_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_SMIN_IMM_vi:
    case AMDGPU::S_ATOMIC_SMIN_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_SUB_IMM_vi:
    case AMDGPU::S_ATOMIC_SUB_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_SWAP_IMM_vi:
    case AMDGPU::S_ATOMIC_SWAP_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_UMAX_IMM_vi:
    case AMDGPU::S_ATOMIC_UMAX_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_UMIN_IMM_vi:
    case AMDGPU::S_ATOMIC_UMIN_X2_IMM_vi:
    case AMDGPU::S_ATOMIC_XOR_IMM_vi:
    case AMDGPU::S_ATOMIC_XOR_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_AND_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_INC_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_OR_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_IMM_vi:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_IMM_vi: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 2:
        // op: offset
        return 32;
      case 0:
        // op: sdata
        return 6;
      }
      break;
    }
    case AMDGPU::S_ATOMIC_ADD_IMM_gfx10:
    case AMDGPU::S_ATOMIC_ADD_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_AND_IMM_gfx10:
    case AMDGPU::S_ATOMIC_AND_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_IMM_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_DEC_IMM_gfx10:
    case AMDGPU::S_ATOMIC_DEC_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_INC_IMM_gfx10:
    case AMDGPU::S_ATOMIC_INC_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_OR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_OR_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SUB_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SUB_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_IMM_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_IMM_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_X2_IMM_gfx10:
    case AMDGPU::S_ATOMIC_XOR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_XOR_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_IMM_gfx10:
    case AMDGPU::S_BUFFER_STORE_DWORDX2_IMM_gfx10:
    case AMDGPU::S_BUFFER_STORE_DWORDX4_IMM_gfx10:
    case AMDGPU::S_BUFFER_STORE_DWORD_IMM_gfx10:
    case AMDGPU::S_SCRATCH_STORE_DWORDX2_IMM_gfx10:
    case AMDGPU::S_SCRATCH_STORE_DWORDX4_IMM_gfx10:
    case AMDGPU::S_SCRATCH_STORE_DWORD_IMM_gfx10:
    case AMDGPU::S_STORE_DWORDX2_IMM_gfx10:
    case AMDGPU::S_STORE_DWORDX4_IMM_gfx10:
    case AMDGPU::S_STORE_DWORD_IMM_gfx10: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 2:
        // op: offset
        return 32;
      case 3:
        // op: cpol
        return 14;
      case 0:
        // op: sdata
        return 6;
      }
      break;
    }
    case AMDGPU::S_BUFFER_STORE_DWORDX2_IMM_vi:
    case AMDGPU::S_BUFFER_STORE_DWORDX4_IMM_vi:
    case AMDGPU::S_BUFFER_STORE_DWORD_IMM_vi:
    case AMDGPU::S_SCRATCH_STORE_DWORDX2_IMM_vi:
    case AMDGPU::S_SCRATCH_STORE_DWORDX4_IMM_vi:
    case AMDGPU::S_SCRATCH_STORE_DWORD_IMM_vi:
    case AMDGPU::S_STORE_DWORDX2_IMM_vi:
    case AMDGPU::S_STORE_DWORDX4_IMM_vi:
    case AMDGPU::S_STORE_DWORD_IMM_vi: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 2:
        // op: offset
        return 32;
      case 3:
        // op: cpol
        return 16;
      case 0:
        // op: sdata
        return 6;
      }
      break;
    }
    case AMDGPU::S_ATC_PROBE_BUFFER_SGPR_vi:
    case AMDGPU::S_ATC_PROBE_SGPR_vi:
    case AMDGPU::S_ATOMIC_ADD_SGPR_vi:
    case AMDGPU::S_ATOMIC_ADD_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_AND_SGPR_vi:
    case AMDGPU::S_ATOMIC_AND_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_CMPSWAP_SGPR_vi:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_DEC_SGPR_vi:
    case AMDGPU::S_ATOMIC_DEC_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_INC_SGPR_vi:
    case AMDGPU::S_ATOMIC_INC_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_OR_SGPR_vi:
    case AMDGPU::S_ATOMIC_OR_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_SMAX_SGPR_vi:
    case AMDGPU::S_ATOMIC_SMAX_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_SMIN_SGPR_vi:
    case AMDGPU::S_ATOMIC_SMIN_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_SUB_SGPR_vi:
    case AMDGPU::S_ATOMIC_SUB_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_SWAP_SGPR_vi:
    case AMDGPU::S_ATOMIC_SWAP_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_UMAX_SGPR_vi:
    case AMDGPU::S_ATOMIC_UMAX_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_UMIN_SGPR_vi:
    case AMDGPU::S_ATOMIC_UMIN_X2_SGPR_vi:
    case AMDGPU::S_ATOMIC_XOR_SGPR_vi:
    case AMDGPU::S_ATOMIC_XOR_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_vi:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_vi: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 2:
        // op: soffset
        return 32;
      case 0:
        // op: sdata
        return 6;
      }
      break;
    }
    case AMDGPU::S_BUFFER_STORE_DWORDX2_SGPR_vi:
    case AMDGPU::S_BUFFER_STORE_DWORDX4_SGPR_vi:
    case AMDGPU::S_BUFFER_STORE_DWORD_SGPR_vi:
    case AMDGPU::S_SCRATCH_STORE_DWORDX2_SGPR_vi:
    case AMDGPU::S_SCRATCH_STORE_DWORDX4_SGPR_vi:
    case AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_vi:
    case AMDGPU::S_STORE_DWORDX2_SGPR_vi:
    case AMDGPU::S_STORE_DWORDX4_SGPR_vi:
    case AMDGPU::S_STORE_DWORD_SGPR_vi: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 2:
        // op: soffset
        return 32;
      case 3:
        // op: cpol
        return 16;
      case 0:
        // op: sdata
        return 6;
      }
      break;
    }
    case AMDGPU::S_ATC_PROBE_BUFFER_SGPR_alt_gfx9:
    case AMDGPU::S_ATC_PROBE_BUFFER_SGPR_gfx10:
    case AMDGPU::S_ATC_PROBE_BUFFER_SGPR_gfx11:
    case AMDGPU::S_ATC_PROBE_SGPR_alt_gfx9:
    case AMDGPU::S_ATC_PROBE_SGPR_gfx10:
    case AMDGPU::S_ATC_PROBE_SGPR_gfx11:
    case AMDGPU::S_ATOMIC_ADD_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_ADD_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_AND_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_AND_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_CMPSWAP_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_DEC_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_DEC_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_INC_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_INC_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_OR_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_OR_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_SMAX_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_SMAX_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_SMIN_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_SMIN_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_SUB_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_SUB_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_SWAP_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_SWAP_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_UMAX_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_UMAX_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_UMIN_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_UMIN_X2_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_XOR_SGPR_alt_gfx9:
    case AMDGPU::S_ATOMIC_XOR_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_alt_gfx9: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 2:
        // op: soffset
        return 57;
      case 0:
        // op: sdata
        return 6;
      }
      break;
    }
    case AMDGPU::S_ATOMIC_ADD_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_ADD_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_AND_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_AND_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_DEC_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_DEC_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_INC_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_INC_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_OR_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_OR_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_SUB_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_SUB_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_X2_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_XOR_SGPR_gfx10:
    case AMDGPU::S_ATOMIC_XOR_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_STORE_DWORDX2_SGPR_gfx10:
    case AMDGPU::S_BUFFER_STORE_DWORDX4_SGPR_gfx10:
    case AMDGPU::S_BUFFER_STORE_DWORD_SGPR_gfx10:
    case AMDGPU::S_SCRATCH_STORE_DWORDX2_SGPR_gfx10:
    case AMDGPU::S_SCRATCH_STORE_DWORDX4_SGPR_gfx10:
    case AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_gfx10:
    case AMDGPU::S_STORE_DWORDX2_SGPR_gfx10:
    case AMDGPU::S_STORE_DWORDX4_SGPR_gfx10:
    case AMDGPU::S_STORE_DWORD_SGPR_gfx10: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 2:
        // op: soffset
        return 57;
      case 3:
        // op: cpol
        return 14;
      case 0:
        // op: sdata
        return 6;
      }
      break;
    }
    case AMDGPU::S_BUFFER_STORE_DWORDX2_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_STORE_DWORDX4_SGPR_alt_gfx9:
    case AMDGPU::S_BUFFER_STORE_DWORD_SGPR_alt_gfx9:
    case AMDGPU::S_SCRATCH_STORE_DWORDX2_SGPR_alt_gfx9:
    case AMDGPU::S_SCRATCH_STORE_DWORDX4_SGPR_alt_gfx9:
    case AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_alt_gfx9:
    case AMDGPU::S_STORE_DWORDX2_SGPR_alt_gfx9:
    case AMDGPU::S_STORE_DWORDX4_SGPR_alt_gfx9:
    case AMDGPU::S_STORE_DWORD_SGPR_alt_gfx9: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 2:
        // op: soffset
        return 57;
      case 3:
        // op: cpol
        return 16;
      case 0:
        // op: sdata
        return 6;
      }
      break;
    }
    case AMDGPU::S_ATC_PROBE_BUFFER_SGPR_IMM_gfx10:
    case AMDGPU::S_ATC_PROBE_BUFFER_SGPR_IMM_gfx11:
    case AMDGPU::S_ATC_PROBE_BUFFER_SGPR_IMM_gfx12:
    case AMDGPU::S_ATC_PROBE_BUFFER_SGPR_IMM_gfx9:
    case AMDGPU::S_ATC_PROBE_SGPR_IMM_gfx10:
    case AMDGPU::S_ATC_PROBE_SGPR_IMM_gfx11:
    case AMDGPU::S_ATC_PROBE_SGPR_IMM_gfx12:
    case AMDGPU::S_ATC_PROBE_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_ADD_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_ADD_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_AND_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_AND_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_CMPSWAP_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_DEC_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_DEC_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_INC_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_INC_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_OR_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_OR_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_SMAX_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_SMAX_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_SMIN_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_SMIN_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_SUB_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_SUB_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_SWAP_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_SWAP_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_UMAX_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_UMAX_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_UMIN_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_UMIN_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_XOR_SGPR_IMM_gfx9:
    case AMDGPU::S_ATOMIC_XOR_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_IMM_gfx9: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 3:
        // op: offset
        return 32;
      case 2:
        // op: soffset
        return 57;
      case 0:
        // op: sdata
        return 6;
      }
      break;
    }
    case AMDGPU::S_ATOMIC_ADD_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_ADD_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_AND_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_AND_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_DEC_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_DEC_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_INC_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_INC_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_OR_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_OR_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SUB_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SUB_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_XOR_SGPR_IMM_gfx10:
    case AMDGPU::S_ATOMIC_XOR_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_STORE_DWORDX2_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_STORE_DWORDX4_SGPR_IMM_gfx10:
    case AMDGPU::S_BUFFER_STORE_DWORD_SGPR_IMM_gfx10:
    case AMDGPU::S_SCRATCH_STORE_DWORDX2_SGPR_IMM_gfx10:
    case AMDGPU::S_SCRATCH_STORE_DWORDX4_SGPR_IMM_gfx10:
    case AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_IMM_gfx10:
    case AMDGPU::S_STORE_DWORDX2_SGPR_IMM_gfx10:
    case AMDGPU::S_STORE_DWORDX4_SGPR_IMM_gfx10:
    case AMDGPU::S_STORE_DWORD_SGPR_IMM_gfx10: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 3:
        // op: offset
        return 32;
      case 2:
        // op: soffset
        return 57;
      case 4:
        // op: cpol
        return 14;
      case 0:
        // op: sdata
        return 6;
      }
      break;
    }
    case AMDGPU::S_BUFFER_STORE_DWORDX2_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_STORE_DWORDX4_SGPR_IMM_gfx9:
    case AMDGPU::S_BUFFER_STORE_DWORD_SGPR_IMM_gfx9:
    case AMDGPU::S_SCRATCH_STORE_DWORDX2_SGPR_IMM_gfx9:
    case AMDGPU::S_SCRATCH_STORE_DWORDX4_SGPR_IMM_gfx9:
    case AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_IMM_gfx9:
    case AMDGPU::S_STORE_DWORDX2_SGPR_IMM_gfx9:
    case AMDGPU::S_STORE_DWORDX4_SGPR_IMM_gfx9:
    case AMDGPU::S_STORE_DWORD_SGPR_IMM_gfx9: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 0;
      case 3:
        // op: offset
        return 32;
      case 2:
        // op: soffset
        return 57;
      case 4:
        // op: cpol
        return 16;
      case 0:
        // op: sdata
        return 6;
      }
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_si:
    case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_si:
    case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_si:
    case AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_si:
    case AMDGPU::S_BUFFER_LOAD_DWORD_IMM_si:
    case AMDGPU::S_LOAD_DWORDX16_IMM_si:
    case AMDGPU::S_LOAD_DWORDX2_IMM_si:
    case AMDGPU::S_LOAD_DWORDX4_IMM_si:
    case AMDGPU::S_LOAD_DWORDX8_IMM_si:
    case AMDGPU::S_LOAD_DWORD_IMM_si: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 9;
      case 0:
        // op: sdst
        return 15;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_ci:
    case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_ci:
    case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_ci:
    case AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_ci:
    case AMDGPU::S_BUFFER_LOAD_DWORD_IMM_ci:
    case AMDGPU::S_LOAD_DWORDX16_IMM_ci:
    case AMDGPU::S_LOAD_DWORDX2_IMM_ci:
    case AMDGPU::S_LOAD_DWORDX4_IMM_ci:
    case AMDGPU::S_LOAD_DWORDX8_IMM_ci:
    case AMDGPU::S_LOAD_DWORD_IMM_ci: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 9;
      case 0:
        // op: sdst
        return 15;
      case 2:
        // op: offset
        return 32;
      }
      break;
    }
    case AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_si:
    case AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_si:
    case AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_si:
    case AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_si:
    case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_si:
    case AMDGPU::S_LOAD_DWORDX16_SGPR_si:
    case AMDGPU::S_LOAD_DWORDX2_SGPR_si:
    case AMDGPU::S_LOAD_DWORDX4_SGPR_si:
    case AMDGPU::S_LOAD_DWORDX8_SGPR_si:
    case AMDGPU::S_LOAD_DWORD_SGPR_si: {
      switch (OpNum) {
      case 1:
        // op: sbase
        return 9;
      case 0:
        // op: sdst
        return 15;
      case 2:
        // op: soffset
        return 0;
      }
      break;
    }
    case AMDGPU::S_SUBVECTOR_LOOP_BEGIN_gfx10:
    case AMDGPU::S_SUBVECTOR_LOOP_BEGIN_gfx11:
    case AMDGPU::S_SUBVECTOR_LOOP_END_gfx10:
    case AMDGPU::S_SUBVECTOR_LOOP_END_gfx11: {
      switch (OpNum) {
      case 1:
        // op: sdst
        return 16;
      case 0:
        // op: simm16
        return 0;
      }
      break;
    }
    case AMDGPU::S_SETREG_IMM32_B32_gfx10:
    case AMDGPU::S_SETREG_IMM32_B32_gfx11:
    case AMDGPU::S_SETREG_IMM32_B32_gfx12:
    case AMDGPU::S_SETREG_IMM32_B32_gfx6_gfx7:
    case AMDGPU::S_SETREG_IMM32_B32_vi: {
      switch (OpNum) {
      case 1:
        // op: simm16
        return 0;
      case 0:
        // op: imm
        return 32;
      }
      break;
    }
    case AMDGPU::V_CVT_F32_BF8_e64_gfx12:
    case AMDGPU::V_CVT_F32_FP8_e64_gfx11:
    case AMDGPU::V_CVT_F32_FP8_e64_gfx12: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 32;
      case 0:
        // op: vdst
        return 0;
      case 2:
        // op: byte_sel
        return 11;
      }
      break;
    }
    case AMDGPU::V_BFREV_B32_e64_gfx10:
    case AMDGPU::V_BFREV_B32_e64_gfx11:
    case AMDGPU::V_BFREV_B32_e64_gfx12:
    case AMDGPU::V_BFREV_B32_e64_gfx6_gfx7:
    case AMDGPU::V_BFREV_B32_e64_vi:
    case AMDGPU::V_CLS_I32_e64_gfx11:
    case AMDGPU::V_CLS_I32_e64_gfx12:
    case AMDGPU::V_CLZ_I32_U32_e64_gfx11:
    case AMDGPU::V_CLZ_I32_U32_e64_gfx12:
    case AMDGPU::V_CTZ_I32_B32_e64_gfx11:
    case AMDGPU::V_CTZ_I32_B32_e64_gfx12:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_e64_gfx12:
    case AMDGPU::V_FFBH_I32_e64_gfx10:
    case AMDGPU::V_FFBH_I32_e64_gfx6_gfx7:
    case AMDGPU::V_FFBH_I32_e64_vi:
    case AMDGPU::V_FFBH_U32_e64_gfx10:
    case AMDGPU::V_FFBH_U32_e64_gfx6_gfx7:
    case AMDGPU::V_FFBH_U32_e64_vi:
    case AMDGPU::V_FFBL_B32_e64_gfx10:
    case AMDGPU::V_FFBL_B32_e64_gfx6_gfx7:
    case AMDGPU::V_FFBL_B32_e64_vi:
    case AMDGPU::V_MOVRELD_B32_e64_gfx10:
    case AMDGPU::V_MOVRELD_B32_e64_gfx11:
    case AMDGPU::V_MOVRELD_B32_e64_gfx12:
    case AMDGPU::V_MOVRELD_B32_e64_gfx6_gfx7:
    case AMDGPU::V_MOVRELD_B32_e64_vi:
    case AMDGPU::V_MOVRELSD_2_B32_e64_gfx10:
    case AMDGPU::V_MOVRELSD_2_B32_e64_gfx11:
    case AMDGPU::V_MOVRELSD_2_B32_e64_gfx12:
    case AMDGPU::V_MOVRELSD_B32_e64_gfx10:
    case AMDGPU::V_MOVRELSD_B32_e64_gfx11:
    case AMDGPU::V_MOVRELSD_B32_e64_gfx12:
    case AMDGPU::V_MOVRELSD_B32_e64_gfx6_gfx7:
    case AMDGPU::V_MOVRELSD_B32_e64_vi:
    case AMDGPU::V_MOVRELS_B32_e64_gfx10:
    case AMDGPU::V_MOVRELS_B32_e64_gfx11:
    case AMDGPU::V_MOVRELS_B32_e64_gfx12:
    case AMDGPU::V_MOVRELS_B32_e64_gfx6_gfx7:
    case AMDGPU::V_MOVRELS_B32_e64_vi:
    case AMDGPU::V_MOV_B32_e64_gfx10:
    case AMDGPU::V_MOV_B32_e64_gfx11:
    case AMDGPU::V_MOV_B32_e64_gfx12:
    case AMDGPU::V_MOV_B32_e64_gfx6_gfx7:
    case AMDGPU::V_MOV_B32_e64_vi:
    case AMDGPU::V_MOV_B64_e64_gfx1250:
    case AMDGPU::V_MOV_B64_e64_vi:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_e64_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_e64_gfx12:
    case AMDGPU::V_NOT_B32_e64_gfx10:
    case AMDGPU::V_NOT_B32_e64_gfx11:
    case AMDGPU::V_NOT_B32_e64_gfx12:
    case AMDGPU::V_NOT_B32_e64_gfx6_gfx7:
    case AMDGPU::V_NOT_B32_e64_vi:
    case AMDGPU::V_PRNG_B32_e64_gfx1250:
    case AMDGPU::V_PRNG_B32_e64_vi:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_fake16_e64_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_fake16_e64_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e64_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_e64_gfx12:
    case AMDGPU::V_SAT_PK_U8_I16_e64_gfx10:
    case AMDGPU::V_SAT_PK_U8_I16_e64_vi:
    case AMDGPU::V_SCREEN_PARTITION_4SE_B32_e64_vi: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 32;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CVT_F32_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_UBYTE0_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_UBYTE1_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_UBYTE2_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_UBYTE3_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F64_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F64_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_OFF_F32_I4_e64_gfx6_gfx7: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: clamp
        return 11;
      case 3:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CVT_F32_FP8_e64_gfx1250: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: byte_sel
        return 11;
      }
      break;
    }
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_F16_I16_e64_gfx10:
    case AMDGPU::V_CVT_F16_I16_e64_vi:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_F16_U16_e64_gfx10:
    case AMDGPU::V_CVT_F16_U16_e64_vi:
    case AMDGPU::V_CVT_F32_BF8_e64_vi:
    case AMDGPU::V_CVT_F32_FP8_e64_vi:
    case AMDGPU::V_CVT_F32_I32_e64_gfx10:
    case AMDGPU::V_CVT_F32_I32_e64_gfx11:
    case AMDGPU::V_CVT_F32_I32_e64_gfx12:
    case AMDGPU::V_CVT_F32_I32_e64_vi:
    case AMDGPU::V_CVT_F32_U32_e64_gfx10:
    case AMDGPU::V_CVT_F32_U32_e64_gfx11:
    case AMDGPU::V_CVT_F32_U32_e64_gfx12:
    case AMDGPU::V_CVT_F32_U32_e64_vi:
    case AMDGPU::V_CVT_F32_UBYTE0_e64_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE0_e64_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE0_e64_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE0_e64_vi:
    case AMDGPU::V_CVT_F32_UBYTE1_e64_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE1_e64_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE1_e64_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE1_e64_vi:
    case AMDGPU::V_CVT_F32_UBYTE2_e64_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE2_e64_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE2_e64_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE2_e64_vi:
    case AMDGPU::V_CVT_F32_UBYTE3_e64_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE3_e64_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE3_e64_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE3_e64_vi:
    case AMDGPU::V_CVT_F64_I32_e64_gfx10:
    case AMDGPU::V_CVT_F64_I32_e64_gfx11:
    case AMDGPU::V_CVT_F64_I32_e64_gfx12:
    case AMDGPU::V_CVT_F64_I32_e64_vi:
    case AMDGPU::V_CVT_F64_U32_e64_gfx10:
    case AMDGPU::V_CVT_F64_U32_e64_gfx11:
    case AMDGPU::V_CVT_F64_U32_e64_gfx12:
    case AMDGPU::V_CVT_F64_U32_e64_vi:
    case AMDGPU::V_CVT_OFF_F32_I4_e64_gfx10:
    case AMDGPU::V_CVT_OFF_F32_I4_e64_gfx11:
    case AMDGPU::V_CVT_OFF_F32_I4_e64_gfx12:
    case AMDGPU::V_CVT_OFF_F32_I4_e64_vi:
    case AMDGPU::V_CVT_PK_F32_BF8_e64_vi:
    case AMDGPU::V_CVT_PK_F32_FP8_e64_vi: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: clamp
        return 15;
      case 3:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CMPX_EQ_I16_e64_vi:
    case AMDGPU::V_CMPX_EQ_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_I32_e64_vi:
    case AMDGPU::V_CMPX_EQ_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_I64_e64_vi:
    case AMDGPU::V_CMPX_EQ_U16_e64_vi:
    case AMDGPU::V_CMPX_EQ_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_U32_e64_vi:
    case AMDGPU::V_CMPX_EQ_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_U64_e64_vi:
    case AMDGPU::V_CMPX_F_I16_e64_vi:
    case AMDGPU::V_CMPX_F_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_I32_e64_vi:
    case AMDGPU::V_CMPX_F_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_I64_e64_vi:
    case AMDGPU::V_CMPX_F_U16_e64_vi:
    case AMDGPU::V_CMPX_F_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_U32_e64_vi:
    case AMDGPU::V_CMPX_F_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_U64_e64_vi:
    case AMDGPU::V_CMPX_GE_I16_e64_vi:
    case AMDGPU::V_CMPX_GE_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_I32_e64_vi:
    case AMDGPU::V_CMPX_GE_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_I64_e64_vi:
    case AMDGPU::V_CMPX_GE_U16_e64_vi:
    case AMDGPU::V_CMPX_GE_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_U32_e64_vi:
    case AMDGPU::V_CMPX_GE_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_U64_e64_vi:
    case AMDGPU::V_CMPX_GT_I16_e64_vi:
    case AMDGPU::V_CMPX_GT_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_I32_e64_vi:
    case AMDGPU::V_CMPX_GT_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_I64_e64_vi:
    case AMDGPU::V_CMPX_GT_U16_e64_vi:
    case AMDGPU::V_CMPX_GT_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_U32_e64_vi:
    case AMDGPU::V_CMPX_GT_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_U64_e64_vi:
    case AMDGPU::V_CMPX_LE_I16_e64_vi:
    case AMDGPU::V_CMPX_LE_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_I32_e64_vi:
    case AMDGPU::V_CMPX_LE_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_I64_e64_vi:
    case AMDGPU::V_CMPX_LE_U16_e64_vi:
    case AMDGPU::V_CMPX_LE_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_U32_e64_vi:
    case AMDGPU::V_CMPX_LE_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_U64_e64_vi:
    case AMDGPU::V_CMPX_LT_I16_e64_vi:
    case AMDGPU::V_CMPX_LT_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_I32_e64_vi:
    case AMDGPU::V_CMPX_LT_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_I64_e64_vi:
    case AMDGPU::V_CMPX_LT_U16_e64_vi:
    case AMDGPU::V_CMPX_LT_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_U32_e64_vi:
    case AMDGPU::V_CMPX_LT_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_U64_e64_vi:
    case AMDGPU::V_CMPX_NE_I16_e64_vi:
    case AMDGPU::V_CMPX_NE_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NE_I32_e64_vi:
    case AMDGPU::V_CMPX_NE_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NE_I64_e64_vi:
    case AMDGPU::V_CMPX_NE_U16_e64_vi:
    case AMDGPU::V_CMPX_NE_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NE_U32_e64_vi:
    case AMDGPU::V_CMPX_NE_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NE_U64_e64_vi:
    case AMDGPU::V_CMPX_T_I16_e64_vi:
    case AMDGPU::V_CMPX_T_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_T_I32_e64_vi:
    case AMDGPU::V_CMPX_T_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_T_I64_e64_vi:
    case AMDGPU::V_CMPX_T_U16_e64_vi:
    case AMDGPU::V_CMPX_T_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_T_U32_e64_vi:
    case AMDGPU::V_CMPX_T_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_T_U64_e64_vi:
    case AMDGPU::V_CMP_EQ_I16_e64_gfx10:
    case AMDGPU::V_CMP_EQ_I16_e64_vi:
    case AMDGPU::V_CMP_EQ_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e64_gfx10:
    case AMDGPU::V_CMP_EQ_I32_e64_gfx11:
    case AMDGPU::V_CMP_EQ_I32_e64_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_I32_e64_vi:
    case AMDGPU::V_CMP_EQ_I64_e64_gfx10:
    case AMDGPU::V_CMP_EQ_I64_e64_gfx11:
    case AMDGPU::V_CMP_EQ_I64_e64_gfx12:
    case AMDGPU::V_CMP_EQ_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_I64_e64_vi:
    case AMDGPU::V_CMP_EQ_U16_e64_gfx10:
    case AMDGPU::V_CMP_EQ_U16_e64_vi:
    case AMDGPU::V_CMP_EQ_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_EQ_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e64_gfx10:
    case AMDGPU::V_CMP_EQ_U32_e64_gfx11:
    case AMDGPU::V_CMP_EQ_U32_e64_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_U32_e64_vi:
    case AMDGPU::V_CMP_EQ_U64_e64_gfx10:
    case AMDGPU::V_CMP_EQ_U64_e64_gfx11:
    case AMDGPU::V_CMP_EQ_U64_e64_gfx12:
    case AMDGPU::V_CMP_EQ_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_U64_e64_vi:
    case AMDGPU::V_CMP_F_I16_e64_vi:
    case AMDGPU::V_CMP_F_I32_e64_gfx10:
    case AMDGPU::V_CMP_F_I32_e64_gfx11:
    case AMDGPU::V_CMP_F_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_F_I32_e64_vi:
    case AMDGPU::V_CMP_F_I64_e64_gfx10:
    case AMDGPU::V_CMP_F_I64_e64_gfx11:
    case AMDGPU::V_CMP_F_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_F_I64_e64_vi:
    case AMDGPU::V_CMP_F_U16_e64_vi:
    case AMDGPU::V_CMP_F_U32_e64_gfx10:
    case AMDGPU::V_CMP_F_U32_e64_gfx11:
    case AMDGPU::V_CMP_F_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_F_U32_e64_vi:
    case AMDGPU::V_CMP_F_U64_e64_gfx10:
    case AMDGPU::V_CMP_F_U64_e64_gfx11:
    case AMDGPU::V_CMP_F_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_F_U64_e64_vi:
    case AMDGPU::V_CMP_GE_I16_e64_gfx10:
    case AMDGPU::V_CMP_GE_I16_e64_vi:
    case AMDGPU::V_CMP_GE_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_GE_I32_e64_gfx10:
    case AMDGPU::V_CMP_GE_I32_e64_gfx11:
    case AMDGPU::V_CMP_GE_I32_e64_gfx12:
    case AMDGPU::V_CMP_GE_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_I32_e64_vi:
    case AMDGPU::V_CMP_GE_I64_e64_gfx10:
    case AMDGPU::V_CMP_GE_I64_e64_gfx11:
    case AMDGPU::V_CMP_GE_I64_e64_gfx12:
    case AMDGPU::V_CMP_GE_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_I64_e64_vi:
    case AMDGPU::V_CMP_GE_U16_e64_gfx10:
    case AMDGPU::V_CMP_GE_U16_e64_vi:
    case AMDGPU::V_CMP_GE_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_GE_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_GE_U32_e64_gfx10:
    case AMDGPU::V_CMP_GE_U32_e64_gfx11:
    case AMDGPU::V_CMP_GE_U32_e64_gfx12:
    case AMDGPU::V_CMP_GE_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_U32_e64_vi:
    case AMDGPU::V_CMP_GE_U64_e64_gfx10:
    case AMDGPU::V_CMP_GE_U64_e64_gfx11:
    case AMDGPU::V_CMP_GE_U64_e64_gfx12:
    case AMDGPU::V_CMP_GE_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_U64_e64_vi:
    case AMDGPU::V_CMP_GT_I16_e64_gfx10:
    case AMDGPU::V_CMP_GT_I16_e64_vi:
    case AMDGPU::V_CMP_GT_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_GT_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_GT_I32_e64_gfx10:
    case AMDGPU::V_CMP_GT_I32_e64_gfx11:
    case AMDGPU::V_CMP_GT_I32_e64_gfx12:
    case AMDGPU::V_CMP_GT_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_I32_e64_vi:
    case AMDGPU::V_CMP_GT_I64_e64_gfx10:
    case AMDGPU::V_CMP_GT_I64_e64_gfx11:
    case AMDGPU::V_CMP_GT_I64_e64_gfx12:
    case AMDGPU::V_CMP_GT_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_I64_e64_vi:
    case AMDGPU::V_CMP_GT_U16_e64_gfx10:
    case AMDGPU::V_CMP_GT_U16_e64_vi:
    case AMDGPU::V_CMP_GT_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_GT_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_GT_U32_e64_gfx10:
    case AMDGPU::V_CMP_GT_U32_e64_gfx11:
    case AMDGPU::V_CMP_GT_U32_e64_gfx12:
    case AMDGPU::V_CMP_GT_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_U32_e64_vi:
    case AMDGPU::V_CMP_GT_U64_e64_gfx10:
    case AMDGPU::V_CMP_GT_U64_e64_gfx11:
    case AMDGPU::V_CMP_GT_U64_e64_gfx12:
    case AMDGPU::V_CMP_GT_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_U64_e64_vi:
    case AMDGPU::V_CMP_LE_I16_e64_gfx10:
    case AMDGPU::V_CMP_LE_I16_e64_vi:
    case AMDGPU::V_CMP_LE_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_LE_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_LE_I32_e64_gfx10:
    case AMDGPU::V_CMP_LE_I32_e64_gfx11:
    case AMDGPU::V_CMP_LE_I32_e64_gfx12:
    case AMDGPU::V_CMP_LE_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_I32_e64_vi:
    case AMDGPU::V_CMP_LE_I64_e64_gfx10:
    case AMDGPU::V_CMP_LE_I64_e64_gfx11:
    case AMDGPU::V_CMP_LE_I64_e64_gfx12:
    case AMDGPU::V_CMP_LE_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_I64_e64_vi:
    case AMDGPU::V_CMP_LE_U16_e64_gfx10:
    case AMDGPU::V_CMP_LE_U16_e64_vi:
    case AMDGPU::V_CMP_LE_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_LE_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_LE_U32_e64_gfx10:
    case AMDGPU::V_CMP_LE_U32_e64_gfx11:
    case AMDGPU::V_CMP_LE_U32_e64_gfx12:
    case AMDGPU::V_CMP_LE_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_U32_e64_vi:
    case AMDGPU::V_CMP_LE_U64_e64_gfx10:
    case AMDGPU::V_CMP_LE_U64_e64_gfx11:
    case AMDGPU::V_CMP_LE_U64_e64_gfx12:
    case AMDGPU::V_CMP_LE_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_U64_e64_vi:
    case AMDGPU::V_CMP_LT_I16_e64_gfx10:
    case AMDGPU::V_CMP_LT_I16_e64_vi:
    case AMDGPU::V_CMP_LT_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_LT_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_LT_I32_e64_gfx10:
    case AMDGPU::V_CMP_LT_I32_e64_gfx11:
    case AMDGPU::V_CMP_LT_I32_e64_gfx12:
    case AMDGPU::V_CMP_LT_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_I32_e64_vi:
    case AMDGPU::V_CMP_LT_I64_e64_gfx10:
    case AMDGPU::V_CMP_LT_I64_e64_gfx11:
    case AMDGPU::V_CMP_LT_I64_e64_gfx12:
    case AMDGPU::V_CMP_LT_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_I64_e64_vi:
    case AMDGPU::V_CMP_LT_U16_e64_gfx10:
    case AMDGPU::V_CMP_LT_U16_e64_vi:
    case AMDGPU::V_CMP_LT_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_LT_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_LT_U32_e64_gfx10:
    case AMDGPU::V_CMP_LT_U32_e64_gfx11:
    case AMDGPU::V_CMP_LT_U32_e64_gfx12:
    case AMDGPU::V_CMP_LT_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_U32_e64_vi:
    case AMDGPU::V_CMP_LT_U64_e64_gfx10:
    case AMDGPU::V_CMP_LT_U64_e64_gfx11:
    case AMDGPU::V_CMP_LT_U64_e64_gfx12:
    case AMDGPU::V_CMP_LT_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_U64_e64_vi:
    case AMDGPU::V_CMP_NE_I16_e64_gfx10:
    case AMDGPU::V_CMP_NE_I16_e64_vi:
    case AMDGPU::V_CMP_NE_I16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_NE_I16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_NE_I32_e64_gfx10:
    case AMDGPU::V_CMP_NE_I32_e64_gfx11:
    case AMDGPU::V_CMP_NE_I32_e64_gfx12:
    case AMDGPU::V_CMP_NE_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NE_I32_e64_vi:
    case AMDGPU::V_CMP_NE_I64_e64_gfx10:
    case AMDGPU::V_CMP_NE_I64_e64_gfx11:
    case AMDGPU::V_CMP_NE_I64_e64_gfx12:
    case AMDGPU::V_CMP_NE_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NE_I64_e64_vi:
    case AMDGPU::V_CMP_NE_U16_e64_gfx10:
    case AMDGPU::V_CMP_NE_U16_e64_vi:
    case AMDGPU::V_CMP_NE_U16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_NE_U16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_NE_U32_e64_gfx10:
    case AMDGPU::V_CMP_NE_U32_e64_gfx11:
    case AMDGPU::V_CMP_NE_U32_e64_gfx12:
    case AMDGPU::V_CMP_NE_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NE_U32_e64_vi:
    case AMDGPU::V_CMP_NE_U64_e64_gfx10:
    case AMDGPU::V_CMP_NE_U64_e64_gfx11:
    case AMDGPU::V_CMP_NE_U64_e64_gfx12:
    case AMDGPU::V_CMP_NE_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NE_U64_e64_vi:
    case AMDGPU::V_CMP_T_I16_e64_vi:
    case AMDGPU::V_CMP_T_I32_e64_gfx10:
    case AMDGPU::V_CMP_T_I32_e64_gfx11:
    case AMDGPU::V_CMP_T_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_T_I32_e64_vi:
    case AMDGPU::V_CMP_T_I64_e64_gfx10:
    case AMDGPU::V_CMP_T_I64_e64_gfx11:
    case AMDGPU::V_CMP_T_I64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_T_I64_e64_vi:
    case AMDGPU::V_CMP_T_U16_e64_vi:
    case AMDGPU::V_CMP_T_U32_e64_gfx10:
    case AMDGPU::V_CMP_T_U32_e64_gfx11:
    case AMDGPU::V_CMP_T_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_T_U32_e64_vi:
    case AMDGPU::V_CMP_T_U64_e64_gfx10:
    case AMDGPU::V_CMP_T_U64_e64_gfx11:
    case AMDGPU::V_CMP_T_U64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_T_U64_e64_vi: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1
        return 41;
      case 0:
        // op: sdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CVT_SCALE_PK16_BF16_BF6_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK16_BF16_FP6_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK16_F16_BF6_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK16_F16_FP6_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK16_F32_BF6_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK16_F32_FP6_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK8_BF16_BF8_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK8_BF16_FP4_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK8_BF16_FP8_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK8_F16_BF8_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK8_F16_FP4_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK8_F16_FP8_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK8_F32_BF8_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK8_F32_FP4_e64_gfx1250:
    case AMDGPU::V_CVT_SCALE_PK8_F32_FP8_e64_gfx1250: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1
        return 41;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: scale_sel
        return 11;
      }
      break;
    }
    case AMDGPU::V_AND_B16_fake16_e64_gfx11:
    case AMDGPU::V_AND_B16_fake16_e64_gfx12:
    case AMDGPU::V_AND_B32_e64_gfx10:
    case AMDGPU::V_AND_B32_e64_gfx11:
    case AMDGPU::V_AND_B32_e64_gfx12:
    case AMDGPU::V_AND_B32_e64_gfx6_gfx7:
    case AMDGPU::V_AND_B32_e64_vi:
    case AMDGPU::V_ASHRREV_I16_e64_vi:
    case AMDGPU::V_ASHRREV_I16_fake16_e64_gfx11:
    case AMDGPU::V_ASHRREV_I16_fake16_e64_gfx12:
    case AMDGPU::V_ASHRREV_I32_e64_gfx10:
    case AMDGPU::V_ASHRREV_I32_e64_gfx11:
    case AMDGPU::V_ASHRREV_I32_e64_gfx12:
    case AMDGPU::V_ASHRREV_I32_e64_gfx6_gfx7:
    case AMDGPU::V_ASHRREV_I32_e64_vi:
    case AMDGPU::V_ASHRREV_I64_e64_gfx11:
    case AMDGPU::V_ASHRREV_I64_e64_gfx12:
    case AMDGPU::V_ASHRREV_I64_e64_gfx1250:
    case AMDGPU::V_ASHRREV_I64_gfx10:
    case AMDGPU::V_ASHRREV_I64_vi:
    case AMDGPU::V_ASHR_I32_e64_gfx6_gfx7:
    case AMDGPU::V_ASHR_I64_gfx6_gfx7:
    case AMDGPU::V_BCNT_U32_B32_e64_gfx10:
    case AMDGPU::V_BCNT_U32_B32_e64_gfx11:
    case AMDGPU::V_BCNT_U32_B32_e64_gfx12:
    case AMDGPU::V_BCNT_U32_B32_e64_gfx6_gfx7:
    case AMDGPU::V_BCNT_U32_B32_e64_vi:
    case AMDGPU::V_BFM_B32_e64_gfx10:
    case AMDGPU::V_BFM_B32_e64_gfx11:
    case AMDGPU::V_BFM_B32_e64_gfx12:
    case AMDGPU::V_BFM_B32_e64_gfx6_gfx7:
    case AMDGPU::V_BFM_B32_e64_vi:
    case AMDGPU::V_CVT_PK_I16_I32_e64_gfx10:
    case AMDGPU::V_CVT_PK_I16_I32_e64_gfx11:
    case AMDGPU::V_CVT_PK_I16_I32_e64_gfx12:
    case AMDGPU::V_CVT_PK_I16_I32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_PK_I16_I32_e64_vi:
    case AMDGPU::V_CVT_PK_U16_U32_e64_gfx10:
    case AMDGPU::V_CVT_PK_U16_U32_e64_gfx11:
    case AMDGPU::V_CVT_PK_U16_U32_e64_gfx12:
    case AMDGPU::V_CVT_PK_U16_U32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_PK_U16_U32_e64_vi:
    case AMDGPU::V_CVT_SCALEF32_PK16_BF6_BF16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK16_BF6_F16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK16_BF6_F32_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK16_FP6_BF16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK16_FP6_F16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK16_FP6_F32_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK32_BF16_BF6_gfx9:
    case AMDGPU::V_CVT_SCALEF32_PK32_BF16_FP6_gfx9:
    case AMDGPU::V_CVT_SCALEF32_PK32_BF6_BF16_gfx9:
    case AMDGPU::V_CVT_SCALEF32_PK32_BF6_F16_gfx9:
    case AMDGPU::V_CVT_SCALEF32_PK32_F16_BF6_gfx9:
    case AMDGPU::V_CVT_SCALEF32_PK32_F16_FP6_gfx9:
    case AMDGPU::V_CVT_SCALEF32_PK32_F32_BF6_gfx9:
    case AMDGPU::V_CVT_SCALEF32_PK32_F32_FP6_gfx9:
    case AMDGPU::V_CVT_SCALEF32_PK32_FP6_BF16_gfx9:
    case AMDGPU::V_CVT_SCALEF32_PK32_FP6_F16_gfx9:
    case AMDGPU::V_CVT_SCALEF32_PK8_BF8_BF16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK8_BF8_F16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK8_BF8_F32_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK8_FP4_BF16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK8_FP4_F16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK8_FP4_F32_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK8_FP8_BF16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK8_FP8_F16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_PK8_FP8_F32_e64_gfx1250:
    case AMDGPU::V_LSHLREV_B16_e64_vi:
    case AMDGPU::V_LSHLREV_B16_fake16_e64_gfx11:
    case AMDGPU::V_LSHLREV_B16_fake16_e64_gfx12:
    case AMDGPU::V_LSHLREV_B32_e64_gfx10:
    case AMDGPU::V_LSHLREV_B32_e64_gfx11:
    case AMDGPU::V_LSHLREV_B32_e64_gfx12:
    case AMDGPU::V_LSHLREV_B32_e64_gfx6_gfx7:
    case AMDGPU::V_LSHLREV_B32_e64_vi:
    case AMDGPU::V_LSHLREV_B64_e64_gfx11:
    case AMDGPU::V_LSHLREV_B64_e64_gfx12:
    case AMDGPU::V_LSHLREV_B64_gfx10:
    case AMDGPU::V_LSHLREV_B64_vi:
    case AMDGPU::V_LSHL_B32_e64_gfx6_gfx7:
    case AMDGPU::V_LSHL_B64_gfx6_gfx7:
    case AMDGPU::V_LSHRREV_B16_e64_vi:
    case AMDGPU::V_LSHRREV_B16_fake16_e64_gfx11:
    case AMDGPU::V_LSHRREV_B16_fake16_e64_gfx12:
    case AMDGPU::V_LSHRREV_B32_e64_gfx10:
    case AMDGPU::V_LSHRREV_B32_e64_gfx11:
    case AMDGPU::V_LSHRREV_B32_e64_gfx12:
    case AMDGPU::V_LSHRREV_B32_e64_gfx6_gfx7:
    case AMDGPU::V_LSHRREV_B32_e64_vi:
    case AMDGPU::V_LSHRREV_B64_e64_gfx11:
    case AMDGPU::V_LSHRREV_B64_e64_gfx12:
    case AMDGPU::V_LSHRREV_B64_e64_gfx1250:
    case AMDGPU::V_LSHRREV_B64_gfx10:
    case AMDGPU::V_LSHRREV_B64_vi:
    case AMDGPU::V_LSHR_B32_e64_gfx6_gfx7:
    case AMDGPU::V_LSHR_B64_gfx6_gfx7:
    case AMDGPU::V_MAX_I16_e64_vi:
    case AMDGPU::V_MAX_I16_fake16_e64_gfx11:
    case AMDGPU::V_MAX_I16_fake16_e64_gfx12:
    case AMDGPU::V_MAX_I32_e64_gfx10:
    case AMDGPU::V_MAX_I32_e64_gfx11:
    case AMDGPU::V_MAX_I32_e64_gfx12:
    case AMDGPU::V_MAX_I32_e64_gfx6_gfx7:
    case AMDGPU::V_MAX_I32_e64_vi:
    case AMDGPU::V_MAX_I64_e64_gfx1250:
    case AMDGPU::V_MAX_U16_e64_vi:
    case AMDGPU::V_MAX_U16_fake16_e64_gfx11:
    case AMDGPU::V_MAX_U16_fake16_e64_gfx12:
    case AMDGPU::V_MAX_U32_e64_gfx10:
    case AMDGPU::V_MAX_U32_e64_gfx11:
    case AMDGPU::V_MAX_U32_e64_gfx12:
    case AMDGPU::V_MAX_U32_e64_gfx6_gfx7:
    case AMDGPU::V_MAX_U32_e64_vi:
    case AMDGPU::V_MAX_U64_e64_gfx1250:
    case AMDGPU::V_MBCNT_HI_U32_B32_e64_gfx10:
    case AMDGPU::V_MBCNT_HI_U32_B32_e64_gfx11:
    case AMDGPU::V_MBCNT_HI_U32_B32_e64_gfx12:
    case AMDGPU::V_MBCNT_HI_U32_B32_e64_gfx6_gfx7:
    case AMDGPU::V_MBCNT_HI_U32_B32_e64_vi:
    case AMDGPU::V_MBCNT_LO_U32_B32_e64_gfx10:
    case AMDGPU::V_MBCNT_LO_U32_B32_e64_gfx11:
    case AMDGPU::V_MBCNT_LO_U32_B32_e64_gfx12:
    case AMDGPU::V_MBCNT_LO_U32_B32_e64_gfx6_gfx7:
    case AMDGPU::V_MBCNT_LO_U32_B32_e64_vi:
    case AMDGPU::V_MIN_I16_e64_vi:
    case AMDGPU::V_MIN_I16_fake16_e64_gfx11:
    case AMDGPU::V_MIN_I16_fake16_e64_gfx12:
    case AMDGPU::V_MIN_I32_e64_gfx10:
    case AMDGPU::V_MIN_I32_e64_gfx11:
    case AMDGPU::V_MIN_I32_e64_gfx12:
    case AMDGPU::V_MIN_I32_e64_gfx6_gfx7:
    case AMDGPU::V_MIN_I32_e64_vi:
    case AMDGPU::V_MIN_I64_e64_gfx1250:
    case AMDGPU::V_MIN_U16_e64_vi:
    case AMDGPU::V_MIN_U16_fake16_e64_gfx11:
    case AMDGPU::V_MIN_U16_fake16_e64_gfx12:
    case AMDGPU::V_MIN_U32_e64_gfx10:
    case AMDGPU::V_MIN_U32_e64_gfx11:
    case AMDGPU::V_MIN_U32_e64_gfx12:
    case AMDGPU::V_MIN_U32_e64_gfx6_gfx7:
    case AMDGPU::V_MIN_U32_e64_vi:
    case AMDGPU::V_MIN_U64_e64_gfx1250:
    case AMDGPU::V_MUL_HI_I32_I24_e64_gfx10:
    case AMDGPU::V_MUL_HI_I32_I24_e64_gfx11:
    case AMDGPU::V_MUL_HI_I32_I24_e64_gfx12:
    case AMDGPU::V_MUL_HI_I32_I24_e64_gfx6_gfx7:
    case AMDGPU::V_MUL_HI_I32_I24_e64_vi:
    case AMDGPU::V_MUL_HI_I32_e64_gfx11:
    case AMDGPU::V_MUL_HI_I32_e64_gfx12:
    case AMDGPU::V_MUL_HI_I32_e64_gfx1250:
    case AMDGPU::V_MUL_HI_I32_gfx10:
    case AMDGPU::V_MUL_HI_I32_gfx6_gfx7:
    case AMDGPU::V_MUL_HI_I32_vi:
    case AMDGPU::V_MUL_HI_U32_U24_e64_gfx10:
    case AMDGPU::V_MUL_HI_U32_U24_e64_gfx11:
    case AMDGPU::V_MUL_HI_U32_U24_e64_gfx12:
    case AMDGPU::V_MUL_HI_U32_U24_e64_gfx6_gfx7:
    case AMDGPU::V_MUL_HI_U32_U24_e64_vi:
    case AMDGPU::V_MUL_HI_U32_e64_gfx11:
    case AMDGPU::V_MUL_HI_U32_e64_gfx12:
    case AMDGPU::V_MUL_HI_U32_e64_gfx1250:
    case AMDGPU::V_MUL_HI_U32_gfx10:
    case AMDGPU::V_MUL_HI_U32_gfx6_gfx7:
    case AMDGPU::V_MUL_HI_U32_vi:
    case AMDGPU::V_MUL_LO_I32_gfx10:
    case AMDGPU::V_MUL_LO_I32_gfx6_gfx7:
    case AMDGPU::V_MUL_LO_I32_vi:
    case AMDGPU::V_MUL_LO_U16_e64_vi:
    case AMDGPU::V_MUL_LO_U16_fake16_e64_gfx11:
    case AMDGPU::V_MUL_LO_U16_fake16_e64_gfx12:
    case AMDGPU::V_MUL_LO_U32_e64_gfx11:
    case AMDGPU::V_MUL_LO_U32_e64_gfx12:
    case AMDGPU::V_MUL_LO_U32_e64_gfx1250:
    case AMDGPU::V_MUL_LO_U32_gfx10:
    case AMDGPU::V_MUL_LO_U32_gfx6_gfx7:
    case AMDGPU::V_MUL_LO_U32_vi:
    case AMDGPU::V_MUL_U64_e64_gfx1250:
    case AMDGPU::V_OR_B16_fake16_e64_gfx11:
    case AMDGPU::V_OR_B16_fake16_e64_gfx12:
    case AMDGPU::V_OR_B32_e64_gfx10:
    case AMDGPU::V_OR_B32_e64_gfx11:
    case AMDGPU::V_OR_B32_e64_gfx12:
    case AMDGPU::V_OR_B32_e64_gfx6_gfx7:
    case AMDGPU::V_OR_B32_e64_vi:
    case AMDGPU::V_PERMLANE_IDX_GEN_B32_e64_gfx12:
    case AMDGPU::V_READLANE_B32_e64_gfx11:
    case AMDGPU::V_READLANE_B32_e64_gfx12:
    case AMDGPU::V_READLANE_B32_gfx10:
    case AMDGPU::V_READLANE_B32_vi:
    case AMDGPU::V_WRITELANE_B32_e64_gfx11:
    case AMDGPU::V_WRITELANE_B32_e64_gfx12:
    case AMDGPU::V_WRITELANE_B32_gfx10:
    case AMDGPU::V_WRITELANE_B32_vi:
    case AMDGPU::V_XNOR_B32_e64_gfx10:
    case AMDGPU::V_XNOR_B32_e64_gfx11:
    case AMDGPU::V_XNOR_B32_e64_gfx12:
    case AMDGPU::V_XNOR_B32_e64_vi:
    case AMDGPU::V_XOR_B16_fake16_e64_gfx11:
    case AMDGPU::V_XOR_B16_fake16_e64_gfx12:
    case AMDGPU::V_XOR_B32_e64_gfx10:
    case AMDGPU::V_XOR_B32_e64_gfx11:
    case AMDGPU::V_XOR_B32_e64_gfx12:
    case AMDGPU::V_XOR_B32_e64_gfx6_gfx7:
    case AMDGPU::V_XOR_B32_e64_vi: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1
        return 41;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_MUL_I32_I24_e64_gfx6_gfx7:
    case AMDGPU::V_MUL_U32_U24_e64_gfx6_gfx7: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1
        return 41;
      case 3:
        // op: clamp
        return 11;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_ADD_I32_vi:
    case AMDGPU::V_ADD_NC_I32_e64_gfx11:
    case AMDGPU::V_ADD_NC_I32_e64_gfx12:
    case AMDGPU::V_ADD_NC_I32_gfx10:
    case AMDGPU::V_ADD_NC_U32_e64_gfx10:
    case AMDGPU::V_ADD_NC_U32_e64_gfx11:
    case AMDGPU::V_ADD_NC_U32_e64_gfx12:
    case AMDGPU::V_ADD_U16_e64_vi:
    case AMDGPU::V_ADD_U32_e64_gfx9:
    case AMDGPU::V_ADD_U64_e64_gfx1250:
    case AMDGPU::V_MUL_I32_I24_e64_gfx10:
    case AMDGPU::V_MUL_I32_I24_e64_gfx11:
    case AMDGPU::V_MUL_I32_I24_e64_gfx12:
    case AMDGPU::V_MUL_I32_I24_e64_vi:
    case AMDGPU::V_MUL_U32_U24_e64_gfx10:
    case AMDGPU::V_MUL_U32_U24_e64_gfx11:
    case AMDGPU::V_MUL_U32_U24_e64_gfx12:
    case AMDGPU::V_MUL_U32_U24_e64_vi:
    case AMDGPU::V_SUBREV_NC_U32_e64_gfx10:
    case AMDGPU::V_SUBREV_NC_U32_e64_gfx11:
    case AMDGPU::V_SUBREV_NC_U32_e64_gfx12:
    case AMDGPU::V_SUBREV_U16_e64_vi:
    case AMDGPU::V_SUBREV_U32_e64_gfx9:
    case AMDGPU::V_SUB_I32_vi:
    case AMDGPU::V_SUB_NC_I32_e64_gfx11:
    case AMDGPU::V_SUB_NC_I32_e64_gfx12:
    case AMDGPU::V_SUB_NC_I32_gfx10:
    case AMDGPU::V_SUB_NC_U32_e64_gfx10:
    case AMDGPU::V_SUB_NC_U32_e64_gfx11:
    case AMDGPU::V_SUB_NC_U32_e64_gfx12:
    case AMDGPU::V_SUB_U16_e64_vi:
    case AMDGPU::V_SUB_U32_e64_gfx9:
    case AMDGPU::V_SUB_U64_e64_gfx1250: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1
        return 41;
      case 3:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_BITOP3_B32_e64_gfx1250:
    case AMDGPU::V_BITOP3_B32_gfx9: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1
        return 41;
      case 3:
        // op: src2
        return 50;
      case 0:
        // op: vdst
        return 0;
      case 4:
        // op: bitop3
        return 8;
      }
      break;
    }
    case AMDGPU::V_ADD3_U32_e64_gfx11:
    case AMDGPU::V_ADD3_U32_e64_gfx12:
    case AMDGPU::V_ADD3_U32_gfx10:
    case AMDGPU::V_ADD3_U32_vi:
    case AMDGPU::V_ADD_LSHL_U32_e64_gfx11:
    case AMDGPU::V_ADD_LSHL_U32_e64_gfx12:
    case AMDGPU::V_ADD_LSHL_U32_gfx10:
    case AMDGPU::V_ADD_LSHL_U32_vi:
    case AMDGPU::V_ALIGNBIT_B32_gfx6_gfx7:
    case AMDGPU::V_ALIGNBIT_B32_vi:
    case AMDGPU::V_ALIGNBYTE_B32_gfx6_gfx7:
    case AMDGPU::V_ALIGNBYTE_B32_vi:
    case AMDGPU::V_AND_OR_B32_e64_gfx11:
    case AMDGPU::V_AND_OR_B32_e64_gfx12:
    case AMDGPU::V_AND_OR_B32_gfx10:
    case AMDGPU::V_AND_OR_B32_vi:
    case AMDGPU::V_BFE_I32_e64_gfx11:
    case AMDGPU::V_BFE_I32_e64_gfx12:
    case AMDGPU::V_BFE_I32_gfx10:
    case AMDGPU::V_BFE_I32_gfx6_gfx7:
    case AMDGPU::V_BFE_I32_vi:
    case AMDGPU::V_BFE_U32_e64_gfx11:
    case AMDGPU::V_BFE_U32_e64_gfx12:
    case AMDGPU::V_BFE_U32_gfx10:
    case AMDGPU::V_BFE_U32_gfx6_gfx7:
    case AMDGPU::V_BFE_U32_vi:
    case AMDGPU::V_BFI_B32_e64_gfx11:
    case AMDGPU::V_BFI_B32_e64_gfx12:
    case AMDGPU::V_BFI_B32_gfx10:
    case AMDGPU::V_BFI_B32_gfx6_gfx7:
    case AMDGPU::V_BFI_B32_vi:
    case AMDGPU::V_CVT_SCALEF32_2XPK16_BF6_F32_gfx9:
    case AMDGPU::V_CVT_SCALEF32_2XPK16_FP6_F32_gfx9:
    case AMDGPU::V_CVT_SCALEF32_SR_PK16_BF6_BF16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK16_BF6_F16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK16_BF6_F32_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK16_FP6_BF16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK16_FP6_F16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK16_FP6_F32_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK32_BF6_BF16_gfx9:
    case AMDGPU::V_CVT_SCALEF32_SR_PK32_BF6_F16_gfx9:
    case AMDGPU::V_CVT_SCALEF32_SR_PK32_BF6_F32_gfx9:
    case AMDGPU::V_CVT_SCALEF32_SR_PK32_FP6_BF16_gfx9:
    case AMDGPU::V_CVT_SCALEF32_SR_PK32_FP6_F16_gfx9:
    case AMDGPU::V_CVT_SCALEF32_SR_PK32_FP6_F32_gfx9:
    case AMDGPU::V_CVT_SCALEF32_SR_PK8_BF8_BF16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK8_BF8_F16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK8_BF8_F32_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK8_FP4_BF16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK8_FP4_F16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK8_FP4_F32_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK8_FP8_BF16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK8_FP8_F16_e64_gfx1250:
    case AMDGPU::V_CVT_SCALEF32_SR_PK8_FP8_F32_e64_gfx1250:
    case AMDGPU::V_LERP_U8_e64_gfx11:
    case AMDGPU::V_LERP_U8_e64_gfx12:
    case AMDGPU::V_LERP_U8_gfx10:
    case AMDGPU::V_LERP_U8_gfx6_gfx7:
    case AMDGPU::V_LERP_U8_vi:
    case AMDGPU::V_LSHL_ADD_U32_e64_gfx11:
    case AMDGPU::V_LSHL_ADD_U32_e64_gfx12:
    case AMDGPU::V_LSHL_ADD_U32_gfx10:
    case AMDGPU::V_LSHL_ADD_U32_vi:
    case AMDGPU::V_LSHL_ADD_U64_e64_gfx1250:
    case AMDGPU::V_LSHL_ADD_U64_vi:
    case AMDGPU::V_LSHL_OR_B32_e64_gfx11:
    case AMDGPU::V_LSHL_OR_B32_e64_gfx12:
    case AMDGPU::V_LSHL_OR_B32_gfx10:
    case AMDGPU::V_LSHL_OR_B32_vi:
    case AMDGPU::V_MAD_U32_e64_gfx1250:
    case AMDGPU::V_MAX3_I32_e64_gfx11:
    case AMDGPU::V_MAX3_I32_e64_gfx12:
    case AMDGPU::V_MAX3_I32_gfx10:
    case AMDGPU::V_MAX3_I32_gfx6_gfx7:
    case AMDGPU::V_MAX3_I32_vi:
    case AMDGPU::V_MAX3_U32_e64_gfx11:
    case AMDGPU::V_MAX3_U32_e64_gfx12:
    case AMDGPU::V_MAX3_U32_gfx10:
    case AMDGPU::V_MAX3_U32_gfx6_gfx7:
    case AMDGPU::V_MAX3_U32_vi:
    case AMDGPU::V_MAXMIN_I32_e64_gfx11:
    case AMDGPU::V_MAXMIN_I32_e64_gfx12:
    case AMDGPU::V_MAXMIN_U32_e64_gfx11:
    case AMDGPU::V_MAXMIN_U32_e64_gfx12:
    case AMDGPU::V_MED3_I32_e64_gfx11:
    case AMDGPU::V_MED3_I32_e64_gfx12:
    case AMDGPU::V_MED3_I32_gfx10:
    case AMDGPU::V_MED3_I32_gfx6_gfx7:
    case AMDGPU::V_MED3_I32_vi:
    case AMDGPU::V_MED3_U32_e64_gfx11:
    case AMDGPU::V_MED3_U32_e64_gfx12:
    case AMDGPU::V_MED3_U32_gfx10:
    case AMDGPU::V_MED3_U32_gfx6_gfx7:
    case AMDGPU::V_MED3_U32_vi:
    case AMDGPU::V_MIN3_I32_e64_gfx11:
    case AMDGPU::V_MIN3_I32_e64_gfx12:
    case AMDGPU::V_MIN3_I32_gfx10:
    case AMDGPU::V_MIN3_I32_gfx6_gfx7:
    case AMDGPU::V_MIN3_I32_vi:
    case AMDGPU::V_MIN3_U32_e64_gfx11:
    case AMDGPU::V_MIN3_U32_e64_gfx12:
    case AMDGPU::V_MIN3_U32_gfx10:
    case AMDGPU::V_MIN3_U32_gfx6_gfx7:
    case AMDGPU::V_MIN3_U32_vi:
    case AMDGPU::V_MINMAX_I32_e64_gfx11:
    case AMDGPU::V_MINMAX_I32_e64_gfx12:
    case AMDGPU::V_MINMAX_U32_e64_gfx11:
    case AMDGPU::V_MINMAX_U32_e64_gfx12:
    case AMDGPU::V_OR3_B32_e64_gfx11:
    case AMDGPU::V_OR3_B32_e64_gfx12:
    case AMDGPU::V_OR3_B32_gfx10:
    case AMDGPU::V_OR3_B32_vi:
    case AMDGPU::V_PERMLANE_BCAST_B32_e64_gfx12:
    case AMDGPU::V_PERMLANE_DOWN_B32_e64_gfx12:
    case AMDGPU::V_PERMLANE_UP_B32_e64_gfx12:
    case AMDGPU::V_PERMLANE_XOR_B32_e64_gfx12:
    case AMDGPU::V_PERM_B32_e64_gfx11:
    case AMDGPU::V_PERM_B32_e64_gfx12:
    case AMDGPU::V_PERM_B32_gfx10:
    case AMDGPU::V_PERM_B32_vi:
    case AMDGPU::V_PERM_PK16_B4_U4_e64_gfx1250:
    case AMDGPU::V_PERM_PK16_B6_U4_e64_gfx1250:
    case AMDGPU::V_PERM_PK16_B8_U4_e64_gfx1250:
    case AMDGPU::V_XAD_U32_e64_gfx11:
    case AMDGPU::V_XAD_U32_e64_gfx12:
    case AMDGPU::V_XAD_U32_gfx10:
    case AMDGPU::V_XAD_U32_vi:
    case AMDGPU::V_XOR3_B32_e64_gfx11:
    case AMDGPU::V_XOR3_B32_e64_gfx12:
    case AMDGPU::V_XOR3_B32_gfx10: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1
        return 41;
      case 3:
        // op: src2
        return 50;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_MAD_I32_I24_gfx6_gfx7:
    case AMDGPU::V_MAD_U32_U24_gfx6_gfx7:
    case AMDGPU::V_MQSAD_PK_U16_U8_gfx6_gfx7:
    case AMDGPU::V_MQSAD_U32_U8_gfx7:
    case AMDGPU::V_MSAD_U8_gfx6_gfx7:
    case AMDGPU::V_QSAD_PK_U16_U8_gfx7:
    case AMDGPU::V_SAD_HI_U8_gfx6_gfx7:
    case AMDGPU::V_SAD_U16_gfx6_gfx7:
    case AMDGPU::V_SAD_U32_gfx6_gfx7:
    case AMDGPU::V_SAD_U8_gfx6_gfx7: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1
        return 41;
      case 3:
        // op: src2
        return 50;
      case 4:
        // op: clamp
        return 11;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_ADD_MAX_I32_e64_gfx1250:
    case AMDGPU::V_ADD_MAX_U32_e64_gfx1250:
    case AMDGPU::V_ADD_MIN_I32_e64_gfx1250:
    case AMDGPU::V_ADD_MIN_U32_e64_gfx1250:
    case AMDGPU::V_MAD_I16_vi:
    case AMDGPU::V_MAD_I32_I24_e64_gfx11:
    case AMDGPU::V_MAD_I32_I24_e64_gfx12:
    case AMDGPU::V_MAD_I32_I24_gfx10:
    case AMDGPU::V_MAD_I32_I24_vi:
    case AMDGPU::V_MAD_LEGACY_I16_gfx9:
    case AMDGPU::V_MAD_LEGACY_U16_gfx9:
    case AMDGPU::V_MAD_NC_I64_I32_e64_gfx1250:
    case AMDGPU::V_MAD_NC_U64_U32_e64_gfx1250:
    case AMDGPU::V_MAD_U16_vi:
    case AMDGPU::V_MAD_U32_U24_e64_gfx11:
    case AMDGPU::V_MAD_U32_U24_e64_gfx12:
    case AMDGPU::V_MAD_U32_U24_gfx10:
    case AMDGPU::V_MAD_U32_U24_vi:
    case AMDGPU::V_MQSAD_PK_U16_U8_e64_gfx11:
    case AMDGPU::V_MQSAD_PK_U16_U8_e64_gfx12:
    case AMDGPU::V_MQSAD_PK_U16_U8_gfx10:
    case AMDGPU::V_MQSAD_PK_U16_U8_vi:
    case AMDGPU::V_MQSAD_U32_U8_e64_gfx11:
    case AMDGPU::V_MQSAD_U32_U8_e64_gfx12:
    case AMDGPU::V_MQSAD_U32_U8_gfx10:
    case AMDGPU::V_MQSAD_U32_U8_vi:
    case AMDGPU::V_MSAD_U8_e64_gfx11:
    case AMDGPU::V_MSAD_U8_e64_gfx12:
    case AMDGPU::V_MSAD_U8_gfx10:
    case AMDGPU::V_MSAD_U8_vi:
    case AMDGPU::V_QSAD_PK_U16_U8_e64_gfx11:
    case AMDGPU::V_QSAD_PK_U16_U8_e64_gfx12:
    case AMDGPU::V_QSAD_PK_U16_U8_gfx10:
    case AMDGPU::V_QSAD_PK_U16_U8_vi:
    case AMDGPU::V_SAD_HI_U8_e64_gfx11:
    case AMDGPU::V_SAD_HI_U8_e64_gfx12:
    case AMDGPU::V_SAD_HI_U8_gfx10:
    case AMDGPU::V_SAD_HI_U8_vi:
    case AMDGPU::V_SAD_U16_e64_gfx11:
    case AMDGPU::V_SAD_U16_e64_gfx12:
    case AMDGPU::V_SAD_U16_gfx10:
    case AMDGPU::V_SAD_U16_vi:
    case AMDGPU::V_SAD_U32_e64_gfx11:
    case AMDGPU::V_SAD_U32_e64_gfx12:
    case AMDGPU::V_SAD_U32_gfx10:
    case AMDGPU::V_SAD_U32_vi:
    case AMDGPU::V_SAD_U8_e64_gfx11:
    case AMDGPU::V_SAD_U8_e64_gfx12:
    case AMDGPU::V_SAD_U8_gfx10:
    case AMDGPU::V_SAD_U8_vi: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1
        return 41;
      case 3:
        // op: src2
        return 50;
      case 4:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CMPX_EQ_I16_sdwa_gfx10:
    case AMDGPU::V_CMPX_EQ_I32_sdwa_gfx10:
    case AMDGPU::V_CMPX_EQ_U16_sdwa_gfx10:
    case AMDGPU::V_CMPX_EQ_U32_sdwa_gfx10:
    case AMDGPU::V_CMPX_F_I32_sdwa_gfx10:
    case AMDGPU::V_CMPX_F_U32_sdwa_gfx10:
    case AMDGPU::V_CMPX_GE_I16_sdwa_gfx10:
    case AMDGPU::V_CMPX_GE_I32_sdwa_gfx10:
    case AMDGPU::V_CMPX_GE_U16_sdwa_gfx10:
    case AMDGPU::V_CMPX_GE_U32_sdwa_gfx10:
    case AMDGPU::V_CMPX_GT_I16_sdwa_gfx10:
    case AMDGPU::V_CMPX_GT_I32_sdwa_gfx10:
    case AMDGPU::V_CMPX_GT_U16_sdwa_gfx10:
    case AMDGPU::V_CMPX_GT_U32_sdwa_gfx10:
    case AMDGPU::V_CMPX_LE_I16_sdwa_gfx10:
    case AMDGPU::V_CMPX_LE_I32_sdwa_gfx10:
    case AMDGPU::V_CMPX_LE_U16_sdwa_gfx10:
    case AMDGPU::V_CMPX_LE_U32_sdwa_gfx10:
    case AMDGPU::V_CMPX_LT_I16_sdwa_gfx10:
    case AMDGPU::V_CMPX_LT_I32_sdwa_gfx10:
    case AMDGPU::V_CMPX_LT_U16_sdwa_gfx10:
    case AMDGPU::V_CMPX_LT_U32_sdwa_gfx10:
    case AMDGPU::V_CMPX_NE_I16_sdwa_gfx10:
    case AMDGPU::V_CMPX_NE_I32_sdwa_gfx10:
    case AMDGPU::V_CMPX_NE_U16_sdwa_gfx10:
    case AMDGPU::V_CMPX_NE_U32_sdwa_gfx10:
    case AMDGPU::V_CMPX_T_I32_sdwa_gfx10:
    case AMDGPU::V_CMPX_T_U32_sdwa_gfx10: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 32;
      case 4:
        // op: src0_sel
        return 48;
      case 0:
        // op: src0_modifiers
        return 51;
      case 5:
        // op: src1_sel
        return 56;
      case 2:
        // op: src1_modifiers
        return 59;
      case 3:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_CLASS_F32_sdwa_gfx10: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 32;
      case 4:
        // op: src0_sel
        return 48;
      case 0:
        // op: src0_modifiers
        return 52;
      case 5:
        // op: src1_sel
        return 56;
      case 2:
        // op: src1_modifiers
        return 59;
      case 3:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_CMPX_EQ_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_EQ_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_F_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_F_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_GE_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_GE_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_GT_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_GT_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_LE_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_LE_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_LG_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_LG_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_LT_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_LT_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_NEQ_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_NEQ_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_NGE_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_NGE_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_NGT_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_NGT_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_NLE_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_NLE_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_NLG_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_NLG_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_NLT_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_NLT_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_O_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_O_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_TRU_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_TRU_F32_sdwa_gfx10:
    case AMDGPU::V_CMPX_U_F16_sdwa_gfx10:
    case AMDGPU::V_CMPX_U_F32_sdwa_gfx10: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 32;
      case 4:
        // op: src0_sel
        return 48;
      case 0:
        // op: src0_modifiers
        return 52;
      case 5:
        // op: src1_sel
        return 56;
      case 2:
        // op: src1_modifiers
        return 60;
      case 3:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_INTERP_MOV_F32_e64_gfx10: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 41;
      case 4:
        // op: clamp
        return 15;
      case 5:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 2:
        // op: attr
        return 32;
      case 3:
        // op: attrchan
        return 38;
      }
      break;
    }
    case AMDGPU::V_INTERP_MOV_F32_e64_vi: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 41;
      case 4:
        // op: clamp
        return 15;
      case 5:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: attrchan
        return 38;
      case 2:
        // op: attr
        return 32;
      }
      break;
    }
    case AMDGPU::V_PERMLANE16_VAR_B32_e64_gfx12:
    case AMDGPU::V_PERMLANEX16_VAR_B32_e64_gfx12: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 11;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 12;
      case 4:
        // op: src1
        return 41;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_ADD_I16_vi:
    case AMDGPU::V_ADD_NC_I16_gfx10:
    case AMDGPU::V_ADD_NC_U16_gfx10:
    case AMDGPU::V_ASHRREV_I16_gfx10:
    case AMDGPU::V_LSHLREV_B16_gfx10:
    case AMDGPU::V_LSHRREV_B16_gfx10:
    case AMDGPU::V_MAX_I16_gfx10:
    case AMDGPU::V_MAX_U16_gfx10:
    case AMDGPU::V_MIN_I16_gfx10:
    case AMDGPU::V_MIN_U16_gfx10:
    case AMDGPU::V_MUL_LO_U16_gfx10:
    case AMDGPU::V_SUB_I16_vi:
    case AMDGPU::V_SUB_NC_I16_gfx10:
    case AMDGPU::V_SUB_NC_U16_gfx10: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 11;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 12;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_BITOP3_B16_gfx1250_fake16_e64_gfx1250:
    case AMDGPU::V_BITOP3_B16_gfx1250_t16_e64_gfx1250:
    case AMDGPU::V_BITOP3_B16_gfx9: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 11;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 12;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2_modifiers
        return 13;
      case 6:
        // op: src2
        return 50;
      case 0:
        // op: vdst
        return 0;
      case 7:
        // op: bitop3
        return 8;
      }
      break;
    }
    case AMDGPU::V_PERMLANE16_B32_e64_gfx11:
    case AMDGPU::V_PERMLANE16_B32_e64_gfx12:
    case AMDGPU::V_PERMLANE16_B32_gfx10:
    case AMDGPU::V_PERMLANEX16_B32_e64_gfx11:
    case AMDGPU::V_PERMLANEX16_B32_e64_gfx12:
    case AMDGPU::V_PERMLANEX16_B32_gfx10: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 11;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 12;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2_modifiers
        return 13;
      case 6:
        // op: src2
        return 50;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_ALIGNBIT_B32_opsel_gfx10:
    case AMDGPU::V_ALIGNBIT_B32_opsel_gfx9:
    case AMDGPU::V_ALIGNBYTE_B32_opsel_gfx10:
    case AMDGPU::V_ALIGNBYTE_B32_opsel_gfx9:
    case AMDGPU::V_MAD_I16_gfx10:
    case AMDGPU::V_MAD_I16_gfx9_gfx9:
    case AMDGPU::V_MAD_I32_I16_gfx10:
    case AMDGPU::V_MAD_I32_I16_vi:
    case AMDGPU::V_MAD_U16_gfx10:
    case AMDGPU::V_MAD_U16_gfx9_gfx9:
    case AMDGPU::V_MAD_U32_U16_gfx10:
    case AMDGPU::V_MAD_U32_U16_vi:
    case AMDGPU::V_MAX3_I16_gfx10:
    case AMDGPU::V_MAX3_I16_vi:
    case AMDGPU::V_MAX3_U16_gfx10:
    case AMDGPU::V_MAX3_U16_vi:
    case AMDGPU::V_MED3_I16_gfx10:
    case AMDGPU::V_MED3_I16_vi:
    case AMDGPU::V_MED3_U16_gfx10:
    case AMDGPU::V_MED3_U16_vi:
    case AMDGPU::V_MIN3_I16_gfx10:
    case AMDGPU::V_MIN3_I16_vi:
    case AMDGPU::V_MIN3_U16_gfx10:
    case AMDGPU::V_MIN3_U16_vi: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 11;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 12;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2_modifiers
        return 13;
      case 6:
        // op: src2
        return 50;
      case 7:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_DOT2C_F32_BF16_dpp_vi:
    case AMDGPU::V_DOT2C_F32_F16_dpp_vi:
    case AMDGPU::V_DOT2C_I32_I16_dpp_vi:
    case AMDGPU::V_DOT4C_I32_I8_dpp_vi:
    case AMDGPU::V_DOT8C_I32_I4_dpp_vi:
    case AMDGPU::V_FMAC_F32_dpp_vi:
    case AMDGPU::V_FMAC_F64_dpp_gfx90a:
    case AMDGPU::V_MAC_F16_dpp_vi:
    case AMDGPU::V_MAC_F32_dpp_vi: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 52;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 54;
      case 6:
        // op: dpp_ctrl
        return 40;
      case 9:
        // op: bound_ctrl
        return 51;
      case 8:
        // op: bank_mask
        return 56;
      case 7:
        // op: row_mask
        return 60;
      case 0:
        // op: vdst
        return 17;
      case 4:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_DOT2ACC_F32_F16_dpp_gfx11:
    case AMDGPU::V_DOT2C_F32_F16_dpp_gfx10:
    case AMDGPU::V_DOT4C_I32_I8_dpp_gfx10:
    case AMDGPU::V_DOT8C_I32_I4_dpp_gfx10:
    case AMDGPU::V_FMAC_F16_dpp_gfx10:
    case AMDGPU::V_FMAC_F16_fake16_dpp_gfx11:
    case AMDGPU::V_FMAC_F16_fake16_dpp_gfx12:
    case AMDGPU::V_FMAC_F16_t16_dpp_gfx11:
    case AMDGPU::V_FMAC_F16_t16_dpp_gfx12:
    case AMDGPU::V_FMAC_F32_dpp_gfx10:
    case AMDGPU::V_FMAC_F32_dpp_gfx11:
    case AMDGPU::V_FMAC_F32_dpp_gfx12:
    case AMDGPU::V_FMAC_F64_dpp_gfx12:
    case AMDGPU::V_MAC_F32_dpp_gfx10: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 52;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 54;
      case 6:
        // op: dpp_ctrl
        return 40;
      case 9:
        // op: bound_ctrl
        return 51;
      case 8:
        // op: bank_mask
        return 56;
      case 7:
        // op: row_mask
        return 60;
      case 10:
        // op: fi
        return 50;
      case 0:
        // op: vdst
        return 17;
      case 4:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_fake16_e64_gfx1250:
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_t16_e64_gfx1250:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_fake16_e64_gfx1250:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_t16_e64_gfx1250: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: byte_sel
        return 11;
      }
      break;
    }
    case AMDGPU::V_COS_BF16V_COS_BF16_fake16_e64_gfx1250:
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_fake16_e64_gfx1250:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_fake16_e64_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_fake16_e64_gfx1250:
    case AMDGPU::V_CVT_PK_F32_BF8_fake16_e64_gfx12:
    case AMDGPU::V_CVT_PK_F32_FP8_fake16_e64_gfx12:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_fake16_e64_gfx1250:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_fake16_e64_gfx1250:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_fake16_e64_gfx1250:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_fake16_e64_gfx1250:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_fake16_e64_gfx1250:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_fake16_e64_gfx1250:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_fake16_e64_gfx1250: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CVT_FLR_I32_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_RPI_I32_F32_e64_gfx6_gfx7:
    case AMDGPU::V_FREXP_EXP_I32_F32_e64_gfx6_gfx7: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: clamp
        return 11;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CEIL_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CEIL_F64_e64_gfx7:
    case AMDGPU::V_COS_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F16_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_F16_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F32_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_F64_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_I32_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_I32_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_U32_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_U32_F64_e64_gfx6_gfx7:
    case AMDGPU::V_EXP_F32_e64_gfx6_gfx7:
    case AMDGPU::V_EXP_LEGACY_F32_e64_gfx7:
    case AMDGPU::V_FLOOR_F32_e64_gfx6_gfx7:
    case AMDGPU::V_FLOOR_F64_e64_gfx7:
    case AMDGPU::V_FRACT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_FRACT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_FREXP_EXP_I32_F64_e64_gfx6_gfx7:
    case AMDGPU::V_FREXP_MANT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_FREXP_MANT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_LOG_CLAMP_F32_e64_gfx6_gfx7:
    case AMDGPU::V_LOG_F32_e64_gfx6_gfx7:
    case AMDGPU::V_LOG_LEGACY_F32_e64_gfx7:
    case AMDGPU::V_RCP_CLAMP_F32_e64_gfx6_gfx7:
    case AMDGPU::V_RCP_CLAMP_F64_e64_gfx6_gfx7:
    case AMDGPU::V_RCP_F32_e64_gfx6_gfx7:
    case AMDGPU::V_RCP_F64_e64_gfx6_gfx7:
    case AMDGPU::V_RCP_IFLAG_F32_e64_gfx6_gfx7:
    case AMDGPU::V_RCP_LEGACY_F32_e64_gfx6_gfx7:
    case AMDGPU::V_RNDNE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_RNDNE_F64_e64_gfx7:
    case AMDGPU::V_RSQ_CLAMP_F32_e64_gfx6_gfx7:
    case AMDGPU::V_RSQ_CLAMP_F64_e64_gfx6_gfx7:
    case AMDGPU::V_RSQ_F32_e64_gfx6_gfx7:
    case AMDGPU::V_RSQ_F64_e64_gfx6_gfx7:
    case AMDGPU::V_RSQ_LEGACY_F32_e64_gfx6_gfx7:
    case AMDGPU::V_SIN_F32_e64_gfx6_gfx7:
    case AMDGPU::V_SQRT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_SQRT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_TRUNC_F32_e64_gfx6_gfx7:
    case AMDGPU::V_TRUNC_F64_e64_gfx7: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: clamp
        return 11;
      case 4:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CVT_FLOOR_I32_F32_e64_gfx11:
    case AMDGPU::V_CVT_FLOOR_I32_F32_e64_gfx12:
    case AMDGPU::V_CVT_FLR_I32_F32_e64_gfx10:
    case AMDGPU::V_CVT_FLR_I32_F32_e64_vi:
    case AMDGPU::V_CVT_NEAREST_I32_F32_e64_gfx11:
    case AMDGPU::V_CVT_NEAREST_I32_F32_e64_gfx12:
    case AMDGPU::V_CVT_PK_BF8_F16_gfx1250_fake16_e64_gfx1250:
    case AMDGPU::V_CVT_PK_FP8_F16_gfx1250_fake16_e64_gfx1250:
    case AMDGPU::V_CVT_RPI_I32_F32_e64_gfx10:
    case AMDGPU::V_CVT_RPI_I32_F32_e64_vi:
    case AMDGPU::V_FREXP_EXP_I32_F32_e64_gfx10:
    case AMDGPU::V_FREXP_EXP_I32_F32_e64_gfx11:
    case AMDGPU::V_FREXP_EXP_I32_F32_e64_gfx12:
    case AMDGPU::V_FREXP_EXP_I32_F32_e64_vi: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CEIL_F16_e64_gfx10:
    case AMDGPU::V_CEIL_F16_e64_vi:
    case AMDGPU::V_CEIL_F16_fake16_e64_gfx11:
    case AMDGPU::V_CEIL_F16_fake16_e64_gfx12:
    case AMDGPU::V_CEIL_F32_e64_gfx10:
    case AMDGPU::V_CEIL_F32_e64_gfx11:
    case AMDGPU::V_CEIL_F32_e64_gfx12:
    case AMDGPU::V_CEIL_F32_e64_vi:
    case AMDGPU::V_CEIL_F64_e64_gfx10:
    case AMDGPU::V_CEIL_F64_e64_gfx11:
    case AMDGPU::V_CEIL_F64_e64_gfx12:
    case AMDGPU::V_CEIL_F64_e64_vi:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_e64_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_e64_gfx12:
    case AMDGPU::V_COS_F16_e64_gfx10:
    case AMDGPU::V_COS_F16_e64_vi:
    case AMDGPU::V_COS_F32_e64_gfx10:
    case AMDGPU::V_COS_F32_e64_gfx11:
    case AMDGPU::V_COS_F32_e64_gfx12:
    case AMDGPU::V_COS_F32_e64_vi:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_e64_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_e64_gfx12:
    case AMDGPU::V_CVT_F16_F32_e64_gfx10:
    case AMDGPU::V_CVT_F16_F32_e64_vi:
    case AMDGPU::V_CVT_F32_BF16_e64_vi:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_F32_F16_e64_gfx10:
    case AMDGPU::V_CVT_F32_F16_e64_vi:
    case AMDGPU::V_CVT_F32_F64_e64_gfx10:
    case AMDGPU::V_CVT_F32_F64_e64_gfx11:
    case AMDGPU::V_CVT_F32_F64_e64_gfx12:
    case AMDGPU::V_CVT_F32_F64_e64_vi:
    case AMDGPU::V_CVT_F64_F32_e64_gfx10:
    case AMDGPU::V_CVT_F64_F32_e64_gfx11:
    case AMDGPU::V_CVT_F64_F32_e64_gfx12:
    case AMDGPU::V_CVT_F64_F32_e64_vi:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_I16_F16_e64_gfx10:
    case AMDGPU::V_CVT_I16_F16_e64_vi:
    case AMDGPU::V_CVT_I32_F32_e64_gfx10:
    case AMDGPU::V_CVT_I32_F32_e64_gfx11:
    case AMDGPU::V_CVT_I32_F32_e64_gfx12:
    case AMDGPU::V_CVT_I32_F32_e64_vi:
    case AMDGPU::V_CVT_I32_F64_e64_gfx10:
    case AMDGPU::V_CVT_I32_F64_e64_gfx11:
    case AMDGPU::V_CVT_I32_F64_e64_gfx12:
    case AMDGPU::V_CVT_I32_F64_e64_vi:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16_e64_gfx10:
    case AMDGPU::V_CVT_NORM_I16_F16_e64_vi:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16_e64_gfx10:
    case AMDGPU::V_CVT_NORM_U16_F16_e64_vi:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_U16_F16_e64_gfx10:
    case AMDGPU::V_CVT_U16_F16_e64_vi:
    case AMDGPU::V_CVT_U32_F32_e64_gfx10:
    case AMDGPU::V_CVT_U32_F32_e64_gfx11:
    case AMDGPU::V_CVT_U32_F32_e64_gfx12:
    case AMDGPU::V_CVT_U32_F32_e64_vi:
    case AMDGPU::V_CVT_U32_F64_e64_gfx10:
    case AMDGPU::V_CVT_U32_F64_e64_gfx11:
    case AMDGPU::V_CVT_U32_F64_e64_gfx12:
    case AMDGPU::V_CVT_U32_F64_e64_vi:
    case AMDGPU::V_EXP_F16_e64_gfx10:
    case AMDGPU::V_EXP_F16_e64_vi:
    case AMDGPU::V_EXP_F16_fake16_e64_gfx11:
    case AMDGPU::V_EXP_F16_fake16_e64_gfx12:
    case AMDGPU::V_EXP_F32_e64_gfx10:
    case AMDGPU::V_EXP_F32_e64_gfx11:
    case AMDGPU::V_EXP_F32_e64_gfx12:
    case AMDGPU::V_EXP_F32_e64_vi:
    case AMDGPU::V_EXP_LEGACY_F32_e64_vi:
    case AMDGPU::V_FLOOR_F16_e64_gfx10:
    case AMDGPU::V_FLOOR_F16_e64_vi:
    case AMDGPU::V_FLOOR_F16_fake16_e64_gfx11:
    case AMDGPU::V_FLOOR_F16_fake16_e64_gfx12:
    case AMDGPU::V_FLOOR_F32_e64_gfx10:
    case AMDGPU::V_FLOOR_F32_e64_gfx11:
    case AMDGPU::V_FLOOR_F32_e64_gfx12:
    case AMDGPU::V_FLOOR_F32_e64_vi:
    case AMDGPU::V_FLOOR_F64_e64_gfx10:
    case AMDGPU::V_FLOOR_F64_e64_gfx11:
    case AMDGPU::V_FLOOR_F64_e64_gfx12:
    case AMDGPU::V_FLOOR_F64_e64_vi:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_e64_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_e64_gfx12:
    case AMDGPU::V_FRACT_F16_e64_gfx10:
    case AMDGPU::V_FRACT_F16_e64_vi:
    case AMDGPU::V_FRACT_F32_e64_gfx10:
    case AMDGPU::V_FRACT_F32_e64_gfx11:
    case AMDGPU::V_FRACT_F32_e64_gfx12:
    case AMDGPU::V_FRACT_F32_e64_vi:
    case AMDGPU::V_FRACT_F64_e64_gfx10:
    case AMDGPU::V_FRACT_F64_e64_gfx11:
    case AMDGPU::V_FRACT_F64_e64_gfx12:
    case AMDGPU::V_FRACT_F64_e64_vi:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e64_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e64_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16_e64_gfx10:
    case AMDGPU::V_FREXP_EXP_I16_F16_e64_vi:
    case AMDGPU::V_FREXP_EXP_I32_F64_e64_gfx10:
    case AMDGPU::V_FREXP_EXP_I32_F64_e64_gfx11:
    case AMDGPU::V_FREXP_EXP_I32_F64_e64_gfx12:
    case AMDGPU::V_FREXP_EXP_I32_F64_e64_vi:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e64_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e64_gfx12:
    case AMDGPU::V_FREXP_MANT_F16_e64_gfx10:
    case AMDGPU::V_FREXP_MANT_F16_e64_vi:
    case AMDGPU::V_FREXP_MANT_F32_e64_gfx10:
    case AMDGPU::V_FREXP_MANT_F32_e64_gfx11:
    case AMDGPU::V_FREXP_MANT_F32_e64_gfx12:
    case AMDGPU::V_FREXP_MANT_F32_e64_vi:
    case AMDGPU::V_FREXP_MANT_F64_e64_gfx10:
    case AMDGPU::V_FREXP_MANT_F64_e64_gfx11:
    case AMDGPU::V_FREXP_MANT_F64_e64_gfx12:
    case AMDGPU::V_FREXP_MANT_F64_e64_vi:
    case AMDGPU::V_LOG_F16_e64_gfx10:
    case AMDGPU::V_LOG_F16_e64_vi:
    case AMDGPU::V_LOG_F16_fake16_e64_gfx11:
    case AMDGPU::V_LOG_F16_fake16_e64_gfx12:
    case AMDGPU::V_LOG_F32_e64_gfx10:
    case AMDGPU::V_LOG_F32_e64_gfx11:
    case AMDGPU::V_LOG_F32_e64_gfx12:
    case AMDGPU::V_LOG_F32_e64_vi:
    case AMDGPU::V_LOG_LEGACY_F32_e64_vi:
    case AMDGPU::V_RCP_F16_e64_gfx10:
    case AMDGPU::V_RCP_F16_e64_vi:
    case AMDGPU::V_RCP_F16_fake16_e64_gfx11:
    case AMDGPU::V_RCP_F16_fake16_e64_gfx12:
    case AMDGPU::V_RCP_F32_e64_gfx10:
    case AMDGPU::V_RCP_F32_e64_gfx11:
    case AMDGPU::V_RCP_F32_e64_gfx12:
    case AMDGPU::V_RCP_F32_e64_vi:
    case AMDGPU::V_RCP_F64_e64_gfx10:
    case AMDGPU::V_RCP_F64_e64_gfx11:
    case AMDGPU::V_RCP_F64_e64_gfx12:
    case AMDGPU::V_RCP_F64_e64_vi:
    case AMDGPU::V_RCP_IFLAG_F32_e64_gfx10:
    case AMDGPU::V_RCP_IFLAG_F32_e64_gfx11:
    case AMDGPU::V_RCP_IFLAG_F32_e64_gfx12:
    case AMDGPU::V_RCP_IFLAG_F32_e64_vi:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_e64_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_e64_gfx12:
    case AMDGPU::V_RNDNE_F16_e64_gfx10:
    case AMDGPU::V_RNDNE_F16_e64_vi:
    case AMDGPU::V_RNDNE_F32_e64_gfx10:
    case AMDGPU::V_RNDNE_F32_e64_gfx11:
    case AMDGPU::V_RNDNE_F32_e64_gfx12:
    case AMDGPU::V_RNDNE_F32_e64_vi:
    case AMDGPU::V_RNDNE_F64_e64_gfx10:
    case AMDGPU::V_RNDNE_F64_e64_gfx11:
    case AMDGPU::V_RNDNE_F64_e64_gfx12:
    case AMDGPU::V_RNDNE_F64_e64_vi:
    case AMDGPU::V_RSQ_F16_e64_gfx10:
    case AMDGPU::V_RSQ_F16_e64_vi:
    case AMDGPU::V_RSQ_F16_fake16_e64_gfx11:
    case AMDGPU::V_RSQ_F16_fake16_e64_gfx12:
    case AMDGPU::V_RSQ_F32_e64_gfx10:
    case AMDGPU::V_RSQ_F32_e64_gfx11:
    case AMDGPU::V_RSQ_F32_e64_gfx12:
    case AMDGPU::V_RSQ_F32_e64_vi:
    case AMDGPU::V_RSQ_F64_e64_gfx10:
    case AMDGPU::V_RSQ_F64_e64_gfx11:
    case AMDGPU::V_RSQ_F64_e64_gfx12:
    case AMDGPU::V_RSQ_F64_e64_vi:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_e64_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_e64_gfx12:
    case AMDGPU::V_SIN_F16_e64_gfx10:
    case AMDGPU::V_SIN_F16_e64_vi:
    case AMDGPU::V_SIN_F32_e64_gfx10:
    case AMDGPU::V_SIN_F32_e64_gfx11:
    case AMDGPU::V_SIN_F32_e64_gfx12:
    case AMDGPU::V_SIN_F32_e64_vi:
    case AMDGPU::V_SQRT_F16_e64_gfx10:
    case AMDGPU::V_SQRT_F16_e64_vi:
    case AMDGPU::V_SQRT_F16_fake16_e64_gfx11:
    case AMDGPU::V_SQRT_F16_fake16_e64_gfx12:
    case AMDGPU::V_SQRT_F32_e64_gfx10:
    case AMDGPU::V_SQRT_F32_e64_gfx11:
    case AMDGPU::V_SQRT_F32_e64_gfx12:
    case AMDGPU::V_SQRT_F32_e64_vi:
    case AMDGPU::V_SQRT_F64_e64_gfx10:
    case AMDGPU::V_SQRT_F64_e64_gfx11:
    case AMDGPU::V_SQRT_F64_e64_gfx12:
    case AMDGPU::V_SQRT_F64_e64_vi:
    case AMDGPU::V_S_EXP_F16_e64_gfx12:
    case AMDGPU::V_S_EXP_F32_e64_gfx12:
    case AMDGPU::V_S_LOG_F16_e64_gfx12:
    case AMDGPU::V_S_LOG_F32_e64_gfx12:
    case AMDGPU::V_S_RCP_F16_e64_gfx12:
    case AMDGPU::V_S_RCP_F32_e64_gfx12:
    case AMDGPU::V_S_RSQ_F16_e64_gfx12:
    case AMDGPU::V_S_RSQ_F32_e64_gfx12:
    case AMDGPU::V_S_SQRT_F16_e64_gfx12:
    case AMDGPU::V_S_SQRT_F32_e64_gfx12:
    case AMDGPU::V_TANH_F16V_TANH_F16_fake16_e64_gfx1250:
    case AMDGPU::V_TANH_F32_e64_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_e64_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_e64_gfx12:
    case AMDGPU::V_TRUNC_F16_e64_gfx10:
    case AMDGPU::V_TRUNC_F16_e64_vi:
    case AMDGPU::V_TRUNC_F32_e64_gfx10:
    case AMDGPU::V_TRUNC_F32_e64_gfx11:
    case AMDGPU::V_TRUNC_F32_e64_gfx12:
    case AMDGPU::V_TRUNC_F32_e64_vi:
    case AMDGPU::V_TRUNC_F64_e64_gfx10:
    case AMDGPU::V_TRUNC_F64_e64_gfx11:
    case AMDGPU::V_TRUNC_F64_e64_gfx12:
    case AMDGPU::V_TRUNC_F64_e64_vi: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: clamp
        return 15;
      case 4:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_e64_vi:
    case AMDGPU::V_CMPX_CLASS_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_CLASS_F32_e64_vi:
    case AMDGPU::V_CMPX_CLASS_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_CLASS_F64_e64_vi:
    case AMDGPU::V_CMP_CLASS_F16_e64_gfx10:
    case AMDGPU::V_CMP_CLASS_F16_e64_vi:
    case AMDGPU::V_CMP_CLASS_F32_e64_gfx10:
    case AMDGPU::V_CMP_CLASS_F32_e64_gfx11:
    case AMDGPU::V_CMP_CLASS_F32_e64_gfx12:
    case AMDGPU::V_CMP_CLASS_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_CLASS_F32_e64_vi:
    case AMDGPU::V_CMP_CLASS_F64_e64_gfx10:
    case AMDGPU::V_CMP_CLASS_F64_e64_gfx11:
    case AMDGPU::V_CMP_CLASS_F64_e64_gfx12:
    case AMDGPU::V_CMP_CLASS_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_CLASS_F64_e64_vi: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1
        return 41;
      case 0:
        // op: sdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CMP_CLASS_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_EQ_I16_t16_e64_gfx11:
    case AMDGPU::V_CMP_EQ_I16_t16_e64_gfx12:
    case AMDGPU::V_CMP_EQ_U16_t16_e64_gfx11:
    case AMDGPU::V_CMP_EQ_U16_t16_e64_gfx12:
    case AMDGPU::V_CMP_GE_I16_t16_e64_gfx11:
    case AMDGPU::V_CMP_GE_I16_t16_e64_gfx12:
    case AMDGPU::V_CMP_GE_U16_t16_e64_gfx11:
    case AMDGPU::V_CMP_GE_U16_t16_e64_gfx12:
    case AMDGPU::V_CMP_GT_I16_t16_e64_gfx11:
    case AMDGPU::V_CMP_GT_I16_t16_e64_gfx12:
    case AMDGPU::V_CMP_GT_U16_t16_e64_gfx11:
    case AMDGPU::V_CMP_GT_U16_t16_e64_gfx12:
    case AMDGPU::V_CMP_LE_I16_t16_e64_gfx11:
    case AMDGPU::V_CMP_LE_I16_t16_e64_gfx12:
    case AMDGPU::V_CMP_LE_U16_t16_e64_gfx11:
    case AMDGPU::V_CMP_LE_U16_t16_e64_gfx12:
    case AMDGPU::V_CMP_LT_I16_t16_e64_gfx11:
    case AMDGPU::V_CMP_LT_I16_t16_e64_gfx12:
    case AMDGPU::V_CMP_LT_U16_t16_e64_gfx11:
    case AMDGPU::V_CMP_LT_U16_t16_e64_gfx12:
    case AMDGPU::V_CMP_NE_I16_t16_e64_gfx11:
    case AMDGPU::V_CMP_NE_I16_t16_e64_gfx12:
    case AMDGPU::V_CMP_NE_U16_t16_e64_gfx11:
    case AMDGPU::V_CMP_NE_U16_t16_e64_gfx12: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 0:
        // op: sdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CVT_SR_BF8_F16_fake16_e64_gfx1250:
    case AMDGPU::V_CVT_SR_BF8_F16_t16_e64_gfx1250:
    case AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_gfx11:
    case AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_gfx12:
    case AMDGPU::V_CVT_SR_FP8_F16_fake16_e64_gfx1250:
    case AMDGPU::V_CVT_SR_FP8_F16_t16_e64_gfx1250:
    case AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_gfx11:
    case AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_gfx12: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 0:
        // op: vdst
        return 0;
      case 6:
        // op: byte_sel
        return 13;
      }
      break;
    }
    case AMDGPU::V_CVT_PK_BF8_F32_fake16_e64_gfx11:
    case AMDGPU::V_CVT_PK_BF8_F32_fake16_e64_gfx12:
    case AMDGPU::V_CVT_PK_BF8_F32_vi:
    case AMDGPU::V_CVT_PK_FP8_F32_fake16_e64_gfx11:
    case AMDGPU::V_CVT_PK_FP8_F32_fake16_e64_gfx12:
    case AMDGPU::V_CVT_PK_FP8_F32_vi:
    case AMDGPU::V_CVT_SCALEF32_F16_BF8_vi:
    case AMDGPU::V_CVT_SCALEF32_F16_FP8_vi:
    case AMDGPU::V_CVT_SCALEF32_F32_BF8_vi:
    case AMDGPU::V_CVT_SCALEF32_F32_FP8_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_BF16_BF8_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_BF16_FP4_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_BF16_FP8_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_BF8_BF16_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_BF8_F16_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_F16_BF8_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_F16_FP4_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_F16_FP8_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_F32_BF8_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_F32_FP4_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_F32_FP8_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_FP8_BF16_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_FP8_F16_vi:
    case AMDGPU::V_CVT_SR_BF16_F32_vi:
    case AMDGPU::V_CVT_SR_F16_F32_vi: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CMPSX_EQ_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_EQ_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_F_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_F_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_GE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_GE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_GT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_GT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LG_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LG_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_LT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NEQ_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NEQ_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NGE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NGE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NGT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NGT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLG_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLG_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_NLT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_O_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_O_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_TRU_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_TRU_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_U_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPSX_U_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_EQ_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_EQ_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_F_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_F_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_GE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_GE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_GT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_GT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_LE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_LE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_LG_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_LG_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_LT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_LT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NEQ_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NEQ_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NGE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NGE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NGT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NGT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLG_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLG_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_NLT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_O_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_O_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_TRU_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_TRU_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_U_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPS_U_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_EQ_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_F_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_GT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LG_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LG_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_LT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NEQ_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NEQ_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NGE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NGE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NGT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NGT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLG_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLG_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_NLT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_O_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_O_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_TRU_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_TRU_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_U_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMPX_U_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_EQ_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_F_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_F_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_GT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LG_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LG_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_LT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NEQ_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NEQ_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NGE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NGE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NGT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NGT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NLE_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NLE_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NLG_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NLG_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NLT_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_NLT_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_O_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_O_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_TRU_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_TRU_F64_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_U_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CMP_U_F64_e64_gfx6_gfx7: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: clamp
        return 11;
      case 0:
        // op: sdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CVT_PKACCUM_U8_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_PKNORM_I16_F32_e64_gfx6_gfx7:
    case AMDGPU::V_CVT_PKNORM_U16_F32_e64_gfx6_gfx7: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: clamp
        return 11;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_ADD_F32_e64_gfx6_gfx7:
    case AMDGPU::V_ADD_F64_gfx6_gfx7:
    case AMDGPU::V_CVT_PKRTZ_F16_F32_e64_gfx6_gfx7:
    case AMDGPU::V_LDEXP_F32_e64_gfx6_gfx7:
    case AMDGPU::V_LDEXP_F64_gfx6_gfx7:
    case AMDGPU::V_MAX_F32_e64_gfx6_gfx7:
    case AMDGPU::V_MAX_F64_gfx6_gfx7:
    case AMDGPU::V_MAX_LEGACY_F32_e64_gfx6_gfx7:
    case AMDGPU::V_MIN_F32_e64_gfx6_gfx7:
    case AMDGPU::V_MIN_F64_gfx6_gfx7:
    case AMDGPU::V_MIN_LEGACY_F32_e64_gfx6_gfx7:
    case AMDGPU::V_MUL_F32_e64_gfx6_gfx7:
    case AMDGPU::V_MUL_F64_gfx6_gfx7:
    case AMDGPU::V_MUL_LEGACY_F32_e64_gfx6_gfx7:
    case AMDGPU::V_SUBREV_F32_e64_gfx6_gfx7:
    case AMDGPU::V_SUB_F32_e64_gfx6_gfx7:
    case AMDGPU::V_TRIG_PREOP_F64_gfx6_gfx7: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: clamp
        return 11;
      case 6:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CMPX_EQ_F16_e64_vi:
    case AMDGPU::V_CMPX_EQ_F32_e64_vi:
    case AMDGPU::V_CMPX_EQ_F64_e64_vi:
    case AMDGPU::V_CMPX_F_F16_e64_vi:
    case AMDGPU::V_CMPX_F_F32_e64_vi:
    case AMDGPU::V_CMPX_F_F64_e64_vi:
    case AMDGPU::V_CMPX_GE_F16_e64_vi:
    case AMDGPU::V_CMPX_GE_F32_e64_vi:
    case AMDGPU::V_CMPX_GE_F64_e64_vi:
    case AMDGPU::V_CMPX_GT_F16_e64_vi:
    case AMDGPU::V_CMPX_GT_F32_e64_vi:
    case AMDGPU::V_CMPX_GT_F64_e64_vi:
    case AMDGPU::V_CMPX_LE_F16_e64_vi:
    case AMDGPU::V_CMPX_LE_F32_e64_vi:
    case AMDGPU::V_CMPX_LE_F64_e64_vi:
    case AMDGPU::V_CMPX_LG_F16_e64_vi:
    case AMDGPU::V_CMPX_LG_F32_e64_vi:
    case AMDGPU::V_CMPX_LG_F64_e64_vi:
    case AMDGPU::V_CMPX_LT_F16_e64_vi:
    case AMDGPU::V_CMPX_LT_F32_e64_vi:
    case AMDGPU::V_CMPX_LT_F64_e64_vi:
    case AMDGPU::V_CMPX_NEQ_F16_e64_vi:
    case AMDGPU::V_CMPX_NEQ_F32_e64_vi:
    case AMDGPU::V_CMPX_NEQ_F64_e64_vi:
    case AMDGPU::V_CMPX_NGE_F16_e64_vi:
    case AMDGPU::V_CMPX_NGE_F32_e64_vi:
    case AMDGPU::V_CMPX_NGE_F64_e64_vi:
    case AMDGPU::V_CMPX_NGT_F16_e64_vi:
    case AMDGPU::V_CMPX_NGT_F32_e64_vi:
    case AMDGPU::V_CMPX_NGT_F64_e64_vi:
    case AMDGPU::V_CMPX_NLE_F16_e64_vi:
    case AMDGPU::V_CMPX_NLE_F32_e64_vi:
    case AMDGPU::V_CMPX_NLE_F64_e64_vi:
    case AMDGPU::V_CMPX_NLG_F16_e64_vi:
    case AMDGPU::V_CMPX_NLG_F32_e64_vi:
    case AMDGPU::V_CMPX_NLG_F64_e64_vi:
    case AMDGPU::V_CMPX_NLT_F16_e64_vi:
    case AMDGPU::V_CMPX_NLT_F32_e64_vi:
    case AMDGPU::V_CMPX_NLT_F64_e64_vi:
    case AMDGPU::V_CMPX_O_F16_e64_vi:
    case AMDGPU::V_CMPX_O_F32_e64_vi:
    case AMDGPU::V_CMPX_O_F64_e64_vi:
    case AMDGPU::V_CMPX_TRU_F16_e64_vi:
    case AMDGPU::V_CMPX_TRU_F32_e64_vi:
    case AMDGPU::V_CMPX_TRU_F64_e64_vi:
    case AMDGPU::V_CMPX_U_F16_e64_vi:
    case AMDGPU::V_CMPX_U_F32_e64_vi:
    case AMDGPU::V_CMPX_U_F64_e64_vi:
    case AMDGPU::V_CMP_EQ_F16_e64_gfx10:
    case AMDGPU::V_CMP_EQ_F16_e64_vi:
    case AMDGPU::V_CMP_EQ_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_EQ_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_EQ_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_EQ_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e64_gfx10:
    case AMDGPU::V_CMP_EQ_F32_e64_gfx11:
    case AMDGPU::V_CMP_EQ_F32_e64_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e64_vi:
    case AMDGPU::V_CMP_EQ_F64_e64_gfx10:
    case AMDGPU::V_CMP_EQ_F64_e64_gfx11:
    case AMDGPU::V_CMP_EQ_F64_e64_gfx12:
    case AMDGPU::V_CMP_EQ_F64_e64_vi:
    case AMDGPU::V_CMP_F_F16_e64_gfx10:
    case AMDGPU::V_CMP_F_F16_e64_vi:
    case AMDGPU::V_CMP_F_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_F_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_F_F32_e64_gfx10:
    case AMDGPU::V_CMP_F_F32_e64_gfx11:
    case AMDGPU::V_CMP_F_F32_e64_vi:
    case AMDGPU::V_CMP_F_F64_e64_gfx10:
    case AMDGPU::V_CMP_F_F64_e64_gfx11:
    case AMDGPU::V_CMP_F_F64_e64_vi:
    case AMDGPU::V_CMP_GE_F16_e64_gfx10:
    case AMDGPU::V_CMP_GE_F16_e64_vi:
    case AMDGPU::V_CMP_GE_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_GE_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_GE_F32_e64_gfx10:
    case AMDGPU::V_CMP_GE_F32_e64_gfx11:
    case AMDGPU::V_CMP_GE_F32_e64_gfx12:
    case AMDGPU::V_CMP_GE_F32_e64_vi:
    case AMDGPU::V_CMP_GE_F64_e64_gfx10:
    case AMDGPU::V_CMP_GE_F64_e64_gfx11:
    case AMDGPU::V_CMP_GE_F64_e64_gfx12:
    case AMDGPU::V_CMP_GE_F64_e64_vi:
    case AMDGPU::V_CMP_GT_F16_e64_gfx10:
    case AMDGPU::V_CMP_GT_F16_e64_vi:
    case AMDGPU::V_CMP_GT_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_GT_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_GT_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_GT_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_GT_F32_e64_gfx10:
    case AMDGPU::V_CMP_GT_F32_e64_gfx11:
    case AMDGPU::V_CMP_GT_F32_e64_gfx12:
    case AMDGPU::V_CMP_GT_F32_e64_vi:
    case AMDGPU::V_CMP_GT_F64_e64_gfx10:
    case AMDGPU::V_CMP_GT_F64_e64_gfx11:
    case AMDGPU::V_CMP_GT_F64_e64_gfx12:
    case AMDGPU::V_CMP_GT_F64_e64_vi:
    case AMDGPU::V_CMP_LE_F16_e64_gfx10:
    case AMDGPU::V_CMP_LE_F16_e64_vi:
    case AMDGPU::V_CMP_LE_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_LE_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_LE_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_LE_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_LE_F32_e64_gfx10:
    case AMDGPU::V_CMP_LE_F32_e64_gfx11:
    case AMDGPU::V_CMP_LE_F32_e64_gfx12:
    case AMDGPU::V_CMP_LE_F32_e64_vi:
    case AMDGPU::V_CMP_LE_F64_e64_gfx10:
    case AMDGPU::V_CMP_LE_F64_e64_gfx11:
    case AMDGPU::V_CMP_LE_F64_e64_gfx12:
    case AMDGPU::V_CMP_LE_F64_e64_vi:
    case AMDGPU::V_CMP_LG_F16_e64_gfx10:
    case AMDGPU::V_CMP_LG_F16_e64_vi:
    case AMDGPU::V_CMP_LG_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_LG_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_LG_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_LG_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_LG_F32_e64_gfx10:
    case AMDGPU::V_CMP_LG_F32_e64_gfx11:
    case AMDGPU::V_CMP_LG_F32_e64_gfx12:
    case AMDGPU::V_CMP_LG_F32_e64_vi:
    case AMDGPU::V_CMP_LG_F64_e64_gfx10:
    case AMDGPU::V_CMP_LG_F64_e64_gfx11:
    case AMDGPU::V_CMP_LG_F64_e64_gfx12:
    case AMDGPU::V_CMP_LG_F64_e64_vi:
    case AMDGPU::V_CMP_LT_F16_e64_gfx10:
    case AMDGPU::V_CMP_LT_F16_e64_vi:
    case AMDGPU::V_CMP_LT_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_LT_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_LT_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_LT_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_LT_F32_e64_gfx10:
    case AMDGPU::V_CMP_LT_F32_e64_gfx11:
    case AMDGPU::V_CMP_LT_F32_e64_gfx12:
    case AMDGPU::V_CMP_LT_F32_e64_vi:
    case AMDGPU::V_CMP_LT_F64_e64_gfx10:
    case AMDGPU::V_CMP_LT_F64_e64_gfx11:
    case AMDGPU::V_CMP_LT_F64_e64_gfx12:
    case AMDGPU::V_CMP_LT_F64_e64_vi:
    case AMDGPU::V_CMP_NEQ_F16_e64_gfx10:
    case AMDGPU::V_CMP_NEQ_F16_e64_vi:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e64_gfx10:
    case AMDGPU::V_CMP_NEQ_F32_e64_gfx11:
    case AMDGPU::V_CMP_NEQ_F32_e64_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e64_vi:
    case AMDGPU::V_CMP_NEQ_F64_e64_gfx10:
    case AMDGPU::V_CMP_NEQ_F64_e64_gfx11:
    case AMDGPU::V_CMP_NEQ_F64_e64_gfx12:
    case AMDGPU::V_CMP_NEQ_F64_e64_vi:
    case AMDGPU::V_CMP_NGE_F16_e64_gfx10:
    case AMDGPU::V_CMP_NGE_F16_e64_vi:
    case AMDGPU::V_CMP_NGE_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_NGE_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_NGE_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_NGE_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e64_gfx10:
    case AMDGPU::V_CMP_NGE_F32_e64_gfx11:
    case AMDGPU::V_CMP_NGE_F32_e64_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e64_vi:
    case AMDGPU::V_CMP_NGE_F64_e64_gfx10:
    case AMDGPU::V_CMP_NGE_F64_e64_gfx11:
    case AMDGPU::V_CMP_NGE_F64_e64_gfx12:
    case AMDGPU::V_CMP_NGE_F64_e64_vi:
    case AMDGPU::V_CMP_NGT_F16_e64_gfx10:
    case AMDGPU::V_CMP_NGT_F16_e64_vi:
    case AMDGPU::V_CMP_NGT_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_NGT_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_NGT_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_NGT_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e64_gfx10:
    case AMDGPU::V_CMP_NGT_F32_e64_gfx11:
    case AMDGPU::V_CMP_NGT_F32_e64_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e64_vi:
    case AMDGPU::V_CMP_NGT_F64_e64_gfx10:
    case AMDGPU::V_CMP_NGT_F64_e64_gfx11:
    case AMDGPU::V_CMP_NGT_F64_e64_gfx12:
    case AMDGPU::V_CMP_NGT_F64_e64_vi:
    case AMDGPU::V_CMP_NLE_F16_e64_gfx10:
    case AMDGPU::V_CMP_NLE_F16_e64_vi:
    case AMDGPU::V_CMP_NLE_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_NLE_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_NLE_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_NLE_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e64_gfx10:
    case AMDGPU::V_CMP_NLE_F32_e64_gfx11:
    case AMDGPU::V_CMP_NLE_F32_e64_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e64_vi:
    case AMDGPU::V_CMP_NLE_F64_e64_gfx10:
    case AMDGPU::V_CMP_NLE_F64_e64_gfx11:
    case AMDGPU::V_CMP_NLE_F64_e64_gfx12:
    case AMDGPU::V_CMP_NLE_F64_e64_vi:
    case AMDGPU::V_CMP_NLG_F16_e64_gfx10:
    case AMDGPU::V_CMP_NLG_F16_e64_vi:
    case AMDGPU::V_CMP_NLG_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_NLG_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_NLG_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_NLG_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e64_gfx10:
    case AMDGPU::V_CMP_NLG_F32_e64_gfx11:
    case AMDGPU::V_CMP_NLG_F32_e64_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e64_vi:
    case AMDGPU::V_CMP_NLG_F64_e64_gfx10:
    case AMDGPU::V_CMP_NLG_F64_e64_gfx11:
    case AMDGPU::V_CMP_NLG_F64_e64_gfx12:
    case AMDGPU::V_CMP_NLG_F64_e64_vi:
    case AMDGPU::V_CMP_NLT_F16_e64_gfx10:
    case AMDGPU::V_CMP_NLT_F16_e64_vi:
    case AMDGPU::V_CMP_NLT_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_NLT_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_NLT_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_NLT_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e64_gfx10:
    case AMDGPU::V_CMP_NLT_F32_e64_gfx11:
    case AMDGPU::V_CMP_NLT_F32_e64_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e64_vi:
    case AMDGPU::V_CMP_NLT_F64_e64_gfx10:
    case AMDGPU::V_CMP_NLT_F64_e64_gfx11:
    case AMDGPU::V_CMP_NLT_F64_e64_gfx12:
    case AMDGPU::V_CMP_NLT_F64_e64_vi:
    case AMDGPU::V_CMP_O_F16_e64_gfx10:
    case AMDGPU::V_CMP_O_F16_e64_vi:
    case AMDGPU::V_CMP_O_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_O_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_O_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_O_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_O_F32_e64_gfx10:
    case AMDGPU::V_CMP_O_F32_e64_gfx11:
    case AMDGPU::V_CMP_O_F32_e64_gfx12:
    case AMDGPU::V_CMP_O_F32_e64_vi:
    case AMDGPU::V_CMP_O_F64_e64_gfx10:
    case AMDGPU::V_CMP_O_F64_e64_gfx11:
    case AMDGPU::V_CMP_O_F64_e64_gfx12:
    case AMDGPU::V_CMP_O_F64_e64_vi:
    case AMDGPU::V_CMP_TRU_F16_e64_gfx10:
    case AMDGPU::V_CMP_TRU_F16_e64_vi:
    case AMDGPU::V_CMP_TRU_F32_e64_gfx10:
    case AMDGPU::V_CMP_TRU_F32_e64_vi:
    case AMDGPU::V_CMP_TRU_F64_e64_gfx10:
    case AMDGPU::V_CMP_TRU_F64_e64_vi:
    case AMDGPU::V_CMP_T_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_T_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_T_F32_e64_gfx11:
    case AMDGPU::V_CMP_T_F64_e64_gfx11:
    case AMDGPU::V_CMP_U_F16_e64_gfx10:
    case AMDGPU::V_CMP_U_F16_e64_vi:
    case AMDGPU::V_CMP_U_F16_fake16_e64_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e64_gfx12:
    case AMDGPU::V_CMP_U_F16_t16_e64_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e64_gfx12:
    case AMDGPU::V_CMP_U_F32_e64_gfx10:
    case AMDGPU::V_CMP_U_F32_e64_gfx11:
    case AMDGPU::V_CMP_U_F32_e64_gfx12:
    case AMDGPU::V_CMP_U_F32_e64_vi:
    case AMDGPU::V_CMP_U_F64_e64_gfx10:
    case AMDGPU::V_CMP_U_F64_e64_gfx11:
    case AMDGPU::V_CMP_U_F64_e64_gfx12:
    case AMDGPU::V_CMP_U_F64_e64_vi: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: clamp
        return 15;
      case 0:
        // op: sdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CVT_SR_FP8_F32_gfx1250_e64_gfx1250: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 7:
        // op: byte_sel
        return 13;
      }
      break;
    }
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_fake16_e64_gfx11:
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_fake16_e64_gfx12:
    case AMDGPU::V_ADD_NC_U16_fake16_e64_gfx11:
    case AMDGPU::V_ADD_NC_U16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_PKACCUM_U8_F32_e64_vi:
    case AMDGPU::V_CVT_PKNORM_I16_F16_gfx10:
    case AMDGPU::V_CVT_PKNORM_I16_F16_vi:
    case AMDGPU::V_CVT_PKNORM_I16_F32_e64_gfx10:
    case AMDGPU::V_CVT_PKNORM_I16_F32_e64_vi:
    case AMDGPU::V_CVT_PKNORM_U16_F16_gfx10:
    case AMDGPU::V_CVT_PKNORM_U16_F16_vi:
    case AMDGPU::V_CVT_PKNORM_U16_F32_e64_gfx10:
    case AMDGPU::V_CVT_PKNORM_U16_F32_e64_vi:
    case AMDGPU::V_CVT_PK_FP8_F32_gfx1250_fake16_e64_gfx1250:
    case AMDGPU::V_CVT_PK_I16_F32_e64_gfx11:
    case AMDGPU::V_CVT_PK_I16_F32_e64_gfx12:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_PK_NORM_I16_F32_e64_gfx11:
    case AMDGPU::V_CVT_PK_NORM_I16_F32_e64_gfx12:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_fake16_e64_gfx11:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_fake16_e64_gfx12:
    case AMDGPU::V_CVT_PK_NORM_U16_F32_e64_gfx11:
    case AMDGPU::V_CVT_PK_NORM_U16_F32_e64_gfx12:
    case AMDGPU::V_CVT_PK_U16_F32_e64_gfx11:
    case AMDGPU::V_CVT_PK_U16_F32_e64_gfx12:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_fake16_e64_gfx11:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_fake16_e64_gfx12:
    case AMDGPU::V_PACK_B32_F16_gfx10:
    case AMDGPU::V_PACK_B32_F16_vi:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_fake16_e64_gfx11:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_fake16_e64_gfx12:
    case AMDGPU::V_SUB_NC_U16_fake16_e64_gfx11:
    case AMDGPU::V_SUB_NC_U16_fake16_e64_gfx12: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_ADD_F16_e64_gfx10:
    case AMDGPU::V_ADD_F16_e64_vi:
    case AMDGPU::V_ADD_F16_fake16_e64_gfx11:
    case AMDGPU::V_ADD_F16_fake16_e64_gfx12:
    case AMDGPU::V_ADD_F32_e64_gfx10:
    case AMDGPU::V_ADD_F32_e64_gfx11:
    case AMDGPU::V_ADD_F32_e64_gfx12:
    case AMDGPU::V_ADD_F32_e64_vi:
    case AMDGPU::V_ADD_F64_e64_gfx11:
    case AMDGPU::V_ADD_F64_e64_gfx12:
    case AMDGPU::V_ADD_F64_gfx10:
    case AMDGPU::V_ADD_F64_vi:
    case AMDGPU::V_CVT_PKRTZ_F16_F32_e64_gfx10:
    case AMDGPU::V_CVT_PKRTZ_F16_F32_e64_vi:
    case AMDGPU::V_CVT_PK_BF16_F32_e64_gfx1250:
    case AMDGPU::V_CVT_PK_BF16_F32_vi:
    case AMDGPU::V_CVT_PK_F16_F32_e64_gfx1250:
    case AMDGPU::V_CVT_PK_F16_F32_gfx9:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_e64_gfx11:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_e64_gfx12:
    case AMDGPU::V_LDEXP_F16_e64_gfx10:
    case AMDGPU::V_LDEXP_F16_e64_vi:
    case AMDGPU::V_LDEXP_F16_fake16_e64_gfx11:
    case AMDGPU::V_LDEXP_F16_fake16_e64_gfx12:
    case AMDGPU::V_LDEXP_F32_e64_gfx10:
    case AMDGPU::V_LDEXP_F32_e64_gfx11:
    case AMDGPU::V_LDEXP_F32_e64_gfx12:
    case AMDGPU::V_LDEXP_F32_e64_vi:
    case AMDGPU::V_LDEXP_F64_e64_gfx11:
    case AMDGPU::V_LDEXP_F64_e64_gfx12:
    case AMDGPU::V_LDEXP_F64_e64_gfx1250:
    case AMDGPU::V_LDEXP_F64_gfx10:
    case AMDGPU::V_LDEXP_F64_vi:
    case AMDGPU::V_MAXIMUM_F16_fake16_e64_gfx12:
    case AMDGPU::V_MAXIMUM_F32_e64_gfx12:
    case AMDGPU::V_MAXIMUM_F64_e64_gfx11:
    case AMDGPU::V_MAXIMUM_F64_e64_gfx12:
    case AMDGPU::V_MAX_F16V_MAX_F16_fake16_e64_gfx11:
    case AMDGPU::V_MAX_F16_e64_gfx10:
    case AMDGPU::V_MAX_F16_e64_vi:
    case AMDGPU::V_MAX_F32_e64_gfx10:
    case AMDGPU::V_MAX_F32_e64_gfx11:
    case AMDGPU::V_MAX_F32_e64_vi:
    case AMDGPU::V_MAX_F64_e64_gfx11:
    case AMDGPU::V_MAX_F64_gfx10:
    case AMDGPU::V_MAX_F64_vi:
    case AMDGPU::V_MAX_NUM_F16_fake16_e64_gfx12:
    case AMDGPU::V_MAX_NUM_F32_e64_gfx12:
    case AMDGPU::V_MAX_NUM_F64_e64_gfx12:
    case AMDGPU::V_MINIMUM_F16_fake16_e64_gfx12:
    case AMDGPU::V_MINIMUM_F32_e64_gfx12:
    case AMDGPU::V_MINIMUM_F64_e64_gfx11:
    case AMDGPU::V_MINIMUM_F64_e64_gfx12:
    case AMDGPU::V_MIN_F16V_MIN_F16_fake16_e64_gfx11:
    case AMDGPU::V_MIN_F16_e64_gfx10:
    case AMDGPU::V_MIN_F16_e64_vi:
    case AMDGPU::V_MIN_F32_e64_gfx10:
    case AMDGPU::V_MIN_F32_e64_gfx11:
    case AMDGPU::V_MIN_F32_e64_vi:
    case AMDGPU::V_MIN_F64_e64_gfx11:
    case AMDGPU::V_MIN_F64_gfx10:
    case AMDGPU::V_MIN_F64_vi:
    case AMDGPU::V_MIN_NUM_F16_fake16_e64_gfx12:
    case AMDGPU::V_MIN_NUM_F32_e64_gfx12:
    case AMDGPU::V_MIN_NUM_F64_e64_gfx12:
    case AMDGPU::V_MUL_DX9_ZERO_F32_e64_gfx11:
    case AMDGPU::V_MUL_DX9_ZERO_F32_e64_gfx12:
    case AMDGPU::V_MUL_F16_e64_gfx10:
    case AMDGPU::V_MUL_F16_e64_vi:
    case AMDGPU::V_MUL_F16_fake16_e64_gfx11:
    case AMDGPU::V_MUL_F16_fake16_e64_gfx12:
    case AMDGPU::V_MUL_F32_e64_gfx10:
    case AMDGPU::V_MUL_F32_e64_gfx11:
    case AMDGPU::V_MUL_F32_e64_gfx12:
    case AMDGPU::V_MUL_F32_e64_vi:
    case AMDGPU::V_MUL_F64_e64_gfx11:
    case AMDGPU::V_MUL_F64_e64_gfx12:
    case AMDGPU::V_MUL_F64_gfx10:
    case AMDGPU::V_MUL_F64_vi:
    case AMDGPU::V_MUL_LEGACY_F32_e64_gfx10:
    case AMDGPU::V_MUL_LEGACY_F32_e64_gfx90a:
    case AMDGPU::V_MUL_LEGACY_F32_e64_vi:
    case AMDGPU::V_PK_FMAC_F16_e64_gfx9:
    case AMDGPU::V_SUBREV_F16_e64_gfx10:
    case AMDGPU::V_SUBREV_F16_e64_vi:
    case AMDGPU::V_SUBREV_F16_fake16_e64_gfx11:
    case AMDGPU::V_SUBREV_F16_fake16_e64_gfx12:
    case AMDGPU::V_SUBREV_F32_e64_gfx10:
    case AMDGPU::V_SUBREV_F32_e64_gfx11:
    case AMDGPU::V_SUBREV_F32_e64_gfx12:
    case AMDGPU::V_SUBREV_F32_e64_vi:
    case AMDGPU::V_SUB_F16_e64_gfx10:
    case AMDGPU::V_SUB_F16_e64_vi:
    case AMDGPU::V_SUB_F16_fake16_e64_gfx11:
    case AMDGPU::V_SUB_F16_fake16_e64_gfx12:
    case AMDGPU::V_SUB_F32_e64_gfx10:
    case AMDGPU::V_SUB_F32_e64_gfx11:
    case AMDGPU::V_SUB_F32_e64_gfx12:
    case AMDGPU::V_SUB_F32_e64_vi:
    case AMDGPU::V_TRIG_PREOP_F64_e64_gfx11:
    case AMDGPU::V_TRIG_PREOP_F64_e64_gfx12:
    case AMDGPU::V_TRIG_PREOP_F64_gfx10:
    case AMDGPU::V_TRIG_PREOP_F64_vi: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: clamp
        return 15;
      case 6:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CNDMASK_B16_fake16_e64_gfx11:
    case AMDGPU::V_CNDMASK_B16_fake16_e64_gfx12:
    case AMDGPU::V_CNDMASK_B32_e64_gfx10:
    case AMDGPU::V_CNDMASK_B32_e64_gfx11:
    case AMDGPU::V_CNDMASK_B32_e64_gfx12:
    case AMDGPU::V_CNDMASK_B32_e64_gfx6_gfx7:
    case AMDGPU::V_CNDMASK_B32_e64_vi: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2
        return 50;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CVT_SCALEF32_PK_FP4_BF16_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_FP4_F16_vi:
    case AMDGPU::V_CVT_SR_BF8_F32_vi:
    case AMDGPU::V_CVT_SR_FP8_F32_vi: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2_modifiers
        return 10;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_ASHR_PK_I8_I32_e64_gfx1250:
    case AMDGPU::V_ASHR_PK_I8_I32_vi:
    case AMDGPU::V_ASHR_PK_U8_I32_e64_gfx1250:
    case AMDGPU::V_ASHR_PK_U8_I32_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_BF8_F32_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_FP4_F32_vi:
    case AMDGPU::V_CVT_SCALEF32_PK_FP8_F32_vi:
    case AMDGPU::V_CVT_SCALEF32_SR_BF8_BF16_vi:
    case AMDGPU::V_CVT_SCALEF32_SR_BF8_F16_vi:
    case AMDGPU::V_CVT_SCALEF32_SR_BF8_F32_vi:
    case AMDGPU::V_CVT_SCALEF32_SR_FP8_BF16_vi:
    case AMDGPU::V_CVT_SCALEF32_SR_FP8_F16_vi:
    case AMDGPU::V_CVT_SCALEF32_SR_FP8_F32_vi:
    case AMDGPU::V_CVT_SCALEF32_SR_PK_FP4_BF16_vi:
    case AMDGPU::V_CVT_SCALEF32_SR_PK_FP4_F16_vi:
    case AMDGPU::V_CVT_SCALEF32_SR_PK_FP4_F32_vi: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2_modifiers
        return 10;
      case 6:
        // op: src2
        return 50;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CVT_PK_U8_F32_gfx6_gfx7: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2_modifiers
        return 10;
      case 6:
        // op: src2
        return 50;
      case 7:
        // op: clamp
        return 11;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CUBEID_F32_gfx6_gfx7:
    case AMDGPU::V_CUBEMA_F32_gfx6_gfx7:
    case AMDGPU::V_CUBESC_F32_gfx6_gfx7:
    case AMDGPU::V_CUBETC_F32_gfx6_gfx7:
    case AMDGPU::V_DIV_FIXUP_F32_gfx6_gfx7:
    case AMDGPU::V_DIV_FIXUP_F64_gfx6_gfx7:
    case AMDGPU::V_DIV_FMAS_F32_gfx6_gfx7:
    case AMDGPU::V_DIV_FMAS_F64_gfx6_gfx7:
    case AMDGPU::V_FMA_F32_gfx6_gfx7:
    case AMDGPU::V_FMA_F64_gfx6_gfx7:
    case AMDGPU::V_MAD_F32_gfx6_gfx7:
    case AMDGPU::V_MAD_LEGACY_F32_gfx6_gfx7:
    case AMDGPU::V_MAX3_F32_gfx6_gfx7:
    case AMDGPU::V_MED3_F32_gfx6_gfx7:
    case AMDGPU::V_MIN3_F32_gfx6_gfx7:
    case AMDGPU::V_MULLIT_F32_gfx6_gfx7: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2_modifiers
        return 10;
      case 6:
        // op: src2
        return 50;
      case 7:
        // op: clamp
        return 11;
      case 8:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_fake16_e64_gfx11:
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_fake16_e64_gfx12:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_fake16_e64_gfx11:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_fake16_e64_gfx12:
    case AMDGPU::V_CVT_PK_U8_F32_e64_gfx11:
    case AMDGPU::V_CVT_PK_U8_F32_e64_gfx12:
    case AMDGPU::V_CVT_PK_U8_F32_gfx10:
    case AMDGPU::V_CVT_PK_U8_F32_vi:
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_fake16_e64_gfx11:
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_fake16_e64_gfx12:
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_fake16_e64_gfx11:
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_fake16_e64_gfx12:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_fake16_e64_gfx11:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_fake16_e64_gfx12:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_fake16_e64_gfx11:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_fake16_e64_gfx12:
    case AMDGPU::V_MAX3_I16_fake16_e64_gfx11:
    case AMDGPU::V_MAX3_I16_fake16_e64_gfx12:
    case AMDGPU::V_MAX3_U16_fake16_e64_gfx11:
    case AMDGPU::V_MAX3_U16_fake16_e64_gfx12:
    case AMDGPU::V_MED3_I16_fake16_e64_gfx11:
    case AMDGPU::V_MED3_I16_fake16_e64_gfx12:
    case AMDGPU::V_MED3_U16V_MED3_U16_fake16_e64_gfx11:
    case AMDGPU::V_MED3_U16V_MED3_U16_fake16_e64_gfx12:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_fake16_e64_gfx11:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_fake16_e64_gfx12:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_fake16_e64_gfx11:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_fake16_e64_gfx12: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2_modifiers
        return 10;
      case 6:
        // op: src2
        return 50;
      case 7:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CUBEID_F32_e64_gfx11:
    case AMDGPU::V_CUBEID_F32_e64_gfx12:
    case AMDGPU::V_CUBEID_F32_gfx10:
    case AMDGPU::V_CUBEID_F32_vi:
    case AMDGPU::V_CUBEMA_F32_e64_gfx11:
    case AMDGPU::V_CUBEMA_F32_e64_gfx12:
    case AMDGPU::V_CUBEMA_F32_gfx10:
    case AMDGPU::V_CUBEMA_F32_vi:
    case AMDGPU::V_CUBESC_F32_e64_gfx11:
    case AMDGPU::V_CUBESC_F32_e64_gfx12:
    case AMDGPU::V_CUBESC_F32_gfx10:
    case AMDGPU::V_CUBESC_F32_vi:
    case AMDGPU::V_CUBETC_F32_e64_gfx11:
    case AMDGPU::V_CUBETC_F32_e64_gfx12:
    case AMDGPU::V_CUBETC_F32_gfx10:
    case AMDGPU::V_CUBETC_F32_vi:
    case AMDGPU::V_CVT_SR_PK_BF16_F32_e64_gfx1250:
    case AMDGPU::V_CVT_SR_PK_F16_F32_e64_gfx1250:
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_fake16_e64_gfx11:
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_fake16_e64_gfx12:
    case AMDGPU::V_DIV_FIXUP_F16_gfx10:
    case AMDGPU::V_DIV_FIXUP_F16_gfx9_gfx9:
    case AMDGPU::V_DIV_FIXUP_F16_vi:
    case AMDGPU::V_DIV_FIXUP_F32_e64_gfx11:
    case AMDGPU::V_DIV_FIXUP_F32_e64_gfx12:
    case AMDGPU::V_DIV_FIXUP_F32_gfx10:
    case AMDGPU::V_DIV_FIXUP_F32_vi:
    case AMDGPU::V_DIV_FIXUP_F64_e64_gfx11:
    case AMDGPU::V_DIV_FIXUP_F64_e64_gfx12:
    case AMDGPU::V_DIV_FIXUP_F64_e64_gfx1250:
    case AMDGPU::V_DIV_FIXUP_F64_gfx10:
    case AMDGPU::V_DIV_FIXUP_F64_vi:
    case AMDGPU::V_DIV_FIXUP_LEGACY_F16_gfx9:
    case AMDGPU::V_DIV_FMAS_F32_e64_gfx11:
    case AMDGPU::V_DIV_FMAS_F32_e64_gfx12:
    case AMDGPU::V_DIV_FMAS_F32_gfx10:
    case AMDGPU::V_DIV_FMAS_F32_vi:
    case AMDGPU::V_DIV_FMAS_F64_e64_gfx11:
    case AMDGPU::V_DIV_FMAS_F64_e64_gfx12:
    case AMDGPU::V_DIV_FMAS_F64_e64_gfx1250:
    case AMDGPU::V_DIV_FMAS_F64_gfx10:
    case AMDGPU::V_DIV_FMAS_F64_vi:
    case AMDGPU::V_FMA_DX9_ZERO_F32_e64_gfx11:
    case AMDGPU::V_FMA_DX9_ZERO_F32_e64_gfx12:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_fake16_e64_gfx11:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_fake16_e64_gfx12:
    case AMDGPU::V_FMA_F16_gfx10:
    case AMDGPU::V_FMA_F16_gfx9_gfx9:
    case AMDGPU::V_FMA_F16_vi:
    case AMDGPU::V_FMA_F32_e64_gfx11:
    case AMDGPU::V_FMA_F32_e64_gfx12:
    case AMDGPU::V_FMA_F32_gfx10:
    case AMDGPU::V_FMA_F32_vi:
    case AMDGPU::V_FMA_F64_e64_gfx11:
    case AMDGPU::V_FMA_F64_e64_gfx12:
    case AMDGPU::V_FMA_F64_e64_gfx1250:
    case AMDGPU::V_FMA_F64_gfx10:
    case AMDGPU::V_FMA_F64_vi:
    case AMDGPU::V_FMA_LEGACY_F16_gfx9:
    case AMDGPU::V_FMA_LEGACY_F32_gfx10:
    case AMDGPU::V_MAD_F16_gfx9_gfx9:
    case AMDGPU::V_MAD_F16_vi:
    case AMDGPU::V_MAD_F32_gfx10:
    case AMDGPU::V_MAD_F32_vi:
    case AMDGPU::V_MAD_LEGACY_F16_gfx9:
    case AMDGPU::V_MAD_LEGACY_F32_gfx10:
    case AMDGPU::V_MAD_LEGACY_F32_vi:
    case AMDGPU::V_MAX3_F16_fake16_e64_gfx11:
    case AMDGPU::V_MAX3_F16_gfx10:
    case AMDGPU::V_MAX3_F16_vi:
    case AMDGPU::V_MAX3_F32_e64_gfx11:
    case AMDGPU::V_MAX3_F32_gfx10:
    case AMDGPU::V_MAX3_F32_vi:
    case AMDGPU::V_MAX3_NUM_F16_fake16_e64_gfx12:
    case AMDGPU::V_MAX3_NUM_F32_e64_gfx12:
    case AMDGPU::V_MAXIMUM3_F16_fake16_e64_gfx12:
    case AMDGPU::V_MAXIMUM3_F32_e64_gfx12:
    case AMDGPU::V_MAXIMUM3_F32_vi:
    case AMDGPU::V_MAXIMUMMINIMUM_F16_fake16_e64_gfx12:
    case AMDGPU::V_MAXIMUMMINIMUM_F32_e64_gfx12:
    case AMDGPU::V_MAXMIN_F16_fake16_e64_gfx11:
    case AMDGPU::V_MAXMIN_F32_e64_gfx11:
    case AMDGPU::V_MAXMIN_NUM_F16_fake16_e64_gfx12:
    case AMDGPU::V_MAXMIN_NUM_F32_e64_gfx12:
    case AMDGPU::V_MED3_F16_fake16_e64_gfx11:
    case AMDGPU::V_MED3_F16_gfx10:
    case AMDGPU::V_MED3_F16_vi:
    case AMDGPU::V_MED3_F32_e64_gfx11:
    case AMDGPU::V_MED3_F32_gfx10:
    case AMDGPU::V_MED3_F32_vi:
    case AMDGPU::V_MED3_NUM_F16_fake16_e64_gfx12:
    case AMDGPU::V_MED3_NUM_F32_e64_gfx12:
    case AMDGPU::V_MIN3_F16_fake16_e64_gfx11:
    case AMDGPU::V_MIN3_F16_gfx10:
    case AMDGPU::V_MIN3_F16_vi:
    case AMDGPU::V_MIN3_F32_e64_gfx11:
    case AMDGPU::V_MIN3_F32_gfx10:
    case AMDGPU::V_MIN3_F32_vi:
    case AMDGPU::V_MIN3_NUM_F16_fake16_e64_gfx12:
    case AMDGPU::V_MIN3_NUM_F32_e64_gfx12:
    case AMDGPU::V_MINIMUM3_F16_fake16_e64_gfx12:
    case AMDGPU::V_MINIMUM3_F32_e64_gfx12:
    case AMDGPU::V_MINIMUM3_F32_vi:
    case AMDGPU::V_MINIMUMMAXIMUM_F16_fake16_e64_gfx12:
    case AMDGPU::V_MINIMUMMAXIMUM_F32_e64_gfx12:
    case AMDGPU::V_MINMAX_F16_fake16_e64_gfx11:
    case AMDGPU::V_MINMAX_F32_e64_gfx11:
    case AMDGPU::V_MINMAX_NUM_F16_fake16_e64_gfx12:
    case AMDGPU::V_MINMAX_NUM_F32_e64_gfx12:
    case AMDGPU::V_MULLIT_F32_e64_gfx11:
    case AMDGPU::V_MULLIT_F32_e64_gfx12:
    case AMDGPU::V_MULLIT_F32_gfx10: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2_modifiers
        return 10;
      case 6:
        // op: src2
        return 50;
      case 7:
        // op: clamp
        return 15;
      case 8:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_MAC_F32_e64_gfx6_gfx7:
    case AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 7:
        // op: clamp
        return 11;
      case 8:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_DOT2C_I32_I16_e64_vi:
    case AMDGPU::V_DOT4C_I32_I8_e64_vi:
    case AMDGPU::V_DOT8C_I32_I4_e64_vi: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 7:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_DOT2C_F32_BF16_e64_vi:
    case AMDGPU::V_DOT2C_F32_F16_e64_vi:
    case AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11:
    case AMDGPU::V_FMAC_F16_e64_gfx10:
    case AMDGPU::V_FMAC_F16_fake16_e64_gfx11:
    case AMDGPU::V_FMAC_F16_fake16_e64_gfx12:
    case AMDGPU::V_FMAC_F32_e64_gfx10:
    case AMDGPU::V_FMAC_F32_e64_gfx11:
    case AMDGPU::V_FMAC_F32_e64_gfx12:
    case AMDGPU::V_FMAC_F32_e64_vi:
    case AMDGPU::V_FMAC_F64_e64_gfx12:
    case AMDGPU::V_FMAC_F64_e64_gfx90a:
    case AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10:
    case AMDGPU::V_MAC_F16_e64_vi:
    case AMDGPU::V_MAC_F32_e64_gfx10:
    case AMDGPU::V_MAC_F32_e64_vi:
    case AMDGPU::V_MAC_LEGACY_F32_e64_gfx10: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 7:
        // op: clamp
        return 15;
      case 8:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CMP_CLASS_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_CLASS_F32_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 3:
        // op: src1
        return 41;
      case 2:
        // op: src0
        return 64;
      case 4:
        // op: dpp8
        return 72;
      case 5:
        // op: fi
        return 32;
      case 0:
        // op: sdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CMP_CLASS_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_CLASS_F32_e64_dpp_gfx12: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 3:
        // op: src1
        return 41;
      case 4:
        // op: dpp_ctrl
        return 72;
      case 7:
        // op: bound_ctrl
        return 83;
      case 6:
        // op: bank_mask
        return 88;
      case 5:
        // op: row_mask
        return 92;
      case 8:
        // op: fi
        return 82;
      case 2:
        // op: src0
        return 64;
      case 0:
        // op: sdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CMP_CLASS_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 2:
        // op: src0
        return 64;
      case 5:
        // op: dpp8
        return 72;
      case 6:
        // op: fi
        return 32;
      case 0:
        // op: sdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CMP_CLASS_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_U16_t16_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 2:
        // op: src0
        return 64;
      case 6:
        // op: dpp8
        return 72;
      case 7:
        // op: fi
        return 32;
      case 0:
        // op: sdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CMP_CLASS_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e64_dpp_gfx12: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: dpp_ctrl
        return 72;
      case 8:
        // op: bound_ctrl
        return 83;
      case 7:
        // op: bank_mask
        return 88;
      case 6:
        // op: row_mask
        return 92;
      case 9:
        // op: fi
        return 82;
      case 2:
        // op: src0
        return 64;
      case 0:
        // op: sdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CMP_CLASS_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GE_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GE_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GT_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GT_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GT_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GT_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LE_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LE_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LE_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LE_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LT_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LT_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LT_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LT_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NE_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NE_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NE_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NE_U16_t16_e64_dpp_gfx12: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 3:
        // op: src1_modifiers
        return 9;
      case 4:
        // op: src1
        return 41;
      case 6:
        // op: dpp_ctrl
        return 72;
      case 9:
        // op: bound_ctrl
        return 83;
      case 8:
        // op: bank_mask
        return 88;
      case 7:
        // op: row_mask
        return 92;
      case 10:
        // op: fi
        return 82;
      case 2:
        // op: src0
        return 64;
      case 0:
        // op: sdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CMP_EQ_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_F_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_F_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LG_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LG_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LG_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LG_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NEQ_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NGE_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NGE_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NGE_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NGT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NGT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NGT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NLE_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NLE_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NLE_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NLG_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NLG_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NLG_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NLT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NLT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NLT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_O_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_O_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_O_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_O_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_T_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_T_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_U_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_U_F32_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 3:
        // op: src1_modifiers
        return 9;
      case 5:
        // op: clamp
        return 15;
      case 4:
        // op: src1
        return 41;
      case 2:
        // op: src0
        return 64;
      case 6:
        // op: dpp8
        return 72;
      case 7:
        // op: fi
        return 32;
      case 0:
        // op: sdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CMP_EQ_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_F_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LG_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LG_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NGE_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NGE_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NGT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NGT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NLE_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NLE_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NLG_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NLG_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NLT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NLT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_O_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_O_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_T_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 3:
        // op: src1_modifiers
        return 9;
      case 5:
        // op: clamp
        return 15;
      case 4:
        // op: src1
        return 41;
      case 2:
        // op: src0
        return 64;
      case 7:
        // op: dpp8
        return 72;
      case 8:
        // op: fi
        return 32;
      case 0:
        // op: sdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CMP_EQ_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_F_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_F_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GE_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GT_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GT_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LE_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LE_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LE_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LE_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LG_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LG_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LG_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LG_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LT_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LT_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NEQ_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NGE_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NGE_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NGE_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NGT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NGT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NGT_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NLE_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NLE_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NLE_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NLG_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NLG_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NLG_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NLT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NLT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NLT_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_O_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_O_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_O_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_O_F32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_T_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_T_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_U_F32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_U_F32_e64_dpp_gfx12: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 3:
        // op: src1_modifiers
        return 9;
      case 5:
        // op: clamp
        return 15;
      case 4:
        // op: src1
        return 41;
      case 6:
        // op: dpp_ctrl
        return 72;
      case 9:
        // op: bound_ctrl
        return 83;
      case 8:
        // op: bank_mask
        return 88;
      case 7:
        // op: row_mask
        return 92;
      case 10:
        // op: fi
        return 82;
      case 2:
        // op: src0
        return 64;
      case 0:
        // op: sdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CMP_EQ_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_F_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LE_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LE_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LG_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LG_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NGE_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NGE_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NGT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NGT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NLE_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NLE_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NLG_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NLG_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NLT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NLT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_O_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_O_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_T_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e64_dpp_gfx12: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 8;
      case 3:
        // op: src1_modifiers
        return 9;
      case 5:
        // op: clamp
        return 15;
      case 4:
        // op: src1
        return 41;
      case 7:
        // op: dpp_ctrl
        return 72;
      case 10:
        // op: bound_ctrl
        return 83;
      case 9:
        // op: bank_mask
        return 88;
      case 8:
        // op: row_mask
        return 92;
      case 11:
        // op: fi
        return 82;
      case 2:
        // op: src0
        return 64;
      case 0:
        // op: sdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_INTERP_P1_F32_e64_gfx10:
    case AMDGPU::V_INTERP_P2_F32_e64_gfx10: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 9;
      case 2:
        // op: src0
        return 41;
      case 5:
        // op: clamp
        return 15;
      case 6:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: attr
        return 32;
      case 4:
        // op: attrchan
        return 38;
      }
      break;
    }
    case AMDGPU::V_INTERP_P1_F32_e64_vi:
    case AMDGPU::V_INTERP_P2_F32_e64_vi: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 9;
      case 2:
        // op: src0
        return 41;
      case 5:
        // op: clamp
        return 15;
      case 6:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 4:
        // op: attrchan
        return 38;
      case 3:
        // op: attr
        return 32;
      }
      break;
    }
    case AMDGPU::V_INTERP_P2_F16_gfx10: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 9;
      case 2:
        // op: src0
        return 41;
      case 5:
        // op: src2_modifiers
        return 10;
      case 6:
        // op: src2
        return 50;
      case 8:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: attr
        return 32;
      case 4:
        // op: attrchan
        return 38;
      case 7:
        // op: high
        return 40;
      }
      break;
    }
    case AMDGPU::V_INTERP_P2_F16_opsel_gfx9:
    case AMDGPU::V_INTERP_P2_F16_vi:
    case AMDGPU::V_INTERP_P2_LEGACY_F16_gfx9: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 9;
      case 2:
        // op: src0
        return 41;
      case 5:
        // op: src2_modifiers
        return 10;
      case 6:
        // op: src2
        return 50;
      case 8:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 4:
        // op: attrchan
        return 38;
      case 3:
        // op: attr
        return 32;
      case 7:
        // op: high
        return 40;
      }
      break;
    }
    case AMDGPU::V_INTERP_P1LV_F16_gfx10: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 9;
      case 2:
        // op: src0
        return 41;
      case 5:
        // op: src2_modifiers
        return 10;
      case 6:
        // op: src2
        return 50;
      case 8:
        // op: clamp
        return 15;
      case 9:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: attr
        return 32;
      case 4:
        // op: attrchan
        return 38;
      case 7:
        // op: high
        return 40;
      }
      break;
    }
    case AMDGPU::V_INTERP_P1LV_F16_vi: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 9;
      case 2:
        // op: src0
        return 41;
      case 5:
        // op: src2_modifiers
        return 10;
      case 6:
        // op: src2
        return 50;
      case 8:
        // op: clamp
        return 15;
      case 9:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 4:
        // op: attrchan
        return 38;
      case 3:
        // op: attr
        return 32;
      case 7:
        // op: high
        return 40;
      }
      break;
    }
    case AMDGPU::V_INTERP_P1LL_F16_gfx10: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 9;
      case 2:
        // op: src0
        return 41;
      case 6:
        // op: clamp
        return 15;
      case 7:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: attr
        return 32;
      case 4:
        // op: attrchan
        return 38;
      case 5:
        // op: high
        return 40;
      }
      break;
    }
    case AMDGPU::V_INTERP_P1LL_F16_vi: {
      switch (OpNum) {
      case 1:
        // op: src0_modifiers
        return 9;
      case 2:
        // op: src0
        return 41;
      case 6:
        // op: clamp
        return 15;
      case 7:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 4:
        // op: attrchan
        return 38;
      case 3:
        // op: attr
        return 32;
      case 5:
        // op: high
        return 40;
      }
      break;
    }
    case AMDGPU::V_CMPX_EQ_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_F_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_F_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMPX_T_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMPX_T_U32_e64_dpp8_gfx11: {
      switch (OpNum) {
      case 1:
        // op: src1
        return 41;
      case 0:
        // op: src0
        return 64;
      case 2:
        // op: dpp8
        return 72;
      case 3:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CMPX_EQ_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_F_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_F_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMPX_T_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMPX_T_U32_e64_dpp_gfx11: {
      switch (OpNum) {
      case 1:
        // op: src1
        return 41;
      case 2:
        // op: dpp_ctrl
        return 72;
      case 5:
        // op: bound_ctrl
        return 83;
      case 4:
        // op: bank_mask
        return 88;
      case 3:
        // op: row_mask
        return 92;
      case 6:
        // op: fi
        return 82;
      case 0:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_CMPX_EQ_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_F_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_F_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_T_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_T_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_F_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_F_I32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_F_I32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_F_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_F_U32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_F_U32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GE_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_I32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GE_I32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GE_I32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_I32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GE_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_U32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GE_U32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GE_U32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_U32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GT_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_I32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GT_I32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GT_I32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GT_I32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GT_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_U32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GT_U32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GT_U32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GT_U32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LE_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_I32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LE_I32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LE_I32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LE_I32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LE_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_U32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LE_U32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LE_U32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LE_U32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LT_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_I32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LT_I32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LT_I32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LT_I32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LT_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_U32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LT_U32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LT_U32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LT_U32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NE_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_I32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_I32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NE_I32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NE_I32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NE_I32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NE_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_U32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_U32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NE_U32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NE_U32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NE_U32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_T_I32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_T_I32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_T_I32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_T_U32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_T_U32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_T_U32_e32_dpp8_w64_gfx11: {
      switch (OpNum) {
      case 1:
        // op: src1
        return 9;
      case 0:
        // op: src0
        return 32;
      case 2:
        // op: dpp8
        return 40;
      case 3:
        // op: fi
        return 0;
      }
      break;
    }
    case AMDGPU::V_CMPX_EQ_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_F_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_F_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_T_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_T_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_EQ_I32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_EQ_U16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_EQ_U32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_F_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_F_I32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_F_I32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_F_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_F_U32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_F_U32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GE_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GE_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GE_I32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GE_I32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GE_I32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_I32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_U16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GE_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GE_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GE_U32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GE_U32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GE_U32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_U32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GT_I16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GT_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GT_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GT_I32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GT_I32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GT_I32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GT_I32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GT_U16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GT_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GT_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GT_U32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GT_U32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GT_U32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GT_U32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LE_I16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LE_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LE_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LE_I32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LE_I32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LE_I32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LE_I32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LE_U16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LE_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LE_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LE_U32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LE_U32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LE_U32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LE_U32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LT_I16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LT_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LT_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LT_I32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LT_I32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LT_I32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LT_I32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LT_U16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LT_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LT_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LT_U32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LT_U32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LT_U32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LT_U32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NE_I16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NE_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NE_I32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NE_I32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NE_I32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NE_I32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NE_I32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NE_U16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NE_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NE_U32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NE_U32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NE_U32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NE_U32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NE_U32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_T_I32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_T_I32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_T_I32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_T_U32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_T_U32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_T_U32_e32_dpp_w64_gfx11: {
      switch (OpNum) {
      case 1:
        // op: src1
        return 9;
      case 0:
        // op: src0
        return 32;
      case 2:
        // op: dpp_ctrl
        return 40;
      case 5:
        // op: bound_ctrl
        return 51;
      case 4:
        // op: bank_mask
        return 56;
      case 3:
        // op: row_mask
        return 60;
      case 6:
        // op: fi
        return 50;
      }
      break;
    }
    case AMDGPU::GLOBAL_LOAD_LDS_DWORD_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_LDS_SBYTE_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_LDS_SSHORT_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_LDS_UBYTE_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_LDS_USHORT_SADDR_gfx10: {
      switch (OpNum) {
      case 1:
        // op: vaddr
        return 32;
      case 0:
        // op: saddr
        return 48;
      case 3:
        // op: cpol
        return 12;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::GLOBAL_LOAD_LDS_DWORDX3_SADDR_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_DWORDX3_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_DWORDX4_SADDR_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_DWORDX4_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_DWORD_SADDR_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_DWORD_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_SBYTE_SADDR_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_SBYTE_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_SSHORT_SADDR_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_SSHORT_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_UBYTE_SADDR_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_UBYTE_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_LDS_USHORT_SADDR_gfx940:
    case AMDGPU::GLOBAL_LOAD_LDS_USHORT_SADDR_vi: {
      switch (OpNum) {
      case 1:
        // op: vaddr
        return 32;
      case 0:
        // op: saddr
        return 48;
      case 3:
        // op: cpol
        return 16;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SVS_gfx11:
    case AMDGPU::SCRATCH_STORE_BYTE_SVS_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX2_SVS_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX3_SVS_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX4_SVS_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORD_SVS_gfx11:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SVS_gfx11:
    case AMDGPU::SCRATCH_STORE_SHORT_SVS_gfx11: {
      switch (OpNum) {
      case 1:
        // op: vaddr
        return 32;
      case 0:
        // op: vdata
        return 40;
      case 2:
        // op: saddr
        return 48;
      case 4:
        // op: cpol
        return 13;
      case 3:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SVS_gfx940:
    case AMDGPU::SCRATCH_STORE_BYTE_SVS_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORDX2_SVS_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORDX3_SVS_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORDX4_SVS_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORD_SVS_gfx940:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SVS_gfx940:
    case AMDGPU::SCRATCH_STORE_SHORT_SVS_gfx940: {
      switch (OpNum) {
      case 1:
        // op: vaddr
        return 32;
      case 0:
        // op: vdata
        return 40;
      case 2:
        // op: saddr
        return 48;
      case 4:
        // op: cpol
        return 16;
      case 3:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_gfx10:
    case AMDGPU::SCRATCH_STORE_BYTE_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORDX2_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORDX3_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORDX4_gfx10:
    case AMDGPU::SCRATCH_STORE_DWORD_gfx10:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_gfx10:
    case AMDGPU::SCRATCH_STORE_SHORT_gfx10: {
      switch (OpNum) {
      case 1:
        // op: vaddr
        return 32;
      case 0:
        // op: vdata
        return 40;
      case 3:
        // op: cpol
        return 12;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_gfx11:
    case AMDGPU::SCRATCH_STORE_BYTE_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX2_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX3_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORDX4_gfx11:
    case AMDGPU::SCRATCH_STORE_DWORD_gfx11:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_gfx11:
    case AMDGPU::SCRATCH_STORE_SHORT_gfx11: {
      switch (OpNum) {
      case 1:
        // op: vaddr
        return 32;
      case 0:
        // op: vdata
        return 40;
      case 3:
        // op: cpol
        return 13;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_VE_gfx940:
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_vi:
    case AMDGPU::SCRATCH_STORE_BYTE_VE_gfx940:
    case AMDGPU::SCRATCH_STORE_BYTE_vi:
    case AMDGPU::SCRATCH_STORE_DWORDX2_VE_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORDX2_vi:
    case AMDGPU::SCRATCH_STORE_DWORDX3_VE_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORDX3_vi:
    case AMDGPU::SCRATCH_STORE_DWORDX4_VE_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORDX4_vi:
    case AMDGPU::SCRATCH_STORE_DWORD_VE_gfx940:
    case AMDGPU::SCRATCH_STORE_DWORD_vi:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_VE_gfx940:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_vi:
    case AMDGPU::SCRATCH_STORE_SHORT_VE_gfx940:
    case AMDGPU::SCRATCH_STORE_SHORT_vi: {
      switch (OpNum) {
      case 1:
        // op: vaddr
        return 32;
      case 0:
        // op: vdata
        return 40;
      case 3:
        // op: cpol
        return 16;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::FLAT_LOAD_DWORDX2_ci:
    case AMDGPU::FLAT_LOAD_DWORDX2_vi:
    case AMDGPU::FLAT_LOAD_DWORDX3_ci:
    case AMDGPU::FLAT_LOAD_DWORDX3_vi:
    case AMDGPU::FLAT_LOAD_DWORDX4_ci:
    case AMDGPU::FLAT_LOAD_DWORDX4_vi:
    case AMDGPU::FLAT_LOAD_DWORD_ci:
    case AMDGPU::FLAT_LOAD_DWORD_vi:
    case AMDGPU::FLAT_LOAD_SBYTE_D16_HI_vi:
    case AMDGPU::FLAT_LOAD_SBYTE_D16_vi:
    case AMDGPU::FLAT_LOAD_SBYTE_ci:
    case AMDGPU::FLAT_LOAD_SBYTE_vi:
    case AMDGPU::FLAT_LOAD_SHORT_D16_HI_vi:
    case AMDGPU::FLAT_LOAD_SHORT_D16_vi:
    case AMDGPU::FLAT_LOAD_SSHORT_ci:
    case AMDGPU::FLAT_LOAD_SSHORT_vi:
    case AMDGPU::FLAT_LOAD_UBYTE_D16_HI_vi:
    case AMDGPU::FLAT_LOAD_UBYTE_D16_vi:
    case AMDGPU::FLAT_LOAD_UBYTE_ci:
    case AMDGPU::FLAT_LOAD_UBYTE_vi:
    case AMDGPU::FLAT_LOAD_USHORT_ci:
    case AMDGPU::FLAT_LOAD_USHORT_vi:
    case AMDGPU::GLOBAL_LOAD_DWORDX2_vi:
    case AMDGPU::GLOBAL_LOAD_DWORDX3_vi:
    case AMDGPU::GLOBAL_LOAD_DWORDX4_vi:
    case AMDGPU::GLOBAL_LOAD_DWORD_vi:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_vi:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_vi:
    case AMDGPU::GLOBAL_LOAD_SBYTE_vi:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_vi:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_vi:
    case AMDGPU::GLOBAL_LOAD_SSHORT_vi:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_vi:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_vi:
    case AMDGPU::GLOBAL_LOAD_UBYTE_vi:
    case AMDGPU::GLOBAL_LOAD_USHORT_vi:
    case AMDGPU::SCRATCH_LOAD_DWORDX2_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_DWORDX2_vi:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_vi:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_vi:
    case AMDGPU::SCRATCH_LOAD_DWORD_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_DWORD_vi:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_vi:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_vi:
    case AMDGPU::SCRATCH_LOAD_SBYTE_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_SBYTE_vi:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_vi:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_vi:
    case AMDGPU::SCRATCH_LOAD_SSHORT_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_SSHORT_vi:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_vi:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_vi:
    case AMDGPU::SCRATCH_LOAD_UBYTE_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_UBYTE_vi:
    case AMDGPU::SCRATCH_LOAD_USHORT_VE_gfx940:
    case AMDGPU::SCRATCH_LOAD_USHORT_vi: {
      switch (OpNum) {
      case 1:
        // op: vaddr
        return 32;
      case 0:
        // op: vdst
        return 55;
      case 3:
        // op: cpol
        return 16;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::FLAT_LOAD_DWORDX2_gfx10:
    case AMDGPU::FLAT_LOAD_DWORDX3_gfx10:
    case AMDGPU::FLAT_LOAD_DWORDX4_gfx10:
    case AMDGPU::FLAT_LOAD_DWORD_gfx10:
    case AMDGPU::FLAT_LOAD_SBYTE_D16_HI_gfx10:
    case AMDGPU::FLAT_LOAD_SBYTE_D16_gfx10:
    case AMDGPU::FLAT_LOAD_SBYTE_gfx10:
    case AMDGPU::FLAT_LOAD_SHORT_D16_HI_gfx10:
    case AMDGPU::FLAT_LOAD_SHORT_D16_gfx10:
    case AMDGPU::FLAT_LOAD_SSHORT_gfx10:
    case AMDGPU::FLAT_LOAD_UBYTE_D16_HI_gfx10:
    case AMDGPU::FLAT_LOAD_UBYTE_D16_gfx10:
    case AMDGPU::FLAT_LOAD_UBYTE_gfx10:
    case AMDGPU::FLAT_LOAD_USHORT_gfx10:
    case AMDGPU::GLOBAL_LOAD_DWORDX2_gfx10:
    case AMDGPU::GLOBAL_LOAD_DWORDX3_gfx10:
    case AMDGPU::GLOBAL_LOAD_DWORDX4_gfx10:
    case AMDGPU::GLOBAL_LOAD_DWORD_gfx10:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_gfx10:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_gfx10:
    case AMDGPU::GLOBAL_LOAD_SBYTE_gfx10:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_gfx10:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_gfx10:
    case AMDGPU::GLOBAL_LOAD_SSHORT_gfx10:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_gfx10:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_gfx10:
    case AMDGPU::GLOBAL_LOAD_UBYTE_gfx10:
    case AMDGPU::GLOBAL_LOAD_USHORT_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORDX2_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_gfx10:
    case AMDGPU::SCRATCH_LOAD_DWORD_gfx10:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_gfx10:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_gfx10:
    case AMDGPU::SCRATCH_LOAD_SBYTE_gfx10:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_gfx10:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_gfx10:
    case AMDGPU::SCRATCH_LOAD_SSHORT_gfx10:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_gfx10:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_gfx10:
    case AMDGPU::SCRATCH_LOAD_UBYTE_gfx10:
    case AMDGPU::SCRATCH_LOAD_USHORT_gfx10: {
      switch (OpNum) {
      case 1:
        // op: vaddr
        return 32;
      case 0:
        // op: vdst
        return 56;
      case 3:
        // op: cpol
        return 12;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::FLAT_LOAD_DWORDX2_gfx11:
    case AMDGPU::FLAT_LOAD_DWORDX3_gfx11:
    case AMDGPU::FLAT_LOAD_DWORDX4_gfx11:
    case AMDGPU::FLAT_LOAD_DWORD_gfx11:
    case AMDGPU::FLAT_LOAD_SBYTE_D16_HI_gfx11:
    case AMDGPU::FLAT_LOAD_SBYTE_D16_gfx11:
    case AMDGPU::FLAT_LOAD_SBYTE_gfx11:
    case AMDGPU::FLAT_LOAD_SHORT_D16_HI_gfx11:
    case AMDGPU::FLAT_LOAD_SHORT_D16_gfx11:
    case AMDGPU::FLAT_LOAD_SSHORT_gfx11:
    case AMDGPU::FLAT_LOAD_UBYTE_D16_HI_gfx11:
    case AMDGPU::FLAT_LOAD_UBYTE_D16_gfx11:
    case AMDGPU::FLAT_LOAD_UBYTE_gfx11:
    case AMDGPU::FLAT_LOAD_USHORT_gfx11:
    case AMDGPU::GLOBAL_LOAD_DWORDX2_gfx11:
    case AMDGPU::GLOBAL_LOAD_DWORDX3_gfx11:
    case AMDGPU::GLOBAL_LOAD_DWORDX4_gfx11:
    case AMDGPU::GLOBAL_LOAD_DWORD_gfx11:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_gfx11:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_gfx11:
    case AMDGPU::GLOBAL_LOAD_SBYTE_gfx11:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_gfx11:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_gfx11:
    case AMDGPU::GLOBAL_LOAD_SSHORT_gfx11:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_gfx11:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_gfx11:
    case AMDGPU::GLOBAL_LOAD_UBYTE_gfx11:
    case AMDGPU::GLOBAL_LOAD_USHORT_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORDX2_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORD_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_gfx11:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_gfx11:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_gfx11:
    case AMDGPU::SCRATCH_LOAD_SSHORT_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_gfx11:
    case AMDGPU::SCRATCH_LOAD_USHORT_gfx11: {
      switch (OpNum) {
      case 1:
        // op: vaddr
        return 32;
      case 0:
        // op: vdst
        return 56;
      case 3:
        // op: cpol
        return 13;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::SCRATCH_LOAD_DWORDX2_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_DWORD_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_SBYTE_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_SSHORT_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_UBYTE_SVS_gfx940:
    case AMDGPU::SCRATCH_LOAD_USHORT_SVS_gfx940: {
      switch (OpNum) {
      case 1:
        // op: vaddr
        return 32;
      case 2:
        // op: saddr
        return 48;
      case 0:
        // op: vdst
        return 55;
      case 4:
        // op: cpol
        return 16;
      case 3:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::SCRATCH_LOAD_DWORDX2_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_DWORD_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_SBYTE_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_SSHORT_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_UBYTE_SVS_gfx11:
    case AMDGPU::SCRATCH_LOAD_USHORT_SVS_gfx11: {
      switch (OpNum) {
      case 1:
        // op: vaddr
        return 32;
      case 2:
        // op: saddr
        return 48;
      case 0:
        // op: vdst
        return 56;
      case 4:
        // op: cpol
        return 13;
      case 3:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_AND_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_AND_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_DEC_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_FCMPSWAP_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_FMAX_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_FMAX_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_FMIN_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_FMIN_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_INC_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_INC_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_OR_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_OR_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_SMAX_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_SMIN_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_SUB_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_SWAP_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_UMAX_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_UMIN_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_XOR_RTN_gfx10:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_ADD_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_AND_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CSUB_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_DEC_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_INC_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_OR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SUB_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_XOR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN_gfx10: {
      switch (OpNum) {
      case 1:
        // op: vaddr
        return 32;
      case 2:
        // op: vdata
        return 40;
      case 0:
        // op: vdst
        return 56;
      case 4:
        // op: cpol
        return 12;
      case 3:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_F32_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_ADD_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_AND_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_AND_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_DEC_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_FCMPSWAP_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_FMAX_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_FMIN_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_INC_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_INC_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_OR_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_OR_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_SMAX_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_SMIN_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_SUB_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_SWAP_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_UMAX_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_UMIN_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_XOR_RTN_gfx11:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_ADD_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_AND_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CSUB_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_DEC_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_INC_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_OR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SUB_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_XOR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN_gfx11: {
      switch (OpNum) {
      case 1:
        // op: vaddr
        return 32;
      case 2:
        // op: vdata
        return 40;
      case 0:
        // op: vdst
        return 56;
      case 4:
        // op: cpol
        return 13;
      case 3:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_F32_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_ADD_F32_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_ADD_F64_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_ADD_F64_RTN_gfx940:
    case AMDGPU::FLAT_ATOMIC_ADD_F64_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_ADD_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_ADD_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_ADD_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_AND_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_AND_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_AND_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_AND_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_AND_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_AND_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_DEC_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_DEC_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_DEC_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_FCMPSWAP_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_FMAX_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_FMAX_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_FMIN_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_FMIN_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_INC_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_INC_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_INC_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_INC_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_INC_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_INC_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_MAX_F64_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_MAX_F64_RTN_gfx940:
    case AMDGPU::FLAT_ATOMIC_MAX_F64_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_MIN_F64_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_MIN_F64_RTN_gfx940:
    case AMDGPU::FLAT_ATOMIC_MIN_F64_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_OR_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_OR_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_OR_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_OR_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_OR_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_OR_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_BF16_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_BF16_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_F16_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_F16_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_SMAX_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_SMAX_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_SMAX_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_SMIN_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_SMIN_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_SMIN_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_SUB_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_SUB_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_SUB_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_SWAP_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_SWAP_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_SWAP_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_UMAX_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_UMAX_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_UMAX_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_UMIN_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_UMIN_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_UMIN_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_XOR_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_XOR_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_XOR_RTN_vi:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_agpr_vi:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_ci:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_RTN_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_RTN_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_RTN_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_OR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_OR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_RTN_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN_vi: {
      switch (OpNum) {
      case 1:
        // op: vaddr
        return 32;
      case 2:
        // op: vdata
        return 40;
      case 0:
        // op: vdst
        return 56;
      case 4:
        // op: cpol
        return 17;
      case 3:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_CSUB_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN_gfx10:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_gfx10: {
      switch (OpNum) {
      case 1:
        // op: vaddr
        return 32;
      case 2:
        // op: vdata
        return 40;
      case 3:
        // op: saddr
        return 48;
      case 0:
        // op: vdst
        return 56;
      case 5:
        // op: cpol
        return 12;
      case 4:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_CSUB_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN_gfx11:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_gfx11: {
      switch (OpNum) {
      case 1:
        // op: vaddr
        return 32;
      case 2:
        // op: vdata
        return 40;
      case 3:
        // op: saddr
        return 48;
      case 0:
        // op: vdst
        return 56;
      case 5:
        // op: cpol
        return 13;
      case 4:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_RTN_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_RTN_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_RTN_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_RTN_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN_gfx940:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_agpr_vi:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_vi: {
      switch (OpNum) {
      case 1:
        // op: vaddr
        return 32;
      case 2:
        // op: vdata
        return 40;
      case 3:
        // op: saddr
        return 48;
      case 0:
        // op: vdst
        return 56;
      case 5:
        // op: cpol
        return 17;
      case 4:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V1_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V2_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V3_gfx90a:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V4_gfx90a: {
      switch (OpNum) {
      case 1:
        // op: vdata
        return 16;
      case 4:
        // op: dmask
        return 8;
      case 5:
        // op: unorm
        return 12;
      case 6:
        // op: cpol
        return 7;
      case 7:
        // op: r128
        return 15;
      case 8:
        // op: lwe
        return 17;
      case 3:
        // op: srsrc
        return 48;
      case 2:
        // op: vaddr
        return 32;
      case 9:
        // op: da
        return 14;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V1_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V2_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V3_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V4_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V1_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V2_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V3_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V4_si:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_RSUB_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V1_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V1_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V1_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V1_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V2_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V2_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V3_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V3_vi:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V4_si:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V4_vi: {
      switch (OpNum) {
      case 1:
        // op: vdata
        return 40;
      case 4:
        // op: dmask
        return 8;
      case 5:
        // op: unorm
        return 12;
      case 6:
        // op: cpol
        return 7;
      case 7:
        // op: r128
        return 15;
      case 8:
        // op: tfe
        return 16;
      case 9:
        // op: lwe
        return 17;
      case 3:
        // op: srsrc
        return 48;
      case 2:
        // op: vaddr
        return 32;
      case 10:
        // op: da
        return 14;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V1_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V2_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V3_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V4_gfx10: {
      switch (OpNum) {
      case 1:
        // op: vdata
        return 40;
      case 4:
        // op: dmask
        return 8;
      case 6:
        // op: unorm
        return 12;
      case 7:
        // op: cpol
        return 7;
      case 8:
        // op: r128
        return 15;
      case 10:
        // op: tfe
        return 16;
      case 11:
        // op: lwe
        return 17;
      case 3:
        // op: srsrc
        return 48;
      case 2:
        // op: vaddr0
        return 32;
      case 5:
        // op: dim
        return 3;
      case 9:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V1_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V2_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V3_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V4_gfx11: {
      switch (OpNum) {
      case 1:
        // op: vdata
        return 40;
      case 4:
        // op: dmask
        return 8;
      case 6:
        // op: unorm
        return 7;
      case 7:
        // op: cpol
        return 12;
      case 8:
        // op: r128
        return 15;
      case 10:
        // op: tfe
        return 53;
      case 11:
        // op: lwe
        return 54;
      case 3:
        // op: srsrc
        return 48;
      case 9:
        // op: a16
        return 16;
      case 2:
        // op: vaddr0
        return 32;
      case 5:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V2_nsa_gfx10: {
      switch (OpNum) {
      case 1:
        // op: vdata
        return 40;
      case 5:
        // op: dmask
        return 8;
      case 7:
        // op: unorm
        return 12;
      case 8:
        // op: cpol
        return 7;
      case 9:
        // op: r128
        return 15;
      case 11:
        // op: tfe
        return 16;
      case 12:
        // op: lwe
        return 17;
      case 4:
        // op: srsrc
        return 48;
      case 2:
        // op: vaddr0
        return 32;
      case 6:
        // op: dim
        return 3;
      case 10:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V2_nsa_gfx11: {
      switch (OpNum) {
      case 1:
        // op: vdata
        return 40;
      case 5:
        // op: dmask
        return 8;
      case 7:
        // op: unorm
        return 7;
      case 8:
        // op: cpol
        return 12;
      case 9:
        // op: r128
        return 15;
      case 11:
        // op: tfe
        return 53;
      case 12:
        // op: lwe
        return 54;
      case 4:
        // op: srsrc
        return 48;
      case 10:
        // op: a16
        return 16;
      case 2:
        // op: vaddr0
        return 32;
      case 6:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V3_nsa_gfx10: {
      switch (OpNum) {
      case 1:
        // op: vdata
        return 40;
      case 6:
        // op: dmask
        return 8;
      case 8:
        // op: unorm
        return 12;
      case 9:
        // op: cpol
        return 7;
      case 10:
        // op: r128
        return 15;
      case 12:
        // op: tfe
        return 16;
      case 13:
        // op: lwe
        return 17;
      case 5:
        // op: srsrc
        return 48;
      case 2:
        // op: vaddr0
        return 32;
      case 7:
        // op: dim
        return 3;
      case 11:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V3_nsa_gfx11: {
      switch (OpNum) {
      case 1:
        // op: vdata
        return 40;
      case 6:
        // op: dmask
        return 8;
      case 8:
        // op: unorm
        return 7;
      case 9:
        // op: cpol
        return 12;
      case 10:
        // op: r128
        return 15;
      case 12:
        // op: tfe
        return 53;
      case 13:
        // op: lwe
        return 54;
      case 5:
        // op: srsrc
        return 48;
      case 11:
        // op: a16
        return 16;
      case 2:
        // op: vaddr0
        return 32;
      case 7:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V4_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FCMPSWAP_V5_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMAX_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_FMIN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_nsa_gfx10:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V4_nsa_gfx10: {
      switch (OpNum) {
      case 1:
        // op: vdata
        return 40;
      case 7:
        // op: dmask
        return 8;
      case 9:
        // op: unorm
        return 12;
      case 10:
        // op: cpol
        return 7;
      case 11:
        // op: r128
        return 15;
      case 13:
        // op: tfe
        return 16;
      case 14:
        // op: lwe
        return 17;
      case 6:
        // op: srsrc
        return 48;
      case 2:
        // op: vaddr0
        return 32;
      case 8:
        // op: dim
        return 3;
      case 12:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_nsa_gfx11:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V4_nsa_gfx11: {
      switch (OpNum) {
      case 1:
        // op: vdata
        return 40;
      case 7:
        // op: dmask
        return 8;
      case 9:
        // op: unorm
        return 7;
      case 10:
        // op: cpol
        return 12;
      case 11:
        // op: r128
        return 15;
      case 13:
        // op: tfe
        return 53;
      case 14:
        // op: lwe
        return 54;
      case 6:
        // op: srsrc
        return 48;
      case 12:
        // op: a16
        return 16;
      case 2:
        // op: vaddr0
        return 32;
      case 8:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::DS_DIRECT_LOAD_gfx12: {
      switch (OpNum) {
      case 1:
        // op: waitvdst
        return 16;
      case 0:
        // op: vdst
        return 0;
      case 2:
        // op: waitvsrc
        return 23;
      }
      break;
    }
    case AMDGPU::LDS_DIRECT_LOAD_gfx11: {
      switch (OpNum) {
      case 1:
        // op: waitvdst
        return 16;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::DS_PARAM_LOAD_gfx12: {
      switch (OpNum) {
      case 2:
        // op: attrchan
        return 8;
      case 1:
        // op: attr
        return 10;
      case 3:
        // op: waitvdst
        return 16;
      case 0:
        // op: vdst
        return 0;
      case 4:
        // op: waitvsrc
        return 23;
      }
      break;
    }
    case AMDGPU::LDS_PARAM_LOAD_gfx11: {
      switch (OpNum) {
      case 2:
        // op: attrchan
        return 8;
      case 1:
        // op: attr
        return 10;
      case 3:
        // op: waitvdst
        return 16;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::FLAT_PREFETCH_B8_gfx1250:
    case AMDGPU::GLOBAL_PREFETCH_B8_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: cpol
        return 7;
      case 0:
        // op: vaddr
        return 64;
      case 1:
        // op: offset
        return 72;
      }
      break;
    }
    case AMDGPU::GLOBAL_STORE_DWORD_ADDTID_gfx12:
    case AMDGPU::SCRATCH_STORE_BLOCK_ST_gfx12:
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_ST_gfx12:
    case AMDGPU::SCRATCH_STORE_BYTE_ST_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX2_ST_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX3_ST_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX4_ST_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORD_ST_gfx12:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_ST_gfx12:
    case AMDGPU::SCRATCH_STORE_SHORT_ST_gfx12: {
      switch (OpNum) {
      case 2:
        // op: cpol
        return 7;
      case 0:
        // op: vdata
        return 55;
      case 1:
        // op: offset
        return 72;
      }
      break;
    }
    case AMDGPU::DS_ADD_SRC2_F32_vi:
    case AMDGPU::DS_ADD_SRC2_U32_vi:
    case AMDGPU::DS_ADD_SRC2_U64_vi:
    case AMDGPU::DS_AND_SRC2_B32_vi:
    case AMDGPU::DS_AND_SRC2_B64_vi:
    case AMDGPU::DS_DEC_SRC2_U32_vi:
    case AMDGPU::DS_DEC_SRC2_U64_vi:
    case AMDGPU::DS_INC_SRC2_U32_vi:
    case AMDGPU::DS_INC_SRC2_U64_vi:
    case AMDGPU::DS_MAX_SRC2_F32_vi:
    case AMDGPU::DS_MAX_SRC2_F64_vi:
    case AMDGPU::DS_MAX_SRC2_I32_vi:
    case AMDGPU::DS_MAX_SRC2_I64_vi:
    case AMDGPU::DS_MAX_SRC2_U32_vi:
    case AMDGPU::DS_MAX_SRC2_U64_vi:
    case AMDGPU::DS_MIN_SRC2_F32_vi:
    case AMDGPU::DS_MIN_SRC2_F64_vi:
    case AMDGPU::DS_MIN_SRC2_I32_vi:
    case AMDGPU::DS_MIN_SRC2_I64_vi:
    case AMDGPU::DS_MIN_SRC2_U32_vi:
    case AMDGPU::DS_MIN_SRC2_U64_vi:
    case AMDGPU::DS_OR_SRC2_B32_vi:
    case AMDGPU::DS_OR_SRC2_B64_vi:
    case AMDGPU::DS_RSUB_SRC2_U32_vi:
    case AMDGPU::DS_RSUB_SRC2_U64_vi:
    case AMDGPU::DS_SUB_SRC2_U32_vi:
    case AMDGPU::DS_SUB_SRC2_U64_vi:
    case AMDGPU::DS_WRITE_SRC2_B32_vi:
    case AMDGPU::DS_WRITE_SRC2_B64_vi:
    case AMDGPU::DS_XOR_SRC2_B32_vi:
    case AMDGPU::DS_XOR_SRC2_B64_vi: {
      switch (OpNum) {
      case 2:
        // op: gds
        return 16;
      case 0:
        // op: addr
        return 32;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_WRITE_ADDTID_B32_vi: {
      switch (OpNum) {
      case 2:
        // op: gds
        return 16;
      case 0:
        // op: data0
        return 25;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_ADD_SRC2_F32_gfx10:
    case AMDGPU::DS_ADD_SRC2_U32_gfx10:
    case AMDGPU::DS_ADD_SRC2_U32_gfx6_gfx7:
    case AMDGPU::DS_ADD_SRC2_U64_gfx10:
    case AMDGPU::DS_ADD_SRC2_U64_gfx6_gfx7:
    case AMDGPU::DS_AND_SRC2_B32_gfx10:
    case AMDGPU::DS_AND_SRC2_B32_gfx6_gfx7:
    case AMDGPU::DS_AND_SRC2_B64_gfx10:
    case AMDGPU::DS_AND_SRC2_B64_gfx6_gfx7:
    case AMDGPU::DS_DEC_SRC2_U32_gfx10:
    case AMDGPU::DS_DEC_SRC2_U32_gfx6_gfx7:
    case AMDGPU::DS_DEC_SRC2_U64_gfx10:
    case AMDGPU::DS_DEC_SRC2_U64_gfx6_gfx7:
    case AMDGPU::DS_INC_SRC2_U32_gfx10:
    case AMDGPU::DS_INC_SRC2_U32_gfx6_gfx7:
    case AMDGPU::DS_INC_SRC2_U64_gfx10:
    case AMDGPU::DS_INC_SRC2_U64_gfx6_gfx7:
    case AMDGPU::DS_MAX_SRC2_F32_gfx10:
    case AMDGPU::DS_MAX_SRC2_F32_gfx6_gfx7:
    case AMDGPU::DS_MAX_SRC2_F64_gfx10:
    case AMDGPU::DS_MAX_SRC2_F64_gfx6_gfx7:
    case AMDGPU::DS_MAX_SRC2_I32_gfx10:
    case AMDGPU::DS_MAX_SRC2_I32_gfx6_gfx7:
    case AMDGPU::DS_MAX_SRC2_I64_gfx10:
    case AMDGPU::DS_MAX_SRC2_I64_gfx6_gfx7:
    case AMDGPU::DS_MAX_SRC2_U32_gfx10:
    case AMDGPU::DS_MAX_SRC2_U32_gfx6_gfx7:
    case AMDGPU::DS_MAX_SRC2_U64_gfx10:
    case AMDGPU::DS_MAX_SRC2_U64_gfx6_gfx7:
    case AMDGPU::DS_MIN_SRC2_F32_gfx10:
    case AMDGPU::DS_MIN_SRC2_F32_gfx6_gfx7:
    case AMDGPU::DS_MIN_SRC2_F64_gfx10:
    case AMDGPU::DS_MIN_SRC2_F64_gfx6_gfx7:
    case AMDGPU::DS_MIN_SRC2_I32_gfx10:
    case AMDGPU::DS_MIN_SRC2_I32_gfx6_gfx7:
    case AMDGPU::DS_MIN_SRC2_I64_gfx10:
    case AMDGPU::DS_MIN_SRC2_I64_gfx6_gfx7:
    case AMDGPU::DS_MIN_SRC2_U32_gfx10:
    case AMDGPU::DS_MIN_SRC2_U32_gfx6_gfx7:
    case AMDGPU::DS_MIN_SRC2_U64_gfx10:
    case AMDGPU::DS_MIN_SRC2_U64_gfx6_gfx7:
    case AMDGPU::DS_OR_SRC2_B32_gfx10:
    case AMDGPU::DS_OR_SRC2_B32_gfx6_gfx7:
    case AMDGPU::DS_OR_SRC2_B64_gfx10:
    case AMDGPU::DS_OR_SRC2_B64_gfx6_gfx7:
    case AMDGPU::DS_RSUB_SRC2_U32_gfx10:
    case AMDGPU::DS_RSUB_SRC2_U32_gfx6_gfx7:
    case AMDGPU::DS_RSUB_SRC2_U64_gfx10:
    case AMDGPU::DS_RSUB_SRC2_U64_gfx6_gfx7:
    case AMDGPU::DS_SUB_SRC2_U32_gfx10:
    case AMDGPU::DS_SUB_SRC2_U32_gfx6_gfx7:
    case AMDGPU::DS_SUB_SRC2_U64_gfx10:
    case AMDGPU::DS_SUB_SRC2_U64_gfx6_gfx7:
    case AMDGPU::DS_WRITE_SRC2_B32_gfx10:
    case AMDGPU::DS_WRITE_SRC2_B32_gfx6_gfx7:
    case AMDGPU::DS_WRITE_SRC2_B64_gfx10:
    case AMDGPU::DS_WRITE_SRC2_B64_gfx6_gfx7:
    case AMDGPU::DS_XOR_SRC2_B32_gfx10:
    case AMDGPU::DS_XOR_SRC2_B32_gfx6_gfx7:
    case AMDGPU::DS_XOR_SRC2_B64_gfx10:
    case AMDGPU::DS_XOR_SRC2_B64_gfx6_gfx7: {
      switch (OpNum) {
      case 2:
        // op: gds
        return 17;
      case 0:
        // op: addr
        return 32;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_WRITE_ADDTID_B32_gfx10:
    case AMDGPU::DS_WRITE_ADDTID_B32_gfx11: {
      switch (OpNum) {
      case 2:
        // op: gds
        return 17;
      case 0:
        // op: data0
        return 40;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::BUFFER_LOAD_DWORDX3_LDS_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX3_LDS_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_LDS_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX4_LDS_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_LDS_DWORD_gfx90a:
    case AMDGPU::BUFFER_STORE_LDS_DWORD_vi: {
      switch (OpNum) {
      case 2:
        // op: offset
        return 0;
      case 3:
        // op: cpol
        return 14;
      case 0:
        // op: srsrc
        return 48;
      case 1:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::TENSOR_LOAD_TO_LDS_D2_gfx1250:
    case AMDGPU::TENSOR_STORE_FROM_LDS_D2_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: r128
        return 4;
      case 3:
        // op: cpol
        return 7;
      case 0:
        // op: vaddr0
        return 64;
      case 1:
        // op: vaddr1
        return 72;
      }
      break;
    }
    case AMDGPU::SCRATCH_LOAD_BLOCK_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX2_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX3_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORDX4_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_DWORD_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_D16_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_SBYTE_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_SHORT_D16_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_SSHORT_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_D16_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_UBYTE_SVS_gfx12:
    case AMDGPU::SCRATCH_LOAD_USHORT_SVS_gfx12: {
      switch (OpNum) {
      case 2:
        // op: saddr
        return 0;
      case 0:
        // op: vdst
        return 32;
      case 4:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr
        return 64;
      case 3:
        // op: offset
        return 72;
      }
      break;
    }
    case AMDGPU::SCRATCH_STORE_BLOCK_SVS_gfx12:
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SVS_gfx12:
    case AMDGPU::SCRATCH_STORE_BYTE_SVS_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX2_SVS_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX3_SVS_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX4_SVS_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORD_SVS_gfx12:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SVS_gfx12:
    case AMDGPU::SCRATCH_STORE_SHORT_SVS_gfx12: {
      switch (OpNum) {
      case 2:
        // op: saddr
        return 0;
      case 4:
        // op: cpol
        return 7;
      case 0:
        // op: vdata
        return 55;
      case 1:
        // op: vaddr
        return 64;
      case 3:
        // op: offset
        return 72;
      }
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_F32_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_ADD_F64_SADDR_gfx1250:
    case AMDGPU::FLAT_ATOMIC_ADD_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_AND_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_AND_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_COND_SUB_U32_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_CSUB_U32_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_DEC_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_FMAX_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_FMIN_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_INC_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_INC_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR_gfx1250:
    case AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR_gfx1250:
    case AMDGPU::FLAT_ATOMIC_OR_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_OR_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_BF16_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_F16_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMAX_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMIN_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_SUB_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_SWAP_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMAX_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMIN_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_XOR_SADDR_gfx12:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR_gfx12:
    case AMDGPU::FLAT_STORE_BYTE_D16_HI_SADDR_gfx12:
    case AMDGPU::FLAT_STORE_BYTE_SADDR_gfx12:
    case AMDGPU::FLAT_STORE_DWORDX2_SADDR_gfx12:
    case AMDGPU::FLAT_STORE_DWORDX3_SADDR_gfx12:
    case AMDGPU::FLAT_STORE_DWORDX4_SADDR_gfx12:
    case AMDGPU::FLAT_STORE_DWORD_SADDR_gfx12:
    case AMDGPU::FLAT_STORE_SHORT_D16_HI_SADDR_gfx12:
    case AMDGPU::FLAT_STORE_SHORT_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_AND_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CSUB_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_INC_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_OR_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_gfx12:
    case AMDGPU::GLOBAL_STORE_BLOCK_SADDR_gfx12:
    case AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR_gfx12:
    case AMDGPU::GLOBAL_STORE_BYTE_SADDR_gfx12:
    case AMDGPU::GLOBAL_STORE_DWORDX2_SADDR_gfx12:
    case AMDGPU::GLOBAL_STORE_DWORDX3_SADDR_gfx12:
    case AMDGPU::GLOBAL_STORE_DWORDX4_SADDR_gfx12:
    case AMDGPU::GLOBAL_STORE_DWORD_SADDR_gfx12:
    case AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR_gfx12:
    case AMDGPU::GLOBAL_STORE_SHORT_SADDR_gfx12: {
      switch (OpNum) {
      case 2:
        // op: saddr
        return 0;
      case 4:
        // op: cpol
        return 7;
      case 1:
        // op: vdata
        return 55;
      case 0:
        // op: vaddr
        return 64;
      case 3:
        // op: offset
        return 72;
      }
      break;
    }
    case AMDGPU::S_ATOMIC_ADD_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_ADD_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_AND_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_AND_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_DEC_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_DEC_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_INC_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_INC_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_OR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_OR_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SUB_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SUB_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_X2_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_XOR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_XOR_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_IMM_RTN_gfx10: {
      switch (OpNum) {
      case 2:
        // op: sbase
        return 0;
      case 0:
        // op: sdst
        return 6;
      case 3:
        // op: offset
        return 32;
      case 4:
        // op: cpol
        return 14;
      }
      break;
    }
    case AMDGPU::S_ATOMIC_ADD_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_ADD_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_AND_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_AND_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_CMPSWAP_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_DEC_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_DEC_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_INC_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_INC_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_OR_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_OR_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_SMAX_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_SMAX_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_SMIN_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_SMIN_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_SUB_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_SUB_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_SWAP_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_SWAP_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_UMAX_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_UMAX_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_UMIN_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_UMIN_X2_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_XOR_IMM_RTN_vi:
    case AMDGPU::S_ATOMIC_XOR_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_AND_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_INC_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_OR_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_IMM_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_IMM_RTN_vi: {
      switch (OpNum) {
      case 2:
        // op: sbase
        return 0;
      case 0:
        // op: sdst
        return 6;
      case 3:
        // op: offset
        return 32;
      }
      break;
    }
    case AMDGPU::S_ATOMIC_ADD_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_ADD_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_AND_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_AND_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_CMPSWAP_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_DEC_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_DEC_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_INC_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_INC_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_OR_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_OR_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_SMAX_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_SMAX_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_SMIN_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_SMIN_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_SUB_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_SUB_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_SWAP_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_SWAP_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_UMAX_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_UMAX_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_UMIN_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_UMIN_X2_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_XOR_SGPR_RTN_vi:
    case AMDGPU::S_ATOMIC_XOR_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_RTN_vi:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_RTN_vi: {
      switch (OpNum) {
      case 2:
        // op: sbase
        return 0;
      case 0:
        // op: sdst
        return 6;
      case 3:
        // op: soffset
        return 32;
      }
      break;
    }
    case AMDGPU::S_ATOMIC_ADD_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_ADD_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_AND_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_AND_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_DEC_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_DEC_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_INC_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_INC_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_OR_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_OR_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SUB_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SUB_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_XOR_SGPR_RTN_gfx10:
    case AMDGPU::S_ATOMIC_XOR_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_RTN_gfx10: {
      switch (OpNum) {
      case 2:
        // op: sbase
        return 0;
      case 0:
        // op: sdst
        return 6;
      case 3:
        // op: soffset
        return 57;
      case 4:
        // op: cpol
        return 14;
      }
      break;
    }
    case AMDGPU::S_ATOMIC_ADD_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_ADD_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_AND_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_AND_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_CMPSWAP_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_DEC_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_DEC_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_INC_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_INC_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_OR_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_OR_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_SMAX_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_SMAX_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_SMIN_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_SMIN_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_SUB_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_SUB_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_SWAP_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_SWAP_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_UMAX_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_UMAX_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_UMIN_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_UMIN_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_XOR_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_ATOMIC_XOR_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_RTN_alt_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_RTN_alt_gfx9: {
      switch (OpNum) {
      case 2:
        // op: sbase
        return 0;
      case 0:
        // op: sdst
        return 6;
      case 3:
        // op: soffset
        return 57;
      }
      break;
    }
    case AMDGPU::S_ATOMIC_ADD_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_ADD_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_AND_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_AND_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_DEC_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_DEC_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_INC_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_INC_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_OR_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_OR_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMAX_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SMIN_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SUB_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SUB_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_SWAP_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMAX_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_UMIN_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_XOR_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_ATOMIC_XOR_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_IMM_RTN_gfx10:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_IMM_RTN_gfx10: {
      switch (OpNum) {
      case 2:
        // op: sbase
        return 0;
      case 0:
        // op: sdst
        return 6;
      case 4:
        // op: offset
        return 32;
      case 3:
        // op: soffset
        return 57;
      case 5:
        // op: cpol
        return 14;
      }
      break;
    }
    case AMDGPU::S_ATOMIC_ADD_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_ADD_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_AND_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_AND_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_CMPSWAP_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_DEC_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_DEC_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_INC_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_INC_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_OR_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_OR_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_SMAX_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_SMAX_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_SMIN_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_SMIN_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_SUB_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_SUB_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_SWAP_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_SWAP_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_UMAX_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_UMAX_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_UMIN_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_UMIN_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_XOR_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_ATOMIC_XOR_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_IMM_RTN_gfx9:
    case AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_IMM_RTN_gfx9: {
      switch (OpNum) {
      case 2:
        // op: sbase
        return 0;
      case 0:
        // op: sdst
        return 6;
      case 4:
        // op: offset
        return 32;
      case 3:
        // op: soffset
        return 57;
      }
      break;
    }
    case AMDGPU::V_FMAC_F32_sdwa_vi:
    case AMDGPU::V_MAC_F16_sdwa_vi:
    case AMDGPU::V_MAC_F32_sdwa_vi: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 10:
        // op: src0_sel
        return 48;
      case 1:
        // op: src0_modifiers
        return 52;
      case 11:
        // op: src1_sel
        return 56;
      case 3:
        // op: src1_modifiers
        return 60;
      case 8:
        // op: dst_sel
        return 40;
      case 9:
        // op: dst_unused
        return 43;
      case 6:
        // op: clamp
        return 45;
      case 0:
        // op: vdst
        return 17;
      case 4:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_BFREV_B32_dpp8_gfx10:
    case AMDGPU::V_BFREV_B32_dpp8_gfx11:
    case AMDGPU::V_BFREV_B32_dpp8_gfx12:
    case AMDGPU::V_CLS_I32_dpp8_gfx11:
    case AMDGPU::V_CLS_I32_dpp8_gfx12:
    case AMDGPU::V_CLZ_I32_U32_dpp8_gfx11:
    case AMDGPU::V_CLZ_I32_U32_dpp8_gfx12:
    case AMDGPU::V_CTZ_I32_B32_dpp8_gfx11:
    case AMDGPU::V_CTZ_I32_B32_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_I16_dpp8_gfx10:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_U16_dpp8_gfx10:
    case AMDGPU::V_CVT_F32_BF8_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_FP8_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_FP8_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_FP8_dpp8_gfx1250:
    case AMDGPU::V_CVT_F32_I32_dpp8_gfx10:
    case AMDGPU::V_CVT_F32_I32_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_I32_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_U32_dpp8_gfx10:
    case AMDGPU::V_CVT_F32_U32_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_U32_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE0_dpp8_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE0_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE0_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE1_dpp8_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE1_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE1_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE2_dpp8_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE2_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE2_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE3_dpp8_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE3_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE3_dpp8_gfx12:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_dpp8_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_dpp8_gfx12:
    case AMDGPU::V_CVT_OFF_F32_I4_dpp8_gfx10:
    case AMDGPU::V_CVT_OFF_F32_I4_dpp8_gfx11:
    case AMDGPU::V_CVT_OFF_F32_I4_dpp8_gfx12:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_dpp8_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_dpp8_gfx12:
    case AMDGPU::V_FFBH_I32_dpp8_gfx10:
    case AMDGPU::V_FFBH_U32_dpp8_gfx10:
    case AMDGPU::V_FFBL_B32_dpp8_gfx10:
    case AMDGPU::V_MOVRELD_B32_dpp8_gfx10:
    case AMDGPU::V_MOVRELD_B32_dpp8_gfx11:
    case AMDGPU::V_MOVRELD_B32_dpp8_gfx12:
    case AMDGPU::V_MOVRELSD_2_B32_dpp8_gfx10:
    case AMDGPU::V_MOVRELSD_2_B32_dpp8_gfx11:
    case AMDGPU::V_MOVRELSD_2_B32_dpp8_gfx12:
    case AMDGPU::V_MOVRELSD_B32_dpp8_gfx10:
    case AMDGPU::V_MOVRELSD_B32_dpp8_gfx11:
    case AMDGPU::V_MOVRELSD_B32_dpp8_gfx12:
    case AMDGPU::V_MOVRELS_B32_dpp8_gfx10:
    case AMDGPU::V_MOVRELS_B32_dpp8_gfx11:
    case AMDGPU::V_MOVRELS_B32_dpp8_gfx12:
    case AMDGPU::V_MOV_B32_dpp8_gfx10:
    case AMDGPU::V_MOV_B32_dpp8_gfx11:
    case AMDGPU::V_MOV_B32_dpp8_gfx12:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_dpp8_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_dpp8_gfx12:
    case AMDGPU::V_NOT_B32_dpp8_gfx10:
    case AMDGPU::V_NOT_B32_dpp8_gfx11:
    case AMDGPU::V_NOT_B32_dpp8_gfx12:
    case AMDGPU::V_PRNG_B32_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_fake16_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_fake16_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_dpp8_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_dpp8_gfx12:
    case AMDGPU::V_SAT_PK_U8_I16_dpp8_gfx10: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: dpp8
        return 40;
      case 4:
        // op: fi
        return 0;
      case 0:
        // op: vdst
        return 17;
      }
      break;
    }
    case AMDGPU::V_BFREV_B32_dpp_vi:
    case AMDGPU::V_CVT_F16_I16_dpp_vi:
    case AMDGPU::V_CVT_F16_U16_dpp_vi:
    case AMDGPU::V_CVT_F32_BF8_dpp_gfx9:
    case AMDGPU::V_CVT_F32_FP8_dpp_gfx9:
    case AMDGPU::V_CVT_F32_I32_dpp_vi:
    case AMDGPU::V_CVT_F32_U32_dpp_vi:
    case AMDGPU::V_CVT_F32_UBYTE0_dpp_vi:
    case AMDGPU::V_CVT_F32_UBYTE1_dpp_vi:
    case AMDGPU::V_CVT_F32_UBYTE2_dpp_vi:
    case AMDGPU::V_CVT_F32_UBYTE3_dpp_vi:
    case AMDGPU::V_CVT_F64_I32_dpp_vi:
    case AMDGPU::V_CVT_F64_U32_dpp_vi:
    case AMDGPU::V_CVT_OFF_F32_I4_dpp_vi:
    case AMDGPU::V_CVT_PK_F32_BF8_dpp_gfx9:
    case AMDGPU::V_CVT_PK_F32_FP8_dpp_gfx9:
    case AMDGPU::V_FFBH_I32_dpp_vi:
    case AMDGPU::V_FFBH_U32_dpp_vi:
    case AMDGPU::V_FFBL_B32_dpp_vi:
    case AMDGPU::V_MOV_B32_dpp_vi:
    case AMDGPU::V_MOV_B64_dpp_gfx9:
    case AMDGPU::V_NOT_B32_dpp_vi:
    case AMDGPU::V_PRNG_B32_dpp_gfx9:
    case AMDGPU::V_SAT_PK_U8_I16_dpp_vi:
    case AMDGPU::V_SCREEN_PARTITION_4SE_B32_dpp_gfx9: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: dpp_ctrl
        return 40;
      case 6:
        // op: bound_ctrl
        return 51;
      case 5:
        // op: bank_mask
        return 56;
      case 4:
        // op: row_mask
        return 60;
      case 0:
        // op: vdst
        return 17;
      }
      break;
    }
    case AMDGPU::V_BFREV_B32_dpp_gfx10:
    case AMDGPU::V_BFREV_B32_dpp_gfx11:
    case AMDGPU::V_BFREV_B32_dpp_gfx12:
    case AMDGPU::V_CLS_I32_dpp_gfx11:
    case AMDGPU::V_CLS_I32_dpp_gfx12:
    case AMDGPU::V_CLZ_I32_U32_dpp_gfx11:
    case AMDGPU::V_CLZ_I32_U32_dpp_gfx12:
    case AMDGPU::V_CTZ_I32_B32_dpp_gfx11:
    case AMDGPU::V_CTZ_I32_B32_dpp_gfx12:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_dpp_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_dpp_gfx12:
    case AMDGPU::V_CVT_F16_I16_dpp_gfx10:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_dpp_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_dpp_gfx12:
    case AMDGPU::V_CVT_F16_U16_dpp_gfx10:
    case AMDGPU::V_CVT_F32_BF8_dpp_gfx12:
    case AMDGPU::V_CVT_F32_FP8_dpp_gfx11:
    case AMDGPU::V_CVT_F32_FP8_dpp_gfx12:
    case AMDGPU::V_CVT_F32_FP8_dpp_gfx1250:
    case AMDGPU::V_CVT_F32_I32_dpp_gfx10:
    case AMDGPU::V_CVT_F32_I32_dpp_gfx11:
    case AMDGPU::V_CVT_F32_I32_dpp_gfx12:
    case AMDGPU::V_CVT_F32_U32_dpp_gfx10:
    case AMDGPU::V_CVT_F32_U32_dpp_gfx11:
    case AMDGPU::V_CVT_F32_U32_dpp_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE0_dpp_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE0_dpp_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE0_dpp_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE1_dpp_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE1_dpp_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE1_dpp_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE2_dpp_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE2_dpp_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE2_dpp_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE3_dpp_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE3_dpp_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE3_dpp_gfx12:
    case AMDGPU::V_CVT_F64_I32_dpp_gfx12:
    case AMDGPU::V_CVT_F64_U32_dpp_gfx12:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_dpp_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_fake16_dpp_gfx12:
    case AMDGPU::V_CVT_OFF_F32_I4_dpp_gfx10:
    case AMDGPU::V_CVT_OFF_F32_I4_dpp_gfx11:
    case AMDGPU::V_CVT_OFF_F32_I4_dpp_gfx12:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_dpp_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_fake16_dpp_gfx12:
    case AMDGPU::V_FFBH_I32_dpp_gfx10:
    case AMDGPU::V_FFBH_U32_dpp_gfx10:
    case AMDGPU::V_FFBL_B32_dpp_gfx10:
    case AMDGPU::V_MOVRELD_B32_dpp_gfx10:
    case AMDGPU::V_MOVRELD_B32_dpp_gfx11:
    case AMDGPU::V_MOVRELD_B32_dpp_gfx12:
    case AMDGPU::V_MOVRELSD_2_B32_dpp_gfx10:
    case AMDGPU::V_MOVRELSD_2_B32_dpp_gfx11:
    case AMDGPU::V_MOVRELSD_2_B32_dpp_gfx12:
    case AMDGPU::V_MOVRELSD_B32_dpp_gfx10:
    case AMDGPU::V_MOVRELSD_B32_dpp_gfx11:
    case AMDGPU::V_MOVRELSD_B32_dpp_gfx12:
    case AMDGPU::V_MOVRELS_B32_dpp_gfx10:
    case AMDGPU::V_MOVRELS_B32_dpp_gfx11:
    case AMDGPU::V_MOVRELS_B32_dpp_gfx12:
    case AMDGPU::V_MOV_B32_dpp_gfx10:
    case AMDGPU::V_MOV_B32_dpp_gfx11:
    case AMDGPU::V_MOV_B32_dpp_gfx12:
    case AMDGPU::V_MOV_B64_dpp_gfx1250:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_dpp_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_fake16_dpp_gfx12:
    case AMDGPU::V_NOT_B32_dpp_gfx10:
    case AMDGPU::V_NOT_B32_dpp_gfx11:
    case AMDGPU::V_NOT_B32_dpp_gfx12:
    case AMDGPU::V_PRNG_B32_dpp_gfx1250:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_fake16_dpp_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_fake16_dpp_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_dpp_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_fake16_dpp_gfx12:
    case AMDGPU::V_SAT_PK_U8_I16_dpp_gfx10: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 3:
        // op: dpp_ctrl
        return 40;
      case 6:
        // op: bound_ctrl
        return 51;
      case 5:
        // op: bank_mask
        return 56;
      case 4:
        // op: row_mask
        return 60;
      case 7:
        // op: fi
        return 50;
      case 0:
        // op: vdst
        return 17;
      }
      break;
    }
    case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
    case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
    case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx12:
    case AMDGPU::V_ADD_CO_CI_U32_dpp8_w32_gfx10:
    case AMDGPU::V_ADD_CO_CI_U32_dpp8_w32_gfx11:
    case AMDGPU::V_ADD_CO_CI_U32_dpp8_w32_gfx12:
    case AMDGPU::V_ADD_CO_CI_U32_dpp8_w64_gfx10:
    case AMDGPU::V_ADD_CO_CI_U32_dpp8_w64_gfx11:
    case AMDGPU::V_ADD_CO_CI_U32_dpp8_w64_gfx12:
    case AMDGPU::V_ADD_NC_U32_dpp8_gfx10:
    case AMDGPU::V_ADD_NC_U32_dpp8_gfx11:
    case AMDGPU::V_ADD_NC_U32_dpp8_gfx12:
    case AMDGPU::V_AND_B32_dpp8_gfx10:
    case AMDGPU::V_AND_B32_dpp8_gfx11:
    case AMDGPU::V_AND_B32_dpp8_gfx12:
    case AMDGPU::V_ASHRREV_I32_dpp8_gfx10:
    case AMDGPU::V_ASHRREV_I32_dpp8_gfx11:
    case AMDGPU::V_ASHRREV_I32_dpp8_gfx12:
    case AMDGPU::V_LSHLREV_B32_dpp8_gfx10:
    case AMDGPU::V_LSHLREV_B32_dpp8_gfx11:
    case AMDGPU::V_LSHLREV_B32_dpp8_gfx12:
    case AMDGPU::V_LSHRREV_B32_dpp8_gfx10:
    case AMDGPU::V_LSHRREV_B32_dpp8_gfx11:
    case AMDGPU::V_LSHRREV_B32_dpp8_gfx12:
    case AMDGPU::V_MAX_I32_dpp8_gfx10:
    case AMDGPU::V_MAX_I32_dpp8_gfx11:
    case AMDGPU::V_MAX_I32_dpp8_gfx12:
    case AMDGPU::V_MAX_U32_dpp8_gfx10:
    case AMDGPU::V_MAX_U32_dpp8_gfx11:
    case AMDGPU::V_MAX_U32_dpp8_gfx12:
    case AMDGPU::V_MIN_I32_dpp8_gfx10:
    case AMDGPU::V_MIN_I32_dpp8_gfx11:
    case AMDGPU::V_MIN_I32_dpp8_gfx12:
    case AMDGPU::V_MIN_U32_dpp8_gfx10:
    case AMDGPU::V_MIN_U32_dpp8_gfx11:
    case AMDGPU::V_MIN_U32_dpp8_gfx12:
    case AMDGPU::V_MUL_HI_I32_I24_dpp8_gfx10:
    case AMDGPU::V_MUL_HI_I32_I24_dpp8_gfx11:
    case AMDGPU::V_MUL_HI_I32_I24_dpp8_gfx12:
    case AMDGPU::V_MUL_HI_U32_U24_dpp8_gfx10:
    case AMDGPU::V_MUL_HI_U32_U24_dpp8_gfx11:
    case AMDGPU::V_MUL_HI_U32_U24_dpp8_gfx12:
    case AMDGPU::V_MUL_I32_I24_dpp8_gfx10:
    case AMDGPU::V_MUL_I32_I24_dpp8_gfx11:
    case AMDGPU::V_MUL_I32_I24_dpp8_gfx12:
    case AMDGPU::V_MUL_U32_U24_dpp8_gfx10:
    case AMDGPU::V_MUL_U32_U24_dpp8_gfx11:
    case AMDGPU::V_MUL_U32_U24_dpp8_gfx12:
    case AMDGPU::V_OR_B32_dpp8_gfx10:
    case AMDGPU::V_OR_B32_dpp8_gfx11:
    case AMDGPU::V_OR_B32_dpp8_gfx12:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx12:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_w32_gfx10:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_w32_gfx11:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_w32_gfx12:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_w64_gfx10:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_w64_gfx11:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_w64_gfx12:
    case AMDGPU::V_SUBREV_NC_U32_dpp8_gfx10:
    case AMDGPU::V_SUBREV_NC_U32_dpp8_gfx11:
    case AMDGPU::V_SUBREV_NC_U32_dpp8_gfx12:
    case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
    case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
    case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx12:
    case AMDGPU::V_SUB_CO_CI_U32_dpp8_w32_gfx10:
    case AMDGPU::V_SUB_CO_CI_U32_dpp8_w32_gfx11:
    case AMDGPU::V_SUB_CO_CI_U32_dpp8_w32_gfx12:
    case AMDGPU::V_SUB_CO_CI_U32_dpp8_w64_gfx10:
    case AMDGPU::V_SUB_CO_CI_U32_dpp8_w64_gfx11:
    case AMDGPU::V_SUB_CO_CI_U32_dpp8_w64_gfx12:
    case AMDGPU::V_SUB_NC_U32_dpp8_gfx10:
    case AMDGPU::V_SUB_NC_U32_dpp8_gfx11:
    case AMDGPU::V_SUB_NC_U32_dpp8_gfx12:
    case AMDGPU::V_XNOR_B32_dpp8_gfx10:
    case AMDGPU::V_XNOR_B32_dpp8_gfx11:
    case AMDGPU::V_XNOR_B32_dpp8_gfx12:
    case AMDGPU::V_XOR_B32_dpp8_gfx10:
    case AMDGPU::V_XOR_B32_dpp8_gfx11:
    case AMDGPU::V_XOR_B32_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 4:
        // op: dpp8
        return 40;
      case 5:
        // op: fi
        return 0;
      case 0:
        // op: vdst
        return 17;
      case 3:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_ADDC_CO_U32_dpp_gfx9:
    case AMDGPU::V_ADDC_U32_dpp_vi:
    case AMDGPU::V_ADD_CO_U32_dpp_gfx9:
    case AMDGPU::V_ADD_U16_dpp_vi:
    case AMDGPU::V_ADD_U32_dpp_gfx9:
    case AMDGPU::V_ADD_U32_dpp_vi:
    case AMDGPU::V_AND_B32_dpp_vi:
    case AMDGPU::V_ASHRREV_I16_dpp_vi:
    case AMDGPU::V_ASHRREV_I32_dpp_vi:
    case AMDGPU::V_LSHLREV_B16_dpp_vi:
    case AMDGPU::V_LSHLREV_B32_dpp_vi:
    case AMDGPU::V_LSHRREV_B16_dpp_vi:
    case AMDGPU::V_LSHRREV_B32_dpp_vi:
    case AMDGPU::V_MAX_I16_dpp_vi:
    case AMDGPU::V_MAX_I32_dpp_vi:
    case AMDGPU::V_MAX_U16_dpp_vi:
    case AMDGPU::V_MAX_U32_dpp_vi:
    case AMDGPU::V_MIN_I16_dpp_vi:
    case AMDGPU::V_MIN_I32_dpp_vi:
    case AMDGPU::V_MIN_U16_dpp_vi:
    case AMDGPU::V_MIN_U32_dpp_vi:
    case AMDGPU::V_MUL_HI_I32_I24_dpp_vi:
    case AMDGPU::V_MUL_HI_U32_U24_dpp_vi:
    case AMDGPU::V_MUL_I32_I24_dpp_vi:
    case AMDGPU::V_MUL_LO_U16_dpp_vi:
    case AMDGPU::V_MUL_U32_U24_dpp_vi:
    case AMDGPU::V_OR_B32_dpp_vi:
    case AMDGPU::V_SUBBREV_CO_U32_dpp_gfx9:
    case AMDGPU::V_SUBBREV_U32_dpp_vi:
    case AMDGPU::V_SUBB_CO_U32_dpp_gfx9:
    case AMDGPU::V_SUBB_U32_dpp_vi:
    case AMDGPU::V_SUBREV_CO_U32_dpp_gfx9:
    case AMDGPU::V_SUBREV_U16_dpp_vi:
    case AMDGPU::V_SUBREV_U32_dpp_gfx9:
    case AMDGPU::V_SUBREV_U32_dpp_vi:
    case AMDGPU::V_SUB_CO_U32_dpp_gfx9:
    case AMDGPU::V_SUB_U16_dpp_vi:
    case AMDGPU::V_SUB_U32_dpp_gfx9:
    case AMDGPU::V_SUB_U32_dpp_vi:
    case AMDGPU::V_XNOR_B32_dpp_vi:
    case AMDGPU::V_XOR_B32_dpp_vi: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 4:
        // op: dpp_ctrl
        return 40;
      case 7:
        // op: bound_ctrl
        return 51;
      case 6:
        // op: bank_mask
        return 56;
      case 5:
        // op: row_mask
        return 60;
      case 0:
        // op: vdst
        return 17;
      case 3:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
    case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
    case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx12:
    case AMDGPU::V_ADD_CO_CI_U32_dpp_w32_gfx10:
    case AMDGPU::V_ADD_CO_CI_U32_dpp_w32_gfx11:
    case AMDGPU::V_ADD_CO_CI_U32_dpp_w32_gfx12:
    case AMDGPU::V_ADD_CO_CI_U32_dpp_w64_gfx10:
    case AMDGPU::V_ADD_CO_CI_U32_dpp_w64_gfx11:
    case AMDGPU::V_ADD_CO_CI_U32_dpp_w64_gfx12:
    case AMDGPU::V_ADD_NC_U32_dpp_gfx10:
    case AMDGPU::V_ADD_NC_U32_dpp_gfx11:
    case AMDGPU::V_ADD_NC_U32_dpp_gfx12:
    case AMDGPU::V_ADD_U64_dpp_gfx1250:
    case AMDGPU::V_AND_B32_dpp_gfx10:
    case AMDGPU::V_AND_B32_dpp_gfx11:
    case AMDGPU::V_AND_B32_dpp_gfx12:
    case AMDGPU::V_ASHRREV_I32_dpp_gfx10:
    case AMDGPU::V_ASHRREV_I32_dpp_gfx11:
    case AMDGPU::V_ASHRREV_I32_dpp_gfx12:
    case AMDGPU::V_LSHLREV_B32_dpp_gfx10:
    case AMDGPU::V_LSHLREV_B32_dpp_gfx11:
    case AMDGPU::V_LSHLREV_B32_dpp_gfx12:
    case AMDGPU::V_LSHLREV_B64_dpp_gfx12:
    case AMDGPU::V_LSHRREV_B32_dpp_gfx10:
    case AMDGPU::V_LSHRREV_B32_dpp_gfx11:
    case AMDGPU::V_LSHRREV_B32_dpp_gfx12:
    case AMDGPU::V_MAX_I32_dpp_gfx10:
    case AMDGPU::V_MAX_I32_dpp_gfx11:
    case AMDGPU::V_MAX_I32_dpp_gfx12:
    case AMDGPU::V_MAX_U32_dpp_gfx10:
    case AMDGPU::V_MAX_U32_dpp_gfx11:
    case AMDGPU::V_MAX_U32_dpp_gfx12:
    case AMDGPU::V_MIN_I32_dpp_gfx10:
    case AMDGPU::V_MIN_I32_dpp_gfx11:
    case AMDGPU::V_MIN_I32_dpp_gfx12:
    case AMDGPU::V_MIN_U32_dpp_gfx10:
    case AMDGPU::V_MIN_U32_dpp_gfx11:
    case AMDGPU::V_MIN_U32_dpp_gfx12:
    case AMDGPU::V_MUL_HI_I32_I24_dpp_gfx10:
    case AMDGPU::V_MUL_HI_I32_I24_dpp_gfx11:
    case AMDGPU::V_MUL_HI_I32_I24_dpp_gfx12:
    case AMDGPU::V_MUL_HI_U32_U24_dpp_gfx10:
    case AMDGPU::V_MUL_HI_U32_U24_dpp_gfx11:
    case AMDGPU::V_MUL_HI_U32_U24_dpp_gfx12:
    case AMDGPU::V_MUL_I32_I24_dpp_gfx10:
    case AMDGPU::V_MUL_I32_I24_dpp_gfx11:
    case AMDGPU::V_MUL_I32_I24_dpp_gfx12:
    case AMDGPU::V_MUL_U32_U24_dpp_gfx10:
    case AMDGPU::V_MUL_U32_U24_dpp_gfx11:
    case AMDGPU::V_MUL_U32_U24_dpp_gfx12:
    case AMDGPU::V_OR_B32_dpp_gfx10:
    case AMDGPU::V_OR_B32_dpp_gfx11:
    case AMDGPU::V_OR_B32_dpp_gfx12:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx12:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp_w32_gfx10:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp_w32_gfx11:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp_w32_gfx12:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp_w64_gfx10:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp_w64_gfx11:
    case AMDGPU::V_SUBREV_CO_CI_U32_dpp_w64_gfx12:
    case AMDGPU::V_SUBREV_NC_U32_dpp_gfx10:
    case AMDGPU::V_SUBREV_NC_U32_dpp_gfx11:
    case AMDGPU::V_SUBREV_NC_U32_dpp_gfx12:
    case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
    case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
    case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx12:
    case AMDGPU::V_SUB_CO_CI_U32_dpp_w32_gfx10:
    case AMDGPU::V_SUB_CO_CI_U32_dpp_w32_gfx11:
    case AMDGPU::V_SUB_CO_CI_U32_dpp_w32_gfx12:
    case AMDGPU::V_SUB_CO_CI_U32_dpp_w64_gfx10:
    case AMDGPU::V_SUB_CO_CI_U32_dpp_w64_gfx11:
    case AMDGPU::V_SUB_CO_CI_U32_dpp_w64_gfx12:
    case AMDGPU::V_SUB_NC_U32_dpp_gfx10:
    case AMDGPU::V_SUB_NC_U32_dpp_gfx11:
    case AMDGPU::V_SUB_NC_U32_dpp_gfx12:
    case AMDGPU::V_SUB_U64_dpp_gfx1250:
    case AMDGPU::V_XNOR_B32_dpp_gfx10:
    case AMDGPU::V_XNOR_B32_dpp_gfx11:
    case AMDGPU::V_XNOR_B32_dpp_gfx12:
    case AMDGPU::V_XOR_B32_dpp_gfx10:
    case AMDGPU::V_XOR_B32_dpp_gfx11:
    case AMDGPU::V_XOR_B32_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 4:
        // op: dpp_ctrl
        return 40;
      case 7:
        // op: bound_ctrl
        return 51;
      case 6:
        // op: bank_mask
        return 56;
      case 5:
        // op: row_mask
        return 60;
      case 8:
        // op: fi
        return 50;
      case 0:
        // op: vdst
        return 17;
      case 3:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_CVT_F32_BF8_sdwa_gfx9:
    case AMDGPU::V_CVT_F32_FP8_sdwa_gfx9:
    case AMDGPU::V_CVT_PK_F32_BF8_sdwa_gfx9:
    case AMDGPU::V_CVT_PK_F32_FP8_sdwa_gfx9: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 5:
        // op: src0_sel
        return 48;
      case 1:
        // op: src0_modifiers
        return 51;
      case 3:
        // op: clamp
        return 45;
      case 4:
        // op: omod
        return 46;
      case 0:
        // op: vdst
        return 17;
      }
      break;
    }
    case AMDGPU::V_DOT2ACC_F32_F16_dpp8_gfx11:
    case AMDGPU::V_DOT2C_F32_F16_dpp8_gfx10:
    case AMDGPU::V_DOT4C_I32_I8_dpp8_gfx10:
    case AMDGPU::V_DOT8C_I32_I4_dpp8_gfx10:
    case AMDGPU::V_FMAC_F16_dpp8_gfx10:
    case AMDGPU::V_FMAC_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_FMAC_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_FMAC_F16_t16_dpp8_gfx11:
    case AMDGPU::V_FMAC_F16_t16_dpp8_gfx12:
    case AMDGPU::V_FMAC_F32_dpp8_gfx10:
    case AMDGPU::V_FMAC_F32_dpp8_gfx11:
    case AMDGPU::V_FMAC_F32_dpp8_gfx12:
    case AMDGPU::V_MAC_F32_dpp8_gfx10: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 6:
        // op: dpp8
        return 40;
      case 7:
        // op: fi
        return 0;
      case 0:
        // op: vdst
        return 17;
      case 4:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_BFREV_B32_sdwa_gfx10:
    case AMDGPU::V_BFREV_B32_sdwa_gfx9:
    case AMDGPU::V_BFREV_B32_sdwa_vi:
    case AMDGPU::V_FFBH_I32_sdwa_gfx10:
    case AMDGPU::V_FFBH_I32_sdwa_gfx9:
    case AMDGPU::V_FFBH_I32_sdwa_vi:
    case AMDGPU::V_FFBH_U32_sdwa_gfx10:
    case AMDGPU::V_FFBH_U32_sdwa_gfx9:
    case AMDGPU::V_FFBH_U32_sdwa_vi:
    case AMDGPU::V_FFBL_B32_sdwa_gfx10:
    case AMDGPU::V_FFBL_B32_sdwa_gfx9:
    case AMDGPU::V_FFBL_B32_sdwa_vi:
    case AMDGPU::V_MOVRELD_B32_sdwa_gfx10:
    case AMDGPU::V_MOVRELSD_2_B32_sdwa_gfx10:
    case AMDGPU::V_MOVRELSD_B32_sdwa_gfx10:
    case AMDGPU::V_MOVRELS_B32_sdwa_gfx10:
    case AMDGPU::V_MOV_B32_sdwa_gfx10:
    case AMDGPU::V_MOV_B32_sdwa_gfx9:
    case AMDGPU::V_MOV_B32_sdwa_vi:
    case AMDGPU::V_NOT_B32_sdwa_gfx10:
    case AMDGPU::V_NOT_B32_sdwa_gfx9:
    case AMDGPU::V_NOT_B32_sdwa_vi:
    case AMDGPU::V_PRNG_B32_sdwa_gfx9:
    case AMDGPU::V_SAT_PK_U8_I16_sdwa_gfx10:
    case AMDGPU::V_SAT_PK_U8_I16_sdwa_gfx9:
    case AMDGPU::V_SAT_PK_U8_I16_sdwa_vi:
    case AMDGPU::V_SCREEN_PARTITION_4SE_B32_sdwa_gfx9: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 6:
        // op: src0_sel
        return 48;
      case 1:
        // op: src0_modifiers
        return 51;
      case 4:
        // op: dst_sel
        return 40;
      case 5:
        // op: dst_unused
        return 43;
      case 3:
        // op: clamp
        return 45;
      case 0:
        // op: vdst
        return 17;
      }
      break;
    }
    case AMDGPU::V_CMPX_EQ_I16_sdwa_gfx9:
    case AMDGPU::V_CMPX_EQ_I32_sdwa_gfx9:
    case AMDGPU::V_CMPX_EQ_U16_sdwa_gfx9:
    case AMDGPU::V_CMPX_EQ_U32_sdwa_gfx9:
    case AMDGPU::V_CMPX_F_I16_sdwa_gfx9:
    case AMDGPU::V_CMPX_F_I32_sdwa_gfx9:
    case AMDGPU::V_CMPX_F_U16_sdwa_gfx9:
    case AMDGPU::V_CMPX_F_U32_sdwa_gfx9:
    case AMDGPU::V_CMPX_GE_I16_sdwa_gfx9:
    case AMDGPU::V_CMPX_GE_I32_sdwa_gfx9:
    case AMDGPU::V_CMPX_GE_U16_sdwa_gfx9:
    case AMDGPU::V_CMPX_GE_U32_sdwa_gfx9:
    case AMDGPU::V_CMPX_GT_I16_sdwa_gfx9:
    case AMDGPU::V_CMPX_GT_I32_sdwa_gfx9:
    case AMDGPU::V_CMPX_GT_U16_sdwa_gfx9:
    case AMDGPU::V_CMPX_GT_U32_sdwa_gfx9:
    case AMDGPU::V_CMPX_LE_I16_sdwa_gfx9:
    case AMDGPU::V_CMPX_LE_I32_sdwa_gfx9:
    case AMDGPU::V_CMPX_LE_U16_sdwa_gfx9:
    case AMDGPU::V_CMPX_LE_U32_sdwa_gfx9:
    case AMDGPU::V_CMPX_LT_I16_sdwa_gfx9:
    case AMDGPU::V_CMPX_LT_I32_sdwa_gfx9:
    case AMDGPU::V_CMPX_LT_U16_sdwa_gfx9:
    case AMDGPU::V_CMPX_LT_U32_sdwa_gfx9:
    case AMDGPU::V_CMPX_NE_I16_sdwa_gfx9:
    case AMDGPU::V_CMPX_NE_I32_sdwa_gfx9:
    case AMDGPU::V_CMPX_NE_U16_sdwa_gfx9:
    case AMDGPU::V_CMPX_NE_U32_sdwa_gfx9:
    case AMDGPU::V_CMPX_T_I16_sdwa_gfx9:
    case AMDGPU::V_CMPX_T_I32_sdwa_gfx9:
    case AMDGPU::V_CMPX_T_U16_sdwa_gfx9:
    case AMDGPU::V_CMPX_T_U32_sdwa_gfx9:
    case AMDGPU::V_CMP_EQ_I16_sdwa_gfx10:
    case AMDGPU::V_CMP_EQ_I16_sdwa_gfx9:
    case AMDGPU::V_CMP_EQ_I32_sdwa_gfx10:
    case AMDGPU::V_CMP_EQ_I32_sdwa_gfx9:
    case AMDGPU::V_CMP_EQ_U16_sdwa_gfx10:
    case AMDGPU::V_CMP_EQ_U16_sdwa_gfx9:
    case AMDGPU::V_CMP_EQ_U32_sdwa_gfx10:
    case AMDGPU::V_CMP_EQ_U32_sdwa_gfx9:
    case AMDGPU::V_CMP_F_I16_sdwa_gfx9:
    case AMDGPU::V_CMP_F_I32_sdwa_gfx10:
    case AMDGPU::V_CMP_F_I32_sdwa_gfx9:
    case AMDGPU::V_CMP_F_U16_sdwa_gfx9:
    case AMDGPU::V_CMP_F_U32_sdwa_gfx10:
    case AMDGPU::V_CMP_F_U32_sdwa_gfx9:
    case AMDGPU::V_CMP_GE_I16_sdwa_gfx10:
    case AMDGPU::V_CMP_GE_I16_sdwa_gfx9:
    case AMDGPU::V_CMP_GE_I32_sdwa_gfx10:
    case AMDGPU::V_CMP_GE_I32_sdwa_gfx9:
    case AMDGPU::V_CMP_GE_U16_sdwa_gfx10:
    case AMDGPU::V_CMP_GE_U16_sdwa_gfx9:
    case AMDGPU::V_CMP_GE_U32_sdwa_gfx10:
    case AMDGPU::V_CMP_GE_U32_sdwa_gfx9:
    case AMDGPU::V_CMP_GT_I16_sdwa_gfx10:
    case AMDGPU::V_CMP_GT_I16_sdwa_gfx9:
    case AMDGPU::V_CMP_GT_I32_sdwa_gfx10:
    case AMDGPU::V_CMP_GT_I32_sdwa_gfx9:
    case AMDGPU::V_CMP_GT_U16_sdwa_gfx10:
    case AMDGPU::V_CMP_GT_U16_sdwa_gfx9:
    case AMDGPU::V_CMP_GT_U32_sdwa_gfx10:
    case AMDGPU::V_CMP_GT_U32_sdwa_gfx9:
    case AMDGPU::V_CMP_LE_I16_sdwa_gfx10:
    case AMDGPU::V_CMP_LE_I16_sdwa_gfx9:
    case AMDGPU::V_CMP_LE_I32_sdwa_gfx10:
    case AMDGPU::V_CMP_LE_I32_sdwa_gfx9:
    case AMDGPU::V_CMP_LE_U16_sdwa_gfx10:
    case AMDGPU::V_CMP_LE_U16_sdwa_gfx9:
    case AMDGPU::V_CMP_LE_U32_sdwa_gfx10:
    case AMDGPU::V_CMP_LE_U32_sdwa_gfx9:
    case AMDGPU::V_CMP_LT_I16_sdwa_gfx10:
    case AMDGPU::V_CMP_LT_I16_sdwa_gfx9:
    case AMDGPU::V_CMP_LT_I32_sdwa_gfx10:
    case AMDGPU::V_CMP_LT_I32_sdwa_gfx9:
    case AMDGPU::V_CMP_LT_U16_sdwa_gfx10:
    case AMDGPU::V_CMP_LT_U16_sdwa_gfx9:
    case AMDGPU::V_CMP_LT_U32_sdwa_gfx10:
    case AMDGPU::V_CMP_LT_U32_sdwa_gfx9:
    case AMDGPU::V_CMP_NE_I16_sdwa_gfx10:
    case AMDGPU::V_CMP_NE_I16_sdwa_gfx9:
    case AMDGPU::V_CMP_NE_I32_sdwa_gfx10:
    case AMDGPU::V_CMP_NE_I32_sdwa_gfx9:
    case AMDGPU::V_CMP_NE_U16_sdwa_gfx10:
    case AMDGPU::V_CMP_NE_U16_sdwa_gfx9:
    case AMDGPU::V_CMP_NE_U32_sdwa_gfx10:
    case AMDGPU::V_CMP_NE_U32_sdwa_gfx9:
    case AMDGPU::V_CMP_T_I16_sdwa_gfx9:
    case AMDGPU::V_CMP_T_I32_sdwa_gfx10:
    case AMDGPU::V_CMP_T_I32_sdwa_gfx9:
    case AMDGPU::V_CMP_T_U16_sdwa_gfx9:
    case AMDGPU::V_CMP_T_U32_sdwa_gfx10:
    case AMDGPU::V_CMP_T_U32_sdwa_gfx9: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 6:
        // op: src0_sel
        return 48;
      case 1:
        // op: src0_modifiers
        return 51;
      case 7:
        // op: src1_sel
        return 56;
      case 3:
        // op: src1_modifiers
        return 59;
      case 0:
        // op: sdst
        return 40;
      case 4:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_CMPX_EQ_I16_sdwa_vi:
    case AMDGPU::V_CMPX_EQ_I32_sdwa_vi:
    case AMDGPU::V_CMPX_EQ_U16_sdwa_vi:
    case AMDGPU::V_CMPX_EQ_U32_sdwa_vi:
    case AMDGPU::V_CMPX_F_I16_sdwa_vi:
    case AMDGPU::V_CMPX_F_I32_sdwa_vi:
    case AMDGPU::V_CMPX_F_U16_sdwa_vi:
    case AMDGPU::V_CMPX_F_U32_sdwa_vi:
    case AMDGPU::V_CMPX_GE_I16_sdwa_vi:
    case AMDGPU::V_CMPX_GE_I32_sdwa_vi:
    case AMDGPU::V_CMPX_GE_U16_sdwa_vi:
    case AMDGPU::V_CMPX_GE_U32_sdwa_vi:
    case AMDGPU::V_CMPX_GT_I16_sdwa_vi:
    case AMDGPU::V_CMPX_GT_I32_sdwa_vi:
    case AMDGPU::V_CMPX_GT_U16_sdwa_vi:
    case AMDGPU::V_CMPX_GT_U32_sdwa_vi:
    case AMDGPU::V_CMPX_LE_I16_sdwa_vi:
    case AMDGPU::V_CMPX_LE_I32_sdwa_vi:
    case AMDGPU::V_CMPX_LE_U16_sdwa_vi:
    case AMDGPU::V_CMPX_LE_U32_sdwa_vi:
    case AMDGPU::V_CMPX_LT_I16_sdwa_vi:
    case AMDGPU::V_CMPX_LT_I32_sdwa_vi:
    case AMDGPU::V_CMPX_LT_U16_sdwa_vi:
    case AMDGPU::V_CMPX_LT_U32_sdwa_vi:
    case AMDGPU::V_CMPX_NE_I16_sdwa_vi:
    case AMDGPU::V_CMPX_NE_I32_sdwa_vi:
    case AMDGPU::V_CMPX_NE_U16_sdwa_vi:
    case AMDGPU::V_CMPX_NE_U32_sdwa_vi:
    case AMDGPU::V_CMPX_T_I16_sdwa_vi:
    case AMDGPU::V_CMPX_T_I32_sdwa_vi:
    case AMDGPU::V_CMPX_T_U16_sdwa_vi:
    case AMDGPU::V_CMPX_T_U32_sdwa_vi:
    case AMDGPU::V_CMP_EQ_I16_sdwa_vi:
    case AMDGPU::V_CMP_EQ_I32_sdwa_vi:
    case AMDGPU::V_CMP_EQ_U16_sdwa_vi:
    case AMDGPU::V_CMP_EQ_U32_sdwa_vi:
    case AMDGPU::V_CMP_F_I16_sdwa_vi:
    case AMDGPU::V_CMP_F_I32_sdwa_vi:
    case AMDGPU::V_CMP_F_U16_sdwa_vi:
    case AMDGPU::V_CMP_F_U32_sdwa_vi:
    case AMDGPU::V_CMP_GE_I16_sdwa_vi:
    case AMDGPU::V_CMP_GE_I32_sdwa_vi:
    case AMDGPU::V_CMP_GE_U16_sdwa_vi:
    case AMDGPU::V_CMP_GE_U32_sdwa_vi:
    case AMDGPU::V_CMP_GT_I16_sdwa_vi:
    case AMDGPU::V_CMP_GT_I32_sdwa_vi:
    case AMDGPU::V_CMP_GT_U16_sdwa_vi:
    case AMDGPU::V_CMP_GT_U32_sdwa_vi:
    case AMDGPU::V_CMP_LE_I16_sdwa_vi:
    case AMDGPU::V_CMP_LE_I32_sdwa_vi:
    case AMDGPU::V_CMP_LE_U16_sdwa_vi:
    case AMDGPU::V_CMP_LE_U32_sdwa_vi:
    case AMDGPU::V_CMP_LT_I16_sdwa_vi:
    case AMDGPU::V_CMP_LT_I32_sdwa_vi:
    case AMDGPU::V_CMP_LT_U16_sdwa_vi:
    case AMDGPU::V_CMP_LT_U32_sdwa_vi:
    case AMDGPU::V_CMP_NE_I16_sdwa_vi:
    case AMDGPU::V_CMP_NE_I32_sdwa_vi:
    case AMDGPU::V_CMP_NE_U16_sdwa_vi:
    case AMDGPU::V_CMP_NE_U32_sdwa_vi:
    case AMDGPU::V_CMP_T_I16_sdwa_vi:
    case AMDGPU::V_CMP_T_I32_sdwa_vi:
    case AMDGPU::V_CMP_T_U16_sdwa_vi:
    case AMDGPU::V_CMP_T_U32_sdwa_vi: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 6:
        // op: src0_sel
        return 48;
      case 1:
        // op: src0_modifiers
        return 51;
      case 7:
        // op: src1_sel
        return 56;
      case 3:
        // op: src1_modifiers
        return 59;
      case 5:
        // op: clamp
        return 45;
      case 4:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_CVT_FLR_I32_F32_sdwa_gfx10:
    case AMDGPU::V_CVT_FLR_I32_F32_sdwa_gfx9:
    case AMDGPU::V_CVT_FLR_I32_F32_sdwa_vi:
    case AMDGPU::V_CVT_I16_F16_sdwa_gfx10:
    case AMDGPU::V_CVT_I16_F16_sdwa_gfx9:
    case AMDGPU::V_CVT_I16_F16_sdwa_vi:
    case AMDGPU::V_CVT_I32_F32_sdwa_gfx10:
    case AMDGPU::V_CVT_I32_F32_sdwa_gfx9:
    case AMDGPU::V_CVT_I32_F32_sdwa_vi:
    case AMDGPU::V_CVT_NORM_I16_F16_sdwa_gfx10:
    case AMDGPU::V_CVT_NORM_I16_F16_sdwa_gfx9:
    case AMDGPU::V_CVT_NORM_I16_F16_sdwa_vi:
    case AMDGPU::V_CVT_NORM_U16_F16_sdwa_gfx10:
    case AMDGPU::V_CVT_NORM_U16_F16_sdwa_gfx9:
    case AMDGPU::V_CVT_NORM_U16_F16_sdwa_vi:
    case AMDGPU::V_CVT_RPI_I32_F32_sdwa_gfx10:
    case AMDGPU::V_CVT_RPI_I32_F32_sdwa_gfx9:
    case AMDGPU::V_CVT_RPI_I32_F32_sdwa_vi:
    case AMDGPU::V_CVT_U16_F16_sdwa_gfx10:
    case AMDGPU::V_CVT_U16_F16_sdwa_gfx9:
    case AMDGPU::V_CVT_U16_F16_sdwa_vi:
    case AMDGPU::V_CVT_U32_F32_sdwa_gfx10:
    case AMDGPU::V_CVT_U32_F32_sdwa_gfx9:
    case AMDGPU::V_CVT_U32_F32_sdwa_vi:
    case AMDGPU::V_FREXP_EXP_I16_F16_sdwa_gfx10:
    case AMDGPU::V_FREXP_EXP_I16_F16_sdwa_gfx9:
    case AMDGPU::V_FREXP_EXP_I16_F16_sdwa_vi:
    case AMDGPU::V_FREXP_EXP_I32_F32_sdwa_gfx10:
    case AMDGPU::V_FREXP_EXP_I32_F32_sdwa_gfx9:
    case AMDGPU::V_FREXP_EXP_I32_F32_sdwa_vi: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 6:
        // op: src0_sel
        return 48;
      case 1:
        // op: src0_modifiers
        return 52;
      case 4:
        // op: dst_sel
        return 40;
      case 5:
        // op: dst_unused
        return 43;
      case 3:
        // op: clamp
        return 45;
      case 0:
        // op: vdst
        return 17;
      }
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_CLASS_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_CLASS_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_CLASS_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_CLASS_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_CLASS_F32_sdwa_gfx9: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 6:
        // op: src0_sel
        return 48;
      case 1:
        // op: src0_modifiers
        return 52;
      case 7:
        // op: src1_sel
        return 56;
      case 3:
        // op: src1_modifiers
        return 59;
      case 0:
        // op: sdst
        return 40;
      case 4:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_sdwa_vi:
    case AMDGPU::V_CMPX_CLASS_F32_sdwa_vi:
    case AMDGPU::V_CMP_CLASS_F16_sdwa_vi:
    case AMDGPU::V_CMP_CLASS_F32_sdwa_vi: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 6:
        // op: src0_sel
        return 48;
      case 1:
        // op: src0_modifiers
        return 52;
      case 7:
        // op: src1_sel
        return 56;
      case 3:
        // op: src1_modifiers
        return 59;
      case 5:
        // op: clamp
        return 45;
      case 4:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_CMPX_EQ_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_EQ_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_F_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_F_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_GE_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_GE_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_GT_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_GT_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_LE_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_LE_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_LG_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_LG_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_LT_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_LT_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_NEQ_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_NEQ_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_NGE_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_NGE_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_NGT_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_NGT_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_NLE_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_NLE_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_NLG_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_NLG_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_NLT_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_NLT_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_O_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_O_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_TRU_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_TRU_F32_sdwa_gfx9:
    case AMDGPU::V_CMPX_U_F16_sdwa_gfx9:
    case AMDGPU::V_CMPX_U_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_EQ_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_EQ_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_EQ_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_EQ_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_F_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_F_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_F_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_F_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_GE_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_GE_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_GE_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_GE_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_GT_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_GT_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_GT_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_GT_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_LE_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_LE_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_LE_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_LE_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_LG_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_LG_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_LG_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_LG_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_LT_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_LT_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_LT_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_LT_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_NEQ_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_NEQ_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_NEQ_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_NEQ_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_NGE_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_NGE_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_NGE_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_NGE_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_NGT_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_NGT_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_NGT_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_NGT_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_NLE_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_NLE_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_NLE_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_NLE_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_NLG_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_NLG_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_NLG_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_NLG_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_NLT_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_NLT_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_NLT_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_NLT_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_O_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_O_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_O_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_O_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_TRU_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_TRU_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_TRU_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_TRU_F32_sdwa_gfx9:
    case AMDGPU::V_CMP_U_F16_sdwa_gfx10:
    case AMDGPU::V_CMP_U_F16_sdwa_gfx9:
    case AMDGPU::V_CMP_U_F32_sdwa_gfx10:
    case AMDGPU::V_CMP_U_F32_sdwa_gfx9: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 6:
        // op: src0_sel
        return 48;
      case 1:
        // op: src0_modifiers
        return 52;
      case 7:
        // op: src1_sel
        return 56;
      case 3:
        // op: src1_modifiers
        return 60;
      case 0:
        // op: sdst
        return 40;
      case 4:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_CMPX_EQ_F16_sdwa_vi:
    case AMDGPU::V_CMPX_EQ_F32_sdwa_vi:
    case AMDGPU::V_CMPX_F_F16_sdwa_vi:
    case AMDGPU::V_CMPX_F_F32_sdwa_vi:
    case AMDGPU::V_CMPX_GE_F16_sdwa_vi:
    case AMDGPU::V_CMPX_GE_F32_sdwa_vi:
    case AMDGPU::V_CMPX_GT_F16_sdwa_vi:
    case AMDGPU::V_CMPX_GT_F32_sdwa_vi:
    case AMDGPU::V_CMPX_LE_F16_sdwa_vi:
    case AMDGPU::V_CMPX_LE_F32_sdwa_vi:
    case AMDGPU::V_CMPX_LG_F16_sdwa_vi:
    case AMDGPU::V_CMPX_LG_F32_sdwa_vi:
    case AMDGPU::V_CMPX_LT_F16_sdwa_vi:
    case AMDGPU::V_CMPX_LT_F32_sdwa_vi:
    case AMDGPU::V_CMPX_NEQ_F16_sdwa_vi:
    case AMDGPU::V_CMPX_NEQ_F32_sdwa_vi:
    case AMDGPU::V_CMPX_NGE_F16_sdwa_vi:
    case AMDGPU::V_CMPX_NGE_F32_sdwa_vi:
    case AMDGPU::V_CMPX_NGT_F16_sdwa_vi:
    case AMDGPU::V_CMPX_NGT_F32_sdwa_vi:
    case AMDGPU::V_CMPX_NLE_F16_sdwa_vi:
    case AMDGPU::V_CMPX_NLE_F32_sdwa_vi:
    case AMDGPU::V_CMPX_NLG_F16_sdwa_vi:
    case AMDGPU::V_CMPX_NLG_F32_sdwa_vi:
    case AMDGPU::V_CMPX_NLT_F16_sdwa_vi:
    case AMDGPU::V_CMPX_NLT_F32_sdwa_vi:
    case AMDGPU::V_CMPX_O_F16_sdwa_vi:
    case AMDGPU::V_CMPX_O_F32_sdwa_vi:
    case AMDGPU::V_CMPX_TRU_F16_sdwa_vi:
    case AMDGPU::V_CMPX_TRU_F32_sdwa_vi:
    case AMDGPU::V_CMPX_U_F16_sdwa_vi:
    case AMDGPU::V_CMPX_U_F32_sdwa_vi:
    case AMDGPU::V_CMP_EQ_F16_sdwa_vi:
    case AMDGPU::V_CMP_EQ_F32_sdwa_vi:
    case AMDGPU::V_CMP_F_F16_sdwa_vi:
    case AMDGPU::V_CMP_F_F32_sdwa_vi:
    case AMDGPU::V_CMP_GE_F16_sdwa_vi:
    case AMDGPU::V_CMP_GE_F32_sdwa_vi:
    case AMDGPU::V_CMP_GT_F16_sdwa_vi:
    case AMDGPU::V_CMP_GT_F32_sdwa_vi:
    case AMDGPU::V_CMP_LE_F16_sdwa_vi:
    case AMDGPU::V_CMP_LE_F32_sdwa_vi:
    case AMDGPU::V_CMP_LG_F16_sdwa_vi:
    case AMDGPU::V_CMP_LG_F32_sdwa_vi:
    case AMDGPU::V_CMP_LT_F16_sdwa_vi:
    case AMDGPU::V_CMP_LT_F32_sdwa_vi:
    case AMDGPU::V_CMP_NEQ_F16_sdwa_vi:
    case AMDGPU::V_CMP_NEQ_F32_sdwa_vi:
    case AMDGPU::V_CMP_NGE_F16_sdwa_vi:
    case AMDGPU::V_CMP_NGE_F32_sdwa_vi:
    case AMDGPU::V_CMP_NGT_F16_sdwa_vi:
    case AMDGPU::V_CMP_NGT_F32_sdwa_vi:
    case AMDGPU::V_CMP_NLE_F16_sdwa_vi:
    case AMDGPU::V_CMP_NLE_F32_sdwa_vi:
    case AMDGPU::V_CMP_NLG_F16_sdwa_vi:
    case AMDGPU::V_CMP_NLG_F32_sdwa_vi:
    case AMDGPU::V_CMP_NLT_F16_sdwa_vi:
    case AMDGPU::V_CMP_NLT_F32_sdwa_vi:
    case AMDGPU::V_CMP_O_F16_sdwa_vi:
    case AMDGPU::V_CMP_O_F32_sdwa_vi:
    case AMDGPU::V_CMP_TRU_F16_sdwa_vi:
    case AMDGPU::V_CMP_TRU_F32_sdwa_vi:
    case AMDGPU::V_CMP_U_F16_sdwa_vi:
    case AMDGPU::V_CMP_U_F32_sdwa_vi: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 6:
        // op: src0_sel
        return 48;
      case 1:
        // op: src0_modifiers
        return 52;
      case 7:
        // op: src1_sel
        return 56;
      case 3:
        // op: src1_modifiers
        return 60;
      case 5:
        // op: clamp
        return 45;
      case 4:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_CVT_F16_I16_sdwa_vi:
    case AMDGPU::V_CVT_F16_U16_sdwa_vi:
    case AMDGPU::V_CVT_F32_I32_sdwa_vi:
    case AMDGPU::V_CVT_F32_U32_sdwa_vi:
    case AMDGPU::V_CVT_F32_UBYTE0_sdwa_vi:
    case AMDGPU::V_CVT_F32_UBYTE1_sdwa_vi:
    case AMDGPU::V_CVT_F32_UBYTE2_sdwa_vi:
    case AMDGPU::V_CVT_F32_UBYTE3_sdwa_vi:
    case AMDGPU::V_CVT_OFF_F32_I4_sdwa_vi: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 7:
        // op: src0_sel
        return 48;
      case 1:
        // op: src0_modifiers
        return 51;
      case 5:
        // op: dst_sel
        return 40;
      case 6:
        // op: dst_unused
        return 43;
      case 3:
        // op: clamp
        return 45;
      case 0:
        // op: vdst
        return 17;
      }
      break;
    }
    case AMDGPU::V_CVT_F16_I16_sdwa_gfx10:
    case AMDGPU::V_CVT_F16_I16_sdwa_gfx9:
    case AMDGPU::V_CVT_F16_U16_sdwa_gfx10:
    case AMDGPU::V_CVT_F16_U16_sdwa_gfx9:
    case AMDGPU::V_CVT_F32_I32_sdwa_gfx10:
    case AMDGPU::V_CVT_F32_I32_sdwa_gfx9:
    case AMDGPU::V_CVT_F32_U32_sdwa_gfx10:
    case AMDGPU::V_CVT_F32_U32_sdwa_gfx9:
    case AMDGPU::V_CVT_F32_UBYTE0_sdwa_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE0_sdwa_gfx9:
    case AMDGPU::V_CVT_F32_UBYTE1_sdwa_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE1_sdwa_gfx9:
    case AMDGPU::V_CVT_F32_UBYTE2_sdwa_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE2_sdwa_gfx9:
    case AMDGPU::V_CVT_F32_UBYTE3_sdwa_gfx10:
    case AMDGPU::V_CVT_F32_UBYTE3_sdwa_gfx9:
    case AMDGPU::V_CVT_OFF_F32_I4_sdwa_gfx10:
    case AMDGPU::V_CVT_OFF_F32_I4_sdwa_gfx9: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 7:
        // op: src0_sel
        return 48;
      case 1:
        // op: src0_modifiers
        return 51;
      case 5:
        // op: dst_sel
        return 40;
      case 6:
        // op: dst_unused
        return 43;
      case 3:
        // op: clamp
        return 45;
      case 4:
        // op: omod
        return 46;
      case 0:
        // op: vdst
        return 17;
      }
      break;
    }
    case AMDGPU::V_CEIL_F16_sdwa_vi:
    case AMDGPU::V_CEIL_F32_sdwa_vi:
    case AMDGPU::V_COS_F16_sdwa_vi:
    case AMDGPU::V_COS_F32_sdwa_vi:
    case AMDGPU::V_CVT_F16_F32_sdwa_vi:
    case AMDGPU::V_CVT_F32_F16_sdwa_vi:
    case AMDGPU::V_EXP_F16_sdwa_vi:
    case AMDGPU::V_EXP_F32_sdwa_vi:
    case AMDGPU::V_EXP_LEGACY_F32_sdwa_vi:
    case AMDGPU::V_FLOOR_F16_sdwa_vi:
    case AMDGPU::V_FLOOR_F32_sdwa_vi:
    case AMDGPU::V_FRACT_F16_sdwa_vi:
    case AMDGPU::V_FRACT_F32_sdwa_vi:
    case AMDGPU::V_FREXP_MANT_F16_sdwa_vi:
    case AMDGPU::V_FREXP_MANT_F32_sdwa_vi:
    case AMDGPU::V_LOG_F16_sdwa_vi:
    case AMDGPU::V_LOG_F32_sdwa_vi:
    case AMDGPU::V_LOG_LEGACY_F32_sdwa_vi:
    case AMDGPU::V_RCP_F16_sdwa_vi:
    case AMDGPU::V_RCP_F32_sdwa_vi:
    case AMDGPU::V_RCP_IFLAG_F32_sdwa_vi:
    case AMDGPU::V_RNDNE_F16_sdwa_vi:
    case AMDGPU::V_RNDNE_F32_sdwa_vi:
    case AMDGPU::V_RSQ_F16_sdwa_vi:
    case AMDGPU::V_RSQ_F32_sdwa_vi:
    case AMDGPU::V_SIN_F16_sdwa_vi:
    case AMDGPU::V_SIN_F32_sdwa_vi:
    case AMDGPU::V_SQRT_F16_sdwa_vi:
    case AMDGPU::V_SQRT_F32_sdwa_vi:
    case AMDGPU::V_TRUNC_F16_sdwa_vi:
    case AMDGPU::V_TRUNC_F32_sdwa_vi: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 7:
        // op: src0_sel
        return 48;
      case 1:
        // op: src0_modifiers
        return 52;
      case 5:
        // op: dst_sel
        return 40;
      case 6:
        // op: dst_unused
        return 43;
      case 3:
        // op: clamp
        return 45;
      case 0:
        // op: vdst
        return 17;
      }
      break;
    }
    case AMDGPU::V_CEIL_F16_sdwa_gfx10:
    case AMDGPU::V_CEIL_F16_sdwa_gfx9:
    case AMDGPU::V_CEIL_F32_sdwa_gfx10:
    case AMDGPU::V_CEIL_F32_sdwa_gfx9:
    case AMDGPU::V_COS_F16_sdwa_gfx10:
    case AMDGPU::V_COS_F16_sdwa_gfx9:
    case AMDGPU::V_COS_F32_sdwa_gfx10:
    case AMDGPU::V_COS_F32_sdwa_gfx9:
    case AMDGPU::V_CVT_F16_F32_sdwa_gfx10:
    case AMDGPU::V_CVT_F16_F32_sdwa_gfx9:
    case AMDGPU::V_CVT_F32_BF16_sdwa_gfx9:
    case AMDGPU::V_CVT_F32_F16_sdwa_gfx10:
    case AMDGPU::V_CVT_F32_F16_sdwa_gfx9:
    case AMDGPU::V_EXP_F16_sdwa_gfx10:
    case AMDGPU::V_EXP_F16_sdwa_gfx9:
    case AMDGPU::V_EXP_F32_sdwa_gfx10:
    case AMDGPU::V_EXP_F32_sdwa_gfx9:
    case AMDGPU::V_EXP_LEGACY_F32_sdwa_gfx9:
    case AMDGPU::V_FLOOR_F16_sdwa_gfx10:
    case AMDGPU::V_FLOOR_F16_sdwa_gfx9:
    case AMDGPU::V_FLOOR_F32_sdwa_gfx10:
    case AMDGPU::V_FLOOR_F32_sdwa_gfx9:
    case AMDGPU::V_FRACT_F16_sdwa_gfx10:
    case AMDGPU::V_FRACT_F16_sdwa_gfx9:
    case AMDGPU::V_FRACT_F32_sdwa_gfx10:
    case AMDGPU::V_FRACT_F32_sdwa_gfx9:
    case AMDGPU::V_FREXP_MANT_F16_sdwa_gfx10:
    case AMDGPU::V_FREXP_MANT_F16_sdwa_gfx9:
    case AMDGPU::V_FREXP_MANT_F32_sdwa_gfx10:
    case AMDGPU::V_FREXP_MANT_F32_sdwa_gfx9:
    case AMDGPU::V_LOG_F16_sdwa_gfx10:
    case AMDGPU::V_LOG_F16_sdwa_gfx9:
    case AMDGPU::V_LOG_F32_sdwa_gfx10:
    case AMDGPU::V_LOG_F32_sdwa_gfx9:
    case AMDGPU::V_LOG_LEGACY_F32_sdwa_gfx9:
    case AMDGPU::V_RCP_F16_sdwa_gfx10:
    case AMDGPU::V_RCP_F16_sdwa_gfx9:
    case AMDGPU::V_RCP_F32_sdwa_gfx10:
    case AMDGPU::V_RCP_F32_sdwa_gfx9:
    case AMDGPU::V_RCP_IFLAG_F32_sdwa_gfx10:
    case AMDGPU::V_RCP_IFLAG_F32_sdwa_gfx9:
    case AMDGPU::V_RNDNE_F16_sdwa_gfx10:
    case AMDGPU::V_RNDNE_F16_sdwa_gfx9:
    case AMDGPU::V_RNDNE_F32_sdwa_gfx10:
    case AMDGPU::V_RNDNE_F32_sdwa_gfx9:
    case AMDGPU::V_RSQ_F16_sdwa_gfx10:
    case AMDGPU::V_RSQ_F16_sdwa_gfx9:
    case AMDGPU::V_RSQ_F32_sdwa_gfx10:
    case AMDGPU::V_RSQ_F32_sdwa_gfx9:
    case AMDGPU::V_SIN_F16_sdwa_gfx10:
    case AMDGPU::V_SIN_F16_sdwa_gfx9:
    case AMDGPU::V_SIN_F32_sdwa_gfx10:
    case AMDGPU::V_SIN_F32_sdwa_gfx9:
    case AMDGPU::V_SQRT_F16_sdwa_gfx10:
    case AMDGPU::V_SQRT_F16_sdwa_gfx9:
    case AMDGPU::V_SQRT_F32_sdwa_gfx10:
    case AMDGPU::V_SQRT_F32_sdwa_gfx9:
    case AMDGPU::V_TRUNC_F16_sdwa_gfx10:
    case AMDGPU::V_TRUNC_F16_sdwa_gfx9:
    case AMDGPU::V_TRUNC_F32_sdwa_gfx10:
    case AMDGPU::V_TRUNC_F32_sdwa_gfx9: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 7:
        // op: src0_sel
        return 48;
      case 1:
        // op: src0_modifiers
        return 52;
      case 5:
        // op: dst_sel
        return 40;
      case 6:
        // op: dst_unused
        return 43;
      case 3:
        // op: clamp
        return 45;
      case 4:
        // op: omod
        return 46;
      case 0:
        // op: vdst
        return 17;
      }
      break;
    }
    case AMDGPU::V_ADDC_CO_U32_sdwa_gfx9:
    case AMDGPU::V_ADDC_U32_sdwa_vi:
    case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
    case AMDGPU::V_ADD_CO_CI_U32_sdwa_w32_gfx10:
    case AMDGPU::V_ADD_CO_CI_U32_sdwa_w64_gfx10:
    case AMDGPU::V_ADD_CO_U32_sdwa_gfx9:
    case AMDGPU::V_ADD_NC_U32_sdwa_gfx10:
    case AMDGPU::V_ADD_U16_sdwa_gfx9:
    case AMDGPU::V_ADD_U16_sdwa_vi:
    case AMDGPU::V_ADD_U32_sdwa_gfx9:
    case AMDGPU::V_ADD_U32_sdwa_vi:
    case AMDGPU::V_AND_B32_sdwa_gfx10:
    case AMDGPU::V_AND_B32_sdwa_gfx9:
    case AMDGPU::V_AND_B32_sdwa_vi:
    case AMDGPU::V_ASHRREV_I16_sdwa_gfx9:
    case AMDGPU::V_ASHRREV_I16_sdwa_vi:
    case AMDGPU::V_ASHRREV_I32_sdwa_gfx10:
    case AMDGPU::V_ASHRREV_I32_sdwa_gfx9:
    case AMDGPU::V_ASHRREV_I32_sdwa_vi:
    case AMDGPU::V_LSHLREV_B16_sdwa_gfx9:
    case AMDGPU::V_LSHLREV_B16_sdwa_vi:
    case AMDGPU::V_LSHLREV_B32_sdwa_gfx10:
    case AMDGPU::V_LSHLREV_B32_sdwa_gfx9:
    case AMDGPU::V_LSHLREV_B32_sdwa_vi:
    case AMDGPU::V_LSHRREV_B16_sdwa_gfx9:
    case AMDGPU::V_LSHRREV_B16_sdwa_vi:
    case AMDGPU::V_LSHRREV_B32_sdwa_gfx10:
    case AMDGPU::V_LSHRREV_B32_sdwa_gfx9:
    case AMDGPU::V_LSHRREV_B32_sdwa_vi:
    case AMDGPU::V_MAX_I16_sdwa_gfx9:
    case AMDGPU::V_MAX_I16_sdwa_vi:
    case AMDGPU::V_MAX_I32_sdwa_gfx10:
    case AMDGPU::V_MAX_I32_sdwa_gfx9:
    case AMDGPU::V_MAX_I32_sdwa_vi:
    case AMDGPU::V_MAX_U16_sdwa_gfx9:
    case AMDGPU::V_MAX_U16_sdwa_vi:
    case AMDGPU::V_MAX_U32_sdwa_gfx10:
    case AMDGPU::V_MAX_U32_sdwa_gfx9:
    case AMDGPU::V_MAX_U32_sdwa_vi:
    case AMDGPU::V_MIN_I16_sdwa_gfx9:
    case AMDGPU::V_MIN_I16_sdwa_vi:
    case AMDGPU::V_MIN_I32_sdwa_gfx10:
    case AMDGPU::V_MIN_I32_sdwa_gfx9:
    case AMDGPU::V_MIN_I32_sdwa_vi:
    case AMDGPU::V_MIN_U16_sdwa_gfx9:
    case AMDGPU::V_MIN_U16_sdwa_vi:
    case AMDGPU::V_MIN_U32_sdwa_gfx10:
    case AMDGPU::V_MIN_U32_sdwa_gfx9:
    case AMDGPU::V_MIN_U32_sdwa_vi:
    case AMDGPU::V_MUL_HI_I32_I24_sdwa_gfx10:
    case AMDGPU::V_MUL_HI_I32_I24_sdwa_gfx9:
    case AMDGPU::V_MUL_HI_I32_I24_sdwa_vi:
    case AMDGPU::V_MUL_HI_U32_U24_sdwa_gfx10:
    case AMDGPU::V_MUL_HI_U32_U24_sdwa_gfx9:
    case AMDGPU::V_MUL_HI_U32_U24_sdwa_vi:
    case AMDGPU::V_MUL_I32_I24_sdwa_gfx10:
    case AMDGPU::V_MUL_I32_I24_sdwa_gfx9:
    case AMDGPU::V_MUL_I32_I24_sdwa_vi:
    case AMDGPU::V_MUL_LO_U16_sdwa_gfx9:
    case AMDGPU::V_MUL_LO_U16_sdwa_vi:
    case AMDGPU::V_MUL_U32_U24_sdwa_gfx10:
    case AMDGPU::V_MUL_U32_U24_sdwa_gfx9:
    case AMDGPU::V_MUL_U32_U24_sdwa_vi:
    case AMDGPU::V_OR_B32_sdwa_gfx10:
    case AMDGPU::V_OR_B32_sdwa_gfx9:
    case AMDGPU::V_OR_B32_sdwa_vi:
    case AMDGPU::V_SUBBREV_CO_U32_sdwa_gfx9:
    case AMDGPU::V_SUBBREV_U32_sdwa_vi:
    case AMDGPU::V_SUBB_CO_U32_sdwa_gfx9:
    case AMDGPU::V_SUBB_U32_sdwa_vi:
    case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
    case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_w32_gfx10:
    case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_w64_gfx10:
    case AMDGPU::V_SUBREV_CO_U32_sdwa_gfx9:
    case AMDGPU::V_SUBREV_NC_U32_sdwa_gfx10:
    case AMDGPU::V_SUBREV_U16_sdwa_gfx9:
    case AMDGPU::V_SUBREV_U16_sdwa_vi:
    case AMDGPU::V_SUBREV_U32_sdwa_gfx9:
    case AMDGPU::V_SUBREV_U32_sdwa_vi:
    case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
    case AMDGPU::V_SUB_CO_CI_U32_sdwa_w32_gfx10:
    case AMDGPU::V_SUB_CO_CI_U32_sdwa_w64_gfx10:
    case AMDGPU::V_SUB_CO_U32_sdwa_gfx9:
    case AMDGPU::V_SUB_NC_U32_sdwa_gfx10:
    case AMDGPU::V_SUB_U16_sdwa_gfx9:
    case AMDGPU::V_SUB_U16_sdwa_vi:
    case AMDGPU::V_SUB_U32_sdwa_gfx9:
    case AMDGPU::V_SUB_U32_sdwa_vi:
    case AMDGPU::V_XNOR_B32_sdwa_gfx10:
    case AMDGPU::V_XNOR_B32_sdwa_gfx9:
    case AMDGPU::V_XNOR_B32_sdwa_vi:
    case AMDGPU::V_XOR_B32_sdwa_gfx10:
    case AMDGPU::V_XOR_B32_sdwa_gfx9:
    case AMDGPU::V_XOR_B32_sdwa_vi: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 8:
        // op: src0_sel
        return 48;
      case 1:
        // op: src0_modifiers
        return 51;
      case 9:
        // op: src1_sel
        return 56;
      case 3:
        // op: src1_modifiers
        return 59;
      case 6:
        // op: dst_sel
        return 40;
      case 7:
        // op: dst_unused
        return 43;
      case 5:
        // op: clamp
        return 45;
      case 0:
        // op: vdst
        return 17;
      case 4:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
    case AMDGPU::V_CNDMASK_B32_sdwa_gfx9:
    case AMDGPU::V_CNDMASK_B32_sdwa_vi:
    case AMDGPU::V_CNDMASK_B32_sdwa_w32_gfx10:
    case AMDGPU::V_CNDMASK_B32_sdwa_w64_gfx10: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 8:
        // op: src0_sel
        return 48;
      case 1:
        // op: src0_modifiers
        return 52;
      case 9:
        // op: src1_sel
        return 56;
      case 3:
        // op: src1_modifiers
        return 60;
      case 6:
        // op: dst_sel
        return 40;
      case 7:
        // op: dst_unused
        return 43;
      case 5:
        // op: clamp
        return 45;
      case 0:
        // op: vdst
        return 17;
      case 4:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_LDEXP_F16_sdwa_vi: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 9:
        // op: src0_sel
        return 48;
      case 1:
        // op: src0_modifiers
        return 52;
      case 10:
        // op: src1_sel
        return 56;
      case 3:
        // op: src1_modifiers
        return 59;
      case 7:
        // op: dst_sel
        return 40;
      case 8:
        // op: dst_unused
        return 43;
      case 5:
        // op: clamp
        return 45;
      case 0:
        // op: vdst
        return 17;
      case 4:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_LDEXP_F16_sdwa_gfx10:
    case AMDGPU::V_LDEXP_F16_sdwa_gfx9: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 9:
        // op: src0_sel
        return 48;
      case 1:
        // op: src0_modifiers
        return 52;
      case 10:
        // op: src1_sel
        return 56;
      case 3:
        // op: src1_modifiers
        return 59;
      case 7:
        // op: dst_sel
        return 40;
      case 8:
        // op: dst_unused
        return 43;
      case 5:
        // op: clamp
        return 45;
      case 6:
        // op: omod
        return 46;
      case 0:
        // op: vdst
        return 17;
      case 4:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_ADD_F16_sdwa_vi:
    case AMDGPU::V_ADD_F32_sdwa_vi:
    case AMDGPU::V_MAX_F16_sdwa_vi:
    case AMDGPU::V_MAX_F32_sdwa_vi:
    case AMDGPU::V_MIN_F16_sdwa_vi:
    case AMDGPU::V_MIN_F32_sdwa_vi:
    case AMDGPU::V_MUL_F16_sdwa_vi:
    case AMDGPU::V_MUL_F32_sdwa_vi:
    case AMDGPU::V_MUL_LEGACY_F32_sdwa_vi:
    case AMDGPU::V_SUBREV_F16_sdwa_vi:
    case AMDGPU::V_SUBREV_F32_sdwa_vi:
    case AMDGPU::V_SUB_F16_sdwa_vi:
    case AMDGPU::V_SUB_F32_sdwa_vi: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 9:
        // op: src0_sel
        return 48;
      case 1:
        // op: src0_modifiers
        return 52;
      case 10:
        // op: src1_sel
        return 56;
      case 3:
        // op: src1_modifiers
        return 60;
      case 7:
        // op: dst_sel
        return 40;
      case 8:
        // op: dst_unused
        return 43;
      case 5:
        // op: clamp
        return 45;
      case 0:
        // op: vdst
        return 17;
      case 4:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_ADD_F16_sdwa_gfx10:
    case AMDGPU::V_ADD_F16_sdwa_gfx9:
    case AMDGPU::V_ADD_F32_sdwa_gfx10:
    case AMDGPU::V_ADD_F32_sdwa_gfx9:
    case AMDGPU::V_CVT_PKRTZ_F16_F32_sdwa_gfx10:
    case AMDGPU::V_MAX_F16_sdwa_gfx10:
    case AMDGPU::V_MAX_F16_sdwa_gfx9:
    case AMDGPU::V_MAX_F32_sdwa_gfx10:
    case AMDGPU::V_MAX_F32_sdwa_gfx9:
    case AMDGPU::V_MIN_F16_sdwa_gfx10:
    case AMDGPU::V_MIN_F16_sdwa_gfx9:
    case AMDGPU::V_MIN_F32_sdwa_gfx10:
    case AMDGPU::V_MIN_F32_sdwa_gfx9:
    case AMDGPU::V_MUL_F16_sdwa_gfx10:
    case AMDGPU::V_MUL_F16_sdwa_gfx9:
    case AMDGPU::V_MUL_F32_sdwa_gfx10:
    case AMDGPU::V_MUL_F32_sdwa_gfx9:
    case AMDGPU::V_MUL_LEGACY_F32_sdwa_gfx10:
    case AMDGPU::V_MUL_LEGACY_F32_sdwa_gfx9:
    case AMDGPU::V_PK_FMAC_F16_sdwa_gfx9:
    case AMDGPU::V_SUBREV_F16_sdwa_gfx10:
    case AMDGPU::V_SUBREV_F16_sdwa_gfx9:
    case AMDGPU::V_SUBREV_F32_sdwa_gfx10:
    case AMDGPU::V_SUBREV_F32_sdwa_gfx9:
    case AMDGPU::V_SUB_F16_sdwa_gfx10:
    case AMDGPU::V_SUB_F16_sdwa_gfx9:
    case AMDGPU::V_SUB_F32_sdwa_gfx10:
    case AMDGPU::V_SUB_F32_sdwa_gfx9: {
      switch (OpNum) {
      case 2:
        // op: src0
        return 32;
      case 9:
        // op: src0_sel
        return 48;
      case 1:
        // op: src0_modifiers
        return 52;
      case 10:
        // op: src1_sel
        return 56;
      case 3:
        // op: src1_modifiers
        return 60;
      case 7:
        // op: dst_sel
        return 40;
      case 8:
        // op: dst_unused
        return 43;
      case 5:
        // op: clamp
        return 45;
      case 6:
        // op: omod
        return 46;
      case 0:
        // op: vdst
        return 17;
      case 4:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 0:
        // op: vdstX
        return 56;
      case 3:
        // op: src0Y
        return 32;
      case 1:
        // op: vdstY
        return 49;
      }
      break;
    }
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMAAK_F32_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 0:
        // op: vdstX
        return 56;
      case 3:
        // op: src0Y
        return 32;
      case 4:
        // op: vsrc1Y
        return 41;
      case 1:
        // op: vdstY
        return 49;
      case 5:
        // op: imm
        return 64;
      }
      break;
    }
    case AMDGPU::V_DUAL_MOV_B32_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_SUB_U32_e32_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 0:
        // op: vdstX
        return 56;
      case 3:
        // op: src0Y
        return 32;
      case 4:
        // op: vsrc1Y
        return 41;
      case 1:
        // op: vdstY
        return 49;
      }
      break;
    }
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMAMK_F32_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 0:
        // op: vdstX
        return 56;
      case 3:
        // op: src0Y
        return 32;
      case 5:
        // op: vsrc1Y
        return 41;
      case 1:
        // op: vdstY
        return 49;
      case 4:
        // op: imm
        return 64;
      }
      break;
    }
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MOV_B32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 0:
        // op: vdstX
        return 64;
      case 3:
        // op: src0Y
        return 32;
      case 1:
        // op: vdstY
        return 88;
      }
      break;
    }
    case AMDGPU::V_DUAL_MOV_B32_e32_X_BITOP2_B32_e64_e96_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 0:
        // op: vdstX
        return 64;
      case 3:
        // op: src0Y
        return 32;
      case 4:
        // op: vsrc1Y
        return 72;
      case 1:
        // op: vdstY
        return 88;
      case 5:
        // op: bitop3
        return 80;
      }
      break;
    }
    case AMDGPU::V_DUAL_MOV_B32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_SUB_U32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 0:
        // op: vdstX
        return 64;
      case 3:
        // op: src0Y
        return 32;
      case 4:
        // op: vsrc1Y
        return 72;
      case 1:
        // op: vdstY
        return 88;
      }
      break;
    }
    case AMDGPU::V_DUAL_MOV_B32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MOV_B32_e32_X_SUB_F32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 0:
        // op: vdstX
        return 64;
      case 4:
        // op: src0Y
        return 32;
      case 6:
        // op: vsrc1Y
        return 72;
      case 1:
        // op: vdstY
        return 88;
      case 3:
        // op: src0Y_modifiers
        return 44;
      case 5:
        // op: vsrc1Y_modifiers
        return 45;
      }
      break;
    }
    case AMDGPU::V_DUAL_MOV_B32_e32_X_CNDMASK_B32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 0:
        // op: vdstX
        return 64;
      case 4:
        // op: src0Y
        return 32;
      case 6:
        // op: vsrc1Y
        return 72;
      case 7:
        // op: vsrc2Y
        return 80;
      case 1:
        // op: vdstY
        return 88;
      case 3:
        // op: src0Y_modifiers
        return 44;
      case 5:
        // op: vsrc1Y_modifiers
        return 45;
      }
      break;
    }
    case AMDGPU::V_DUAL_MOV_B32_e32_X_FMA_F32_e64_e96_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 0:
        // op: vdstX
        return 64;
      case 4:
        // op: src0Y
        return 32;
      case 6:
        // op: vsrc1Y
        return 72;
      case 8:
        // op: vsrc2Y
        return 80;
      case 1:
        // op: vdstY
        return 88;
      case 3:
        // op: src0Y_modifiers
        return 44;
      case 5:
        // op: vsrc1Y_modifiers
        return 45;
      case 7:
        // op: vsrc2Y_modifiers
        return 46;
      }
      break;
    }
    case AMDGPU::V_DUAL_ADD_U32_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_MOV_B32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 3:
        // op: vsrc1X
        return 48;
      case 0:
        // op: vdstX
        return 64;
      case 4:
        // op: src0Y
        return 32;
      case 1:
        // op: vdstY
        return 88;
      }
      break;
    }
    case AMDGPU::V_DUAL_ADD_U32_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_BITOP2_B32_e64_e96_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 3:
        // op: vsrc1X
        return 48;
      case 0:
        // op: vdstX
        return 64;
      case 4:
        // op: src0Y
        return 32;
      case 5:
        // op: vsrc1Y
        return 72;
      case 1:
        // op: vdstY
        return 88;
      case 6:
        // op: bitop3
        return 80;
      }
      break;
    }
    case AMDGPU::V_DUAL_ADD_U32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_SUB_U32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 3:
        // op: vsrc1X
        return 48;
      case 0:
        // op: vdstX
        return 64;
      case 4:
        // op: src0Y
        return 32;
      case 5:
        // op: vsrc1Y
        return 72;
      case 1:
        // op: vdstY
        return 88;
      }
      break;
    }
    case AMDGPU::V_DUAL_ADD_U32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_U32_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_SUB_F32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 3:
        // op: vsrc1X
        return 48;
      case 0:
        // op: vdstX
        return 64;
      case 5:
        // op: src0Y
        return 32;
      case 7:
        // op: vsrc1Y
        return 72;
      case 1:
        // op: vdstY
        return 88;
      case 4:
        // op: src0Y_modifiers
        return 44;
      case 6:
        // op: vsrc1Y_modifiers
        return 45;
      }
      break;
    }
    case AMDGPU::V_DUAL_ADD_U32_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_CNDMASK_B32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 3:
        // op: vsrc1X
        return 48;
      case 0:
        // op: vdstX
        return 64;
      case 5:
        // op: src0Y
        return 32;
      case 7:
        // op: vsrc1Y
        return 72;
      case 8:
        // op: vsrc2Y
        return 80;
      case 1:
        // op: vdstY
        return 88;
      case 4:
        // op: src0Y_modifiers
        return 44;
      case 6:
        // op: vsrc1Y_modifiers
        return 45;
      }
      break;
    }
    case AMDGPU::V_DUAL_ADD_U32_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_ASHRREV_I32_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHLREV_B32_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_LSHRREV_B32_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_U32_e32_X_FMA_F32_e64_e96_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 3:
        // op: vsrc1X
        return 48;
      case 0:
        // op: vdstX
        return 64;
      case 5:
        // op: src0Y
        return 32;
      case 7:
        // op: vsrc1Y
        return 72;
      case 9:
        // op: vsrc2Y
        return 80;
      case 1:
        // op: vdstY
        return 88;
      case 4:
        // op: src0Y_modifiers
        return 44;
      case 6:
        // op: vsrc1Y_modifiers
        return 45;
      case 8:
        // op: vsrc2Y_modifiers
        return 46;
      }
      break;
    }
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MOV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MOV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MOV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MOV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MOV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MOV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MOV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MOV_B32_e32_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 3:
        // op: vsrc1X
        return 9;
      case 0:
        // op: vdstX
        return 56;
      case 4:
        // op: src0Y
        return 32;
      case 1:
        // op: vdstY
        return 49;
      }
      break;
    }
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMAAK_F32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMAAK_F32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMAAK_F32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMAAK_F32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMAAK_F32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMAAK_F32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMAAK_F32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMAAK_F32_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 3:
        // op: vsrc1X
        return 9;
      case 0:
        // op: vdstX
        return 56;
      case 4:
        // op: src0Y
        return 32;
      case 5:
        // op: vsrc1Y
        return 41;
      case 1:
        // op: vdstY
        return 49;
      case 6:
        // op: imm
        return 64;
      }
      break;
    }
    case AMDGPU::V_DUAL_ADD_F32_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_SUB_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_SUB_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_SUB_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_SUB_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_SUB_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_SUB_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_SUB_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_SUB_U32_e32_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 3:
        // op: vsrc1X
        return 9;
      case 0:
        // op: vdstX
        return 56;
      case 4:
        // op: src0Y
        return 32;
      case 5:
        // op: vsrc1Y
        return 41;
      case 1:
        // op: vdstY
        return 49;
      }
      break;
    }
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMAMK_F32_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMAMK_F32_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMAMK_F32_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMAMK_F32_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMAMK_F32_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMAMK_F32_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMAMK_F32_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMAMK_F32_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 3:
        // op: vsrc1X
        return 9;
      case 0:
        // op: vdstX
        return 56;
      case 4:
        // op: src0Y
        return 32;
      case 6:
        // op: vsrc1Y
        return 41;
      case 1:
        // op: vdstY
        return 49;
      case 5:
        // op: imm
        return 64;
      }
      break;
    }
    case AMDGPU::V_DUAL_FMAAK_F32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MOV_B32_e32_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 3:
        // op: vsrc1X
        return 9;
      case 0:
        // op: vdstX
        return 56;
      case 5:
        // op: src0Y
        return 32;
      case 1:
        // op: vdstY
        return 49;
      case 4:
        // op: imm
        return 64;
      }
      break;
    }
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MOV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MOV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MOV_B32_e32_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 3:
        // op: vsrc1X
        return 9;
      case 0:
        // op: vdstX
        return 56;
      case 5:
        // op: src0Y
        return 32;
      case 1:
        // op: vdstY
        return 49;
      }
      break;
    }
    case AMDGPU::V_DUAL_FMAAK_F32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_SUB_U32_e32_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 3:
        // op: vsrc1X
        return 9;
      case 0:
        // op: vdstX
        return 56;
      case 5:
        // op: src0Y
        return 32;
      case 6:
        // op: vsrc1Y
        return 41;
      case 1:
        // op: vdstY
        return 49;
      case 4:
        // op: imm
        return 64;
      }
      break;
    }
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMAAK_F32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMAAK_F32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_FMAAK_F32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMAAK_F32_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 3:
        // op: vsrc1X
        return 9;
      case 0:
        // op: vdstX
        return 56;
      case 5:
        // op: src0Y
        return 32;
      case 6:
        // op: vsrc1Y
        return 41;
      case 1:
        // op: vdstY
        return 49;
      case 7:
        // op: imm
        return 64;
      }
      break;
    }
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_SUB_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_SUB_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_SUB_U32_e32_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 3:
        // op: vsrc1X
        return 9;
      case 0:
        // op: vdstX
        return 56;
      case 5:
        // op: src0Y
        return 32;
      case 6:
        // op: vsrc1Y
        return 41;
      case 1:
        // op: vdstY
        return 49;
      }
      break;
    }
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMAMK_F32_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMAMK_F32_gfx1250:
    case AMDGPU::V_DUAL_FMAAK_F32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_FMAAK_F32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_FMAAK_F32_X_FMAMK_F32_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMAMK_F32_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 3:
        // op: vsrc1X
        return 9;
      case 0:
        // op: vdstX
        return 56;
      case 5:
        // op: src0Y
        return 32;
      case 7:
        // op: vsrc1Y
        return 41;
      case 1:
        // op: vdstY
        return 49;
      case 6:
        // op: imm
        return 64;
      }
      break;
    }
    case AMDGPU::V_DUAL_FMAMK_F32_X_MOV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MOV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MOV_B32_e32_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 4:
        // op: vsrc1X
        return 9;
      case 0:
        // op: vdstX
        return 56;
      case 5:
        // op: src0Y
        return 32;
      case 1:
        // op: vdstY
        return 49;
      case 3:
        // op: imm
        return 64;
      }
      break;
    }
    case AMDGPU::V_DUAL_FMAMK_F32_X_ADD_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_ADD_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_ADD_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_ADD_U32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_ADD_U32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_ADD_U32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_AND_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_AND_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_ASHRREV_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_CNDMASK_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_CNDMASK_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_CNDMASK_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_DOT2C_F32_BF16_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_DOT2C_F32_BF16_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_DOT2C_F32_BF16_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_DOT2C_F32_F16_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_DOT2C_F32_F16_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_DOT2C_F32_F16_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_FMAC_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_FMAC_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_FMAC_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_LSHLREV_B32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_LSHLREV_B32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_LSHLREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_LSHRREV_B32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MAX_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MAX_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MAX_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MAX_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MIN_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MIN_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MIN_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MIN_I32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MUL_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MUL_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MUL_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MUL_LEGACY_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MUL_LEGACY_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_MUL_LEGACY_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_SUBREV_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_SUBREV_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_SUBREV_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_SUB_F32_e32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_SUB_F32_e32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_SUB_F32_e32_gfx1250:
    case AMDGPU::V_DUAL_FMAMK_F32_X_SUB_U32_e32_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 4:
        // op: vsrc1X
        return 9;
      case 0:
        // op: vdstX
        return 56;
      case 5:
        // op: src0Y
        return 32;
      case 6:
        // op: vsrc1Y
        return 41;
      case 1:
        // op: vdstY
        return 49;
      case 3:
        // op: imm
        return 64;
      }
      break;
    }
    case AMDGPU::V_DUAL_FMAMK_F32_X_FMAAK_F32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_FMAAK_F32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_FMAAK_F32_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 4:
        // op: vsrc1X
        return 9;
      case 0:
        // op: vdstX
        return 56;
      case 5:
        // op: src0Y
        return 32;
      case 6:
        // op: vsrc1Y
        return 41;
      case 1:
        // op: vdstY
        return 49;
      case 7:
        // op: imm
        return 64;
      }
      break;
    }
    case AMDGPU::V_DUAL_FMAMK_F32_X_FMAMK_F32_gfx11:
    case AMDGPU::V_DUAL_FMAMK_F32_X_FMAMK_F32_gfx12:
    case AMDGPU::V_DUAL_FMAMK_F32_X_FMAMK_F32_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0X
        return 0;
      case 4:
        // op: vsrc1X
        return 9;
      case 0:
        // op: vdstX
        return 56;
      case 5:
        // op: src0Y
        return 32;
      case 7:
        // op: vsrc1Y
        return 41;
      case 1:
        // op: vdstY
        return 49;
      case 6:
        // op: imm
        return 64;
      }
      break;
    }
    case AMDGPU::V_BITOP3_B16_gfx1250_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_BITOP3_B16_gfx1250_t16_e64_dpp_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 11;
      case 4:
        // op: src1_modifiers
        return 12;
      case 6:
        // op: src2_modifiers
        return 13;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 7:
        // op: src2
        return 50;
      case 10:
        // op: dpp_ctrl
        return 72;
      case 13:
        // op: bound_ctrl
        return 83;
      case 12:
        // op: bank_mask
        return 88;
      case 11:
        // op: row_mask
        return 92;
      case 14:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      case 8:
        // op: bitop3
        return 8;
      }
      break;
    }
    case AMDGPU::V_BITOP3_B16_gfx1250_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_BITOP3_B16_gfx1250_t16_e64_dpp8_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 11;
      case 4:
        // op: src1_modifiers
        return 12;
      case 6:
        // op: src2_modifiers
        return 13;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 7:
        // op: src2
        return 50;
      case 3:
        // op: src0
        return 64;
      case 10:
        // op: dpp8
        return 72;
      case 11:
        // op: fi
        return 32;
      case 8:
        // op: bitop3
        return 8;
      }
      break;
    }
    case AMDGPU::V_CEIL_F16_dpp_vi:
    case AMDGPU::V_CEIL_F32_dpp_vi:
    case AMDGPU::V_CEIL_F64_dpp_vi:
    case AMDGPU::V_COS_F16_dpp_vi:
    case AMDGPU::V_COS_F32_dpp_vi:
    case AMDGPU::V_CVT_F16_F32_dpp_vi:
    case AMDGPU::V_CVT_F32_BF16_dpp_gfx9:
    case AMDGPU::V_CVT_F32_F16_dpp_vi:
    case AMDGPU::V_CVT_F32_F64_dpp_vi:
    case AMDGPU::V_CVT_F64_F32_dpp_vi:
    case AMDGPU::V_CVT_FLR_I32_F32_dpp_vi:
    case AMDGPU::V_CVT_I16_F16_dpp_vi:
    case AMDGPU::V_CVT_I32_F32_dpp_vi:
    case AMDGPU::V_CVT_I32_F64_dpp_vi:
    case AMDGPU::V_CVT_NORM_I16_F16_dpp_vi:
    case AMDGPU::V_CVT_NORM_U16_F16_dpp_vi:
    case AMDGPU::V_CVT_RPI_I32_F32_dpp_vi:
    case AMDGPU::V_CVT_U16_F16_dpp_vi:
    case AMDGPU::V_CVT_U32_F32_dpp_vi:
    case AMDGPU::V_CVT_U32_F64_dpp_vi:
    case AMDGPU::V_EXP_F16_dpp_vi:
    case AMDGPU::V_EXP_F32_dpp_vi:
    case AMDGPU::V_EXP_LEGACY_F32_dpp_vi:
    case AMDGPU::V_FLOOR_F16_dpp_vi:
    case AMDGPU::V_FLOOR_F32_dpp_vi:
    case AMDGPU::V_FLOOR_F64_dpp_vi:
    case AMDGPU::V_FRACT_F16_dpp_vi:
    case AMDGPU::V_FRACT_F32_dpp_vi:
    case AMDGPU::V_FRACT_F64_dpp_vi:
    case AMDGPU::V_FREXP_EXP_I16_F16_dpp_vi:
    case AMDGPU::V_FREXP_EXP_I32_F32_dpp_vi:
    case AMDGPU::V_FREXP_EXP_I32_F64_dpp_vi:
    case AMDGPU::V_FREXP_MANT_F16_dpp_vi:
    case AMDGPU::V_FREXP_MANT_F32_dpp_vi:
    case AMDGPU::V_FREXP_MANT_F64_dpp_vi:
    case AMDGPU::V_LOG_F16_dpp_vi:
    case AMDGPU::V_LOG_F32_dpp_vi:
    case AMDGPU::V_LOG_LEGACY_F32_dpp_vi:
    case AMDGPU::V_RCP_F16_dpp_vi:
    case AMDGPU::V_RCP_F32_dpp_vi:
    case AMDGPU::V_RCP_F64_dpp_vi:
    case AMDGPU::V_RCP_IFLAG_F32_dpp_vi:
    case AMDGPU::V_RNDNE_F16_dpp_vi:
    case AMDGPU::V_RNDNE_F32_dpp_vi:
    case AMDGPU::V_RNDNE_F64_dpp_vi:
    case AMDGPU::V_RSQ_F16_dpp_vi:
    case AMDGPU::V_RSQ_F32_dpp_vi:
    case AMDGPU::V_RSQ_F64_dpp_vi:
    case AMDGPU::V_SIN_F16_dpp_vi:
    case AMDGPU::V_SIN_F32_dpp_vi:
    case AMDGPU::V_SQRT_F16_dpp_vi:
    case AMDGPU::V_SQRT_F32_dpp_vi:
    case AMDGPU::V_SQRT_F64_dpp_vi:
    case AMDGPU::V_TRUNC_F16_dpp_vi:
    case AMDGPU::V_TRUNC_F32_dpp_vi:
    case AMDGPU::V_TRUNC_F64_dpp_vi: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 52;
      case 3:
        // op: src0
        return 32;
      case 4:
        // op: dpp_ctrl
        return 40;
      case 7:
        // op: bound_ctrl
        return 51;
      case 6:
        // op: bank_mask
        return 56;
      case 5:
        // op: row_mask
        return 60;
      case 0:
        // op: vdst
        return 17;
      }
      break;
    }
    case AMDGPU::V_CEIL_F16_dpp_gfx10:
    case AMDGPU::V_CEIL_F16_fake16_dpp_gfx11:
    case AMDGPU::V_CEIL_F16_fake16_dpp_gfx12:
    case AMDGPU::V_CEIL_F16_t16_dpp_gfx11:
    case AMDGPU::V_CEIL_F16_t16_dpp_gfx12:
    case AMDGPU::V_CEIL_F32_dpp_gfx10:
    case AMDGPU::V_CEIL_F32_dpp_gfx11:
    case AMDGPU::V_CEIL_F32_dpp_gfx12:
    case AMDGPU::V_CEIL_F64_dpp_gfx12:
    case AMDGPU::V_COS_BF16V_COS_BF16_fake16_dpp_gfx1250:
    case AMDGPU::V_COS_BF16V_COS_BF16_t16_dpp_gfx1250:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_dpp_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_dpp_gfx12:
    case AMDGPU::V_COS_F16V_COS_F16_t16_dpp_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_t16_dpp_gfx12:
    case AMDGPU::V_COS_F16_dpp_gfx10:
    case AMDGPU::V_COS_F32_dpp_gfx10:
    case AMDGPU::V_COS_F32_dpp_gfx11:
    case AMDGPU::V_COS_F32_dpp_gfx12:
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_fake16_dpp_gfx1250:
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_t16_dpp_gfx1250:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_dpp_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_dpp_gfx12:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_dpp_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_dpp_gfx12:
    case AMDGPU::V_CVT_F16_F32_dpp_gfx10:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_fake16_dpp_gfx1250:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_t16_dpp_gfx1250:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_dpp_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_dpp_gfx12:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_dpp_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_dpp_gfx12:
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_fake16_dpp_gfx1250:
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_t16_dpp_gfx1250:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_dpp_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_dpp_gfx12:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_dpp_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_dpp_gfx12:
    case AMDGPU::V_CVT_F32_F16_dpp_gfx10:
    case AMDGPU::V_CVT_F32_F64_dpp_gfx12:
    case AMDGPU::V_CVT_F64_F32_dpp_gfx12:
    case AMDGPU::V_CVT_FLOOR_I32_F32_dpp_gfx11:
    case AMDGPU::V_CVT_FLOOR_I32_F32_dpp_gfx12:
    case AMDGPU::V_CVT_FLR_I32_F32_dpp_gfx10:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_dpp_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_dpp_gfx12:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_dpp_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_dpp_gfx12:
    case AMDGPU::V_CVT_I16_F16_dpp_gfx10:
    case AMDGPU::V_CVT_I32_F32_dpp_gfx10:
    case AMDGPU::V_CVT_I32_F32_dpp_gfx11:
    case AMDGPU::V_CVT_I32_F32_dpp_gfx12:
    case AMDGPU::V_CVT_I32_F64_dpp_gfx12:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_dpp_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_dpp_gfx12:
    case AMDGPU::V_CVT_NEAREST_I32_F32_dpp_gfx11:
    case AMDGPU::V_CVT_NEAREST_I32_F32_dpp_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_dpp_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_dpp_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_dpp_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_dpp_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16_dpp_gfx10:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_dpp_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_dpp_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_dpp_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_dpp_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16_dpp_gfx10:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_fake16_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_t16_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_fake16_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_t16_dpp_gfx1250:
    case AMDGPU::V_CVT_RPI_I32_F32_dpp_gfx10:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_dpp_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_dpp_gfx12:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_dpp_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_dpp_gfx12:
    case AMDGPU::V_CVT_U16_F16_dpp_gfx10:
    case AMDGPU::V_CVT_U32_F32_dpp_gfx10:
    case AMDGPU::V_CVT_U32_F32_dpp_gfx11:
    case AMDGPU::V_CVT_U32_F32_dpp_gfx12:
    case AMDGPU::V_CVT_U32_F64_dpp_gfx12:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_dpp_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_dpp_gfx12:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_fake16_dpp_gfx1250:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_t16_dpp_gfx1250:
    case AMDGPU::V_EXP_F16_dpp_gfx10:
    case AMDGPU::V_EXP_F16_fake16_dpp_gfx11:
    case AMDGPU::V_EXP_F16_fake16_dpp_gfx12:
    case AMDGPU::V_EXP_F16_t16_dpp_gfx11:
    case AMDGPU::V_EXP_F16_t16_dpp_gfx12:
    case AMDGPU::V_EXP_F32_dpp_gfx10:
    case AMDGPU::V_EXP_F32_dpp_gfx11:
    case AMDGPU::V_EXP_F32_dpp_gfx12:
    case AMDGPU::V_FLOOR_F16_dpp_gfx10:
    case AMDGPU::V_FLOOR_F16_fake16_dpp_gfx11:
    case AMDGPU::V_FLOOR_F16_fake16_dpp_gfx12:
    case AMDGPU::V_FLOOR_F16_t16_dpp_gfx11:
    case AMDGPU::V_FLOOR_F16_t16_dpp_gfx12:
    case AMDGPU::V_FLOOR_F32_dpp_gfx10:
    case AMDGPU::V_FLOOR_F32_dpp_gfx11:
    case AMDGPU::V_FLOOR_F32_dpp_gfx12:
    case AMDGPU::V_FLOOR_F64_dpp_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_dpp_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_dpp_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_dpp_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_dpp_gfx12:
    case AMDGPU::V_FRACT_F16_dpp_gfx10:
    case AMDGPU::V_FRACT_F32_dpp_gfx10:
    case AMDGPU::V_FRACT_F32_dpp_gfx11:
    case AMDGPU::V_FRACT_F32_dpp_gfx12:
    case AMDGPU::V_FRACT_F64_dpp_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_dpp_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_dpp_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_dpp_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_dpp_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16_dpp_gfx10:
    case AMDGPU::V_FREXP_EXP_I32_F32_dpp_gfx10:
    case AMDGPU::V_FREXP_EXP_I32_F32_dpp_gfx11:
    case AMDGPU::V_FREXP_EXP_I32_F32_dpp_gfx12:
    case AMDGPU::V_FREXP_EXP_I32_F64_dpp_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_dpp_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_dpp_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_dpp_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_dpp_gfx12:
    case AMDGPU::V_FREXP_MANT_F16_dpp_gfx10:
    case AMDGPU::V_FREXP_MANT_F32_dpp_gfx10:
    case AMDGPU::V_FREXP_MANT_F32_dpp_gfx11:
    case AMDGPU::V_FREXP_MANT_F32_dpp_gfx12:
    case AMDGPU::V_FREXP_MANT_F64_dpp_gfx12:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_fake16_dpp_gfx1250:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_t16_dpp_gfx1250:
    case AMDGPU::V_LOG_F16_dpp_gfx10:
    case AMDGPU::V_LOG_F16_fake16_dpp_gfx11:
    case AMDGPU::V_LOG_F16_fake16_dpp_gfx12:
    case AMDGPU::V_LOG_F16_t16_dpp_gfx11:
    case AMDGPU::V_LOG_F16_t16_dpp_gfx12:
    case AMDGPU::V_LOG_F32_dpp_gfx10:
    case AMDGPU::V_LOG_F32_dpp_gfx11:
    case AMDGPU::V_LOG_F32_dpp_gfx12:
    case AMDGPU::V_MOV_B16_t16_dpp_gfx11:
    case AMDGPU::V_MOV_B16_t16_dpp_gfx12:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_dpp_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_dpp_gfx12:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_fake16_dpp_gfx1250:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_t16_dpp_gfx1250:
    case AMDGPU::V_RCP_F16_dpp_gfx10:
    case AMDGPU::V_RCP_F16_fake16_dpp_gfx11:
    case AMDGPU::V_RCP_F16_fake16_dpp_gfx12:
    case AMDGPU::V_RCP_F16_t16_dpp_gfx11:
    case AMDGPU::V_RCP_F16_t16_dpp_gfx12:
    case AMDGPU::V_RCP_F32_dpp_gfx10:
    case AMDGPU::V_RCP_F32_dpp_gfx11:
    case AMDGPU::V_RCP_F32_dpp_gfx12:
    case AMDGPU::V_RCP_IFLAG_F32_dpp_gfx10:
    case AMDGPU::V_RCP_IFLAG_F32_dpp_gfx11:
    case AMDGPU::V_RCP_IFLAG_F32_dpp_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_dpp_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_dpp_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_dpp_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_dpp_gfx12:
    case AMDGPU::V_RNDNE_F16_dpp_gfx10:
    case AMDGPU::V_RNDNE_F32_dpp_gfx10:
    case AMDGPU::V_RNDNE_F32_dpp_gfx11:
    case AMDGPU::V_RNDNE_F32_dpp_gfx12:
    case AMDGPU::V_RNDNE_F64_dpp_gfx12:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_fake16_dpp_gfx1250:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_t16_dpp_gfx1250:
    case AMDGPU::V_RSQ_F16_dpp_gfx10:
    case AMDGPU::V_RSQ_F16_fake16_dpp_gfx11:
    case AMDGPU::V_RSQ_F16_fake16_dpp_gfx12:
    case AMDGPU::V_RSQ_F16_t16_dpp_gfx11:
    case AMDGPU::V_RSQ_F16_t16_dpp_gfx12:
    case AMDGPU::V_RSQ_F32_dpp_gfx10:
    case AMDGPU::V_RSQ_F32_dpp_gfx11:
    case AMDGPU::V_RSQ_F32_dpp_gfx12:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_t16_dpp_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_t16_dpp_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_dpp_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_dpp_gfx12:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_fake16_dpp_gfx1250:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_t16_dpp_gfx1250:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_dpp_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_dpp_gfx12:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_dpp_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_dpp_gfx12:
    case AMDGPU::V_SIN_F16_dpp_gfx10:
    case AMDGPU::V_SIN_F32_dpp_gfx10:
    case AMDGPU::V_SIN_F32_dpp_gfx11:
    case AMDGPU::V_SIN_F32_dpp_gfx12:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_fake16_dpp_gfx1250:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_t16_dpp_gfx1250:
    case AMDGPU::V_SQRT_F16_dpp_gfx10:
    case AMDGPU::V_SQRT_F16_fake16_dpp_gfx11:
    case AMDGPU::V_SQRT_F16_fake16_dpp_gfx12:
    case AMDGPU::V_SQRT_F16_t16_dpp_gfx11:
    case AMDGPU::V_SQRT_F16_t16_dpp_gfx12:
    case AMDGPU::V_SQRT_F32_dpp_gfx10:
    case AMDGPU::V_SQRT_F32_dpp_gfx11:
    case AMDGPU::V_SQRT_F32_dpp_gfx12:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_fake16_dpp_gfx1250:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_t16_dpp_gfx1250:
    case AMDGPU::V_TANH_F16V_TANH_F16_fake16_dpp_gfx1250:
    case AMDGPU::V_TANH_F16V_TANH_F16_t16_dpp_gfx1250:
    case AMDGPU::V_TANH_F32_dpp_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_dpp_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_dpp_gfx12:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_dpp_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_dpp_gfx12:
    case AMDGPU::V_TRUNC_F16_dpp_gfx10:
    case AMDGPU::V_TRUNC_F32_dpp_gfx10:
    case AMDGPU::V_TRUNC_F32_dpp_gfx11:
    case AMDGPU::V_TRUNC_F32_dpp_gfx12:
    case AMDGPU::V_TRUNC_F64_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 52;
      case 3:
        // op: src0
        return 32;
      case 4:
        // op: dpp_ctrl
        return 40;
      case 7:
        // op: bound_ctrl
        return 51;
      case 6:
        // op: bank_mask
        return 56;
      case 5:
        // op: row_mask
        return 60;
      case 8:
        // op: fi
        return 50;
      case 0:
        // op: vdst
        return 17;
      }
      break;
    }
    case AMDGPU::V_ADD_F16_dpp_vi:
    case AMDGPU::V_ADD_F32_dpp_vi:
    case AMDGPU::V_CNDMASK_B32_dpp_vi:
    case AMDGPU::V_LDEXP_F16_dpp_vi:
    case AMDGPU::V_MAX_F16_dpp_vi:
    case AMDGPU::V_MAX_F32_dpp_vi:
    case AMDGPU::V_MIN_F16_dpp_vi:
    case AMDGPU::V_MIN_F32_dpp_vi:
    case AMDGPU::V_MUL_F16_dpp_vi:
    case AMDGPU::V_MUL_F32_dpp_vi:
    case AMDGPU::V_MUL_LEGACY_F32_dpp_vi:
    case AMDGPU::V_PK_FMAC_F16_dpp_gfx9:
    case AMDGPU::V_SUBREV_F16_dpp_vi:
    case AMDGPU::V_SUBREV_F32_dpp_vi:
    case AMDGPU::V_SUB_F16_dpp_vi:
    case AMDGPU::V_SUB_F32_dpp_vi: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 52;
      case 3:
        // op: src0
        return 32;
      case 4:
        // op: src1_modifiers
        return 54;
      case 6:
        // op: dpp_ctrl
        return 40;
      case 9:
        // op: bound_ctrl
        return 51;
      case 8:
        // op: bank_mask
        return 56;
      case 7:
        // op: row_mask
        return 60;
      case 0:
        // op: vdst
        return 17;
      case 5:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_ADD_F16_dpp_gfx10:
    case AMDGPU::V_ADD_F16_fake16_dpp_gfx11:
    case AMDGPU::V_ADD_F16_fake16_dpp_gfx12:
    case AMDGPU::V_ADD_F16_t16_dpp_gfx11:
    case AMDGPU::V_ADD_F16_t16_dpp_gfx12:
    case AMDGPU::V_ADD_F32_dpp_gfx10:
    case AMDGPU::V_ADD_F32_dpp_gfx11:
    case AMDGPU::V_ADD_F32_dpp_gfx12:
    case AMDGPU::V_ADD_F64_dpp_gfx12:
    case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
    case AMDGPU::V_CNDMASK_B32_dpp_gfx11:
    case AMDGPU::V_CNDMASK_B32_dpp_gfx12:
    case AMDGPU::V_CNDMASK_B32_dpp_w32_gfx10:
    case AMDGPU::V_CNDMASK_B32_dpp_w32_gfx11:
    case AMDGPU::V_CNDMASK_B32_dpp_w32_gfx12:
    case AMDGPU::V_CNDMASK_B32_dpp_w64_gfx10:
    case AMDGPU::V_CNDMASK_B32_dpp_w64_gfx11:
    case AMDGPU::V_CNDMASK_B32_dpp_w64_gfx12:
    case AMDGPU::V_CVT_PKRTZ_F16_F32_dpp_gfx10:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_dpp_gfx11:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_dpp_gfx12:
    case AMDGPU::V_LDEXP_F16_dpp_gfx10:
    case AMDGPU::V_LDEXP_F16_fake16_dpp_gfx11:
    case AMDGPU::V_LDEXP_F16_fake16_dpp_gfx12:
    case AMDGPU::V_LDEXP_F16_t16_dpp_gfx11:
    case AMDGPU::V_LDEXP_F16_t16_dpp_gfx12:
    case AMDGPU::V_MAX_F16V_MAX_F16_fake16_dpp_gfx11:
    case AMDGPU::V_MAX_F16V_MAX_F16_t16_dpp_gfx11:
    case AMDGPU::V_MAX_F16_dpp_gfx10:
    case AMDGPU::V_MAX_F32_dpp_gfx10:
    case AMDGPU::V_MAX_F32_dpp_gfx11:
    case AMDGPU::V_MAX_NUM_F16_fake16_dpp_gfx12:
    case AMDGPU::V_MAX_NUM_F16_t16_dpp_gfx12:
    case AMDGPU::V_MAX_NUM_F32_dpp_gfx12:
    case AMDGPU::V_MAX_NUM_F64_dpp_gfx12:
    case AMDGPU::V_MIN_F16V_MIN_F16_fake16_dpp_gfx11:
    case AMDGPU::V_MIN_F16V_MIN_F16_t16_dpp_gfx11:
    case AMDGPU::V_MIN_F16_dpp_gfx10:
    case AMDGPU::V_MIN_F32_dpp_gfx10:
    case AMDGPU::V_MIN_F32_dpp_gfx11:
    case AMDGPU::V_MIN_NUM_F16_fake16_dpp_gfx12:
    case AMDGPU::V_MIN_NUM_F16_t16_dpp_gfx12:
    case AMDGPU::V_MIN_NUM_F32_dpp_gfx12:
    case AMDGPU::V_MIN_NUM_F64_dpp_gfx12:
    case AMDGPU::V_MUL_DX9_ZERO_F32_dpp_gfx11:
    case AMDGPU::V_MUL_DX9_ZERO_F32_dpp_gfx12:
    case AMDGPU::V_MUL_F16_dpp_gfx10:
    case AMDGPU::V_MUL_F16_fake16_dpp_gfx11:
    case AMDGPU::V_MUL_F16_fake16_dpp_gfx12:
    case AMDGPU::V_MUL_F16_t16_dpp_gfx11:
    case AMDGPU::V_MUL_F16_t16_dpp_gfx12:
    case AMDGPU::V_MUL_F32_dpp_gfx10:
    case AMDGPU::V_MUL_F32_dpp_gfx11:
    case AMDGPU::V_MUL_F32_dpp_gfx12:
    case AMDGPU::V_MUL_F64_dpp_gfx12:
    case AMDGPU::V_MUL_LEGACY_F32_dpp_gfx10:
    case AMDGPU::V_PK_FMAC_F16_dpp_gfx10:
    case AMDGPU::V_SUBREV_F16_dpp_gfx10:
    case AMDGPU::V_SUBREV_F16_fake16_dpp_gfx11:
    case AMDGPU::V_SUBREV_F16_fake16_dpp_gfx12:
    case AMDGPU::V_SUBREV_F16_t16_dpp_gfx11:
    case AMDGPU::V_SUBREV_F16_t16_dpp_gfx12:
    case AMDGPU::V_SUBREV_F32_dpp_gfx10:
    case AMDGPU::V_SUBREV_F32_dpp_gfx11:
    case AMDGPU::V_SUBREV_F32_dpp_gfx12:
    case AMDGPU::V_SUB_F16_dpp_gfx10:
    case AMDGPU::V_SUB_F16_fake16_dpp_gfx11:
    case AMDGPU::V_SUB_F16_fake16_dpp_gfx12:
    case AMDGPU::V_SUB_F16_t16_dpp_gfx11:
    case AMDGPU::V_SUB_F16_t16_dpp_gfx12:
    case AMDGPU::V_SUB_F32_dpp_gfx10:
    case AMDGPU::V_SUB_F32_dpp_gfx11:
    case AMDGPU::V_SUB_F32_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 52;
      case 3:
        // op: src0
        return 32;
      case 4:
        // op: src1_modifiers
        return 54;
      case 6:
        // op: dpp_ctrl
        return 40;
      case 9:
        // op: bound_ctrl
        return 51;
      case 8:
        // op: bank_mask
        return 56;
      case 7:
        // op: row_mask
        return 60;
      case 10:
        // op: fi
        return 50;
      case 0:
        // op: vdst
        return 17;
      case 5:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_COS_BF16V_COS_BF16_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_fake16_e64_dpp8_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: src0
        return 64;
      case 4:
        // op: dpp8
        return 72;
      case 5:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_COS_BF16V_COS_BF16_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_MOV_B16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MOV_B16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_t16_e64_dpp8_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: src0
        return 64;
      case 5:
        // op: dpp8
        return 72;
      case 6:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_COS_BF16V_COS_BF16_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_fake16_e64_dpp_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 0:
        // op: vdst
        return 0;
      case 4:
        // op: dpp_ctrl
        return 72;
      case 7:
        // op: bound_ctrl
        return 83;
      case 6:
        // op: bank_mask
        return 88;
      case 5:
        // op: row_mask
        return 92;
      case 8:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_COS_BF16V_COS_BF16_t16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_t16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_t16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_t16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_t16_e64_dpp_gfx1250:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_t16_e64_dpp_gfx1250:
    case AMDGPU::V_MOV_B16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MOV_B16_t16_e64_dpp_gfx12:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_e64_dpp_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_e64_dpp_gfx12:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_t16_e64_dpp_gfx1250:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_t16_e64_dpp_gfx1250:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_t16_e64_dpp_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_t16_e64_dpp_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_t16_e64_dpp_gfx1250:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_t16_e64_dpp_gfx1250:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_t16_e64_dpp_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: dpp_ctrl
        return 72;
      case 8:
        // op: bound_ctrl
        return 83;
      case 7:
        // op: bank_mask
        return 88;
      case 6:
        // op: row_mask
        return 92;
      case 9:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_t16_e64_dpp8_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: byte_sel
        return 11;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: src0
        return 64;
      case 6:
        // op: dpp8
        return 72;
      case 7:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_t16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_t16_e64_dpp_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: byte_sel
        return 11;
      case 0:
        // op: vdst
        return 0;
      case 6:
        // op: dpp_ctrl
        return 72;
      case 9:
        // op: bound_ctrl
        return 83;
      case 8:
        // op: bank_mask
        return 88;
      case 7:
        // op: row_mask
        return 92;
      case 10:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_CVT_FLOOR_I32_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_FLOOR_I32_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_NEAREST_I32_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_NEAREST_I32_F32_e64_dpp8_gfx12:
    case AMDGPU::V_FREXP_EXP_I32_F32_e64_dpp8_gfx11:
    case AMDGPU::V_FREXP_EXP_I32_F32_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: src0
        return 64;
      case 5:
        // op: dpp8
        return 72;
      case 6:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CVT_PK_BF8_F16_gfx1250_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_BF8_F16_gfx1250_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_FP8_F16_gfx1250_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_FP8_F16_gfx1250_t16_e64_dpp8_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: src0
        return 64;
      case 6:
        // op: dpp8
        return 72;
      case 7:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CVT_FLOOR_I32_F32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_FLOOR_I32_F32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_NEAREST_I32_F32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_NEAREST_I32_F32_e64_dpp_gfx12:
    case AMDGPU::V_FREXP_EXP_I32_F32_e64_dpp_gfx11:
    case AMDGPU::V_FREXP_EXP_I32_F32_e64_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: dpp_ctrl
        return 72;
      case 8:
        // op: bound_ctrl
        return 83;
      case 7:
        // op: bank_mask
        return 88;
      case 6:
        // op: row_mask
        return 92;
      case 9:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_CVT_PK_BF8_F16_gfx1250_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_BF8_F16_gfx1250_t16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_FP8_F16_gfx1250_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_FP8_F16_gfx1250_t16_e64_dpp_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 6:
        // op: dpp_ctrl
        return 72;
      case 9:
        // op: bound_ctrl
        return 83;
      case 8:
        // op: bank_mask
        return 88;
      case 7:
        // op: row_mask
        return 92;
      case 10:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_CEIL_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CEIL_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CEIL_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CEIL_F32_e64_dpp8_gfx12:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_COS_F32_e64_dpp8_gfx11:
    case AMDGPU::V_COS_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_I32_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_I32_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_U32_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_U32_F32_e64_dpp8_gfx12:
    case AMDGPU::V_EXP_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_EXP_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_EXP_F32_e64_dpp8_gfx11:
    case AMDGPU::V_EXP_F32_e64_dpp8_gfx12:
    case AMDGPU::V_FLOOR_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_FLOOR_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_FLOOR_F32_e64_dpp8_gfx11:
    case AMDGPU::V_FLOOR_F32_e64_dpp8_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_FRACT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_FRACT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_FREXP_MANT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_FREXP_MANT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_LOG_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_LOG_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_LOG_F32_e64_dpp8_gfx11:
    case AMDGPU::V_LOG_F32_e64_dpp8_gfx12:
    case AMDGPU::V_RCP_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_RCP_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_RCP_F32_e64_dpp8_gfx11:
    case AMDGPU::V_RCP_F32_e64_dpp8_gfx12:
    case AMDGPU::V_RCP_IFLAG_F32_e64_dpp8_gfx11:
    case AMDGPU::V_RCP_IFLAG_F32_e64_dpp8_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_RNDNE_F32_e64_dpp8_gfx11:
    case AMDGPU::V_RNDNE_F32_e64_dpp8_gfx12:
    case AMDGPU::V_RSQ_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_RSQ_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_RSQ_F32_e64_dpp8_gfx11:
    case AMDGPU::V_RSQ_F32_e64_dpp8_gfx12:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_SIN_F32_e64_dpp8_gfx11:
    case AMDGPU::V_SIN_F32_e64_dpp8_gfx12:
    case AMDGPU::V_SQRT_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_SQRT_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_SQRT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_SQRT_F32_e64_dpp8_gfx12:
    case AMDGPU::V_TANH_F16V_TANH_F16_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_TANH_F32_e64_dpp8_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_TRUNC_F32_e64_dpp8_gfx11:
    case AMDGPU::V_TRUNC_F32_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: clamp
        return 15;
      case 5:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: src0
        return 64;
      case 6:
        // op: dpp8
        return 72;
      case 7:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CEIL_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CEIL_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_COS_F16V_COS_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_EXP_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_EXP_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_FLOOR_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_FLOOR_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_LOG_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_LOG_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_RCP_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_RCP_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_RSQ_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_RSQ_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_SQRT_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_SQRT_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_TANH_F16V_TANH_F16_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: clamp
        return 15;
      case 5:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: src0
        return 64;
      case 7:
        // op: dpp8
        return 72;
      case 8:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CEIL_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CEIL_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CEIL_F32_e64_dpp_gfx11:
    case AMDGPU::V_CEIL_F32_e64_dpp_gfx12:
    case AMDGPU::V_CEIL_F64_e64_dpp_gfx12:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_COS_F32_e64_dpp_gfx11:
    case AMDGPU::V_COS_F32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F32_F64_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F64_F32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_I32_F32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_I32_F32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_I32_F64_e64_dpp_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_U32_F32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_U32_F32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_U32_F64_e64_dpp_gfx12:
    case AMDGPU::V_EXP_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_EXP_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_EXP_F32_e64_dpp_gfx11:
    case AMDGPU::V_EXP_F32_e64_dpp_gfx12:
    case AMDGPU::V_FLOOR_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_FLOOR_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_FLOOR_F32_e64_dpp_gfx11:
    case AMDGPU::V_FLOOR_F32_e64_dpp_gfx12:
    case AMDGPU::V_FLOOR_F64_e64_dpp_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_FRACT_F32_e64_dpp_gfx11:
    case AMDGPU::V_FRACT_F32_e64_dpp_gfx12:
    case AMDGPU::V_FRACT_F64_e64_dpp_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_FREXP_EXP_I32_F64_e64_dpp_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_FREXP_MANT_F32_e64_dpp_gfx11:
    case AMDGPU::V_FREXP_MANT_F32_e64_dpp_gfx12:
    case AMDGPU::V_FREXP_MANT_F64_e64_dpp_gfx12:
    case AMDGPU::V_LOG_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_LOG_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_LOG_F32_e64_dpp_gfx11:
    case AMDGPU::V_LOG_F32_e64_dpp_gfx12:
    case AMDGPU::V_RCP_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_RCP_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_RCP_F32_e64_dpp_gfx11:
    case AMDGPU::V_RCP_F32_e64_dpp_gfx12:
    case AMDGPU::V_RCP_IFLAG_F32_e64_dpp_gfx11:
    case AMDGPU::V_RCP_IFLAG_F32_e64_dpp_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_RNDNE_F32_e64_dpp_gfx11:
    case AMDGPU::V_RNDNE_F32_e64_dpp_gfx12:
    case AMDGPU::V_RNDNE_F64_e64_dpp_gfx12:
    case AMDGPU::V_RSQ_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_RSQ_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_RSQ_F32_e64_dpp_gfx11:
    case AMDGPU::V_RSQ_F32_e64_dpp_gfx12:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_SIN_F32_e64_dpp_gfx11:
    case AMDGPU::V_SIN_F32_e64_dpp_gfx12:
    case AMDGPU::V_SQRT_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_SQRT_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_SQRT_F32_e64_dpp_gfx11:
    case AMDGPU::V_SQRT_F32_e64_dpp_gfx12:
    case AMDGPU::V_TANH_F16V_TANH_F16_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_TANH_F32_e64_dpp_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_TRUNC_F32_e64_dpp_gfx11:
    case AMDGPU::V_TRUNC_F32_e64_dpp_gfx12:
    case AMDGPU::V_TRUNC_F64_e64_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: clamp
        return 15;
      case 5:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 6:
        // op: dpp_ctrl
        return 72;
      case 9:
        // op: bound_ctrl
        return 83;
      case 8:
        // op: bank_mask
        return 88;
      case 7:
        // op: row_mask
        return 92;
      case 10:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_CEIL_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CEIL_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_COS_F16V_COS_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_EXP_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_EXP_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_FLOOR_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_FLOOR_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_LOG_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_LOG_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_RCP_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_RCP_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_RSQ_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_RSQ_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_SQRT_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_SQRT_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_TANH_F16V_TANH_F16_t16_e64_dpp_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_e64_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: clamp
        return 15;
      case 5:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 7:
        // op: dpp_ctrl
        return 72;
      case 10:
        // op: bound_ctrl
        return 83;
      case 9:
        // op: bank_mask
        return 88;
      case 8:
        // op: row_mask
        return 92;
      case 11:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_AND_B16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_AND_B16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_ASHRREV_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_ASHRREV_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_LSHLREV_B16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_LSHLREV_B16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_LSHRREV_B16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_LSHRREV_B16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MUL_LO_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MUL_LO_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_OR_B16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_OR_B16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_XOR_B16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_XOR_B16_t16_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 3:
        // op: src0
        return 64;
      case 7:
        // op: dpp8
        return 72;
      case 8:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CVT_PK_BF8_F32_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_BF8_F32_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_BF8_F32_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_BF8_F32_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_FP8_F32_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_FP8_F32_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_FP8_F32_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_FP8_F32_t16_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 3:
        // op: src0
        return 64;
      case 8:
        // op: dpp8
        return 72;
      case 9:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CNDMASK_B16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CNDMASK_B16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CNDMASK_B32_e64_dpp8_gfx11:
    case AMDGPU::V_CNDMASK_B32_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 6:
        // op: src2
        return 50;
      case 3:
        // op: src0
        return 64;
      case 7:
        // op: dpp8
        return 72;
      case 8:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CNDMASK_B16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CNDMASK_B16_t16_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 6:
        // op: src2
        return 50;
      case 3:
        // op: src0
        return 64;
      case 8:
        // op: dpp8
        return 72;
      case 9:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CNDMASK_B16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CNDMASK_B16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CNDMASK_B32_e64_dpp_gfx11:
    case AMDGPU::V_CNDMASK_B32_e64_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 6:
        // op: src2
        return 50;
      case 7:
        // op: dpp_ctrl
        return 72;
      case 10:
        // op: bound_ctrl
        return 83;
      case 9:
        // op: bank_mask
        return 88;
      case 8:
        // op: row_mask
        return 92;
      case 11:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_CNDMASK_B16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CNDMASK_B16_t16_e64_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 6:
        // op: src2
        return 50;
      case 8:
        // op: dpp_ctrl
        return 72;
      case 11:
        // op: bound_ctrl
        return 83;
      case 10:
        // op: bank_mask
        return 88;
      case 9:
        // op: row_mask
        return 92;
      case 12:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_AND_B16_t16_e64_dpp_gfx11:
    case AMDGPU::V_AND_B16_t16_e64_dpp_gfx12:
    case AMDGPU::V_ASHRREV_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_ASHRREV_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_LSHLREV_B16_t16_e64_dpp_gfx11:
    case AMDGPU::V_LSHLREV_B16_t16_e64_dpp_gfx12:
    case AMDGPU::V_LSHRREV_B16_t16_e64_dpp_gfx11:
    case AMDGPU::V_LSHRREV_B16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAX_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAX_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAX_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAX_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MIN_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MIN_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MIN_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MIN_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MUL_LO_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MUL_LO_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_OR_B16_t16_e64_dpp_gfx11:
    case AMDGPU::V_OR_B16_t16_e64_dpp_gfx12:
    case AMDGPU::V_XOR_B16_t16_e64_dpp_gfx11:
    case AMDGPU::V_XOR_B16_t16_e64_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 7:
        // op: dpp_ctrl
        return 72;
      case 10:
        // op: bound_ctrl
        return 83;
      case 9:
        // op: bank_mask
        return 88;
      case 8:
        // op: row_mask
        return 92;
      case 11:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_CVT_PK_BF8_F32_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_BF8_F32_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_BF8_F32_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_BF8_F32_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_FP8_F32_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_FP8_F32_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_FP8_F32_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_FP8_F32_t16_e64_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 8:
        // op: dpp_ctrl
        return 72;
      case 11:
        // op: bound_ctrl
        return 83;
      case 10:
        // op: bank_mask
        return 88;
      case 9:
        // op: row_mask
        return 92;
      case 12:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_CVT_PK_I16_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_I16_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_NORM_I16_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_NORM_I16_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_NORM_U16_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_NORM_U16_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_U16_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_U16_F32_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 3:
        // op: src0
        return 64;
      case 7:
        // op: dpp8
        return 72;
      case 8:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_ADD_NC_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_NC_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_ADD_NC_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_NC_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_NC_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_NC_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_NC_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_NC_U16_t16_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 3:
        // op: src0
        return 64;
      case 8:
        // op: dpp8
        return 72;
      case 9:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CVT_PK_FP8_F32_gfx1250_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_FP8_F32_gfx1250_t16_e64_dpp8_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 3:
        // op: src0
        return 64;
      case 9:
        // op: dpp8
        return 72;
      case 10:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CVT_PK_I16_F32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_I16_F32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_NORM_I16_F32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_NORM_I16_F32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_NORM_U16_F32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_NORM_U16_F32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_U16_F32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_U16_F32_e64_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 7:
        // op: dpp_ctrl
        return 72;
      case 10:
        // op: bound_ctrl
        return 83;
      case 9:
        // op: bank_mask
        return 88;
      case 8:
        // op: row_mask
        return 92;
      case 11:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_ADD_NC_I16V_ADD_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_ADD_NC_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_ADD_NC_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_ADD_NC_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_ADD_NC_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_NORM_I16_F16V_CVT_PKNORM_I16_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_NORM_U16_F16V_CVT_PKNORM_U16_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_PACK_B32_F16V_PACK_B32_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_SUB_NC_I16V_SUB_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_SUB_NC_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_SUB_NC_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_SUB_NC_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_SUB_NC_U16_t16_e64_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 8:
        // op: dpp_ctrl
        return 72;
      case 11:
        // op: bound_ctrl
        return 83;
      case 10:
        // op: bank_mask
        return 88;
      case 9:
        // op: row_mask
        return 92;
      case 12:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_CVT_PK_FP8_F32_gfx1250_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_FP8_F32_gfx1250_t16_e64_dpp_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 9:
        // op: dpp_ctrl
        return 72;
      case 12:
        // op: bound_ctrl
        return 83;
      case 11:
        // op: bank_mask
        return 88;
      case 10:
        // op: row_mask
        return 92;
      case 13:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_ADD_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_ADD_F32_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_PK_BF16_F32_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_F16_F32_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_e64_dpp8_gfx12:
    case AMDGPU::V_LDEXP_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_LDEXP_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_LDEXP_F32_e64_dpp8_gfx11:
    case AMDGPU::V_LDEXP_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MAXIMUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MAX_F16V_MAX_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX_F32_e64_dpp8_gfx11:
    case AMDGPU::V_MAX_NUM_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX_NUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MINIMUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MIN_F16V_MIN_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN_F32_e64_dpp8_gfx11:
    case AMDGPU::V_MIN_NUM_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN_NUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MUL_DX9_ZERO_F32_e64_dpp8_gfx11:
    case AMDGPU::V_MUL_DX9_ZERO_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MUL_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MUL_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MUL_F32_e64_dpp8_gfx11:
    case AMDGPU::V_MUL_F32_e64_dpp8_gfx12:
    case AMDGPU::V_SUBREV_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_SUBREV_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_SUBREV_F32_e64_dpp8_gfx11:
    case AMDGPU::V_SUBREV_F32_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_F32_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_F32_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: clamp
        return 15;
      case 7:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 3:
        // op: src0
        return 64;
      case 8:
        // op: dpp8
        return 72;
      case 9:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_ADD_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_LDEXP_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_LDEXP_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAXIMUM_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAXIMUM_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX_F16V_MAX_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX_NUM_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MINIMUM_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MINIMUM_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN_F16V_MIN_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN_NUM_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MUL_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MUL_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_SUBREV_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_SUBREV_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_F16_t16_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: clamp
        return 15;
      case 7:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 3:
        // op: src0
        return 64;
      case 9:
        // op: dpp8
        return 72;
      case 10:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_ADD_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_ADD_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_ADD_F32_e64_dpp_gfx11:
    case AMDGPU::V_ADD_F32_e64_dpp_gfx12:
    case AMDGPU::V_ADD_F64_e64_dpp_gfx12:
    case AMDGPU::V_CVT_PK_BF16_F32_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_F16_F32_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_e64_dpp_gfx12:
    case AMDGPU::V_LDEXP_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_LDEXP_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_LDEXP_F32_e64_dpp_gfx11:
    case AMDGPU::V_LDEXP_F32_e64_dpp_gfx12:
    case AMDGPU::V_LDEXP_F64_e64_dpp_gfx1250:
    case AMDGPU::V_MAXIMUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MAXIMUM_F64_e64_dpp_gfx11:
    case AMDGPU::V_MAXIMUM_F64_e64_dpp_gfx12:
    case AMDGPU::V_MAX_F16V_MAX_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAX_F32_e64_dpp_gfx11:
    case AMDGPU::V_MAX_NUM_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAX_NUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MAX_NUM_F64_e64_dpp_gfx12:
    case AMDGPU::V_MINIMUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MINIMUM_F64_e64_dpp_gfx11:
    case AMDGPU::V_MINIMUM_F64_e64_dpp_gfx12:
    case AMDGPU::V_MIN_F16V_MIN_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MIN_F32_e64_dpp_gfx11:
    case AMDGPU::V_MIN_NUM_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MIN_NUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MIN_NUM_F64_e64_dpp_gfx12:
    case AMDGPU::V_MUL_DX9_ZERO_F32_e64_dpp_gfx11:
    case AMDGPU::V_MUL_DX9_ZERO_F32_e64_dpp_gfx12:
    case AMDGPU::V_MUL_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MUL_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MUL_F32_e64_dpp_gfx11:
    case AMDGPU::V_MUL_F32_e64_dpp_gfx12:
    case AMDGPU::V_MUL_F64_e64_dpp_gfx12:
    case AMDGPU::V_SUBREV_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_SUBREV_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_SUBREV_F32_e64_dpp_gfx11:
    case AMDGPU::V_SUBREV_F32_e64_dpp_gfx12:
    case AMDGPU::V_SUB_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_SUB_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_SUB_F32_e64_dpp_gfx11:
    case AMDGPU::V_SUB_F32_e64_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: clamp
        return 15;
      case 7:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 8:
        // op: dpp_ctrl
        return 72;
      case 11:
        // op: bound_ctrl
        return 83;
      case 10:
        // op: bank_mask
        return 88;
      case 9:
        // op: row_mask
        return 92;
      case 12:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_ADD_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_ADD_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_LDEXP_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_LDEXP_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAXIMUM_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAXIMUM_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAX_F16V_MAX_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAX_NUM_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MINIMUM_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MINIMUM_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MIN_F16V_MIN_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MIN_NUM_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MUL_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MUL_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_SUBREV_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_SUBREV_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_SUB_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_SUB_F16_t16_e64_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: clamp
        return 15;
      case 7:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 9:
        // op: dpp_ctrl
        return 72;
      case 12:
        // op: bound_ctrl
        return 83;
      case 11:
        // op: bank_mask
        return 88;
      case 10:
        // op: row_mask
        return 92;
      case 13:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_CVT_SR_FP8_F32_gfx1250_e64_dpp8_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: clamp
        return 15;
      case 8:
        // op: byte_sel
        return 13;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 3:
        // op: src0
        return 64;
      case 9:
        // op: dpp8
        return 72;
      case 10:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CVT_SR_FP8_F32_gfx1250_e64_dpp_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: clamp
        return 15;
      case 8:
        // op: byte_sel
        return 13;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 9:
        // op: dpp_ctrl
        return 72;
      case 12:
        // op: bound_ctrl
        return 83;
      case 11:
        // op: bank_mask
        return 88;
      case 10:
        // op: row_mask
        return 92;
      case 13:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_ASHR_PK_I8_I32_e64_dpp8_gfx1250:
    case AMDGPU::V_ASHR_PK_U8_I32_e64_dpp8_gfx1250:
    case AMDGPU::V_DOT2_BF16_BF16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_DOT2_BF16_BF16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_DOT2_BF16_BF16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_DOT2_BF16_BF16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_DOT2_F16_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_DOT2_F16_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_DOT2_F16_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_DOT2_F16_F16_t16_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: src2_modifiers
        return 10;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 7:
        // op: src2
        return 50;
      case 3:
        // op: src0
        return 64;
      case 9:
        // op: dpp8
        return 72;
      case 10:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_ASHR_PK_I8_I32_e64_dpp_gfx1250:
    case AMDGPU::V_ASHR_PK_U8_I32_e64_dpp_gfx1250:
    case AMDGPU::V_DOT2_BF16_BF16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_DOT2_BF16_BF16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_DOT2_BF16_BF16_t16_e64_dpp_gfx11:
    case AMDGPU::V_DOT2_BF16_BF16_t16_e64_dpp_gfx12:
    case AMDGPU::V_DOT2_F16_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_DOT2_F16_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_DOT2_F16_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_DOT2_F16_F16_t16_e64_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: src2_modifiers
        return 10;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 7:
        // op: src2
        return 50;
      case 9:
        // op: dpp_ctrl
        return 72;
      case 12:
        // op: bound_ctrl
        return 83;
      case 11:
        // op: bank_mask
        return 88;
      case 10:
        // op: row_mask
        return 92;
      case 13:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_fake16_e64_dpp_gfx11:
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_fake16_e64_dpp_gfx12:
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_t16_e64_dpp_gfx11:
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_t16_e64_dpp_gfx12:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_fake16_e64_dpp_gfx11:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_fake16_e64_dpp_gfx12:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_t16_e64_dpp_gfx11:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAX3_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAX3_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAX3_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAX3_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAX3_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAX3_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAX3_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAX3_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MED3_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MED3_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MED3_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MED3_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MED3_U16V_MED3_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MED3_U16V_MED3_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MED3_U16V_MED3_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MED3_U16V_MED3_U16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_t16_e64_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: src2_modifiers
        return 10;
      case 8:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 7:
        // op: src2
        return 50;
      case 10:
        // op: dpp_ctrl
        return 72;
      case 13:
        // op: bound_ctrl
        return 83;
      case 12:
        // op: bank_mask
        return 88;
      case 11:
        // op: row_mask
        return 92;
      case 14:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_FMA_MIX_F32_BF16_dpp_gfx1250:
    case AMDGPU::V_FMA_MIX_F32_dpp_gfx11:
    case AMDGPU::V_FMA_MIX_F32_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: src2_modifiers
        return 10;
      case 8:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 7:
        // op: src2
        return 50;
      case 11:
        // op: dpp_ctrl
        return 72;
      case 14:
        // op: bound_ctrl
        return 83;
      case 13:
        // op: bank_mask
        return 88;
      case 12:
        // op: row_mask
        return 92;
      case 15:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_FMA_MIXHI_BF16_dpp_gfx1250:
    case AMDGPU::V_FMA_MIXHI_F16_dpp_gfx11:
    case AMDGPU::V_FMA_MIXHI_F16_dpp_gfx12:
    case AMDGPU::V_FMA_MIXLO_BF16_dpp_gfx1250:
    case AMDGPU::V_FMA_MIXLO_F16_dpp_gfx11:
    case AMDGPU::V_FMA_MIXLO_F16_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: src2_modifiers
        return 10;
      case 8:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 7:
        // op: src2
        return 50;
      case 12:
        // op: dpp_ctrl
        return 72;
      case 15:
        // op: bound_ctrl
        return 83;
      case 14:
        // op: bank_mask
        return 88;
      case 13:
        // op: row_mask
        return 92;
      case 16:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_DOT2_F32_BF16_dpp_gfx11:
    case AMDGPU::V_DOT2_F32_BF16_dpp_gfx12:
    case AMDGPU::V_DOT2_F32_F16_dpp_gfx11:
    case AMDGPU::V_DOT2_F32_F16_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: src2_modifiers
        return 10;
      case 8:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 7:
        // op: src2
        return 50;
      case 13:
        // op: dpp_ctrl
        return 72;
      case 16:
        // op: bound_ctrl
        return 83;
      case 15:
        // op: bank_mask
        return 88;
      case 14:
        // op: row_mask
        return 92;
      case 17:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_t16_e64_dpp8_gfx11:
    case AMDGPU::V_ALIGNBIT_B32V_ALIGNBIT_B32_t16_e64_dpp8_gfx12:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_t16_e64_dpp8_gfx11:
    case AMDGPU::V_ALIGNBYTE_B32V_ALIGNBYTE_B32_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAD_I16V_MAD_I16_gfx9_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAD_I32_I16V_MAD_I32_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAD_U16V_MAD_U16_gfx9_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAD_U32_U16V_MAD_U32_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX3_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX3_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX3_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX3_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX3_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX3_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX3_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX3_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MED3_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MED3_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MED3_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MED3_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MED3_U16V_MED3_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MED3_U16V_MED3_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MED3_U16V_MED3_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MED3_U16V_MED3_U16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN3_I16V_MIN3_I16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN3_U16V_MIN3_U16_t16_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: src2_modifiers
        return 10;
      case 8:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 7:
        // op: src2
        return 50;
      case 3:
        // op: src0
        return 64;
      case 10:
        // op: dpp8
        return 72;
      case 11:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_FMA_MIX_F32_BF16_dpp8_gfx1250:
    case AMDGPU::V_FMA_MIX_F32_dpp8_gfx11:
    case AMDGPU::V_FMA_MIX_F32_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: src2_modifiers
        return 10;
      case 8:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 7:
        // op: src2
        return 50;
      case 3:
        // op: src0
        return 64;
      case 11:
        // op: dpp8
        return 72;
      case 12:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_FMA_MIXHI_BF16_dpp8_gfx1250:
    case AMDGPU::V_FMA_MIXHI_F16_dpp8_gfx11:
    case AMDGPU::V_FMA_MIXHI_F16_dpp8_gfx12:
    case AMDGPU::V_FMA_MIXLO_BF16_dpp8_gfx1250:
    case AMDGPU::V_FMA_MIXLO_F16_dpp8_gfx11:
    case AMDGPU::V_FMA_MIXLO_F16_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: src2_modifiers
        return 10;
      case 8:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 7:
        // op: src2
        return 50;
      case 3:
        // op: src0
        return 64;
      case 12:
        // op: dpp8
        return 72;
      case 13:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_DOT2_F32_BF16_dpp8_gfx11:
    case AMDGPU::V_DOT2_F32_BF16_dpp8_gfx12:
    case AMDGPU::V_DOT2_F32_F16_dpp8_gfx11:
    case AMDGPU::V_DOT2_F32_F16_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: src2_modifiers
        return 10;
      case 8:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 7:
        // op: src2
        return 50;
      case 3:
        // op: src0
        return 64;
      case 13:
        // op: dpp8
        return 72;
      case 14:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CVT_PK_U8_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_U8_F32_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: src2_modifiers
        return 10;
      case 8:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 7:
        // op: src2
        return 50;
      case 3:
        // op: src0
        return 64;
      case 9:
        // op: dpp8
        return 72;
      case 10:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CVT_PK_U8_F32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_PK_U8_F32_e64_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: src2_modifiers
        return 10;
      case 8:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 7:
        // op: src2
        return 50;
      case 9:
        // op: dpp_ctrl
        return 72;
      case 12:
        // op: bound_ctrl
        return 83;
      case 11:
        // op: bank_mask
        return 88;
      case 10:
        // op: row_mask
        return 92;
      case 13:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_CUBEID_F32_e64_dpp_gfx11:
    case AMDGPU::V_CUBEID_F32_e64_dpp_gfx12:
    case AMDGPU::V_CUBEMA_F32_e64_dpp_gfx11:
    case AMDGPU::V_CUBEMA_F32_e64_dpp_gfx12:
    case AMDGPU::V_CUBESC_F32_e64_dpp_gfx11:
    case AMDGPU::V_CUBESC_F32_e64_dpp_gfx12:
    case AMDGPU::V_CUBETC_F32_e64_dpp_gfx11:
    case AMDGPU::V_CUBETC_F32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_SR_PK_BF16_F32_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_SR_PK_F16_F32_e64_dpp_gfx1250:
    case AMDGPU::V_DIV_FIXUP_F64_e64_dpp_gfx1250:
    case AMDGPU::V_DIV_FMAS_F64_e64_dpp_gfx1250:
    case AMDGPU::V_FMA_F32_e64_dpp_gfx11:
    case AMDGPU::V_FMA_F32_e64_dpp_gfx12:
    case AMDGPU::V_FMA_F64_e64_dpp_gfx1250:
    case AMDGPU::V_MAX3_F32_e64_dpp_gfx11:
    case AMDGPU::V_MAX3_NUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MAXIMUM3_F32_e64_dpp_gfx12:
    case AMDGPU::V_MAXIMUMMINIMUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MAXMIN_F32_e64_dpp_gfx11:
    case AMDGPU::V_MAXMIN_NUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MED3_F32_e64_dpp_gfx11:
    case AMDGPU::V_MED3_NUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MIN3_F32_e64_dpp_gfx11:
    case AMDGPU::V_MIN3_NUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MINIMUM3_F32_e64_dpp_gfx12:
    case AMDGPU::V_MINIMUMMAXIMUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MINMAX_F32_e64_dpp_gfx11:
    case AMDGPU::V_MINMAX_NUM_F32_e64_dpp_gfx12:
    case AMDGPU::V_MULLIT_F32_e64_dpp_gfx11:
    case AMDGPU::V_MULLIT_F32_e64_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: src2_modifiers
        return 10;
      case 8:
        // op: clamp
        return 15;
      case 9:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 7:
        // op: src2
        return 50;
      case 10:
        // op: dpp_ctrl
        return 72;
      case 13:
        // op: bound_ctrl
        return 83;
      case 12:
        // op: bank_mask
        return 88;
      case 11:
        // op: row_mask
        return 92;
      case 14:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_fake16_e64_dpp_gfx11:
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_fake16_e64_dpp_gfx12:
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_t16_e64_dpp_gfx11:
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_t16_e64_dpp_gfx12:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_fake16_e64_dpp_gfx11:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_fake16_e64_dpp_gfx12:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_t16_e64_dpp_gfx11:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAX3_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAX3_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAX3_NUM_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAX3_NUM_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAXIMUM3_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAXIMUM3_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAXIMUMMINIMUM_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAXIMUMMINIMUM_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MAXMIN_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MAXMIN_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MAXMIN_NUM_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MAXMIN_NUM_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MED3_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MED3_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MED3_NUM_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MED3_NUM_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MIN3_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MIN3_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MIN3_NUM_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MIN3_NUM_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MINIMUM3_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MINIMUM3_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MINIMUMMAXIMUM_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MINIMUMMAXIMUM_F16_t16_e64_dpp_gfx12:
    case AMDGPU::V_MINMAX_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_MINMAX_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_MINMAX_NUM_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_MINMAX_NUM_F16_t16_e64_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: src2_modifiers
        return 10;
      case 8:
        // op: clamp
        return 15;
      case 9:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 7:
        // op: src2
        return 50;
      case 11:
        // op: dpp_ctrl
        return 72;
      case 14:
        // op: bound_ctrl
        return 83;
      case 13:
        // op: bank_mask
        return 88;
      case 12:
        // op: row_mask
        return 92;
      case 15:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_CUBEID_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CUBEID_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CUBEMA_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CUBEMA_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CUBESC_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CUBESC_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CUBETC_F32_e64_dpp8_gfx11:
    case AMDGPU::V_CUBETC_F32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_SR_PK_BF16_F32_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_SR_PK_F16_F32_e64_dpp8_gfx1250:
    case AMDGPU::V_FMA_F32_e64_dpp8_gfx11:
    case AMDGPU::V_FMA_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MAX3_F32_e64_dpp8_gfx11:
    case AMDGPU::V_MAX3_NUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MAXIMUM3_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MAXIMUMMINIMUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MAXMIN_F32_e64_dpp8_gfx11:
    case AMDGPU::V_MAXMIN_NUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MED3_F32_e64_dpp8_gfx11:
    case AMDGPU::V_MED3_NUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MIN3_F32_e64_dpp8_gfx11:
    case AMDGPU::V_MIN3_NUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MINIMUM3_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MINIMUMMAXIMUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MINMAX_F32_e64_dpp8_gfx11:
    case AMDGPU::V_MINMAX_NUM_F32_e64_dpp8_gfx12:
    case AMDGPU::V_MULLIT_F32_e64_dpp8_gfx11:
    case AMDGPU::V_MULLIT_F32_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: src2_modifiers
        return 10;
      case 8:
        // op: clamp
        return 15;
      case 9:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 7:
        // op: src2
        return 50;
      case 3:
        // op: src0
        return 64;
      case 10:
        // op: dpp8
        return 72;
      case 11:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_t16_e64_dpp8_gfx11:
    case AMDGPU::V_DIV_FIXUP_F16V_DIV_FIXUP_F16_gfx9_t16_e64_dpp8_gfx12:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_t16_e64_dpp8_gfx11:
    case AMDGPU::V_FMA_F16V_FMA_F16_gfx9_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX3_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX3_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAX3_NUM_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAX3_NUM_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAXIMUM3_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAXIMUM3_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAXIMUMMINIMUM_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAXIMUMMINIMUM_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MAXMIN_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MAXMIN_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MAXMIN_NUM_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MAXMIN_NUM_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MED3_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MED3_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MED3_NUM_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MED3_NUM_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN3_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN3_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MIN3_NUM_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MIN3_NUM_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MINIMUM3_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MINIMUM3_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MINIMUMMAXIMUM_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MINIMUMMAXIMUM_F16_t16_e64_dpp8_gfx12:
    case AMDGPU::V_MINMAX_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_MINMAX_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_MINMAX_NUM_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_MINMAX_NUM_F16_t16_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 6:
        // op: src2_modifiers
        return 10;
      case 8:
        // op: clamp
        return 15;
      case 9:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 7:
        // op: src2
        return 50;
      case 3:
        // op: src0
        return 64;
      case 11:
        // op: dpp8
        return 72;
      case 12:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 7:
        // op: byte_sel
        return 13;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 3:
        // op: src0
        return 64;
      case 8:
        // op: dpp8
        return 72;
      case 9:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CVT_SR_BF8_F16_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_SR_BF8_F16_t16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_SR_FP8_F16_fake16_e64_dpp8_gfx1250:
    case AMDGPU::V_CVT_SR_FP8_F16_t16_e64_dpp8_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 7:
        // op: byte_sel
        return 13;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 3:
        // op: src0
        return 64;
      case 9:
        // op: dpp8
        return 72;
      case 10:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp_gfx11:
    case AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp_gfx12:
    case AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp_gfx11:
    case AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 7:
        // op: byte_sel
        return 13;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 8:
        // op: dpp_ctrl
        return 72;
      case 11:
        // op: bound_ctrl
        return 83;
      case 10:
        // op: bank_mask
        return 88;
      case 9:
        // op: row_mask
        return 92;
      case 12:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_CVT_SR_BF8_F16_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_SR_BF8_F16_t16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_SR_FP8_F16_fake16_e64_dpp_gfx1250:
    case AMDGPU::V_CVT_SR_FP8_F16_t16_e64_dpp_gfx1250: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 7:
        // op: byte_sel
        return 13;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 9:
        // op: dpp_ctrl
        return 72;
      case 12:
        // op: bound_ctrl
        return 83;
      case 11:
        // op: bank_mask
        return 88;
      case 10:
        // op: row_mask
        return 92;
      case 13:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_FMAC_F16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_FMAC_F16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_FMAC_F32_e64_dpp_gfx11:
    case AMDGPU::V_FMAC_F32_e64_dpp_gfx12:
    case AMDGPU::V_FMAC_F64_e64_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 8:
        // op: clamp
        return 15;
      case 9:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 10:
        // op: dpp_ctrl
        return 72;
      case 13:
        // op: bound_ctrl
        return 83;
      case 12:
        // op: bank_mask
        return 88;
      case 11:
        // op: row_mask
        return 92;
      case 14:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_FMAC_F16_t16_e64_dpp_gfx11:
    case AMDGPU::V_FMAC_F16_t16_e64_dpp_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 8:
        // op: clamp
        return 15;
      case 9:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 11:
        // op: dpp_ctrl
        return 72;
      case 14:
        // op: bound_ctrl
        return 83;
      case 13:
        // op: bank_mask
        return 88;
      case 12:
        // op: row_mask
        return 92;
      case 15:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_FMAC_F16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_FMAC_F16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_FMAC_F32_e64_dpp8_gfx11:
    case AMDGPU::V_FMAC_F32_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 8:
        // op: clamp
        return 15;
      case 9:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 3:
        // op: src0
        return 64;
      case 10:
        // op: dpp8
        return 72;
      case 11:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_FMAC_F16_t16_e64_dpp8_gfx11:
    case AMDGPU::V_FMAC_F16_t16_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src0_modifiers
        return 8;
      case 4:
        // op: src1_modifiers
        return 9;
      case 8:
        // op: clamp
        return 15;
      case 9:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: src1
        return 41;
      case 3:
        // op: src0
        return 64;
      case 11:
        // op: dpp8
        return 72;
      case 12:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CMP_EQ_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_F_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_F_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CMP_T_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CMP_T_U32_e64_dpp8_gfx11: {
      switch (OpNum) {
      case 2:
        // op: src1
        return 41;
      case 1:
        // op: src0
        return 64;
      case 3:
        // op: dpp8
        return 72;
      case 4:
        // op: fi
        return 32;
      case 0:
        // op: sdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CMP_EQ_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_F_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_F_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GE_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GE_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GE_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GE_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GT_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GT_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GT_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GT_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GT_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GT_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_GT_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_GT_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LE_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LE_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LE_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LE_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LE_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LE_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LE_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LE_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LT_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LT_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LT_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LT_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LT_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LT_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_LT_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_LT_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NE_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NE_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NE_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NE_I32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NE_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NE_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CMP_NE_U32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_NE_U32_e64_dpp_gfx12:
    case AMDGPU::V_CMP_T_I32_e64_dpp_gfx11:
    case AMDGPU::V_CMP_T_U32_e64_dpp_gfx11: {
      switch (OpNum) {
      case 2:
        // op: src1
        return 41;
      case 3:
        // op: dpp_ctrl
        return 72;
      case 6:
        // op: bound_ctrl
        return 83;
      case 5:
        // op: bank_mask
        return 88;
      case 4:
        // op: row_mask
        return 92;
      case 7:
        // op: fi
        return 82;
      case 1:
        // op: src0
        return 64;
      case 0:
        // op: sdst
        return 0;
      }
      break;
    }
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp_w64_gfx12: {
      switch (OpNum) {
      case 2:
        // op: src1
        return 9;
      case 0:
        // op: src0_modifiers
        return 52;
      case 1:
        // op: src0
        return 32;
      case 3:
        // op: dpp_ctrl
        return 40;
      case 6:
        // op: bound_ctrl
        return 51;
      case 5:
        // op: bank_mask
        return 56;
      case 4:
        // op: row_mask
        return 60;
      case 7:
        // op: fi
        return 50;
      }
      break;
    }
    case AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_DWORD_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_SBYTE_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_SSHORT_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_UBYTE_SADDR_vi:
    case AMDGPU::GLOBAL_LOAD_USHORT_SADDR_vi: {
      switch (OpNum) {
      case 2:
        // op: vaddr
        return 32;
      case 1:
        // op: saddr
        return 48;
      case 0:
        // op: vdst
        return 55;
      case 4:
        // op: cpol
        return 16;
      case 3:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_DWORD_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_SBYTE_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_SSHORT_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_UBYTE_SADDR_gfx10:
    case AMDGPU::GLOBAL_LOAD_USHORT_SADDR_gfx10: {
      switch (OpNum) {
      case 2:
        // op: vaddr
        return 32;
      case 1:
        // op: saddr
        return 48;
      case 0:
        // op: vdst
        return 56;
      case 4:
        // op: cpol
        return 12;
      case 3:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_DWORD_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_SBYTE_D16_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_SBYTE_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_SSHORT_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_UBYTE_SADDR_gfx11:
    case AMDGPU::GLOBAL_LOAD_USHORT_SADDR_gfx11: {
      switch (OpNum) {
      case 2:
        // op: vaddr
        return 32;
      case 1:
        // op: saddr
        return 48;
      case 0:
        // op: vdst
        return 56;
      case 4:
        // op: cpol
        return 13;
      case 3:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::V_CVT_F32_BF8_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_FP8_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_FP8_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 3:
        // op: byte_sel
        return 11;
      case 0:
        // op: vdst
        return 0;
      case 2:
        // op: src0
        return 64;
      case 4:
        // op: dpp8
        return 72;
      case 5:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CVT_F32_BF8_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F32_FP8_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F32_FP8_e64_dpp_gfx12: {
      switch (OpNum) {
      case 3:
        // op: byte_sel
        return 11;
      case 0:
        // op: vdst
        return 0;
      case 4:
        // op: dpp_ctrl
        return 72;
      case 7:
        // op: bound_ctrl
        return 83;
      case 6:
        // op: bank_mask
        return 88;
      case 5:
        // op: row_mask
        return 92;
      case 8:
        // op: fi
        return 82;
      case 2:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_CVT_F32_FP8_e64_dpp8_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: clamp
        return 15;
      case 4:
        // op: byte_sel
        return 11;
      case 0:
        // op: vdst
        return 0;
      case 2:
        // op: src0
        return 64;
      case 5:
        // op: dpp8
        return 72;
      case 6:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CVT_F32_FP8_e64_dpp_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: clamp
        return 15;
      case 4:
        // op: byte_sel
        return 11;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: dpp_ctrl
        return 72;
      case 8:
        // op: bound_ctrl
        return 83;
      case 7:
        // op: bank_mask
        return 88;
      case 6:
        // op: row_mask
        return 92;
      case 9:
        // op: fi
        return 82;
      case 2:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_I32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_I32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_U32_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_U32_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE0_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE0_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE1_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE1_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE2_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE2_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE3_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE3_e64_dpp8_gfx12:
    case AMDGPU::V_CVT_OFF_F32_I4_e64_dpp8_gfx11:
    case AMDGPU::V_CVT_OFF_F32_I4_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 3:
        // op: clamp
        return 15;
      case 4:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 2:
        // op: src0
        return 64;
      case 5:
        // op: dpp8
        return 72;
      case 6:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_fake16_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F32_I32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F32_I32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F32_U32_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F32_U32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE0_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE0_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE1_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE1_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE2_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE2_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F32_UBYTE3_e64_dpp_gfx11:
    case AMDGPU::V_CVT_F32_UBYTE3_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F64_I32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_F64_U32_e64_dpp_gfx12:
    case AMDGPU::V_CVT_OFF_F32_I4_e64_dpp_gfx11:
    case AMDGPU::V_CVT_OFF_F32_I4_e64_dpp_gfx12: {
      switch (OpNum) {
      case 3:
        // op: clamp
        return 15;
      case 4:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 5:
        // op: dpp_ctrl
        return 72;
      case 8:
        // op: bound_ctrl
        return 83;
      case 7:
        // op: bank_mask
        return 88;
      case 6:
        // op: row_mask
        return 92;
      case 9:
        // op: fi
        return 82;
      case 2:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::SCRATCH_STORE_BLOCK_gfx12:
    case AMDGPU::SCRATCH_STORE_BYTE_D16_HI_gfx12:
    case AMDGPU::SCRATCH_STORE_BYTE_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX2_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX3_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORDX4_gfx12:
    case AMDGPU::SCRATCH_STORE_DWORD_gfx12:
    case AMDGPU::SCRATCH_STORE_SHORT_D16_HI_gfx12:
    case AMDGPU::SCRATCH_STORE_SHORT_gfx12: {
      switch (OpNum) {
      case 3:
        // op: cpol
        return 7;
      case 0:
        // op: vdata
        return 55;
      case 1:
        // op: vaddr
        return 64;
      case 2:
        // op: offset
        return 72;
      }
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_F32_gfx12:
    case AMDGPU::FLAT_ATOMIC_ADD_F64_gfx1250:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_ADD_gfx12:
    case AMDGPU::FLAT_ATOMIC_AND_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_AND_gfx12:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_gfx12:
    case AMDGPU::FLAT_ATOMIC_COND_SUB_U32_gfx12:
    case AMDGPU::FLAT_ATOMIC_CSUB_U32_gfx12:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_DEC_gfx12:
    case AMDGPU::FLAT_ATOMIC_FMAX_gfx12:
    case AMDGPU::FLAT_ATOMIC_FMIN_gfx12:
    case AMDGPU::FLAT_ATOMIC_INC_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_INC_gfx12:
    case AMDGPU::FLAT_ATOMIC_MAX_F64_gfx1250:
    case AMDGPU::FLAT_ATOMIC_MIN_F64_gfx1250:
    case AMDGPU::FLAT_ATOMIC_OR_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_OR_gfx12:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_BF16_gfx12:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_F16_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMAX_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMIN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_SUB_gfx12:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_SWAP_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMAX_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMIN_gfx12:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_gfx12:
    case AMDGPU::FLAT_ATOMIC_XOR_gfx12:
    case AMDGPU::FLAT_STORE_BYTE_D16_HI_gfx12:
    case AMDGPU::FLAT_STORE_BYTE_gfx12:
    case AMDGPU::FLAT_STORE_DWORDX2_gfx12:
    case AMDGPU::FLAT_STORE_DWORDX3_gfx12:
    case AMDGPU::FLAT_STORE_DWORDX4_gfx12:
    case AMDGPU::FLAT_STORE_DWORD_gfx12:
    case AMDGPU::FLAT_STORE_SHORT_D16_HI_gfx12:
    case AMDGPU::FLAT_STORE_SHORT_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_AND_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CSUB_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_DEC_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_INC_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_OR_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SUB_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_XOR_gfx12:
    case AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B128_gfx1250:
    case AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B32_gfx1250:
    case AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B64_gfx1250:
    case AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B8_gfx1250:
    case AMDGPU::GLOBAL_STORE_BLOCK_gfx12:
    case AMDGPU::GLOBAL_STORE_BYTE_D16_HI_gfx12:
    case AMDGPU::GLOBAL_STORE_BYTE_gfx12:
    case AMDGPU::GLOBAL_STORE_DWORDX2_gfx12:
    case AMDGPU::GLOBAL_STORE_DWORDX3_gfx12:
    case AMDGPU::GLOBAL_STORE_DWORDX4_gfx12:
    case AMDGPU::GLOBAL_STORE_DWORD_gfx12:
    case AMDGPU::GLOBAL_STORE_SHORT_D16_HI_gfx12:
    case AMDGPU::GLOBAL_STORE_SHORT_gfx12: {
      switch (OpNum) {
      case 3:
        // op: cpol
        return 7;
      case 1:
        // op: vdata
        return 55;
      case 0:
        // op: vaddr
        return 64;
      case 2:
        // op: offset
        return 72;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V12_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V11_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V10_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V6_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V7_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V9_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V5_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V8_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V4_gfx10:
    case AMDGPU::IMAGE_SAMPLE_nortn_V1_gfx10:
    case AMDGPU::IMAGE_SAMPLE_nortn_V2_gfx10:
    case AMDGPU::IMAGE_SAMPLE_nortn_V3_gfx10:
    case AMDGPU::IMAGE_SAMPLE_nortn_V4_gfx10: {
      switch (OpNum) {
      case 3:
        // op: dmask
        return 8;
      case 5:
        // op: unorm
        return 12;
      case 6:
        // op: cpol
        return 7;
      case 7:
        // op: r128
        return 15;
      case 9:
        // op: tfe
        return 16;
      case 10:
        // op: lwe
        return 17;
      case 11:
        // op: d16
        return 63;
      case 1:
        // op: srsrc
        return 48;
      case 2:
        // op: ssamp
        return 53;
      case 0:
        // op: vaddr0
        return 32;
      case 4:
        // op: dim
        return 3;
      case 8:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V12_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V11_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V10_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V6_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V7_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V9_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V5_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V8_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V4_gfx11:
    case AMDGPU::IMAGE_SAMPLE_nortn_V1_gfx11:
    case AMDGPU::IMAGE_SAMPLE_nortn_V2_gfx11:
    case AMDGPU::IMAGE_SAMPLE_nortn_V3_gfx11:
    case AMDGPU::IMAGE_SAMPLE_nortn_V4_gfx11: {
      switch (OpNum) {
      case 3:
        // op: dmask
        return 8;
      case 5:
        // op: unorm
        return 7;
      case 6:
        // op: cpol
        return 12;
      case 7:
        // op: r128
        return 15;
      case 9:
        // op: tfe
        return 53;
      case 10:
        // op: lwe
        return 54;
      case 1:
        // op: srsrc
        return 48;
      case 2:
        // op: ssamp
        return 58;
      case 11:
        // op: d16
        return 17;
      case 8:
        // op: a16
        return 16;
      case 0:
        // op: vaddr0
        return 32;
      case 4:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::DS_ADD_F32_vi:
    case AMDGPU::DS_ADD_F32_vi_gfx9:
    case AMDGPU::DS_ADD_F64_vi:
    case AMDGPU::DS_ADD_U32_vi:
    case AMDGPU::DS_ADD_U32_vi_gfx9:
    case AMDGPU::DS_ADD_U64_vi:
    case AMDGPU::DS_ADD_U64_vi_gfx9:
    case AMDGPU::DS_AND_B32_vi:
    case AMDGPU::DS_AND_B32_vi_gfx9:
    case AMDGPU::DS_AND_B64_vi:
    case AMDGPU::DS_AND_B64_vi_gfx9:
    case AMDGPU::DS_DEC_U32_vi:
    case AMDGPU::DS_DEC_U32_vi_gfx9:
    case AMDGPU::DS_DEC_U64_vi:
    case AMDGPU::DS_DEC_U64_vi_gfx9:
    case AMDGPU::DS_INC_U32_vi:
    case AMDGPU::DS_INC_U32_vi_gfx9:
    case AMDGPU::DS_INC_U64_vi:
    case AMDGPU::DS_INC_U64_vi_gfx9:
    case AMDGPU::DS_MAX_F32_vi:
    case AMDGPU::DS_MAX_F32_vi_gfx9:
    case AMDGPU::DS_MAX_F64_vi:
    case AMDGPU::DS_MAX_F64_vi_gfx9:
    case AMDGPU::DS_MAX_I32_vi:
    case AMDGPU::DS_MAX_I32_vi_gfx9:
    case AMDGPU::DS_MAX_I64_vi:
    case AMDGPU::DS_MAX_I64_vi_gfx9:
    case AMDGPU::DS_MAX_U32_vi:
    case AMDGPU::DS_MAX_U32_vi_gfx9:
    case AMDGPU::DS_MAX_U64_vi:
    case AMDGPU::DS_MAX_U64_vi_gfx9:
    case AMDGPU::DS_MIN_F32_vi:
    case AMDGPU::DS_MIN_F32_vi_gfx9:
    case AMDGPU::DS_MIN_F64_vi:
    case AMDGPU::DS_MIN_F64_vi_gfx9:
    case AMDGPU::DS_MIN_I32_vi:
    case AMDGPU::DS_MIN_I32_vi_gfx9:
    case AMDGPU::DS_MIN_I64_vi:
    case AMDGPU::DS_MIN_I64_vi_gfx9:
    case AMDGPU::DS_MIN_U32_vi:
    case AMDGPU::DS_MIN_U32_vi_gfx9:
    case AMDGPU::DS_MIN_U64_vi:
    case AMDGPU::DS_MIN_U64_vi_gfx9:
    case AMDGPU::DS_OR_B32_vi:
    case AMDGPU::DS_OR_B32_vi_gfx9:
    case AMDGPU::DS_OR_B64_vi:
    case AMDGPU::DS_OR_B64_vi_gfx9:
    case AMDGPU::DS_PK_ADD_BF16_vi:
    case AMDGPU::DS_PK_ADD_F16_vi:
    case AMDGPU::DS_RSUB_U32_vi:
    case AMDGPU::DS_RSUB_U32_vi_gfx9:
    case AMDGPU::DS_RSUB_U64_vi:
    case AMDGPU::DS_RSUB_U64_vi_gfx9:
    case AMDGPU::DS_SUB_U32_vi:
    case AMDGPU::DS_SUB_U32_vi_gfx9:
    case AMDGPU::DS_SUB_U64_vi:
    case AMDGPU::DS_SUB_U64_vi_gfx9:
    case AMDGPU::DS_WRITE_B128_vi:
    case AMDGPU::DS_WRITE_B128_vi_gfx9:
    case AMDGPU::DS_WRITE_B16_D16_HI_vi:
    case AMDGPU::DS_WRITE_B16_vi:
    case AMDGPU::DS_WRITE_B16_vi_gfx9:
    case AMDGPU::DS_WRITE_B32_vi:
    case AMDGPU::DS_WRITE_B32_vi_gfx9:
    case AMDGPU::DS_WRITE_B64_vi:
    case AMDGPU::DS_WRITE_B64_vi_gfx9:
    case AMDGPU::DS_WRITE_B8_D16_HI_vi:
    case AMDGPU::DS_WRITE_B8_vi:
    case AMDGPU::DS_WRITE_B8_vi_gfx9:
    case AMDGPU::DS_WRITE_B96_vi:
    case AMDGPU::DS_WRITE_B96_vi_gfx9:
    case AMDGPU::DS_XOR_B32_vi:
    case AMDGPU::DS_XOR_B32_vi_gfx9:
    case AMDGPU::DS_XOR_B64_vi:
    case AMDGPU::DS_XOR_B64_vi_gfx9: {
      switch (OpNum) {
      case 3:
        // op: gds
        return 16;
      case 0:
        // op: addr
        return 32;
      case 1:
        // op: data0
        return 25;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_ADD_F32_gfx10:
    case AMDGPU::DS_ADD_F32_gfx11:
    case AMDGPU::DS_ADD_U32_gfx10:
    case AMDGPU::DS_ADD_U32_gfx11:
    case AMDGPU::DS_ADD_U32_gfx6_gfx7:
    case AMDGPU::DS_ADD_U64_gfx10:
    case AMDGPU::DS_ADD_U64_gfx11:
    case AMDGPU::DS_ADD_U64_gfx6_gfx7:
    case AMDGPU::DS_AND_B32_gfx10:
    case AMDGPU::DS_AND_B32_gfx11:
    case AMDGPU::DS_AND_B32_gfx6_gfx7:
    case AMDGPU::DS_AND_B64_gfx10:
    case AMDGPU::DS_AND_B64_gfx11:
    case AMDGPU::DS_AND_B64_gfx6_gfx7:
    case AMDGPU::DS_DEC_U32_gfx10:
    case AMDGPU::DS_DEC_U32_gfx11:
    case AMDGPU::DS_DEC_U32_gfx6_gfx7:
    case AMDGPU::DS_DEC_U64_gfx10:
    case AMDGPU::DS_DEC_U64_gfx11:
    case AMDGPU::DS_DEC_U64_gfx6_gfx7:
    case AMDGPU::DS_INC_U32_gfx10:
    case AMDGPU::DS_INC_U32_gfx11:
    case AMDGPU::DS_INC_U32_gfx6_gfx7:
    case AMDGPU::DS_INC_U64_gfx10:
    case AMDGPU::DS_INC_U64_gfx11:
    case AMDGPU::DS_INC_U64_gfx6_gfx7:
    case AMDGPU::DS_MAX_F32_gfx10:
    case AMDGPU::DS_MAX_F32_gfx11:
    case AMDGPU::DS_MAX_F32_gfx6_gfx7:
    case AMDGPU::DS_MAX_F64_gfx10:
    case AMDGPU::DS_MAX_F64_gfx11:
    case AMDGPU::DS_MAX_F64_gfx6_gfx7:
    case AMDGPU::DS_MAX_I32_gfx10:
    case AMDGPU::DS_MAX_I32_gfx11:
    case AMDGPU::DS_MAX_I32_gfx6_gfx7:
    case AMDGPU::DS_MAX_I64_gfx10:
    case AMDGPU::DS_MAX_I64_gfx11:
    case AMDGPU::DS_MAX_I64_gfx6_gfx7:
    case AMDGPU::DS_MAX_U32_gfx10:
    case AMDGPU::DS_MAX_U32_gfx11:
    case AMDGPU::DS_MAX_U32_gfx6_gfx7:
    case AMDGPU::DS_MAX_U64_gfx10:
    case AMDGPU::DS_MAX_U64_gfx11:
    case AMDGPU::DS_MAX_U64_gfx6_gfx7:
    case AMDGPU::DS_MIN_F32_gfx10:
    case AMDGPU::DS_MIN_F32_gfx11:
    case AMDGPU::DS_MIN_F32_gfx6_gfx7:
    case AMDGPU::DS_MIN_F64_gfx10:
    case AMDGPU::DS_MIN_F64_gfx11:
    case AMDGPU::DS_MIN_F64_gfx6_gfx7:
    case AMDGPU::DS_MIN_I32_gfx10:
    case AMDGPU::DS_MIN_I32_gfx11:
    case AMDGPU::DS_MIN_I32_gfx6_gfx7:
    case AMDGPU::DS_MIN_I64_gfx10:
    case AMDGPU::DS_MIN_I64_gfx11:
    case AMDGPU::DS_MIN_I64_gfx6_gfx7:
    case AMDGPU::DS_MIN_U32_gfx10:
    case AMDGPU::DS_MIN_U32_gfx11:
    case AMDGPU::DS_MIN_U32_gfx6_gfx7:
    case AMDGPU::DS_MIN_U64_gfx10:
    case AMDGPU::DS_MIN_U64_gfx11:
    case AMDGPU::DS_MIN_U64_gfx6_gfx7:
    case AMDGPU::DS_OR_B32_gfx10:
    case AMDGPU::DS_OR_B32_gfx11:
    case AMDGPU::DS_OR_B32_gfx6_gfx7:
    case AMDGPU::DS_OR_B64_gfx10:
    case AMDGPU::DS_OR_B64_gfx11:
    case AMDGPU::DS_OR_B64_gfx6_gfx7:
    case AMDGPU::DS_RSUB_U32_gfx10:
    case AMDGPU::DS_RSUB_U32_gfx11:
    case AMDGPU::DS_RSUB_U32_gfx6_gfx7:
    case AMDGPU::DS_RSUB_U64_gfx10:
    case AMDGPU::DS_RSUB_U64_gfx11:
    case AMDGPU::DS_RSUB_U64_gfx6_gfx7:
    case AMDGPU::DS_SUB_U32_gfx10:
    case AMDGPU::DS_SUB_U32_gfx11:
    case AMDGPU::DS_SUB_U32_gfx6_gfx7:
    case AMDGPU::DS_SUB_U64_gfx10:
    case AMDGPU::DS_SUB_U64_gfx11:
    case AMDGPU::DS_SUB_U64_gfx6_gfx7:
    case AMDGPU::DS_WRITE_B128_gfx10:
    case AMDGPU::DS_WRITE_B128_gfx11:
    case AMDGPU::DS_WRITE_B128_gfx7:
    case AMDGPU::DS_WRITE_B16_D16_HI_gfx10:
    case AMDGPU::DS_WRITE_B16_D16_HI_gfx11:
    case AMDGPU::DS_WRITE_B16_gfx10:
    case AMDGPU::DS_WRITE_B16_gfx11:
    case AMDGPU::DS_WRITE_B16_gfx6_gfx7:
    case AMDGPU::DS_WRITE_B32_gfx10:
    case AMDGPU::DS_WRITE_B32_gfx11:
    case AMDGPU::DS_WRITE_B32_gfx6_gfx7:
    case AMDGPU::DS_WRITE_B64_gfx10:
    case AMDGPU::DS_WRITE_B64_gfx11:
    case AMDGPU::DS_WRITE_B64_gfx6_gfx7:
    case AMDGPU::DS_WRITE_B8_D16_HI_gfx10:
    case AMDGPU::DS_WRITE_B8_D16_HI_gfx11:
    case AMDGPU::DS_WRITE_B8_gfx10:
    case AMDGPU::DS_WRITE_B8_gfx11:
    case AMDGPU::DS_WRITE_B8_gfx6_gfx7:
    case AMDGPU::DS_WRITE_B96_gfx10:
    case AMDGPU::DS_WRITE_B96_gfx11:
    case AMDGPU::DS_WRITE_B96_gfx7:
    case AMDGPU::DS_XOR_B32_gfx10:
    case AMDGPU::DS_XOR_B32_gfx11:
    case AMDGPU::DS_XOR_B32_gfx6_gfx7:
    case AMDGPU::DS_XOR_B64_gfx10:
    case AMDGPU::DS_XOR_B64_gfx11:
    case AMDGPU::DS_XOR_B64_gfx6_gfx7: {
      switch (OpNum) {
      case 3:
        // op: gds
        return 17;
      case 0:
        // op: addr
        return 32;
      case 1:
        // op: data0
        return 40;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CSUB_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORD_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_USHORT_OFFSET_gfx11:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_DWORD_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_OFFSET_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_OFFSET_gfx11: {
      switch (OpNum) {
      case 3:
        // op: offset
        return 0;
      case 4:
        // op: cpol
        return 12;
      case 0:
        // op: vdata
        return 40;
      case 1:
        // op: srsrc
        return 48;
      case 2:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::BUFFER_LOAD_DWORDX3_LDS_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX3_LDS_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX3_LDS_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX3_LDS_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX3_LDS_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX3_LDS_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_LDS_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX4_LDS_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_LDS_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX4_LDS_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_LDS_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX4_LDS_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_vi: {
      switch (OpNum) {
      case 3:
        // op: offset
        return 0;
      case 4:
        // op: cpol
        return 14;
      case 0:
        // op: vaddr
        return 32;
      case 1:
        // op: srsrc
        return 48;
      case 2:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORD_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_TFE_OFFSET_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_TFE_OFFSET_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_TFE_OFFSET_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_TFE_OFFSET_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_OFFSET_gfx90a:
    case AMDGPU::BUFFER_LOAD_USHORT_OFFSET_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_BYTE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_BYTE_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_BYTE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_DWORD_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_DWORD_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORD_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORD_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_TFE_OFFSET_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_TFE_OFFSET_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_TFE_OFFSET_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_TFE_OFFSET_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_SHORT_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_SHORT_OFFSET_gfx90a:
    case AMDGPU::BUFFER_STORE_SHORT_OFFSET_vi:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_OFFSET_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_OFFSET_vi: {
      switch (OpNum) {
      case 3:
        // op: offset
        return 0;
      case 4:
        // op: cpol
        return 14;
      case 0:
        // op: vdata
        return 40;
      case 1:
        // op: srsrc
        return 48;
      case 2:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFSET_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFSET_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFSET_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_vi: {
      switch (OpNum) {
      case 3:
        // op: offset
        return 0;
      case 4:
        // op: cpol
        return 15;
      case 0:
        // op: vdata
        return 40;
      case 1:
        // op: srsrc
        return 48;
      case 2:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFSET_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFSET_gfx90a: {
      switch (OpNum) {
      case 3:
        // op: offset
        return 0;
      case 4:
        // op: cpol
        return 17;
      case 0:
        // op: vdata
        return 40;
      case 1:
        // op: srsrc
        return 48;
      case 2:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CSUB_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_gfx6_gfx7: {
      switch (OpNum) {
      case 3:
        // op: offset
        return 0;
      case 4:
        // op: cpol
        return 54;
      case 0:
        // op: vdata
        return 40;
      case 1:
        // op: srsrc
        return 48;
      case 2:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_gfx11: {
      switch (OpNum) {
      case 3:
        // op: offset
        return 0;
      case 5:
        // op: cpol
        return 12;
      case 4:
        // op: format
        return 19;
      case 0:
        // op: vdata
        return 40;
      case 1:
        // op: srsrc
        return 48;
      case 2:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFSET_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_vi: {
      switch (OpNum) {
      case 3:
        // op: offset
        return 0;
      case 5:
        // op: cpol
        return 14;
      case 4:
        // op: format
        return 19;
      case 0:
        // op: vdata
        return 40;
      case 1:
        // op: srsrc
        return 48;
      case 2:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_VBUFFER_OFFSET_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET_gfx12_format: {
      switch (OpNum) {
      case 3:
        // op: offset
        return 72;
      case 0:
        // op: vdata
        return 32;
      case 1:
        // op: srsrc
        return 41;
      case 2:
        // op: soffset
        return 0;
      case 4:
        // op: cpol
        return 7;
      }
      break;
    }
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_gfx12: {
      switch (OpNum) {
      case 3:
        // op: offset
        return 72;
      case 0:
        // op: vdata
        return 32;
      case 1:
        // op: srsrc
        return 41;
      case 2:
        // op: soffset
        return 0;
      case 5:
        // op: cpol
        return 7;
      case 4:
        // op: format
        return 55;
      }
      break;
    }
    case AMDGPU::FLAT_ATOMIC_ADD_F32_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_ADD_F64_SADDR_RTN_gfx1250:
    case AMDGPU::FLAT_ATOMIC_ADD_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_AND_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_AND_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_COND_SUB_U32_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_CSUB_U32_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_DEC_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_FMAX_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_FMIN_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_INC_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_INC_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR_RTN_gfx1250:
    case AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR_RTN_gfx1250:
    case AMDGPU::FLAT_ATOMIC_OR_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_OR_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_BF16_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_PK_ADD_F16_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMAX_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMIN_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SUB_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SWAP_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMAX_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMIN_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_XOR_SADDR_RTN_gfx12:
    case AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_RTN_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_CSUB_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_RTN_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_RTN_gfx1250:
    case AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN_gfx12:
    case AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_gfx12: {
      switch (OpNum) {
      case 3:
        // op: saddr
        return 0;
      case 0:
        // op: vdst
        return 32;
      case 5:
        // op: cpol
        return 7;
      case 2:
        // op: vdata
        return 55;
      case 1:
        // op: vaddr
        return 64;
      case 4:
        // op: offset
        return 72;
      }
      break;
    }
    case AMDGPU::V_CEIL_F16_dpp8_gfx10:
    case AMDGPU::V_CEIL_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_CEIL_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_CEIL_F16_t16_dpp8_gfx11:
    case AMDGPU::V_CEIL_F16_t16_dpp8_gfx12:
    case AMDGPU::V_CEIL_F32_dpp8_gfx10:
    case AMDGPU::V_CEIL_F32_dpp8_gfx11:
    case AMDGPU::V_CEIL_F32_dpp8_gfx12:
    case AMDGPU::V_COS_BF16V_COS_BF16_fake16_dpp8_gfx1250:
    case AMDGPU::V_COS_BF16V_COS_BF16_t16_dpp8_gfx1250:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_COS_F16V_COS_F16_t16_dpp8_gfx11:
    case AMDGPU::V_COS_F16V_COS_F16_t16_dpp8_gfx12:
    case AMDGPU::V_COS_F16_dpp8_gfx10:
    case AMDGPU::V_COS_F32_dpp8_gfx10:
    case AMDGPU::V_COS_F32_dpp8_gfx11:
    case AMDGPU::V_COS_F32_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_fake16_dpp8_gfx1250:
    case AMDGPU::V_CVT_F16_BF8V_CVT_F16_BF8_t16_dpp8_gfx1250:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_fake16_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_F32V_CVT_F16_F32_t16_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_F32_dpp8_gfx10:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_fake16_dpp8_gfx1250:
    case AMDGPU::V_CVT_F16_FP8V_CVT_F16_FP8_t16_dpp8_gfx1250:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_I16V_CVT_F16_I16_t16_dpp8_gfx12:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_dpp8_gfx11:
    case AMDGPU::V_CVT_F16_U16V_CVT_F16_U16_t16_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_fake16_dpp8_gfx1250:
    case AMDGPU::V_CVT_F32_BF16_gfx1250V_CVT_F32_BF16_gfx1250_t16_dpp8_gfx1250:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_dpp8_gfx11:
    case AMDGPU::V_CVT_F32_F16V_CVT_F32_F16_t16_dpp8_gfx12:
    case AMDGPU::V_CVT_F32_F16_dpp8_gfx10:
    case AMDGPU::V_CVT_FLOOR_I32_F32_dpp8_gfx11:
    case AMDGPU::V_CVT_FLOOR_I32_F32_dpp8_gfx12:
    case AMDGPU::V_CVT_FLR_I32_F32_dpp8_gfx10:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_dpp8_gfx11:
    case AMDGPU::V_CVT_I16_F16V_CVT_I16_F16_t16_dpp8_gfx12:
    case AMDGPU::V_CVT_I16_F16_dpp8_gfx10:
    case AMDGPU::V_CVT_I32_F32_dpp8_gfx10:
    case AMDGPU::V_CVT_I32_F32_dpp8_gfx11:
    case AMDGPU::V_CVT_I32_F32_dpp8_gfx12:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_dpp8_gfx11:
    case AMDGPU::V_CVT_I32_I16V_CVT_I32_I16_t16_dpp8_gfx12:
    case AMDGPU::V_CVT_NEAREST_I32_F32_dpp8_gfx11:
    case AMDGPU::V_CVT_NEAREST_I32_F32_dpp8_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_dpp8_gfx11:
    case AMDGPU::V_CVT_NORM_I16_F16V_CVT_NORM_I16_F16_t16_dpp8_gfx12:
    case AMDGPU::V_CVT_NORM_I16_F16_dpp8_gfx10:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_dpp8_gfx11:
    case AMDGPU::V_CVT_NORM_U16_F16V_CVT_NORM_U16_F16_t16_dpp8_gfx12:
    case AMDGPU::V_CVT_NORM_U16_F16_dpp8_gfx10:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_fake16_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_F16_BF8V_CVT_PK_F16_BF8_t16_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_fake16_dpp8_gfx1250:
    case AMDGPU::V_CVT_PK_F16_FP8V_CVT_PK_F16_FP8_t16_dpp8_gfx1250:
    case AMDGPU::V_CVT_RPI_I32_F32_dpp8_gfx10:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_dpp8_gfx11:
    case AMDGPU::V_CVT_U16_F16V_CVT_U16_F16_t16_dpp8_gfx12:
    case AMDGPU::V_CVT_U16_F16_dpp8_gfx10:
    case AMDGPU::V_CVT_U32_F32_dpp8_gfx10:
    case AMDGPU::V_CVT_U32_F32_dpp8_gfx11:
    case AMDGPU::V_CVT_U32_F32_dpp8_gfx12:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_dpp8_gfx11:
    case AMDGPU::V_CVT_U32_U16V_CVT_U32_U16_t16_dpp8_gfx12:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_fake16_dpp8_gfx1250:
    case AMDGPU::V_EXP_BF16V_EXP_BF16_t16_dpp8_gfx1250:
    case AMDGPU::V_EXP_F16_dpp8_gfx10:
    case AMDGPU::V_EXP_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_EXP_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_EXP_F16_t16_dpp8_gfx11:
    case AMDGPU::V_EXP_F16_t16_dpp8_gfx12:
    case AMDGPU::V_EXP_F32_dpp8_gfx10:
    case AMDGPU::V_EXP_F32_dpp8_gfx11:
    case AMDGPU::V_EXP_F32_dpp8_gfx12:
    case AMDGPU::V_FLOOR_F16_dpp8_gfx10:
    case AMDGPU::V_FLOOR_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_FLOOR_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_FLOOR_F16_t16_dpp8_gfx11:
    case AMDGPU::V_FLOOR_F16_t16_dpp8_gfx12:
    case AMDGPU::V_FLOOR_F32_dpp8_gfx10:
    case AMDGPU::V_FLOOR_F32_dpp8_gfx11:
    case AMDGPU::V_FLOOR_F32_dpp8_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_dpp8_gfx11:
    case AMDGPU::V_FRACT_F16V_FRACT_F16_t16_dpp8_gfx12:
    case AMDGPU::V_FRACT_F16_dpp8_gfx10:
    case AMDGPU::V_FRACT_F32_dpp8_gfx10:
    case AMDGPU::V_FRACT_F32_dpp8_gfx11:
    case AMDGPU::V_FRACT_F32_dpp8_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_dpp8_gfx11:
    case AMDGPU::V_FREXP_EXP_I16_F16V_FREXP_EXP_I16_F16_t16_dpp8_gfx12:
    case AMDGPU::V_FREXP_EXP_I16_F16_dpp8_gfx10:
    case AMDGPU::V_FREXP_EXP_I32_F32_dpp8_gfx10:
    case AMDGPU::V_FREXP_EXP_I32_F32_dpp8_gfx11:
    case AMDGPU::V_FREXP_EXP_I32_F32_dpp8_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_dpp8_gfx11:
    case AMDGPU::V_FREXP_MANT_F16V_FREXP_MANT_F16_t16_dpp8_gfx12:
    case AMDGPU::V_FREXP_MANT_F16_dpp8_gfx10:
    case AMDGPU::V_FREXP_MANT_F32_dpp8_gfx10:
    case AMDGPU::V_FREXP_MANT_F32_dpp8_gfx11:
    case AMDGPU::V_FREXP_MANT_F32_dpp8_gfx12:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_fake16_dpp8_gfx1250:
    case AMDGPU::V_LOG_BF16V_LOG_BF16_t16_dpp8_gfx1250:
    case AMDGPU::V_LOG_F16_dpp8_gfx10:
    case AMDGPU::V_LOG_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_LOG_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_LOG_F16_t16_dpp8_gfx11:
    case AMDGPU::V_LOG_F16_t16_dpp8_gfx12:
    case AMDGPU::V_LOG_F32_dpp8_gfx10:
    case AMDGPU::V_LOG_F32_dpp8_gfx11:
    case AMDGPU::V_LOG_F32_dpp8_gfx12:
    case AMDGPU::V_MOV_B16_t16_dpp8_gfx11:
    case AMDGPU::V_MOV_B16_t16_dpp8_gfx12:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_dpp8_gfx11:
    case AMDGPU::V_NOT_B16V_NOT_B16_t16_dpp8_gfx12:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_fake16_dpp8_gfx1250:
    case AMDGPU::V_RCP_BF16V_RCP_BF16_t16_dpp8_gfx1250:
    case AMDGPU::V_RCP_F16_dpp8_gfx10:
    case AMDGPU::V_RCP_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_RCP_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_RCP_F16_t16_dpp8_gfx11:
    case AMDGPU::V_RCP_F16_t16_dpp8_gfx12:
    case AMDGPU::V_RCP_F32_dpp8_gfx10:
    case AMDGPU::V_RCP_F32_dpp8_gfx11:
    case AMDGPU::V_RCP_F32_dpp8_gfx12:
    case AMDGPU::V_RCP_IFLAG_F32_dpp8_gfx10:
    case AMDGPU::V_RCP_IFLAG_F32_dpp8_gfx11:
    case AMDGPU::V_RCP_IFLAG_F32_dpp8_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_dpp8_gfx11:
    case AMDGPU::V_RNDNE_F16V_RNDNE_F16_t16_dpp8_gfx12:
    case AMDGPU::V_RNDNE_F16_dpp8_gfx10:
    case AMDGPU::V_RNDNE_F32_dpp8_gfx10:
    case AMDGPU::V_RNDNE_F32_dpp8_gfx11:
    case AMDGPU::V_RNDNE_F32_dpp8_gfx12:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_fake16_dpp8_gfx1250:
    case AMDGPU::V_RSQ_BF16V_RSQ_BF16_t16_dpp8_gfx1250:
    case AMDGPU::V_RSQ_F16_dpp8_gfx10:
    case AMDGPU::V_RSQ_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_RSQ_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_RSQ_F16_t16_dpp8_gfx11:
    case AMDGPU::V_RSQ_F16_t16_dpp8_gfx12:
    case AMDGPU::V_RSQ_F32_dpp8_gfx10:
    case AMDGPU::V_RSQ_F32_dpp8_gfx11:
    case AMDGPU::V_RSQ_F32_dpp8_gfx12:
    case AMDGPU::V_SAT_PK4_I4_I8V_SAT_PK4_I4_I8_t16_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK4_U4_U8V_SAT_PK4_U4_U8_t16_dpp8_gfx1250:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_dpp8_gfx11:
    case AMDGPU::V_SAT_PK_U8_I16V_SAT_PK_U8_I16_t16_dpp8_gfx12:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_fake16_dpp8_gfx1250:
    case AMDGPU::V_SIN_BF16V_SIN_BF16_t16_dpp8_gfx1250:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_dpp8_gfx11:
    case AMDGPU::V_SIN_F16V_SIN_F16_t16_dpp8_gfx12:
    case AMDGPU::V_SIN_F16_dpp8_gfx10:
    case AMDGPU::V_SIN_F32_dpp8_gfx10:
    case AMDGPU::V_SIN_F32_dpp8_gfx11:
    case AMDGPU::V_SIN_F32_dpp8_gfx12:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_fake16_dpp8_gfx1250:
    case AMDGPU::V_SQRT_BF16V_SQRT_BF16_t16_dpp8_gfx1250:
    case AMDGPU::V_SQRT_F16_dpp8_gfx10:
    case AMDGPU::V_SQRT_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_SQRT_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_SQRT_F16_t16_dpp8_gfx11:
    case AMDGPU::V_SQRT_F16_t16_dpp8_gfx12:
    case AMDGPU::V_SQRT_F32_dpp8_gfx10:
    case AMDGPU::V_SQRT_F32_dpp8_gfx11:
    case AMDGPU::V_SQRT_F32_dpp8_gfx12:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_fake16_dpp8_gfx1250:
    case AMDGPU::V_TANH_BF16V_TANH_BF16_t16_dpp8_gfx1250:
    case AMDGPU::V_TANH_F16V_TANH_F16_fake16_dpp8_gfx1250:
    case AMDGPU::V_TANH_F16V_TANH_F16_t16_dpp8_gfx1250:
    case AMDGPU::V_TANH_F32_dpp8_gfx1250:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_dpp8_gfx11:
    case AMDGPU::V_TRUNC_F16V_TRUNC_F16_t16_dpp8_gfx12:
    case AMDGPU::V_TRUNC_F16_dpp8_gfx10:
    case AMDGPU::V_TRUNC_F32_dpp8_gfx10:
    case AMDGPU::V_TRUNC_F32_dpp8_gfx11:
    case AMDGPU::V_TRUNC_F32_dpp8_gfx12: {
      switch (OpNum) {
      case 3:
        // op: src0
        return 32;
      case 4:
        // op: dpp8
        return 40;
      case 5:
        // op: fi
        return 0;
      case 0:
        // op: vdst
        return 17;
      }
      break;
    }
    case AMDGPU::V_ADD_F16_dpp8_gfx10:
    case AMDGPU::V_ADD_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_ADD_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_ADD_F16_t16_dpp8_gfx11:
    case AMDGPU::V_ADD_F16_t16_dpp8_gfx12:
    case AMDGPU::V_ADD_F32_dpp8_gfx10:
    case AMDGPU::V_ADD_F32_dpp8_gfx11:
    case AMDGPU::V_ADD_F32_dpp8_gfx12:
    case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
    case AMDGPU::V_CNDMASK_B32_dpp8_gfx11:
    case AMDGPU::V_CNDMASK_B32_dpp8_gfx12:
    case AMDGPU::V_CNDMASK_B32_dpp8_w32_gfx10:
    case AMDGPU::V_CNDMASK_B32_dpp8_w32_gfx11:
    case AMDGPU::V_CNDMASK_B32_dpp8_w32_gfx12:
    case AMDGPU::V_CNDMASK_B32_dpp8_w64_gfx10:
    case AMDGPU::V_CNDMASK_B32_dpp8_w64_gfx11:
    case AMDGPU::V_CNDMASK_B32_dpp8_w64_gfx12:
    case AMDGPU::V_CVT_PKRTZ_F16_F32_dpp8_gfx10:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_dpp8_gfx11:
    case AMDGPU::V_CVT_PK_RTZ_F16_F32_dpp8_gfx12:
    case AMDGPU::V_LDEXP_F16_dpp8_gfx10:
    case AMDGPU::V_LDEXP_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_LDEXP_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_LDEXP_F16_t16_dpp8_gfx11:
    case AMDGPU::V_LDEXP_F16_t16_dpp8_gfx12:
    case AMDGPU::V_MAX_F16V_MAX_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_MAX_F16V_MAX_F16_t16_dpp8_gfx11:
    case AMDGPU::V_MAX_F16_dpp8_gfx10:
    case AMDGPU::V_MAX_F32_dpp8_gfx10:
    case AMDGPU::V_MAX_F32_dpp8_gfx11:
    case AMDGPU::V_MAX_NUM_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_MAX_NUM_F16_t16_dpp8_gfx12:
    case AMDGPU::V_MAX_NUM_F32_dpp8_gfx12:
    case AMDGPU::V_MIN_F16V_MIN_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_MIN_F16V_MIN_F16_t16_dpp8_gfx11:
    case AMDGPU::V_MIN_F16_dpp8_gfx10:
    case AMDGPU::V_MIN_F32_dpp8_gfx10:
    case AMDGPU::V_MIN_F32_dpp8_gfx11:
    case AMDGPU::V_MIN_NUM_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_MIN_NUM_F16_t16_dpp8_gfx12:
    case AMDGPU::V_MIN_NUM_F32_dpp8_gfx12:
    case AMDGPU::V_MUL_DX9_ZERO_F32_dpp8_gfx11:
    case AMDGPU::V_MUL_DX9_ZERO_F32_dpp8_gfx12:
    case AMDGPU::V_MUL_F16_dpp8_gfx10:
    case AMDGPU::V_MUL_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_MUL_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_MUL_F16_t16_dpp8_gfx11:
    case AMDGPU::V_MUL_F16_t16_dpp8_gfx12:
    case AMDGPU::V_MUL_F32_dpp8_gfx10:
    case AMDGPU::V_MUL_F32_dpp8_gfx11:
    case AMDGPU::V_MUL_F32_dpp8_gfx12:
    case AMDGPU::V_MUL_LEGACY_F32_dpp8_gfx10:
    case AMDGPU::V_PK_FMAC_F16_dpp8_gfx10:
    case AMDGPU::V_SUBREV_F16_dpp8_gfx10:
    case AMDGPU::V_SUBREV_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_SUBREV_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_SUBREV_F16_t16_dpp8_gfx11:
    case AMDGPU::V_SUBREV_F16_t16_dpp8_gfx12:
    case AMDGPU::V_SUBREV_F32_dpp8_gfx10:
    case AMDGPU::V_SUBREV_F32_dpp8_gfx11:
    case AMDGPU::V_SUBREV_F32_dpp8_gfx12:
    case AMDGPU::V_SUB_F16_dpp8_gfx10:
    case AMDGPU::V_SUB_F16_fake16_dpp8_gfx11:
    case AMDGPU::V_SUB_F16_fake16_dpp8_gfx12:
    case AMDGPU::V_SUB_F16_t16_dpp8_gfx11:
    case AMDGPU::V_SUB_F16_t16_dpp8_gfx12:
    case AMDGPU::V_SUB_F32_dpp8_gfx10:
    case AMDGPU::V_SUB_F32_dpp8_gfx11:
    case AMDGPU::V_SUB_F32_dpp8_gfx12: {
      switch (OpNum) {
      case 3:
        // op: src0
        return 32;
      case 6:
        // op: dpp8
        return 40;
      case 7:
        // op: fi
        return 0;
      case 0:
        // op: vdst
        return 17;
      case 5:
        // op: src1
        return 9;
      }
      break;
    }
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MOV_B32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 0:
        // op: vdstX
        return 64;
      case 6:
        // op: src0Y
        return 32;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      }
      break;
    }
    case AMDGPU::V_DUAL_ADD_F32_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_BITOP2_B32_e64_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 0:
        // op: vdstX
        return 64;
      case 6:
        // op: src0Y
        return 32;
      case 7:
        // op: vsrc1Y
        return 72;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      case 8:
        // op: bitop3
        return 80;
      }
      break;
    }
    case AMDGPU::V_DUAL_ADD_F32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_SUB_U32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 0:
        // op: vdstX
        return 64;
      case 6:
        // op: src0Y
        return 32;
      case 7:
        // op: vsrc1Y
        return 72;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      }
      break;
    }
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MOV_B32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 0:
        // op: vdstX
        return 64;
      case 7:
        // op: src0Y
        return 32;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      }
      break;
    }
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_BITOP2_B32_e64_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 0:
        // op: vdstX
        return 64;
      case 7:
        // op: src0Y
        return 32;
      case 8:
        // op: vsrc1Y
        return 72;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      case 9:
        // op: bitop3
        return 80;
      }
      break;
    }
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_SUB_U32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 0:
        // op: vdstX
        return 64;
      case 7:
        // op: src0Y
        return 32;
      case 8:
        // op: vsrc1Y
        return 72;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      }
      break;
    }
    case AMDGPU::V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 0:
        // op: vdstX
        return 64;
      case 7:
        // op: src0Y
        return 32;
      case 9:
        // op: vsrc1Y
        return 72;
      case 10:
        // op: vsrc2Y
        return 80;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 6:
        // op: src0Y_modifiers
        return 44;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      case 8:
        // op: vsrc1Y_modifiers
        return 45;
      }
      break;
    }
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMA_F32_e64_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 0:
        // op: vdstX
        return 64;
      case 7:
        // op: src0Y
        return 32;
      case 9:
        // op: vsrc1Y
        return 72;
      case 11:
        // op: vsrc2Y
        return 80;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 6:
        // op: src0Y_modifiers
        return 44;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      case 8:
        // op: vsrc1Y_modifiers
        return 45;
      case 10:
        // op: vsrc2Y_modifiers
        return 46;
      }
      break;
    }
    case AMDGPU::V_DUAL_ADD_F32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F32_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_ADD_F64_pseudo_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_F32_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MAX_NUM_F64_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_F32_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MIN_NUM_F64_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F32_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_F64_pseudo_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_MUL_LEGACY_F32_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUBREV_F32_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_SUB_F32_e32_X_SUB_F32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 0:
        // op: vdstX
        return 64;
      case 7:
        // op: src0Y
        return 32;
      case 9:
        // op: vsrc1Y
        return 72;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 6:
        // op: src0Y_modifiers
        return 44;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      case 8:
        // op: vsrc1Y_modifiers
        return 45;
      }
      break;
    }
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 0:
        // op: vdstX
        return 64;
      case 8:
        // op: src0Y
        return 32;
      case 10:
        // op: vsrc1Y
        return 72;
      case 11:
        // op: vsrc2Y
        return 80;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 7:
        // op: src0Y_modifiers
        return 44;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      case 9:
        // op: vsrc1Y_modifiers
        return 45;
      }
      break;
    }
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMA_F32_e64_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 0:
        // op: vdstX
        return 64;
      case 8:
        // op: src0Y
        return 32;
      case 10:
        // op: vsrc1Y
        return 72;
      case 12:
        // op: vsrc2Y
        return 80;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 7:
        // op: src0Y_modifiers
        return 44;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      case 9:
        // op: vsrc1Y_modifiers
        return 45;
      case 11:
        // op: vsrc2Y_modifiers
        return 46;
      }
      break;
    }
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_BF16_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_DOT2C_F32_F16_e32_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMAC_F32_e32_X_SUB_F32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 0:
        // op: vdstX
        return 64;
      case 8:
        // op: src0Y
        return 32;
      case 10:
        // op: vsrc1Y
        return 72;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 7:
        // op: src0Y_modifiers
        return 44;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      case 9:
        // op: vsrc1Y_modifiers
        return 45;
      }
      break;
    }
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MOV_B32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 6:
        // op: vsrc2X
        return 56;
      case 0:
        // op: vdstX
        return 64;
      case 7:
        // op: src0Y
        return 32;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      }
      break;
    }
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_BITOP2_B32_e64_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 6:
        // op: vsrc2X
        return 56;
      case 0:
        // op: vdstX
        return 64;
      case 7:
        // op: src0Y
        return 32;
      case 8:
        // op: vsrc1Y
        return 72;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      case 9:
        // op: bitop3
        return 80;
      }
      break;
    }
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_SUB_U32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 6:
        // op: vsrc2X
        return 56;
      case 0:
        // op: vdstX
        return 64;
      case 7:
        // op: src0Y
        return 32;
      case 8:
        // op: vsrc1Y
        return 72;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      }
      break;
    }
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_CNDMASK_B32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 6:
        // op: vsrc2X
        return 56;
      case 0:
        // op: vdstX
        return 64;
      case 8:
        // op: src0Y
        return 32;
      case 10:
        // op: vsrc1Y
        return 72;
      case 11:
        // op: vsrc2Y
        return 80;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 7:
        // op: src0Y_modifiers
        return 44;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      case 9:
        // op: vsrc1Y_modifiers
        return 45;
      }
      break;
    }
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMA_F32_e64_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 6:
        // op: vsrc2X
        return 56;
      case 0:
        // op: vdstX
        return 64;
      case 8:
        // op: src0Y
        return 32;
      case 10:
        // op: vsrc1Y
        return 72;
      case 12:
        // op: vsrc2Y
        return 80;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 7:
        // op: src0Y_modifiers
        return 44;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      case 9:
        // op: vsrc1Y_modifiers
        return 45;
      case 11:
        // op: vsrc2Y_modifiers
        return 46;
      }
      break;
    }
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 6:
        // op: vsrc2X
        return 56;
      case 0:
        // op: vdstX
        return 64;
      case 8:
        // op: src0Y
        return 32;
      case 10:
        // op: vsrc1Y
        return 72;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 7:
        // op: src0Y_modifiers
        return 44;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      case 9:
        // op: vsrc1Y_modifiers
        return 45;
      }
      break;
    }
    case AMDGPU::V_DUAL_FMA_F32_e64_X_MOV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_MOV_B32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 7:
        // op: vsrc2X
        return 56;
      case 0:
        // op: vdstX
        return 64;
      case 8:
        // op: src0Y
        return 32;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      case 6:
        // op: vsrc2X_modifiers
        return 43;
      }
      break;
    }
    case AMDGPU::V_DUAL_FMA_F32_e64_X_BITOP2_B32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_BITOP2_B32_e64_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 7:
        // op: vsrc2X
        return 56;
      case 0:
        // op: vdstX
        return 64;
      case 8:
        // op: src0Y
        return 32;
      case 9:
        // op: vsrc1Y
        return 72;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      case 6:
        // op: vsrc2X_modifiers
        return 43;
      case 10:
        // op: bitop3
        return 80;
      }
      break;
    }
    case AMDGPU::V_DUAL_FMA_F32_e64_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_SUB_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_ADD_U32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_ASHRREV_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_LSHLREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_LSHRREV_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_MAX_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_MIN_I32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_SUB_U32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 7:
        // op: vsrc2X
        return 56;
      case 0:
        // op: vdstX
        return 64;
      case 8:
        // op: src0Y
        return 32;
      case 9:
        // op: vsrc1Y
        return 72;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      case 6:
        // op: vsrc2X_modifiers
        return 43;
      }
      break;
    }
    case AMDGPU::V_DUAL_FMA_F32_e64_X_CNDMASK_B32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_CNDMASK_B32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 7:
        // op: vsrc2X
        return 56;
      case 0:
        // op: vdstX
        return 64;
      case 9:
        // op: src0Y
        return 32;
      case 11:
        // op: vsrc1Y
        return 72;
      case 12:
        // op: vsrc2Y
        return 80;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 8:
        // op: src0Y_modifiers
        return 44;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      case 10:
        // op: vsrc1Y_modifiers
        return 45;
      case 6:
        // op: vsrc2X_modifiers
        return 43;
      }
      break;
    }
    case AMDGPU::V_DUAL_FMA_F32_e64_X_FMA_F32_e64_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_FMA_F32_e64_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 7:
        // op: vsrc2X
        return 56;
      case 0:
        // op: vdstX
        return 64;
      case 9:
        // op: src0Y
        return 32;
      case 11:
        // op: vsrc1Y
        return 72;
      case 13:
        // op: vsrc2Y
        return 80;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 8:
        // op: src0Y_modifiers
        return 44;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      case 10:
        // op: vsrc1Y_modifiers
        return 45;
      case 6:
        // op: vsrc2X_modifiers
        return 43;
      case 12:
        // op: vsrc2Y_modifiers
        return 46;
      }
      break;
    }
    case AMDGPU::V_DUAL_FMA_F32_e64_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F32_e64_X_SUB_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_ADD_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_DOT2C_F32_BF16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_DOT2C_F32_F16_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_FMAC_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_MAX_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_MIN_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_MUL_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_MUL_LEGACY_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_SUBREV_F32_e32_e96_gfx1250:
    case AMDGPU::V_DUAL_FMA_F64_e64_X_SUB_F32_e32_e96_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0X
        return 0;
      case 5:
        // op: vsrc1X
        return 48;
      case 7:
        // op: vsrc2X
        return 56;
      case 0:
        // op: vdstX
        return 64;
      case 9:
        // op: src0Y
        return 32;
      case 11:
        // op: vsrc1Y
        return 72;
      case 1:
        // op: vdstY
        return 88;
      case 2:
        // op: src0X_modifiers
        return 41;
      case 8:
        // op: src0Y_modifiers
        return 44;
      case 4:
        // op: vsrc1X_modifiers
        return 42;
      case 10:
        // op: vsrc1Y_modifiers
        return 45;
      case 6:
        // op: vsrc2X_modifiers
        return 43;
      }
      break;
    }
    case AMDGPU::V_DIV_SCALE_F64_e64_dpp_gfx1250: {
      switch (OpNum) {
      case 3:
        // op: src0_modifiers
        return 61;
      case 5:
        // op: src1_modifiers
        return 62;
      case 7:
        // op: src2_modifiers
        return 63;
      case 9:
        // op: clamp
        return 15;
      case 10:
        // op: omod
        return 59;
      case 0:
        // op: vdst
        return 0;
      case 6:
        // op: src1
        return 41;
      case 8:
        // op: src2
        return 50;
      case 11:
        // op: dpp_ctrl
        return 72;
      case 14:
        // op: bound_ctrl
        return 83;
      case 13:
        // op: bank_mask
        return 88;
      case 12:
        // op: row_mask
        return 92;
      case 15:
        // op: fi
        return 82;
      case 4:
        // op: src0
        return 64;
      case 1:
        // op: sdst
        return 8;
      }
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_CLASS_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_CLASS_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_CLASS_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_F_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_F_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_F_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GE_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GE_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_GT_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_GT_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LE_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LE_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LG_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LG_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LG_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LG_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LG_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LG_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_LT_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_LT_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NEQ_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NEQ_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NE_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NE_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NGE_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NGE_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NGT_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NGT_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NLE_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NLE_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NLG_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NLG_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_NLT_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_NLT_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_O_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_O_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_O_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_O_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_O_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_O_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_T_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_T_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_T_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_U_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMPX_U_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMPX_U_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_F_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_F_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_F_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_F_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_F_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_F_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_F_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_F_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_F_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GE_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GE_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GE_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GE_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GE_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GT_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GT_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GT_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GT_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GT_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GT_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LE_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LE_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LE_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LE_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LE_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LE_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LG_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LG_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LG_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LG_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LG_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LG_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LT_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LT_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LT_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LT_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LT_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LT_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_O_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_O_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_O_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_O_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_O_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_O_F32_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_T_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_T_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_T_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_T_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_T_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_T_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_T_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_T_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_T_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp_gfx12:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp_w64_gfx12:
    case AMDGPU::V_CMP_U_F32_e32_dpp_gfx11:
    case AMDGPU::V_CMP_U_F32_e32_dpp_gfx12:
    case AMDGPU::V_CMP_U_F32_e32_dpp_w32_gfx11:
    case AMDGPU::V_CMP_U_F32_e32_dpp_w32_gfx12:
    case AMDGPU::V_CMP_U_F32_e32_dpp_w64_gfx11:
    case AMDGPU::V_CMP_U_F32_e32_dpp_w64_gfx12: {
      switch (OpNum) {
      case 3:
        // op: src1
        return 9;
      case 0:
        // op: src0_modifiers
        return 52;
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1_modifiers
        return 54;
      case 4:
        // op: dpp_ctrl
        return 40;
      case 7:
        // op: bound_ctrl
        return 51;
      case 6:
        // op: bank_mask
        return 56;
      case 5:
        // op: row_mask
        return 60;
      case 8:
        // op: fi
        return 50;
      }
      break;
    }
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_CLASS_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_CLASS_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_CLASS_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_CLASS_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_EQ_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_EQ_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_F_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_F_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_F_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GE_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GE_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_GT_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_GT_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LE_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LE_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LG_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LG_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LG_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LG_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LG_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LG_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_LT_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_LT_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NEQ_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NEQ_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NEQ_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NE_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NE_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGE_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGE_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGE_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGE_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGT_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGT_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NGT_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NGT_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLE_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLE_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLE_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLE_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLG_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLG_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLG_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLG_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLT_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLT_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_NLT_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_NLT_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_O_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_O_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_O_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_O_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_O_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_O_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_T_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_T_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_T_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_U_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_U_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_U_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMPX_U_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMPX_U_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_CLASS_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_CLASS_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_EQ_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_EQ_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_EQ_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_EQ_I16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_EQ_U16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_F_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_F_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_F_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_F_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_F_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_F_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_F_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_F_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_F_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GE_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GE_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GE_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_I16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GE_U16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GT_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GT_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GT_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GT_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GT_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GT_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GT_I16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_GT_U16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LE_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LE_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LE_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LE_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LE_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LE_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LE_I16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LE_U16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LG_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LG_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LG_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LG_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LG_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LG_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LG_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LG_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LT_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LT_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LT_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LT_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LT_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LT_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LT_I16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_LT_U16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NEQ_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NEQ_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NE_I16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NE_U16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NGE_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NGE_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NGE_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NGT_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NGT_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NGT_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NLE_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NLE_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NLE_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NLG_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NLG_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NLG_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NLT_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NLT_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_NLT_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_O_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_O_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_O_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_O_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_O_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_O_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_O_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_O_F32_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_T_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_T_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_T_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_T_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_T_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_T_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_T_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_T_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_T_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_U_F16_fake16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_U_F16_t16_e32_dpp8_w64_gfx12:
    case AMDGPU::V_CMP_U_F32_e32_dpp8_gfx11:
    case AMDGPU::V_CMP_U_F32_e32_dpp8_gfx12:
    case AMDGPU::V_CMP_U_F32_e32_dpp8_w32_gfx11:
    case AMDGPU::V_CMP_U_F32_e32_dpp8_w32_gfx12:
    case AMDGPU::V_CMP_U_F32_e32_dpp8_w64_gfx11:
    case AMDGPU::V_CMP_U_F32_e32_dpp8_w64_gfx12: {
      switch (OpNum) {
      case 3:
        // op: src1
        return 9;
      case 1:
        // op: src0
        return 32;
      case 4:
        // op: dpp8
        return 40;
      case 5:
        // op: fi
        return 0;
      }
      break;
    }
    case AMDGPU::V_ADD_NC_I32_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_NC_I32_e64_dpp8_gfx12:
    case AMDGPU::V_ADD_NC_U32_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_NC_U32_e64_dpp8_gfx12:
    case AMDGPU::V_MUL_I32_I24_e64_dpp8_gfx11:
    case AMDGPU::V_MUL_I32_I24_e64_dpp8_gfx12:
    case AMDGPU::V_MUL_U32_U24_e64_dpp8_gfx11:
    case AMDGPU::V_MUL_U32_U24_e64_dpp8_gfx12:
    case AMDGPU::V_SUBREV_NC_U32_e64_dpp8_gfx11:
    case AMDGPU::V_SUBREV_NC_U32_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_NC_I32_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_NC_I32_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_NC_U32_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_NC_U32_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 4:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: src1
        return 41;
      case 2:
        // op: src0
        return 64;
      case 5:
        // op: dpp8
        return 72;
      case 6:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_ADD_NC_I32_e64_dpp_gfx11:
    case AMDGPU::V_ADD_NC_I32_e64_dpp_gfx12:
    case AMDGPU::V_ADD_NC_U32_e64_dpp_gfx11:
    case AMDGPU::V_ADD_NC_U32_e64_dpp_gfx12:
    case AMDGPU::V_ADD_U64_e64_dpp_gfx1250:
    case AMDGPU::V_MUL_I32_I24_e64_dpp_gfx11:
    case AMDGPU::V_MUL_I32_I24_e64_dpp_gfx12:
    case AMDGPU::V_MUL_U32_U24_e64_dpp_gfx11:
    case AMDGPU::V_MUL_U32_U24_e64_dpp_gfx12:
    case AMDGPU::V_SUBREV_NC_U32_e64_dpp_gfx11:
    case AMDGPU::V_SUBREV_NC_U32_e64_dpp_gfx12:
    case AMDGPU::V_SUB_NC_I32_e64_dpp_gfx11:
    case AMDGPU::V_SUB_NC_I32_e64_dpp_gfx12:
    case AMDGPU::V_SUB_NC_U32_e64_dpp_gfx11:
    case AMDGPU::V_SUB_NC_U32_e64_dpp_gfx12:
    case AMDGPU::V_SUB_U64_e64_dpp_gfx1250: {
      switch (OpNum) {
      case 4:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: src1
        return 41;
      case 5:
        // op: dpp_ctrl
        return 72;
      case 8:
        // op: bound_ctrl
        return 83;
      case 7:
        // op: bank_mask
        return 88;
      case 6:
        // op: row_mask
        return 92;
      case 9:
        // op: fi
        return 82;
      case 2:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V1_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V1_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V1_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V1_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V1_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V1_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V1_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V1_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V1_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V1_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V1_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V1_V1_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V2_V1_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V3_V1_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V4_V1_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V5_V1_gfx12: {
      switch (OpNum) {
      case 4:
        // op: dim
        return 0;
      case 8:
        // op: tfe
        return 55;
      case 6:
        // op: r128
        return 4;
      case 7:
        // op: a16
        return 6;
      case 3:
        // op: dmask
        return 22;
      case 0:
        // op: vdata
        return 32;
      case 2:
        // op: rsrc
        return 41;
      case 5:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr0
        return 64;
      }
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_V1_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_V2_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_V3_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_V4_V1_gfx12:
    case AMDGPU::IMAGE_LOAD_V5_V1_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V1_V1_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V2_V1_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V3_V1_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V4_V1_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V5_V1_gfx12:
    case AMDGPU::IMAGE_STORE_V1_V1_gfx12:
    case AMDGPU::IMAGE_STORE_V2_V1_gfx12:
    case AMDGPU::IMAGE_STORE_V3_V1_gfx12:
    case AMDGPU::IMAGE_STORE_V4_V1_gfx12:
    case AMDGPU::IMAGE_STORE_V5_V1_gfx12: {
      switch (OpNum) {
      case 4:
        // op: dim
        return 0;
      case 8:
        // op: tfe
        return 55;
      case 6:
        // op: r128
        return 4;
      case 9:
        // op: d16
        return 5;
      case 7:
        // op: a16
        return 6;
      case 3:
        // op: dmask
        return 22;
      case 0:
        // op: vdata
        return 32;
      case 2:
        // op: rsrc
        return 41;
      case 5:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr0
        return 64;
      }
      break;
    }
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V1_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V1_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V1_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V1_gfx12: {
      switch (OpNum) {
      case 4:
        // op: dim
        return 0;
      case 9:
        // op: tfe
        return 3;
      case 7:
        // op: r128
        return 4;
      case 11:
        // op: d16
        return 5;
      case 8:
        // op: a16
        return 6;
      case 3:
        // op: dmask
        return 22;
      case 0:
        // op: vdata
        return 32;
      case 2:
        // op: rsrc
        return 41;
      case 6:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr0
        return 64;
      case 5:
        // op: unorm
        return 13;
      case 10:
        // op: lwe
        return 40;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_nortn_V1_gfx12: {
      switch (OpNum) {
      case 4:
        // op: dim
        return 0;
      case 9:
        // op: tfe
        return 3;
      case 7:
        // op: r128
        return 4;
      case 11:
        // op: d16
        return 5;
      case 8:
        // op: a16
        return 6;
      case 3:
        // op: dmask
        return 22;
      case 1:
        // op: rsrc
        return 41;
      case 6:
        // op: cpol
        return 7;
      case 0:
        // op: vaddr0
        return 64;
      case 5:
        // op: unorm
        return 13;
      case 10:
        // op: lwe
        return 40;
      case 2:
        // op: samp
        return 55;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V2_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_nortn_V2_nsa_gfx10: {
      switch (OpNum) {
      case 4:
        // op: dmask
        return 8;
      case 6:
        // op: unorm
        return 12;
      case 7:
        // op: cpol
        return 7;
      case 8:
        // op: r128
        return 15;
      case 10:
        // op: tfe
        return 16;
      case 11:
        // op: lwe
        return 17;
      case 12:
        // op: d16
        return 63;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: ssamp
        return 53;
      case 0:
        // op: vaddr0
        return 32;
      case 5:
        // op: dim
        return 3;
      case 9:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V2_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_nortn_V2_nsa_gfx11: {
      switch (OpNum) {
      case 4:
        // op: dmask
        return 8;
      case 6:
        // op: unorm
        return 7;
      case 7:
        // op: cpol
        return 12;
      case 8:
        // op: r128
        return 15;
      case 10:
        // op: tfe
        return 53;
      case 11:
        // op: lwe
        return 54;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: ssamp
        return 58;
      case 12:
        // op: d16
        return 17;
      case 9:
        // op: a16
        return 16;
      case 0:
        // op: vaddr0
        return 32;
      case 5:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::V_PERMLANE16_SWAP_B32_e64_gfx1250:
    case AMDGPU::V_PERMLANE16_SWAP_B32_e64_gfx9:
    case AMDGPU::V_PERMLANE32_SWAP_B32_e64_gfx9: {
      switch (OpNum) {
      case 4:
        // op: fi
        return 11;
      case 5:
        // op: bound_ctrl
        return 12;
      case 3:
        // op: src0
        return 32;
      case 0:
        // op: vdst
        return 0;
      }
      break;
    }
    case AMDGPU::DS_CMPST_B32_vi:
    case AMDGPU::DS_CMPST_B32_vi_agpr:
    case AMDGPU::DS_CMPST_B32_vi_gfx9:
    case AMDGPU::DS_CMPST_B64_vi:
    case AMDGPU::DS_CMPST_B64_vi_agpr:
    case AMDGPU::DS_CMPST_B64_vi_gfx9:
    case AMDGPU::DS_CMPST_F32_vi:
    case AMDGPU::DS_CMPST_F32_vi_agpr:
    case AMDGPU::DS_CMPST_F32_vi_gfx9:
    case AMDGPU::DS_CMPST_F64_vi:
    case AMDGPU::DS_CMPST_F64_vi_agpr:
    case AMDGPU::DS_CMPST_F64_vi_gfx9:
    case AMDGPU::DS_MSKOR_B32_vi:
    case AMDGPU::DS_MSKOR_B32_vi_agpr:
    case AMDGPU::DS_MSKOR_B32_vi_gfx9:
    case AMDGPU::DS_MSKOR_B64_vi:
    case AMDGPU::DS_MSKOR_B64_vi_agpr:
    case AMDGPU::DS_MSKOR_B64_vi_gfx9: {
      switch (OpNum) {
      case 4:
        // op: gds
        return 16;
      case 0:
        // op: addr
        return 32;
      case 1:
        // op: data0
        return 40;
      case 2:
        // op: data1
        return 48;
      case 3:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::DS_CMPSTORE_B32_gfx11:
    case AMDGPU::DS_CMPSTORE_B64_gfx11:
    case AMDGPU::DS_CMPSTORE_F32_gfx11:
    case AMDGPU::DS_CMPSTORE_F64_gfx11:
    case AMDGPU::DS_CMPST_B32_gfx10:
    case AMDGPU::DS_CMPST_B32_gfx6_gfx7:
    case AMDGPU::DS_CMPST_B64_gfx10:
    case AMDGPU::DS_CMPST_B64_gfx6_gfx7:
    case AMDGPU::DS_CMPST_F32_gfx10:
    case AMDGPU::DS_CMPST_F32_gfx6_gfx7:
    case AMDGPU::DS_CMPST_F64_gfx10:
    case AMDGPU::DS_CMPST_F64_gfx6_gfx7:
    case AMDGPU::DS_MSKOR_B32_gfx10:
    case AMDGPU::DS_MSKOR_B32_gfx11:
    case AMDGPU::DS_MSKOR_B32_gfx6_gfx7:
    case AMDGPU::DS_MSKOR_B64_gfx10:
    case AMDGPU::DS_MSKOR_B64_gfx11:
    case AMDGPU::DS_MSKOR_B64_gfx6_gfx7: {
      switch (OpNum) {
      case 4:
        // op: gds
        return 17;
      case 0:
        // op: addr
        return 32;
      case 1:
        // op: data0
        return 40;
      case 2:
        // op: data1
        return 48;
      case 3:
        // op: offset
        return 0;
      }
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CSUB_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_gfx11: {
      switch (OpNum) {
      case 4:
        // op: offset
        return 0;
      case 5:
        // op: cpol
        return 12;
      case 0:
        // op: vdata
        return 40;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CSUB_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CSUB_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CSUB_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORD_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORD_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_USHORT_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_USHORT_OFFEN_gfx11:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORD_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORD_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORD_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_OFFEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_BOTHEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_IDXEN_gfx11:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_OFFEN_gfx11: {
      switch (OpNum) {
      case 4:
        // op: offset
        return 0;
      case 5:
        // op: cpol
        return 12;
      case 1:
        // op: vaddr
        return 32;
      case 0:
        // op: vdata
        return 40;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORD_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_DWORD_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_TFE_BOTHEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_TFE_IDXEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_TFE_OFFEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_TFE_BOTHEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_TFE_IDXEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_TFE_OFFEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_TFE_BOTHEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_TFE_IDXEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_TFE_OFFEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_TFE_BOTHEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_TFE_IDXEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_TFE_OFFEN_gfx80:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_IDXEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_USHORT_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_OFFEN_gfx90a:
    case AMDGPU::BUFFER_LOAD_USHORT_OFFEN_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_BYTE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_BYTE_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_BYTE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_BYTE_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_BYTE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_BYTE_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_BYTE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX3_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX4_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_DWORD_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORD_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORD_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORD_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORD_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_DWORD_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORD_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORD_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORD_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_DWORD_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORD_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORD_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_DWORD_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_TFE_BOTHEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_TFE_IDXEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_TFE_OFFEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_TFE_BOTHEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_TFE_IDXEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_TFE_OFFEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_TFE_BOTHEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_TFE_IDXEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_TFE_OFFEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_TFE_BOTHEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_TFE_IDXEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_TFE_OFFEN_gfx80:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_X_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_SHORT_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_SHORT_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_SHORT_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_SHORT_IDXEN_gfx90a:
    case AMDGPU::BUFFER_STORE_SHORT_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_SHORT_OFFEN_gfx90a:
    case AMDGPU::BUFFER_STORE_SHORT_OFFEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_BOTHEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_BOTHEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_IDXEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_IDXEN_vi:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_OFFEN_gfx10:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_OFFEN_vi: {
      switch (OpNum) {
      case 4:
        // op: offset
        return 0;
      case 5:
        // op: cpol
        return 14;
      case 1:
        // op: vaddr
        return 32;
      case 0:
        // op: vdata
        return 40;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFSET_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFSET_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFSET_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_vi: {
      switch (OpNum) {
      case 4:
        // op: offset
        return 0;
      case 5:
        // op: cpol
        return 15;
      case 0:
        // op: vdata
        return 40;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_BOTHEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_IDXEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_BOTHEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_IDXEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_BOTHEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_IDXEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_IDXEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_IDXEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFEN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_vi: {
      switch (OpNum) {
      case 4:
        // op: offset
        return 0;
      case 5:
        // op: cpol
        return 15;
      case 1:
        // op: vaddr
        return 32;
      case 0:
        // op: vdata
        return 40;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFSET_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFSET_RTN_gfx90a: {
      switch (OpNum) {
      case 4:
        // op: offset
        return 0;
      case 5:
        // op: cpol
        return 17;
      case 0:
        // op: vdata
        return 40;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_IDXEN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFEN_gfx90a: {
      switch (OpNum) {
      case 4:
        // op: offset
        return 0;
      case 5:
        // op: cpol
        return 17;
      case 1:
        // op: vaddr
        return 32;
      case 0:
        // op: vdata
        return 40;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CSUB_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_gfx6_gfx7: {
      switch (OpNum) {
      case 4:
        // op: offset
        return 0;
      case 5:
        // op: cpol
        return 54;
      case 0:
        // op: vdata
        return 40;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CSUB_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CSUB_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CSUB_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_gfx6_gfx7: {
      switch (OpNum) {
      case 4:
        // op: offset
        return 0;
      case 5:
        // op: cpol
        return 54;
      case 1:
        // op: vaddr
        return 32;
      case 0:
        // op: vdata
        return 40;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_gfx11:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_gfx11:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_gfx11: {
      switch (OpNum) {
      case 4:
        // op: offset
        return 0;
      case 6:
        // op: cpol
        return 12;
      case 5:
        // op: format
        return 19;
      case 1:
        // op: vaddr
        return 32;
      case 0:
        // op: vdata
        return 40;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_gfx80:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_ADDR64_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_ADDR64_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_ADDR64_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_ADDR64_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_vi:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_gfx10:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_IDXEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_gfx80:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_ADDR64_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_ADDR64_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_ADDR64_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_ADDR64_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_vi:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_gfx10:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_gfx6_gfx7:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_gfx90a:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_vi: {
      switch (OpNum) {
      case 4:
        // op: offset
        return 0;
      case 6:
        // op: cpol
        return 14;
      case 5:
        // op: format
        return 19;
      case 1:
        // op: vaddr
        return 32;
      case 0:
        // op: vdata
        return 40;
      case 2:
        // op: srsrc
        return 48;
      case 3:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN_gfx12_format: {
      switch (OpNum) {
      case 4:
        // op: offset
        return 72;
      case 0:
        // op: vdata
        return 32;
      case 2:
        // op: srsrc
        return 41;
      case 3:
        // op: soffset
        return 0;
      case 5:
        // op: cpol
        return 7;
      }
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_D16_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SHORT_D16_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SSHORT_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_D16_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX2_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX3_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX4_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORD_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_X_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_TFE_VBUFFER_OFFEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_VBUFFER_BOTHEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_VBUFFER_IDXEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_VBUFFER_IDXEN_gfx12_format:
    case AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFEN_gfx12:
    case AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFEN_gfx12_format: {
      switch (OpNum) {
      case 4:
        // op: offset
        return 72;
      case 1:
        // op: vaddr
        return 64;
      case 0:
        // op: vdata
        return 32;
      case 2:
        // op: srsrc
        return 41;
      case 3:
        // op: soffset
        return 0;
      case 5:
        // op: cpol
        return 7;
      }
      break;
    }
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_gfx12:
    case AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_gfx12: {
      switch (OpNum) {
      case 4:
        // op: offset
        return 72;
      case 1:
        // op: vaddr
        return 64;
      case 0:
        // op: vdata
        return 32;
      case 2:
        // op: srsrc
        return 41;
      case 3:
        // op: soffset
        return 0;
      case 6:
        // op: cpol
        return 7;
      case 5:
        // op: format
        return 55;
      }
      break;
    }
    case AMDGPU::TENSOR_LOAD_TO_LDS_gfx1250:
    case AMDGPU::TENSOR_STORE_FROM_LDS_gfx1250: {
      switch (OpNum) {
      case 4:
        // op: r128
        return 4;
      case 5:
        // op: cpol
        return 7;
      case 0:
        // op: vaddr0
        return 64;
      case 1:
        // op: vaddr1
        return 72;
      case 2:
        // op: vaddr2
        return 80;
      case 3:
        // op: vaddr3
        return 88;
      }
      break;
    }
    case AMDGPU::V_DOT4_F32_BF8_BF8_dpp8_gfx12:
    case AMDGPU::V_DOT4_F32_BF8_FP8_dpp8_gfx12:
    case AMDGPU::V_DOT4_F32_FP8_BF8_dpp8_gfx12:
    case AMDGPU::V_DOT4_F32_FP8_FP8_dpp8_gfx12: {
      switch (OpNum) {
      case 4:
        // op: src2_modifiers
        return 10;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: src1
        return 41;
      case 5:
        // op: src2
        return 50;
      case 2:
        // op: src0
        return 64;
      case 8:
        // op: dpp8
        return 72;
      case 9:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_DOT4_F32_BF8_BF8_dpp_gfx12:
    case AMDGPU::V_DOT4_F32_BF8_FP8_dpp_gfx12:
    case AMDGPU::V_DOT4_F32_FP8_BF8_dpp_gfx12:
    case AMDGPU::V_DOT4_F32_FP8_FP8_dpp_gfx12: {
      switch (OpNum) {
      case 4:
        // op: src2_modifiers
        return 10;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: src1
        return 41;
      case 5:
        // op: src2
        return 50;
      case 8:
        // op: dpp_ctrl
        return 72;
      case 11:
        // op: bound_ctrl
        return 83;
      case 10:
        // op: bank_mask
        return 88;
      case 9:
        // op: row_mask
        return 92;
      case 12:
        // op: fi
        return 82;
      case 2:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_ADD_MAX_I32_e64_dpp8_gfx1250:
    case AMDGPU::V_ADD_MAX_U32_e64_dpp8_gfx1250:
    case AMDGPU::V_ADD_MIN_I32_e64_dpp8_gfx1250:
    case AMDGPU::V_ADD_MIN_U32_e64_dpp8_gfx1250:
    case AMDGPU::V_MAD_I32_I24_e64_dpp8_gfx11:
    case AMDGPU::V_MAD_I32_I24_e64_dpp8_gfx12:
    case AMDGPU::V_MAD_U32_U24_e64_dpp8_gfx11:
    case AMDGPU::V_MAD_U32_U24_e64_dpp8_gfx12:
    case AMDGPU::V_MSAD_U8_e64_dpp8_gfx11:
    case AMDGPU::V_MSAD_U8_e64_dpp8_gfx12:
    case AMDGPU::V_SAD_HI_U8_e64_dpp8_gfx11:
    case AMDGPU::V_SAD_HI_U8_e64_dpp8_gfx12:
    case AMDGPU::V_SAD_U16_e64_dpp8_gfx11:
    case AMDGPU::V_SAD_U16_e64_dpp8_gfx12:
    case AMDGPU::V_SAD_U32_e64_dpp8_gfx11:
    case AMDGPU::V_SAD_U32_e64_dpp8_gfx12:
    case AMDGPU::V_SAD_U8_e64_dpp8_gfx11:
    case AMDGPU::V_SAD_U8_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 5:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: src1
        return 41;
      case 4:
        // op: src2
        return 50;
      case 2:
        // op: src0
        return 64;
      case 6:
        // op: dpp8
        return 72;
      case 7:
        // op: fi
        return 32;
      }
      break;
    }
    case AMDGPU::V_ADD_MAX_I32_e64_dpp_gfx1250:
    case AMDGPU::V_ADD_MAX_U32_e64_dpp_gfx1250:
    case AMDGPU::V_ADD_MIN_I32_e64_dpp_gfx1250:
    case AMDGPU::V_ADD_MIN_U32_e64_dpp_gfx1250:
    case AMDGPU::V_MAD_I32_I24_e64_dpp_gfx11:
    case AMDGPU::V_MAD_I32_I24_e64_dpp_gfx12:
    case AMDGPU::V_MAD_NC_I64_I32_e64_dpp_gfx1250:
    case AMDGPU::V_MAD_NC_U64_U32_e64_dpp_gfx1250:
    case AMDGPU::V_MAD_U32_U24_e64_dpp_gfx11:
    case AMDGPU::V_MAD_U32_U24_e64_dpp_gfx12:
    case AMDGPU::V_MSAD_U8_e64_dpp_gfx11:
    case AMDGPU::V_MSAD_U8_e64_dpp_gfx12:
    case AMDGPU::V_SAD_HI_U8_e64_dpp_gfx11:
    case AMDGPU::V_SAD_HI_U8_e64_dpp_gfx12:
    case AMDGPU::V_SAD_U16_e64_dpp_gfx11:
    case AMDGPU::V_SAD_U16_e64_dpp_gfx12:
    case AMDGPU::V_SAD_U32_e64_dpp_gfx11:
    case AMDGPU::V_SAD_U32_e64_dpp_gfx12:
    case AMDGPU::V_SAD_U8_e64_dpp_gfx11:
    case AMDGPU::V_SAD_U8_e64_dpp_gfx12: {
      switch (OpNum) {
      case 5:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 3:
        // op: src1
        return 41;
      case 4:
        // op: src2
        return 50;
      case 6:
        // op: dpp_ctrl
        return 72;
      case 9:
        // op: bound_ctrl
        return 83;
      case 8:
        // op: bank_mask
        return 88;
      case 7:
        // op: row_mask
        return 92;
      case 10:
        // op: fi
        return 82;
      case 2:
        // op: src0
        return 64;
      }
      break;
    }
    case AMDGPU::V_ADD_CO_U32_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_CO_U32_e64_dpp8_gfx12:
    case AMDGPU::V_SUBREV_CO_U32_e64_dpp8_gfx11:
    case AMDGPU::V_SUBREV_CO_U32_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_CO_U32_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_CO_U32_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 5:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 4:
        // op: src1
        return 41;
      case 3:
        // op: src0
        return 64;
      case 6:
        // op: dpp8
        return 72;
      case 7:
        // op: fi
        return 32;
      case 1:
        // op: sdst
        return 8;
      }
      break;
    }
    case AMDGPU::V_ADD_CO_U32_e64_dpp_gfx11:
    case AMDGPU::V_ADD_CO_U32_e64_dpp_gfx12:
    case AMDGPU::V_SUBREV_CO_U32_e64_dpp_gfx11:
    case AMDGPU::V_SUBREV_CO_U32_e64_dpp_gfx12:
    case AMDGPU::V_SUB_CO_U32_e64_dpp_gfx11:
    case AMDGPU::V_SUB_CO_U32_e64_dpp_gfx12: {
      switch (OpNum) {
      case 5:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 4:
        // op: src1
        return 41;
      case 6:
        // op: dpp_ctrl
        return 72;
      case 9:
        // op: bound_ctrl
        return 83;
      case 8:
        // op: bank_mask
        return 88;
      case 7:
        // op: row_mask
        return 92;
      case 10:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      case 1:
        // op: sdst
        return 8;
      }
      break;
    }
    case AMDGPU::IMAGE_GATHER4H_V2_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4H_V4_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4H_V5_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V2_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V4_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V5_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_V2_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_V4_V1_gfx12:
    case AMDGPU::IMAGE_GATHER4_V5_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V1_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V2_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V3_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V4_V1_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V5_V1_gfx12: {
      switch (OpNum) {
      case 5:
        // op: dim
        return 0;
      case 10:
        // op: tfe
        return 3;
      case 8:
        // op: r128
        return 4;
      case 12:
        // op: d16
        return 5;
      case 9:
        // op: a16
        return 6;
      case 4:
        // op: dmask
        return 22;
      case 0:
        // op: vdata
        return 32;
      case 2:
        // op: rsrc
        return 41;
      case 7:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr0
        return 64;
      case 6:
        // op: unorm
        return 13;
      case 11:
        // op: lwe
        return 40;
      case 3:
        // op: samp
        return 55;
      }
      break;
    }
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V2_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V2_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V2_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V2_gfx12: {
      switch (OpNum) {
      case 5:
        // op: dim
        return 0;
      case 10:
        // op: tfe
        return 3;
      case 8:
        // op: r128
        return 4;
      case 12:
        // op: d16
        return 5;
      case 9:
        // op: a16
        return 6;
      case 4:
        // op: dmask
        return 22;
      case 0:
        // op: vdata
        return 32;
      case 3:
        // op: rsrc
        return 41;
      case 7:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr0
        return 64;
      case 2:
        // op: vaddr1
        return 72;
      case 6:
        // op: unorm
        return 13;
      case 11:
        // op: lwe
        return 40;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_nortn_V2_gfx12: {
      switch (OpNum) {
      case 5:
        // op: dim
        return 0;
      case 10:
        // op: tfe
        return 3;
      case 8:
        // op: r128
        return 4;
      case 12:
        // op: d16
        return 5;
      case 9:
        // op: a16
        return 6;
      case 4:
        // op: dmask
        return 22;
      case 2:
        // op: rsrc
        return 41;
      case 7:
        // op: cpol
        return 7;
      case 0:
        // op: vaddr0
        return 64;
      case 1:
        // op: vaddr1
        return 72;
      case 6:
        // op: unorm
        return 13;
      case 11:
        // op: lwe
        return 40;
      case 3:
        // op: samp
        return 55;
      }
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V1_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V2_V1_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V3_V1_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V4_V1_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V5_V1_gfx12: {
      switch (OpNum) {
      case 5:
        // op: dim
        return 0;
      case 10:
        // op: tfe
        return 3;
      case 8:
        // op: r128
        return 4;
      case 9:
        // op: a16
        return 6;
      case 4:
        // op: dmask
        return 22;
      case 0:
        // op: vdata
        return 32;
      case 2:
        // op: rsrc
        return 41;
      case 7:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr0
        return 64;
      case 6:
        // op: unorm
        return 13;
      case 11:
        // op: lwe
        return 40;
      case 3:
        // op: samp
        return 55;
      }
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_V1_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_V2_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_V3_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_V4_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_V5_V2_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V1_V2_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V2_V2_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V3_V2_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V4_V2_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V5_V2_gfx12:
    case AMDGPU::IMAGE_STORE_V1_V2_gfx12:
    case AMDGPU::IMAGE_STORE_V2_V2_gfx12:
    case AMDGPU::IMAGE_STORE_V3_V2_gfx12:
    case AMDGPU::IMAGE_STORE_V4_V2_gfx12:
    case AMDGPU::IMAGE_STORE_V5_V2_gfx12: {
      switch (OpNum) {
      case 5:
        // op: dim
        return 0;
      case 9:
        // op: tfe
        return 55;
      case 7:
        // op: r128
        return 4;
      case 10:
        // op: d16
        return 5;
      case 8:
        // op: a16
        return 6;
      case 4:
        // op: dmask
        return 22;
      case 0:
        // op: vdata
        return 32;
      case 3:
        // op: rsrc
        return 41;
      case 6:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr0
        return 64;
      case 2:
        // op: vaddr1
        return 72;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V2_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V2_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V2_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V2_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V2_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V2_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V2_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V2_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V1_V2_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V2_V2_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V3_V2_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V4_V2_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V5_V2_gfx12: {
      switch (OpNum) {
      case 5:
        // op: dim
        return 0;
      case 9:
        // op: tfe
        return 55;
      case 7:
        // op: r128
        return 4;
      case 8:
        // op: a16
        return 6;
      case 4:
        // op: dmask
        return 22;
      case 0:
        // op: vdata
        return 32;
      case 3:
        // op: rsrc
        return 41;
      case 6:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr0
        return 64;
      case 2:
        // op: vaddr1
        return 72;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V1_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V1_gfx12: {
      switch (OpNum) {
      case 5:
        // op: dim
        return 0;
      case 9:
        // op: tfe
        return 55;
      case 7:
        // op: r128
        return 4;
      case 8:
        // op: a16
        return 6;
      case 4:
        // op: dmask
        return 22;
      case 1:
        // op: vdata
        return 32;
      case 3:
        // op: rsrc
        return 41;
      case 6:
        // op: cpol
        return 7;
      case 2:
        // op: vaddr0
        return 64;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V3_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_nortn_V3_nsa_gfx10: {
      switch (OpNum) {
      case 5:
        // op: dmask
        return 8;
      case 7:
        // op: unorm
        return 12;
      case 8:
        // op: cpol
        return 7;
      case 9:
        // op: r128
        return 15;
      case 11:
        // op: tfe
        return 16;
      case 12:
        // op: lwe
        return 17;
      case 13:
        // op: d16
        return 63;
      case 3:
        // op: srsrc
        return 48;
      case 4:
        // op: ssamp
        return 53;
      case 0:
        // op: vaddr0
        return 32;
      case 6:
        // op: dim
        return 3;
      case 10:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V3_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_nortn_V3_nsa_gfx11: {
      switch (OpNum) {
      case 5:
        // op: dmask
        return 8;
      case 7:
        // op: unorm
        return 7;
      case 8:
        // op: cpol
        return 12;
      case 9:
        // op: r128
        return 15;
      case 11:
        // op: tfe
        return 53;
      case 12:
        // op: lwe
        return 54;
      case 3:
        // op: srsrc
        return 48;
      case 4:
        // op: ssamp
        return 58;
      case 13:
        // op: d16
        return 17;
      case 10:
        // op: a16
        return 16;
      case 0:
        // op: vaddr0
        return 32;
      case 6:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::DS_WRITE2ST64_B32_vi:
    case AMDGPU::DS_WRITE2ST64_B32_vi_agpr:
    case AMDGPU::DS_WRITE2ST64_B32_vi_gfx9:
    case AMDGPU::DS_WRITE2ST64_B64_vi:
    case AMDGPU::DS_WRITE2ST64_B64_vi_agpr:
    case AMDGPU::DS_WRITE2ST64_B64_vi_gfx9:
    case AMDGPU::DS_WRITE2_B32_vi:
    case AMDGPU::DS_WRITE2_B32_vi_agpr:
    case AMDGPU::DS_WRITE2_B32_vi_gfx9:
    case AMDGPU::DS_WRITE2_B64_vi:
    case AMDGPU::DS_WRITE2_B64_vi_agpr:
    case AMDGPU::DS_WRITE2_B64_vi_gfx9: {
      switch (OpNum) {
      case 5:
        // op: gds
        return 16;
      case 0:
        // op: addr
        return 32;
      case 1:
        // op: data0
        return 40;
      case 2:
        // op: data1
        return 48;
      case 3:
        // op: offset0
        return 0;
      case 4:
        // op: offset1
        return 8;
      }
      break;
    }
    case AMDGPU::DS_WRITE2ST64_B32_gfx10:
    case AMDGPU::DS_WRITE2ST64_B32_gfx11:
    case AMDGPU::DS_WRITE2ST64_B32_gfx6_gfx7:
    case AMDGPU::DS_WRITE2ST64_B64_gfx10:
    case AMDGPU::DS_WRITE2ST64_B64_gfx11:
    case AMDGPU::DS_WRITE2ST64_B64_gfx6_gfx7:
    case AMDGPU::DS_WRITE2_B32_gfx10:
    case AMDGPU::DS_WRITE2_B32_gfx11:
    case AMDGPU::DS_WRITE2_B32_gfx6_gfx7:
    case AMDGPU::DS_WRITE2_B64_gfx10:
    case AMDGPU::DS_WRITE2_B64_gfx11:
    case AMDGPU::DS_WRITE2_B64_gfx6_gfx7: {
      switch (OpNum) {
      case 5:
        // op: gds
        return 17;
      case 0:
        // op: addr
        return 32;
      case 1:
        // op: data0
        return 40;
      case 2:
        // op: data1
        return 48;
      case 3:
        // op: offset0
        return 0;
      case 4:
        // op: offset1
        return 8;
      }
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CSUB_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CSUB_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_CSUB_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_gfx11:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_gfx11: {
      switch (OpNum) {
      case 5:
        // op: offset
        return 0;
      case 6:
        // op: cpol
        return 12;
      case 2:
        // op: vaddr
        return 32;
      case 0:
        // op: vdata
        return 40;
      case 3:
        // op: srsrc
        return 48;
      case 4:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_BOTHEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_IDXEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_BOTHEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_IDXEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_BOTHEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_IDXEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_IDXEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_IDXEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFEN_RTN_gfx940:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_vi:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_vi: {
      switch (OpNum) {
      case 5:
        // op: offset
        return 0;
      case 6:
        // op: cpol
        return 15;
      case 2:
        // op: vaddr
        return 32;
      case 0:
        // op: vdata
        return 40;
      case 3:
        // op: srsrc
        return 48;
      case 4:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_IDXEN_RTN_gfx90a:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFEN_RTN_gfx90a: {
      switch (OpNum) {
      case 5:
        // op: offset
        return 0;
      case 6:
        // op: cpol
        return 17;
      case 2:
        // op: vaddr
        return 32;
      case 0:
        // op: vdata
        return 40;
      case 3:
        // op: srsrc
        return 48;
      case 4:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_CSUB_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CSUB_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_CSUB_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_gfx6_gfx7:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_gfx10:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_gfx6_gfx7: {
      switch (OpNum) {
      case 5:
        // op: offset
        return 0;
      case 6:
        // op: cpol
        return 54;
      case 2:
        // op: vaddr
        return 32;
      case 0:
        // op: vdata
        return 40;
      case 3:
        // op: srsrc
        return 48;
      case 4:
        // op: soffset
        return 56;
      }
      break;
    }
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_BOTHEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_BOTHEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_IDXEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_IDXEN_RTN_gfx12_format:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFEN_RTN_gfx12:
    case AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFEN_RTN_gfx12_format: {
      switch (OpNum) {
      case 5:
        // op: offset
        return 72;
      case 2:
        // op: vaddr
        return 64;
      case 0:
        // op: vdata
        return 32;
      case 3:
        // op: srsrc
        return 41;
      case 4:
        // op: soffset
        return 0;
      case 6:
        // op: cpol
        return 7;
      }
      break;
    }
    case AMDGPU::V_ADD_CO_CI_U32_e64_dpp8_gfx11:
    case AMDGPU::V_ADD_CO_CI_U32_e64_dpp8_gfx12:
    case AMDGPU::V_SUBREV_CO_CI_U32_e64_dpp8_gfx11:
    case AMDGPU::V_SUBREV_CO_CI_U32_e64_dpp8_gfx12:
    case AMDGPU::V_SUB_CO_CI_U32_e64_dpp8_gfx11:
    case AMDGPU::V_SUB_CO_CI_U32_e64_dpp8_gfx12: {
      switch (OpNum) {
      case 6:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2
        return 50;
      case 3:
        // op: src0
        return 64;
      case 7:
        // op: dpp8
        return 72;
      case 8:
        // op: fi
        return 32;
      case 1:
        // op: sdst
        return 8;
      }
      break;
    }
    case AMDGPU::V_ADD_CO_CI_U32_e64_dpp_gfx11:
    case AMDGPU::V_ADD_CO_CI_U32_e64_dpp_gfx12:
    case AMDGPU::V_MAD_CO_I64_I32_e64_dpp_gfx12:
    case AMDGPU::V_MAD_CO_U64_U32_e64_dpp_gfx12:
    case AMDGPU::V_SUBREV_CO_CI_U32_e64_dpp_gfx11:
    case AMDGPU::V_SUBREV_CO_CI_U32_e64_dpp_gfx12:
    case AMDGPU::V_SUB_CO_CI_U32_e64_dpp_gfx11:
    case AMDGPU::V_SUB_CO_CI_U32_e64_dpp_gfx12: {
      switch (OpNum) {
      case 6:
        // op: clamp
        return 15;
      case 0:
        // op: vdst
        return 0;
      case 4:
        // op: src1
        return 41;
      case 5:
        // op: src2
        return 50;
      case 7:
        // op: dpp_ctrl
        return 72;
      case 10:
        // op: bound_ctrl
        return 83;
      case 9:
        // op: bank_mask
        return 88;
      case 8:
        // op: row_mask
        return 92;
      case 11:
        // op: fi
        return 82;
      case 3:
        // op: src0
        return 64;
      case 1:
        // op: sdst
        return 8;
      }
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_V1_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_V2_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_V3_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_V4_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_V5_V3_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V1_V3_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V2_V3_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V3_V3_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V4_V3_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V5_V3_gfx12:
    case AMDGPU::IMAGE_STORE_V1_V3_gfx12:
    case AMDGPU::IMAGE_STORE_V2_V3_gfx12:
    case AMDGPU::IMAGE_STORE_V3_V3_gfx12:
    case AMDGPU::IMAGE_STORE_V4_V3_gfx12:
    case AMDGPU::IMAGE_STORE_V5_V3_gfx12: {
      switch (OpNum) {
      case 6:
        // op: dim
        return 0;
      case 10:
        // op: tfe
        return 55;
      case 8:
        // op: r128
        return 4;
      case 11:
        // op: d16
        return 5;
      case 9:
        // op: a16
        return 6;
      case 5:
        // op: dmask
        return 22;
      case 0:
        // op: vdata
        return 32;
      case 4:
        // op: rsrc
        return 41;
      case 7:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr0
        return 64;
      case 2:
        // op: vaddr1
        return 72;
      case 3:
        // op: vaddr2
        return 80;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V3_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V3_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V3_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V3_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V3_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V3_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V3_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V3_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V1_V3_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V2_V3_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V3_V3_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V4_V3_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V5_V3_gfx12: {
      switch (OpNum) {
      case 6:
        // op: dim
        return 0;
      case 10:
        // op: tfe
        return 55;
      case 8:
        // op: r128
        return 4;
      case 9:
        // op: a16
        return 6;
      case 5:
        // op: dmask
        return 22;
      case 0:
        // op: vdata
        return 32;
      case 4:
        // op: rsrc
        return 41;
      case 7:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr0
        return 64;
      case 2:
        // op: vaddr1
        return 72;
      case 3:
        // op: vaddr2
        return 80;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V2_gfx12: {
      switch (OpNum) {
      case 6:
        // op: dim
        return 0;
      case 10:
        // op: tfe
        return 55;
      case 8:
        // op: r128
        return 4;
      case 9:
        // op: a16
        return 6;
      case 5:
        // op: dmask
        return 22;
      case 1:
        // op: vdata
        return 32;
      case 4:
        // op: rsrc
        return 41;
      case 7:
        // op: cpol
        return 7;
      case 2:
        // op: vaddr0
        return 64;
      case 3:
        // op: vaddr1
        return 72;
      }
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V2_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V2_V2_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V3_V2_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V4_V2_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V5_V2_gfx12: {
      switch (OpNum) {
      case 6:
        // op: dim
        return 0;
      case 11:
        // op: tfe
        return 3;
      case 9:
        // op: r128
        return 4;
      case 10:
        // op: a16
        return 6;
      case 5:
        // op: dmask
        return 22;
      case 0:
        // op: vdata
        return 32;
      case 3:
        // op: rsrc
        return 41;
      case 8:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr0
        return 64;
      case 2:
        // op: vaddr1
        return 72;
      case 7:
        // op: unorm
        return 13;
      case 12:
        // op: lwe
        return 40;
      case 4:
        // op: samp
        return 55;
      }
      break;
    }
    case AMDGPU::IMAGE_GATHER4H_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4H_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4H_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_O_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_O_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_O_V5_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_V2_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_V4_V2_gfx12:
    case AMDGPU::IMAGE_GATHER4_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V1_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V2_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V3_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V4_V2_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V5_V2_gfx12: {
      switch (OpNum) {
      case 6:
        // op: dim
        return 0;
      case 11:
        // op: tfe
        return 3;
      case 9:
        // op: r128
        return 4;
      case 13:
        // op: d16
        return 5;
      case 10:
        // op: a16
        return 6;
      case 5:
        // op: dmask
        return 22;
      case 0:
        // op: vdata
        return 32;
      case 3:
        // op: rsrc
        return 41;
      case 8:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr0
        return 64;
      case 2:
        // op: vaddr1
        return 72;
      case 7:
        // op: unorm
        return 13;
      case 12:
        // op: lwe
        return 40;
      case 4:
        // op: samp
        return 55;
      }
      break;
    }
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V3_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V3_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V3_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V3_gfx12: {
      switch (OpNum) {
      case 6:
        // op: dim
        return 0;
      case 11:
        // op: tfe
        return 3;
      case 9:
        // op: r128
        return 4;
      case 13:
        // op: d16
        return 5;
      case 10:
        // op: a16
        return 6;
      case 5:
        // op: dmask
        return 22;
      case 0:
        // op: vdata
        return 32;
      case 4:
        // op: rsrc
        return 41;
      case 8:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr0
        return 64;
      case 2:
        // op: vaddr1
        return 72;
      case 3:
        // op: vaddr2
        return 80;
      case 7:
        // op: unorm
        return 13;
      case 12:
        // op: lwe
        return 40;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_nortn_V3_gfx12: {
      switch (OpNum) {
      case 6:
        // op: dim
        return 0;
      case 11:
        // op: tfe
        return 3;
      case 9:
        // op: r128
        return 4;
      case 13:
        // op: d16
        return 5;
      case 10:
        // op: a16
        return 6;
      case 5:
        // op: dmask
        return 22;
      case 3:
        // op: rsrc
        return 41;
      case 8:
        // op: cpol
        return 7;
      case 0:
        // op: vaddr0
        return 64;
      case 1:
        // op: vaddr1
        return 72;
      case 2:
        // op: vaddr2
        return 80;
      case 7:
        // op: unorm
        return 13;
      case 12:
        // op: lwe
        return 40;
      case 4:
        // op: samp
        return 55;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V4_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V4_nsa_gfx10: {
      switch (OpNum) {
      case 6:
        // op: dmask
        return 8;
      case 8:
        // op: unorm
        return 12;
      case 9:
        // op: cpol
        return 7;
      case 10:
        // op: r128
        return 15;
      case 12:
        // op: tfe
        return 16;
      case 13:
        // op: lwe
        return 17;
      case 14:
        // op: d16
        return 63;
      case 4:
        // op: srsrc
        return 48;
      case 5:
        // op: ssamp
        return 53;
      case 0:
        // op: vaddr0
        return 32;
      case 7:
        // op: dim
        return 3;
      case 11:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V4_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V4_nsa_gfx11: {
      switch (OpNum) {
      case 6:
        // op: dmask
        return 8;
      case 8:
        // op: unorm
        return 7;
      case 9:
        // op: cpol
        return 12;
      case 10:
        // op: r128
        return 15;
      case 12:
        // op: tfe
        return 53;
      case 13:
        // op: lwe
        return 54;
      case 4:
        // op: srsrc
        return 48;
      case 5:
        // op: ssamp
        return 58;
      case 14:
        // op: d16
        return 17;
      case 11:
        // op: a16
        return 16;
      case 0:
        // op: vaddr0
        return 32;
      case 7:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V4_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_NORTN_V5_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_NORTN_V3_V4_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V1_V4_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V2_V4_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V3_V4_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V4_V4_gfx12:
    case AMDGPU::IMAGE_GET_RESINFO_V5_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V1_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V2_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V3_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V4_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_PCK_V5_V4_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_PCK_V5_V4_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V1_V4_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V2_V4_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V3_V4_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V4_V4_gfx12:
    case AMDGPU::IMAGE_STORE_PCK_V5_V4_gfx12: {
      switch (OpNum) {
      case 7:
        // op: dim
        return 0;
      case 11:
        // op: tfe
        return 55;
      case 9:
        // op: r128
        return 4;
      case 10:
        // op: a16
        return 6;
      case 6:
        // op: dmask
        return 22;
      case 0:
        // op: vdata
        return 32;
      case 5:
        // op: rsrc
        return 41;
      case 8:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr0
        return 64;
      case 2:
        // op: vaddr1
        return 72;
      case 3:
        // op: vaddr2
        return 80;
      case 4:
        // op: vaddr3
        return 88;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V3_gfx12: {
      switch (OpNum) {
      case 7:
        // op: dim
        return 0;
      case 11:
        // op: tfe
        return 55;
      case 9:
        // op: r128
        return 4;
      case 10:
        // op: a16
        return 6;
      case 6:
        // op: dmask
        return 22;
      case 1:
        // op: vdata
        return 32;
      case 5:
        // op: rsrc
        return 41;
      case 8:
        // op: cpol
        return 7;
      case 2:
        // op: vaddr0
        return 64;
      case 3:
        // op: vaddr1
        return 72;
      case 4:
        // op: vaddr2
        return 80;
      }
      break;
    }
    case AMDGPU::IMAGE_LOAD_MIP_V1_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V2_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V3_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V4_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_MIP_V5_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_V1_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_V2_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_V3_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_V4_V4_gfx12:
    case AMDGPU::IMAGE_LOAD_V5_V4_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V1_V4_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V2_V4_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V3_V4_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V4_V4_gfx12:
    case AMDGPU::IMAGE_STORE_MIP_V5_V4_gfx12:
    case AMDGPU::IMAGE_STORE_V1_V4_gfx12:
    case AMDGPU::IMAGE_STORE_V2_V4_gfx12:
    case AMDGPU::IMAGE_STORE_V3_V4_gfx12:
    case AMDGPU::IMAGE_STORE_V4_V4_gfx12:
    case AMDGPU::IMAGE_STORE_V5_V4_gfx12: {
      switch (OpNum) {
      case 7:
        // op: dim
        return 0;
      case 11:
        // op: tfe
        return 55;
      case 9:
        // op: r128
        return 4;
      case 12:
        // op: d16
        return 5;
      case 10:
        // op: a16
        return 6;
      case 6:
        // op: dmask
        return 22;
      case 0:
        // op: vdata
        return 32;
      case 5:
        // op: rsrc
        return 41;
      case 8:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr0
        return 64;
      case 2:
        // op: vaddr1
        return 72;
      case 3:
        // op: vaddr2
        return 80;
      case 4:
        // op: vaddr3
        return 88;
      }
      break;
    }
    case AMDGPU::IMAGE_GET_LOD_V1_V3_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V2_V3_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V3_V3_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V4_V3_gfx12:
    case AMDGPU::IMAGE_GET_LOD_V5_V3_gfx12: {
      switch (OpNum) {
      case 7:
        // op: dim
        return 0;
      case 12:
        // op: tfe
        return 3;
      case 10:
        // op: r128
        return 4;
      case 11:
        // op: a16
        return 6;
      case 6:
        // op: dmask
        return 22;
      case 0:
        // op: vdata
        return 32;
      case 4:
        // op: rsrc
        return 41;
      case 9:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr0
        return 64;
      case 2:
        // op: vaddr1
        return 72;
      case 3:
        // op: vaddr2
        return 80;
      case 8:
        // op: unorm
        return 13;
      case 13:
        // op: lwe
        return 40;
      case 5:
        // op: samp
        return 55;
      }
      break;
    }
    case AMDGPU::IMAGE_GATHER4H_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4H_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4H_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_V2_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_V4_V3_gfx12:
    case AMDGPU::IMAGE_GATHER4_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V1_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V2_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V3_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V4_V3_gfx12:
    case AMDGPU::IMAGE_SAMPLE_V5_V3_gfx12: {
      switch (OpNum) {
      case 7:
        // op: dim
        return 0;
      case 12:
        // op: tfe
        return 3;
      case 10:
        // op: r128
        return 4;
      case 14:
        // op: d16
        return 5;
      case 11:
        // op: a16
        return 6;
      case 6:
        // op: dmask
        return 22;
      case 0:
        // op: vdata
        return 32;
      case 4:
        // op: rsrc
        return 41;
      case 9:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr0
        return 64;
      case 2:
        // op: vaddr1
        return 72;
      case 3:
        // op: vaddr2
        return 80;
      case 8:
        // op: unorm
        return 13;
      case 13:
        // op: lwe
        return 40;
      case 5:
        // op: samp
        return 55;
      }
      break;
    }
    case AMDGPU::IMAGE_MSAA_LOAD_V2_V4_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V3_V4_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V4_V4_gfx12:
    case AMDGPU::IMAGE_MSAA_LOAD_V5_V4_gfx12: {
      switch (OpNum) {
      case 7:
        // op: dim
        return 0;
      case 12:
        // op: tfe
        return 3;
      case 10:
        // op: r128
        return 4;
      case 14:
        // op: d16
        return 5;
      case 11:
        // op: a16
        return 6;
      case 6:
        // op: dmask
        return 22;
      case 0:
        // op: vdata
        return 32;
      case 5:
        // op: rsrc
        return 41;
      case 9:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr0
        return 64;
      case 2:
        // op: vaddr1
        return 72;
      case 3:
        // op: vaddr2
        return 80;
      case 4:
        // op: vaddr3
        return 88;
      case 8:
        // op: unorm
        return 13;
      case 13:
        // op: lwe
        return 40;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V12_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_nortn_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_nortn_V4_gfx12: {
      switch (OpNum) {
      case 7:
        // op: dim
        return 0;
      case 12:
        // op: tfe
        return 3;
      case 10:
        // op: r128
        return 4;
      case 14:
        // op: d16
        return 5;
      case 11:
        // op: a16
        return 6;
      case 6:
        // op: dmask
        return 22;
      case 4:
        // op: rsrc
        return 41;
      case 9:
        // op: cpol
        return 7;
      case 0:
        // op: vaddr0
        return 64;
      case 1:
        // op: vaddr1
        return 72;
      case 2:
        // op: vaddr2
        return 80;
      case 3:
        // op: vaddr3
        return 88;
      case 8:
        // op: unorm
        return 13;
      case 13:
        // op: lwe
        return 40;
      case 5:
        // op: samp
        return 55;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V5_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V5_nsa_gfx10: {
      switch (OpNum) {
      case 7:
        // op: dmask
        return 8;
      case 9:
        // op: unorm
        return 12;
      case 10:
        // op: cpol
        return 7;
      case 11:
        // op: r128
        return 15;
      case 13:
        // op: tfe
        return 16;
      case 14:
        // op: lwe
        return 17;
      case 15:
        // op: d16
        return 63;
      case 5:
        // op: srsrc
        return 48;
      case 6:
        // op: ssamp
        return 53;
      case 0:
        // op: vaddr0
        return 32;
      case 8:
        // op: dim
        return 3;
      case 12:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_CL_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_B_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_CL_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_B_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_CL_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V12_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_L_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_C_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V11_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V10_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V5_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V6_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V7_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V8_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V9_nsa_gfx11:
    case AMDGPU::IMAGE_SAMPLE_L_O_nortn_V5_nsa_gfx11: {
      switch (OpNum) {
      case 7:
        // op: dmask
        return 8;
      case 9:
        // op: unorm
        return 7;
      case 10:
        // op: cpol
        return 12;
      case 11:
        // op: r128
        return 15;
      case 13:
        // op: tfe
        return 53;
      case 14:
        // op: lwe
        return 54;
      case 5:
        // op: srsrc
        return 48;
      case 6:
        // op: ssamp
        return 58;
      case 15:
        // op: d16
        return 17;
      case 12:
        // op: a16
        return 16;
      case 0:
        // op: vaddr0
        return 32;
      case 8:
        // op: dim
        return 2;
      }
      break;
    }
    case AMDGPU::EXP_DONE_gfx10:
    case AMDGPU::EXP_DONE_si:
    case AMDGPU::EXP_DONE_vi:
    case AMDGPU::EXP_gfx10:
    case AMDGPU::EXP_si:
    case AMDGPU::EXP_vi: {
      switch (OpNum) {
      case 7:
        // op: en
        return 0;
      case 0:
        // op: tgt
        return 4;
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1
        return 40;
      case 3:
        // op: src2
        return 48;
      case 4:
        // op: src3
        return 56;
      case 6:
        // op: compr
        return 10;
      case 5:
        // op: vm
        return 12;
      }
      break;
    }
    case AMDGPU::EXP_DONE_gfx11:
    case AMDGPU::EXP_DONE_gfx12:
    case AMDGPU::EXP_ROW_DONE_gfx11:
    case AMDGPU::EXP_ROW_DONE_gfx12:
    case AMDGPU::EXP_ROW_gfx11:
    case AMDGPU::EXP_ROW_gfx12:
    case AMDGPU::EXP_gfx11:
    case AMDGPU::EXP_gfx12: {
      switch (OpNum) {
      case 7:
        // op: en
        return 0;
      case 0:
        // op: tgt
        return 4;
      case 1:
        // op: src0
        return 32;
      case 2:
        // op: src1
        return 40;
      case 3:
        // op: src2
        return 48;
      case 4:
        // op: src3
        return 56;
      }
      break;
    }
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_FLT_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_ADD_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_AND_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V4_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_CMPSWAP_V5_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_DEC_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_INC_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MAX_FLT_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_MIN_FLT_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_OR_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMAX_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SMIN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SUB_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_SWAP_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMAX_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_UMIN_V3_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_gfx12:
    case AMDGPU::IMAGE_ATOMIC_XOR_V3_V4_gfx12: {
      switch (OpNum) {
      case 8:
        // op: dim
        return 0;
      case 12:
        // op: tfe
        return 55;
      case 10:
        // op: r128
        return 4;
      case 11:
        // op: a16
        return 6;
      case 7:
        // op: dmask
        return 22;
      case 1:
        // op: vdata
        return 32;
      case 6:
        // op: rsrc
        return 41;
      case 9:
        // op: cpol
        return 7;
      case 2:
        // op: vaddr0
        return 64;
      case 3:
        // op: vaddr1
        return 72;
      case 4:
        // op: vaddr2
        return 80;
      case 5:
        // op: vaddr3
        return 88;
      }
      break;
    }
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V2_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V4_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_CL_V5_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_B_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_CL_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V6_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V6_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V6_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_V2_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_V4_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_B_V5_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V2_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V4_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_CL_V5_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_LZ_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V2_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V4_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_L_V5_V5_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_C_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_LZ_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_L_V5_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_GATHER4_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_CL_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_B_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_CL_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_B_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_CL_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V12_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V12_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V12_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V12_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V12_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_D_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_L_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_C_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V11_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_CL_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_G16_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V10_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_O_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V1_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V2_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V3_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V4_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V6_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V7_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V8_gfx12:
    case AMDGPU::IMAGE_SAMPLE_D_V5_V9_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V1_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V2_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V3_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V4_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_O_V5_V5_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_L_V5_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V1_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V2_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V3_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V4_V4_gfx12:
    case AMDGPU::IMAGE_SAMPLE_O_V5_V4_gfx12: {
      switch (OpNum) {
      case 8:
        // op: dim
        return 0;
      case 13:
        // op: tfe
        return 3;
      case 11:
        // op: r128
        return 4;
      case 15:
        // op: d16
        return 5;
      case 12:
        // op: a16
        return 6;
      case 7:
        // op: dmask
        return 22;
      case 0:
        // op: vdata
        return 32;
      case 5:
        // op: rsrc
        return 41;
      case 10:
        // op: cpol
        return 7;
      case 1:
        // op: vaddr0
        return 64;
      case 2:
        // op: vaddr1
        return 72;
      case 3:
        // op: vaddr2
        return 80;
      case 4:
        // op: vaddr3
        return 88;
      case 9:
        // op: unorm
        return 13;
      case 14:
        // op: lwe
        return 40;
      case 6:
        // op: samp
        return 55;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_B_CL_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CL_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_L_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V6_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V6_nsa_gfx10: {
      switch (OpNum) {
      case 8:
        // op: dmask
        return 8;
      case 10:
        // op: unorm
        return 12;
      case 11:
        // op: cpol
        return 7;
      case 12:
        // op: r128
        return 15;
      case 14:
        // op: tfe
        return 16;
      case 15:
        // op: lwe
        return 17;
      case 16:
        // op: d16
        return 63;
      case 6:
        // op: srsrc
        return 48;
      case 7:
        // op: ssamp
        return 53;
      case 0:
        // op: vaddr0
        return 32;
      case 9:
        // op: dim
        return 3;
      case 13:
        // op: a16
        return 62;
      }
      break;
    }
    case AMDGPU::IMAGE_SAMPLE_CD_CL_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_O_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_CL_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_O_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_CD_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_B_CL_O_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_CL_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_O_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_CD_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_O_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_CL_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_O_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_C_D_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_O_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_CL_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_G16_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_O_nortn_V7_nsa_gfx10:
    case AMDGPU::IMAGE_SAMPLE_D_nortn_V7_nsa_gfx10: {
      switch (OpNum) {
      case 9:
        // op: dmask
        return 8;
      case 11:
        // op: unorm
        return 12;
      case 12:
        // op: cpol
        return 7;
      case 13:
        // op: r128
        return 15;
      case 15:
        // op: tfe
        return 16;
      case 16:
        // op: lwe
        return 17;
      case 17:
        // op: d16
        return 63;
      case 7:
        // op: srsrc
        return 48;
      case 8:
        // op: ssamp
        return 53;
      case 0:
        // op: vaddr0
        return 32;
      case 10:
        // op: dim
        return 3;
      case 14:
        // op: a16
        return 62;
      }
      break;
    }
  default:
    reportUnsupportedInst(MI);
  }
  reportUnsupportedOperand(MI, OpNum);
}

#endif // GET_OPERAND_BIT_OFFSET

