/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|*  * PPC Disassembler                                                        *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/DataTypes.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/LEB128.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/TargetParser/SubtargetFeature.h"
#include <assert.h>

namespace {

// InsnBitWidth is essentially a type trait used by the decoder emitter to query
// the supported bitwidth for a given type. But default, the value is 0, making
// it an invalid type for use as `InsnType` when instantiating the decoder.
// Individual targets are expected to provide specializations for these based
// on their usage.
template <typename T> constexpr uint32_t InsnBitWidth = 0;

[[maybe_unused]]
static DecodeStatus Decodeppc_ptr_rcRegClassByHwMode(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) {
  switch (Decoder->getSubtargetInfo().getHwMode(MCSubtargetInfo::HwMode_RegInfo)) {
  case 0: // DefaultMode
    return DecodeGPRCRegisterClass(Inst, Imm, Addr, Decoder);
  case 1: // PPC64
    return DecodeG8RCRegisterClass(Inst, Imm, Addr, Decoder);
  default:
    llvm_unreachable("no decoder for hwmode");
  }
}

[[maybe_unused]]
static DecodeStatus Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) {
  switch (Decoder->getSubtargetInfo().getHwMode(MCSubtargetInfo::HwMode_RegInfo)) {
  case 0: // DefaultMode
    return DecodeGPRCRegisterClass(Inst, Imm, Addr, Decoder);
  case 1: // PPC64
    return DecodeG8RCRegisterClass(Inst, Imm, Addr, Decoder);
  default:
    llvm_unreachable("no decoder for hwmode");
  }
}

[[maybe_unused]]
static DecodeStatus Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) {
  switch (Decoder->getSubtargetInfo().getHwMode(MCSubtargetInfo::HwMode_RegInfo)) {
  case 0: // DefaultMode
    return DecodeGPRC_NOR0RegisterClass(Inst, Imm, Addr, Decoder);
  case 1: // PPC64
    return DecodeG8RC_NOX0RegisterClass(Inst, Imm, Addr, Decoder);
  default:
    llvm_unreachable("no decoder for hwmode");
  }
}


static const uint8_t DecoderTable32[16427] = {
  OPC_SwitchField, 26, 6,                    //     0: switch Inst[31:26] {
  0, 9,                                      //     3: case 0x0: {
  OPC_CheckField, 1, 10, 128, 2,             //     5:  check Inst[10:1] == 0x100
  OPC_Decode, 169, 4, 0,                     //    10:  decode to ATTN using decoder 0
                                             //    10: }
  2, 4,                                      //    14: case 0x2: {
  OPC_Decode, 244, 16, 1,                    //    16:  decode to TDI using decoder 1
                                             //    16: }
  3, 4,                                      //    20: case 0x3: {
  OPC_Decode, 148, 17, 2,                    //    22:  decode to TWI using decoder 2
                                             //    22: }
  4, 186, 31,                                //    26: case 0x4: {
  OPC_SwitchField, 1, 5,                     //    29:  switch Inst[5:1] {
  0, 215, 3,                                 //    32:  case 0x0: {
  OPC_SwitchField, 6, 3,                     //    35:   switch Inst[8:6] {
  0, 68,                                     //    38:   case 0x0: {
  OPC_SwitchField, 0, 1,                     //    40:    switch Inst[0] {
  0, 27,                                     //    43:    case 0x0: {
  OPC_SwitchField, 9, 2,                     //    45:     switch Inst[10:9] {
  0, 4,                                      //    48:     case 0x0: {
  OPC_Decode, 162, 17, 3,                    //    50:      decode to VADDUBM using decoder 3
                                             //    50:     }
  1, 4,                                      //    54:     case 0x1: {
  OPC_Decode, 163, 17, 3,                    //    56:      decode to VADDUBS using decoder 3
                                             //    56:     }
  2, 4,                                      //    60:     case 0x2: {
  OPC_Decode, 130, 20, 3,                    //    62:      decode to VSUBUBM using decoder 3
                                             //    62:     }
  3, 0,                                      //    66:     case 0x3: {
  OPC_Decode, 131, 20, 3,                    //    68:      decode to VSUBUBS using decoder 3
                                             //    68:     }
                                             //    68:     } // switch Inst[10:9]
                                             //    68:    }
  1, 0,                                      //    72:    case 0x1: {
  OPC_SwitchField, 10, 1,                    //    74:     switch Inst[10] {
  0, 23,                                     //    77:     case 0x0: {
  OPC_SwitchField, 9, 1,                     //    79:      switch Inst[9] {
  0, 8,                                      //    82:      case 0x0: {
  OPC_CheckField, 11, 5, 0,                  //    84:       check Inst[15:11] == 0x0
  OPC_Decode, 253, 18, 4,                    //    88:       decode to VMUL10CUQ using decoder 4
                                             //    88:      }
  1, 0,                                      //    92:      case 0x1: {
  OPC_CheckField, 11, 5, 0,                  //    94:       check Inst[15:11] == 0x0
  OPC_Decode, 128, 19, 4,                    //    98:       decode to VMUL10UQ using decoder 4
                                             //    98:      }
                                             //    98:      } // switch Inst[9]
                                             //    98:     }
  1, 0,                                      //   102:     case 0x1: {
  OPC_Decode, 191, 4, 5,                     //   104:      decode to BCDADD_rec using decoder 5
                                             //   104:     }
                                             //   104:     } // switch Inst[10]
                                             //   104:    }
                                             //   104:    } // switch Inst[0]
                                             //   104:   }
  1, 60,                                     //   108:   case 0x1: {
  OPC_SwitchField, 0, 1,                     //   110:    switch Inst[0] {
  0, 27,                                     //   113:    case 0x0: {
  OPC_SwitchField, 9, 2,                     //   115:     switch Inst[10:9] {
  0, 4,                                      //   118:     case 0x0: {
  OPC_Decode, 165, 17, 3,                    //   120:      decode to VADDUHM using decoder 3
                                             //   120:     }
  1, 4,                                      //   124:     case 0x1: {
  OPC_Decode, 166, 17, 3,                    //   126:      decode to VADDUHS using decoder 3
                                             //   126:     }
  2, 4,                                      //   130:     case 0x2: {
  OPC_Decode, 133, 20, 3,                    //   132:      decode to VSUBUHM using decoder 3
                                             //   132:     }
  3, 0,                                      //   136:     case 0x3: {
  OPC_Decode, 134, 20, 3,                    //   138:      decode to VSUBUHS using decoder 3
                                             //   138:     }
                                             //   138:     } // switch Inst[10:9]
                                             //   138:    }
  1, 0,                                      //   142:    case 0x1: {
  OPC_SwitchField, 10, 1,                    //   144:     switch Inst[10] {
  0, 15,                                     //   147:     case 0x0: {
  OPC_SwitchField, 9, 1,                     //   149:      switch Inst[9] {
  0, 4,                                      //   152:      case 0x0: {
  OPC_Decode, 254, 18, 3,                    //   154:       decode to VMUL10ECUQ using decoder 3
                                             //   154:      }
  1, 0,                                      //   158:      case 0x1: {
  OPC_Decode, 255, 18, 3,                    //   160:       decode to VMUL10EUQ using decoder 3
                                             //   160:      }
                                             //   160:      } // switch Inst[9]
                                             //   160:     }
  1, 0,                                      //   164:     case 0x1: {
  OPC_Decode, 201, 4, 5,                     //   166:      decode to BCDSUB_rec using decoder 5
                                             //   166:     }
                                             //   166:     } // switch Inst[10]
                                             //   166:    }
                                             //   166:    } // switch Inst[0]
                                             //   166:   }
  2, 50,                                     //   170:   case 0x2: {
  OPC_SwitchField, 9, 2,                     //   172:    switch Inst[10:9] {
  0, 8,                                      //   175:    case 0x0: {
  OPC_CheckField, 0, 1, 0,                   //   177:     check Inst[0] == 0x0
  OPC_Decode, 168, 17, 3,                    //   181:     decode to VADDUWM using decoder 3
                                             //   181:    }
  1, 8,                                      //   185:    case 0x1: {
  OPC_CheckField, 0, 1, 0,                   //   187:     check Inst[0] == 0x0
  OPC_Decode, 169, 17, 3,                    //   191:     decode to VADDUWS using decoder 3
                                             //   191:    }
  2, 15,                                     //   195:    case 0x2: {
  OPC_SwitchField, 0, 1,                     //   197:     switch Inst[0] {
  0, 4,                                      //   200:     case 0x0: {
  OPC_Decode, 136, 20, 3,                    //   202:      decode to VSUBUWM using decoder 3
                                             //   202:     }
  1, 0,                                      //   206:     case 0x1: {
  OPC_Decode, 204, 4, 3,                     //   208:      decode to BCDUS_rec using decoder 3
                                             //   208:     }
                                             //   208:     } // switch Inst[0]
                                             //   208:    }
  3, 0,                                      //   212:    case 0x3: {
  OPC_CheckField, 0, 1, 0,                   //   214:     check Inst[0] == 0x0
  OPC_Decode, 137, 20, 3,                    //   218:     decode to VSUBUWS using decoder 3
                                             //   218:    }
                                             //   218:    } // switch Inst[10:9]
                                             //   218:   }
  3, 30,                                     //   222:   case 0x3: {
  OPC_SwitchField, 0, 1,                     //   224:    switch Inst[0] {
  0, 15,                                     //   227:    case 0x0: {
  OPC_SwitchField, 9, 2,                     //   229:     switch Inst[10:9] {
  0, 4,                                      //   232:     case 0x0: {
  OPC_Decode, 164, 17, 3,                    //   234:      decode to VADDUDM using decoder 3
                                             //   234:     }
  2, 0,                                      //   238:     case 0x2: {
  OPC_Decode, 132, 20, 3,                    //   240:      decode to VSUBUDM using decoder 3
                                             //   240:     }
                                             //   240:     } // switch Inst[10:9]
                                             //   240:    }
  1, 0,                                      //   244:    case 0x1: {
  OPC_CheckField, 10, 1, 1,                  //   246:     check Inst[10] == 0x1
  OPC_Decode, 202, 4, 5,                     //   250:     decode to BCDS_rec using decoder 5
                                             //   250:    }
                                             //   250:    } // switch Inst[0]
                                             //   250:   }
  4, 57,                                     //   254:   case 0x4: {
  OPC_SwitchField, 0, 1,                     //   256:    switch Inst[0] {
  0, 27,                                     //   259:    case 0x0: {
  OPC_SwitchField, 9, 2,                     //   261:     switch Inst[10:9] {
  0, 4,                                      //   264:     case 0x0: {
  OPC_Decode, 167, 17, 3,                    //   266:      decode to VADDUQM using decoder 3
                                             //   266:     }
  1, 4,                                      //   270:     case 0x1: {
  OPC_Decode, 159, 17, 3,                    //   272:      decode to VADDSBS using decoder 3
                                             //   272:     }
  2, 4,                                      //   276:     case 0x2: {
  OPC_Decode, 135, 20, 3,                    //   278:      decode to VSUBUQM using decoder 3
                                             //   278:     }
  3, 0,                                      //   282:     case 0x3: {
  OPC_Decode, 255, 19, 3,                    //   284:      decode to VSUBSBS using decoder 3
                                             //   284:     }
                                             //   284:     } // switch Inst[10:9]
                                             //   284:    }
  1, 0,                                      //   288:    case 0x1: {
  OPC_SwitchField, 10, 1,                    //   290:     switch Inst[10] {
  0, 12,                                     //   293:     case 0x0: {
  OPC_CheckField, 21, 2, 0,                  //   295:      check Inst[22:21] == 0x0
  OPC_CheckField, 9, 1, 0,                   //   299:      check Inst[9] == 0x0
  OPC_Decode, 246, 17, 6,                    //   303:      decode to VCMPUQ using decoder 6
                                             //   303:     }
  1, 0,                                      //   307:     case 0x1: {
  OPC_Decode, 203, 4, 5,                     //   309:      decode to BCDTRUNC_rec using decoder 5
                                             //   309:     }
                                             //   309:     } // switch Inst[10]
                                             //   309:    }
                                             //   309:    } // switch Inst[0]
                                             //   309:   }
  5, 68,                                     //   313:   case 0x5: {
  OPC_SwitchField, 9, 2,                     //   315:    switch Inst[10:9] {
  0, 19,                                     //   318:    case 0x0: {
  OPC_SwitchField, 0, 1,                     //   320:     switch Inst[0] {
  0, 4,                                      //   323:     case 0x0: {
  OPC_Decode, 154, 17, 3,                    //   325:      decode to VADDCUQ using decoder 3
                                             //   325:     }
  1, 0,                                      //   329:     case 0x1: {
  OPC_CheckField, 21, 2, 0,                  //   331:      check Inst[22:21] == 0x0
  OPC_Decode, 245, 17, 6,                    //   335:      decode to VCMPSQ using decoder 6
                                             //   335:     }
                                             //   335:     } // switch Inst[0]
                                             //   335:    }
  1, 15,                                     //   339:    case 0x1: {
  OPC_SwitchField, 0, 1,                     //   341:     switch Inst[0] {
  0, 4,                                      //   344:     case 0x0: {
  OPC_Decode, 160, 17, 3,                    //   346:      decode to VADDSHS using decoder 3
                                             //   346:     }
  1, 0,                                      //   350:     case 0x1: {
  OPC_Decode, 195, 4, 3,                     //   352:      decode to BCDCPSGN_rec using decoder 3
                                             //   352:     }
                                             //   352:     } // switch Inst[0]
                                             //   352:    }
  2, 15,                                     //   356:    case 0x2: {
  OPC_SwitchField, 0, 1,                     //   358:     switch Inst[0] {
  0, 4,                                      //   361:     case 0x0: {
  OPC_Decode, 250, 19, 3,                    //   363:      decode to VSUBCUQ using decoder 3
                                             //   363:     }
  1, 0,                                      //   367:     case 0x1: {
  OPC_Decode, 205, 4, 3,                     //   369:      decode to BCDUTRUNC_rec using decoder 3
                                             //   369:     }
                                             //   369:     } // switch Inst[0]
                                             //   369:    }
  3, 0,                                      //   373:    case 0x3: {
  OPC_CheckField, 0, 1, 0,                   //   375:     check Inst[0] == 0x0
  OPC_Decode, 128, 20, 3,                    //   379:     decode to VSUBSHS using decoder 3
                                             //   379:    }
                                             //   379:    } // switch Inst[10:9]
                                             //   379:   }
  6, 107,                                    //   383:   case 0x6: {
  OPC_SwitchField, 0, 1,                     //   385:    switch Inst[0] {
  0, 27,                                     //   388:    case 0x0: {
  OPC_SwitchField, 9, 2,                     //   390:     switch Inst[10:9] {
  0, 4,                                      //   393:     case 0x0: {
  OPC_Decode, 155, 17, 3,                    //   395:      decode to VADDCUW using decoder 3
                                             //   395:     }
  1, 4,                                      //   399:     case 0x1: {
  OPC_Decode, 161, 17, 3,                    //   401:      decode to VADDSWS using decoder 3
                                             //   401:     }
  2, 4,                                      //   405:     case 0x2: {
  OPC_Decode, 251, 19, 3,                    //   407:      decode to VSUBCUW using decoder 3
                                             //   407:     }
  3, 0,                                      //   411:     case 0x3: {
  OPC_Decode, 129, 20, 3,                    //   413:      decode to VSUBSWS using decoder 3
                                             //   413:     }
                                             //   413:     } // switch Inst[10:9]
                                             //   413:    }
  1, 0,                                      //   417:    case 0x1: {
  OPC_SwitchField, 16, 5,                    //   419:     switch Inst[20:16] {
  0, 8,                                      //   422:     case 0x0: {
  OPC_CheckField, 9, 2, 2,                   //   424:      check Inst[10:9] == 0x2
  OPC_Decode, 197, 4, 7,                     //   428:      decode to BCDCTSQ_rec using decoder 7
                                             //   428:     }
  2, 8,                                      //   432:     case 0x2: {
  OPC_CheckField, 10, 1, 1,                  //   434:      check Inst[10] == 0x1
  OPC_Decode, 193, 4, 8,                     //   438:      decode to BCDCFSQ_rec using decoder 8
                                             //   438:     }
  4, 8,                                      //   442:     case 0x4: {
  OPC_CheckField, 10, 1, 1,                  //   444:      check Inst[10] == 0x1
  OPC_Decode, 198, 4, 8,                     //   448:      decode to BCDCTZ_rec using decoder 8
                                             //   448:     }
  5, 8,                                      //   452:     case 0x5: {
  OPC_CheckField, 9, 2, 2,                   //   454:      check Inst[10:9] == 0x2
  OPC_Decode, 196, 4, 7,                     //   458:      decode to BCDCTN_rec using decoder 7
                                             //   458:     }
  6, 8,                                      //   462:     case 0x6: {
  OPC_CheckField, 10, 1, 1,                  //   464:      check Inst[10] == 0x1
  OPC_Decode, 194, 4, 8,                     //   468:      decode to BCDCFZ_rec using decoder 8
                                             //   468:     }
  7, 8,                                      //   472:     case 0x7: {
  OPC_CheckField, 10, 1, 1,                  //   474:      check Inst[10] == 0x1
  OPC_Decode, 192, 4, 8,                     //   478:      decode to BCDCFN_rec using decoder 8
                                             //   478:     }
  31, 0,                                     //   482:     case 0x1f: {
  OPC_CheckField, 10, 1, 1,                  //   484:      check Inst[10] == 0x1
  OPC_Decode, 199, 4, 8,                     //   488:      decode to BCDSETSGN_rec using decoder 8
                                             //   488:     }
                                             //   488:     } // switch Inst[20:16]
                                             //   488:    }
                                             //   488:    } // switch Inst[0]
                                             //   488:   }
  7, 0,                                      //   492:   case 0x7: {
  OPC_CheckField, 10, 1, 1,                  //   494:    check Inst[10] == 0x1
  OPC_CheckField, 0, 1, 1,                   //   498:    check Inst[0] == 0x1
  OPC_Decode, 200, 4, 5,                     //   502:    decode to BCDSR_rec using decoder 5
                                             //   502:   }
                                             //   502:   } // switch Inst[8:6]
                                             //   502:  }
  1, 237, 6,                                 //   506:  case 0x1: {
  OPC_SwitchField, 6, 5,                     //   509:   switch Inst[10:6] {
  0, 15,                                     //   512:   case 0x0: {
  OPC_SwitchField, 0, 1,                     //   514:    switch Inst[0] {
  0, 4,                                      //   517:    case 0x0: {
  OPC_Decode, 215, 18, 3,                    //   519:     decode to VMAXUB using decoder 3
                                             //   519:    }
  1, 0,                                      //   523:    case 0x1: {
  OPC_Decode, 145, 20, 3,                    //   525:     decode to VUCMPRHN using decoder 3
                                             //   525:    }
                                             //   525:    } // switch Inst[0]
                                             //   525:   }
  1, 15,                                     //   529:   case 0x1: {
  OPC_SwitchField, 0, 1,                     //   531:    switch Inst[0] {
  0, 4,                                      //   534:    case 0x0: {
  OPC_Decode, 217, 18, 3,                    //   536:     decode to VMAXUH using decoder 3
                                             //   536:    }
  1, 0,                                      //   540:    case 0x1: {
  OPC_Decode, 148, 20, 3,                    //   542:     decode to VUCMPRLN using decoder 3
                                             //   542:    }
                                             //   542:    } // switch Inst[0]
                                             //   542:   }
  2, 15,                                     //   546:   case 0x2: {
  OPC_SwitchField, 0, 1,                     //   548:    switch Inst[0] {
  0, 4,                                      //   551:    case 0x0: {
  OPC_Decode, 218, 18, 3,                    //   553:     decode to VMAXUW using decoder 3
                                             //   553:    }
  1, 0,                                      //   557:    case 0x1: {
  OPC_Decode, 143, 20, 3,                    //   559:     decode to VUCMPRHB using decoder 3
                                             //   559:    }
                                             //   559:    } // switch Inst[0]
                                             //   559:   }
  3, 15,                                     //   563:   case 0x3: {
  OPC_SwitchField, 0, 1,                     //   565:    switch Inst[0] {
  0, 4,                                      //   568:    case 0x0: {
  OPC_Decode, 216, 18, 3,                    //   570:     decode to VMAXUD using decoder 3
                                             //   570:    }
  1, 0,                                      //   574:    case 0x1: {
  OPC_Decode, 146, 20, 3,                    //   576:     decode to VUCMPRLB using decoder 3
                                             //   576:    }
                                             //   576:    } // switch Inst[0]
                                             //   576:   }
  4, 15,                                     //   580:   case 0x4: {
  OPC_SwitchField, 0, 1,                     //   582:    switch Inst[0] {
  0, 4,                                      //   585:    case 0x0: {
  OPC_Decode, 211, 18, 3,                    //   587:     decode to VMAXSB using decoder 3
                                             //   587:    }
  1, 0,                                      //   591:    case 0x1: {
  OPC_Decode, 144, 20, 3,                    //   593:     decode to VUCMPRHH using decoder 3
                                             //   593:    }
                                             //   593:    } // switch Inst[0]
                                             //   593:   }
  5, 15,                                     //   597:   case 0x5: {
  OPC_SwitchField, 0, 1,                     //   599:    switch Inst[0] {
  0, 4,                                      //   602:    case 0x0: {
  OPC_Decode, 213, 18, 3,                    //   604:     decode to VMAXSH using decoder 3
                                             //   604:    }
  1, 0,                                      //   608:    case 0x1: {
  OPC_Decode, 147, 20, 3,                    //   610:     decode to VUCMPRLH using decoder 3
                                             //   610:    }
                                             //   610:    } // switch Inst[0]
                                             //   610:   }
  6, 65,                                     //   614:   case 0x6: {
  OPC_SwitchField, 0, 1,                     //   616:    switch Inst[0] {
  0, 4,                                      //   619:    case 0x0: {
  OPC_Decode, 214, 18, 3,                    //   621:     decode to VMAXSW using decoder 3
                                             //   621:    }
  1, 0,                                      //   625:    case 0x1: {
  OPC_SwitchField, 19, 2,                    //   627:     switch Inst[20:19] {
  0, 26,                                     //   630:     case 0x0: {
  OPC_SwitchField, 17, 2,                    //   632:      switch Inst[18:17] {
  0, 15,                                     //   635:      case 0x0: {
  OPC_SwitchField, 16, 1,                    //   637:       switch Inst[16] {
  0, 4,                                      //   640:       case 0x0: {
  OPC_Decode, 152, 20, 7,                    //   642:        decode to VUPKHSNTOB using decoder 7
                                             //   642:       }
  1, 0,                                      //   646:       case 0x1: {
  OPC_Decode, 161, 20, 7,                    //   648:        decode to VUPKLSNTOB using decoder 7
                                             //   648:       }
                                             //   648:       } // switch Inst[16]
                                             //   648:      }
  1, 0,                                      //   652:      case 0x1: {
  OPC_Decode, 156, 20, 9,                    //   654:       decode to VUPKINT8TOBF16 using decoder 9
                                             //   654:      }
                                             //   654:      } // switch Inst[18:17]
                                             //   654:     }
  1, 15,                                     //   658:     case 0x1: {
  OPC_SwitchField, 18, 1,                    //   660:      switch Inst[18] {
  0, 4,                                      //   663:      case 0x0: {
  OPC_Decode, 154, 20, 10,                   //   665:       decode to VUPKINT4TOBF16 using decoder 10
                                             //   665:      }
  1, 0,                                      //   669:      case 0x1: {
  OPC_Decode, 157, 20, 10,                   //   671:       decode to VUPKINT8TOFP32 using decoder 10
                                             //   671:      }
                                             //   671:      } // switch Inst[18]
                                             //   671:     }
  2, 0,                                      //   675:     case 0x2: {
  OPC_Decode, 155, 20, 11,                   //   677:      decode to VUPKINT4TOFP32 using decoder 11
                                             //   677:     }
                                             //   677:     } // switch Inst[20:19]
                                             //   677:    }
                                             //   677:    } // switch Inst[0]
                                             //   677:   }
  7, 8,                                      //   681:   case 0x7: {
  OPC_CheckField, 0, 1, 0,                   //   683:    check Inst[0] == 0x0
  OPC_Decode, 212, 18, 3,                    //   687:    decode to VMAXSD using decoder 3
                                             //   687:   }
  8, 8,                                      //   691:   case 0x8: {
  OPC_CheckField, 0, 1, 0,                   //   693:    check Inst[0] == 0x0
  OPC_Decode, 226, 18, 3,                    //   697:    decode to VMINUB using decoder 3
                                             //   697:   }
  9, 8,                                      //   701:   case 0x9: {
  OPC_CheckField, 0, 1, 0,                   //   703:    check Inst[0] == 0x0
  OPC_Decode, 228, 18, 3,                    //   707:    decode to VMINUH using decoder 3
                                             //   707:   }
  10, 8,                                     //   711:   case 0xa: {
  OPC_CheckField, 0, 1, 0,                   //   713:    check Inst[0] == 0x0
  OPC_Decode, 229, 18, 3,                    //   717:    decode to VMINUW using decoder 3
                                             //   717:   }
  11, 8,                                     //   721:   case 0xb: {
  OPC_CheckField, 0, 1, 0,                   //   723:    check Inst[0] == 0x0
  OPC_Decode, 227, 18, 3,                    //   727:    decode to VMINUD using decoder 3
                                             //   727:   }
  12, 8,                                     //   731:   case 0xc: {
  OPC_CheckField, 0, 1, 0,                   //   733:    check Inst[0] == 0x0
  OPC_Decode, 222, 18, 3,                    //   737:    decode to VMINSB using decoder 3
                                             //   737:   }
  13, 8,                                     //   741:   case 0xd: {
  OPC_CheckField, 0, 1, 0,                   //   743:    check Inst[0] == 0x0
  OPC_Decode, 224, 18, 3,                    //   747:    decode to VMINSH using decoder 3
                                             //   747:   }
  14, 8,                                     //   751:   case 0xe: {
  OPC_CheckField, 0, 1, 0,                   //   753:    check Inst[0] == 0x0
  OPC_Decode, 225, 18, 3,                    //   757:    decode to VMINSW using decoder 3
                                             //   757:   }
  15, 8,                                     //   761:   case 0xf: {
  OPC_CheckField, 0, 1, 0,                   //   763:    check Inst[0] == 0x0
  OPC_Decode, 223, 18, 3,                    //   767:    decode to VMINSD using decoder 3
                                             //   767:   }
  16, 15,                                    //   771:   case 0x10: {
  OPC_SwitchField, 0, 1,                     //   773:    switch Inst[0] {
  0, 4,                                      //   776:    case 0x0: {
  OPC_Decode, 175, 17, 3,                    //   778:     decode to VAVGUB using decoder 3
                                             //   778:    }
  1, 0,                                      //   782:    case 0x1: {
  OPC_Decode, 151, 17, 3,                    //   784:     decode to VABSDUB using decoder 3
                                             //   784:    }
                                             //   784:    } // switch Inst[0]
                                             //   784:   }
  17, 15,                                    //   788:   case 0x11: {
  OPC_SwitchField, 0, 1,                     //   790:    switch Inst[0] {
  0, 4,                                      //   793:    case 0x0: {
  OPC_Decode, 176, 17, 3,                    //   795:     decode to VAVGUH using decoder 3
                                             //   795:    }
  1, 0,                                      //   799:    case 0x1: {
  OPC_Decode, 152, 17, 3,                    //   801:     decode to VABSDUH using decoder 3
                                             //   801:    }
                                             //   801:    } // switch Inst[0]
                                             //   801:   }
  18, 15,                                    //   805:   case 0x12: {
  OPC_SwitchField, 0, 1,                     //   807:    switch Inst[0] {
  0, 4,                                      //   810:    case 0x0: {
  OPC_Decode, 177, 17, 3,                    //   812:     decode to VAVGUW using decoder 3
                                             //   812:    }
  1, 0,                                      //   816:    case 0x1: {
  OPC_Decode, 153, 17, 3,                    //   818:     decode to VABSDUW using decoder 3
                                             //   818:    }
                                             //   818:    } // switch Inst[0]
                                             //   818:   }
  20, 8,                                     //   822:   case 0x14: {
  OPC_CheckField, 0, 1, 0,                   //   824:    check Inst[0] == 0x0
  OPC_Decode, 172, 17, 3,                    //   828:    decode to VAVGSB using decoder 3
                                             //   828:   }
  21, 8,                                     //   832:   case 0x15: {
  OPC_CheckField, 0, 1, 0,                   //   834:    check Inst[0] == 0x0
  OPC_Decode, 173, 17, 3,                    //   838:    decode to VAVGSH using decoder 3
                                             //   838:   }
  22, 8,                                     //   842:   case 0x16: {
  OPC_CheckField, 0, 1, 0,                   //   844:    check Inst[0] == 0x0
  OPC_Decode, 174, 17, 3,                    //   848:    decode to VAVGSW using decoder 3
                                             //   848:   }
  24, 173, 1,                                //   852:   case 0x18: {
  OPC_SwitchField, 16, 5,                    //   855:    switch Inst[20:16] {
  0, 8,                                      //   858:    case 0x0: {
  OPC_CheckField, 0, 1, 0,                   //   860:     check Inst[0] == 0x0
  OPC_Decode, 193, 17, 12,                   //   864:     decode to VCLZLSBB using decoder 12
                                             //   864:    }
  1, 8,                                      //   868:    case 0x1: {
  OPC_CheckField, 0, 1, 0,                   //   870:     check Inst[0] == 0x0
  OPC_Decode, 131, 18, 12,                   //   874:     decode to VCTZLSBB using decoder 12
                                             //   874:    }
  6, 8,                                      //   878:    case 0x6: {
  OPC_CheckField, 0, 1, 0,                   //   880:     check Inst[0] == 0x0
  OPC_Decode, 155, 19, 7,                    //   884:     decode to VNEGW using decoder 7
                                             //   884:    }
  7, 8,                                      //   888:    case 0x7: {
  OPC_CheckField, 0, 1, 0,                   //   890:     check Inst[0] == 0x0
  OPC_Decode, 154, 19, 7,                    //   894:     decode to VNEGD using decoder 7
                                             //   894:    }
  8, 8,                                      //   898:    case 0x8: {
  OPC_CheckField, 0, 1, 0,                   //   900:     check Inst[0] == 0x0
  OPC_Decode, 188, 19, 7,                    //   904:     decode to VPRTYBW using decoder 7
                                             //   904:    }
  9, 8,                                      //   908:    case 0x9: {
  OPC_CheckField, 0, 1, 0,                   //   910:     check Inst[0] == 0x0
  OPC_Decode, 186, 19, 7,                    //   914:     decode to VPRTYBD using decoder 7
                                             //   914:    }
  10, 8,                                     //   918:    case 0xa: {
  OPC_CheckField, 0, 1, 0,                   //   920:     check Inst[0] == 0x0
  OPC_Decode, 187, 19, 7,                    //   924:     decode to VPRTYBQ using decoder 7
                                             //   924:    }
  16, 8,                                     //   928:    case 0x10: {
  OPC_CheckField, 0, 1, 0,                   //   930:     check Inst[0] == 0x0
  OPC_Decode, 171, 18, 7,                    //   934:     decode to VEXTSB2W using decoder 7
                                             //   934:    }
  17, 8,                                     //   938:    case 0x11: {
  OPC_CheckField, 0, 1, 0,                   //   940:     check Inst[0] == 0x0
  OPC_Decode, 176, 18, 7,                    //   944:     decode to VEXTSH2W using decoder 7
                                             //   944:    }
  24, 8,                                     //   948:    case 0x18: {
  OPC_CheckField, 0, 1, 0,                   //   950:     check Inst[0] == 0x0
  OPC_Decode, 169, 18, 7,                    //   954:     decode to VEXTSB2D using decoder 7
                                             //   954:    }
  25, 8,                                     //   958:    case 0x19: {
  OPC_CheckField, 0, 1, 0,                   //   960:     check Inst[0] == 0x0
  OPC_Decode, 174, 18, 7,                    //   964:     decode to VEXTSH2D using decoder 7
                                             //   964:    }
  26, 8,                                     //   968:    case 0x1a: {
  OPC_CheckField, 0, 1, 0,                   //   970:     check Inst[0] == 0x0
  OPC_Decode, 178, 18, 7,                    //   974:     decode to VEXTSW2D using decoder 7
                                             //   974:    }
  27, 8,                                     //   978:    case 0x1b: {
  OPC_CheckField, 0, 1, 0,                   //   980:     check Inst[0] == 0x0
  OPC_Decode, 173, 18, 7,                    //   984:     decode to VEXTSD2Q using decoder 7
                                             //   984:    }
  28, 8,                                     //   988:    case 0x1c: {
  OPC_CheckField, 0, 1, 0,                   //   990:     check Inst[0] == 0x0
  OPC_Decode, 255, 17, 7,                    //   994:     decode to VCTZB using decoder 7
                                             //   994:    }
  29, 8,                                     //   998:    case 0x1d: {
  OPC_CheckField, 0, 1, 0,                   //  1000:     check Inst[0] == 0x0
  OPC_Decode, 130, 18, 7,                    //  1004:     decode to VCTZH using decoder 7
                                             //  1004:    }
  30, 8,                                     //  1008:    case 0x1e: {
  OPC_CheckField, 0, 1, 0,                   //  1010:     check Inst[0] == 0x0
  OPC_Decode, 132, 18, 7,                    //  1014:     decode to VCTZW using decoder 7
                                             //  1014:    }
  31, 0,                                     //  1018:    case 0x1f: {
  OPC_CheckField, 0, 1, 0,                   //  1020:     check Inst[0] == 0x0
  OPC_Decode, 128, 18, 7,                    //  1024:     decode to VCTZD using decoder 7
                                             //  1024:    }
                                             //  1024:    } // switch Inst[20:16]
                                             //  1024:   }
  25, 235, 1,                                //  1028:   case 0x19: {
  OPC_SwitchField, 17, 4,                    //  1031:    switch Inst[20:17] {
  0, 23,                                     //  1034:    case 0x0: {
  OPC_SwitchField, 16, 1,                    //  1036:     switch Inst[16] {
  0, 8,                                      //  1039:     case 0x0: {
  OPC_CheckField, 0, 1, 0,                   //  1041:      check Inst[0] == 0x0
  OPC_Decode, 146, 18, 7,                    //  1045:      decode to VEXPANDBM using decoder 7
                                             //  1045:     }
  1, 0,                                      //  1049:     case 0x1: {
  OPC_CheckField, 0, 1, 0,                   //  1051:      check Inst[0] == 0x0
  OPC_Decode, 148, 18, 7,                    //  1055:      decode to VEXPANDHM using decoder 7
                                             //  1055:     }
                                             //  1055:     } // switch Inst[16]
                                             //  1055:    }
  1, 23,                                     //  1059:    case 0x1: {
  OPC_SwitchField, 16, 1,                    //  1061:     switch Inst[16] {
  0, 8,                                      //  1064:     case 0x0: {
  OPC_CheckField, 0, 1, 0,                   //  1066:      check Inst[0] == 0x0
  OPC_Decode, 150, 18, 7,                    //  1070:      decode to VEXPANDWM using decoder 7
                                             //  1070:     }
  1, 0,                                      //  1074:     case 0x1: {
  OPC_CheckField, 0, 1, 0,                   //  1076:      check Inst[0] == 0x0
  OPC_Decode, 147, 18, 7,                    //  1080:      decode to VEXPANDDM using decoder 7
                                             //  1080:     }
                                             //  1080:     } // switch Inst[16]
                                             //  1080:    }
  2, 12,                                     //  1084:    case 0x2: {
  OPC_CheckField, 16, 1, 0,                  //  1086:     check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  1090:     check Inst[0] == 0x0
  OPC_Decode, 149, 18, 7,                    //  1094:     decode to VEXPANDQM using decoder 7
                                             //  1094:    }
  4, 23,                                     //  1098:    case 0x4: {
  OPC_SwitchField, 16, 1,                    //  1100:     switch Inst[16] {
  0, 8,                                      //  1103:     case 0x0: {
  OPC_CheckField, 0, 1, 0,                   //  1105:      check Inst[0] == 0x0
  OPC_Decode, 160, 18, 12,                   //  1109:      decode to VEXTRACTBM using decoder 12
                                             //  1109:     }
  1, 0,                                      //  1113:     case 0x1: {
  OPC_CheckField, 0, 1, 0,                   //  1115:      check Inst[0] == 0x0
  OPC_Decode, 163, 18, 12,                   //  1119:      decode to VEXTRACTHM using decoder 12
                                             //  1119:     }
                                             //  1119:     } // switch Inst[16]
                                             //  1119:    }
  5, 23,                                     //  1123:    case 0x5: {
  OPC_SwitchField, 16, 1,                    //  1125:     switch Inst[16] {
  0, 8,                                      //  1128:     case 0x0: {
  OPC_CheckField, 0, 1, 0,                   //  1130:      check Inst[0] == 0x0
  OPC_Decode, 168, 18, 12,                   //  1134:      decode to VEXTRACTWM using decoder 12
                                             //  1134:     }
  1, 0,                                      //  1138:     case 0x1: {
  OPC_CheckField, 0, 1, 0,                   //  1140:      check Inst[0] == 0x0
  OPC_Decode, 162, 18, 12,                   //  1144:      decode to VEXTRACTDM using decoder 12
                                             //  1144:     }
                                             //  1144:     } // switch Inst[16]
                                             //  1144:    }
  6, 12,                                     //  1148:    case 0x6: {
  OPC_CheckField, 16, 1, 0,                  //  1150:     check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  1154:     check Inst[0] == 0x0
  OPC_Decode, 164, 18, 12,                   //  1158:     decode to VEXTRACTQM using decoder 12
                                             //  1158:    }
  8, 23,                                     //  1162:    case 0x8: {
  OPC_SwitchField, 16, 1,                    //  1164:     switch Inst[16] {
  0, 8,                                      //  1167:     case 0x0: {
  OPC_CheckField, 0, 1, 0,                   //  1169:      check Inst[0] == 0x0
  OPC_Decode, 166, 12, 13,                   //  1173:      decode to MTVSRBM using decoder 13
                                             //  1173:     }
  1, 0,                                      //  1177:     case 0x1: {
  OPC_CheckField, 0, 1, 0,                   //  1179:      check Inst[0] == 0x0
  OPC_Decode, 171, 12, 13,                   //  1183:      decode to MTVSRHM using decoder 13
                                             //  1183:     }
                                             //  1183:     } // switch Inst[16]
                                             //  1183:    }
  9, 23,                                     //  1187:    case 0x9: {
  OPC_SwitchField, 16, 1,                    //  1189:     switch Inst[16] {
  0, 8,                                      //  1192:     case 0x0: {
  OPC_CheckField, 0, 1, 0,                   //  1194:      check Inst[0] == 0x0
  OPC_Decode, 174, 12, 13,                   //  1198:      decode to MTVSRWM using decoder 13
                                             //  1198:     }
  1, 0,                                      //  1202:     case 0x1: {
  OPC_CheckField, 0, 1, 0,                   //  1204:      check Inst[0] == 0x0
  OPC_Decode, 170, 12, 13,                   //  1208:      decode to MTVSRDM using decoder 13
                                             //  1208:     }
                                             //  1208:     } // switch Inst[16]
                                             //  1208:    }
  10, 12,                                    //  1212:    case 0xa: {
  OPC_CheckField, 16, 1, 0,                  //  1214:     check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  1218:     check Inst[0] == 0x0
  OPC_Decode, 172, 12, 13,                   //  1222:     decode to MTVSRQM using decoder 13
                                             //  1222:    }
  12, 8,                                     //  1226:    case 0xc: {
  OPC_CheckField, 0, 1, 0,                   //  1228:     check Inst[0] == 0x0
  OPC_Decode, 247, 17, 14,                   //  1232:     decode to VCNTMBB using decoder 14
                                             //  1232:    }
  13, 8,                                     //  1236:    case 0xd: {
  OPC_CheckField, 0, 1, 0,                   //  1238:     check Inst[0] == 0x0
  OPC_Decode, 249, 17, 14,                   //  1242:     decode to VCNTMBH using decoder 14
                                             //  1242:    }
  14, 8,                                     //  1246:    case 0xe: {
  OPC_CheckField, 0, 1, 0,                   //  1248:     check Inst[0] == 0x0
  OPC_Decode, 250, 17, 14,                   //  1252:     decode to VCNTMBW using decoder 14
                                             //  1252:    }
  15, 0,                                     //  1256:    case 0xf: {
  OPC_CheckField, 0, 1, 0,                   //  1258:     check Inst[0] == 0x0
  OPC_Decode, 248, 17, 14,                   //  1262:     decode to VCNTMBD using decoder 14
                                             //  1262:    }
                                             //  1262:    } // switch Inst[20:17]
                                             //  1262:   }
  26, 8,                                     //  1266:   case 0x1a: {
  OPC_CheckField, 0, 1, 0,                   //  1268:    check Inst[0] == 0x0
  OPC_Decode, 209, 19, 15,                   //  1272:    decode to VSHASIGMAW using decoder 15
                                             //  1272:   }
  27, 8,                                     //  1276:   case 0x1b: {
  OPC_CheckField, 0, 1, 0,                   //  1278:    check Inst[0] == 0x0
  OPC_Decode, 208, 19, 15,                   //  1282:    decode to VSHASIGMAD using decoder 15
                                             //  1282:   }
  28, 23,                                    //  1286:   case 0x1c: {
  OPC_SwitchField, 0, 1,                     //  1288:    switch Inst[0] {
  0, 8,                                      //  1291:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  //  1293:     check Inst[20:16] == 0x0
  OPC_Decode, 189, 17, 7,                    //  1297:     decode to VCLZB using decoder 7
                                             //  1297:    }
  1, 0,                                      //  1301:    case 0x1: {
  OPC_CheckField, 16, 5, 0,                  //  1303:     check Inst[20:16] == 0x0
  OPC_Decode, 182, 19, 7,                    //  1307:     decode to VPOPCNTB using decoder 7
                                             //  1307:    }
                                             //  1307:    } // switch Inst[0]
                                             //  1307:   }
  29, 23,                                    //  1311:   case 0x1d: {
  OPC_SwitchField, 0, 1,                     //  1313:    switch Inst[0] {
  0, 8,                                      //  1316:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  //  1318:     check Inst[20:16] == 0x0
  OPC_Decode, 192, 17, 7,                    //  1322:     decode to VCLZH using decoder 7
                                             //  1322:    }
  1, 0,                                      //  1326:    case 0x1: {
  OPC_CheckField, 16, 5, 0,                  //  1328:     check Inst[20:16] == 0x0
  OPC_Decode, 184, 19, 7,                    //  1332:     decode to VPOPCNTH using decoder 7
                                             //  1332:    }
                                             //  1332:    } // switch Inst[0]
                                             //  1332:   }
  30, 23,                                    //  1336:   case 0x1e: {
  OPC_SwitchField, 0, 1,                     //  1338:    switch Inst[0] {
  0, 8,                                      //  1341:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  //  1343:     check Inst[20:16] == 0x0
  OPC_Decode, 194, 17, 7,                    //  1347:     decode to VCLZW using decoder 7
                                             //  1347:    }
  1, 0,                                      //  1351:    case 0x1: {
  OPC_CheckField, 16, 5, 0,                  //  1353:     check Inst[20:16] == 0x0
  OPC_Decode, 185, 19, 7,                    //  1357:     decode to VPOPCNTW using decoder 7
                                             //  1357:    }
                                             //  1357:    } // switch Inst[0]
                                             //  1357:   }
  31, 0,                                     //  1361:   case 0x1f: {
  OPC_SwitchField, 0, 1,                     //  1363:    switch Inst[0] {
  0, 8,                                      //  1366:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  //  1368:     check Inst[20:16] == 0x0
  OPC_Decode, 190, 17, 7,                    //  1372:     decode to VCLZD using decoder 7
                                             //  1372:    }
  1, 0,                                      //  1376:    case 0x1: {
  OPC_CheckField, 16, 5, 0,                  //  1378:     check Inst[20:16] == 0x0
  OPC_Decode, 183, 19, 7,                    //  1382:     decode to VPOPCNTD using decoder 7
                                             //  1382:    }
                                             //  1382:    } // switch Inst[0]
                                             //  1382:   }
                                             //  1382:   } // switch Inst[10:6]
                                             //  1382:  }
  2, 145, 3,                                 //  1386:  case 0x2: {
  OPC_SwitchField, 6, 5,                     //  1389:   switch Inst[10:6] {
  0, 15,                                     //  1392:   case 0x0: {
  OPC_SwitchField, 0, 1,                     //  1394:    switch Inst[0] {
  0, 4,                                      //  1397:    case 0x0: {
  OPC_Decode, 194, 19, 3,                    //  1399:     decode to VRLB using decoder 3
                                             //  1399:    }
  1, 0,                                      //  1403:    case 0x1: {
  OPC_Decode, 199, 19, 3,                    //  1405:     decode to VRLQ using decoder 3
                                             //  1405:    }
                                             //  1405:    } // switch Inst[0]
                                             //  1405:   }
  1, 15,                                     //  1409:   case 0x1: {
  OPC_SwitchField, 0, 1,                     //  1411:    switch Inst[0] {
  0, 4,                                      //  1414:    case 0x0: {
  OPC_Decode, 198, 19, 3,                    //  1416:     decode to VRLH using decoder 3
                                             //  1416:    }
  1, 0,                                      //  1420:    case 0x1: {
  OPC_Decode, 200, 19, 16,                   //  1422:     decode to VRLQMI using decoder 16
                                             //  1422:    }
                                             //  1422:    } // switch Inst[0]
                                             //  1422:   }
  2, 15,                                     //  1426:   case 0x2: {
  OPC_SwitchField, 0, 1,                     //  1428:    switch Inst[0] {
  0, 4,                                      //  1431:    case 0x0: {
  OPC_Decode, 202, 19, 3,                    //  1433:     decode to VRLW using decoder 3
                                             //  1433:    }
  1, 0,                                      //  1437:    case 0x1: {
  OPC_Decode, 203, 19, 16,                   //  1439:     decode to VRLWMI using decoder 16
                                             //  1439:    }
                                             //  1439:    } // switch Inst[0]
                                             //  1439:   }
  3, 15,                                     //  1443:   case 0x3: {
  OPC_SwitchField, 0, 1,                     //  1445:    switch Inst[0] {
  0, 4,                                      //  1448:    case 0x0: {
  OPC_Decode, 195, 19, 3,                    //  1450:     decode to VRLD using decoder 3
                                             //  1450:    }
  1, 0,                                      //  1454:    case 0x1: {
  OPC_Decode, 196, 19, 16,                   //  1456:     decode to VRLDMI using decoder 16
                                             //  1456:    }
                                             //  1456:    } // switch Inst[0]
                                             //  1456:   }
  4, 15,                                     //  1460:   case 0x4: {
  OPC_SwitchField, 0, 1,                     //  1462:    switch Inst[0] {
  0, 4,                                      //  1465:    case 0x0: {
  OPC_Decode, 211, 19, 3,                    //  1467:     decode to VSLB using decoder 3
                                             //  1467:    }
  1, 0,                                      //  1471:    case 0x1: {
  OPC_Decode, 217, 19, 3,                    //  1473:     decode to VSLQ using decoder 3
                                             //  1473:    }
                                             //  1473:    } // switch Inst[0]
                                             //  1473:   }
  5, 15,                                     //  1477:   case 0x5: {
  OPC_SwitchField, 0, 1,                     //  1479:    switch Inst[0] {
  0, 4,                                      //  1482:    case 0x0: {
  OPC_Decode, 215, 19, 3,                    //  1484:     decode to VSLH using decoder 3
                                             //  1484:    }
  1, 0,                                      //  1488:    case 0x1: {
  OPC_Decode, 201, 19, 3,                    //  1490:     decode to VRLQNM using decoder 3
                                             //  1490:    }
                                             //  1490:    } // switch Inst[0]
                                             //  1490:   }
  6, 15,                                     //  1494:   case 0x6: {
  OPC_SwitchField, 0, 1,                     //  1496:    switch Inst[0] {
  0, 4,                                      //  1499:    case 0x0: {
  OPC_Decode, 219, 19, 3,                    //  1501:     decode to VSLW using decoder 3
                                             //  1501:    }
  1, 0,                                      //  1505:    case 0x1: {
  OPC_Decode, 204, 19, 3,                    //  1507:     decode to VRLWNM using decoder 3
                                             //  1507:    }
                                             //  1507:    } // switch Inst[0]
                                             //  1507:   }
  7, 15,                                     //  1511:   case 0x7: {
  OPC_SwitchField, 0, 1,                     //  1513:    switch Inst[0] {
  0, 4,                                      //  1516:    case 0x0: {
  OPC_Decode, 210, 19, 3,                    //  1518:     decode to VSL using decoder 3
                                             //  1518:    }
  1, 0,                                      //  1522:    case 0x1: {
  OPC_Decode, 197, 19, 3,                    //  1524:     decode to VRLDNM using decoder 3
                                             //  1524:    }
                                             //  1524:    } // switch Inst[0]
                                             //  1524:   }
  8, 15,                                     //  1528:   case 0x8: {
  OPC_SwitchField, 0, 1,                     //  1530:    switch Inst[0] {
  0, 4,                                      //  1533:    case 0x0: {
  OPC_Decode, 234, 19, 3,                    //  1535:     decode to VSRB using decoder 3
                                             //  1535:    }
  1, 0,                                      //  1539:    case 0x1: {
  OPC_Decode, 239, 19, 3,                    //  1541:     decode to VSRQ using decoder 3
                                             //  1541:    }
                                             //  1541:    } // switch Inst[0]
                                             //  1541:   }
  9, 8,                                      //  1545:   case 0x9: {
  OPC_CheckField, 0, 1, 0,                   //  1547:    check Inst[0] == 0x0
  OPC_Decode, 237, 19, 3,                    //  1551:    decode to VSRH using decoder 3
                                             //  1551:   }
  10, 8,                                     //  1555:   case 0xa: {
  OPC_CheckField, 0, 1, 0,                   //  1557:    check Inst[0] == 0x0
  OPC_Decode, 241, 19, 3,                    //  1561:    decode to VSRW using decoder 3
                                             //  1561:   }
  11, 8,                                     //  1565:   case 0xb: {
  OPC_CheckField, 0, 1, 0,                   //  1567:    check Inst[0] == 0x0
  OPC_Decode, 228, 19, 3,                    //  1571:    decode to VSR using decoder 3
                                             //  1571:   }
  12, 15,                                    //  1575:   case 0xc: {
  OPC_SwitchField, 0, 1,                     //  1577:    switch Inst[0] {
  0, 4,                                      //  1580:    case 0x0: {
  OPC_Decode, 229, 19, 3,                    //  1582:     decode to VSRAB using decoder 3
                                             //  1582:    }
  1, 0,                                      //  1586:    case 0x1: {
  OPC_Decode, 232, 19, 3,                    //  1588:     decode to VSRAQ using decoder 3
                                             //  1588:    }
                                             //  1588:    } // switch Inst[0]
                                             //  1588:   }
  13, 8,                                     //  1592:   case 0xd: {
  OPC_CheckField, 0, 1, 0,                   //  1594:    check Inst[0] == 0x0
  OPC_Decode, 231, 19, 3,                    //  1598:    decode to VSRAH using decoder 3
                                             //  1598:   }
  14, 8,                                     //  1602:   case 0xe: {
  OPC_CheckField, 0, 1, 0,                   //  1604:    check Inst[0] == 0x0
  OPC_Decode, 233, 19, 3,                    //  1608:    decode to VSRAW using decoder 3
                                             //  1608:   }
  15, 8,                                     //  1612:   case 0xf: {
  OPC_CheckField, 0, 1, 0,                   //  1614:    check Inst[0] == 0x0
  OPC_Decode, 230, 19, 3,                    //  1618:    decode to VSRAD using decoder 3
                                             //  1618:   }
  16, 8,                                     //  1622:   case 0x10: {
  OPC_CheckField, 0, 1, 0,                   //  1624:    check Inst[0] == 0x0
  OPC_Decode, 170, 17, 3,                    //  1628:    decode to VAND using decoder 3
                                             //  1628:   }
  17, 8,                                     //  1632:   case 0x11: {
  OPC_CheckField, 0, 1, 0,                   //  1634:    check Inst[0] == 0x0
  OPC_Decode, 171, 17, 3,                    //  1638:    decode to VANDC using decoder 3
                                             //  1638:   }
  18, 8,                                     //  1642:   case 0x12: {
  OPC_CheckField, 0, 1, 0,                   //  1644:    check Inst[0] == 0x0
  OPC_Decode, 158, 19, 3,                    //  1648:    decode to VOR using decoder 3
                                             //  1648:   }
  19, 8,                                     //  1652:   case 0x13: {
  OPC_CheckField, 0, 1, 0,                   //  1654:    check Inst[0] == 0x0
  OPC_Decode, 163, 20, 3,                    //  1658:    decode to VXOR using decoder 3
                                             //  1658:   }
  20, 8,                                     //  1662:   case 0x14: {
  OPC_CheckField, 0, 1, 0,                   //  1664:    check Inst[0] == 0x0
  OPC_Decode, 157, 19, 3,                    //  1668:    decode to VNOR using decoder 3
                                             //  1668:   }
  21, 8,                                     //  1672:   case 0x15: {
  OPC_CheckField, 0, 1, 0,                   //  1674:    check Inst[0] == 0x0
  OPC_Decode, 159, 19, 3,                    //  1678:    decode to VORC using decoder 3
                                             //  1678:   }
  22, 8,                                     //  1682:   case 0x16: {
  OPC_CheckField, 0, 1, 0,                   //  1684:    check Inst[0] == 0x0
  OPC_Decode, 151, 19, 3,                    //  1688:    decode to VNAND using decoder 3
                                             //  1688:   }
  23, 8,                                     //  1692:   case 0x17: {
  OPC_CheckField, 0, 1, 0,                   //  1694:    check Inst[0] == 0x0
  OPC_Decode, 212, 19, 3,                    //  1698:    decode to VSLD using decoder 3
                                             //  1698:   }
  24, 12,                                    //  1702:   case 0x18: {
  OPC_CheckField, 11, 10, 0,                 //  1704:    check Inst[20:11] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  1708:    check Inst[0] == 0x0
  OPC_Decode, 249, 11, 17,                   //  1712:    decode to MFVSCR using decoder 17
                                             //  1712:   }
  25, 12,                                    //  1716:   case 0x19: {
  OPC_CheckField, 16, 10, 0,                 //  1718:    check Inst[25:16] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  1722:    check Inst[0] == 0x0
  OPC_Decode, 165, 12, 18,                   //  1726:    decode to MTVSCR using decoder 18
                                             //  1726:   }
  26, 8,                                     //  1730:   case 0x1a: {
  OPC_CheckField, 0, 1, 0,                   //  1732:    check Inst[0] == 0x0
  OPC_Decode, 145, 18, 3,                    //  1736:    decode to VEQV using decoder 3
                                             //  1736:   }
  27, 8,                                     //  1740:   case 0x1b: {
  OPC_CheckField, 0, 1, 0,                   //  1742:    check Inst[0] == 0x0
  OPC_Decode, 235, 19, 3,                    //  1746:    decode to VSRD using decoder 3
                                             //  1746:   }
  28, 8,                                     //  1750:   case 0x1c: {
  OPC_CheckField, 0, 1, 0,                   //  1752:    check Inst[0] == 0x0
  OPC_Decode, 240, 19, 3,                    //  1756:    decode to VSRV using decoder 3
                                             //  1756:   }
  29, 8,                                     //  1760:   case 0x1d: {
  OPC_CheckField, 0, 1, 0,                   //  1762:    check Inst[0] == 0x0
  OPC_Decode, 218, 19, 3,                    //  1766:    decode to VSLV using decoder 3
                                             //  1766:   }
  30, 8,                                     //  1770:   case 0x1e: {
  OPC_CheckField, 0, 1, 0,                   //  1772:    check Inst[0] == 0x0
  OPC_Decode, 191, 17, 3,                    //  1776:    decode to VCLZDM using decoder 3
                                             //  1776:   }
  31, 0,                                     //  1780:   case 0x1f: {
  OPC_CheckField, 0, 1, 0,                   //  1782:    check Inst[0] == 0x0
  OPC_Decode, 129, 18, 3,                    //  1786:    decode to VCTZDM using decoder 3
                                             //  1786:   }
                                             //  1786:   } // switch Inst[10:6]
                                             //  1786:  }
  3, 193, 3,                                 //  1790:  case 0x3: {
  OPC_SwitchField, 6, 5,                     //  1793:   switch Inst[10:6] {
  0, 15,                                     //  1796:   case 0x0: {
  OPC_SwitchField, 0, 1,                     //  1798:    switch Inst[0] {
  0, 4,                                      //  1801:    case 0x0: {
  OPC_Decode, 199, 17, 3,                    //  1803:     decode to VCMPEQUB using decoder 3
                                             //  1803:    }
  1, 0,                                      //  1807:    case 0x1: {
  OPC_Decode, 233, 17, 3,                    //  1809:     decode to VCMPNEB using decoder 3
                                             //  1809:    }
                                             //  1809:    } // switch Inst[0]
                                             //  1809:   }
  1, 15,                                     //  1813:   case 0x1: {
  OPC_SwitchField, 0, 1,                     //  1815:    switch Inst[0] {
  0, 4,                                      //  1818:    case 0x0: {
  OPC_Decode, 203, 17, 3,                    //  1820:     decode to VCMPEQUH using decoder 3
                                             //  1820:    }
  1, 0,                                      //  1824:    case 0x1: {
  OPC_Decode, 235, 17, 3,                    //  1826:     decode to VCMPNEH using decoder 3
                                             //  1826:    }
                                             //  1826:    } // switch Inst[0]
                                             //  1826:   }
  2, 15,                                     //  1830:   case 0x2: {
  OPC_SwitchField, 0, 1,                     //  1832:    switch Inst[0] {
  0, 4,                                      //  1835:    case 0x0: {
  OPC_Decode, 207, 17, 3,                    //  1837:     decode to VCMPEQUW using decoder 3
                                             //  1837:    }
  1, 0,                                      //  1841:    case 0x1: {
  OPC_Decode, 237, 17, 3,                    //  1843:     decode to VCMPNEW using decoder 3
                                             //  1843:    }
                                             //  1843:    } // switch Inst[0]
                                             //  1843:   }
  3, 15,                                     //  1847:   case 0x3: {
  OPC_SwitchField, 0, 1,                     //  1849:    switch Inst[0] {
  0, 4,                                      //  1852:    case 0x0: {
  OPC_Decode, 197, 17, 3,                    //  1854:     decode to VCMPEQFP using decoder 3
                                             //  1854:    }
  1, 0,                                      //  1858:    case 0x1: {
  OPC_Decode, 201, 17, 3,                    //  1860:     decode to VCMPEQUD using decoder 3
                                             //  1860:    }
                                             //  1860:    } // switch Inst[0]
                                             //  1860:   }
  4, 8,                                      //  1864:   case 0x4: {
  OPC_CheckField, 0, 1, 1,                   //  1866:    check Inst[0] == 0x1
  OPC_Decode, 239, 17, 3,                    //  1870:    decode to VCMPNEZB using decoder 3
                                             //  1870:   }
  5, 8,                                      //  1874:   case 0x5: {
  OPC_CheckField, 0, 1, 1,                   //  1876:    check Inst[0] == 0x1
  OPC_Decode, 241, 17, 3,                    //  1880:    decode to VCMPNEZH using decoder 3
                                             //  1880:   }
  6, 8,                                      //  1884:   case 0x6: {
  OPC_CheckField, 0, 1, 1,                   //  1886:    check Inst[0] == 0x1
  OPC_Decode, 243, 17, 3,                    //  1890:    decode to VCMPNEZW using decoder 3
                                             //  1890:   }
  7, 15,                                     //  1894:   case 0x7: {
  OPC_SwitchField, 0, 1,                     //  1896:    switch Inst[0] {
  0, 4,                                      //  1899:    case 0x0: {
  OPC_Decode, 209, 17, 3,                    //  1901:     decode to VCMPGEFP using decoder 3
                                             //  1901:    }
  1, 0,                                      //  1905:    case 0x1: {
  OPC_Decode, 205, 17, 3,                    //  1907:     decode to VCMPEQUQ using decoder 3
                                             //  1907:    }
                                             //  1907:    } // switch Inst[0]
                                             //  1907:   }
  8, 8,                                      //  1911:   case 0x8: {
  OPC_CheckField, 0, 1, 0,                   //  1913:    check Inst[0] == 0x0
  OPC_Decode, 223, 17, 3,                    //  1917:    decode to VCMPGTUB using decoder 3
                                             //  1917:   }
  9, 8,                                      //  1921:   case 0x9: {
  OPC_CheckField, 0, 1, 0,                   //  1923:    check Inst[0] == 0x0
  OPC_Decode, 227, 17, 3,                    //  1927:    decode to VCMPGTUH using decoder 3
                                             //  1927:   }
  10, 15,                                    //  1931:   case 0xa: {
  OPC_SwitchField, 0, 1,                     //  1933:    switch Inst[0] {
  0, 4,                                      //  1936:    case 0x0: {
  OPC_Decode, 231, 17, 3,                    //  1938:     decode to VCMPGTUW using decoder 3
                                             //  1938:    }
  1, 0,                                      //  1942:    case 0x1: {
  OPC_Decode, 229, 17, 3,                    //  1944:     decode to VCMPGTUQ using decoder 3
                                             //  1944:    }
                                             //  1944:    } // switch Inst[0]
                                             //  1944:   }
  11, 15,                                    //  1948:   case 0xb: {
  OPC_SwitchField, 0, 1,                     //  1950:    switch Inst[0] {
  0, 4,                                      //  1953:    case 0x0: {
  OPC_Decode, 211, 17, 3,                    //  1955:     decode to VCMPGTFP using decoder 3
                                             //  1955:    }
  1, 0,                                      //  1959:    case 0x1: {
  OPC_Decode, 225, 17, 3,                    //  1961:     decode to VCMPGTUD using decoder 3
                                             //  1961:    }
                                             //  1961:    } // switch Inst[0]
                                             //  1961:   }
  12, 8,                                     //  1965:   case 0xc: {
  OPC_CheckField, 0, 1, 0,                   //  1967:    check Inst[0] == 0x0
  OPC_Decode, 213, 17, 3,                    //  1971:    decode to VCMPGTSB using decoder 3
                                             //  1971:   }
  13, 8,                                     //  1975:   case 0xd: {
  OPC_CheckField, 0, 1, 0,                   //  1977:    check Inst[0] == 0x0
  OPC_Decode, 217, 17, 3,                    //  1981:    decode to VCMPGTSH using decoder 3
                                             //  1981:   }
  14, 15,                                    //  1985:   case 0xe: {
  OPC_SwitchField, 0, 1,                     //  1987:    switch Inst[0] {
  0, 4,                                      //  1990:    case 0x0: {
  OPC_Decode, 221, 17, 3,                    //  1992:     decode to VCMPGTSW using decoder 3
                                             //  1992:    }
  1, 0,                                      //  1996:    case 0x1: {
  OPC_Decode, 219, 17, 3,                    //  1998:     decode to VCMPGTSQ using decoder 3
                                             //  1998:    }
                                             //  1998:    } // switch Inst[0]
                                             //  1998:   }
  15, 15,                                    //  2002:   case 0xf: {
  OPC_SwitchField, 0, 1,                     //  2004:    switch Inst[0] {
  0, 4,                                      //  2007:    case 0x0: {
  OPC_Decode, 195, 17, 3,                    //  2009:     decode to VCMPBFP using decoder 3
                                             //  2009:    }
  1, 0,                                      //  2013:    case 0x1: {
  OPC_Decode, 215, 17, 3,                    //  2015:     decode to VCMPGTSD using decoder 3
                                             //  2015:    }
                                             //  2015:    } // switch Inst[0]
                                             //  2015:   }
  16, 15,                                    //  2019:   case 0x10: {
  OPC_SwitchField, 0, 1,                     //  2021:    switch Inst[0] {
  0, 4,                                      //  2024:    case 0x0: {
  OPC_Decode, 200, 17, 3,                    //  2026:     decode to VCMPEQUB_rec using decoder 3
                                             //  2026:    }
  1, 0,                                      //  2030:    case 0x1: {
  OPC_Decode, 234, 17, 3,                    //  2032:     decode to VCMPNEB_rec using decoder 3
                                             //  2032:    }
                                             //  2032:    } // switch Inst[0]
                                             //  2032:   }
  17, 15,                                    //  2036:   case 0x11: {
  OPC_SwitchField, 0, 1,                     //  2038:    switch Inst[0] {
  0, 4,                                      //  2041:    case 0x0: {
  OPC_Decode, 204, 17, 3,                    //  2043:     decode to VCMPEQUH_rec using decoder 3
                                             //  2043:    }
  1, 0,                                      //  2047:    case 0x1: {
  OPC_Decode, 236, 17, 3,                    //  2049:     decode to VCMPNEH_rec using decoder 3
                                             //  2049:    }
                                             //  2049:    } // switch Inst[0]
                                             //  2049:   }
  18, 15,                                    //  2053:   case 0x12: {
  OPC_SwitchField, 0, 1,                     //  2055:    switch Inst[0] {
  0, 4,                                      //  2058:    case 0x0: {
  OPC_Decode, 208, 17, 3,                    //  2060:     decode to VCMPEQUW_rec using decoder 3
                                             //  2060:    }
  1, 0,                                      //  2064:    case 0x1: {
  OPC_Decode, 238, 17, 3,                    //  2066:     decode to VCMPNEW_rec using decoder 3
                                             //  2066:    }
                                             //  2066:    } // switch Inst[0]
                                             //  2066:   }
  19, 15,                                    //  2070:   case 0x13: {
  OPC_SwitchField, 0, 1,                     //  2072:    switch Inst[0] {
  0, 4,                                      //  2075:    case 0x0: {
  OPC_Decode, 198, 17, 3,                    //  2077:     decode to VCMPEQFP_rec using decoder 3
                                             //  2077:    }
  1, 0,                                      //  2081:    case 0x1: {
  OPC_Decode, 202, 17, 3,                    //  2083:     decode to VCMPEQUD_rec using decoder 3
                                             //  2083:    }
                                             //  2083:    } // switch Inst[0]
                                             //  2083:   }
  20, 8,                                     //  2087:   case 0x14: {
  OPC_CheckField, 0, 1, 1,                   //  2089:    check Inst[0] == 0x1
  OPC_Decode, 240, 17, 3,                    //  2093:    decode to VCMPNEZB_rec using decoder 3
                                             //  2093:   }
  21, 8,                                     //  2097:   case 0x15: {
  OPC_CheckField, 0, 1, 1,                   //  2099:    check Inst[0] == 0x1
  OPC_Decode, 242, 17, 3,                    //  2103:    decode to VCMPNEZH_rec using decoder 3
                                             //  2103:   }
  22, 8,                                     //  2107:   case 0x16: {
  OPC_CheckField, 0, 1, 1,                   //  2109:    check Inst[0] == 0x1
  OPC_Decode, 244, 17, 3,                    //  2113:    decode to VCMPNEZW_rec using decoder 3
                                             //  2113:   }
  23, 15,                                    //  2117:   case 0x17: {
  OPC_SwitchField, 0, 1,                     //  2119:    switch Inst[0] {
  0, 4,                                      //  2122:    case 0x0: {
  OPC_Decode, 210, 17, 3,                    //  2124:     decode to VCMPGEFP_rec using decoder 3
                                             //  2124:    }
  1, 0,                                      //  2128:    case 0x1: {
  OPC_Decode, 206, 17, 3,                    //  2130:     decode to VCMPEQUQ_rec using decoder 3
                                             //  2130:    }
                                             //  2130:    } // switch Inst[0]
                                             //  2130:   }
  24, 8,                                     //  2134:   case 0x18: {
  OPC_CheckField, 0, 1, 0,                   //  2136:    check Inst[0] == 0x0
  OPC_Decode, 224, 17, 3,                    //  2140:    decode to VCMPGTUB_rec using decoder 3
                                             //  2140:   }
  25, 8,                                     //  2144:   case 0x19: {
  OPC_CheckField, 0, 1, 0,                   //  2146:    check Inst[0] == 0x0
  OPC_Decode, 228, 17, 3,                    //  2150:    decode to VCMPGTUH_rec using decoder 3
                                             //  2150:   }
  26, 15,                                    //  2154:   case 0x1a: {
  OPC_SwitchField, 0, 1,                     //  2156:    switch Inst[0] {
  0, 4,                                      //  2159:    case 0x0: {
  OPC_Decode, 232, 17, 3,                    //  2161:     decode to VCMPGTUW_rec using decoder 3
                                             //  2161:    }
  1, 0,                                      //  2165:    case 0x1: {
  OPC_Decode, 230, 17, 3,                    //  2167:     decode to VCMPGTUQ_rec using decoder 3
                                             //  2167:    }
                                             //  2167:    } // switch Inst[0]
                                             //  2167:   }
  27, 15,                                    //  2171:   case 0x1b: {
  OPC_SwitchField, 0, 1,                     //  2173:    switch Inst[0] {
  0, 4,                                      //  2176:    case 0x0: {
  OPC_Decode, 212, 17, 3,                    //  2178:     decode to VCMPGTFP_rec using decoder 3
                                             //  2178:    }
  1, 0,                                      //  2182:    case 0x1: {
  OPC_Decode, 226, 17, 3,                    //  2184:     decode to VCMPGTUD_rec using decoder 3
                                             //  2184:    }
                                             //  2184:    } // switch Inst[0]
                                             //  2184:   }
  28, 8,                                     //  2188:   case 0x1c: {
  OPC_CheckField, 0, 1, 0,                   //  2190:    check Inst[0] == 0x0
  OPC_Decode, 214, 17, 3,                    //  2194:    decode to VCMPGTSB_rec using decoder 3
                                             //  2194:   }
  29, 8,                                     //  2198:   case 0x1d: {
  OPC_CheckField, 0, 1, 0,                   //  2200:    check Inst[0] == 0x0
  OPC_Decode, 218, 17, 3,                    //  2204:    decode to VCMPGTSH_rec using decoder 3
                                             //  2204:   }
  30, 15,                                    //  2208:   case 0x1e: {
  OPC_SwitchField, 0, 1,                     //  2210:    switch Inst[0] {
  0, 4,                                      //  2213:    case 0x0: {
  OPC_Decode, 222, 17, 3,                    //  2215:     decode to VCMPGTSW_rec using decoder 3
                                             //  2215:    }
  1, 0,                                      //  2219:    case 0x1: {
  OPC_Decode, 220, 17, 3,                    //  2221:     decode to VCMPGTSQ_rec using decoder 3
                                             //  2221:    }
                                             //  2221:    } // switch Inst[0]
                                             //  2221:   }
  31, 0,                                     //  2225:   case 0x1f: {
  OPC_SwitchField, 0, 1,                     //  2227:    switch Inst[0] {
  0, 4,                                      //  2230:    case 0x0: {
  OPC_Decode, 196, 17, 3,                    //  2232:     decode to VCMPBFP_rec using decoder 3
                                             //  2232:    }
  1, 0,                                      //  2236:    case 0x1: {
  OPC_Decode, 216, 17, 3,                    //  2238:     decode to VCMPGTSD_rec using decoder 3
                                             //  2238:    }
                                             //  2238:    } // switch Inst[0]
                                             //  2238:   }
                                             //  2238:   } // switch Inst[10:6]
                                             //  2238:  }
  4, 215, 2,                                 //  2242:  case 0x4: {
  OPC_SwitchField, 6, 5,                     //  2245:   switch Inst[10:6] {
  0, 8,                                      //  2248:   case 0x0: {
  OPC_CheckField, 0, 1, 0,                   //  2250:    check Inst[0] == 0x0
  OPC_Decode, 146, 19, 3,                    //  2254:    decode to VMULOUB using decoder 3
                                             //  2254:   }
  1, 8,                                      //  2258:   case 0x1: {
  OPC_CheckField, 0, 1, 0,                   //  2260:    check Inst[0] == 0x0
  OPC_Decode, 148, 19, 3,                    //  2264:    decode to VMULOUH using decoder 3
                                             //  2264:   }
  2, 15,                                     //  2268:   case 0x2: {
  OPC_SwitchField, 0, 1,                     //  2270:    switch Inst[0] {
  0, 4,                                      //  2273:    case 0x0: {
  OPC_Decode, 149, 19, 3,                    //  2275:     decode to VMULOUW using decoder 3
                                             //  2275:    }
  1, 0,                                      //  2279:    case 0x1: {
  OPC_Decode, 150, 19, 3,                    //  2281:     decode to VMULUWM using decoder 3
                                             //  2281:    }
                                             //  2281:    } // switch Inst[0]
                                             //  2281:   }
  3, 8,                                      //  2285:   case 0x3: {
  OPC_CheckField, 0, 1, 0,                   //  2287:    check Inst[0] == 0x0
  OPC_Decode, 147, 19, 3,                    //  2291:    decode to VMULOUD using decoder 3
                                             //  2291:   }
  4, 8,                                      //  2295:   case 0x4: {
  OPC_CheckField, 0, 1, 0,                   //  2297:    check Inst[0] == 0x0
  OPC_Decode, 142, 19, 3,                    //  2301:    decode to VMULOSB using decoder 3
                                             //  2301:   }
  5, 8,                                      //  2305:   case 0x5: {
  OPC_CheckField, 0, 1, 0,                   //  2307:    check Inst[0] == 0x0
  OPC_Decode, 144, 19, 3,                    //  2311:    decode to VMULOSH using decoder 3
                                             //  2311:   }
  6, 8,                                      //  2315:   case 0x6: {
  OPC_CheckField, 0, 1, 0,                   //  2317:    check Inst[0] == 0x0
  OPC_Decode, 145, 19, 3,                    //  2321:    decode to VMULOSW using decoder 3
                                             //  2321:   }
  7, 15,                                     //  2325:   case 0x7: {
  OPC_SwitchField, 0, 1,                     //  2327:    switch Inst[0] {
  0, 4,                                      //  2330:    case 0x0: {
  OPC_Decode, 143, 19, 3,                    //  2332:     decode to VMULOSD using decoder 3
                                             //  2332:    }
  1, 0,                                      //  2336:    case 0x1: {
  OPC_Decode, 141, 19, 3,                    //  2338:     decode to VMULLD using decoder 3
                                             //  2338:    }
                                             //  2338:    } // switch Inst[0]
                                             //  2338:   }
  8, 8,                                      //  2342:   case 0x8: {
  OPC_CheckField, 0, 1, 0,                   //  2344:    check Inst[0] == 0x0
  OPC_Decode, 133, 19, 3,                    //  2348:    decode to VMULEUB using decoder 3
                                             //  2348:   }
  9, 8,                                      //  2352:   case 0x9: {
  OPC_CheckField, 0, 1, 0,                   //  2354:    check Inst[0] == 0x0
  OPC_Decode, 135, 19, 3,                    //  2358:    decode to VMULEUH using decoder 3
                                             //  2358:   }
  10, 15,                                    //  2362:   case 0xa: {
  OPC_SwitchField, 0, 1,                     //  2364:    switch Inst[0] {
  0, 4,                                      //  2367:    case 0x0: {
  OPC_Decode, 136, 19, 3,                    //  2369:     decode to VMULEUW using decoder 3
                                             //  2369:    }
  1, 0,                                      //  2373:    case 0x1: {
  OPC_Decode, 140, 19, 3,                    //  2375:     decode to VMULHUW using decoder 3
                                             //  2375:    }
                                             //  2375:    } // switch Inst[0]
                                             //  2375:   }
  11, 15,                                    //  2379:   case 0xb: {
  OPC_SwitchField, 0, 1,                     //  2381:    switch Inst[0] {
  0, 4,                                      //  2384:    case 0x0: {
  OPC_Decode, 134, 19, 3,                    //  2386:     decode to VMULEUD using decoder 3
                                             //  2386:    }
  1, 0,                                      //  2390:    case 0x1: {
  OPC_Decode, 139, 19, 3,                    //  2392:     decode to VMULHUD using decoder 3
                                             //  2392:    }
                                             //  2392:    } // switch Inst[0]
                                             //  2392:   }
  12, 8,                                     //  2396:   case 0xc: {
  OPC_CheckField, 0, 1, 0,                   //  2398:    check Inst[0] == 0x0
  OPC_Decode, 129, 19, 3,                    //  2402:    decode to VMULESB using decoder 3
                                             //  2402:   }
  13, 8,                                     //  2406:   case 0xd: {
  OPC_CheckField, 0, 1, 0,                   //  2408:    check Inst[0] == 0x0
  OPC_Decode, 131, 19, 3,                    //  2412:    decode to VMULESH using decoder 3
                                             //  2412:   }
  14, 15,                                    //  2416:   case 0xe: {
  OPC_SwitchField, 0, 1,                     //  2418:    switch Inst[0] {
  0, 4,                                      //  2421:    case 0x0: {
  OPC_Decode, 132, 19, 3,                    //  2423:     decode to VMULESW using decoder 3
                                             //  2423:    }
  1, 0,                                      //  2427:    case 0x1: {
  OPC_Decode, 138, 19, 3,                    //  2429:     decode to VMULHSW using decoder 3
                                             //  2429:    }
                                             //  2429:    } // switch Inst[0]
                                             //  2429:   }
  15, 15,                                    //  2433:   case 0xf: {
  OPC_SwitchField, 0, 1,                     //  2435:    switch Inst[0] {
  0, 4,                                      //  2438:    case 0x0: {
  OPC_Decode, 130, 19, 3,                    //  2440:     decode to VMULESD using decoder 3
                                             //  2440:    }
  1, 0,                                      //  2444:    case 0x1: {
  OPC_Decode, 137, 19, 3,                    //  2446:     decode to VMULHSD using decoder 3
                                             //  2446:    }
                                             //  2446:    } // switch Inst[0]
                                             //  2446:   }
  16, 8,                                     //  2450:   case 0x10: {
  OPC_CheckField, 0, 1, 0,                   //  2452:    check Inst[0] == 0x0
  OPC_Decode, 178, 19, 3,                    //  2456:    decode to VPMSUMB using decoder 3
                                             //  2456:   }
  17, 8,                                     //  2460:   case 0x11: {
  OPC_CheckField, 0, 1, 0,                   //  2462:    check Inst[0] == 0x0
  OPC_Decode, 180, 19, 3,                    //  2466:    decode to VPMSUMH using decoder 3
                                             //  2466:   }
  18, 8,                                     //  2470:   case 0x12: {
  OPC_CheckField, 0, 1, 0,                   //  2472:    check Inst[0] == 0x0
  OPC_Decode, 181, 19, 3,                    //  2476:    decode to VPMSUMW using decoder 3
                                             //  2476:   }
  19, 8,                                     //  2480:   case 0x13: {
  OPC_CheckField, 0, 1, 0,                   //  2482:    check Inst[0] == 0x0
  OPC_Decode, 179, 19, 3,                    //  2486:    decode to VPMSUMD using decoder 3
                                             //  2486:   }
  20, 15,                                    //  2490:   case 0x14: {
  OPC_SwitchField, 0, 1,                     //  2492:    switch Inst[0] {
  0, 4,                                      //  2495:    case 0x0: {
  OPC_Decode, 185, 17, 3,                    //  2497:     decode to VCIPHER using decoder 3
                                             //  2497:    }
  1, 0,                                      //  2501:    case 0x1: {
  OPC_Decode, 186, 17, 3,                    //  2503:     decode to VCIPHERLAST using decoder 3
                                             //  2503:    }
                                             //  2503:    } // switch Inst[0]
                                             //  2503:   }
  21, 15,                                    //  2507:   case 0x15: {
  OPC_SwitchField, 0, 1,                     //  2509:    switch Inst[0] {
  0, 4,                                      //  2512:    case 0x0: {
  OPC_Decode, 152, 19, 3,                    //  2514:     decode to VNCIPHER using decoder 3
                                             //  2514:    }
  1, 0,                                      //  2518:    case 0x1: {
  OPC_Decode, 153, 19, 3,                    //  2520:     decode to VNCIPHERLAST using decoder 3
                                             //  2520:    }
                                             //  2520:    } // switch Inst[0]
                                             //  2520:   }
  23, 12,                                    //  2524:   case 0x17: {
  OPC_CheckField, 11, 5, 0,                  //  2526:    check Inst[15:11] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  2530:    check Inst[0] == 0x0
  OPC_Decode, 206, 19, 4,                    //  2534:    decode to VSBOX using decoder 4
                                             //  2534:   }
  24, 8,                                     //  2538:   case 0x18: {
  OPC_CheckField, 0, 1, 0,                   //  2540:    check Inst[0] == 0x0
  OPC_Decode, 141, 20, 3,                    //  2544:    decode to VSUM4UBS using decoder 3
                                             //  2544:   }
  25, 8,                                     //  2548:   case 0x19: {
  OPC_CheckField, 0, 1, 0,                   //  2550:    check Inst[0] == 0x0
  OPC_Decode, 140, 20, 3,                    //  2554:    decode to VSUM4SHS using decoder 3
                                             //  2554:   }
  26, 8,                                     //  2558:   case 0x1a: {
  OPC_CheckField, 0, 1, 0,                   //  2560:    check Inst[0] == 0x0
  OPC_Decode, 138, 20, 3,                    //  2564:    decode to VSUM2SWS using decoder 3
                                             //  2564:   }
  28, 8,                                     //  2568:   case 0x1c: {
  OPC_CheckField, 0, 1, 0,                   //  2570:    check Inst[0] == 0x0
  OPC_Decode, 139, 20, 3,                    //  2574:    decode to VSUM4SBS using decoder 3
                                             //  2574:   }
  30, 0,                                     //  2578:   case 0x1e: {
  OPC_CheckField, 0, 1, 0,                   //  2580:    check Inst[0] == 0x0
  OPC_Decode, 142, 20, 3,                    //  2584:    decode to VSUMSWS using decoder 3
                                             //  2584:   }
                                             //  2584:   } // switch Inst[10:6]
                                             //  2584:  }
  5, 217, 2,                                 //  2588:  case 0x5: {
  OPC_SwitchField, 6, 5,                     //  2591:   switch Inst[10:6] {
  0, 15,                                     //  2594:   case 0x0: {
  OPC_SwitchField, 0, 1,                     //  2596:    switch Inst[0] {
  0, 4,                                      //  2599:    case 0x0: {
  OPC_Decode, 158, 17, 3,                    //  2601:     decode to VADDFP using decoder 3
                                             //  2601:    }
  1, 0,                                      //  2605:    case 0x1: {
  OPC_Decode, 143, 18, 3,                    //  2607:     decode to VDIVUQ using decoder 3
                                             //  2607:    }
                                             //  2607:    } // switch Inst[0]
                                             //  2607:   }
  1, 8,                                      //  2611:   case 0x1: {
  OPC_CheckField, 0, 1, 0,                   //  2613:    check Inst[0] == 0x0
  OPC_Decode, 254, 19, 3,                    //  2617:    decode to VSUBFP using decoder 3
                                             //  2617:   }
  2, 8,                                      //  2621:   case 0x2: {
  OPC_CheckField, 0, 1, 1,                   //  2623:    check Inst[0] == 0x1
  OPC_Decode, 144, 18, 3,                    //  2627:    decode to VDIVUW using decoder 3
                                             //  2627:   }
  3, 8,                                      //  2631:   case 0x3: {
  OPC_CheckField, 0, 1, 1,                   //  2633:    check Inst[0] == 0x1
  OPC_Decode, 142, 18, 3,                    //  2637:    decode to VDIVUD using decoder 3
                                             //  2637:   }
  4, 19,                                     //  2641:   case 0x4: {
  OPC_SwitchField, 0, 1,                     //  2643:    switch Inst[0] {
  0, 8,                                      //  2646:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  //  2648:     check Inst[20:16] == 0x0
  OPC_Decode, 189, 19, 7,                    //  2652:     decode to VREFP using decoder 7
                                             //  2652:    }
  1, 0,                                      //  2656:    case 0x1: {
  OPC_Decode, 140, 18, 3,                    //  2658:     decode to VDIVSQ using decoder 3
                                             //  2658:    }
                                             //  2658:    } // switch Inst[0]
                                             //  2658:   }
  5, 12,                                     //  2662:   case 0x5: {
  OPC_CheckField, 16, 5, 0,                  //  2664:    check Inst[20:16] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  2668:    check Inst[0] == 0x0
  OPC_Decode, 205, 19, 7,                    //  2672:    decode to VRSQRTEFP using decoder 7
                                             //  2672:   }
  6, 19,                                     //  2676:   case 0x6: {
  OPC_SwitchField, 0, 1,                     //  2678:    switch Inst[0] {
  0, 8,                                      //  2681:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  //  2683:     check Inst[20:16] == 0x0
  OPC_Decode, 151, 18, 7,                    //  2687:     decode to VEXPTEFP using decoder 7
                                             //  2687:    }
  1, 0,                                      //  2691:    case 0x1: {
  OPC_Decode, 141, 18, 3,                    //  2693:     decode to VDIVSW using decoder 3
                                             //  2693:    }
                                             //  2693:    } // switch Inst[0]
                                             //  2693:   }
  7, 19,                                     //  2697:   case 0x7: {
  OPC_SwitchField, 0, 1,                     //  2699:    switch Inst[0] {
  0, 8,                                      //  2702:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  //  2704:     check Inst[20:16] == 0x0
  OPC_Decode, 208, 18, 7,                    //  2708:     decode to VLOGEFP using decoder 7
                                             //  2708:    }
  1, 0,                                      //  2712:    case 0x1: {
  OPC_Decode, 139, 18, 3,                    //  2714:     decode to VDIVSD using decoder 3
                                             //  2714:    }
                                             //  2714:    } // switch Inst[0]
                                             //  2714:   }
  8, 19,                                     //  2718:   case 0x8: {
  OPC_SwitchField, 0, 1,                     //  2720:    switch Inst[0] {
  0, 8,                                      //  2723:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  //  2725:     check Inst[20:16] == 0x0
  OPC_Decode, 191, 19, 7,                    //  2729:     decode to VRFIN using decoder 7
                                             //  2729:    }
  1, 0,                                      //  2733:    case 0x1: {
  OPC_Decode, 137, 18, 3,                    //  2735:     decode to VDIVEUQ using decoder 3
                                             //  2735:    }
                                             //  2735:    } // switch Inst[0]
                                             //  2735:   }
  9, 12,                                     //  2739:   case 0x9: {
  OPC_CheckField, 16, 5, 0,                  //  2741:    check Inst[20:16] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  2745:    check Inst[0] == 0x0
  OPC_Decode, 193, 19, 7,                    //  2749:    decode to VRFIZ using decoder 7
                                             //  2749:   }
  10, 19,                                    //  2753:   case 0xa: {
  OPC_SwitchField, 0, 1,                     //  2755:    switch Inst[0] {
  0, 8,                                      //  2758:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  //  2760:     check Inst[20:16] == 0x0
  OPC_Decode, 192, 19, 7,                    //  2764:     decode to VRFIP using decoder 7
                                             //  2764:    }
  1, 0,                                      //  2768:    case 0x1: {
  OPC_Decode, 138, 18, 3,                    //  2770:     decode to VDIVEUW using decoder 3
                                             //  2770:    }
                                             //  2770:    } // switch Inst[0]
                                             //  2770:   }
  11, 19,                                    //  2774:   case 0xb: {
  OPC_SwitchField, 0, 1,                     //  2776:    switch Inst[0] {
  0, 8,                                      //  2779:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  //  2781:     check Inst[20:16] == 0x0
  OPC_Decode, 190, 19, 7,                    //  2785:     decode to VRFIM using decoder 7
                                             //  2785:    }
  1, 0,                                      //  2789:    case 0x1: {
  OPC_Decode, 136, 18, 3,                    //  2791:     decode to VDIVEUD using decoder 3
                                             //  2791:    }
                                             //  2791:    } // switch Inst[0]
                                             //  2791:   }
  12, 15,                                    //  2795:   case 0xc: {
  OPC_SwitchField, 0, 1,                     //  2797:    switch Inst[0] {
  0, 4,                                      //  2800:    case 0x0: {
  OPC_Decode, 183, 17, 19,                   //  2802:     decode to VCFUX using decoder 19
                                             //  2802:    }
  1, 0,                                      //  2806:    case 0x1: {
  OPC_Decode, 134, 18, 3,                    //  2808:     decode to VDIVESQ using decoder 3
                                             //  2808:    }
                                             //  2808:    } // switch Inst[0]
                                             //  2808:   }
  13, 8,                                     //  2812:   case 0xd: {
  OPC_CheckField, 0, 1, 0,                   //  2814:    check Inst[0] == 0x0
  OPC_Decode, 180, 17, 19,                   //  2818:    decode to VCFSX using decoder 19
                                             //  2818:   }
  14, 15,                                    //  2822:   case 0xe: {
  OPC_SwitchField, 0, 1,                     //  2824:    switch Inst[0] {
  0, 4,                                      //  2827:    case 0x0: {
  OPC_Decode, 253, 17, 19,                   //  2829:     decode to VCTUXS using decoder 19
                                             //  2829:    }
  1, 0,                                      //  2833:    case 0x1: {
  OPC_Decode, 135, 18, 3,                    //  2835:     decode to VDIVESW using decoder 3
                                             //  2835:    }
                                             //  2835:    } // switch Inst[0]
                                             //  2835:   }
  15, 15,                                    //  2839:   case 0xf: {
  OPC_SwitchField, 0, 1,                     //  2841:    switch Inst[0] {
  0, 4,                                      //  2844:    case 0x0: {
  OPC_Decode, 251, 17, 19,                   //  2846:     decode to VCTSXS using decoder 19
                                             //  2846:    }
  1, 0,                                      //  2850:    case 0x1: {
  OPC_Decode, 133, 18, 3,                    //  2852:     decode to VDIVESD using decoder 3
                                             //  2852:    }
                                             //  2852:    } // switch Inst[0]
                                             //  2852:   }
  16, 8,                                     //  2856:   case 0x10: {
  OPC_CheckField, 0, 1, 0,                   //  2858:    check Inst[0] == 0x0
  OPC_Decode, 210, 18, 3,                    //  2862:    decode to VMAXFP using decoder 3
                                             //  2862:   }
  17, 8,                                     //  2866:   case 0x11: {
  OPC_CheckField, 0, 1, 0,                   //  2868:    check Inst[0] == 0x0
  OPC_Decode, 221, 18, 3,                    //  2872:    decode to VMINFP using decoder 3
                                             //  2872:   }
  24, 8,                                     //  2876:   case 0x18: {
  OPC_CheckField, 0, 1, 1,                   //  2878:    check Inst[0] == 0x1
  OPC_Decode, 235, 18, 3,                    //  2882:    decode to VMODUQ using decoder 3
                                             //  2882:   }
  26, 8,                                     //  2886:   case 0x1a: {
  OPC_CheckField, 0, 1, 1,                   //  2888:    check Inst[0] == 0x1
  OPC_Decode, 236, 18, 3,                    //  2892:    decode to VMODUW using decoder 3
                                             //  2892:   }
  27, 8,                                     //  2896:   case 0x1b: {
  OPC_CheckField, 0, 1, 1,                   //  2898:    check Inst[0] == 0x1
  OPC_Decode, 234, 18, 3,                    //  2902:    decode to VMODUD using decoder 3
                                             //  2902:   }
  28, 8,                                     //  2906:   case 0x1c: {
  OPC_CheckField, 0, 1, 1,                   //  2908:    check Inst[0] == 0x1
  OPC_Decode, 232, 18, 3,                    //  2912:    decode to VMODSQ using decoder 3
                                             //  2912:   }
  30, 8,                                     //  2916:   case 0x1e: {
  OPC_CheckField, 0, 1, 1,                   //  2918:    check Inst[0] == 0x1
  OPC_Decode, 233, 18, 3,                    //  2922:    decode to VMODSW using decoder 3
                                             //  2922:   }
  31, 0,                                     //  2926:   case 0x1f: {
  OPC_CheckField, 0, 1, 1,                   //  2928:    check Inst[0] == 0x1
  OPC_Decode, 231, 18, 3,                    //  2932:    decode to VMODSD using decoder 3
                                             //  2932:   }
                                             //  2932:   } // switch Inst[10:6]
                                             //  2932:  }
  6, 184, 3,                                 //  2936:  case 0x6: {
  OPC_SwitchField, 6, 5,                     //  2939:   switch Inst[10:6] {
  0, 38,                                     //  2942:   case 0x0: {
  OPC_SwitchField, 0, 1,                     //  2944:    switch Inst[0] {
  0, 4,                                      //  2947:    case 0x0: {
  OPC_Decode, 238, 18, 3,                    //  2949:     decode to VMRGHB using decoder 3
                                             //  2949:    }
  1, 0,                                      //  2953:    case 0x1: {
  OPC_SwitchField, 16, 5,                    //  2955:     switch Inst[20:16] {
  0, 4,                                      //  2958:     case 0x0: {
  OPC_Decode, 242, 19, 7,                    //  2960:      decode to VSTRIBL using decoder 7
                                             //  2960:     }
  1, 4,                                      //  2964:     case 0x1: {
  OPC_Decode, 244, 19, 7,                    //  2966:      decode to VSTRIBR using decoder 7
                                             //  2966:     }
  2, 4,                                      //  2970:     case 0x2: {
  OPC_Decode, 246, 19, 7,                    //  2972:      decode to VSTRIHL using decoder 7
                                             //  2972:     }
  3, 0,                                      //  2976:     case 0x3: {
  OPC_Decode, 248, 19, 7,                    //  2978:      decode to VSTRIHR using decoder 7
                                             //  2978:     }
                                             //  2978:     } // switch Inst[20:16]
                                             //  2978:    }
                                             //  2978:    } // switch Inst[0]
                                             //  2978:   }
  1, 8,                                      //  2982:   case 0x1: {
  OPC_CheckField, 0, 1, 0,                   //  2984:    check Inst[0] == 0x0
  OPC_Decode, 239, 18, 3,                    //  2988:    decode to VMRGHH using decoder 3
                                             //  2988:   }
  2, 8,                                      //  2992:   case 0x2: {
  OPC_CheckField, 0, 1, 0,                   //  2994:    check Inst[0] == 0x0
  OPC_Decode, 240, 18, 3,                    //  2998:    decode to VMRGHW using decoder 3
                                             //  2998:   }
  4, 8,                                      //  3002:   case 0x4: {
  OPC_CheckField, 0, 1, 0,                   //  3004:    check Inst[0] == 0x0
  OPC_Decode, 241, 18, 3,                    //  3008:    decode to VMRGLB using decoder 3
                                             //  3008:   }
  5, 8,                                      //  3012:   case 0x5: {
  OPC_CheckField, 0, 1, 0,                   //  3014:    check Inst[0] == 0x0
  OPC_Decode, 242, 18, 3,                    //  3018:    decode to VMRGLH using decoder 3
                                             //  3018:   }
  6, 15,                                     //  3022:   case 0x6: {
  OPC_SwitchField, 0, 1,                     //  3024:    switch Inst[0] {
  0, 4,                                      //  3027:    case 0x0: {
  OPC_Decode, 243, 18, 3,                    //  3029:     decode to VMRGLW using decoder 3
                                             //  3029:    }
  1, 0,                                      //  3033:    case 0x1: {
  OPC_Decode, 187, 17, 20,                   //  3035:     decode to VCLRLB using decoder 20
                                             //  3035:    }
                                             //  3035:    } // switch Inst[0]
                                             //  3035:   }
  7, 8,                                      //  3039:   case 0x7: {
  OPC_CheckField, 0, 1, 1,                   //  3041:    check Inst[0] == 0x1
  OPC_Decode, 188, 17, 20,                   //  3045:    decode to VCLRRB using decoder 20
                                             //  3045:   }
  8, 15,                                     //  3049:   case 0x8: {
  OPC_SwitchField, 0, 1,                     //  3051:    switch Inst[0] {
  0, 4,                                      //  3054:    case 0x0: {
  OPC_Decode, 220, 19, 19,                   //  3056:     decode to VSPLTB using decoder 19
                                             //  3056:    }
  1, 0,                                      //  3060:    case 0x1: {
  OPC_Decode, 165, 18, 21,                   //  3062:     decode to VEXTRACTUB using decoder 21
                                             //  3062:    }
                                             //  3062:    } // switch Inst[0]
                                             //  3062:   }
  9, 15,                                     //  3066:   case 0x9: {
  OPC_SwitchField, 0, 1,                     //  3068:    switch Inst[0] {
  0, 4,                                      //  3071:    case 0x0: {
  OPC_Decode, 222, 19, 19,                   //  3073:     decode to VSPLTH using decoder 19
                                             //  3073:    }
  1, 0,                                      //  3077:    case 0x1: {
  OPC_Decode, 166, 18, 21,                   //  3079:     decode to VEXTRACTUH using decoder 21
                                             //  3079:    }
                                             //  3079:    } // switch Inst[0]
                                             //  3079:   }
  10, 15,                                    //  3083:   case 0xa: {
  OPC_SwitchField, 0, 1,                     //  3085:    switch Inst[0] {
  0, 4,                                      //  3088:    case 0x0: {
  OPC_Decode, 227, 19, 19,                   //  3090:     decode to VSPLTW using decoder 19
                                             //  3090:    }
  1, 0,                                      //  3094:    case 0x1: {
  OPC_Decode, 167, 18, 21,                   //  3096:     decode to VEXTRACTUW using decoder 21
                                             //  3096:    }
                                             //  3096:    } // switch Inst[0]
                                             //  3096:   }
  11, 8,                                     //  3100:   case 0xb: {
  OPC_CheckField, 0, 1, 1,                   //  3102:    check Inst[0] == 0x1
  OPC_Decode, 161, 18, 21,                   //  3106:    decode to VEXTRACTD using decoder 21
                                             //  3106:   }
  12, 19,                                    //  3110:   case 0xc: {
  OPC_SwitchField, 0, 1,                     //  3112:    switch Inst[0] {
  0, 8,                                      //  3115:    case 0x0: {
  OPC_CheckField, 11, 5, 0,                  //  3117:     check Inst[15:11] == 0x0
  OPC_Decode, 224, 19, 22,                   //  3121:     decode to VSPLTISB using decoder 22
                                             //  3121:    }
  1, 0,                                      //  3125:    case 0x1: {
  OPC_Decode, 195, 18, 23,                   //  3127:     decode to VINSERTB using decoder 23
                                             //  3127:    }
                                             //  3127:    } // switch Inst[0]
                                             //  3127:   }
  13, 19,                                    //  3131:   case 0xd: {
  OPC_SwitchField, 0, 1,                     //  3133:    switch Inst[0] {
  0, 8,                                      //  3136:    case 0x0: {
  OPC_CheckField, 11, 5, 0,                  //  3138:     check Inst[15:11] == 0x0
  OPC_Decode, 225, 19, 22,                   //  3142:     decode to VSPLTISH using decoder 22
                                             //  3142:    }
  1, 0,                                      //  3146:    case 0x1: {
  OPC_Decode, 197, 18, 23,                   //  3148:     decode to VINSERTH using decoder 23
                                             //  3148:    }
                                             //  3148:    } // switch Inst[0]
                                             //  3148:   }
  14, 19,                                    //  3152:   case 0xe: {
  OPC_SwitchField, 0, 1,                     //  3154:    switch Inst[0] {
  0, 8,                                      //  3157:    case 0x0: {
  OPC_CheckField, 11, 5, 0,                  //  3159:     check Inst[15:11] == 0x0
  OPC_Decode, 226, 19, 22,                   //  3163:     decode to VSPLTISW using decoder 22
                                             //  3163:    }
  1, 0,                                      //  3167:    case 0x1: {
  OPC_Decode, 198, 18, 21,                   //  3169:     decode to VINSERTW using decoder 21
                                             //  3169:    }
                                             //  3169:    } // switch Inst[0]
                                             //  3169:   }
  15, 8,                                     //  3173:   case 0xf: {
  OPC_CheckField, 0, 1, 1,                   //  3175:    check Inst[0] == 0x1
  OPC_Decode, 196, 18, 21,                   //  3179:    decode to VINSERTD using decoder 21
                                             //  3179:   }
  16, 38,                                    //  3183:   case 0x10: {
  OPC_SwitchField, 0, 1,                     //  3185:    switch Inst[0] {
  0, 4,                                      //  3188:    case 0x0: {
  OPC_Decode, 216, 19, 3,                    //  3190:     decode to VSLO using decoder 3
                                             //  3190:    }
  1, 0,                                      //  3194:    case 0x1: {
  OPC_SwitchField, 16, 5,                    //  3196:     switch Inst[20:16] {
  0, 4,                                      //  3199:     case 0x0: {
  OPC_Decode, 243, 19, 7,                    //  3201:      decode to VSTRIBL_rec using decoder 7
                                             //  3201:     }
  1, 4,                                      //  3205:     case 0x1: {
  OPC_Decode, 245, 19, 7,                    //  3207:      decode to VSTRIBR_rec using decoder 7
                                             //  3207:     }
  2, 4,                                      //  3211:     case 0x2: {
  OPC_Decode, 247, 19, 7,                    //  3213:      decode to VSTRIHL_rec using decoder 7
                                             //  3213:     }
  3, 0,                                      //  3217:     case 0x3: {
  OPC_Decode, 249, 19, 7,                    //  3219:      decode to VSTRIHR_rec using decoder 7
                                             //  3219:     }
                                             //  3219:     } // switch Inst[20:16]
                                             //  3219:    }
                                             //  3219:    } // switch Inst[0]
                                             //  3219:   }
  17, 8,                                     //  3223:   case 0x11: {
  OPC_CheckField, 0, 1, 0,                   //  3225:    check Inst[0] == 0x0
  OPC_Decode, 238, 19, 3,                    //  3229:    decode to VSRO using decoder 3
                                             //  3229:   }
  19, 12,                                    //  3233:   case 0x13: {
  OPC_CheckField, 19, 2, 0,                  //  3235:    check Inst[20:19] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  3239:    check Inst[0] == 0x0
  OPC_Decode, 187, 18, 24,                   //  3243:    decode to VGNB using decoder 24
                                             //  3243:   }
  20, 12,                                    //  3247:   case 0x14: {
  OPC_CheckField, 16, 5, 0,                  //  3249:    check Inst[20:16] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  3253:    check Inst[0] == 0x0
  OPC_Decode, 186, 18, 7,                    //  3257:    decode to VGBBD using decoder 7
                                             //  3257:   }
  21, 15,                                    //  3261:   case 0x15: {
  OPC_SwitchField, 0, 1,                     //  3263:    switch Inst[0] {
  0, 4,                                      //  3266:    case 0x0: {
  OPC_Decode, 179, 17, 3,                    //  3268:     decode to VBPERMQ using decoder 3
                                             //  3268:    }
  1, 0,                                      //  3272:    case 0x1: {
  OPC_Decode, 182, 17, 3,                    //  3274:     decode to VCFUGED using decoder 3
                                             //  3274:    }
                                             //  3274:    } // switch Inst[0]
                                             //  3274:   }
  22, 8,                                     //  3278:   case 0x16: {
  OPC_CheckField, 0, 1, 1,                   //  3280:    check Inst[0] == 0x1
  OPC_Decode, 164, 19, 3,                    //  3284:    decode to VPEXTD using decoder 3
                                             //  3284:   }
  23, 15,                                    //  3288:   case 0x17: {
  OPC_SwitchField, 0, 1,                     //  3290:    switch Inst[0] {
  0, 4,                                      //  3293:    case 0x0: {
  OPC_Decode, 178, 17, 3,                    //  3295:     decode to VBPERMD using decoder 3
                                             //  3295:    }
  1, 0,                                      //  3299:    case 0x1: {
  OPC_Decode, 160, 19, 3,                    //  3301:     decode to VPDEPD using decoder 3
                                             //  3301:    }
                                             //  3301:    } // switch Inst[0]
                                             //  3301:   }
  24, 8,                                     //  3305:   case 0x18: {
  OPC_CheckField, 0, 1, 1,                   //  3307:    check Inst[0] == 0x1
  OPC_Decode, 180, 18, 25,                   //  3311:    decode to VEXTUBLX using decoder 25
                                             //  3311:   }
  25, 8,                                     //  3315:   case 0x19: {
  OPC_CheckField, 0, 1, 1,                   //  3317:    check Inst[0] == 0x1
  OPC_Decode, 182, 18, 25,                   //  3321:    decode to VEXTUHLX using decoder 25
                                             //  3321:   }
  26, 15,                                    //  3325:   case 0x1a: {
  OPC_SwitchField, 0, 1,                     //  3327:    switch Inst[0] {
  0, 4,                                      //  3330:    case 0x0: {
  OPC_Decode, 244, 18, 3,                    //  3332:     decode to VMRGOW using decoder 3
                                             //  3332:    }
  1, 0,                                      //  3336:    case 0x1: {
  OPC_Decode, 184, 18, 25,                   //  3338:     decode to VEXTUWLX using decoder 25
                                             //  3338:    }
                                             //  3338:    } // switch Inst[0]
                                             //  3338:   }
  28, 8,                                     //  3342:   case 0x1c: {
  OPC_CheckField, 0, 1, 1,                   //  3344:    check Inst[0] == 0x1
  OPC_Decode, 181, 18, 25,                   //  3348:    decode to VEXTUBRX using decoder 25
                                             //  3348:   }
  29, 8,                                     //  3352:   case 0x1d: {
  OPC_CheckField, 0, 1, 1,                   //  3354:    check Inst[0] == 0x1
  OPC_Decode, 183, 18, 25,                   //  3358:    decode to VEXTUHRX using decoder 25
                                             //  3358:   }
  30, 0,                                     //  3362:   case 0x1e: {
  OPC_SwitchField, 0, 1,                     //  3364:    switch Inst[0] {
  0, 4,                                      //  3367:    case 0x0: {
  OPC_Decode, 237, 18, 3,                    //  3369:     decode to VMRGEW using decoder 3
                                             //  3369:    }
  1, 0,                                      //  3373:    case 0x1: {
  OPC_Decode, 185, 18, 25,                   //  3375:     decode to VEXTUWRX using decoder 25
                                             //  3375:    }
                                             //  3375:    } // switch Inst[0]
                                             //  3375:   }
                                             //  3375:   } // switch Inst[10:6]
                                             //  3375:  }
  7, 232, 2,                                 //  3379:  case 0x7: {
  OPC_SwitchField, 6, 5,                     //  3382:   switch Inst[10:6] {
  0, 15,                                     //  3385:   case 0x0: {
  OPC_SwitchField, 0, 1,                     //  3387:    switch Inst[0] {
  0, 4,                                      //  3390:    case 0x0: {
  OPC_Decode, 174, 19, 3,                    //  3392:     decode to VPKUHUM using decoder 3
                                             //  3392:    }
  1, 0,                                      //  3396:    case 0x1: {
  OPC_Decode, 190, 18, 26,                   //  3398:     decode to VINSBVLX using decoder 26
                                             //  3398:    }
                                             //  3398:    } // switch Inst[0]
                                             //  3398:   }
  1, 15,                                     //  3402:   case 0x1: {
  OPC_SwitchField, 0, 1,                     //  3404:    switch Inst[0] {
  0, 4,                                      //  3407:    case 0x0: {
  OPC_Decode, 176, 19, 3,                    //  3409:     decode to VPKUWUM using decoder 3
                                             //  3409:    }
  1, 0,                                      //  3413:    case 0x1: {
  OPC_Decode, 201, 18, 26,                   //  3415:     decode to VINSHVLX using decoder 26
                                             //  3415:    }
                                             //  3415:    } // switch Inst[0]
                                             //  3415:   }
  2, 15,                                     //  3419:   case 0x2: {
  OPC_SwitchField, 0, 1,                     //  3421:    switch Inst[0] {
  0, 4,                                      //  3424:    case 0x0: {
  OPC_Decode, 175, 19, 3,                    //  3426:     decode to VPKUHUS using decoder 3
                                             //  3426:    }
  1, 0,                                      //  3430:    case 0x1: {
  OPC_Decode, 206, 18, 26,                   //  3432:     decode to VINSWVLX using decoder 26
                                             //  3432:    }
                                             //  3432:    } // switch Inst[0]
                                             //  3432:   }
  3, 15,                                     //  3436:   case 0x3: {
  OPC_SwitchField, 0, 1,                     //  3438:    switch Inst[0] {
  0, 4,                                      //  3441:    case 0x0: {
  OPC_Decode, 177, 19, 3,                    //  3443:     decode to VPKUWUS using decoder 3
                                             //  3443:    }
  1, 0,                                      //  3447:    case 0x1: {
  OPC_Decode, 203, 18, 27,                   //  3449:     decode to VINSW using decoder 27
                                             //  3449:    }
                                             //  3449:    } // switch Inst[0]
                                             //  3449:   }
  4, 15,                                     //  3453:   case 0x4: {
  OPC_SwitchField, 0, 1,                     //  3455:    switch Inst[0] {
  0, 4,                                      //  3458:    case 0x0: {
  OPC_Decode, 169, 19, 3,                    //  3460:     decode to VPKSHUS using decoder 3
                                             //  3460:    }
  1, 0,                                      //  3464:    case 0x1: {
  OPC_Decode, 191, 18, 26,                   //  3466:     decode to VINSBVRX using decoder 26
                                             //  3466:    }
                                             //  3466:    } // switch Inst[0]
                                             //  3466:   }
  5, 15,                                     //  3470:   case 0x5: {
  OPC_SwitchField, 0, 1,                     //  3472:    switch Inst[0] {
  0, 4,                                      //  3475:    case 0x0: {
  OPC_Decode, 171, 19, 3,                    //  3477:     decode to VPKSWUS using decoder 3
                                             //  3477:    }
  1, 0,                                      //  3481:    case 0x1: {
  OPC_Decode, 202, 18, 26,                   //  3483:     decode to VINSHVRX using decoder 26
                                             //  3483:    }
                                             //  3483:    } // switch Inst[0]
                                             //  3483:   }
  6, 15,                                     //  3487:   case 0x6: {
  OPC_SwitchField, 0, 1,                     //  3489:    switch Inst[0] {
  0, 4,                                      //  3492:    case 0x0: {
  OPC_Decode, 168, 19, 3,                    //  3494:     decode to VPKSHSS using decoder 3
                                             //  3494:    }
  1, 0,                                      //  3498:    case 0x1: {
  OPC_Decode, 207, 18, 26,                   //  3500:     decode to VINSWVRX using decoder 26
                                             //  3500:    }
                                             //  3500:    } // switch Inst[0]
                                             //  3500:   }
  7, 15,                                     //  3504:   case 0x7: {
  OPC_SwitchField, 0, 1,                     //  3506:    switch Inst[0] {
  0, 4,                                      //  3509:    case 0x0: {
  OPC_Decode, 170, 19, 3,                    //  3511:     decode to VPKSWSS using decoder 3
                                             //  3511:    }
  1, 0,                                      //  3515:    case 0x1: {
  OPC_Decode, 192, 18, 28,                   //  3517:     decode to VINSD using decoder 28
                                             //  3517:    }
                                             //  3517:    } // switch Inst[0]
                                             //  3517:   }
  8, 19,                                     //  3521:   case 0x8: {
  OPC_SwitchField, 0, 1,                     //  3523:    switch Inst[0] {
  0, 8,                                      //  3526:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  //  3528:     check Inst[20:16] == 0x0
  OPC_Decode, 150, 20, 7,                    //  3532:     decode to VUPKHSB using decoder 7
                                             //  3532:    }
  1, 0,                                      //  3536:    case 0x1: {
  OPC_Decode, 188, 18, 29,                   //  3538:     decode to VINSBLX using decoder 29
                                             //  3538:    }
                                             //  3538:    } // switch Inst[0]
                                             //  3538:   }
  9, 19,                                     //  3542:   case 0x9: {
  OPC_SwitchField, 0, 1,                     //  3544:    switch Inst[0] {
  0, 8,                                      //  3547:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  //  3549:     check Inst[20:16] == 0x0
  OPC_Decode, 151, 20, 7,                    //  3553:     decode to VUPKHSH using decoder 7
                                             //  3553:    }
  1, 0,                                      //  3557:    case 0x1: {
  OPC_Decode, 199, 18, 29,                   //  3559:     decode to VINSHLX using decoder 29
                                             //  3559:    }
                                             //  3559:    } // switch Inst[0]
                                             //  3559:   }
  10, 19,                                    //  3563:   case 0xa: {
  OPC_SwitchField, 0, 1,                     //  3565:    switch Inst[0] {
  0, 8,                                      //  3568:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  //  3570:     check Inst[20:16] == 0x0
  OPC_Decode, 159, 20, 7,                    //  3574:     decode to VUPKLSB using decoder 7
                                             //  3574:    }
  1, 0,                                      //  3578:    case 0x1: {
  OPC_Decode, 204, 18, 29,                   //  3580:     decode to VINSWLX using decoder 29
                                             //  3580:    }
                                             //  3580:    } // switch Inst[0]
                                             //  3580:   }
  11, 19,                                    //  3584:   case 0xb: {
  OPC_SwitchField, 0, 1,                     //  3586:    switch Inst[0] {
  0, 8,                                      //  3589:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  //  3591:     check Inst[20:16] == 0x0
  OPC_Decode, 160, 20, 7,                    //  3595:     decode to VUPKLSH using decoder 7
                                             //  3595:    }
  1, 0,                                      //  3599:    case 0x1: {
  OPC_Decode, 193, 18, 30,                   //  3601:     decode to VINSDLX using decoder 30
                                             //  3601:    }
                                             //  3601:    } // switch Inst[0]
                                             //  3601:   }
  12, 15,                                    //  3605:   case 0xc: {
  OPC_SwitchField, 0, 1,                     //  3607:    switch Inst[0] {
  0, 4,                                      //  3610:    case 0x0: {
  OPC_Decode, 165, 19, 3,                    //  3612:     decode to VPKPX using decoder 3
                                             //  3612:    }
  1, 0,                                      //  3616:    case 0x1: {
  OPC_Decode, 189, 18, 29,                   //  3618:     decode to VINSBRX using decoder 29
                                             //  3618:    }
                                             //  3618:    } // switch Inst[0]
                                             //  3618:   }
  13, 19,                                    //  3622:   case 0xd: {
  OPC_SwitchField, 0, 1,                     //  3624:    switch Inst[0] {
  0, 8,                                      //  3627:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  //  3629:     check Inst[20:16] == 0x0
  OPC_Decode, 149, 20, 7,                    //  3633:     decode to VUPKHPX using decoder 7
                                             //  3633:    }
  1, 0,                                      //  3637:    case 0x1: {
  OPC_Decode, 200, 18, 29,                   //  3639:     decode to VINSHRX using decoder 29
                                             //  3639:    }
                                             //  3639:    } // switch Inst[0]
                                             //  3639:   }
  14, 8,                                     //  3643:   case 0xe: {
  OPC_CheckField, 0, 1, 1,                   //  3645:    check Inst[0] == 0x1
  OPC_Decode, 205, 18, 29,                   //  3649:    decode to VINSWRX using decoder 29
                                             //  3649:   }
  15, 19,                                    //  3653:   case 0xf: {
  OPC_SwitchField, 0, 1,                     //  3655:    switch Inst[0] {
  0, 8,                                      //  3658:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  //  3660:     check Inst[20:16] == 0x0
  OPC_Decode, 158, 20, 7,                    //  3664:     decode to VUPKLPX using decoder 7
                                             //  3664:    }
  1, 0,                                      //  3668:    case 0x1: {
  OPC_Decode, 194, 18, 30,                   //  3670:     decode to VINSDRX using decoder 30
                                             //  3670:    }
                                             //  3670:    } // switch Inst[0]
                                             //  3670:   }
  17, 8,                                     //  3674:   case 0x11: {
  OPC_CheckField, 0, 1, 0,                   //  3676:    check Inst[0] == 0x0
  OPC_Decode, 172, 19, 3,                    //  3680:    decode to VPKUDUM using decoder 3
                                             //  3680:   }
  19, 8,                                     //  3684:   case 0x13: {
  OPC_CheckField, 0, 1, 0,                   //  3686:    check Inst[0] == 0x0
  OPC_Decode, 173, 19, 3,                    //  3690:    decode to VPKUDUS using decoder 3
                                             //  3690:   }
  21, 8,                                     //  3694:   case 0x15: {
  OPC_CheckField, 0, 1, 0,                   //  3696:    check Inst[0] == 0x0
  OPC_Decode, 167, 19, 3,                    //  3700:    decode to VPKSDUS using decoder 3
                                             //  3700:   }
  23, 8,                                     //  3704:   case 0x17: {
  OPC_CheckField, 0, 1, 0,                   //  3706:    check Inst[0] == 0x0
  OPC_Decode, 166, 19, 3,                    //  3710:    decode to VPKSDSS using decoder 3
                                             //  3710:   }
  25, 12,                                    //  3714:   case 0x19: {
  OPC_CheckField, 16, 5, 0,                  //  3716:    check Inst[20:16] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  3720:    check Inst[0] == 0x0
  OPC_Decode, 153, 20, 7,                    //  3724:    decode to VUPKHSW using decoder 7
                                             //  3724:   }
  27, 0,                                     //  3728:   case 0x1b: {
  OPC_CheckField, 16, 5, 0,                  //  3730:    check Inst[20:16] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  3734:    check Inst[0] == 0x0
  OPC_Decode, 162, 20, 7,                    //  3738:    decode to VUPKLSW using decoder 7
                                             //  3738:   }
                                             //  3738:   } // switch Inst[10:6]
                                             //  3738:  }
  10, 4,                                     //  3742:  case 0xa: {
  OPC_Decode, 167, 12, 31,                   //  3744:   decode to MTVSRBMI using decoder 31
                                             //  3744:  }
  11, 26,                                    //  3748:  case 0xb: {
  OPC_SwitchField, 0, 1,                     //  3750:   switch Inst[0] {
  0, 15,                                     //  3753:   case 0x0: {
  OPC_SwitchField, 9, 2,                     //  3755:    switch Inst[10:9] {
  0, 4,                                      //  3758:    case 0x0: {
  OPC_Decode, 213, 19, 32,                   //  3760:     decode to VSLDBI using decoder 32
                                             //  3760:    }
  1, 0,                                      //  3764:    case 0x1: {
  OPC_Decode, 236, 19, 32,                   //  3766:     decode to VSRDBI using decoder 32
                                             //  3766:    }
                                             //  3766:    } // switch Inst[10:9]
                                             //  3766:   }
  1, 0,                                      //  3770:   case 0x1: {
  OPC_Decode, 245, 18, 33,                   //  3772:    decode to VMSUMCUD using decoder 33
                                             //  3772:   }
                                             //  3772:   } // switch Inst[0]
                                             //  3772:  }
  12, 15,                                    //  3776:  case 0xc: {
  OPC_SwitchField, 0, 1,                     //  3778:   switch Inst[0] {
  0, 4,                                      //  3781:   case 0x0: {
  OPC_Decode, 154, 18, 34,                   //  3783:    decode to VEXTDUBVLX using decoder 34
                                             //  3783:   }
  1, 0,                                      //  3787:   case 0x1: {
  OPC_Decode, 155, 18, 34,                   //  3789:    decode to VEXTDUBVRX using decoder 34
                                             //  3789:   }
                                             //  3789:   } // switch Inst[0]
                                             //  3789:  }
  13, 15,                                    //  3793:  case 0xd: {
  OPC_SwitchField, 0, 1,                     //  3795:   switch Inst[0] {
  0, 4,                                      //  3798:   case 0x0: {
  OPC_Decode, 156, 18, 34,                   //  3800:    decode to VEXTDUHVLX using decoder 34
                                             //  3800:   }
  1, 0,                                      //  3804:   case 0x1: {
  OPC_Decode, 157, 18, 34,                   //  3806:    decode to VEXTDUHVRX using decoder 34
                                             //  3806:   }
                                             //  3806:   } // switch Inst[0]
                                             //  3806:  }
  14, 15,                                    //  3810:  case 0xe: {
  OPC_SwitchField, 0, 1,                     //  3812:   switch Inst[0] {
  0, 4,                                      //  3815:   case 0x0: {
  OPC_Decode, 158, 18, 34,                   //  3817:    decode to VEXTDUWVLX using decoder 34
                                             //  3817:   }
  1, 0,                                      //  3821:   case 0x1: {
  OPC_Decode, 159, 18, 34,                   //  3823:    decode to VEXTDUWVRX using decoder 34
                                             //  3823:   }
                                             //  3823:   } // switch Inst[0]
                                             //  3823:  }
  15, 15,                                    //  3827:  case 0xf: {
  OPC_SwitchField, 0, 1,                     //  3829:   switch Inst[0] {
  0, 4,                                      //  3832:   case 0x0: {
  OPC_Decode, 152, 18, 34,                   //  3834:    decode to VEXTDDVLX using decoder 34
                                             //  3834:   }
  1, 0,                                      //  3838:   case 0x1: {
  OPC_Decode, 153, 18, 34,                   //  3840:    decode to VEXTDDVRX using decoder 34
                                             //  3840:   }
                                             //  3840:   } // switch Inst[0]
                                             //  3840:  }
  16, 15,                                    //  3844:  case 0x10: {
  OPC_SwitchField, 0, 1,                     //  3846:   switch Inst[0] {
  0, 4,                                      //  3849:   case 0x0: {
  OPC_Decode, 219, 18, 33,                   //  3851:    decode to VMHADDSHS using decoder 33
                                             //  3851:   }
  1, 0,                                      //  3855:   case 0x1: {
  OPC_Decode, 220, 18, 33,                   //  3857:    decode to VMHRADDSHS using decoder 33
                                             //  3857:   }
                                             //  3857:   } // switch Inst[0]
                                             //  3857:  }
  17, 15,                                    //  3861:  case 0x11: {
  OPC_SwitchField, 0, 1,                     //  3863:   switch Inst[0] {
  0, 4,                                      //  3866:   case 0x0: {
  OPC_Decode, 230, 18, 33,                   //  3868:    decode to VMLADDUHM using decoder 33
                                             //  3868:   }
  1, 0,                                      //  3872:   case 0x1: {
  OPC_Decode, 250, 18, 33,                   //  3874:    decode to VMSUMUDM using decoder 33
                                             //  3874:   }
                                             //  3874:   } // switch Inst[0]
                                             //  3874:  }
  18, 15,                                    //  3878:  case 0x12: {
  OPC_SwitchField, 0, 1,                     //  3880:   switch Inst[0] {
  0, 4,                                      //  3883:   case 0x0: {
  OPC_Decode, 249, 18, 33,                   //  3885:    decode to VMSUMUBM using decoder 33
                                             //  3885:   }
  1, 0,                                      //  3889:   case 0x1: {
  OPC_Decode, 246, 18, 33,                   //  3891:    decode to VMSUMMBM using decoder 33
                                             //  3891:   }
                                             //  3891:   } // switch Inst[0]
                                             //  3891:  }
  19, 15,                                    //  3895:  case 0x13: {
  OPC_SwitchField, 0, 1,                     //  3897:   switch Inst[0] {
  0, 4,                                      //  3900:   case 0x0: {
  OPC_Decode, 251, 18, 33,                   //  3902:    decode to VMSUMUHM using decoder 33
                                             //  3902:   }
  1, 0,                                      //  3906:   case 0x1: {
  OPC_Decode, 252, 18, 33,                   //  3908:    decode to VMSUMUHS using decoder 33
                                             //  3908:   }
                                             //  3908:   } // switch Inst[0]
                                             //  3908:  }
  20, 15,                                    //  3912:  case 0x14: {
  OPC_SwitchField, 0, 1,                     //  3914:   switch Inst[0] {
  0, 4,                                      //  3917:   case 0x0: {
  OPC_Decode, 247, 18, 33,                   //  3919:    decode to VMSUMSHM using decoder 33
                                             //  3919:   }
  1, 0,                                      //  3923:   case 0x1: {
  OPC_Decode, 248, 18, 33,                   //  3925:    decode to VMSUMSHS using decoder 33
                                             //  3925:   }
                                             //  3925:   } // switch Inst[0]
                                             //  3925:  }
  21, 15,                                    //  3929:  case 0x15: {
  OPC_SwitchField, 0, 1,                     //  3931:   switch Inst[0] {
  0, 4,                                      //  3934:   case 0x0: {
  OPC_Decode, 207, 19, 33,                   //  3936:    decode to VSEL using decoder 33
                                             //  3936:   }
  1, 0,                                      //  3940:   case 0x1: {
  OPC_Decode, 161, 19, 33,                   //  3942:    decode to VPERM using decoder 33
                                             //  3942:   }
                                             //  3942:   } // switch Inst[0]
                                             //  3942:  }
  22, 19,                                    //  3946:  case 0x16: {
  OPC_SwitchField, 0, 1,                     //  3948:   switch Inst[0] {
  0, 8,                                      //  3951:   case 0x0: {
  OPC_CheckField, 10, 1, 0,                  //  3953:    check Inst[10] == 0x0
  OPC_Decode, 214, 19, 35,                   //  3957:    decode to VSLDOI using decoder 35
                                             //  3957:   }
  1, 0,                                      //  3961:   case 0x1: {
  OPC_Decode, 163, 19, 33,                   //  3963:    decode to VPERMXOR using decoder 33
                                             //  3963:   }
                                             //  3963:   } // switch Inst[0]
                                             //  3963:  }
  23, 15,                                    //  3967:  case 0x17: {
  OPC_SwitchField, 0, 1,                     //  3969:   switch Inst[0] {
  0, 4,                                      //  3972:   case 0x0: {
  OPC_Decode, 209, 18, 36,                   //  3974:    decode to VMADDFP using decoder 36
                                             //  3974:   }
  1, 0,                                      //  3978:   case 0x1: {
  OPC_Decode, 156, 19, 36,                   //  3980:    decode to VNMSUBFP using decoder 36
                                             //  3980:   }
                                             //  3980:   } // switch Inst[0]
                                             //  3980:  }
  24, 15,                                    //  3984:  case 0x18: {
  OPC_SwitchField, 0, 1,                     //  3986:   switch Inst[0] {
  0, 4,                                      //  3989:   case 0x0: {
  OPC_Decode, 210, 11, 37,                   //  3991:    decode to MADDHD using decoder 37
                                             //  3991:   }
  1, 0,                                      //  3995:   case 0x1: {
  OPC_Decode, 211, 11, 37,                   //  3997:    decode to MADDHDU using decoder 37
                                             //  3997:   }
                                             //  3997:   } // switch Inst[0]
                                             //  3997:  }
  25, 8,                                     //  4001:  case 0x19: {
  OPC_CheckField, 0, 1, 1,                   //  4003:   check Inst[0] == 0x1
  OPC_Decode, 212, 11, 38,                   //  4007:   decode to MADDLD using decoder 38
                                             //  4007:  }
  29, 8,                                     //  4011:  case 0x1d: {
  OPC_CheckField, 0, 1, 1,                   //  4013:   check Inst[0] == 0x1
  OPC_Decode, 162, 19, 33,                   //  4017:   decode to VPERMR using decoder 33
                                             //  4017:  }
  30, 15,                                    //  4021:  case 0x1e: {
  OPC_SwitchField, 0, 1,                     //  4023:   switch Inst[0] {
  0, 4,                                      //  4026:   case 0x0: {
  OPC_Decode, 157, 17, 33,                   //  4028:    decode to VADDEUQM using decoder 33
                                             //  4028:   }
  1, 0,                                      //  4032:   case 0x1: {
  OPC_Decode, 156, 17, 33,                   //  4034:    decode to VADDECUQ using decoder 33
                                             //  4034:   }
                                             //  4034:   } // switch Inst[0]
                                             //  4034:  }
  31, 0,                                     //  4038:  case 0x1f: {
  OPC_SwitchField, 0, 1,                     //  4040:   switch Inst[0] {
  0, 4,                                      //  4043:   case 0x0: {
  OPC_Decode, 253, 19, 33,                   //  4045:    decode to VSUBEUQM using decoder 33
                                             //  4045:   }
  1, 0,                                      //  4049:   case 0x1: {
  OPC_Decode, 252, 19, 33,                   //  4051:    decode to VSUBECUQ using decoder 33
                                             //  4051:   }
                                             //  4051:   } // switch Inst[0]
                                             //  4051:  }
                                             //  4051:  } // switch Inst[5:1]
                                             //  4051: }
  6, 15,                                     //  4055: case 0x6: {
  OPC_SwitchField, 0, 4,                     //  4057:  switch Inst[3:0] {
  0, 4,                                      //  4060:  case 0x0: {
  OPC_Decode, 196, 11, 39,                   //  4062:   decode to LXVP using decoder 39
                                             //  4062:  }
  1, 0,                                      //  4066:  case 0x1: {
  OPC_Decode, 163, 16, 39,                   //  4068:   decode to STXVP using decoder 39
                                             //  4068:  }
                                             //  4068:  } // switch Inst[3:0]
                                             //  4068: }
  7, 4,                                      //  4072: case 0x7: {
  OPC_Decode, 189, 12, 40,                   //  4074:  decode to MULLI using decoder 40
                                             //  4074: }
  8, 4,                                      //  4078: case 0x8: {
  OPC_Decode, 197, 16, 40,                   //  4080:  decode to SUBFIC using decoder 40
                                             //  4080: }
  10, 15,                                    //  4084: case 0xa: {
  OPC_SwitchField, 21, 2,                    //  4086:  switch Inst[22:21] {
  0, 4,                                      //  4089:  case 0x0: {
  OPC_Decode, 181, 5, 41,                    //  4091:   decode to CMPLWI using decoder 41
                                             //  4091:  }
  1, 0,                                      //  4095:  case 0x1: {
  OPC_Decode, 179, 5, 42,                    //  4097:   decode to CMPLDI using decoder 42
                                             //  4097:  }
                                             //  4097:  } // switch Inst[22:21]
                                             //  4097: }
  11, 15,                                    //  4101: case 0xb: {
  OPC_SwitchField, 21, 2,                    //  4103:  switch Inst[22:21] {
  0, 4,                                      //  4106:  case 0x0: {
  OPC_Decode, 185, 5, 43,                    //  4108:   decode to CMPWI using decoder 43
                                             //  4108:  }
  1, 0,                                      //  4112:  case 0x1: {
  OPC_Decode, 176, 5, 44,                    //  4114:   decode to CMPDI using decoder 44
                                             //  4114:  }
                                             //  4114:  } // switch Inst[22:21]
                                             //  4114: }
  12, 4,                                     //  4118: case 0xc: {
  OPC_Decode, 188, 3, 40,                    //  4120:  decode to ADDIC using decoder 40
                                             //  4120: }
  13, 4,                                     //  4124: case 0xd: {
  OPC_Decode, 190, 3, 40,                    //  4126:  decode to ADDIC_rec using decoder 40
                                             //  4126: }
  14, 14,                                    //  4130: case 0xe: {
  OPC_Scope, 8,                              //  4132:  try {
  OPC_CheckField, 16, 5, 0,                  //  4134:   check Inst[20:16] == 0x0
  OPC_Decode, 134, 11, 45,                   //  4138:   decode to LI using decoder 45
                                             //  4138:  } else try {
  OPC_Decode, 186, 3, 46,                    //  4142:   decode to ADDI using decoder 46
                                             //  4142:  }
                                             //  4142: }
  15, 14,                                    //  4146: case 0xf: {
  OPC_Scope, 8,                              //  4148:  try {
  OPC_CheckField, 16, 5, 0,                  //  4150:   check Inst[20:16] == 0x0
  OPC_Decode, 136, 11, 45,                   //  4154:   decode to LIS using decoder 45
                                             //  4154:  } else try {
  OPC_Decode, 191, 3, 46,                    //  4158:   decode to ADDIS using decoder 46
                                             //  4158:  }
                                             //  4158: }
  16, 215, 1,                                //  4162: case 0x10: {
  OPC_SwitchField, 0, 2,                     //  4165:  switch Inst[1:0] {
  0, 51,                                     //  4168:  case 0x0: {
  OPC_Scope, 45,                             //  4170:   try {
  OPC_SwitchField, 16, 10,                   //  4172:    switch Inst[25:16] {
  128, 4, 4,                                 //  4175:    case 0x200: {
  OPC_Decode, 224, 4, 47,                    //  4178:     decode to BDNZ using decoder 47
                                             //  4178:    }
  192, 4, 4,                                 //  4182:    case 0x240: {
  OPC_Decode, 244, 4, 47,                    //  4185:     decode to BDZ using decoder 47
                                             //  4185:    }
  128, 6, 4,                                 //  4189:    case 0x300: {
  OPC_Decode, 242, 4, 47,                    //  4192:     decode to BDNZm using decoder 47
                                             //  4192:    }
  160, 6, 4,                                 //  4196:    case 0x320: {
  OPC_Decode, 243, 4, 47,                    //  4199:     decode to BDNZp using decoder 47
                                             //  4199:    }
  192, 6, 4,                                 //  4203:    case 0x340: {
  OPC_Decode, 134, 5, 47,                    //  4206:     decode to BDZm using decoder 47
                                             //  4206:    }
  224, 6, 0,                                 //  4210:    case 0x360: {
  OPC_Decode, 135, 5, 47,                    //  4213:     decode to BDZp using decoder 47
                                             //  4213:    }
                                             //  4213:    } // switch Inst[25:16]
                                             //  4213:   } else try {
  OPC_Decode, 168, 23, 48,                   //  4217:    decode to gBC using decoder 48
                                             //  4217:   }
                                             //  4217:  }
  1, 51,                                     //  4221:  case 0x1: {
  OPC_Scope, 45,                             //  4223:   try {
  OPC_SwitchField, 16, 10,                   //  4225:    switch Inst[25:16] {
  128, 4, 4,                                 //  4228:    case 0x200: {
  OPC_Decode, 229, 4, 47,                    //  4231:     decode to BDNZL using decoder 47
                                             //  4231:    }
  192, 4, 4,                                 //  4235:    case 0x240: {
  OPC_Decode, 249, 4, 47,                    //  4238:     decode to BDZL using decoder 47
                                             //  4238:    }
  128, 6, 4,                                 //  4242:    case 0x300: {
  OPC_Decode, 240, 4, 47,                    //  4245:     decode to BDNZLm using decoder 47
                                             //  4245:    }
  160, 6, 4,                                 //  4249:    case 0x320: {
  OPC_Decode, 241, 4, 47,                    //  4252:     decode to BDNZLp using decoder 47
                                             //  4252:    }
  192, 6, 4,                                 //  4256:    case 0x340: {
  OPC_Decode, 132, 5, 47,                    //  4259:     decode to BDZLm using decoder 47
                                             //  4259:    }
  224, 6, 0,                                 //  4263:    case 0x360: {
  OPC_Decode, 133, 5, 47,                    //  4266:     decode to BDZLp using decoder 47
                                             //  4266:    }
                                             //  4266:    } // switch Inst[25:16]
                                             //  4266:   } else try {
  OPC_Decode, 173, 23, 48,                   //  4270:    decode to gBCL using decoder 48
                                             //  4270:   }
                                             //  4270:  }
  2, 51,                                     //  4274:  case 0x2: {
  OPC_Scope, 45,                             //  4276:   try {
  OPC_SwitchField, 16, 10,                   //  4278:    switch Inst[25:16] {
  128, 4, 4,                                 //  4281:    case 0x200: {
  OPC_Decode, 226, 4, 47,                    //  4284:     decode to BDNZA using decoder 47
                                             //  4284:    }
  192, 4, 4,                                 //  4288:    case 0x240: {
  OPC_Decode, 246, 4, 47,                    //  4291:     decode to BDZA using decoder 47
                                             //  4291:    }
  128, 6, 4,                                 //  4295:    case 0x300: {
  OPC_Decode, 227, 4, 47,                    //  4298:     decode to BDNZAm using decoder 47
                                             //  4298:    }
  160, 6, 4,                                 //  4302:    case 0x320: {
  OPC_Decode, 228, 4, 47,                    //  4305:     decode to BDNZAp using decoder 47
                                             //  4305:    }
  192, 6, 4,                                 //  4309:    case 0x340: {
  OPC_Decode, 247, 4, 47,                    //  4312:     decode to BDZAm using decoder 47
                                             //  4312:    }
  224, 6, 0,                                 //  4316:    case 0x360: {
  OPC_Decode, 248, 4, 47,                    //  4319:     decode to BDZAp using decoder 47
                                             //  4319:    }
                                             //  4319:    } // switch Inst[25:16]
                                             //  4319:   } else try {
  OPC_Decode, 169, 23, 48,                   //  4323:    decode to gBCA using decoder 48
                                             //  4323:   }
                                             //  4323:  }
  3, 0,                                      //  4327:  case 0x3: {
  OPC_Scope, 45,                             //  4329:   try {
  OPC_SwitchField, 16, 10,                   //  4331:    switch Inst[25:16] {
  128, 4, 4,                                 //  4334:    case 0x200: {
  OPC_Decode, 230, 4, 47,                    //  4337:     decode to BDNZLA using decoder 47
                                             //  4337:    }
  192, 4, 4,                                 //  4341:    case 0x240: {
  OPC_Decode, 250, 4, 47,                    //  4344:     decode to BDZLA using decoder 47
                                             //  4344:    }
  128, 6, 4,                                 //  4348:    case 0x300: {
  OPC_Decode, 231, 4, 47,                    //  4351:     decode to BDNZLAm using decoder 47
                                             //  4351:    }
  160, 6, 4,                                 //  4355:    case 0x320: {
  OPC_Decode, 232, 4, 47,                    //  4358:     decode to BDNZLAp using decoder 47
                                             //  4358:    }
  192, 6, 4,                                 //  4362:    case 0x340: {
  OPC_Decode, 251, 4, 47,                    //  4365:     decode to BDZLAm using decoder 47
                                             //  4365:    }
  224, 6, 0,                                 //  4369:    case 0x360: {
  OPC_Decode, 252, 4, 47,                    //  4372:     decode to BDZLAp using decoder 47
                                             //  4372:    }
                                             //  4372:    } // switch Inst[25:16]
                                             //  4372:   } else try {
  OPC_Decode, 174, 23, 48,                   //  4376:    decode to gBCLA using decoder 48
                                             //  4376:   }
                                             //  4376:  }
                                             //  4376:  } // switch Inst[1:0]
                                             //  4376: }
  17, 15,                                    //  4380: case 0x11: {
  OPC_SwitchField, 0, 2,                     //  4382:  switch Inst[1:0] {
  1, 4,                                      //  4385:  case 0x1: {
  OPC_Decode, 242, 14, 49,                   //  4387:   decode to SCV using decoder 49
                                             //  4387:  }
  2, 0,                                      //  4391:  case 0x2: {
  OPC_Decode, 241, 14, 49,                   //  4393:   decode to SC using decoder 49
                                             //  4393:  }
                                             //  4393:  } // switch Inst[1:0]
                                             //  4393: }
  18, 27,                                    //  4397: case 0x12: {
  OPC_SwitchField, 0, 2,                     //  4399:  switch Inst[1:0] {
  0, 4,                                      //  4402:  case 0x0: {
  OPC_Decode, 170, 4, 50,                    //  4404:   decode to B using decoder 50
                                             //  4404:  }
  1, 4,                                      //  4408:  case 0x1: {
  OPC_Decode, 136, 5, 50,                    //  4410:   decode to BL using decoder 50
                                             //  4410:  }
  2, 4,                                      //  4414:  case 0x2: {
  OPC_Decode, 171, 4, 50,                    //  4416:   decode to BA using decoder 50
                                             //  4416:  }
  3, 0,                                      //  4420:  case 0x3: {
  OPC_Decode, 147, 5, 50,                    //  4422:   decode to BLA using decoder 50
                                             //  4422:  }
                                             //  4422:  } // switch Inst[1:0]
                                             //  4422: }
  19, 251, 3,                                //  4426: case 0x13: {
  OPC_SwitchField, 1, 5,                     //  4429:  switch Inst[5:1] {
  0, 16,                                     //  4432:  case 0x0: {
  OPC_CheckField, 21, 2, 0,                  //  4434:   check Inst[22:21] == 0x0
  OPC_CheckField, 6, 12, 0,                  //  4438:   check Inst[17:6] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  4442:   check Inst[0] == 0x0
  OPC_Decode, 215, 11, 51,                   //  4446:   decode to MCRF using decoder 51
                                             //  4446:  }
  1, 83,                                     //  4450:  case 0x1: {
  OPC_SwitchField, 6, 5,                     //  4452:   switch Inst[10:6] {
  1, 8,                                      //  4455:   case 0x1: {
  OPC_CheckField, 0, 1, 0,                   //  4457:    check Inst[0] == 0x0
  OPC_Decode, 211, 5, 52,                    //  4461:    decode to CRNOR using decoder 52
                                             //  4461:   }
  4, 8,                                      //  4465:   case 0x4: {
  OPC_CheckField, 0, 1, 0,                   //  4467:    check Inst[0] == 0x0
  OPC_Decode, 208, 5, 52,                    //  4471:    decode to CRANDC using decoder 52
                                             //  4471:   }
  6, 8,                                      //  4475:   case 0x6: {
  OPC_CheckField, 0, 1, 0,                   //  4477:    check Inst[0] == 0x0
  OPC_Decode, 217, 5, 52,                    //  4481:    decode to CRXOR using decoder 52
                                             //  4481:   }
  7, 8,                                      //  4485:   case 0x7: {
  OPC_CheckField, 0, 1, 0,                   //  4487:    check Inst[0] == 0x0
  OPC_Decode, 210, 5, 52,                    //  4491:    decode to CRNAND using decoder 52
                                             //  4491:   }
  8, 8,                                      //  4495:   case 0x8: {
  OPC_CheckField, 0, 1, 0,                   //  4497:    check Inst[0] == 0x0
  OPC_Decode, 207, 5, 52,                    //  4501:    decode to CRAND using decoder 52
                                             //  4501:   }
  9, 8,                                      //  4505:   case 0x9: {
  OPC_CheckField, 0, 1, 0,                   //  4507:    check Inst[0] == 0x0
  OPC_Decode, 209, 5, 52,                    //  4511:    decode to CREQV using decoder 52
                                             //  4511:   }
  13, 8,                                     //  4515:   case 0xd: {
  OPC_CheckField, 0, 1, 0,                   //  4517:    check Inst[0] == 0x0
  OPC_Decode, 214, 5, 52,                    //  4521:    decode to CRORC using decoder 52
                                             //  4521:   }
  14, 0,                                     //  4525:   case 0xe: {
  OPC_CheckField, 0, 1, 0,                   //  4527:    check Inst[0] == 0x0
  OPC_Decode, 213, 5, 52,                    //  4531:    decode to CROR using decoder 52
                                             //  4531:   }
                                             //  4531:   } // switch Inst[10:6]
                                             //  4531:  }
  2, 4,                                      //  4535:  case 0x2: {
  OPC_Decode, 222, 3, 53,                    //  4537:   decode to ADDPCIS using decoder 53
                                             //  4537:  }
  6, 12,                                     //  4541:  case 0x6: {
  OPC_CheckField, 6, 20, 1,                  //  4543:   check Inst[25:6] == 0x1
  OPC_CheckField, 0, 1, 0,                   //  4547:   check Inst[0] == 0x0
  OPC_Decode, 211, 14, 0,                    //  4551:   decode to RFMCI using decoder 0
                                             //  4551:  }
  7, 12,                                     //  4555:  case 0x7: {
  OPC_CheckField, 6, 20, 1,                  //  4557:   check Inst[25:6] == 0x1
  OPC_CheckField, 0, 1, 0,                   //  4561:   check Inst[0] == 0x0
  OPC_Decode, 207, 14, 0,                    //  4565:   decode to RFDI using decoder 0
                                             //  4565:  }
  16, 247, 1,                                //  4569:  case 0x10: {
  OPC_SwitchField, 0, 1,                     //  4572:   switch Inst[0] {
  0, 120,                                    //  4575:   case 0x0: {
  OPC_SwitchField, 6, 5,                     //  4577:    switch Inst[10:6] {
  0, 90,                                     //  4580:    case 0x0: {
  OPC_CheckField, 13, 3, 0,                  //  4582:     check Inst[15:13] == 0x0
  OPC_Scope, 80,                             //  4586:     try {
  OPC_SwitchField, 16, 10,                   //  4588:      switch Inst[25:16] {
  128, 4, 8,                                 //  4591:      case 0x200: {
  OPC_CheckField, 11, 2, 0,                  //  4594:       check Inst[12:11] == 0x0
  OPC_Decode, 233, 4, 0,                     //  4598:       decode to BDNZLR using decoder 0
                                             //  4598:      }
  192, 4, 8,                                 //  4602:      case 0x240: {
  OPC_CheckField, 11, 2, 0,                  //  4605:       check Inst[12:11] == 0x0
  OPC_Decode, 253, 4, 0,                     //  4609:       decode to BDZLR using decoder 0
                                             //  4609:      }
  128, 5, 8,                                 //  4613:      case 0x280: {
  OPC_CheckField, 11, 2, 0,                  //  4616:       check Inst[12:11] == 0x0
  OPC_Decode, 153, 5, 0,                     //  4620:       decode to BLR using decoder 0
                                             //  4620:      }
  128, 6, 8,                                 //  4624:      case 0x300: {
  OPC_CheckField, 11, 2, 0,                  //  4627:       check Inst[12:11] == 0x0
  OPC_Decode, 238, 4, 0,                     //  4631:       decode to BDNZLRm using decoder 0
                                             //  4631:      }
  160, 6, 8,                                 //  4635:      case 0x320: {
  OPC_CheckField, 11, 2, 0,                  //  4638:       check Inst[12:11] == 0x0
  OPC_Decode, 239, 4, 0,                     //  4642:       decode to BDNZLRp using decoder 0
                                             //  4642:      }
  192, 6, 8,                                 //  4646:      case 0x340: {
  OPC_CheckField, 11, 2, 0,                  //  4649:       check Inst[12:11] == 0x0
  OPC_Decode, 130, 5, 0,                     //  4653:       decode to BDZLRm using decoder 0
                                             //  4653:      }
  224, 6, 0,                                 //  4657:      case 0x360: {
  OPC_CheckField, 11, 2, 0,                  //  4660:       check Inst[12:11] == 0x0
  OPC_Decode, 131, 5, 0,                     //  4664:       decode to BDZLRp using decoder 0
                                             //  4664:      }
                                             //  4664:      } // switch Inst[25:16]
                                             //  4664:     } else try {
  OPC_Decode, 176, 23, 54,                   //  4668:      decode to gBCLR using decoder 54
                                             //  4668:     }
                                             //  4668:    }
  16, 0,                                     //  4672:    case 0x10: {
  OPC_CheckField, 13, 3, 0,                  //  4674:     check Inst[15:13] == 0x0
  OPC_Scope, 13,                             //  4678:     try {
  OPC_CheckField, 11, 2, 0,                  //  4680:      check Inst[12:11] == 0x0
  OPC_CheckField, 16, 10, 128, 5,            //  4684:      check Inst[25:16] == 0x280
  OPC_Decode, 213, 4, 0,                     //  4689:      decode to BCTR using decoder 0
                                             //  4689:     } else try {
  OPC_Decode, 171, 23, 54,                   //  4693:      decode to gBCCTR using decoder 54
                                             //  4693:     }
                                             //  4693:    }
                                             //  4693:    } // switch Inst[10:6]
                                             //  4693:   }
  1, 0,                                      //  4697:   case 0x1: {
  OPC_SwitchField, 6, 5,                     //  4699:    switch Inst[10:6] {
  0, 90,                                     //  4702:    case 0x0: {
  OPC_CheckField, 13, 3, 0,                  //  4704:     check Inst[15:13] == 0x0
  OPC_Scope, 80,                             //  4708:     try {
  OPC_SwitchField, 16, 10,                   //  4710:      switch Inst[25:16] {
  128, 4, 8,                                 //  4713:      case 0x200: {
  OPC_CheckField, 11, 2, 0,                  //  4716:       check Inst[12:11] == 0x0
  OPC_Decode, 235, 4, 0,                     //  4720:       decode to BDNZLRL using decoder 0
                                             //  4720:      }
  192, 4, 8,                                 //  4724:      case 0x240: {
  OPC_CheckField, 11, 2, 0,                  //  4727:       check Inst[12:11] == 0x0
  OPC_Decode, 255, 4, 0,                     //  4731:       decode to BDZLRL using decoder 0
                                             //  4731:      }
  128, 5, 8,                                 //  4735:      case 0x280: {
  OPC_CheckField, 11, 2, 0,                  //  4738:       check Inst[12:11] == 0x0
  OPC_Decode, 155, 5, 0,                     //  4742:       decode to BLRL using decoder 0
                                             //  4742:      }
  128, 6, 8,                                 //  4746:      case 0x300: {
  OPC_CheckField, 11, 2, 0,                  //  4749:       check Inst[12:11] == 0x0
  OPC_Decode, 236, 4, 0,                     //  4753:       decode to BDNZLRLm using decoder 0
                                             //  4753:      }
  160, 6, 8,                                 //  4757:      case 0x320: {
  OPC_CheckField, 11, 2, 0,                  //  4760:       check Inst[12:11] == 0x0
  OPC_Decode, 237, 4, 0,                     //  4764:       decode to BDNZLRLp using decoder 0
                                             //  4764:      }
  192, 6, 8,                                 //  4768:      case 0x340: {
  OPC_CheckField, 11, 2, 0,                  //  4771:       check Inst[12:11] == 0x0
  OPC_Decode, 128, 5, 0,                     //  4775:       decode to BDZLRLm using decoder 0
                                             //  4775:      }
  224, 6, 0,                                 //  4779:      case 0x360: {
  OPC_CheckField, 11, 2, 0,                  //  4782:       check Inst[12:11] == 0x0
  OPC_Decode, 129, 5, 0,                     //  4786:       decode to BDZLRLp using decoder 0
                                             //  4786:      }
                                             //  4786:      } // switch Inst[25:16]
                                             //  4786:     } else try {
  OPC_Decode, 177, 23, 54,                   //  4790:      decode to gBCLRL using decoder 54
                                             //  4790:     }
                                             //  4790:    }
  16, 0,                                     //  4794:    case 0x10: {
  OPC_CheckField, 13, 3, 0,                  //  4796:     check Inst[15:13] == 0x0
  OPC_Scope, 13,                             //  4800:     try {
  OPC_CheckField, 11, 2, 0,                  //  4802:      check Inst[12:11] == 0x0
  OPC_CheckField, 16, 10, 128, 5,            //  4806:      check Inst[25:16] == 0x280
  OPC_Decode, 215, 4, 0,                     //  4811:      decode to BCTRL using decoder 0
                                             //  4811:     } else try {
  OPC_Decode, 172, 23, 54,                   //  4815:      decode to gBCCTRL using decoder 54
                                             //  4815:     }
                                             //  4815:    }
                                             //  4815:    } // switch Inst[10:6]
                                             //  4815:   }
                                             //  4815:   } // switch Inst[0]
                                             //  4815:  }
  18, 87,                                    //  4819:  case 0x12: {
  OPC_SwitchField, 6, 5,                     //  4821:   switch Inst[10:6] {
  0, 12,                                     //  4824:   case 0x0: {
  OPC_CheckField, 11, 15, 0,                 //  4826:    check Inst[25:11] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  4830:    check Inst[0] == 0x0
  OPC_Decode, 210, 14, 0,                    //  4834:    decode to RFID using decoder 0
                                             //  4834:   }
  1, 12,                                     //  4838:   case 0x1: {
  OPC_CheckField, 11, 15, 0,                 //  4840:    check Inst[25:11] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  4844:    check Inst[0] == 0x0
  OPC_Decode, 209, 14, 0,                    //  4848:    decode to RFI using decoder 0
                                             //  4848:   }
  4, 12,                                     //  4852:   case 0x4: {
  OPC_CheckField, 12, 14, 0,                 //  4854:    check Inst[25:12] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  4858:    check Inst[0] == 0x0
  OPC_Decode, 208, 14, 55,                   //  4862:    decode to RFEBB using decoder 55
                                             //  4862:   }
  8, 12,                                     //  4866:   case 0x8: {
  OPC_CheckField, 11, 15, 0,                 //  4868:    check Inst[25:11] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  4872:    check Inst[0] == 0x0
  OPC_Decode, 172, 10, 0,                    //  4876:    decode to HRFID using decoder 0
                                             //  4876:   }
  11, 12,                                    //  4880:   case 0xb: {
  OPC_CheckField, 11, 15, 0,                 //  4882:    check Inst[25:11] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  4886:    check Inst[0] == 0x0
  OPC_Decode, 250, 15, 0,                    //  4890:    decode to STOP using decoder 0
                                             //  4890:   }
  13, 0,                                     //  4894:   case 0xd: {
  OPC_CheckField, 11, 15, 0,                 //  4896:    check Inst[25:11] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  4900:    check Inst[0] == 0x0
  OPC_Decode, 202, 12, 0,                    //  4904:    decode to NAP using decoder 0
                                             //  4904:   }
                                             //  4904:   } // switch Inst[10:6]
                                             //  4904:  }
  19, 12,                                    //  4908:  case 0x13: {
  OPC_CheckField, 6, 20, 1,                  //  4910:   check Inst[25:6] == 0x1
  OPC_CheckField, 0, 1, 0,                   //  4914:   check Inst[0] == 0x0
  OPC_Decode, 206, 14, 0,                    //  4918:   decode to RFCI using decoder 0
                                             //  4918:  }
  22, 0,                                     //  4922:  case 0x16: {
  OPC_CheckField, 6, 20, 4,                  //  4924:   check Inst[25:6] == 0x4
  OPC_CheckField, 0, 1, 0,                   //  4928:   check Inst[0] == 0x0
  OPC_Decode, 182, 10, 0,                    //  4932:   decode to ISYNC using decoder 0
                                             //  4932:  }
                                             //  4932:  } // switch Inst[5:1]
                                             //  4932: }
  20, 15,                                    //  4936: case 0x14: {
  OPC_SwitchField, 0, 1,                     //  4938:  switch Inst[0] {
  0, 4,                                      //  4941:  case 0x0: {
  OPC_Decode, 228, 14, 56,                   //  4943:   decode to RLWIMI using decoder 56
                                             //  4943:  }
  1, 0,                                      //  4947:  case 0x1: {
  OPC_Decode, 231, 14, 56,                   //  4949:   decode to RLWIMI_rec using decoder 56
                                             //  4949:  }
                                             //  4949:  } // switch Inst[0]
                                             //  4949: }
  21, 15,                                    //  4953: case 0x15: {
  OPC_SwitchField, 0, 1,                     //  4955:  switch Inst[0] {
  0, 4,                                      //  4958:  case 0x0: {
  OPC_Decode, 232, 14, 57,                   //  4960:   decode to RLWINM using decoder 57
                                             //  4960:  }
  1, 0,                                      //  4964:  case 0x1: {
  OPC_Decode, 235, 14, 57,                   //  4966:   decode to RLWINM_rec using decoder 57
                                             //  4966:  }
                                             //  4966:  } // switch Inst[0]
                                             //  4966: }
  23, 15,                                    //  4970: case 0x17: {
  OPC_SwitchField, 0, 1,                     //  4972:  switch Inst[0] {
  0, 4,                                      //  4975:  case 0x0: {
  OPC_Decode, 236, 14, 58,                   //  4977:   decode to RLWNM using decoder 58
                                             //  4977:  }
  1, 0,                                      //  4981:  case 0x1: {
  OPC_Decode, 239, 14, 58,                   //  4983:   decode to RLWNM_rec using decoder 58
                                             //  4983:  }
                                             //  4983:  } // switch Inst[0]
                                             //  4983: }
  24, 14,                                    //  4987: case 0x18: {
  OPC_Scope, 8,                              //  4989:  try {
  OPC_CheckField, 0, 26, 0,                  //  4991:   check Inst[25:0] == 0x0
  OPC_Decode, 211, 12, 0,                    //  4995:   decode to NOP using decoder 0
                                             //  4995:  } else try {
  OPC_Decode, 225, 12, 59,                   //  4999:   decode to ORI using decoder 59
                                             //  4999:  }
                                             //  4999: }
  25, 4,                                     //  5003: case 0x19: {
  OPC_Decode, 227, 12, 59,                   //  5005:  decode to ORIS using decoder 59
                                             //  5005: }
  26, 4,                                     //  5009: case 0x1a: {
  OPC_Decode, 177, 20, 59,                   //  5011:  decode to XORI using decoder 59
                                             //  5011: }
  27, 4,                                     //  5015: case 0x1b: {
  OPC_Decode, 179, 20, 59,                   //  5017:  decode to XORIS using decoder 59
                                             //  5017: }
  28, 4,                                     //  5021: case 0x1c: {
  OPC_Decode, 243, 3, 59,                    //  5023:  decode to ANDI_rec using decoder 59
                                             //  5023: }
  29, 4,                                     //  5027: case 0x1d: {
  OPC_Decode, 242, 3, 59,                    //  5029:  decode to ANDIS_rec using decoder 59
                                             //  5029: }
  30, 100,                                   //  5033: case 0x1e: {
  OPC_SwitchField, 2, 3,                     //  5035:  switch Inst[4:2] {
  0, 15,                                     //  5038:  case 0x0: {
  OPC_SwitchField, 0, 1,                     //  5040:   switch Inst[0] {
  0, 4,                                      //  5043:   case 0x0: {
  OPC_Decode, 217, 14, 60,                   //  5045:    decode to RLDICL using decoder 60
                                             //  5045:   }
  1, 0,                                      //  5049:   case 0x1: {
  OPC_Decode, 221, 14, 60,                   //  5051:    decode to RLDICL_rec using decoder 60
                                             //  5051:   }
                                             //  5051:   } // switch Inst[0]
                                             //  5051:  }
  1, 15,                                     //  5055:  case 0x1: {
  OPC_SwitchField, 0, 1,                     //  5057:   switch Inst[0] {
  0, 4,                                      //  5060:   case 0x0: {
  OPC_Decode, 222, 14, 60,                   //  5062:    decode to RLDICR using decoder 60
                                             //  5062:   }
  1, 0,                                      //  5066:   case 0x1: {
  OPC_Decode, 224, 14, 60,                   //  5068:    decode to RLDICR_rec using decoder 60
                                             //  5068:   }
                                             //  5068:   } // switch Inst[0]
                                             //  5068:  }
  2, 15,                                     //  5072:  case 0x2: {
  OPC_SwitchField, 0, 1,                     //  5074:   switch Inst[0] {
  0, 4,                                      //  5077:   case 0x0: {
  OPC_Decode, 216, 14, 60,                   //  5079:    decode to RLDIC using decoder 60
                                             //  5079:   }
  1, 0,                                      //  5083:   case 0x1: {
  OPC_Decode, 225, 14, 60,                   //  5085:    decode to RLDIC_rec using decoder 60
                                             //  5085:   }
                                             //  5085:   } // switch Inst[0]
                                             //  5085:  }
  3, 15,                                     //  5089:  case 0x3: {
  OPC_SwitchField, 0, 1,                     //  5091:   switch Inst[0] {
  0, 4,                                      //  5094:   case 0x0: {
  OPC_Decode, 226, 14, 61,                   //  5096:    decode to RLDIMI using decoder 61
                                             //  5096:   }
  1, 0,                                      //  5100:   case 0x1: {
  OPC_Decode, 227, 14, 61,                   //  5102:    decode to RLDIMI_rec using decoder 61
                                             //  5102:   }
                                             //  5102:   } // switch Inst[0]
                                             //  5102:  }
  4, 0,                                      //  5106:  case 0x4: {
  OPC_SwitchField, 0, 2,                     //  5108:   switch Inst[1:0] {
  0, 4,                                      //  5111:   case 0x0: {
  OPC_Decode, 212, 14, 62,                   //  5113:    decode to RLDCL using decoder 62
                                             //  5113:   }
  1, 4,                                      //  5117:   case 0x1: {
  OPC_Decode, 213, 14, 62,                   //  5119:    decode to RLDCL_rec using decoder 62
                                             //  5119:   }
  2, 4,                                      //  5123:   case 0x2: {
  OPC_Decode, 214, 14, 62,                   //  5125:    decode to RLDCR using decoder 62
                                             //  5125:   }
  3, 0,                                      //  5129:   case 0x3: {
  OPC_Decode, 215, 14, 62,                   //  5131:    decode to RLDCR_rec using decoder 62
                                             //  5131:   }
                                             //  5131:   } // switch Inst[1:0]
                                             //  5131:  }
                                             //  5131:  } // switch Inst[4:2]
                                             //  5131: }
  31, 217, 36,                               //  5135: case 0x1f: {
  OPC_SwitchField, 2, 4,                     //  5138:  switch Inst[5:2] {
  0, 165, 1,                                 //  5141:  case 0x0: {
  OPC_SwitchField, 6, 5,                     //  5144:   switch Inst[10:6] {
  0, 23,                                     //  5147:   case 0x0: {
  OPC_SwitchField, 21, 2,                    //  5149:    switch Inst[22:21] {
  0, 8,                                      //  5152:    case 0x0: {
  OPC_CheckField, 0, 2, 0,                   //  5154:     check Inst[1:0] == 0x0
  OPC_Decode, 184, 5, 63,                    //  5158:     decode to CMPW using decoder 63
                                             //  5158:    }
  1, 0,                                      //  5162:    case 0x1: {
  OPC_CheckField, 0, 2, 0,                   //  5164:     check Inst[1:0] == 0x0
  OPC_Decode, 175, 5, 64,                    //  5168:     decode to CMPD using decoder 64
                                             //  5168:    }
                                             //  5168:    } // switch Inst[22:21]
                                             //  5168:   }
  1, 23,                                     //  5172:   case 0x1: {
  OPC_SwitchField, 21, 2,                    //  5174:    switch Inst[22:21] {
  0, 8,                                      //  5177:    case 0x0: {
  OPC_CheckField, 0, 2, 0,                   //  5179:     check Inst[1:0] == 0x0
  OPC_Decode, 180, 5, 63,                    //  5183:     decode to CMPLW using decoder 63
                                             //  5183:    }
  1, 0,                                      //  5187:    case 0x1: {
  OPC_CheckField, 0, 2, 0,                   //  5189:     check Inst[1:0] == 0x0
  OPC_Decode, 178, 5, 64,                    //  5193:     decode to CMPLD using decoder 64
                                             //  5193:    }
                                             //  5193:    } // switch Inst[22:21]
                                             //  5193:   }
  4, 12,                                     //  5197:   case 0x4: {
  OPC_CheckField, 11, 7, 0,                  //  5199:    check Inst[17:11] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  5203:    check Inst[1:0] == 0x0
  OPC_Decode, 137, 15, 65,                   //  5207:    decode to SETB using decoder 65
                                             //  5207:   }
  6, 12,                                     //  5211:   case 0x6: {
  OPC_CheckField, 22, 1, 0,                  //  5213:    check Inst[22] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  5217:    check Inst[1:0] == 0x0
  OPC_Decode, 182, 5, 66,                    //  5221:    decode to CMPRB using decoder 66
                                             //  5221:   }
  7, 12,                                     //  5225:   case 0x7: {
  OPC_CheckField, 21, 2, 0,                  //  5227:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  5231:    check Inst[1:0] == 0x0
  OPC_Decode, 177, 5, 64,                    //  5235:    decode to CMPEQB using decoder 64
                                             //  5235:   }
  12, 12,                                    //  5239:   case 0xc: {
  OPC_CheckField, 11, 5, 0,                  //  5241:    check Inst[15:11] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  5245:    check Inst[1:0] == 0x0
  OPC_Decode, 139, 15, 67,                   //  5249:    decode to SETBC using decoder 67
                                             //  5249:   }
  13, 12,                                    //  5253:   case 0xd: {
  OPC_CheckField, 11, 5, 0,                  //  5255:    check Inst[15:11] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  5259:    check Inst[1:0] == 0x0
  OPC_Decode, 141, 15, 67,                   //  5263:    decode to SETBCR using decoder 67
                                             //  5263:   }
  14, 12,                                    //  5267:   case 0xe: {
  OPC_CheckField, 11, 5, 0,                  //  5269:    check Inst[15:11] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  5273:    check Inst[1:0] == 0x0
  OPC_Decode, 144, 15, 67,                   //  5277:    decode to SETNBC using decoder 67
                                             //  5277:   }
  15, 12,                                    //  5281:   case 0xf: {
  OPC_CheckField, 11, 5, 0,                  //  5283:    check Inst[15:11] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  5287:    check Inst[1:0] == 0x0
  OPC_Decode, 146, 15, 67,                   //  5291:    decode to SETNBCR using decoder 67
                                             //  5291:   }
  18, 0,                                     //  5295:   case 0x12: {
  OPC_CheckField, 11, 12, 0,                 //  5297:    check Inst[22:11] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  5301:    check Inst[1:0] == 0x0
  OPC_Decode, 217, 11, 68,                   //  5305:    decode to MCRXRX using decoder 68
                                             //  5305:   }
                                             //  5305:   } // switch Inst[10:6]
                                             //  5305:  }
  1, 47,                                     //  5309:  case 0x1: {
  OPC_SwitchField, 6, 5,                     //  5311:   switch Inst[10:6] {
  4, 12,                                     //  5314:   case 0x4: {
  OPC_CheckField, 16, 1, 0,                  //  5316:    check Inst[16] == 0x0
  OPC_CheckField, 1, 1, 1,                   //  5320:    check Inst[1] == 0x1
  OPC_Decode, 172, 20, 69,                   //  5324:    decode to WRTEE using decoder 69
                                             //  5324:   }
  5, 8,                                      //  5328:   case 0x5: {
  OPC_CheckField, 1, 1, 1,                   //  5330:    check Inst[1] == 0x1
  OPC_Decode, 173, 20, 70,                   //  5334:    decode to WRTEEI using decoder 70
                                             //  5334:   }
  10, 8,                                     //  5338:   case 0xa: {
  OPC_CheckField, 0, 2, 2,                   //  5340:    check Inst[1:0] == 0x2
  OPC_Decode, 223, 11, 71,                   //  5344:    decode to MFDCR using decoder 71
                                             //  5344:   }
  14, 0,                                     //  5348:   case 0xe: {
  OPC_CheckField, 0, 2, 2,                   //  5350:    check Inst[1:0] == 0x2
  OPC_Decode, 137, 12, 71,                   //  5354:    decode to MTDCR using decoder 71
                                             //  5354:   }
                                             //  5354:   } // switch Inst[10:6]
                                             //  5354:  }
  2, 35,                                     //  5358:  case 0x2: {
  OPC_SwitchField, 6, 5,                     //  5360:   switch Inst[10:6] {
  0, 20,                                     //  5363:   case 0x0: {
  OPC_CheckField, 0, 2, 0,                   //  5365:    check Inst[1:0] == 0x0
  OPC_Scope, 10,                             //  5369:    try {
  OPC_CheckField, 11, 15, 128, 248, 1,       //  5371:     check Inst[25:11] == 0x7c00
  OPC_Decode, 143, 17, 0,                    //  5377:     decode to TRAP using decoder 0
                                             //  5377:    } else try {
  OPC_Decode, 147, 17, 72,                   //  5381:     decode to TW using decoder 72
                                             //  5381:    }
                                             //  5381:   }
  2, 0,                                      //  5385:   case 0x2: {
  OPC_CheckField, 0, 2, 0,                   //  5387:    check Inst[1:0] == 0x0
  OPC_Decode, 243, 16, 73,                   //  5391:    decode to TD using decoder 73
                                             //  5391:   }
                                             //  5391:   } // switch Inst[10:6]
                                             //  5391:  }
  3, 132, 2,                                 //  5395:  case 0x3: {
  OPC_SwitchField, 6, 5,                     //  5398:   switch Inst[10:6] {
  0, 15,                                     //  5401:   case 0x0: {
  OPC_SwitchField, 0, 2,                     //  5403:    switch Inst[1:0] {
  0, 4,                                      //  5406:    case 0x0: {
  OPC_Decode, 147, 11, 74,                   //  5408:     decode to LVSL using decoder 74
                                             //  5408:    }
  2, 0,                                      //  5412:    case 0x2: {
  OPC_Decode, 144, 11, 74,                   //  5414:     decode to LVEBX using decoder 74
                                             //  5414:    }
                                             //  5414:    } // switch Inst[1:0]
                                             //  5414:   }
  1, 15,                                     //  5418:   case 0x1: {
  OPC_SwitchField, 0, 2,                     //  5420:    switch Inst[1:0] {
  0, 4,                                      //  5423:    case 0x0: {
  OPC_Decode, 148, 11, 74,                   //  5425:     decode to LVSR using decoder 74
                                             //  5425:    }
  2, 0,                                      //  5429:    case 0x2: {
  OPC_Decode, 145, 11, 74,                   //  5431:     decode to LVEHX using decoder 74
                                             //  5431:    }
                                             //  5431:    } // switch Inst[1:0]
                                             //  5431:   }
  2, 8,                                      //  5435:   case 0x2: {
  OPC_CheckField, 0, 2, 2,                   //  5437:    check Inst[1:0] == 0x2
  OPC_Decode, 146, 11, 74,                   //  5441:    decode to LVEWX using decoder 74
                                             //  5441:   }
  3, 8,                                      //  5445:   case 0x3: {
  OPC_CheckField, 0, 2, 2,                   //  5447:    check Inst[1:0] == 0x2
  OPC_Decode, 149, 11, 74,                   //  5451:    decode to LVX using decoder 74
                                             //  5451:   }
  4, 8,                                      //  5455:   case 0x4: {
  OPC_CheckField, 0, 2, 2,                   //  5457:    check Inst[1:0] == 0x2
  OPC_Decode, 255, 15, 74,                   //  5461:    decode to STVEBX using decoder 74
                                             //  5461:   }
  5, 8,                                      //  5465:   case 0x5: {
  OPC_CheckField, 0, 2, 2,                   //  5467:    check Inst[1:0] == 0x2
  OPC_Decode, 128, 16, 74,                   //  5471:    decode to STVEHX using decoder 74
                                             //  5471:   }
  6, 19,                                     //  5475:   case 0x6: {
  OPC_SwitchField, 0, 2,                     //  5477:    switch Inst[1:0] {
  0, 8,                                      //  5480:    case 0x0: {
  OPC_CheckField, 25, 1, 0,                  //  5482:     check Inst[25] == 0x0
  OPC_Decode, 176, 10, 75,                   //  5486:     decode to ICBLQ using decoder 75
                                             //  5486:    }
  2, 0,                                      //  5490:    case 0x2: {
  OPC_Decode, 129, 16, 74,                   //  5492:     decode to STVEWX using decoder 74
                                             //  5492:    }
                                             //  5492:    } // switch Inst[1:0]
                                             //  5492:   }
  7, 19,                                     //  5496:   case 0x7: {
  OPC_SwitchField, 0, 2,                     //  5498:    switch Inst[1:0] {
  0, 8,                                      //  5501:    case 0x0: {
  OPC_CheckField, 25, 1, 0,                  //  5503:     check Inst[25] == 0x0
  OPC_Decode, 175, 10, 75,                   //  5507:     decode to ICBLC using decoder 75
                                             //  5507:    }
  2, 0,                                      //  5511:    case 0x2: {
  OPC_Decode, 130, 16, 74,                   //  5513:     decode to STVX using decoder 74
                                             //  5513:    }
                                             //  5513:    } // switch Inst[1:0]
                                             //  5513:   }
  11, 8,                                     //  5517:   case 0xb: {
  OPC_CheckField, 0, 2, 2,                   //  5519:    check Inst[1:0] == 0x2
  OPC_Decode, 150, 11, 74,                   //  5523:    decode to LVXL using decoder 74
                                             //  5523:   }
  14, 12,                                    //  5527:   case 0xe: {
  OPC_CheckField, 21, 5, 0,                  //  5529:    check Inst[25:21] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  5533:    check Inst[1:0] == 0x0
  OPC_Decode, 238, 5, 76,                    //  5537:    decode to DCCCI using decoder 76
                                             //  5537:   }
  15, 19,                                    //  5541:   case 0xf: {
  OPC_SwitchField, 0, 2,                     //  5543:    switch Inst[1:0] {
  0, 8,                                      //  5546:    case 0x0: {
  OPC_CheckField, 25, 1, 0,                  //  5548:     check Inst[25] == 0x0
  OPC_Decode, 178, 10, 75,                   //  5552:     decode to ICBTLS using decoder 75
                                             //  5552:    }
  2, 0,                                      //  5556:    case 0x2: {
  OPC_Decode, 131, 16, 74,                   //  5558:     decode to STVXL using decoder 74
                                             //  5558:    }
                                             //  5558:    } // switch Inst[1:0]
                                             //  5558:   }
  18, 8,                                     //  5562:   case 0x12: {
  OPC_CheckField, 0, 2, 0,                   //  5564:    check Inst[1:0] == 0x0
  OPC_Decode, 154, 11, 77,                   //  5568:    decode to LWAT using decoder 77
                                             //  5568:   }
  19, 8,                                     //  5572:   case 0x13: {
  OPC_CheckField, 0, 2, 0,                   //  5574:    check Inst[1:0] == 0x0
  OPC_Decode, 203, 10, 77,                   //  5578:    decode to LDAT using decoder 77
                                             //  5578:   }
  22, 8,                                     //  5582:   case 0x16: {
  OPC_CheckField, 0, 2, 0,                   //  5584:    check Inst[1:0] == 0x0
  OPC_Decode, 134, 16, 78,                   //  5588:    decode to STWAT using decoder 78
                                             //  5588:   }
  23, 8,                                     //  5592:   case 0x17: {
  OPC_CheckField, 0, 2, 0,                   //  5594:    check Inst[1:0] == 0x0
  OPC_Decode, 211, 15, 79,                   //  5598:    decode to STDAT using decoder 79
                                             //  5598:   }
  24, 12,                                    //  5602:   case 0x18: {
  OPC_CheckField, 21, 5, 1,                  //  5604:    check Inst[25:21] == 0x1
  OPC_CheckField, 0, 2, 0,                   //  5608:    check Inst[1:0] == 0x0
  OPC_Decode, 201, 5, 76,                    //  5612:    decode to CP_COPY using decoder 76
                                             //  5612:   }
  26, 12,                                    //  5616:   case 0x1a: {
  OPC_CheckField, 11, 15, 0,                 //  5618:    check Inst[25:11] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  5622:    check Inst[1:0] == 0x0
  OPC_Decode, 200, 5, 0,                     //  5626:    decode to CP_ABORT using decoder 0
                                             //  5626:   }
  28, 12,                                    //  5630:   case 0x1c: {
  OPC_CheckField, 22, 4, 0,                  //  5632:    check Inst[25:22] == 0x0
  OPC_CheckField, 0, 2, 1,                   //  5636:    check Inst[1:0] == 0x1
  OPC_Decode, 204, 5, 80,                    //  5640:    decode to CP_PASTE_rec using decoder 80
                                             //  5640:   }
  30, 0,                                     //  5644:   case 0x1e: {
  OPC_CheckField, 21, 5, 0,                  //  5646:    check Inst[25:21] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  5650:    check Inst[1:0] == 0x0
  OPC_Decode, 179, 10, 76,                   //  5654:    decode to ICCCI using decoder 76
                                             //  5654:   }
                                             //  5654:   } // switch Inst[10:6]
                                             //  5654:  }
  4, 253, 3,                                 //  5658:  case 0x4: {
  OPC_SwitchField, 6, 4,                     //  5661:   switch Inst[9:6] {
  0, 57,                                     //  5664:   case 0x0: {
  OPC_SwitchField, 0, 2,                     //  5666:    switch Inst[1:0] {
  0, 15,                                     //  5669:    case 0x0: {
  OPC_SwitchField, 10, 1,                    //  5671:     switch Inst[10] {
  0, 4,                                      //  5674:     case 0x0: {
  OPC_Decode, 181, 16, 81,                   //  5676:      decode to SUBFC using decoder 81
                                             //  5676:     }
  1, 0,                                      //  5680:     case 0x1: {
  OPC_Decode, 186, 16, 81,                   //  5682:      decode to SUBFCO using decoder 81
                                             //  5682:     }
                                             //  5682:     } // switch Inst[10]
                                             //  5682:    }
  1, 15,                                     //  5686:    case 0x1: {
  OPC_SwitchField, 10, 1,                    //  5688:     switch Inst[10] {
  0, 4,                                      //  5691:     case 0x0: {
  OPC_Decode, 188, 16, 81,                   //  5693:      decode to SUBFC_rec using decoder 81
                                             //  5693:     }
  1, 0,                                      //  5697:     case 0x1: {
  OPC_Decode, 187, 16, 81,                   //  5699:      decode to SUBFCO_rec using decoder 81
                                             //  5699:     }
                                             //  5699:     } // switch Inst[10]
                                             //  5699:    }
  2, 8,                                      //  5703:    case 0x2: {
  OPC_CheckField, 10, 1, 0,                  //  5705:     check Inst[10] == 0x0
  OPC_Decode, 178, 12, 82,                   //  5709:     decode to MULHDU using decoder 82
                                             //  5709:    }
  3, 0,                                      //  5713:    case 0x3: {
  OPC_CheckField, 10, 1, 0,                  //  5715:     check Inst[10] == 0x0
  OPC_Decode, 179, 12, 82,                   //  5719:     decode to MULHDU_rec using decoder 82
                                             //  5719:    }
                                             //  5719:    } // switch Inst[1:0]
                                             //  5719:   }
  1, 37,                                     //  5723:   case 0x1: {
  OPC_SwitchField, 0, 2,                     //  5725:    switch Inst[1:0] {
  0, 15,                                     //  5728:    case 0x0: {
  OPC_SwitchField, 10, 1,                    //  5730:     switch Inst[10] {
  0, 4,                                      //  5733:     case 0x0: {
  OPC_Decode, 176, 16, 81,                   //  5735:      decode to SUBF using decoder 81
                                             //  5735:     }
  1, 0,                                      //  5739:     case 0x1: {
  OPC_Decode, 207, 16, 81,                   //  5741:      decode to SUBFO using decoder 81
                                             //  5741:     }
                                             //  5741:     } // switch Inst[10]
                                             //  5741:    }
  1, 0,                                      //  5745:    case 0x1: {
  OPC_SwitchField, 10, 1,                    //  5747:     switch Inst[10] {
  0, 4,                                      //  5750:     case 0x0: {
  OPC_Decode, 219, 16, 81,                   //  5752:      decode to SUBF_rec using decoder 81
                                             //  5752:     }
  1, 0,                                      //  5756:     case 0x1: {
  OPC_Decode, 208, 16, 81,                   //  5758:      decode to SUBFO_rec using decoder 81
                                             //  5758:     }
                                             //  5758:     } // switch Inst[10]
                                             //  5758:    }
                                             //  5758:    } // switch Inst[1:0]
                                             //  5758:   }
  2, 35,                                     //  5762:   case 0x2: {
  OPC_SwitchField, 0, 2,                     //  5764:    switch Inst[1:0] {
  0, 4,                                      //  5767:    case 0x0: {
  OPC_Decode, 209, 16, 83,                   //  5769:     decode to SUBFUS using decoder 83
                                             //  5769:    }
  1, 4,                                      //  5773:    case 0x1: {
  OPC_Decode, 210, 16, 83,                   //  5775:     decode to SUBFUS_rec using decoder 83
                                             //  5775:    }
  2, 8,                                      //  5779:    case 0x2: {
  OPC_CheckField, 10, 1, 0,                  //  5781:     check Inst[10] == 0x0
  OPC_Decode, 177, 12, 82,                   //  5785:     decode to MULHD using decoder 82
                                             //  5785:    }
  3, 0,                                      //  5789:    case 0x3: {
  OPC_CheckField, 10, 1, 0,                  //  5791:     check Inst[10] == 0x0
  OPC_Decode, 180, 12, 82,                   //  5795:     decode to MULHD_rec using decoder 82
                                             //  5795:    }
                                             //  5795:    } // switch Inst[1:0]
                                             //  5795:   }
  3, 37,                                     //  5799:   case 0x3: {
  OPC_SwitchField, 0, 2,                     //  5801:    switch Inst[1:0] {
  0, 15,                                     //  5804:    case 0x0: {
  OPC_SwitchField, 10, 6,                    //  5806:     switch Inst[15:10] {
  0, 4,                                      //  5809:     case 0x0: {
  OPC_Decode, 203, 12, 84,                   //  5811:      decode to NEG using decoder 84
                                             //  5811:     }
  1, 0,                                      //  5815:     case 0x1: {
  OPC_Decode, 208, 12, 84,                   //  5817:      decode to NEGO using decoder 84
                                             //  5817:     }
                                             //  5817:     } // switch Inst[15:10]
                                             //  5817:    }
  1, 0,                                      //  5821:    case 0x1: {
  OPC_SwitchField, 10, 6,                    //  5823:     switch Inst[15:10] {
  0, 4,                                      //  5826:     case 0x0: {
  OPC_Decode, 210, 12, 84,                   //  5828:      decode to NEG_rec using decoder 84
                                             //  5828:     }
  1, 0,                                      //  5832:     case 0x1: {
  OPC_Decode, 209, 12, 84,                   //  5834:      decode to NEGO_rec using decoder 84
                                             //  5834:     }
                                             //  5834:     } // switch Inst[15:10]
                                             //  5834:    }
                                             //  5834:    } // switch Inst[1:0]
                                             //  5834:   }
  4, 37,                                     //  5838:   case 0x4: {
  OPC_SwitchField, 0, 2,                     //  5840:    switch Inst[1:0] {
  0, 15,                                     //  5843:    case 0x0: {
  OPC_SwitchField, 10, 1,                    //  5845:     switch Inst[10] {
  0, 4,                                      //  5848:     case 0x0: {
  OPC_Decode, 189, 16, 81,                   //  5850:      decode to SUBFE using decoder 81
                                             //  5850:     }
  1, 0,                                      //  5854:     case 0x1: {
  OPC_Decode, 194, 16, 81,                   //  5856:      decode to SUBFEO using decoder 81
                                             //  5856:     }
                                             //  5856:     } // switch Inst[10]
                                             //  5856:    }
  1, 0,                                      //  5860:    case 0x1: {
  OPC_SwitchField, 10, 1,                    //  5862:     switch Inst[10] {
  0, 4,                                      //  5865:     case 0x0: {
  OPC_Decode, 196, 16, 81,                   //  5867:      decode to SUBFE_rec using decoder 81
                                             //  5867:     }
  1, 0,                                      //  5871:     case 0x1: {
  OPC_Decode, 195, 16, 81,                   //  5873:      decode to SUBFEO_rec using decoder 81
                                             //  5873:     }
                                             //  5873:     } // switch Inst[10]
                                             //  5873:    }
                                             //  5873:    } // switch Inst[1:0]
                                             //  5873:   }
  6, 37,                                     //  5877:   case 0x6: {
  OPC_SwitchField, 0, 2,                     //  5879:    switch Inst[1:0] {
  0, 15,                                     //  5882:    case 0x0: {
  OPC_SwitchField, 10, 6,                    //  5884:     switch Inst[15:10] {
  0, 4,                                      //  5887:     case 0x0: {
  OPC_Decode, 211, 16, 84,                   //  5889:      decode to SUBFZE using decoder 84
                                             //  5889:     }
  1, 0,                                      //  5893:     case 0x1: {
  OPC_Decode, 216, 16, 84,                   //  5895:      decode to SUBFZEO using decoder 84
                                             //  5895:     }
                                             //  5895:     } // switch Inst[15:10]
                                             //  5895:    }
  1, 0,                                      //  5899:    case 0x1: {
  OPC_SwitchField, 10, 6,                    //  5901:     switch Inst[15:10] {
  0, 4,                                      //  5904:     case 0x0: {
  OPC_Decode, 218, 16, 84,                   //  5906:      decode to SUBFZE_rec using decoder 84
                                             //  5906:     }
  1, 0,                                      //  5910:     case 0x1: {
  OPC_Decode, 217, 16, 84,                   //  5912:      decode to SUBFZEO_rec using decoder 84
                                             //  5912:     }
                                             //  5912:     } // switch Inst[15:10]
                                             //  5912:    }
                                             //  5912:    } // switch Inst[1:0]
                                             //  5912:   }
  7, 71,                                     //  5916:   case 0x7: {
  OPC_SwitchField, 0, 2,                     //  5918:    switch Inst[1:0] {
  0, 15,                                     //  5921:    case 0x0: {
  OPC_SwitchField, 10, 6,                    //  5923:     switch Inst[15:10] {
  0, 4,                                      //  5926:     case 0x0: {
  OPC_Decode, 199, 16, 84,                   //  5928:      decode to SUBFME using decoder 84
                                             //  5928:     }
  1, 0,                                      //  5932:     case 0x1: {
  OPC_Decode, 204, 16, 84,                   //  5934:      decode to SUBFMEO using decoder 84
                                             //  5934:     }
                                             //  5934:     } // switch Inst[15:10]
                                             //  5934:    }
  1, 15,                                     //  5938:    case 0x1: {
  OPC_SwitchField, 10, 6,                    //  5940:     switch Inst[15:10] {
  0, 4,                                      //  5943:     case 0x0: {
  OPC_Decode, 206, 16, 84,                   //  5945:      decode to SUBFME_rec using decoder 84
                                             //  5945:     }
  1, 0,                                      //  5949:     case 0x1: {
  OPC_Decode, 205, 16, 84,                   //  5951:      decode to SUBFMEO_rec using decoder 84
                                             //  5951:     }
                                             //  5951:     } // switch Inst[15:10]
                                             //  5951:    }
  2, 15,                                     //  5955:    case 0x2: {
  OPC_SwitchField, 10, 1,                    //  5957:     switch Inst[10] {
  0, 4,                                      //  5960:     case 0x0: {
  OPC_Decode, 185, 12, 82,                   //  5962:      decode to MULLD using decoder 82
                                             //  5962:     }
  1, 0,                                      //  5966:     case 0x1: {
  OPC_Decode, 186, 12, 82,                   //  5968:      decode to MULLDO using decoder 82
                                             //  5968:     }
                                             //  5968:     } // switch Inst[10]
                                             //  5968:    }
  3, 0,                                      //  5972:    case 0x3: {
  OPC_SwitchField, 10, 1,                    //  5974:     switch Inst[10] {
  0, 4,                                      //  5977:     case 0x0: {
  OPC_Decode, 188, 12, 82,                   //  5979:      decode to MULLD_rec using decoder 82
                                             //  5979:     }
  1, 0,                                      //  5983:     case 0x1: {
  OPC_Decode, 187, 12, 82,                   //  5985:      decode to MULLDO_rec using decoder 82
                                             //  5985:     }
                                             //  5985:     } // switch Inst[10]
                                             //  5985:    }
                                             //  5985:    } // switch Inst[1:0]
                                             //  5985:   }
  8, 23,                                     //  5989:   case 0x8: {
  OPC_SwitchField, 10, 1,                    //  5991:    switch Inst[10] {
  0, 8,                                      //  5994:    case 0x0: {
  OPC_CheckField, 0, 2, 2,                   //  5996:     check Inst[1:0] == 0x2
  OPC_Decode, 255, 11, 82,                   //  6000:     decode to MODUD using decoder 82
                                             //  6000:    }
  1, 0,                                      //  6004:    case 0x1: {
  OPC_CheckField, 0, 2, 2,                   //  6006:     check Inst[1:0] == 0x2
  OPC_Decode, 253, 11, 82,                   //  6010:     decode to MODSD using decoder 82
                                             //  6010:    }
                                             //  6010:    } // switch Inst[10]
                                             //  6010:   }
  12, 37,                                    //  6014:   case 0xc: {
  OPC_SwitchField, 0, 2,                     //  6016:    switch Inst[1:0] {
  2, 15,                                     //  6019:    case 0x2: {
  OPC_SwitchField, 10, 1,                    //  6021:     switch Inst[10] {
  0, 4,                                      //  6024:     case 0x0: {
  OPC_Decode, 149, 6, 82,                    //  6026:      decode to DIVDEU using decoder 82
                                             //  6026:     }
  1, 0,                                      //  6030:     case 0x1: {
  OPC_Decode, 150, 6, 82,                    //  6032:      decode to DIVDEUO using decoder 82
                                             //  6032:     }
                                             //  6032:     } // switch Inst[10]
                                             //  6032:    }
  3, 0,                                      //  6036:    case 0x3: {
  OPC_SwitchField, 10, 1,                    //  6038:     switch Inst[10] {
  0, 4,                                      //  6041:     case 0x0: {
  OPC_Decode, 152, 6, 82,                    //  6043:      decode to DIVDEU_rec using decoder 82
                                             //  6043:     }
  1, 0,                                      //  6047:     case 0x1: {
  OPC_Decode, 151, 6, 82,                    //  6049:      decode to DIVDEUO_rec using decoder 82
                                             //  6049:     }
                                             //  6049:     } // switch Inst[10]
                                             //  6049:    }
                                             //  6049:    } // switch Inst[1:0]
                                             //  6049:   }
  13, 37,                                    //  6053:   case 0xd: {
  OPC_SwitchField, 0, 2,                     //  6055:    switch Inst[1:0] {
  2, 15,                                     //  6058:    case 0x2: {
  OPC_SwitchField, 10, 1,                    //  6060:     switch Inst[10] {
  0, 4,                                      //  6063:     case 0x0: {
  OPC_Decode, 146, 6, 82,                    //  6065:      decode to DIVDE using decoder 82
                                             //  6065:     }
  1, 0,                                      //  6069:     case 0x1: {
  OPC_Decode, 147, 6, 82,                    //  6071:      decode to DIVDEO using decoder 82
                                             //  6071:     }
                                             //  6071:     } // switch Inst[10]
                                             //  6071:    }
  3, 0,                                      //  6075:    case 0x3: {
  OPC_SwitchField, 10, 1,                    //  6077:     switch Inst[10] {
  0, 4,                                      //  6080:     case 0x0: {
  OPC_Decode, 153, 6, 82,                    //  6082:      decode to DIVDE_rec using decoder 82
                                             //  6082:     }
  1, 0,                                      //  6086:     case 0x1: {
  OPC_Decode, 148, 6, 82,                    //  6088:      decode to DIVDEO_rec using decoder 82
                                             //  6088:     }
                                             //  6088:     } // switch Inst[10]
                                             //  6088:    }
                                             //  6088:    } // switch Inst[1:0]
                                             //  6088:   }
  14, 37,                                    //  6092:   case 0xe: {
  OPC_SwitchField, 0, 2,                     //  6094:    switch Inst[1:0] {
  2, 15,                                     //  6097:    case 0x2: {
  OPC_SwitchField, 10, 1,                    //  6099:     switch Inst[10] {
  0, 4,                                      //  6102:     case 0x0: {
  OPC_Decode, 156, 6, 82,                    //  6104:      decode to DIVDU using decoder 82
                                             //  6104:     }
  1, 0,                                      //  6108:     case 0x1: {
  OPC_Decode, 157, 6, 82,                    //  6110:      decode to DIVDUO using decoder 82
                                             //  6110:     }
                                             //  6110:     } // switch Inst[10]
                                             //  6110:    }
  3, 0,                                      //  6114:    case 0x3: {
  OPC_SwitchField, 10, 1,                    //  6116:     switch Inst[10] {
  0, 4,                                      //  6119:     case 0x0: {
  OPC_Decode, 159, 6, 82,                    //  6121:      decode to DIVDU_rec using decoder 82
                                             //  6121:     }
  1, 0,                                      //  6125:     case 0x1: {
  OPC_Decode, 158, 6, 82,                    //  6127:      decode to DIVDUO_rec using decoder 82
                                             //  6127:     }
                                             //  6127:     } // switch Inst[10]
                                             //  6127:    }
                                             //  6127:    } // switch Inst[1:0]
                                             //  6127:   }
  15, 0,                                     //  6131:   case 0xf: {
  OPC_SwitchField, 0, 2,                     //  6133:    switch Inst[1:0] {
  2, 15,                                     //  6136:    case 0x2: {
  OPC_SwitchField, 10, 1,                    //  6138:     switch Inst[10] {
  0, 4,                                      //  6141:     case 0x0: {
  OPC_Decode, 145, 6, 82,                    //  6143:      decode to DIVD using decoder 82
                                             //  6143:     }
  1, 0,                                      //  6147:     case 0x1: {
  OPC_Decode, 154, 6, 82,                    //  6149:      decode to DIVDO using decoder 82
                                             //  6149:     }
                                             //  6149:     } // switch Inst[10]
                                             //  6149:    }
  3, 0,                                      //  6153:    case 0x3: {
  OPC_SwitchField, 10, 1,                    //  6155:     switch Inst[10] {
  0, 4,                                      //  6158:     case 0x0: {
  OPC_Decode, 160, 6, 82,                    //  6160:      decode to DIVD_rec using decoder 82
                                             //  6160:     }
  1, 0,                                      //  6164:     case 0x1: {
  OPC_Decode, 155, 6, 82,                    //  6166:      decode to DIVDO_rec using decoder 82
                                             //  6166:     }
                                             //  6166:     } // switch Inst[10]
                                             //  6166:    }
                                             //  6166:    } // switch Inst[1:0]
                                             //  6166:   }
                                             //  6166:   } // switch Inst[9:6]
                                             //  6166:  }
  5, 166, 3,                                 //  6170:  case 0x5: {
  OPC_SwitchField, 6, 3,                     //  6173:   switch Inst[8:6] {
  0, 94,                                     //  6176:   case 0x0: {
  OPC_SwitchField, 0, 2,                     //  6178:    switch Inst[1:0] {
  0, 27,                                     //  6181:    case 0x0: {
  OPC_SwitchField, 9, 2,                     //  6183:     switch Inst[10:9] {
  0, 4,                                      //  6186:     case 0x0: {
  OPC_Decode, 166, 3, 81,                    //  6188:      decode to ADDC using decoder 81
                                             //  6188:     }
  1, 4,                                      //  6192:     case 0x1: {
  OPC_Decode, 155, 3, 81,                    //  6194:      decode to ADD4 using decoder 81
                                             //  6194:     }
  2, 4,                                      //  6198:     case 0x2: {
  OPC_Decode, 171, 3, 81,                    //  6200:      decode to ADDCO using decoder 81
                                             //  6200:     }
  3, 0,                                      //  6204:     case 0x3: {
  OPC_Decode, 156, 3, 81,                    //  6206:      decode to ADD4O using decoder 81
                                             //  6206:     }
                                             //  6206:     } // switch Inst[10:9]
                                             //  6206:    }
  1, 27,                                     //  6210:    case 0x1: {
  OPC_SwitchField, 9, 2,                     //  6212:     switch Inst[10:9] {
  0, 4,                                      //  6215:     case 0x0: {
  OPC_Decode, 173, 3, 81,                    //  6217:      decode to ADDC_rec using decoder 81
                                             //  6217:     }
  1, 4,                                      //  6221:     case 0x1: {
  OPC_Decode, 159, 3, 81,                    //  6223:      decode to ADD4_rec using decoder 81
                                             //  6223:     }
  2, 4,                                      //  6227:     case 0x2: {
  OPC_Decode, 172, 3, 81,                    //  6229:      decode to ADDCO_rec using decoder 81
                                             //  6229:     }
  3, 0,                                      //  6233:     case 0x3: {
  OPC_Decode, 157, 3, 81,                    //  6235:      decode to ADD4O_rec using decoder 81
                                             //  6235:     }
                                             //  6235:     } // switch Inst[10:9]
                                             //  6235:    }
  2, 21,                                     //  6239:    case 0x2: {
  OPC_SwitchField, 9, 2,                     //  6241:     switch Inst[10:9] {
  0, 4,                                      //  6244:     case 0x0: {
  OPC_Decode, 182, 12, 81,                   //  6246:      decode to MULHWU using decoder 81
                                             //  6246:     }
  1, 4,                                      //  6250:     case 0x1: {
  OPC_Decode, 128, 12, 81,                   //  6252:      decode to MODUW using decoder 81
                                             //  6252:     }
  3, 0,                                      //  6256:     case 0x3: {
  OPC_Decode, 254, 11, 81,                   //  6258:      decode to MODSW using decoder 81
                                             //  6258:     }
                                             //  6258:     } // switch Inst[10:9]
                                             //  6258:    }
  3, 0,                                      //  6262:    case 0x3: {
  OPC_CheckField, 9, 2, 0,                   //  6264:     check Inst[10:9] == 0x0
  OPC_Decode, 183, 12, 81,                   //  6268:     decode to MULHWU_rec using decoder 81
                                             //  6268:    }
                                             //  6268:    } // switch Inst[1:0]
                                             //  6268:   }
  2, 33,                                     //  6272:   case 0x2: {
  OPC_SwitchField, 0, 2,                     //  6274:    switch Inst[1:0] {
  0, 8,                                      //  6277:    case 0x0: {
  OPC_CheckField, 9, 2, 0,                   //  6279:     check Inst[10:9] == 0x0
  OPC_Decode, 184, 3, 81,                    //  6283:     decode to ADDG6S using decoder 81
                                             //  6283:    }
  2, 8,                                      //  6287:    case 0x2: {
  OPC_CheckField, 9, 2, 0,                   //  6289:     check Inst[10:9] == 0x0
  OPC_Decode, 181, 12, 81,                   //  6293:     decode to MULHW using decoder 81
                                             //  6293:    }
  3, 0,                                      //  6297:    case 0x3: {
  OPC_CheckField, 9, 2, 0,                   //  6299:     check Inst[10:9] == 0x0
  OPC_Decode, 184, 12, 81,                   //  6303:     decode to MULHW_rec using decoder 81
                                             //  6303:    }
                                             //  6303:    } // switch Inst[1:0]
                                             //  6303:   }
  4, 71,                                     //  6307:   case 0x4: {
  OPC_SwitchField, 0, 2,                     //  6309:    switch Inst[1:0] {
  0, 15,                                     //  6312:    case 0x0: {
  OPC_SwitchField, 9, 2,                     //  6314:     switch Inst[10:9] {
  0, 4,                                      //  6317:     case 0x0: {
  OPC_Decode, 174, 3, 81,                    //  6319:      decode to ADDE using decoder 81
                                             //  6319:     }
  2, 0,                                      //  6323:     case 0x2: {
  OPC_Decode, 179, 3, 81,                    //  6325:      decode to ADDEO using decoder 81
                                             //  6325:     }
                                             //  6325:     } // switch Inst[10:9]
                                             //  6325:    }
  1, 15,                                     //  6329:    case 0x1: {
  OPC_SwitchField, 9, 2,                     //  6331:     switch Inst[10:9] {
  0, 4,                                      //  6334:     case 0x0: {
  OPC_Decode, 183, 3, 81,                    //  6336:      decode to ADDE_rec using decoder 81
                                             //  6336:     }
  2, 0,                                      //  6340:     case 0x2: {
  OPC_Decode, 180, 3, 81,                    //  6342:      decode to ADDEO_rec using decoder 81
                                             //  6342:     }
                                             //  6342:     } // switch Inst[10:9]
                                             //  6342:    }
  2, 15,                                     //  6346:    case 0x2: {
  OPC_SwitchField, 9, 2,                     //  6348:     switch Inst[10:9] {
  1, 4,                                      //  6351:     case 0x1: {
  OPC_Decode, 165, 6, 81,                    //  6353:      decode to DIVWEU using decoder 81
                                             //  6353:     }
  3, 0,                                      //  6357:     case 0x3: {
  OPC_Decode, 166, 6, 81,                    //  6359:      decode to DIVWEUO using decoder 81
                                             //  6359:     }
                                             //  6359:     } // switch Inst[10:9]
                                             //  6359:    }
  3, 0,                                      //  6363:    case 0x3: {
  OPC_SwitchField, 9, 2,                     //  6365:     switch Inst[10:9] {
  1, 4,                                      //  6368:     case 0x1: {
  OPC_Decode, 168, 6, 81,                    //  6370:      decode to DIVWEU_rec using decoder 81
                                             //  6370:     }
  3, 0,                                      //  6374:     case 0x3: {
  OPC_Decode, 167, 6, 81,                    //  6376:      decode to DIVWEUO_rec using decoder 81
                                             //  6376:     }
                                             //  6376:     } // switch Inst[10:9]
                                             //  6376:    }
                                             //  6376:    } // switch Inst[1:0]
                                             //  6376:   }
  5, 43,                                     //  6380:   case 0x5: {
  OPC_SwitchField, 0, 2,                     //  6382:    switch Inst[1:0] {
  0, 4,                                      //  6385:    case 0x0: {
  OPC_Decode, 181, 3, 85,                    //  6387:     decode to ADDEX using decoder 85
                                             //  6387:    }
  2, 15,                                     //  6391:    case 0x2: {
  OPC_SwitchField, 9, 2,                     //  6393:     switch Inst[10:9] {
  1, 4,                                      //  6396:     case 0x1: {
  OPC_Decode, 162, 6, 81,                    //  6398:      decode to DIVWE using decoder 81
                                             //  6398:     }
  3, 0,                                      //  6402:     case 0x3: {
  OPC_Decode, 163, 6, 81,                    //  6404:      decode to DIVWEO using decoder 81
                                             //  6404:     }
                                             //  6404:     } // switch Inst[10:9]
                                             //  6404:    }
  3, 0,                                      //  6408:    case 0x3: {
  OPC_SwitchField, 9, 2,                     //  6410:     switch Inst[10:9] {
  1, 4,                                      //  6413:     case 0x1: {
  OPC_Decode, 169, 6, 81,                    //  6415:      decode to DIVWE_rec using decoder 81
                                             //  6415:     }
  3, 0,                                      //  6419:     case 0x3: {
  OPC_Decode, 164, 6, 81,                    //  6421:      decode to DIVWEO_rec using decoder 81
                                             //  6421:     }
                                             //  6421:     } // switch Inst[10:9]
                                             //  6421:    }
                                             //  6421:    } // switch Inst[1:0]
                                             //  6421:   }
  6, 71,                                     //  6425:   case 0x6: {
  OPC_SwitchField, 0, 2,                     //  6427:    switch Inst[1:0] {
  0, 15,                                     //  6430:    case 0x0: {
  OPC_SwitchField, 9, 7,                     //  6432:     switch Inst[15:9] {
  0, 4,                                      //  6435:     case 0x0: {
  OPC_Decode, 223, 3, 84,                    //  6437:      decode to ADDZE using decoder 84
                                             //  6437:     }
  2, 0,                                      //  6441:     case 0x2: {
  OPC_Decode, 228, 3, 84,                    //  6443:      decode to ADDZEO using decoder 84
                                             //  6443:     }
                                             //  6443:     } // switch Inst[15:9]
                                             //  6443:    }
  1, 15,                                     //  6447:    case 0x1: {
  OPC_SwitchField, 9, 7,                     //  6449:     switch Inst[15:9] {
  0, 4,                                      //  6452:     case 0x0: {
  OPC_Decode, 230, 3, 84,                    //  6454:      decode to ADDZE_rec using decoder 84
                                             //  6454:     }
  2, 0,                                      //  6458:     case 0x2: {
  OPC_Decode, 229, 3, 84,                    //  6460:      decode to ADDZEO_rec using decoder 84
                                             //  6460:     }
                                             //  6460:     } // switch Inst[15:9]
                                             //  6460:    }
  2, 15,                                     //  6464:    case 0x2: {
  OPC_SwitchField, 9, 2,                     //  6466:     switch Inst[10:9] {
  1, 4,                                      //  6469:     case 0x1: {
  OPC_Decode, 172, 6, 81,                    //  6471:      decode to DIVWU using decoder 81
                                             //  6471:     }
  3, 0,                                      //  6475:     case 0x3: {
  OPC_Decode, 173, 6, 81,                    //  6477:      decode to DIVWUO using decoder 81
                                             //  6477:     }
                                             //  6477:     } // switch Inst[10:9]
                                             //  6477:    }
  3, 0,                                      //  6481:    case 0x3: {
  OPC_SwitchField, 9, 2,                     //  6483:     switch Inst[10:9] {
  1, 4,                                      //  6486:     case 0x1: {
  OPC_Decode, 175, 6, 81,                    //  6488:      decode to DIVWU_rec using decoder 81
                                             //  6488:     }
  3, 0,                                      //  6492:     case 0x3: {
  OPC_Decode, 174, 6, 81,                    //  6494:      decode to DIVWUO_rec using decoder 81
                                             //  6494:     }
                                             //  6494:     } // switch Inst[10:9]
                                             //  6494:    }
                                             //  6494:    } // switch Inst[1:0]
                                             //  6494:   }
  7, 0,                                      //  6498:   case 0x7: {
  OPC_SwitchField, 0, 2,                     //  6500:    switch Inst[1:0] {
  0, 15,                                     //  6503:    case 0x0: {
  OPC_SwitchField, 9, 7,                     //  6505:     switch Inst[15:9] {
  0, 4,                                      //  6508:     case 0x0: {
  OPC_Decode, 214, 3, 84,                    //  6510:      decode to ADDME using decoder 84
                                             //  6510:     }
  2, 0,                                      //  6514:     case 0x2: {
  OPC_Decode, 219, 3, 84,                    //  6516:      decode to ADDMEO using decoder 84
                                             //  6516:     }
                                             //  6516:     } // switch Inst[15:9]
                                             //  6516:    }
  1, 15,                                     //  6520:    case 0x1: {
  OPC_SwitchField, 9, 7,                     //  6522:     switch Inst[15:9] {
  0, 4,                                      //  6525:     case 0x0: {
  OPC_Decode, 221, 3, 84,                    //  6527:      decode to ADDME_rec using decoder 84
                                             //  6527:     }
  2, 0,                                      //  6531:     case 0x2: {
  OPC_Decode, 220, 3, 84,                    //  6533:      decode to ADDMEO_rec using decoder 84
                                             //  6533:     }
                                             //  6533:     } // switch Inst[15:9]
                                             //  6533:    }
  2, 27,                                     //  6537:    case 0x2: {
  OPC_SwitchField, 9, 2,                     //  6539:     switch Inst[10:9] {
  0, 4,                                      //  6542:     case 0x0: {
  OPC_Decode, 191, 12, 81,                   //  6544:      decode to MULLW using decoder 81
                                             //  6544:     }
  1, 4,                                      //  6548:     case 0x1: {
  OPC_Decode, 161, 6, 81,                    //  6550:      decode to DIVW using decoder 81
                                             //  6550:     }
  2, 4,                                      //  6554:     case 0x2: {
  OPC_Decode, 192, 12, 81,                   //  6556:      decode to MULLWO using decoder 81
                                             //  6556:     }
  3, 0,                                      //  6560:     case 0x3: {
  OPC_Decode, 170, 6, 81,                    //  6562:      decode to DIVWO using decoder 81
                                             //  6562:     }
                                             //  6562:     } // switch Inst[10:9]
                                             //  6562:    }
  3, 0,                                      //  6566:    case 0x3: {
  OPC_SwitchField, 9, 2,                     //  6568:     switch Inst[10:9] {
  0, 4,                                      //  6571:     case 0x0: {
  OPC_Decode, 194, 12, 81,                   //  6573:      decode to MULLW_rec using decoder 81
                                             //  6573:     }
  1, 4,                                      //  6577:     case 0x1: {
  OPC_Decode, 176, 6, 81,                    //  6579:      decode to DIVW_rec using decoder 81
                                             //  6579:     }
  2, 4,                                      //  6583:     case 0x2: {
  OPC_Decode, 193, 12, 81,                   //  6585:      decode to MULLWO_rec using decoder 81
                                             //  6585:     }
  3, 0,                                      //  6589:     case 0x3: {
  OPC_Decode, 171, 6, 81,                    //  6591:      decode to DIVWO_rec using decoder 81
                                             //  6591:     }
                                             //  6591:     } // switch Inst[10:9]
                                             //  6591:    }
                                             //  6591:    } // switch Inst[1:0]
                                             //  6591:   }
                                             //  6591:   } // switch Inst[8:6]
                                             //  6591:  }
  6, 189, 3,                                 //  6595:  case 0x6: {
  OPC_SwitchField, 6, 5,                     //  6598:   switch Inst[10:6] {
  0, 15,                                     //  6601:   case 0x0: {
  OPC_SwitchField, 1, 1,                     //  6603:    switch Inst[1] {
  0, 4,                                      //  6606:    case 0x0: {
  OPC_Decode, 185, 11, 86,                   //  6608:     decode to LXSIWZX using decoder 86
                                             //  6608:    }
  1, 0,                                      //  6612:    case 0x1: {
  OPC_Decode, 201, 11, 87,                   //  6614:     decode to LXVRBX using decoder 87
                                             //  6614:    }
                                             //  6614:    } // switch Inst[1]
                                             //  6614:   }
  1, 8,                                      //  6618:   case 0x1: {
  OPC_CheckField, 1, 1, 1,                   //  6620:    check Inst[1] == 0x1
  OPC_Decode, 203, 11, 87,                   //  6624:    decode to LXVRHX using decoder 87
                                             //  6624:   }
  2, 15,                                     //  6628:   case 0x2: {
  OPC_SwitchField, 1, 1,                     //  6630:    switch Inst[1] {
  0, 4,                                      //  6633:    case 0x0: {
  OPC_Decode, 184, 11, 86,                   //  6635:     decode to LXSIWAX using decoder 86
                                             //  6635:    }
  1, 0,                                      //  6639:    case 0x1: {
  OPC_Decode, 206, 11, 87,                   //  6641:     decode to LXVRWX using decoder 87
                                             //  6641:    }
                                             //  6641:    } // switch Inst[1]
                                             //  6641:   }
  3, 8,                                      //  6645:   case 0x3: {
  OPC_CheckField, 1, 1, 1,                   //  6647:    check Inst[1] == 0x1
  OPC_Decode, 202, 11, 87,                   //  6651:    decode to LXVRDX using decoder 87
                                             //  6651:   }
  4, 15,                                     //  6655:   case 0x4: {
  OPC_SwitchField, 1, 1,                     //  6657:    switch Inst[1] {
  0, 4,                                      //  6660:    case 0x0: {
  OPC_Decode, 154, 16, 86,                   //  6662:     decode to STXSIWX using decoder 86
                                             //  6662:    }
  1, 0,                                      //  6666:    case 0x1: {
  OPC_Decode, 168, 16, 87,                   //  6668:     decode to STXVRBX using decoder 87
                                             //  6668:    }
                                             //  6668:    } // switch Inst[1]
                                             //  6668:   }
  5, 8,                                      //  6672:   case 0x5: {
  OPC_CheckField, 1, 1, 1,                   //  6674:    check Inst[1] == 0x1
  OPC_Decode, 170, 16, 87,                   //  6678:    decode to STXVRHX using decoder 87
                                             //  6678:   }
  6, 8,                                      //  6682:   case 0x6: {
  OPC_CheckField, 1, 1, 1,                   //  6684:    check Inst[1] == 0x1
  OPC_Decode, 173, 16, 87,                   //  6688:    decode to STXVRWX using decoder 87
                                             //  6688:   }
  7, 8,                                      //  6692:   case 0x7: {
  OPC_CheckField, 1, 1, 1,                   //  6694:    check Inst[1] == 0x1
  OPC_Decode, 169, 16, 87,                   //  6698:    decode to STXVRDX using decoder 87
                                             //  6698:   }
  8, 15,                                     //  6702:   case 0x8: {
  OPC_SwitchField, 1, 1,                     //  6704:    switch Inst[1] {
  0, 4,                                      //  6707:    case 0x0: {
  OPC_Decode, 209, 11, 87,                   //  6709:     decode to LXVX using decoder 87
                                             //  6709:    }
  1, 0,                                      //  6713:    case 0x1: {
  OPC_Decode, 194, 11, 88,                   //  6715:     decode to LXVL using decoder 88
                                             //  6715:    }
                                             //  6715:    } // switch Inst[1]
                                             //  6715:   }
  9, 8,                                      //  6719:   case 0x9: {
  OPC_CheckField, 1, 1, 1,                   //  6721:    check Inst[1] == 0x1
  OPC_Decode, 195, 11, 88,                   //  6725:    decode to LXVLL using decoder 88
                                             //  6725:   }
  10, 19,                                    //  6729:   case 0xa: {
  OPC_SwitchField, 1, 1,                     //  6731:    switch Inst[1] {
  0, 4,                                      //  6734:    case 0x0: {
  OPC_Decode, 191, 11, 87,                   //  6736:     decode to LXVDSX using decoder 87
                                             //  6736:    }
  1, 0,                                      //  6740:    case 0x1: {
  OPC_CheckField, 0, 1, 0,                   //  6742:     check Inst[0] == 0x0
  OPC_Decode, 200, 11, 89,                   //  6746:     decode to LXVPX using decoder 89
                                             //  6746:    }
                                             //  6746:    } // switch Inst[1]
                                             //  6746:   }
  11, 8,                                     //  6750:   case 0xb: {
  OPC_CheckField, 1, 1, 0,                   //  6752:    check Inst[1] == 0x0
  OPC_Decode, 208, 11, 87,                   //  6756:    decode to LXVWSX using decoder 87
                                             //  6756:   }
  12, 15,                                    //  6760:   case 0xc: {
  OPC_SwitchField, 1, 1,                     //  6762:    switch Inst[1] {
  0, 4,                                      //  6765:    case 0x0: {
  OPC_Decode, 175, 16, 87,                   //  6767:     decode to STXVX using decoder 87
                                             //  6767:    }
  1, 0,                                      //  6771:    case 0x1: {
  OPC_Decode, 161, 16, 88,                   //  6773:     decode to STXVL using decoder 88
                                             //  6773:    }
                                             //  6773:    } // switch Inst[1]
                                             //  6773:   }
  13, 8,                                     //  6777:   case 0xd: {
  OPC_CheckField, 1, 1, 1,                   //  6779:    check Inst[1] == 0x1
  OPC_Decode, 162, 16, 88,                   //  6783:    decode to STXVLL using decoder 88
                                             //  6783:   }
  14, 8,                                     //  6787:   case 0xe: {
  OPC_CheckField, 0, 2, 2,                   //  6789:    check Inst[1:0] == 0x2
  OPC_Decode, 167, 16, 89,                   //  6793:    decode to STXVPX using decoder 89
                                             //  6793:   }
  16, 15,                                    //  6797:   case 0x10: {
  OPC_SwitchField, 1, 1,                     //  6799:    switch Inst[1] {
  0, 4,                                      //  6802:    case 0x0: {
  OPC_Decode, 187, 11, 90,                   //  6804:     decode to LXSSPX using decoder 90
                                             //  6804:    }
  1, 0,                                      //  6808:    case 0x1: {
  OPC_Decode, 204, 11, 88,                   //  6810:     decode to LXVRL using decoder 88
                                             //  6810:    }
                                             //  6810:    } // switch Inst[1]
                                             //  6810:   }
  17, 8,                                     //  6814:   case 0x11: {
  OPC_CheckField, 1, 1, 1,                   //  6816:    check Inst[1] == 0x1
  OPC_Decode, 205, 11, 88,                   //  6820:    decode to LXVRLL using decoder 88
                                             //  6820:   }
  18, 19,                                    //  6824:   case 0x12: {
  OPC_SwitchField, 1, 1,                     //  6826:    switch Inst[1] {
  0, 4,                                      //  6829:    case 0x0: {
  OPC_Decode, 181, 11, 86,                   //  6831:     decode to LXSDX using decoder 86
                                             //  6831:    }
  1, 0,                                      //  6835:    case 0x1: {
  OPC_CheckField, 0, 1, 0,                   //  6837:     check Inst[0] == 0x0
  OPC_Decode, 198, 11, 91,                   //  6841:     decode to LXVPRL using decoder 91
                                             //  6841:    }
                                             //  6841:    } // switch Inst[1]
                                             //  6841:   }
  19, 8,                                     //  6845:   case 0x13: {
  OPC_CheckField, 0, 2, 2,                   //  6847:    check Inst[1:0] == 0x2
  OPC_Decode, 199, 11, 91,                   //  6851:    decode to LXVPRLL using decoder 91
                                             //  6851:   }
  20, 15,                                    //  6855:   case 0x14: {
  OPC_SwitchField, 1, 1,                     //  6857:    switch Inst[1] {
  0, 4,                                      //  6860:    case 0x0: {
  OPC_Decode, 156, 16, 90,                   //  6862:     decode to STXSSPX using decoder 90
                                             //  6862:    }
  1, 0,                                      //  6866:    case 0x1: {
  OPC_Decode, 171, 16, 88,                   //  6868:     decode to STXVRL using decoder 88
                                             //  6868:    }
                                             //  6868:    } // switch Inst[1]
                                             //  6868:   }
  21, 8,                                     //  6872:   case 0x15: {
  OPC_CheckField, 1, 1, 1,                   //  6874:    check Inst[1] == 0x1
  OPC_Decode, 172, 16, 88,                   //  6878:    decode to STXVRLL using decoder 88
                                             //  6878:   }
  22, 19,                                    //  6882:   case 0x16: {
  OPC_SwitchField, 1, 1,                     //  6884:    switch Inst[1] {
  0, 4,                                      //  6887:    case 0x0: {
  OPC_Decode, 149, 16, 86,                   //  6889:     decode to STXSDX using decoder 86
                                             //  6889:    }
  1, 0,                                      //  6893:    case 0x1: {
  OPC_CheckField, 0, 1, 0,                   //  6895:     check Inst[0] == 0x0
  OPC_Decode, 165, 16, 91,                   //  6899:     decode to STXVPRL using decoder 91
                                             //  6899:    }
                                             //  6899:    } // switch Inst[1]
                                             //  6899:   }
  23, 8,                                     //  6903:   case 0x17: {
  OPC_CheckField, 0, 2, 2,                   //  6905:    check Inst[1:0] == 0x2
  OPC_Decode, 166, 16, 91,                   //  6909:    decode to STXVPRLL using decoder 91
                                             //  6909:   }
  24, 15,                                    //  6913:   case 0x18: {
  OPC_SwitchField, 1, 1,                     //  6915:    switch Inst[1] {
  0, 4,                                      //  6918:    case 0x0: {
  OPC_Decode, 207, 11, 87,                   //  6920:     decode to LXVW4X using decoder 87
                                             //  6920:    }
  1, 0,                                      //  6924:    case 0x1: {
  OPC_Decode, 182, 11, 86,                   //  6926:     decode to LXSIBZX using decoder 86
                                             //  6926:    }
                                             //  6926:    } // switch Inst[1]
                                             //  6926:   }
  25, 15,                                    //  6930:   case 0x19: {
  OPC_SwitchField, 1, 1,                     //  6932:    switch Inst[1] {
  0, 4,                                      //  6935:    case 0x0: {
  OPC_Decode, 192, 11, 87,                   //  6937:     decode to LXVH8X using decoder 87
                                             //  6937:    }
  1, 0,                                      //  6941:    case 0x1: {
  OPC_Decode, 183, 11, 86,                   //  6943:     decode to LXSIHZX using decoder 86
                                             //  6943:    }
                                             //  6943:    } // switch Inst[1]
                                             //  6943:   }
  26, 8,                                     //  6947:   case 0x1a: {
  OPC_CheckField, 1, 1, 0,                   //  6949:    check Inst[1] == 0x0
  OPC_Decode, 190, 11, 87,                   //  6953:    decode to LXVD2X using decoder 87
                                             //  6953:   }
  27, 19,                                    //  6957:   case 0x1b: {
  OPC_SwitchField, 1, 1,                     //  6959:    switch Inst[1] {
  0, 4,                                      //  6962:    case 0x0: {
  OPC_Decode, 189, 11, 87,                   //  6964:     decode to LXVB16X using decoder 87
                                             //  6964:    }
  1, 0,                                      //  6968:    case 0x1: {
  OPC_CheckField, 0, 1, 0,                   //  6970:     check Inst[0] == 0x0
  OPC_Decode, 197, 11, 91,                   //  6974:     decode to LXVPB32X using decoder 91
                                             //  6974:    }
                                             //  6974:    } // switch Inst[1]
                                             //  6974:   }
  28, 15,                                    //  6978:   case 0x1c: {
  OPC_SwitchField, 1, 1,                     //  6980:    switch Inst[1] {
  0, 4,                                      //  6983:    case 0x0: {
  OPC_Decode, 174, 16, 87,                   //  6985:     decode to STXVW4X using decoder 87
                                             //  6985:    }
  1, 0,                                      //  6989:    case 0x1: {
  OPC_Decode, 150, 16, 86,                   //  6991:     decode to STXSIBX using decoder 86
                                             //  6991:    }
                                             //  6991:    } // switch Inst[1]
                                             //  6991:   }
  29, 15,                                    //  6995:   case 0x1d: {
  OPC_SwitchField, 1, 1,                     //  6997:    switch Inst[1] {
  0, 4,                                      //  7000:    case 0x0: {
  OPC_Decode, 160, 16, 87,                   //  7002:     decode to STXVH8X using decoder 87
                                             //  7002:    }
  1, 0,                                      //  7006:    case 0x1: {
  OPC_Decode, 152, 16, 86,                   //  7008:     decode to STXSIHX using decoder 86
                                             //  7008:    }
                                             //  7008:    } // switch Inst[1]
                                             //  7008:   }
  30, 8,                                     //  7012:   case 0x1e: {
  OPC_CheckField, 1, 1, 0,                   //  7014:    check Inst[1] == 0x0
  OPC_Decode, 159, 16, 87,                   //  7018:    decode to STXVD2X using decoder 87
                                             //  7018:   }
  31, 0,                                     //  7022:   case 0x1f: {
  OPC_SwitchField, 1, 1,                     //  7024:    switch Inst[1] {
  0, 4,                                      //  7027:    case 0x0: {
  OPC_Decode, 158, 16, 87,                   //  7029:     decode to STXVB16X using decoder 87
                                             //  7029:    }
  1, 0,                                      //  7033:    case 0x1: {
  OPC_CheckField, 0, 1, 0,                   //  7035:     check Inst[0] == 0x0
  OPC_Decode, 164, 16, 91,                   //  7039:     decode to STXVPB32X using decoder 91
                                             //  7039:    }
                                             //  7039:    } // switch Inst[1]
                                             //  7039:   }
                                             //  7039:   } // switch Inst[10:6]
                                             //  7039:  }
  7, 157, 1,                                 //  7043:  case 0x7: {
  OPC_SwitchField, 0, 2,                     //  7046:   switch Inst[1:0] {
  0, 41,                                     //  7049:   case 0x0: {
  OPC_SwitchField, 6, 5,                     //  7051:    switch Inst[10:6] {
  9, 4,                                      //  7054:    case 0x9: {
  OPC_Decode, 218, 11, 92,                   //  7056:     decode to MFBHRBE using decoder 92
                                             //  7056:    }
  10, 4,                                     //  7060:    case 0xa: {
  OPC_Decode, 237, 11, 71,                   //  7062:     decode to MFPMR using decoder 71
                                             //  7062:    }
  13, 8,                                     //  7066:    case 0xd: {
  OPC_CheckField, 11, 15, 0,                 //  7068:     check Inst[25:11] == 0x0
  OPC_Decode, 172, 5, 0,                     //  7072:     decode to CLRBHRB using decoder 0
                                             //  7072:    }
  14, 4,                                     //  7076:    case 0xe: {
  OPC_Decode, 154, 12, 93,                   //  7078:     decode to MTPMR using decoder 93
                                             //  7078:    }
  22, 0,                                     //  7082:    case 0x16: {
  OPC_CheckField, 11, 12, 0,                 //  7084:     check Inst[22:11] == 0x0
  OPC_Decode, 235, 16, 68,                   //  7088:     decode to TCHECK using decoder 68
                                             //  7088:    }
                                             //  7088:    } // switch Inst[10:6]
                                             //  7088:   }
  1, 103,                                    //  7092:   case 0x1: {
  OPC_SwitchField, 6, 5,                     //  7094:    switch Inst[10:6] {
  20, 12,                                    //  7097:    case 0x14: {
  OPC_CheckField, 22, 4, 0,                  //  7099:     check Inst[25:22] == 0x0
  OPC_CheckField, 11, 10, 0,                 //  7103:     check Inst[20:11] == 0x0
  OPC_Decode, 233, 16, 94,                   //  7107:     decode to TBEGIN using decoder 94
                                             //  7107:    }
  21, 8,                                     //  7111:    case 0x15: {
  OPC_CheckField, 11, 14, 0,                 //  7113:     check Inst[24:11] == 0x0
  OPC_Decode, 245, 16, 95,                   //  7117:     decode to TEND using decoder 95
                                             //  7117:    }
  23, 12,                                    //  7121:    case 0x17: {
  OPC_CheckField, 22, 3, 0,                  //  7123:     check Inst[24:22] == 0x0
  OPC_CheckField, 11, 10, 0,                 //  7127:     check Inst[20:11] == 0x0
  OPC_Decode, 146, 17, 94,                   //  7131:     decode to TSR using decoder 94
                                             //  7131:    }
  24, 4,                                     //  7135:    case 0x18: {
  OPC_Decode, 225, 16, 72,                   //  7137:     decode to TABORTWC using decoder 72
                                             //  7137:    }
  25, 4,                                     //  7141:    case 0x19: {
  OPC_Decode, 223, 16, 72,                   //  7143:     decode to TABORTDC using decoder 72
                                             //  7143:    }
  26, 4,                                     //  7147:    case 0x1a: {
  OPC_Decode, 226, 16, 96,                   //  7149:     decode to TABORTWCI using decoder 96
                                             //  7149:    }
  27, 4,                                     //  7153:    case 0x1b: {
  OPC_Decode, 224, 16, 96,                   //  7155:     decode to TABORTDCI using decoder 96
                                             //  7155:    }
  28, 12,                                    //  7159:    case 0x1c: {
  OPC_CheckField, 21, 5, 0,                  //  7161:     check Inst[25:21] == 0x0
  OPC_CheckField, 11, 5, 0,                  //  7165:     check Inst[15:11] == 0x0
  OPC_Decode, 222, 16, 97,                   //  7169:     decode to TABORT using decoder 97
                                             //  7169:    }
  29, 12,                                    //  7173:    case 0x1d: {
  OPC_CheckField, 21, 5, 0,                  //  7175:     check Inst[25:21] == 0x0
  OPC_CheckField, 11, 5, 0,                  //  7179:     check Inst[15:11] == 0x0
  OPC_Decode, 145, 17, 97,                   //  7183:     decode to TRECLAIM using decoder 97
                                             //  7183:    }
  31, 0,                                     //  7187:    case 0x1f: {
  OPC_CheckField, 11, 15, 0,                 //  7189:     check Inst[25:11] == 0x0
  OPC_Decode, 144, 17, 0,                    //  7193:     decode to TRECHKPT using decoder 0
                                             //  7193:    }
                                             //  7193:    } // switch Inst[10:6]
                                             //  7193:   }
  2, 0,                                      //  7197:   case 0x2: {
  OPC_Decode, 180, 10, 98,                   //  7199:    decode to ISEL using decoder 98
                                             //  7199:   }
                                             //  7199:   } // switch Inst[1:0]
                                             //  7199:  }
  8, 145, 1,                                 //  7203:  case 0x8: {
  OPC_SwitchField, 0, 2,                     //  7206:   switch Inst[1:0] {
  0, 23,                                     //  7209:   case 0x0: {
  OPC_SwitchField, 20, 1,                    //  7211:    switch Inst[20] {
  0, 8,                                      //  7214:    case 0x0: {
  OPC_CheckField, 6, 6, 4,                   //  7216:     check Inst[11:6] == 0x4
  OPC_Decode, 131, 12, 99,                   //  7220:     decode to MTCRF using decoder 99
                                             //  7220:    }
  1, 0,                                      //  7224:    case 0x1: {
  OPC_CheckField, 6, 6, 4,                   //  7226:     check Inst[11:6] == 0x4
  OPC_Decode, 152, 12, 100,                  //  7230:     decode to MTOCRF using decoder 100
                                             //  7230:    }
                                             //  7230:    } // switch Inst[20]
                                             //  7230:   }
  2, 0,                                      //  7234:   case 0x2: {
  OPC_SwitchField, 16, 5,                    //  7236:    switch Inst[20:16] {
  0, 12,                                     //  7239:    case 0x0: {
  OPC_CheckField, 21, 2, 0,                  //  7241:     check Inst[22:21] == 0x0
  OPC_CheckField, 6, 10, 5,                  //  7245:     check Inst[15:6] == 0x5
  OPC_Decode, 141, 23, 101,                  //  7249:     decode to XXMFACC using decoder 101
                                             //  7249:    }
  1, 12,                                     //  7253:    case 0x1: {
  OPC_CheckField, 21, 2, 0,                  //  7255:     check Inst[22:21] == 0x0
  OPC_CheckField, 6, 10, 5,                  //  7259:     check Inst[15:6] == 0x5
  OPC_Decode, 145, 23, 101,                  //  7263:     decode to XXMTACC using decoder 101
                                             //  7263:    }
  2, 12,                                     //  7267:    case 0x2: {
  OPC_CheckField, 21, 2, 0,                  //  7269:     check Inst[22:21] == 0x0
  OPC_CheckField, 6, 10, 5,                  //  7273:     check Inst[15:6] == 0x5
  OPC_Decode, 178, 6, 102,                   //  7277:     decode to DMSETDMRZ using decoder 102
                                             //  7277:    }
  3, 12,                                     //  7281:    case 0x3: {
  OPC_CheckField, 21, 2, 0,                  //  7283:     check Inst[22:21] == 0x0
  OPC_CheckField, 6, 10, 5,                  //  7287:     check Inst[15:6] == 0x5
  OPC_Decode, 156, 23, 103,                  //  7291:     decode to XXSETACCZ using decoder 103
                                             //  7291:    }
  6, 12,                                     //  7295:    case 0x6: {
  OPC_CheckField, 21, 2, 0,                  //  7297:     check Inst[22:21] == 0x0
  OPC_CheckField, 6, 7, 5,                   //  7301:     check Inst[12:6] == 0x5
  OPC_Decode, 177, 6, 104,                   //  7305:     decode to DMMR using decoder 104
                                             //  7305:    }
  7, 12,                                     //  7309:    case 0x7: {
  OPC_CheckField, 21, 2, 0,                  //  7311:     check Inst[22:21] == 0x0
  OPC_CheckField, 6, 7, 5,                   //  7315:     check Inst[12:6] == 0x5
  OPC_Decode, 185, 6, 105,                   //  7319:     decode to DMXOR using decoder 105
                                             //  7319:    }
  14, 12,                                    //  7323:    case 0xe: {
  OPC_CheckField, 22, 1, 0,                  //  7325:     check Inst[22] == 0x0
  OPC_CheckField, 6, 7, 5,                   //  7329:     check Inst[12:6] == 0x5
  OPC_Decode, 179, 6, 106,                   //  7333:     decode to DMSHA2HASH using decoder 106
                                             //  7333:    }
  15, 0,                                     //  7337:    case 0xf: {
  OPC_CheckField, 21, 3, 0,                  //  7339:     check Inst[23:21] == 0x0
  OPC_CheckField, 6, 5, 5,                   //  7343:     check Inst[10:6] == 0x5
  OPC_Decode, 180, 6, 107,                   //  7347:     decode to DMSHA3HASH using decoder 107
                                             //  7347:    }
                                             //  7347:    } // switch Inst[20:16]
                                             //  7347:   }
                                             //  7347:   } // switch Inst[1:0]
                                             //  7347:  }
  9, 132, 5,                                 //  7351:  case 0x9: {
  OPC_SwitchField, 6, 5,                     //  7354:   switch Inst[10:6] {
  0, 48,                                     //  7357:   case 0x0: {
  OPC_SwitchField, 0, 2,                     //  7359:    switch Inst[1:0] {
  0, 18,                                     //  7362:    case 0x0: {
  OPC_Scope, 12,                             //  7364:     try {
  OPC_CheckField, 16, 2, 0,                  //  7366:      check Inst[17:16] == 0x0
  OPC_CheckField, 20, 1, 0,                  //  7370:      check Inst[20] == 0x0
  OPC_Decode, 249, 16, 108,                  //  7374:      decode to TLBIEIO using decoder 108
                                             //  7374:     } else try {
  OPC_Decode, 254, 16, 109,                  //  7378:      decode to TLBILX using decoder 109
                                             //  7378:     }
                                             //  7378:    }
  2, 0,                                      //  7382:    case 0x2: {
  OPC_SwitchField, 20, 1,                    //  7384:     switch Inst[20] {
  0, 8,                                      //  7387:     case 0x0: {
  OPC_CheckField, 11, 9, 0,                  //  7389:      check Inst[19:11] == 0x0
  OPC_Decode, 219, 11, 69,                   //  7393:      decode to MFCR using decoder 69
                                             //  7393:     }
  1, 0,                                      //  7397:     case 0x1: {
  OPC_CheckField, 11, 1, 0,                  //  7399:      check Inst[11] == 0x0
  OPC_Decode, 235, 11, 110,                  //  7403:      decode to MFOCRF using decoder 110
                                             //  7403:     }
                                             //  7403:     } // switch Inst[20]
                                             //  7403:    }
                                             //  7403:    } // switch Inst[1:0]
                                             //  7403:   }
  1, 27,                                     //  7407:   case 0x1: {
  OPC_SwitchField, 1, 1,                     //  7409:    switch Inst[1] {
  0, 12,                                     //  7412:    case 0x0: {
  OPC_CheckField, 20, 1, 0,                  //  7414:     check Inst[20] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  7418:     check Inst[0] == 0x0
  OPC_Decode, 251, 16, 111,                  //  7422:     decode to TLBIEP using decoder 111
                                             //  7422:    }
  1, 0,                                      //  7426:    case 0x1: {
  OPC_CheckField, 11, 5, 0,                  //  7428:     check Inst[15:11] == 0x0
  OPC_Decode, 250, 11, 112,                  //  7432:     decode to MFVSRD using decoder 112
                                             //  7432:    }
                                             //  7432:    } // switch Inst[1]
                                             //  7432:   }
  2, 12,                                     //  7436:   case 0x2: {
  OPC_CheckField, 11, 10, 0,                 //  7438:    check Inst[20:11] == 0x0
  OPC_CheckField, 0, 2, 2,                   //  7442:    check Inst[1:0] == 0x2
  OPC_Decode, 234, 11, 69,                   //  7446:    decode to MFMSR using decoder 69
                                             //  7446:   }
  3, 12,                                     //  7450:   case 0x3: {
  OPC_CheckField, 11, 5, 0,                  //  7452:    check Inst[15:11] == 0x0
  OPC_CheckField, 1, 1, 1,                   //  7456:    check Inst[1] == 0x1
  OPC_Decode, 252, 11, 113,                  //  7460:    decode to MFVSRWZ using decoder 113
                                             //  7460:   }
  4, 8,                                      //  7464:   case 0x4: {
  OPC_CheckField, 1, 1, 0,                   //  7466:    check Inst[1] == 0x0
  OPC_Decode, 150, 12, 114,                  //  7470:    decode to MTMSR using decoder 114
                                             //  7470:   }
  5, 19,                                     //  7474:   case 0x5: {
  OPC_SwitchField, 1, 1,                     //  7476:    switch Inst[1] {
  0, 4,                                      //  7479:    case 0x0: {
  OPC_Decode, 151, 12, 114,                  //  7481:     decode to MTMSRD using decoder 114
                                             //  7481:    }
  1, 0,                                      //  7485:    case 0x1: {
  OPC_CheckField, 11, 5, 0,                  //  7487:     check Inst[15:11] == 0x0
  OPC_Decode, 168, 12, 115,                  //  7491:     decode to MTVSRD using decoder 115
                                             //  7491:    }
                                             //  7491:    } // switch Inst[1]
                                             //  7491:   }
  6, 19,                                     //  7495:   case 0x6: {
  OPC_SwitchField, 1, 1,                     //  7497:    switch Inst[1] {
  0, 4,                                      //  7500:    case 0x0: {
  OPC_Decode, 157, 12, 116,                  //  7502:     decode to MTSR using decoder 116
                                             //  7502:    }
  1, 0,                                      //  7506:    case 0x1: {
  OPC_CheckField, 11, 5, 0,                  //  7508:     check Inst[15:11] == 0x0
  OPC_Decode, 173, 12, 117,                  //  7512:     decode to MTVSRWA using decoder 117
                                             //  7512:    }
                                             //  7512:    } // switch Inst[1]
                                             //  7512:   }
  7, 19,                                     //  7516:   case 0x7: {
  OPC_SwitchField, 1, 1,                     //  7518:    switch Inst[1] {
  0, 4,                                      //  7521:    case 0x0: {
  OPC_Decode, 158, 12, 118,                  //  7523:     decode to MTSRIN using decoder 118
                                             //  7523:    }
  1, 0,                                      //  7527:    case 0x1: {
  OPC_CheckField, 11, 5, 0,                  //  7529:     check Inst[15:11] == 0x0
  OPC_Decode, 176, 12, 117,                  //  7533:     decode to MTVSRWZ using decoder 117
                                             //  7533:    }
                                             //  7533:    } // switch Inst[1]
                                             //  7533:   }
  8, 23,                                     //  7537:   case 0x8: {
  OPC_SwitchField, 0, 2,                     //  7539:    switch Inst[1:0] {
  0, 8,                                      //  7542:    case 0x0: {
  OPC_CheckField, 16, 10, 0,                 //  7544:     check Inst[25:16] == 0x0
  OPC_Decode, 250, 16, 119,                  //  7548:     decode to TLBIEL using decoder 119
                                             //  7548:    }
  2, 0,                                      //  7552:    case 0x2: {
  OPC_CheckField, 16, 5, 0,                  //  7554:     check Inst[20:16] == 0x0
  OPC_Decode, 146, 12, 120,                  //  7558:     decode to MTLPL using decoder 120
                                             //  7558:    }
                                             //  7558:    } // switch Inst[1:0]
                                             //  7558:   }
  9, 37,                                     //  7562:   case 0x9: {
  OPC_SwitchField, 1, 1,                     //  7564:    switch Inst[1] {
  0, 22,                                     //  7567:    case 0x0: {
  OPC_CheckField, 0, 1, 0,                   //  7569:     check Inst[0] == 0x0
  OPC_CheckField, 20, 1, 0,                  //  7573:     check Inst[20] == 0x0
  OPC_Scope, 8,                              //  7577:     try {
  OPC_CheckField, 16, 4, 0,                  //  7579:      check Inst[19:16] == 0x0
  OPC_Decode, 247, 16, 118,                  //  7583:      decode to TLBIE using decoder 118
                                             //  7583:     } else try {
  OPC_Decode, 253, 16, 111,                  //  7587:      decode to TLBIEP9 using decoder 111
                                             //  7587:     }
                                             //  7587:    }
  1, 0,                                      //  7591:    case 0x1: {
  OPC_CheckField, 11, 5, 0,                  //  7593:     check Inst[15:11] == 0x0
  OPC_Decode, 251, 11, 121,                  //  7597:     decode to MFVSRLD using decoder 121
                                             //  7597:    }
                                             //  7597:    } // switch Inst[1]
                                             //  7597:   }
  10, 44,                                    //  7601:   case 0xa: {
  OPC_SwitchField, 0, 2,                     //  7603:    switch Inst[1:0] {
  0, 8,                                      //  7606:    case 0x0: {
  OPC_CheckField, 11, 15, 0,                 //  7608:     check Inst[25:11] == 0x0
  OPC_Decode, 157, 15, 0,                    //  7612:     decode to SLBSYNC using decoder 0
                                             //  7612:    }
  2, 0,                                      //  7616:    case 0x2: {
  OPC_Scope, 23,                             //  7618:     try {
  OPC_SwitchField, 11, 10,                   //  7620:      switch Inst[20:11] {
  96, 4,                                     //  7623:      case 0x60: {
  OPC_Decode, 244, 11, 69,                   //  7625:       decode to MFUDSCR using decoder 69
                                             //  7625:      }
  128, 2, 4,                                 //  7629:      case 0x100: {
  OPC_Decode, 232, 11, 69,                   //  7632:       decode to MFLR using decoder 69
                                             //  7632:      }
  160, 2, 0,                                 //  7636:      case 0x120: {
  OPC_Decode, 221, 11, 69,                   //  7639:       decode to MFCTR using decoder 69
                                             //  7639:      }
                                             //  7639:      } // switch Inst[20:11]
                                             //  7639:     } else try {
  OPC_Decode, 238, 11, 71,                   //  7643:      decode to MFSPR using decoder 71
                                             //  7643:     }
                                             //  7643:    }
                                             //  7643:    } // switch Inst[1:0]
                                             //  7643:   }
  11, 19,                                    //  7647:   case 0xb: {
  OPC_SwitchField, 0, 2,                     //  7649:    switch Inst[1:0] {
  0, 8,                                      //  7652:    case 0x0: {
  OPC_CheckField, 11, 15, 0,                 //  7654:     check Inst[25:11] == 0x0
  OPC_Decode, 246, 16, 0,                    //  7658:     decode to TLBIA using decoder 0
                                             //  7658:    }
  2, 0,                                      //  7662:    case 0x2: {
  OPC_Decode, 242, 11, 71,                   //  7664:     decode to MFTB using decoder 71
                                             //  7664:    }
                                             //  7664:    } // switch Inst[1:0]
                                             //  7664:   }
  12, 27,                                    //  7668:   case 0xc: {
  OPC_SwitchField, 1, 1,                     //  7670:    switch Inst[1] {
  0, 12,                                     //  7673:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  //  7675:     check Inst[20:16] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  7679:     check Inst[0] == 0x0
  OPC_Decode, 156, 15, 118,                  //  7683:     decode to SLBMTE using decoder 118
                                             //  7683:    }
  1, 0,                                      //  7687:    case 0x1: {
  OPC_CheckField, 11, 5, 0,                  //  7689:     check Inst[15:11] == 0x0
  OPC_Decode, 175, 12, 122,                  //  7693:     decode to MTVSRWS using decoder 122
                                             //  7693:    }
                                             //  7693:    } // switch Inst[1]
                                             //  7693:   }
  13, 23,                                    //  7697:   case 0xd: {
  OPC_SwitchField, 1, 1,                     //  7699:    switch Inst[1] {
  0, 12,                                     //  7702:    case 0x0: {
  OPC_CheckField, 16, 10, 0,                 //  7704:     check Inst[25:16] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  7708:     check Inst[0] == 0x0
  OPC_Decode, 152, 15, 119,                  //  7712:     decode to SLBIE using decoder 119
                                             //  7712:    }
  1, 0,                                      //  7716:    case 0x1: {
  OPC_Decode, 169, 12, 123,                  //  7718:     decode to MTVSRDD using decoder 123
                                             //  7718:    }
                                             //  7718:    } // switch Inst[1]
                                             //  7718:   }
  14, 44,                                    //  7722:   case 0xe: {
  OPC_SwitchField, 0, 2,                     //  7724:    switch Inst[1:0] {
  0, 8,                                      //  7727:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  //  7729:     check Inst[20:16] == 0x0
  OPC_Decode, 153, 15, 118,                  //  7733:     decode to SLBIEG using decoder 118
                                             //  7733:    }
  2, 0,                                      //  7737:    case 0x2: {
  OPC_Scope, 23,                             //  7739:     try {
  OPC_SwitchField, 11, 10,                   //  7741:      switch Inst[20:11] {
  96, 4,                                     //  7744:      case 0x60: {
  OPC_Decode, 159, 12, 69,                   //  7746:       decode to MTUDSCR using decoder 69
                                             //  7746:      }
  128, 2, 4,                                 //  7750:      case 0x100: {
  OPC_Decode, 148, 12, 69,                   //  7753:       decode to MTLR using decoder 69
                                             //  7753:      }
  160, 2, 0,                                 //  7757:      case 0x120: {
  OPC_Decode, 133, 12, 69,                   //  7760:       decode to MTCTR using decoder 69
                                             //  7760:      }
                                             //  7760:      } // switch Inst[20:11]
                                             //  7760:     } else try {
  OPC_Decode, 155, 12, 93,                   //  7764:      decode to MTSPR using decoder 93
                                             //  7764:     }
                                             //  7764:    }
                                             //  7764:    } // switch Inst[1:0]
                                             //  7764:   }
  15, 12,                                    //  7768:   case 0xf: {
  OPC_CheckField, 11, 15, 0,                 //  7770:    check Inst[25:11] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  7774:    check Inst[1:0] == 0x0
  OPC_Decode, 151, 15, 0,                    //  7778:    decode to SLBIA using decoder 0
                                             //  7778:   }
  18, 8,                                     //  7782:   case 0x12: {
  OPC_CheckField, 1, 1, 1,                   //  7784:    check Inst[1] == 0x1
  OPC_Decode, 240, 11, 116,                  //  7788:    decode to MFSR using decoder 116
                                             //  7788:   }
  20, 15,                                    //  7792:   case 0x14: {
  OPC_SwitchField, 1, 1,                     //  7794:    switch Inst[1] {
  0, 4,                                      //  7797:    case 0x0: {
  OPC_Decode, 170, 10, 124,                  //  7799:     decode to HASHSTP using decoder 124
                                             //  7799:    }
  1, 0,                                      //  7803:    case 0x1: {
  OPC_Decode, 241, 11, 118,                  //  7805:     decode to MFSRIN using decoder 118
                                             //  7805:    }
                                             //  7805:    } // switch Inst[1]
                                             //  7805:   }
  21, 8,                                     //  7809:   case 0x15: {
  OPC_CheckField, 1, 1, 0,                   //  7811:    check Inst[1] == 0x0
  OPC_Decode, 166, 10, 124,                  //  7815:    decode to HASHCHKP using decoder 124
                                             //  7815:   }
  22, 8,                                     //  7819:   case 0x16: {
  OPC_CheckField, 1, 1, 0,                   //  7821:    check Inst[1] == 0x0
  OPC_Decode, 168, 10, 124,                  //  7825:    decode to HASHST using decoder 124
                                             //  7825:   }
  23, 27,                                    //  7829:   case 0x17: {
  OPC_SwitchField, 1, 1,                     //  7831:    switch Inst[1] {
  0, 4,                                      //  7834:    case 0x0: {
  OPC_Decode, 164, 10, 124,                  //  7836:     decode to HASHCHK using decoder 124
                                             //  7836:    }
  1, 0,                                      //  7840:    case 0x1: {
  OPC_CheckField, 18, 3, 0,                  //  7842:     check Inst[20:18] == 0x0
  OPC_CheckField, 11, 5, 0,                  //  7846:     check Inst[15:11] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  7850:     check Inst[0] == 0x0
  OPC_Decode, 223, 5, 125,                   //  7854:     decode to DARN using decoder 125
                                             //  7854:    }
                                             //  7854:    } // switch Inst[1]
                                             //  7854:   }
  24, 12,                                    //  7858:   case 0x18: {
  OPC_CheckField, 21, 5, 0,                  //  7860:    check Inst[25:21] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  7864:    check Inst[1:0] == 0x0
  OPC_Decode, 255, 16, 76,                   //  7868:    decode to TLBIVAX using decoder 76
                                             //  7868:   }
  26, 12,                                    //  7872:   case 0x1a: {
  OPC_CheckField, 16, 5, 0,                  //  7874:    check Inst[20:16] == 0x0
  OPC_CheckField, 0, 2, 2,                   //  7878:    check Inst[1:0] == 0x2
  OPC_Decode, 155, 15, 118,                  //  7882:    decode to SLBMFEV using decoder 118
                                             //  7882:   }
  28, 35,                                    //  7886:   case 0x1c: {
  OPC_SwitchField, 0, 2,                     //  7888:    switch Inst[1:0] {
  0, 14,                                     //  7891:    case 0x0: {
  OPC_Scope, 8,                              //  7893:     try {
  OPC_CheckField, 21, 5, 0,                  //  7895:      check Inst[25:21] == 0x0
  OPC_Decode, 132, 17, 76,                   //  7899:      decode to TLBSX using decoder 76
                                             //  7899:     } else try {
  OPC_Decode, 133, 17, 81,                   //  7903:      decode to TLBSX2 using decoder 81
                                             //  7903:     }
                                             //  7903:    }
  1, 4,                                      //  7907:    case 0x1: {
  OPC_Decode, 134, 17, 81,                   //  7909:     decode to TLBSX2D using decoder 81
                                             //  7909:    }
  2, 0,                                      //  7913:    case 0x2: {
  OPC_CheckField, 16, 5, 0,                  //  7915:     check Inst[20:16] == 0x0
  OPC_Decode, 154, 15, 118,                  //  7919:     decode to SLBMFEE using decoder 118
                                             //  7919:    }
                                             //  7919:    } // switch Inst[1:0]
                                             //  7919:   }
  29, 18,                                    //  7923:   case 0x1d: {
  OPC_CheckField, 0, 2, 0,                   //  7925:    check Inst[1:0] == 0x0
  OPC_Scope, 8,                              //  7929:    try {
  OPC_CheckField, 11, 15, 0,                 //  7931:     check Inst[25:11] == 0x0
  OPC_Decode, 130, 17, 0,                    //  7935:     decode to TLBRE using decoder 0
                                             //  7935:    } else try {
  OPC_Decode, 131, 17, 126,                  //  7939:     decode to TLBRE2 using decoder 126
                                             //  7939:    }
                                             //  7939:   }
  30, 39,                                    //  7943:   case 0x1e: {
  OPC_SwitchField, 0, 2,                     //  7945:    switch Inst[1:0] {
  0, 24,                                     //  7948:    case 0x0: {
  OPC_Scope, 8,                              //  7950:     try {
  OPC_CheckField, 11, 15, 0,                 //  7952:      check Inst[25:11] == 0x0
  OPC_Decode, 137, 17, 0,                    //  7956:      decode to TLBWE using decoder 0
  OPC_Scope, 8,                              //  7960:     } else try {
  OPC_CheckField, 16, 10, 0,                 //  7962:      check Inst[25:16] == 0x0
  OPC_Decode, 128, 17, 119,                  //  7966:      decode to TLBLD using decoder 119
                                             //  7966:     } else try {
  OPC_Decode, 138, 17, 126,                  //  7970:      decode to TLBWE2 using decoder 126
                                             //  7970:     }
                                             //  7970:    }
  3, 0,                                      //  7974:    case 0x3: {
  OPC_CheckField, 16, 5, 0,                  //  7976:     check Inst[20:16] == 0x0
  OPC_Decode, 150, 15, 118,                  //  7980:     decode to SLBFEE_rec using decoder 118
                                             //  7980:    }
                                             //  7980:    } // switch Inst[1:0]
                                             //  7980:   }
  31, 0,                                     //  7984:   case 0x1f: {
  OPC_CheckField, 16, 10, 0,                 //  7986:    check Inst[25:16] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  7990:    check Inst[1:0] == 0x0
  OPC_Decode, 129, 17, 119,                  //  7994:    decode to TLBLI using decoder 119
                                             //  7994:   }
                                             //  7994:   } // switch Inst[10:6]
                                             //  7994:  }
  10, 171, 2,                                //  7998:  case 0xa: {
  OPC_SwitchField, 6, 5,                     //  8001:   switch Inst[10:6] {
  0, 22,                                     //  8004:   case 0x0: {
  OPC_SwitchField, 0, 2,                     //  8006:    switch Inst[1:0] {
  0, 4,                                      //  8009:    case 0x0: {
  OPC_Decode, 152, 11, 127,                  //  8011:     decode to LWARX using decoder 127
                                             //  8011:    }
  1, 4,                                      //  8015:    case 0x1: {
  OPC_Decode, 153, 11, 127,                  //  8017:     decode to LWARXL using decoder 127
                                             //  8017:    }
  2, 0,                                      //  8021:    case 0x2: {
  OPC_Decode, 209, 10, 128, 1,               //  8023:     decode to LDX using decoder 128
                                             //  8023:    }
                                             //  8023:    } // switch Inst[1:0]
                                             //  8023:   }
  1, 22,                                     //  8028:   case 0x1: {
  OPC_SwitchField, 0, 2,                     //  8030:    switch Inst[1:0] {
  0, 4,                                      //  8033:    case 0x0: {
  OPC_Decode, 185, 10, 127,                  //  8035:     decode to LBARX using decoder 127
                                             //  8035:    }
  1, 4,                                      //  8039:    case 0x1: {
  OPC_Decode, 186, 10, 127,                  //  8041:     decode to LBARXL using decoder 127
                                             //  8041:    }
  2, 0,                                      //  8045:    case 0x2: {
  OPC_Decode, 208, 10, 129, 1,               //  8047:     decode to LDUX using decoder 129
                                             //  8047:    }
                                             //  8047:    } // switch Inst[1:0]
                                             //  8047:   }
  2, 17,                                     //  8052:   case 0x2: {
  OPC_SwitchField, 0, 2,                     //  8054:    switch Inst[1:0] {
  0, 5,                                      //  8057:    case 0x0: {
  OPC_Decode, 201, 10, 128, 1,               //  8059:     decode to LDARX using decoder 128
                                             //  8059:    }
  1, 0,                                      //  8064:    case 0x1: {
  OPC_Decode, 202, 10, 128, 1,               //  8066:     decode to LDARXL using decoder 128
                                             //  8066:    }
                                             //  8066:    } // switch Inst[1:0]
                                             //  8066:   }
  3, 15,                                     //  8071:   case 0x3: {
  OPC_SwitchField, 0, 2,                     //  8073:    switch Inst[1:0] {
  0, 4,                                      //  8076:    case 0x0: {
  OPC_Decode, 236, 10, 127,                  //  8078:     decode to LHARX using decoder 127
                                             //  8078:    }
  1, 0,                                      //  8082:    case 0x1: {
  OPC_Decode, 237, 10, 127,                  //  8084:     decode to LHARXL using decoder 127
                                             //  8084:    }
                                             //  8084:    } // switch Inst[1:0]
                                             //  8084:   }
  4, 9,                                      //  8088:   case 0x4: {
  OPC_CheckField, 0, 2, 2,                   //  8090:    check Inst[1:0] == 0x2
  OPC_Decode, 217, 15, 128, 1,               //  8094:    decode to STDX using decoder 128
                                             //  8094:   }
  5, 9,                                      //  8099:   case 0x5: {
  OPC_CheckField, 0, 2, 2,                   //  8101:    check Inst[1:0] == 0x2
  OPC_Decode, 216, 15, 130, 1,               //  8105:    decode to STDUX using decoder 130
                                             //  8105:   }
  8, 17,                                     //  8110:   case 0x8: {
  OPC_SwitchField, 0, 2,                     //  8112:    switch Inst[1:0] {
  0, 5,                                      //  8115:    case 0x0: {
  OPC_Decode, 140, 11, 131, 1,               //  8117:     decode to LQARX using decoder 131
                                             //  8117:    }
  1, 0,                                      //  8122:    case 0x1: {
  OPC_Decode, 141, 11, 131, 1,               //  8124:     decode to LQARXL using decoder 131
                                             //  8124:    }
                                             //  8124:    } // switch Inst[1:0]
                                             //  8124:   }
  10, 9,                                     //  8129:   case 0xa: {
  OPC_CheckField, 0, 2, 2,                   //  8131:    check Inst[1:0] == 0x2
  OPC_Decode, 157, 11, 128, 1,               //  8135:    decode to LWAX using decoder 128
                                             //  8135:   }
  11, 9,                                     //  8140:   case 0xb: {
  OPC_CheckField, 0, 2, 2,                   //  8142:    check Inst[1:0] == 0x2
  OPC_Decode, 156, 11, 129, 1,               //  8146:    decode to LWAUX using decoder 129
                                             //  8146:   }
  16, 9,                                     //  8151:   case 0x10: {
  OPC_CheckField, 0, 2, 0,                   //  8153:    check Inst[1:0] == 0x0
  OPC_Decode, 205, 10, 128, 1,               //  8157:    decode to LDBRX using decoder 128
                                             //  8157:   }
  17, 13,                                    //  8162:   case 0x11: {
  OPC_CheckField, 11, 10, 0,                 //  8164:    check Inst[20:11] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  8168:    check Inst[1:0] == 0x0
  OPC_Decode, 136, 17, 132, 1,               //  8172:    decode to TLBSYNCIO using decoder 132
                                             //  8172:   }
  18, 20,                                    //  8177:   case 0x12: {
  OPC_SwitchField, 0, 2,                     //  8179:    switch Inst[1:0] {
  0, 9,                                      //  8182:    case 0x0: {
  OPC_CheckField, 11, 10, 0,                 //  8184:     check Inst[20:11] == 0x0
  OPC_Decode, 196, 14, 132, 1,               //  8188:     decode to PTESYNCIO using decoder 132
                                             //  8188:    }
  2, 0,                                      //  8193:    case 0x2: {
  OPC_Decode, 143, 11, 78,                   //  8195:     decode to LSWI using decoder 78
                                             //  8195:    }
                                             //  8195:    } // switch Inst[1:0]
                                             //  8195:   }
  20, 9,                                     //  8199:   case 0x14: {
  OPC_CheckField, 0, 2, 0,                   //  8201:    check Inst[1:0] == 0x0
  OPC_Decode, 212, 15, 128, 1,               //  8205:    decode to STDBRX using decoder 128
                                             //  8205:   }
  22, 8,                                     //  8210:   case 0x16: {
  OPC_CheckField, 0, 2, 2,                   //  8212:    check Inst[1:0] == 0x2
  OPC_Decode, 254, 15, 78,                   //  8216:    decode to STSWI using decoder 78
                                             //  8216:   }
  24, 8,                                     //  8220:   case 0x18: {
  OPC_CheckField, 0, 2, 2,                   //  8222:    check Inst[1:0] == 0x2
  OPC_Decode, 168, 11, 81,                   //  8226:    decode to LWZCIX using decoder 81
                                             //  8226:   }
  25, 8,                                     //  8230:   case 0x19: {
  OPC_CheckField, 0, 2, 2,                   //  8232:    check Inst[1:0] == 0x2
  OPC_Decode, 252, 10, 81,                   //  8236:    decode to LHZCIX using decoder 81
                                             //  8236:   }
  26, 8,                                     //  8240:   case 0x1a: {
  OPC_CheckField, 0, 2, 2,                   //  8242:    check Inst[1:0] == 0x2
  OPC_Decode, 190, 10, 81,                   //  8246:    decode to LBZCIX using decoder 81
                                             //  8246:   }
  27, 8,                                     //  8250:   case 0x1b: {
  OPC_CheckField, 0, 2, 2,                   //  8252:    check Inst[1:0] == 0x2
  OPC_Decode, 206, 10, 81,                   //  8256:    decode to LDCIX using decoder 81
                                             //  8256:   }
  28, 8,                                     //  8260:   case 0x1c: {
  OPC_CheckField, 0, 2, 2,                   //  8262:    check Inst[1:0] == 0x2
  OPC_Decode, 136, 16, 81,                   //  8266:    decode to STWCIX using decoder 81
                                             //  8266:   }
  29, 8,                                     //  8270:   case 0x1d: {
  OPC_CheckField, 0, 2, 2,                   //  8272:    check Inst[1:0] == 0x2
  OPC_Decode, 237, 15, 81,                   //  8276:    decode to STHCIX using decoder 81
                                             //  8276:   }
  30, 8,                                     //  8280:   case 0x1e: {
  OPC_CheckField, 0, 2, 2,                   //  8282:    check Inst[1:0] == 0x2
  OPC_Decode, 198, 15, 81,                   //  8286:    decode to STBCIX using decoder 81
                                             //  8286:   }
  31, 0,                                     //  8290:   case 0x1f: {
  OPC_CheckField, 0, 2, 2,                   //  8292:    check Inst[1:0] == 0x2
  OPC_Decode, 213, 15, 81,                   //  8296:    decode to STDCIX using decoder 81
                                             //  8296:   }
                                             //  8296:   } // switch Inst[10:6]
                                             //  8296:  }
  11, 228, 4,                                //  8300:  case 0xb: {
  OPC_SwitchField, 6, 5,                     //  8303:   switch Inst[10:6] {
  0, 19,                                     //  8306:   case 0x0: {
  OPC_SwitchField, 0, 2,                     //  8308:    switch Inst[1:0] {
  0, 8,                                      //  8311:    case 0x0: {
  OPC_CheckField, 25, 1, 0,                  //  8313:     check Inst[25] == 0x0
  OPC_Decode, 177, 10, 75,                   //  8317:     decode to ICBT using decoder 75
                                             //  8317:    }
  2, 0,                                      //  8321:    case 0x2: {
  OPC_Decode, 173, 11, 127,                  //  8323:     decode to LWZX using decoder 127
                                             //  8323:    }
                                             //  8323:    } // switch Inst[1:0]
                                             //  8323:   }
  1, 21,                                     //  8327:   case 0x1: {
  OPC_SwitchField, 0, 2,                     //  8329:    switch Inst[1:0] {
  0, 9,                                      //  8332:    case 0x0: {
  OPC_CheckField, 21, 5, 0,                  //  8334:     check Inst[25:21] == 0x0
  OPC_Decode, 228, 5, 133, 1,                //  8338:     decode to DCBST using decoder 133
                                             //  8338:    }
  2, 0,                                      //  8343:    case 0x2: {
  OPC_Decode, 171, 11, 134, 1,               //  8345:     decode to LWZUX using decoder 134
                                             //  8345:    }
                                             //  8345:    } // switch Inst[1:0]
                                             //  8345:   }
  2, 16,                                     //  8350:   case 0x2: {
  OPC_SwitchField, 0, 2,                     //  8352:    switch Inst[1:0] {
  0, 5,                                      //  8355:    case 0x0: {
  OPC_Decode, 225, 5, 135, 1,                //  8357:     decode to DCBF using decoder 135
                                             //  8357:    }
  2, 0,                                      //  8362:    case 0x2: {
  OPC_Decode, 195, 10, 127,                  //  8364:     decode to LBZX using decoder 127
                                             //  8364:    }
                                             //  8364:    } // switch Inst[1:0]
                                             //  8364:   }
  3, 9,                                      //  8368:   case 0x3: {
  OPC_CheckField, 0, 2, 2,                   //  8370:    check Inst[1:0] == 0x2
  OPC_Decode, 193, 10, 134, 1,               //  8374:    decode to LBZUX using decoder 134
                                             //  8374:   }
  4, 15,                                     //  8379:   case 0x4: {
  OPC_SwitchField, 0, 2,                     //  8381:    switch Inst[1:0] {
  1, 4,                                      //  8384:    case 0x1: {
  OPC_Decode, 137, 16, 127,                  //  8386:     decode to STWCX using decoder 127
                                             //  8386:    }
  2, 0,                                      //  8390:    case 0x2: {
  OPC_Decode, 143, 16, 127,                  //  8392:     decode to STWX using decoder 127
                                             //  8392:    }
                                             //  8392:    } // switch Inst[1:0]
                                             //  8392:   }
  5, 17,                                     //  8396:   case 0x5: {
  OPC_SwitchField, 0, 2,                     //  8398:    switch Inst[1:0] {
  1, 5,                                      //  8401:    case 0x1: {
  OPC_Decode, 252, 15, 131, 1,               //  8403:     decode to STQCX using decoder 131
                                             //  8403:    }
  2, 0,                                      //  8408:    case 0x2: {
  OPC_Decode, 141, 16, 136, 1,               //  8410:     decode to STWUX using decoder 136
                                             //  8410:    }
                                             //  8410:    } // switch Inst[1:0]
                                             //  8410:   }
  6, 16,                                     //  8415:   case 0x6: {
  OPC_SwitchField, 0, 2,                     //  8417:    switch Inst[1:0] {
  1, 5,                                      //  8420:    case 0x1: {
  OPC_Decode, 214, 15, 128, 1,               //  8422:     decode to STDCX using decoder 128
                                             //  8422:    }
  2, 0,                                      //  8427:    case 0x2: {
  OPC_Decode, 205, 15, 127,                  //  8429:     decode to STBX using decoder 127
                                             //  8429:    }
                                             //  8429:    } // switch Inst[1:0]
                                             //  8429:   }
  7, 17,                                     //  8433:   case 0x7: {
  OPC_SwitchField, 0, 2,                     //  8435:    switch Inst[1:0] {
  0, 5,                                      //  8438:    case 0x0: {
  OPC_Decode, 232, 5, 137, 1,                //  8440:     decode to DCBTST using decoder 137
                                             //  8440:    }
  2, 0,                                      //  8445:    case 0x2: {
  OPC_Decode, 203, 15, 136, 1,               //  8447:     decode to STBUX using decoder 136
                                             //  8447:    }
                                             //  8447:    } // switch Inst[1:0]
                                             //  8447:   }
  8, 16,                                     //  8452:   case 0x8: {
  OPC_SwitchField, 0, 2,                     //  8454:    switch Inst[1:0] {
  0, 5,                                      //  8457:    case 0x0: {
  OPC_Decode, 230, 5, 137, 1,                //  8459:     decode to DCBT using decoder 137
                                             //  8459:    }
  2, 0,                                      //  8464:    case 0x2: {
  OPC_Decode, 129, 11, 127,                  //  8466:     decode to LHZX using decoder 127
                                             //  8466:    }
                                             //  8466:    } // switch Inst[1:0]
                                             //  8466:   }
  9, 9,                                      //  8470:   case 0x9: {
  OPC_CheckField, 0, 2, 2,                   //  8472:    check Inst[1:0] == 0x2
  OPC_Decode, 255, 10, 134, 1,               //  8476:    decode to LHZUX using decoder 134
                                             //  8476:   }
  10, 28,                                    //  8481:   case 0xa: {
  OPC_SwitchField, 0, 2,                     //  8483:    switch Inst[1:0] {
  0, 17,                                     //  8486:    case 0x0: {
  OPC_SwitchField, 23, 3,                    //  8488:     switch Inst[25:23] {
  0, 5,                                      //  8491:     case 0x0: {
  OPC_Decode, 241, 6, 138, 1,                //  8493:      decode to DST using decoder 138
                                             //  8493:     }
  4, 0,                                      //  8498:     case 0x4: {
  OPC_Decode, 247, 6, 138, 1,                //  8500:      decode to DSTT using decoder 138
                                             //  8500:     }
                                             //  8500:     } // switch Inst[25:23]
                                             //  8500:    }
  2, 0,                                      //  8505:    case 0x2: {
  OPC_Decode, 242, 10, 127,                  //  8507:     decode to LHAX using decoder 127
                                             //  8507:    }
                                             //  8507:    } // switch Inst[1:0]
                                             //  8507:   }
  11, 29,                                    //  8511:   case 0xb: {
  OPC_SwitchField, 0, 2,                     //  8513:    switch Inst[1:0] {
  0, 17,                                     //  8516:    case 0x0: {
  OPC_SwitchField, 23, 3,                    //  8518:     switch Inst[25:23] {
  0, 5,                                      //  8521:     case 0x0: {
  OPC_Decode, 243, 6, 138, 1,                //  8523:      decode to DSTST using decoder 138
                                             //  8523:     }
  4, 0,                                      //  8528:     case 0x4: {
  OPC_Decode, 245, 6, 138, 1,                //  8530:      decode to DSTSTT using decoder 138
                                             //  8530:     }
                                             //  8530:     } // switch Inst[25:23]
                                             //  8530:    }
  2, 0,                                      //  8535:    case 0x2: {
  OPC_Decode, 240, 10, 134, 1,               //  8537:     decode to LHAUX using decoder 134
                                             //  8537:    }
                                             //  8537:    } // switch Inst[1:0]
                                             //  8537:   }
  12, 8,                                     //  8542:   case 0xc: {
  OPC_CheckField, 0, 2, 2,                   //  8544:    check Inst[1:0] == 0x2
  OPC_Decode, 244, 15, 127,                  //  8548:    decode to STHX using decoder 127
                                             //  8548:   }
  13, 9,                                     //  8552:   case 0xd: {
  OPC_CheckField, 0, 2, 2,                   //  8554:    check Inst[1:0] == 0x2
  OPC_Decode, 242, 15, 136, 1,               //  8558:    decode to STHUX using decoder 136
                                             //  8558:   }
  14, 13,                                    //  8563:   case 0xe: {
  OPC_CheckField, 21, 5, 0,                  //  8565:    check Inst[25:21] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  8569:    check Inst[1:0] == 0x0
  OPC_Decode, 227, 5, 133, 1,                //  8573:    decode to DCBI using decoder 133
                                             //  8573:   }
  16, 16,                                    //  8578:   case 0x10: {
  OPC_SwitchField, 0, 2,                     //  8580:    switch Inst[1:0] {
  0, 4,                                      //  8583:    case 0x0: {
  OPC_Decode, 163, 11, 127,                  //  8585:     decode to LWBRX using decoder 127
                                             //  8585:    }
  2, 0,                                      //  8589:    case 0x2: {
  OPC_Decode, 231, 10, 139, 1,               //  8591:     decode to LFSX using decoder 139
                                             //  8591:    }
                                             //  8591:    } // switch Inst[1:0]
                                             //  8591:   }
  17, 20,                                    //  8596:   case 0x11: {
  OPC_SwitchField, 0, 2,                     //  8598:    switch Inst[1:0] {
  0, 8,                                      //  8601:    case 0x0: {
  OPC_CheckField, 11, 15, 0,                 //  8603:     check Inst[25:11] == 0x0
  OPC_Decode, 135, 17, 0,                    //  8607:     decode to TLBSYNC using decoder 0
                                             //  8607:    }
  2, 0,                                      //  8611:    case 0x2: {
  OPC_Decode, 230, 10, 140, 1,               //  8613:     decode to LFSUX using decoder 140
                                             //  8613:    }
                                             //  8613:    } // switch Inst[1:0]
                                             //  8613:   }
  18, 44,                                    //  8618:   case 0x12: {
  OPC_SwitchField, 0, 2,                     //  8620:    switch Inst[1:0] {
  0, 32,                                     //  8623:    case 0x0: {
  OPC_CheckField, 11, 5, 0,                  //  8625:     check Inst[15:11] == 0x0
  OPC_CheckField, 18, 3, 0,                  //  8629:     check Inst[20:18] == 0x0
  OPC_CheckField, 24, 2, 0,                  //  8633:     check Inst[25:24] == 0x0
  OPC_Scope, 13,                             //  8637:     try {
  OPC_CheckField, 16, 2, 0,                  //  8639:      check Inst[17:16] == 0x0
  OPC_CheckField, 23, 1, 0,                  //  8643:      check Inst[23] == 0x0
  OPC_Decode, 220, 16, 141, 1,               //  8647:      decode to SYNC using decoder 141
                                             //  8647:     } else try {
  OPC_Decode, 221, 16, 142, 1,               //  8652:      decode to SYNCP10 using decoder 142
                                             //  8652:     }
                                             //  8652:    }
  2, 0,                                      //  8657:    case 0x2: {
  OPC_Decode, 223, 10, 143, 1,               //  8659:     decode to LFDX using decoder 143
                                             //  8659:    }
                                             //  8659:    } // switch Inst[1:0]
                                             //  8659:   }
  19, 9,                                     //  8664:   case 0x13: {
  OPC_CheckField, 0, 2, 2,                   //  8666:    check Inst[1:0] == 0x2
  OPC_Decode, 222, 10, 144, 1,               //  8670:    decode to LFDUX using decoder 144
                                             //  8670:   }
  20, 16,                                    //  8675:   case 0x14: {
  OPC_SwitchField, 0, 2,                     //  8677:    switch Inst[1:0] {
  0, 4,                                      //  8680:    case 0x0: {
  OPC_Decode, 135, 16, 127,                  //  8682:     decode to STWBRX using decoder 127
                                             //  8682:    }
  2, 0,                                      //  8686:    case 0x2: {
  OPC_Decode, 231, 15, 139, 1,               //  8688:     decode to STFSX using decoder 139
                                             //  8688:    }
                                             //  8688:    } // switch Inst[1:0]
                                             //  8688:   }
  21, 16,                                    //  8693:   case 0x15: {
  OPC_SwitchField, 0, 2,                     //  8695:    switch Inst[1:0] {
  1, 4,                                      //  8698:    case 0x1: {
  OPC_Decode, 199, 15, 127,                  //  8700:     decode to STBCX using decoder 127
                                             //  8700:    }
  2, 0,                                      //  8704:    case 0x2: {
  OPC_Decode, 230, 15, 145, 1,               //  8706:     decode to STFSUX using decoder 145
                                             //  8706:    }
                                             //  8706:    } // switch Inst[1:0]
                                             //  8706:   }
  22, 16,                                    //  8711:   case 0x16: {
  OPC_SwitchField, 0, 2,                     //  8713:    switch Inst[1:0] {
  1, 4,                                      //  8716:    case 0x1: {
  OPC_Decode, 238, 15, 127,                  //  8718:     decode to STHCX using decoder 127
                                             //  8718:    }
  2, 0,                                      //  8722:    case 0x2: {
  OPC_Decode, 224, 15, 143, 1,               //  8724:     decode to STFDX using decoder 143
                                             //  8724:    }
                                             //  8724:    } // switch Inst[1:0]
                                             //  8724:   }
  23, 21,                                    //  8729:   case 0x17: {
  OPC_SwitchField, 0, 2,                     //  8731:    switch Inst[1:0] {
  0, 9,                                      //  8734:    case 0x0: {
  OPC_CheckField, 21, 5, 0,                  //  8736:     check Inst[25:21] == 0x0
  OPC_Decode, 224, 5, 133, 1,                //  8740:     decode to DCBA using decoder 133
                                             //  8740:    }
  2, 0,                                      //  8745:    case 0x2: {
  OPC_Decode, 223, 15, 146, 1,               //  8747:     decode to STFDUX using decoder 146
                                             //  8747:    }
                                             //  8747:    } // switch Inst[1:0]
                                             //  8747:   }
  24, 8,                                     //  8752:   case 0x18: {
  OPC_CheckField, 0, 2, 0,                   //  8754:    check Inst[1:0] == 0x0
  OPC_Decode, 247, 10, 127,                  //  8758:    decode to LHBRX using decoder 127
                                             //  8758:   }
  25, 32,                                    //  8762:   case 0x19: {
  OPC_SwitchField, 23, 3,                    //  8764:    switch Inst[25:23] {
  0, 13,                                     //  8767:    case 0x0: {
  OPC_CheckField, 11, 10, 0,                 //  8769:     check Inst[20:11] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  8773:     check Inst[1:0] == 0x0
  OPC_Decode, 239, 6, 147, 1,                //  8777:     decode to DSS using decoder 147
                                             //  8777:    }
  4, 0,                                      //  8782:    case 0x4: {
  OPC_CheckField, 11, 12, 0,                 //  8784:     check Inst[22:11] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  8788:     check Inst[1:0] == 0x0
  OPC_Decode, 240, 6, 0,                     //  8792:     decode to DSSALL using decoder 0
                                             //  8792:    }
                                             //  8792:    } // switch Inst[25:23]
                                             //  8792:   }
  26, 35,                                    //  8796:   case 0x1a: {
  OPC_SwitchField, 1, 1,                     //  8798:    switch Inst[1] {
  0, 19,                                     //  8801:    case 0x0: {
  OPC_Scope, 12,                             //  8803:     try {
  OPC_CheckField, 0, 1, 0,                   //  8805:      check Inst[0] == 0x0
  OPC_CheckField, 11, 15, 0,                 //  8809:      check Inst[25:11] == 0x0
  OPC_Decode, 164, 9, 0,                     //  8813:      decode to EnforceIEIO using decoder 0
                                             //  8813:     } else try {
  OPC_Decode, 214, 11, 148, 1,               //  8817:      decode to MBAR using decoder 148
                                             //  8817:     }
                                             //  8817:    }
  1, 0,                                      //  8822:    case 0x1: {
  OPC_CheckField, 0, 1, 0,                   //  8824:     check Inst[0] == 0x0
  OPC_Decode, 226, 10, 143, 1,               //  8828:     decode to LFIWAX using decoder 143
                                             //  8828:    }
                                             //  8828:    } // switch Inst[1]
                                             //  8828:   }
  27, 20,                                    //  8833:   case 0x1b: {
  OPC_SwitchField, 0, 2,                     //  8835:    switch Inst[1:0] {
  0, 8,                                      //  8838:    case 0x0: {
  OPC_CheckField, 11, 15, 0,                 //  8840:     check Inst[25:11] == 0x0
  OPC_Decode, 129, 12, 0,                    //  8844:     decode to MSGSYNC using decoder 0
                                             //  8844:    }
  2, 0,                                      //  8848:    case 0x2: {
  OPC_Decode, 227, 10, 143, 1,               //  8850:     decode to LFIWZX using decoder 143
                                             //  8850:    }
                                             //  8850:    } // switch Inst[1:0]
                                             //  8850:   }
  28, 8,                                     //  8855:   case 0x1c: {
  OPC_CheckField, 0, 2, 0,                   //  8857:    check Inst[1:0] == 0x0
  OPC_Decode, 236, 15, 127,                  //  8861:    decode to STHBRX using decoder 127
                                             //  8861:   }
  30, 21,                                    //  8865:   case 0x1e: {
  OPC_SwitchField, 0, 2,                     //  8867:    switch Inst[1:0] {
  0, 9,                                      //  8870:    case 0x0: {
  OPC_CheckField, 21, 5, 0,                  //  8872:     check Inst[25:21] == 0x0
  OPC_Decode, 173, 10, 133, 1,               //  8876:     decode to ICBI using decoder 133
                                             //  8876:    }
  2, 0,                                      //  8881:    case 0x2: {
  OPC_Decode, 227, 15, 143, 1,               //  8883:     decode to STFIWX using decoder 143
                                             //  8883:    }
                                             //  8883:    } // switch Inst[1:0]
                                             //  8883:   }
  31, 0,                                     //  8888:   case 0x1f: {
  OPC_SwitchField, 21, 5,                    //  8890:    switch Inst[25:21] {
  0, 9,                                      //  8893:    case 0x0: {
  OPC_CheckField, 0, 2, 0,                   //  8895:     check Inst[1:0] == 0x0
  OPC_Decode, 234, 5, 133, 1,                //  8899:     decode to DCBZ using decoder 133
                                             //  8899:    }
  1, 0,                                      //  8904:    case 0x1: {
  OPC_CheckField, 0, 2, 0,                   //  8906:     check Inst[1:0] == 0x0
  OPC_Decode, 236, 5, 133, 1,                //  8910:     decode to DCBZL using decoder 133
                                             //  8910:    }
                                             //  8910:    } // switch Inst[25:21]
                                             //  8910:   }
                                             //  8910:   } // switch Inst[10:6]
                                             //  8910:  }
  12, 79,                                    //  8915:  case 0xc: {
  OPC_SwitchField, 6, 5,                     //  8917:   switch Inst[10:6] {
  0, 17,                                     //  8920:   case 0x0: {
  OPC_SwitchField, 0, 2,                     //  8922:    switch Inst[1:0] {
  0, 5,                                      //  8925:    case 0x0: {
  OPC_Decode, 160, 15, 149, 1,               //  8927:     decode to SLW using decoder 149
                                             //  8927:    }
  1, 0,                                      //  8932:    case 0x1: {
  OPC_Decode, 163, 15, 149, 1,               //  8934:     decode to SLW_rec using decoder 149
                                             //  8934:    }
                                             //  8934:    } // switch Inst[1:0]
                                             //  8934:   }
  16, 17,                                    //  8939:   case 0x10: {
  OPC_SwitchField, 0, 2,                     //  8941:    switch Inst[1:0] {
  0, 5,                                      //  8944:    case 0x0: {
  OPC_Decode, 192, 15, 149, 1,               //  8946:     decode to SRW using decoder 149
                                             //  8946:    }
  1, 0,                                      //  8951:    case 0x1: {
  OPC_Decode, 195, 15, 149, 1,               //  8953:     decode to SRW_rec using decoder 149
                                             //  8953:    }
                                             //  8953:    } // switch Inst[1:0]
                                             //  8953:   }
  24, 17,                                    //  8958:   case 0x18: {
  OPC_SwitchField, 0, 2,                     //  8960:    switch Inst[1:0] {
  0, 5,                                      //  8963:    case 0x0: {
  OPC_Decode, 182, 15, 149, 1,               //  8965:     decode to SRAW using decoder 149
                                             //  8965:    }
  1, 0,                                      //  8970:    case 0x1: {
  OPC_Decode, 189, 15, 149, 1,               //  8972:     decode to SRAW_rec using decoder 149
                                             //  8972:    }
                                             //  8972:    } // switch Inst[1:0]
                                             //  8972:   }
  25, 0,                                     //  8977:   case 0x19: {
  OPC_SwitchField, 0, 2,                     //  8979:    switch Inst[1:0] {
  0, 5,                                      //  8982:    case 0x0: {
  OPC_Decode, 185, 15, 150, 1,               //  8984:     decode to SRAWI using decoder 150
                                             //  8984:    }
  1, 0,                                      //  8989:    case 0x1: {
  OPC_Decode, 188, 15, 150, 1,               //  8991:     decode to SRAWI_rec using decoder 150
                                             //  8991:    }
                                             //  8991:    } // switch Inst[1:0]
                                             //  8991:   }
                                             //  8991:   } // switch Inst[10:6]
                                             //  8991:  }
  13, 155, 3,                                //  8996:  case 0xd: {
  OPC_SwitchField, 6, 5,                     //  8999:   switch Inst[10:6] {
  0, 39,                                     //  9002:   case 0x0: {
  OPC_SwitchField, 0, 2,                     //  9004:    switch Inst[1:0] {
  0, 9,                                      //  9007:    case 0x0: {
  OPC_CheckField, 11, 5, 0,                  //  9009:     check Inst[15:11] == 0x0
  OPC_Decode, 189, 5, 151, 1,                //  9013:     decode to CNTLZW using decoder 151
                                             //  9013:    }
  1, 9,                                      //  9018:    case 0x1: {
  OPC_CheckField, 11, 5, 0,                  //  9020:     check Inst[15:11] == 0x0
  OPC_Decode, 192, 5, 151, 1,                //  9024:     decode to CNTLZW_rec using decoder 151
                                             //  9024:    }
  2, 5,                                      //  9029:    case 0x2: {
  OPC_Decode, 158, 15, 152, 1,               //  9031:     decode to SLD using decoder 152
                                             //  9031:    }
  3, 0,                                      //  9036:    case 0x3: {
  OPC_Decode, 159, 15, 152, 1,               //  9038:     decode to SLD_rec using decoder 152
                                             //  9038:    }
                                             //  9038:    } // switch Inst[1:0]
                                             //  9038:   }
  1, 32,                                     //  9043:   case 0x1: {
  OPC_SwitchField, 0, 2,                     //  9045:    switch Inst[1:0] {
  0, 9,                                      //  9048:    case 0x0: {
  OPC_CheckField, 11, 5, 0,                  //  9050:     check Inst[15:11] == 0x0
  OPC_Decode, 186, 5, 153, 1,                //  9054:     decode to CNTLZD using decoder 153
                                             //  9054:    }
  1, 9,                                      //  9059:    case 0x1: {
  OPC_CheckField, 11, 5, 0,                  //  9061:     check Inst[15:11] == 0x0
  OPC_Decode, 188, 5, 153, 1,                //  9065:     decode to CNTLZD_rec using decoder 153
                                             //  9065:    }
  2, 0,                                      //  9070:    case 0x2: {
  OPC_Decode, 187, 5, 154, 1,                //  9072:     decode to CNTLZDM using decoder 154
                                             //  9072:    }
                                             //  9072:    } // switch Inst[1:0]
                                             //  9072:   }
  3, 13,                                     //  9077:   case 0x3: {
  OPC_CheckField, 11, 5, 0,                  //  9079:    check Inst[15:11] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  9083:    check Inst[1:0] == 0x0
  OPC_Decode, 130, 14, 151, 1,               //  9087:    decode to POPCNTB using decoder 151
                                             //  9087:   }
  4, 13,                                     //  9092:   case 0x4: {
  OPC_CheckField, 11, 5, 0,                  //  9094:    check Inst[15:11] == 0x0
  OPC_CheckField, 0, 2, 2,                   //  9098:    check Inst[1:0] == 0x2
  OPC_Decode, 165, 5, 151, 1,                //  9102:    decode to BRW using decoder 151
                                             //  9102:   }
  5, 13,                                     //  9107:   case 0x5: {
  OPC_CheckField, 11, 5, 0,                  //  9109:    check Inst[15:11] == 0x0
  OPC_CheckField, 0, 2, 2,                   //  9113:    check Inst[1:0] == 0x2
  OPC_Decode, 161, 5, 153, 1,                //  9117:    decode to BRD using decoder 153
                                             //  9117:   }
  6, 13,                                     //  9122:   case 0x6: {
  OPC_CheckField, 11, 5, 0,                  //  9124:    check Inst[15:11] == 0x0
  OPC_CheckField, 0, 2, 2,                   //  9128:    check Inst[1:0] == 0x2
  OPC_Decode, 162, 5, 151, 1,                //  9132:    decode to BRH using decoder 151
                                             //  9132:   }
  8, 13,                                     //  9137:   case 0x8: {
  OPC_CheckField, 11, 5, 0,                  //  9139:    check Inst[15:11] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  9143:    check Inst[1:0] == 0x0
  OPC_Decode, 169, 5, 151, 1,                //  9147:    decode to CDTBCD using decoder 151
                                             //  9147:   }
  9, 13,                                     //  9152:   case 0x9: {
  OPC_CheckField, 11, 5, 0,                  //  9154:    check Inst[15:11] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  9158:    check Inst[1:0] == 0x0
  OPC_Decode, 167, 5, 151, 1,                //  9162:    decode to CBCDTD using decoder 151
                                             //  9162:   }
  11, 13,                                    //  9167:   case 0xb: {
  OPC_CheckField, 11, 5, 0,                  //  9169:    check Inst[15:11] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  9173:    check Inst[1:0] == 0x0
  OPC_Decode, 133, 14, 151, 1,               //  9177:    decode to POPCNTW using decoder 151
                                             //  9177:   }
  15, 13,                                    //  9182:   case 0xf: {
  OPC_CheckField, 11, 5, 0,                  //  9184:    check Inst[15:11] == 0x0
  OPC_CheckField, 0, 2, 0,                   //  9188:    check Inst[1:0] == 0x0
  OPC_Decode, 132, 14, 153, 1,               //  9192:    decode to POPCNTD using decoder 153
                                             //  9192:   }
  16, 39,                                    //  9197:   case 0x10: {
  OPC_SwitchField, 0, 2,                     //  9199:    switch Inst[1:0] {
  0, 9,                                      //  9202:    case 0x0: {
  OPC_CheckField, 11, 5, 0,                  //  9204:     check Inst[15:11] == 0x0
  OPC_Decode, 196, 5, 151, 1,                //  9208:     decode to CNTTZW using decoder 151
                                             //  9208:    }
  1, 9,                                      //  9213:    case 0x1: {
  OPC_CheckField, 11, 5, 0,                  //  9215:     check Inst[15:11] == 0x0
  OPC_Decode, 199, 5, 151, 1,                //  9219:     decode to CNTTZW_rec using decoder 151
                                             //  9219:    }
  2, 5,                                      //  9224:    case 0x2: {
  OPC_Decode, 190, 15, 152, 1,               //  9226:     decode to SRD using decoder 152
                                             //  9226:    }
  3, 0,                                      //  9231:    case 0x3: {
  OPC_Decode, 191, 15, 152, 1,               //  9233:     decode to SRD_rec using decoder 152
                                             //  9233:    }
                                             //  9233:    } // switch Inst[1:0]
                                             //  9233:   }
  17, 32,                                    //  9238:   case 0x11: {
  OPC_SwitchField, 0, 2,                     //  9240:    switch Inst[1:0] {
  0, 9,                                      //  9243:    case 0x0: {
  OPC_CheckField, 11, 5, 0,                  //  9245:     check Inst[15:11] == 0x0
  OPC_Decode, 193, 5, 153, 1,                //  9249:     decode to CNTTZD using decoder 153
                                             //  9249:    }
  1, 9,                                      //  9254:    case 0x1: {
  OPC_CheckField, 11, 5, 0,                  //  9256:     check Inst[15:11] == 0x0
  OPC_Decode, 195, 5, 153, 1,                //  9260:     decode to CNTTZD_rec using decoder 153
                                             //  9260:    }
  2, 0,                                      //  9265:    case 0x2: {
  OPC_Decode, 194, 5, 154, 1,                //  9267:     decode to CNTTZDM using decoder 154
                                             //  9267:    }
                                             //  9267:    } // switch Inst[1:0]
                                             //  9267:   }
  24, 17,                                    //  9272:   case 0x18: {
  OPC_SwitchField, 0, 2,                     //  9274:    switch Inst[1:0] {
  0, 5,                                      //  9277:    case 0x0: {
  OPC_Decode, 177, 15, 152, 1,               //  9279:     decode to SRAD using decoder 152
                                             //  9279:    }
  1, 0,                                      //  9284:    case 0x1: {
  OPC_Decode, 181, 15, 152, 1,               //  9286:     decode to SRAD_rec using decoder 152
                                             //  9286:    }
                                             //  9286:    } // switch Inst[1:0]
                                             //  9286:   }
  25, 17,                                    //  9291:   case 0x19: {
  OPC_SwitchField, 0, 1,                     //  9293:    switch Inst[0] {
  0, 5,                                      //  9296:    case 0x0: {
  OPC_Decode, 178, 15, 155, 1,               //  9298:     decode to SRADI using decoder 155
                                             //  9298:    }
  1, 0,                                      //  9303:    case 0x1: {
  OPC_Decode, 180, 15, 155, 1,               //  9305:     decode to SRADI_rec using decoder 155
                                             //  9305:    }
                                             //  9305:    } // switch Inst[0]
                                             //  9305:   }
  27, 17,                                    //  9310:   case 0x1b: {
  OPC_SwitchField, 0, 1,                     //  9312:    switch Inst[0] {
  0, 5,                                      //  9315:    case 0x0: {
  OPC_Decode, 156, 9, 155, 1,                //  9317:     decode to EXTSWSLI using decoder 155
                                             //  9317:    }
  1, 0,                                      //  9322:    case 0x1: {
  OPC_Decode, 159, 9, 155, 1,                //  9324:     decode to EXTSWSLI_rec using decoder 155
                                             //  9324:    }
                                             //  9324:    } // switch Inst[0]
                                             //  9324:   }
  28, 25,                                    //  9329:   case 0x1c: {
  OPC_SwitchField, 0, 2,                     //  9331:    switch Inst[1:0] {
  0, 9,                                      //  9334:    case 0x0: {
  OPC_CheckField, 11, 5, 0,                  //  9336:     check Inst[15:11] == 0x0
  OPC_Decode, 150, 9, 151, 1,                //  9340:     decode to EXTSH using decoder 151
                                             //  9340:    }
  1, 0,                                      //  9345:    case 0x1: {
  OPC_CheckField, 11, 5, 0,                  //  9347:     check Inst[15:11] == 0x0
  OPC_Decode, 154, 9, 151, 1,                //  9351:     decode to EXTSH_rec using decoder 151
                                             //  9351:    }
                                             //  9351:    } // switch Inst[1:0]
                                             //  9351:   }
  29, 25,                                    //  9356:   case 0x1d: {
  OPC_SwitchField, 0, 2,                     //  9358:    switch Inst[1:0] {
  0, 9,                                      //  9361:    case 0x0: {
  OPC_CheckField, 11, 5, 0,                  //  9363:     check Inst[15:11] == 0x0
  OPC_Decode, 145, 9, 151, 1,                //  9367:     decode to EXTSB using decoder 151
                                             //  9367:    }
  1, 0,                                      //  9372:    case 0x1: {
  OPC_CheckField, 11, 5, 0,                  //  9374:     check Inst[15:11] == 0x0
  OPC_Decode, 149, 9, 151, 1,                //  9378:     decode to EXTSB_rec using decoder 151
                                             //  9378:    }
                                             //  9378:    } // switch Inst[1:0]
                                             //  9378:   }
  30, 0,                                     //  9383:   case 0x1e: {
  OPC_SwitchField, 0, 2,                     //  9385:    switch Inst[1:0] {
  0, 9,                                      //  9388:    case 0x0: {
  OPC_CheckField, 11, 5, 0,                  //  9390:     check Inst[15:11] == 0x0
  OPC_Decode, 155, 9, 153, 1,                //  9394:     decode to EXTSW using decoder 153
                                             //  9394:    }
  1, 0,                                      //  9399:    case 0x1: {
  OPC_CheckField, 11, 5, 0,                  //  9401:     check Inst[15:11] == 0x0
  OPC_Decode, 163, 9, 153, 1,                //  9405:     decode to EXTSW_rec using decoder 153
                                             //  9405:    }
                                             //  9405:    } // switch Inst[1:0]
                                             //  9405:   }
                                             //  9405:   } // switch Inst[10:6]
                                             //  9405:  }
  14, 210, 1,                                //  9410:  case 0xe: {
  OPC_SwitchField, 6, 5,                     //  9413:   switch Inst[10:6] {
  0, 17,                                     //  9416:   case 0x0: {
  OPC_SwitchField, 0, 2,                     //  9418:    switch Inst[1:0] {
  0, 5,                                      //  9421:    case 0x0: {
  OPC_Decode, 233, 3, 149, 1,                //  9423:     decode to AND using decoder 149
                                             //  9423:    }
  1, 0,                                      //  9428:    case 0x1: {
  OPC_Decode, 248, 3, 149, 1,                //  9430:     decode to AND_rec using decoder 149
                                             //  9430:    }
                                             //  9430:    } // switch Inst[1:0]
                                             //  9430:   }
  1, 17,                                     //  9435:   case 0x1: {
  OPC_SwitchField, 0, 2,                     //  9437:    switch Inst[1:0] {
  0, 5,                                      //  9440:    case 0x0: {
  OPC_Decode, 236, 3, 149, 1,                //  9442:     decode to ANDC using decoder 149
                                             //  9442:    }
  1, 0,                                      //  9447:    case 0x1: {
  OPC_Decode, 239, 3, 149, 1,                //  9449:     decode to ANDC_rec using decoder 149
                                             //  9449:    }
                                             //  9449:    } // switch Inst[1:0]
                                             //  9449:   }
  3, 17,                                     //  9454:   case 0x3: {
  OPC_SwitchField, 0, 2,                     //  9456:    switch Inst[1:0] {
  0, 5,                                      //  9459:    case 0x0: {
  OPC_Decode, 214, 12, 149, 1,               //  9461:     decode to NOR using decoder 149
                                             //  9461:    }
  1, 0,                                      //  9466:    case 0x1: {
  OPC_Decode, 217, 12, 149, 1,               //  9468:     decode to NOR_rec using decoder 149
                                             //  9468:    }
                                             //  9468:    } // switch Inst[1:0]
                                             //  9468:   }
  4, 9,                                      //  9473:   case 0x4: {
  OPC_CheckField, 0, 2, 0,                   //  9475:    check Inst[1:0] == 0x0
  OPC_Decode, 239, 12, 154, 1,               //  9479:    decode to PDEPD using decoder 154
                                             //  9479:   }
  5, 9,                                      //  9484:   case 0x5: {
  OPC_CheckField, 0, 2, 0,                   //  9486:    check Inst[1:0] == 0x0
  OPC_Decode, 240, 12, 154, 1,               //  9490:    decode to PEXTD using decoder 154
                                             //  9490:   }
  6, 9,                                      //  9495:   case 0x6: {
  OPC_CheckField, 0, 2, 0,                   //  9497:    check Inst[1:0] == 0x0
  OPC_Decode, 171, 5, 154, 1,                //  9501:    decode to CFUGED using decoder 154
                                             //  9501:   }
  7, 9,                                      //  9506:   case 0x7: {
  OPC_CheckField, 0, 2, 0,                   //  9508:    check Inst[1:0] == 0x0
  OPC_Decode, 160, 5, 154, 1,                //  9512:    decode to BPERMD using decoder 154
                                             //  9512:   }
  8, 17,                                     //  9517:   case 0x8: {
  OPC_SwitchField, 0, 2,                     //  9519:    switch Inst[1:0] {
  0, 5,                                      //  9522:    case 0x0: {
  OPC_Decode, 202, 7, 149, 1,                //  9524:     decode to EQV using decoder 149
                                             //  9524:    }
  1, 0,                                      //  9529:    case 0x1: {
  OPC_Decode, 205, 7, 149, 1,                //  9531:     decode to EQV_rec using decoder 149
                                             //  9531:    }
                                             //  9531:    } // switch Inst[1:0]
                                             //  9531:   }
  9, 17,                                     //  9536:   case 0x9: {
  OPC_SwitchField, 0, 2,                     //  9538:    switch Inst[1:0] {
  0, 5,                                      //  9541:    case 0x0: {
  OPC_Decode, 174, 20, 149, 1,               //  9543:     decode to XOR using decoder 149
                                             //  9543:    }
  1, 0,                                      //  9548:    case 0x1: {
  OPC_Decode, 181, 20, 149, 1,               //  9550:     decode to XOR_rec using decoder 149
                                             //  9550:    }
                                             //  9550:    } // switch Inst[1:0]
                                             //  9550:   }
  12, 17,                                    //  9555:   case 0xc: {
  OPC_SwitchField, 0, 2,                     //  9557:    switch Inst[1:0] {
  0, 5,                                      //  9560:    case 0x0: {
  OPC_Decode, 221, 12, 149, 1,               //  9562:     decode to ORC using decoder 149
                                             //  9562:    }
  1, 0,                                      //  9567:    case 0x1: {
  OPC_Decode, 224, 12, 149, 1,               //  9569:     decode to ORC_rec using decoder 149
                                             //  9569:    }
                                             //  9569:    } // switch Inst[1:0]
                                             //  9569:   }
  13, 17,                                    //  9574:   case 0xd: {
  OPC_SwitchField, 0, 2,                     //  9576:    switch Inst[1:0] {
  0, 5,                                      //  9579:    case 0x0: {
  OPC_Decode, 218, 12, 149, 1,               //  9581:     decode to OR using decoder 149
                                             //  9581:    }
  1, 0,                                      //  9586:    case 0x1: {
  OPC_Decode, 229, 12, 149, 1,               //  9588:     decode to OR_rec using decoder 149
                                             //  9588:    }
                                             //  9588:    } // switch Inst[1:0]
                                             //  9588:   }
  14, 17,                                    //  9593:   case 0xe: {
  OPC_SwitchField, 0, 2,                     //  9595:    switch Inst[1:0] {
  0, 5,                                      //  9598:    case 0x0: {
  OPC_Decode, 198, 12, 149, 1,               //  9600:     decode to NAND using decoder 149
                                             //  9600:    }
  1, 0,                                      //  9605:    case 0x1: {
  OPC_Decode, 201, 12, 149, 1,               //  9607:     decode to NAND_rec using decoder 149
                                             //  9607:    }
                                             //  9607:    } // switch Inst[1:0]
                                             //  9607:   }
  15, 0,                                     //  9612:   case 0xf: {
  OPC_CheckField, 0, 2, 0,                   //  9614:    check Inst[1:0] == 0x0
  OPC_Decode, 173, 5, 149, 1,                //  9618:    decode to CMPB using decoder 149
                                             //  9618:   }
                                             //  9618:   } // switch Inst[10:6]
                                             //  9618:  }
  15, 0,                                     //  9623:  case 0xf: {
  OPC_SwitchField, 6, 5,                     //  9625:   switch Inst[10:6] {
  0, 39,                                     //  9628:   case 0x0: {
  OPC_SwitchField, 0, 2,                     //  9630:    switch Inst[1:0] {
  0, 28,                                     //  9633:    case 0x0: {
  OPC_CheckField, 11, 5, 0,                  //  9635:     check Inst[15:11] == 0x0
  OPC_CheckField, 18, 3, 0,                  //  9639:     check Inst[20:18] == 0x0
  OPC_CheckField, 23, 3, 0,                  //  9643:     check Inst[25:23] == 0x0
  OPC_Scope, 9,                              //  9647:     try {
  OPC_CheckField, 16, 2, 0,                  //  9649:      check Inst[17:16] == 0x0
  OPC_Decode, 170, 20, 141, 1,               //  9653:      decode to WAIT using decoder 141
                                             //  9653:     } else try {
  OPC_Decode, 171, 20, 156, 1,               //  9658:      decode to WAITP10 using decoder 156
                                             //  9658:     }
                                             //  9658:    }
  2, 0,                                      //  9663:    case 0x2: {
  OPC_Decode, 165, 11, 127,                  //  9665:     decode to LWEPX using decoder 127
                                             //  9665:    }
                                             //  9665:    } // switch Inst[1:0]
                                             //  9665:   }
  1, 13,                                     //  9669:   case 0x1: {
  OPC_CheckField, 21, 5, 0,                  //  9671:    check Inst[25:21] == 0x0
  OPC_CheckField, 0, 2, 2,                   //  9675:    check Inst[1:0] == 0x2
  OPC_Decode, 229, 5, 133, 1,                //  9679:    decode to DCBSTEP using decoder 133
                                             //  9679:   }
  2, 8,                                      //  9684:   case 0x2: {
  OPC_CheckField, 0, 2, 2,                   //  9686:    check Inst[1:0] == 0x2
  OPC_Decode, 187, 10, 127,                  //  9690:    decode to LBEPX using decoder 127
                                             //  9690:   }
  3, 13,                                     //  9694:   case 0x3: {
  OPC_CheckField, 21, 5, 0,                  //  9696:    check Inst[25:21] == 0x0
  OPC_CheckField, 0, 2, 2,                   //  9700:    check Inst[1:0] == 0x2
  OPC_Decode, 226, 5, 133, 1,                //  9704:    decode to DCBFEP using decoder 133
                                             //  9704:   }
  4, 8,                                      //  9709:   case 0x4: {
  OPC_CheckField, 0, 2, 2,                   //  9711:    check Inst[1:0] == 0x2
  OPC_Decode, 138, 16, 127,                  //  9715:    decode to STWEPX using decoder 127
                                             //  9715:   }
  6, 8,                                      //  9719:   case 0x6: {
  OPC_CheckField, 0, 2, 2,                   //  9721:    check Inst[1:0] == 0x2
  OPC_Decode, 200, 15, 127,                  //  9725:    decode to STBEPX using decoder 127
                                             //  9725:   }
  7, 9,                                      //  9729:   case 0x7: {
  OPC_CheckField, 0, 2, 2,                   //  9731:    check Inst[1:0] == 0x2
  OPC_Decode, 233, 5, 157, 1,                //  9735:    decode to DCBTSTEP using decoder 157
                                             //  9735:   }
  8, 8,                                      //  9740:   case 0x8: {
  OPC_CheckField, 0, 2, 2,                   //  9742:    check Inst[1:0] == 0x2
  OPC_Decode, 249, 10, 127,                  //  9746:    decode to LHEPX using decoder 127
                                             //  9746:   }
  9, 9,                                      //  9750:   case 0x9: {
  OPC_CheckField, 0, 2, 2,                   //  9752:    check Inst[1:0] == 0x2
  OPC_Decode, 231, 5, 157, 1,                //  9756:    decode to DCBTEP using decoder 157
                                             //  9756:   }
  12, 8,                                     //  9761:   case 0xc: {
  OPC_CheckField, 0, 2, 2,                   //  9763:    check Inst[1:0] == 0x2
  OPC_Decode, 239, 15, 127,                  //  9767:    decode to STHEPX using decoder 127
                                             //  9767:   }
  18, 9,                                     //  9771:   case 0x12: {
  OPC_CheckField, 0, 2, 2,                   //  9773:    check Inst[1:0] == 0x2
  OPC_Decode, 220, 10, 143, 1,               //  9777:    decode to LFDEPX using decoder 143
                                             //  9777:   }
  22, 9,                                     //  9782:   case 0x16: {
  OPC_CheckField, 0, 2, 2,                   //  9784:    check Inst[1:0] == 0x2
  OPC_Decode, 221, 15, 143, 1,               //  9788:    decode to STFDEPX using decoder 143
                                             //  9788:   }
  30, 13,                                    //  9793:   case 0x1e: {
  OPC_CheckField, 21, 5, 0,                  //  9795:    check Inst[25:21] == 0x0
  OPC_CheckField, 0, 2, 2,                   //  9799:    check Inst[1:0] == 0x2
  OPC_Decode, 174, 10, 133, 1,               //  9803:    decode to ICBIEP using decoder 133
                                             //  9803:   }
  31, 0,                                     //  9808:   case 0x1f: {
  OPC_SwitchField, 21, 5,                    //  9810:    switch Inst[25:21] {
  0, 9,                                      //  9813:    case 0x0: {
  OPC_CheckField, 0, 2, 2,                   //  9815:     check Inst[1:0] == 0x2
  OPC_Decode, 235, 5, 133, 1,                //  9819:     decode to DCBZEP using decoder 133
                                             //  9819:    }
  1, 0,                                      //  9824:    case 0x1: {
  OPC_CheckField, 0, 2, 2,                   //  9826:     check Inst[1:0] == 0x2
  OPC_Decode, 237, 5, 133, 1,                //  9830:     decode to DCBZLEP using decoder 133
                                             //  9830:    }
                                             //  9830:    } // switch Inst[25:21]
                                             //  9830:   }
                                             //  9830:   } // switch Inst[10:6]
                                             //  9830:  }
                                             //  9830:  } // switch Inst[5:2]
                                             //  9830: }
  32, 5,                                     //  9835: case 0x20: {
  OPC_Decode, 166, 11, 158, 1,               //  9837:  decode to LWZ using decoder 158
                                             //  9837: }
  33, 5,                                     //  9842: case 0x21: {
  OPC_Decode, 169, 11, 159, 1,               //  9844:  decode to LWZU using decoder 159
                                             //  9844: }
  34, 5,                                     //  9849: case 0x22: {
  OPC_Decode, 188, 10, 158, 1,               //  9851:  decode to LBZ using decoder 158
                                             //  9851: }
  35, 5,                                     //  9856: case 0x23: {
  OPC_Decode, 191, 10, 159, 1,               //  9858:  decode to LBZU using decoder 159
                                             //  9858: }
  36, 5,                                     //  9863: case 0x24: {
  OPC_Decode, 132, 16, 158, 1,               //  9865:  decode to STW using decoder 158
                                             //  9865: }
  37, 5,                                     //  9870: case 0x25: {
  OPC_Decode, 139, 16, 160, 1,               //  9872:  decode to STWU using decoder 160
                                             //  9872: }
  38, 5,                                     //  9877: case 0x26: {
  OPC_Decode, 196, 15, 158, 1,               //  9879:  decode to STB using decoder 158
                                             //  9879: }
  39, 5,                                     //  9884: case 0x27: {
  OPC_Decode, 201, 15, 160, 1,               //  9886:  decode to STBU using decoder 160
                                             //  9886: }
  40, 5,                                     //  9891: case 0x28: {
  OPC_Decode, 250, 10, 158, 1,               //  9893:  decode to LHZ using decoder 158
                                             //  9893: }
  41, 5,                                     //  9898: case 0x29: {
  OPC_Decode, 253, 10, 159, 1,               //  9900:  decode to LHZU using decoder 159
                                             //  9900: }
  42, 5,                                     //  9905: case 0x2a: {
  OPC_Decode, 234, 10, 158, 1,               //  9907:  decode to LHA using decoder 158
                                             //  9907: }
  43, 5,                                     //  9912: case 0x2b: {
  OPC_Decode, 238, 10, 159, 1,               //  9914:  decode to LHAU using decoder 159
                                             //  9914: }
  44, 5,                                     //  9919: case 0x2c: {
  OPC_Decode, 234, 15, 158, 1,               //  9921:  decode to STH using decoder 158
                                             //  9921: }
  45, 5,                                     //  9926: case 0x2d: {
  OPC_Decode, 240, 15, 160, 1,               //  9928:  decode to STHU using decoder 160
                                             //  9928: }
  46, 5,                                     //  9933: case 0x2e: {
  OPC_Decode, 138, 11, 158, 1,               //  9935:  decode to LMW using decoder 158
                                             //  9935: }
  47, 5,                                     //  9940: case 0x2f: {
  OPC_Decode, 249, 15, 158, 1,               //  9942:  decode to STMW using decoder 158
                                             //  9942: }
  48, 5,                                     //  9947: case 0x30: {
  OPC_Decode, 228, 10, 161, 1,               //  9949:  decode to LFS using decoder 161
                                             //  9949: }
  49, 5,                                     //  9954: case 0x31: {
  OPC_Decode, 229, 10, 162, 1,               //  9956:  decode to LFSU using decoder 162
                                             //  9956: }
  50, 5,                                     //  9961: case 0x32: {
  OPC_Decode, 219, 10, 163, 1,               //  9963:  decode to LFD using decoder 163
                                             //  9963: }
  51, 5,                                     //  9968: case 0x33: {
  OPC_Decode, 221, 10, 164, 1,               //  9970:  decode to LFDU using decoder 164
                                             //  9970: }
  52, 5,                                     //  9975: case 0x34: {
  OPC_Decode, 228, 15, 161, 1,               //  9977:  decode to STFS using decoder 161
                                             //  9977: }
  53, 5,                                     //  9982: case 0x35: {
  OPC_Decode, 229, 15, 165, 1,               //  9984:  decode to STFSU using decoder 165
                                             //  9984: }
  54, 5,                                     //  9989: case 0x36: {
  OPC_Decode, 220, 15, 163, 1,               //  9991:  decode to STFD using decoder 163
                                             //  9991: }
  55, 5,                                     //  9996: case 0x37: {
  OPC_Decode, 222, 15, 166, 1,               //  9998:  decode to STFDU using decoder 166
                                             //  9998: }
  56, 9,                                     // 10003: case 0x38: {
  OPC_CheckField, 0, 4, 0,                   // 10005:  check Inst[3:0] == 0x0
  OPC_Decode, 139, 11, 167, 1,               // 10009:  decode to LQ using decoder 167
                                             // 10009: }
  57, 17,                                    // 10014: case 0x39: {
  OPC_SwitchField, 0, 2,                     // 10016:  switch Inst[1:0] {
  2, 5,                                      // 10019:  case 0x2: {
  OPC_Decode, 180, 11, 168, 1,               // 10021:   decode to LXSD using decoder 168
                                             // 10021:  }
  3, 0,                                      // 10026:  case 0x3: {
  OPC_Decode, 186, 11, 168, 1,               // 10028:   decode to LXSSP using decoder 168
                                             // 10028:  }
                                             // 10028:  } // switch Inst[1:0]
                                             // 10028: }
  58, 24,                                    // 10033: case 0x3a: {
  OPC_SwitchField, 0, 2,                     // 10035:  switch Inst[1:0] {
  0, 5,                                      // 10038:  case 0x0: {
  OPC_Decode, 200, 10, 169, 1,               // 10040:   decode to LD using decoder 169
                                             // 10040:  }
  1, 5,                                      // 10045:  case 0x1: {
  OPC_Decode, 207, 10, 170, 1,               // 10047:   decode to LDU using decoder 170
                                             // 10047:  }
  2, 0,                                      // 10052:  case 0x2: {
  OPC_Decode, 151, 11, 169, 1,               // 10054:   decode to LWA using decoder 169
                                             // 10054:  }
                                             // 10054:  } // switch Inst[1:0]
                                             // 10054: }
  59, 190, 13,                               // 10059: case 0x3b: {
  OPC_SwitchField, 3, 3,                     // 10062:  switch Inst[5:3] {
  0, 206, 4,                                 // 10065:  case 0x0: {
  OPC_SwitchField, 6, 3,                     // 10068:   switch Inst[8:6] {
  0, 99,                                     // 10071:   case 0x0: {
  OPC_SwitchField, 0, 3,                     // 10073:    switch Inst[2:0] {
  4, 39,                                     // 10076:    case 0x4: {
  OPC_SwitchField, 9, 2,                     // 10078:     switch Inst[10:9] {
  0, 5,                                      // 10081:     case 0x0: {
  OPC_Decode, 219, 5, 171, 1,                // 10083:      decode to DADD using decoder 171
                                             // 10083:     }
  1, 9,                                      // 10088:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 10090:      check Inst[20:16] == 0x0
  OPC_Decode, 248, 5, 172, 1,                // 10094:      decode to DCTDP using decoder 172
                                             // 10094:     }
  2, 5,                                      // 10099:     case 0x2: {
  OPC_Decode, 249, 6, 171, 1,                // 10101:      decode to DSUB using decoder 171
                                             // 10101:     }
  3, 0,                                      // 10106:     case 0x3: {
  OPC_CheckField, 16, 5, 0,                  // 10108:      check Inst[20:16] == 0x0
  OPC_Decode, 229, 6, 172, 1,                // 10112:      decode to DRSP using decoder 172
                                             // 10112:     }
                                             // 10112:     } // switch Inst[10:9]
                                             // 10112:    }
  5, 39,                                     // 10117:    case 0x5: {
  OPC_SwitchField, 9, 2,                     // 10119:     switch Inst[10:9] {
  0, 5,                                      // 10122:     case 0x0: {
  OPC_Decode, 222, 5, 171, 1,                // 10124:      decode to DADD_rec using decoder 171
                                             // 10124:     }
  1, 9,                                      // 10129:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 10131:      check Inst[20:16] == 0x0
  OPC_Decode, 249, 5, 172, 1,                // 10135:      decode to DCTDP_rec using decoder 172
                                             // 10135:     }
  2, 5,                                      // 10140:     case 0x2: {
  OPC_Decode, 252, 6, 171, 1,                // 10142:      decode to DSUB_rec using decoder 171
                                             // 10142:     }
  3, 0,                                      // 10147:     case 0x3: {
  OPC_CheckField, 16, 5, 0,                  // 10149:      check Inst[20:16] == 0x0
  OPC_Decode, 230, 6, 172, 1,                // 10153:      decode to DRSP_rec using decoder 172
                                             // 10153:     }
                                             // 10153:     } // switch Inst[10:9]
                                             // 10153:    }
  6, 5,                                      // 10158:    case 0x6: {
  OPC_Decode, 207, 6, 173, 1,                // 10160:     decode to DQUA using decoder 173
                                             // 10160:    }
  7, 0,                                      // 10165:    case 0x7: {
  OPC_Decode, 214, 6, 173, 1,                // 10167:     decode to DQUA_rec using decoder 173
                                             // 10167:    }
                                             // 10167:    } // switch Inst[2:0]
                                             // 10167:   }
  1, 99,                                     // 10172:   case 0x1: {
  OPC_SwitchField, 0, 3,                     // 10174:    switch Inst[2:0] {
  4, 39,                                     // 10177:    case 0x4: {
  OPC_SwitchField, 9, 2,                     // 10179:     switch Inst[10:9] {
  0, 5,                                      // 10182:     case 0x0: {
  OPC_Decode, 181, 6, 171, 1,                // 10184:      decode to DMUL using decoder 171
                                             // 10184:     }
  1, 9,                                      // 10189:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 10191:      check Inst[20:16] == 0x0
  OPC_Decode, 250, 5, 172, 1,                // 10195:      decode to DCTFIX using decoder 172
                                             // 10195:     }
  2, 5,                                      // 10200:     case 0x2: {
  OPC_Decode, 133, 6, 171, 1,                // 10202:      decode to DDIV using decoder 171
                                             // 10202:     }
  3, 0,                                      // 10207:     case 0x3: {
  OPC_CheckField, 16, 5, 0,                  // 10209:      check Inst[20:16] == 0x0
  OPC_Decode, 239, 5, 172, 1,                // 10213:      decode to DCFFIX using decoder 172
                                             // 10213:     }
                                             // 10213:     } // switch Inst[10:9]
                                             // 10213:    }
  5, 39,                                     // 10218:    case 0x5: {
  OPC_SwitchField, 9, 2,                     // 10220:     switch Inst[10:9] {
  0, 5,                                      // 10223:     case 0x0: {
  OPC_Decode, 184, 6, 171, 1,                // 10225:      decode to DMUL_rec using decoder 171
                                             // 10225:     }
  1, 9,                                      // 10230:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 10232:      check Inst[20:16] == 0x0
  OPC_Decode, 254, 5, 172, 1,                // 10236:      decode to DCTFIX_rec using decoder 172
                                             // 10236:     }
  2, 5,                                      // 10241:     case 0x2: {
  OPC_Decode, 136, 6, 171, 1,                // 10243:      decode to DDIV_rec using decoder 171
                                             // 10243:     }
  3, 0,                                      // 10248:     case 0x3: {
  OPC_CheckField, 16, 5, 0,                  // 10250:      check Inst[20:16] == 0x0
  OPC_Decode, 243, 5, 172, 1,                // 10254:      decode to DCFFIX_rec using decoder 172
                                             // 10254:     }
                                             // 10254:     } // switch Inst[10:9]
                                             // 10254:    }
  6, 5,                                      // 10259:    case 0x6: {
  OPC_Decode, 225, 6, 173, 1,                // 10261:     decode to DRRND using decoder 173
                                             // 10261:    }
  7, 0,                                      // 10266:    case 0x7: {
  OPC_Decode, 228, 6, 173, 1,                // 10268:     decode to DRRND_rec using decoder 173
                                             // 10268:    }
                                             // 10268:    } // switch Inst[2:0]
                                             // 10268:   }
  2, 95,                                     // 10273:   case 0x2: {
  OPC_SwitchField, 0, 3,                     // 10275:    switch Inst[2:0] {
  4, 37,                                     // 10278:    case 0x4: {
  OPC_SwitchField, 9, 1,                     // 10280:     switch Inst[9] {
  0, 5,                                      // 10283:     case 0x0: {
  OPC_Decode, 231, 6, 174, 1,                // 10285:      decode to DSCLI using decoder 174
                                             // 10285:     }
  1, 0,                                      // 10290:     case 0x1: {
  OPC_SwitchField, 10, 1,                    // 10292:      switch Inst[10] {
  0, 9,                                      // 10295:      case 0x0: {
  OPC_CheckField, 16, 3, 0,                  // 10297:       check Inst[18:16] == 0x0
  OPC_Decode, 129, 6, 175, 1,                // 10301:       decode to DDEDPD using decoder 175
                                             // 10301:      }
  1, 0,                                      // 10306:      case 0x1: {
  OPC_CheckField, 16, 4, 0,                  // 10308:       check Inst[19:16] == 0x0
  OPC_Decode, 137, 6, 176, 1,                // 10312:       decode to DENBCD using decoder 176
                                             // 10312:      }
                                             // 10312:      } // switch Inst[10]
                                             // 10312:     }
                                             // 10312:     } // switch Inst[9]
                                             // 10312:    }
  5, 37,                                     // 10317:    case 0x5: {
  OPC_SwitchField, 9, 1,                     // 10319:     switch Inst[9] {
  0, 5,                                      // 10322:     case 0x0: {
  OPC_Decode, 234, 6, 174, 1,                // 10324:      decode to DSCLI_rec using decoder 174
                                             // 10324:     }
  1, 0,                                      // 10329:     case 0x1: {
  OPC_SwitchField, 10, 1,                    // 10331:      switch Inst[10] {
  0, 9,                                      // 10334:      case 0x0: {
  OPC_CheckField, 16, 3, 0,                  // 10336:       check Inst[18:16] == 0x0
  OPC_Decode, 132, 6, 175, 1,                // 10340:       decode to DDEDPD_rec using decoder 175
                                             // 10340:      }
  1, 0,                                      // 10345:      case 0x1: {
  OPC_CheckField, 16, 4, 0,                  // 10347:       check Inst[19:16] == 0x0
  OPC_Decode, 140, 6, 176, 1,                // 10351:       decode to DENBCD_rec using decoder 176
                                             // 10351:      }
                                             // 10351:      } // switch Inst[10]
                                             // 10351:     }
                                             // 10351:     } // switch Inst[9]
                                             // 10351:    }
  6, 5,                                      // 10356:    case 0x6: {
  OPC_Decode, 208, 6, 177, 1,                // 10358:     decode to DQUAI using decoder 177
                                             // 10358:    }
  7, 0,                                      // 10363:    case 0x7: {
  OPC_Decode, 211, 6, 177, 1,                // 10365:     decode to DQUAI_rec using decoder 177
                                             // 10365:    }
                                             // 10365:    } // switch Inst[2:0]
                                             // 10365:   }
  3, 95,                                     // 10370:   case 0x3: {
  OPC_SwitchField, 0, 3,                     // 10372:    switch Inst[2:0] {
  4, 33,                                     // 10375:    case 0x4: {
  OPC_SwitchField, 9, 1,                     // 10377:     switch Inst[9] {
  0, 5,                                      // 10380:     case 0x0: {
  OPC_Decode, 235, 6, 174, 1,                // 10382:      decode to DSCRI using decoder 174
                                             // 10382:     }
  1, 0,                                      // 10387:     case 0x1: {
  OPC_SwitchField, 10, 1,                    // 10389:      switch Inst[10] {
  0, 9,                                      // 10392:      case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 10394:       check Inst[20:16] == 0x0
  OPC_Decode, 135, 7, 172, 1,                // 10398:       decode to DXEX using decoder 172
                                             // 10398:      }
  1, 0,                                      // 10403:      case 0x1: {
  OPC_Decode, 141, 6, 171, 1,                // 10405:       decode to DIEX using decoder 171
                                             // 10405:      }
                                             // 10405:      } // switch Inst[10]
                                             // 10405:     }
                                             // 10405:     } // switch Inst[9]
                                             // 10405:    }
  5, 33,                                     // 10410:    case 0x5: {
  OPC_SwitchField, 9, 1,                     // 10412:     switch Inst[9] {
  0, 5,                                      // 10415:     case 0x0: {
  OPC_Decode, 238, 6, 174, 1,                // 10417:      decode to DSCRI_rec using decoder 174
                                             // 10417:     }
  1, 0,                                      // 10422:     case 0x1: {
  OPC_SwitchField, 10, 1,                    // 10424:      switch Inst[10] {
  0, 9,                                      // 10427:      case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 10429:       check Inst[20:16] == 0x0
  OPC_Decode, 138, 7, 172, 1,                // 10433:       decode to DXEX_rec using decoder 172
                                             // 10433:      }
  1, 0,                                      // 10438:      case 0x1: {
  OPC_Decode, 144, 6, 171, 1,                // 10440:       decode to DIEX_rec using decoder 171
                                             // 10440:      }
                                             // 10440:      } // switch Inst[10]
                                             // 10440:     }
                                             // 10440:     } // switch Inst[9]
                                             // 10440:    }
  6, 9,                                      // 10445:    case 0x6: {
  OPC_CheckField, 17, 4, 0,                  // 10447:     check Inst[20:17] == 0x0
  OPC_Decode, 221, 6, 178, 1,                // 10451:     decode to DRINTX using decoder 178
                                             // 10451:    }
  7, 0,                                      // 10456:    case 0x7: {
  OPC_CheckField, 17, 4, 0,                  // 10458:     check Inst[20:17] == 0x0
  OPC_Decode, 224, 6, 178, 1,                // 10462:     decode to DRINTX_rec using decoder 178
                                             // 10462:    }
                                             // 10462:    } // switch Inst[2:0]
                                             // 10462:   }
  4, 47,                                     // 10467:   case 0x4: {
  OPC_SwitchField, 9, 2,                     // 10469:    switch Inst[10:9] {
  0, 13,                                     // 10472:    case 0x0: {
  OPC_CheckField, 21, 2, 0,                  // 10474:     check Inst[22:21] == 0x0
  OPC_CheckField, 0, 3, 4,                   // 10478:     check Inst[2:0] == 0x4
  OPC_Decode, 244, 5, 179, 1,                // 10482:     decode to DCMPO using decoder 179
                                             // 10482:    }
  1, 5,                                      // 10487:    case 0x1: {
  OPC_Decode, 185, 20, 180, 1,               // 10489:     decode to XSADDADDUQM using decoder 180
                                             // 10489:    }
  2, 13,                                     // 10494:    case 0x2: {
  OPC_CheckField, 21, 2, 0,                  // 10496:     check Inst[22:21] == 0x0
  OPC_CheckField, 0, 3, 4,                   // 10500:     check Inst[2:0] == 0x4
  OPC_Decode, 246, 5, 179, 1,                // 10504:     decode to DCMPU using decoder 179
                                             // 10504:    }
  3, 0,                                      // 10509:    case 0x3: {
  OPC_Decode, 190, 20, 180, 1,               // 10511:     decode to XSADDSUBSUQM using decoder 180
                                             // 10511:    }
                                             // 10511:    } // switch Inst[10:9]
                                             // 10511:   }
  5, 59,                                     // 10516:   case 0x5: {
  OPC_SwitchField, 9, 2,                     // 10518:    switch Inst[10:9] {
  0, 13,                                     // 10521:    case 0x0: {
  OPC_CheckField, 21, 2, 0,                  // 10523:     check Inst[22:21] == 0x0
  OPC_CheckField, 0, 3, 4,                   // 10527:     check Inst[2:0] == 0x4
  OPC_Decode, 129, 7, 179, 1,                // 10531:     decode to DTSTEX using decoder 179
                                             // 10531:    }
  1, 5,                                      // 10536:    case 0x1: {
  OPC_Decode, 184, 20, 180, 1,               // 10538:     decode to XSADDADDSUQM using decoder 180
                                             // 10538:    }
  2, 25,                                     // 10543:    case 0x2: {
  OPC_SwitchField, 0, 3,                     // 10545:     switch Inst[2:0] {
  4, 9,                                      // 10548:     case 0x4: {
  OPC_CheckField, 21, 2, 0,                  // 10550:      check Inst[22:21] == 0x0
  OPC_Decode, 131, 7, 179, 1,                // 10554:      decode to DTSTSF using decoder 179
                                             // 10554:     }
  6, 0,                                      // 10559:     case 0x6: {
  OPC_CheckField, 22, 1, 0,                  // 10561:      check Inst[22] == 0x0
  OPC_Decode, 132, 7, 181, 1,                // 10565:      decode to DTSTSFI using decoder 181
                                             // 10565:     }
                                             // 10565:     } // switch Inst[2:0]
                                             // 10565:    }
  3, 0,                                      // 10570:    case 0x3: {
  OPC_Decode, 253, 20, 180, 1,               // 10572:     decode to XSMERGE2T1UQM using decoder 180
                                             // 10572:    }
                                             // 10572:    } // switch Inst[10:9]
                                             // 10572:   }
  6, 37,                                     // 10577:   case 0x6: {
  OPC_SwitchField, 9, 1,                     // 10579:    switch Inst[9] {
  0, 13,                                     // 10582:    case 0x0: {
  OPC_CheckField, 21, 2, 0,                  // 10584:     check Inst[22:21] == 0x0
  OPC_CheckField, 0, 3, 4,                   // 10588:     check Inst[2:0] == 0x4
  OPC_Decode, 253, 6, 182, 1,                // 10592:     decode to DTSTDC using decoder 182
                                             // 10592:    }
  1, 0,                                      // 10597:    case 0x1: {
  OPC_SwitchField, 10, 1,                    // 10599:     switch Inst[10] {
  0, 5,                                      // 10602:     case 0x0: {
  OPC_Decode, 191, 20, 180, 1,               // 10604:      decode to XSADDSUBUQM using decoder 180
                                             // 10604:     }
  1, 0,                                      // 10609:     case 0x1: {
  OPC_Decode, 254, 20, 180, 1,               // 10611:      decode to XSMERGE2T2UQM using decoder 180
                                             // 10611:     }
                                             // 10611:     } // switch Inst[10]
                                             // 10611:    }
                                             // 10611:    } // switch Inst[9]
                                             // 10611:   }
  7, 0,                                      // 10616:   case 0x7: {
  OPC_SwitchField, 0, 3,                     // 10618:    switch Inst[2:0] {
  4, 13,                                     // 10621:    case 0x4: {
  OPC_CheckField, 21, 2, 0,                  // 10623:     check Inst[22:21] == 0x0
  OPC_CheckField, 9, 1, 0,                   // 10627:     check Inst[9] == 0x0
  OPC_Decode, 255, 6, 182, 1,                // 10631:     decode to DTSTDG using decoder 182
                                             // 10631:    }
  6, 9,                                      // 10636:    case 0x6: {
  OPC_CheckField, 17, 4, 0,                  // 10638:     check Inst[20:17] == 0x0
  OPC_Decode, 217, 6, 178, 1,                // 10642:     decode to DRINTN using decoder 178
                                             // 10642:    }
  7, 0,                                      // 10647:    case 0x7: {
  OPC_CheckField, 17, 4, 0,                  // 10649:     check Inst[20:17] == 0x0
  OPC_Decode, 220, 6, 178, 1,                // 10653:     decode to DRINTN_rec using decoder 178
                                             // 10653:    }
                                             // 10653:    } // switch Inst[2:0]
                                             // 10653:   }
                                             // 10653:   } // switch Inst[8:6]
                                             // 10653:  }
  1, 119,                                    // 10658:  case 0x1: {
  OPC_SwitchField, 6, 2,                     // 10660:   switch Inst[7:6] {
  0, 5,                                      // 10663:   case 0x0: {
  OPC_Decode, 147, 23, 183, 1,               // 10665:    decode to XXMULMUL using decoder 183
                                             // 10665:   }
  1, 5,                                      // 10670:   case 0x1: {
  OPC_Decode, 148, 23, 184, 1,               // 10672:    decode to XXMULMULHIADD using decoder 184
                                             // 10672:   }
  2, 43,                                     // 10677:   case 0x2: {
  OPC_SwitchField, 10, 1,                    // 10679:    switch Inst[10] {
  0, 5,                                      // 10682:    case 0x0: {
  OPC_Decode, 149, 23, 185, 1,               // 10684:     decode to XXMULMULLOADD using decoder 185
                                             // 10684:    }
  1, 0,                                      // 10689:    case 0x1: {
  OPC_SwitchField, 8, 2,                     // 10691:     switch Inst[9:8] {
  0, 5,                                      // 10694:     case 0x0: {
  OPC_Decode, 165, 21, 180, 1,               // 10696:      decode to XSREBASE2T1UQM using decoder 180
                                             // 10696:     }
  1, 5,                                      // 10701:     case 0x1: {
  OPC_Decode, 166, 21, 180, 1,               // 10703:      decode to XSREBASE2T2UQM using decoder 180
                                             // 10703:     }
  2, 5,                                      // 10708:     case 0x2: {
  OPC_Decode, 167, 21, 180, 1,               // 10710:      decode to XSREBASE2T3UQM using decoder 180
                                             // 10710:     }
  3, 0,                                      // 10715:     case 0x3: {
  OPC_Decode, 169, 21, 180, 1,               // 10717:      decode to XSREBASE3T1UQM using decoder 180
                                             // 10717:     }
                                             // 10717:     } // switch Inst[9:8]
                                             // 10717:    }
                                             // 10717:    } // switch Inst[10]
                                             // 10717:   }
  3, 0,                                      // 10722:   case 0x3: {
  OPC_SwitchField, 8, 2,                     // 10724:    switch Inst[9:8] {
  0, 5,                                      // 10727:    case 0x0: {
  OPC_Decode, 165, 23, 186, 1,               // 10729:     decode to XXSSUMUDM using decoder 186
                                             // 10729:    }
  1, 5,                                      // 10734:    case 0x1: {
  OPC_Decode, 166, 23, 186, 1,               // 10736:     decode to XXSSUMUDMC using decoder 186
                                             // 10736:    }
  2, 17,                                     // 10741:    case 0x2: {
  OPC_SwitchField, 10, 1,                    // 10743:     switch Inst[10] {
  0, 5,                                      // 10746:     case 0x0: {
  OPC_Decode, 255, 20, 180, 1,               // 10748:      decode to XSMERGE2T3UQM using decoder 180
                                             // 10748:     }
  1, 0,                                      // 10753:     case 0x1: {
  OPC_Decode, 168, 21, 180, 1,               // 10755:      decode to XSREBASE2T4UQM using decoder 180
                                             // 10755:     }
                                             // 10755:     } // switch Inst[10]
                                             // 10755:    }
  3, 0,                                      // 10760:    case 0x3: {
  OPC_SwitchField, 10, 1,                    // 10762:     switch Inst[10] {
  0, 5,                                      // 10765:     case 0x0: {
  OPC_Decode, 128, 21, 180, 1,               // 10767:      decode to XSMERGE3T1UQM using decoder 180
                                             // 10767:     }
  1, 0,                                      // 10772:     case 0x1: {
  OPC_Decode, 170, 21, 180, 1,               // 10774:      decode to XSREBASE3T2UQM using decoder 180
                                             // 10774:     }
                                             // 10774:     } // switch Inst[10]
                                             // 10774:    }
                                             // 10774:    } // switch Inst[9:8]
                                             // 10774:   }
                                             // 10774:   } // switch Inst[7:6]
                                             // 10774:  }
  2, 146, 3,                                 // 10779:  case 0x2: {
  OPC_SwitchField, 6, 5,                     // 10782:   switch Inst[10:6] {
  0, 13,                                     // 10785:   case 0x0: {
  OPC_CheckField, 21, 2, 0,                  // 10787:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 10791:    check Inst[0] == 0x0
  OPC_Decode, 166, 22, 187, 1,               // 10795:    decode to XVI8GER4PP using decoder 187
                                             // 10795:   }
  1, 17,                                     // 10800:   case 0x1: {
  OPC_CheckField, 21, 2, 0,                  // 10802:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 10806:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 10810:    check Inst[0] == 0x0
  OPC_Decode, 197, 6, 188, 1,                // 10814:    decode to DMXVI8GERX4PP using decoder 188
                                             // 10814:   }
  2, 13,                                     // 10819:   case 0x2: {
  OPC_CheckField, 21, 2, 0,                  // 10821:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 10825:    check Inst[0] == 0x0
  OPC_Decode, 255, 21, 187, 1,               // 10829:    decode to XVF16GER2PP using decoder 187
                                             // 10829:   }
  3, 13,                                     // 10834:   case 0x3: {
  OPC_CheckField, 21, 2, 0,                  // 10836:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 10840:    check Inst[0] == 0x0
  OPC_Decode, 137, 22, 187, 1,               // 10844:    decode to XVF32GERPP using decoder 187
                                             // 10844:   }
  4, 13,                                     // 10849:   case 0x4: {
  OPC_CheckField, 21, 2, 0,                  // 10851:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 10855:    check Inst[0] == 0x0
  OPC_Decode, 162, 22, 187, 1,               // 10859:    decode to XVI4GER8PP using decoder 187
                                             // 10859:   }
  5, 13,                                     // 10864:   case 0x5: {
  OPC_CheckField, 21, 2, 0,                  // 10866:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 10870:    check Inst[0] == 0x0
  OPC_Decode, 156, 22, 187, 1,               // 10874:    decode to XVI16GER2SPP using decoder 187
                                             // 10874:   }
  6, 13,                                     // 10879:   case 0x6: {
  OPC_CheckField, 21, 2, 0,                  // 10881:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 10885:    check Inst[0] == 0x0
  OPC_Decode, 207, 21, 187, 1,               // 10889:    decode to XVBF16GER2PP using decoder 187
                                             // 10889:   }
  7, 13,                                     // 10894:   case 0x7: {
  OPC_CheckField, 21, 2, 0,                  // 10896:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 10900:    check Inst[0] == 0x0
  OPC_Decode, 147, 22, 189, 1,               // 10904:    decode to XVF64GERPP using decoder 189
                                             // 10904:   }
  8, 17,                                     // 10909:   case 0x8: {
  OPC_CheckField, 21, 2, 0,                  // 10911:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 10915:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 10919:    check Inst[0] == 0x0
  OPC_Decode, 195, 6, 188, 1,                // 10923:    decode to DMXVF16GERX2PP using decoder 188
                                             // 10923:   }
  9, 17,                                     // 10928:   case 0x9: {
  OPC_CheckField, 21, 2, 0,                  // 10930:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 10934:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 10938:    check Inst[0] == 0x0
  OPC_Decode, 190, 6, 188, 1,                // 10942:    decode to DMXVBF16GERX2PP using decoder 188
                                             // 10942:   }
  10, 13,                                    // 10947:   case 0xa: {
  OPC_CheckField, 21, 2, 0,                  // 10949:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 10953:    check Inst[0] == 0x0
  OPC_Decode, 253, 21, 187, 1,               // 10957:    decode to XVF16GER2NP using decoder 187
                                             // 10957:   }
  11, 13,                                    // 10962:   case 0xb: {
  OPC_CheckField, 21, 2, 0,                  // 10964:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 10968:    check Inst[0] == 0x0
  OPC_Decode, 135, 22, 187, 1,               // 10972:    decode to XVF32GERNP using decoder 187
                                             // 10972:   }
  12, 17,                                    // 10977:   case 0xc: {
  OPC_CheckField, 21, 2, 0,                  // 10979:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 10983:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 10987:    check Inst[0] == 0x0
  OPC_Decode, 198, 6, 188, 1,                // 10991:    decode to DMXVI8GERX4SPP using decoder 188
                                             // 10991:   }
  14, 13,                                    // 10996:   case 0xe: {
  OPC_CheckField, 21, 2, 0,                  // 10998:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11002:    check Inst[0] == 0x0
  OPC_Decode, 205, 21, 187, 1,               // 11006:    decode to XVBF16GER2NP using decoder 187
                                             // 11006:   }
  15, 13,                                    // 11011:   case 0xf: {
  OPC_CheckField, 21, 2, 0,                  // 11013:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11017:    check Inst[0] == 0x0
  OPC_Decode, 145, 22, 189, 1,               // 11021:    decode to XVF64GERNP using decoder 189
                                             // 11021:   }
  18, 13,                                    // 11026:   case 0x12: {
  OPC_CheckField, 21, 2, 0,                  // 11028:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11032:    check Inst[0] == 0x0
  OPC_Decode, 254, 21, 187, 1,               // 11036:    decode to XVF16GER2PN using decoder 187
                                             // 11036:   }
  19, 13,                                    // 11041:   case 0x13: {
  OPC_CheckField, 21, 2, 0,                  // 11043:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11047:    check Inst[0] == 0x0
  OPC_Decode, 136, 22, 187, 1,               // 11051:    decode to XVF32GERPN using decoder 187
                                             // 11051:   }
  22, 13,                                    // 11056:   case 0x16: {
  OPC_CheckField, 21, 2, 0,                  // 11058:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11062:    check Inst[0] == 0x0
  OPC_Decode, 206, 21, 187, 1,               // 11066:    decode to XVBF16GER2PN using decoder 187
                                             // 11066:   }
  23, 13,                                    // 11071:   case 0x17: {
  OPC_CheckField, 21, 2, 0,                  // 11073:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11077:    check Inst[0] == 0x0
  OPC_Decode, 146, 22, 189, 1,               // 11081:    decode to XVF64GERPN using decoder 189
                                             // 11081:   }
  25, 17,                                    // 11086:   case 0x19: {
  OPC_CheckField, 21, 2, 0,                  // 11088:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 11092:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11096:    check Inst[0] == 0x0
  OPC_Decode, 192, 6, 188, 1,                // 11100:    decode to DMXVF16GERX2NN using decoder 188
                                             // 11100:   }
  26, 13,                                    // 11105:   case 0x1a: {
  OPC_CheckField, 21, 2, 0,                  // 11107:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11111:    check Inst[0] == 0x0
  OPC_Decode, 252, 21, 187, 1,               // 11115:    decode to XVF16GER2NN using decoder 187
                                             // 11115:   }
  27, 13,                                    // 11120:   case 0x1b: {
  OPC_CheckField, 21, 2, 0,                  // 11122:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11126:    check Inst[0] == 0x0
  OPC_Decode, 134, 22, 187, 1,               // 11130:    decode to XVF32GERNN using decoder 187
                                             // 11130:   }
  29, 17,                                    // 11135:   case 0x1d: {
  OPC_CheckField, 21, 2, 0,                  // 11137:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 11141:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11145:    check Inst[0] == 0x0
  OPC_Decode, 187, 6, 188, 1,                // 11149:    decode to DMXVBF16GERX2NN using decoder 188
                                             // 11149:   }
  30, 13,                                    // 11154:   case 0x1e: {
  OPC_CheckField, 21, 2, 0,                  // 11156:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11160:    check Inst[0] == 0x0
  OPC_Decode, 204, 21, 187, 1,               // 11164:    decode to XVBF16GER2NN using decoder 187
                                             // 11164:   }
  31, 0,                                     // 11169:   case 0x1f: {
  OPC_CheckField, 21, 2, 0,                  // 11171:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11175:    check Inst[0] == 0x0
  OPC_Decode, 144, 22, 189, 1,               // 11179:    decode to XVF64GERNN using decoder 189
                                             // 11179:   }
                                             // 11179:   } // switch Inst[10:6]
                                             // 11179:  }
  3, 219, 2,                                 // 11184:  case 0x3: {
  OPC_SwitchField, 6, 5,                     // 11187:   switch Inst[10:6] {
  0, 13,                                     // 11190:   case 0x0: {
  OPC_CheckField, 21, 2, 0,                  // 11192:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11196:    check Inst[0] == 0x0
  OPC_Decode, 165, 22, 190, 1,               // 11200:    decode to XVI8GER4 using decoder 190
                                             // 11200:   }
  1, 17,                                     // 11205:   case 0x1: {
  OPC_CheckField, 21, 2, 0,                  // 11207:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 11211:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11215:    check Inst[0] == 0x0
  OPC_Decode, 196, 6, 191, 1,                // 11219:    decode to DMXVI8GERX4 using decoder 191
                                             // 11219:   }
  2, 13,                                     // 11224:   case 0x2: {
  OPC_CheckField, 21, 2, 0,                  // 11226:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11230:    check Inst[0] == 0x0
  OPC_Decode, 251, 21, 190, 1,               // 11234:    decode to XVF16GER2 using decoder 190
                                             // 11234:   }
  3, 13,                                     // 11239:   case 0x3: {
  OPC_CheckField, 21, 2, 0,                  // 11241:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11245:    check Inst[0] == 0x0
  OPC_Decode, 133, 22, 190, 1,               // 11249:    decode to XVF32GER using decoder 190
                                             // 11249:   }
  4, 13,                                     // 11254:   case 0x4: {
  OPC_CheckField, 21, 2, 0,                  // 11256:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11260:    check Inst[0] == 0x0
  OPC_Decode, 161, 22, 190, 1,               // 11264:    decode to XVI4GER8 using decoder 190
                                             // 11264:   }
  5, 13,                                     // 11269:   case 0x5: {
  OPC_CheckField, 21, 2, 0,                  // 11271:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11275:    check Inst[0] == 0x0
  OPC_Decode, 155, 22, 190, 1,               // 11279:    decode to XVI16GER2S using decoder 190
                                             // 11279:   }
  6, 13,                                     // 11284:   case 0x6: {
  OPC_CheckField, 21, 2, 0,                  // 11286:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11290:    check Inst[0] == 0x0
  OPC_Decode, 203, 21, 190, 1,               // 11294:    decode to XVBF16GER2 using decoder 190
                                             // 11294:   }
  7, 13,                                     // 11299:   case 0x7: {
  OPC_CheckField, 21, 2, 0,                  // 11301:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11305:    check Inst[0] == 0x0
  OPC_Decode, 143, 22, 192, 1,               // 11309:    decode to XVF64GER using decoder 192
                                             // 11309:   }
  8, 17,                                     // 11314:   case 0x8: {
  OPC_CheckField, 21, 2, 0,                  // 11316:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 11320:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11324:    check Inst[0] == 0x0
  OPC_Decode, 191, 6, 191, 1,                // 11328:    decode to DMXVF16GERX2 using decoder 191
                                             // 11328:   }
  9, 13,                                     // 11333:   case 0x9: {
  OPC_CheckField, 21, 2, 0,                  // 11335:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11339:    check Inst[0] == 0x0
  OPC_Decode, 153, 22, 190, 1,               // 11343:    decode to XVI16GER2 using decoder 190
                                             // 11343:   }
  10, 17,                                    // 11348:   case 0xa: {
  OPC_CheckField, 21, 2, 0,                  // 11350:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 11354:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11358:    check Inst[0] == 0x0
  OPC_Decode, 193, 6, 188, 1,                // 11362:    decode to DMXVF16GERX2NP using decoder 188
                                             // 11362:   }
  11, 17,                                    // 11367:   case 0xb: {
  OPC_CheckField, 21, 2, 0,                  // 11369:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 11373:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11377:    check Inst[0] == 0x0
  OPC_Decode, 186, 6, 191, 1,                // 11381:    decode to DMXVBF16GERX2 using decoder 191
                                             // 11381:   }
  12, 13,                                    // 11386:   case 0xc: {
  OPC_CheckField, 21, 2, 0,                  // 11388:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11392:    check Inst[0] == 0x0
  OPC_Decode, 167, 22, 187, 1,               // 11396:    decode to XVI8GER4SPP using decoder 187
                                             // 11396:   }
  13, 13,                                    // 11401:   case 0xd: {
  OPC_CheckField, 21, 2, 0,                  // 11403:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11407:    check Inst[0] == 0x0
  OPC_Decode, 154, 22, 187, 1,               // 11411:    decode to XVI16GER2PP using decoder 187
                                             // 11411:   }
  14, 17,                                    // 11416:   case 0xe: {
  OPC_CheckField, 21, 2, 0,                  // 11418:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 11422:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11426:    check Inst[0] == 0x0
  OPC_Decode, 188, 6, 188, 1,                // 11430:    decode to DMXVBF16GERX2NP using decoder 188
                                             // 11430:   }
  18, 17,                                    // 11435:   case 0x12: {
  OPC_CheckField, 21, 2, 0,                  // 11437:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 11441:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11445:    check Inst[0] == 0x0
  OPC_Decode, 194, 6, 188, 1,                // 11449:    decode to DMXVF16GERX2PN using decoder 188
                                             // 11449:   }
  22, 17,                                    // 11454:   case 0x16: {
  OPC_CheckField, 21, 2, 0,                  // 11456:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 11460:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 11464:    check Inst[0] == 0x0
  OPC_Decode, 189, 6, 188, 1,                // 11468:    decode to DMXVBF16GERX2PN using decoder 188
                                             // 11468:   }
  24, 5,                                     // 11473:   case 0x18: {
  OPC_Decode, 171, 21, 180, 1,               // 11475:    decode to XSREBASE3T3UQM using decoder 180
                                             // 11475:   }
  26, 25,                                    // 11480:   case 0x1a: {
  OPC_SwitchField, 0, 3,                     // 11482:    switch Inst[2:0] {
  4, 9,                                      // 11485:    case 0x4: {
  OPC_CheckField, 16, 5, 0,                  // 11487:     check Inst[20:16] == 0x0
  OPC_Decode, 175, 9, 193, 1,                // 11491:     decode to FCFIDS using decoder 193
                                             // 11491:    }
  5, 0,                                      // 11496:    case 0x5: {
  OPC_CheckField, 16, 5, 0,                  // 11498:     check Inst[20:16] == 0x0
  OPC_Decode, 176, 9, 193, 1,                // 11502:     decode to FCFIDS_rec using decoder 193
                                             // 11502:    }
                                             // 11502:    } // switch Inst[2:0]
                                             // 11502:   }
  30, 0,                                     // 11507:   case 0x1e: {
  OPC_SwitchField, 0, 3,                     // 11509:    switch Inst[2:0] {
  4, 9,                                      // 11512:    case 0x4: {
  OPC_CheckField, 16, 5, 0,                  // 11514:     check Inst[20:16] == 0x0
  OPC_Decode, 178, 9, 193, 1,                // 11518:     decode to FCFIDUS using decoder 193
                                             // 11518:    }
  5, 0,                                      // 11523:    case 0x5: {
  OPC_CheckField, 16, 5, 0,                  // 11525:     check Inst[20:16] == 0x0
  OPC_Decode, 179, 9, 193, 1,                // 11529:     decode to FCFIDUS_rec using decoder 193
                                             // 11529:    }
                                             // 11529:    } // switch Inst[2:0]
                                             // 11529:   }
                                             // 11529:   } // switch Inst[10:6]
                                             // 11529:  }
  4, 25,                                     // 11534:  case 0x4: {
  OPC_SwitchField, 0, 3,                     // 11536:   switch Inst[2:0] {
  4, 9,                                      // 11539:   case 0x4: {
  OPC_CheckField, 6, 5, 0,                   // 11541:    check Inst[10:6] == 0x0
  OPC_Decode, 207, 9, 194, 1,                // 11545:    decode to FDIVS using decoder 194
                                             // 11545:   }
  5, 0,                                      // 11550:   case 0x5: {
  OPC_CheckField, 6, 5, 0,                   // 11552:    check Inst[10:6] == 0x0
  OPC_Decode, 208, 9, 194, 1,                // 11556:    decode to FDIVS_rec using decoder 194
                                             // 11556:   }
                                             // 11556:   } // switch Inst[2:0]
                                             // 11556:  }
  5, 77,                                     // 11561:  case 0x5: {
  OPC_SwitchField, 0, 3,                     // 11563:   switch Inst[2:0] {
  0, 9,                                      // 11566:   case 0x0: {
  OPC_CheckField, 6, 5, 0,                   // 11568:    check Inst[10:6] == 0x0
  OPC_Decode, 148, 10, 194, 1,               // 11572:    decode to FSUBS using decoder 194
                                             // 11572:   }
  1, 9,                                      // 11577:   case 0x1: {
  OPC_CheckField, 6, 5, 0,                   // 11579:    check Inst[10:6] == 0x0
  OPC_Decode, 149, 10, 194, 1,               // 11583:    decode to FSUBS_rec using decoder 194
                                             // 11583:   }
  2, 9,                                      // 11588:   case 0x2: {
  OPC_CheckField, 6, 5, 0,                   // 11590:    check Inst[10:6] == 0x0
  OPC_Decode, 170, 9, 194, 1,                // 11594:    decode to FADDS using decoder 194
                                             // 11594:   }
  3, 9,                                      // 11599:   case 0x3: {
  OPC_CheckField, 6, 5, 0,                   // 11601:    check Inst[10:6] == 0x0
  OPC_Decode, 171, 9, 194, 1,                // 11605:    decode to FADDS_rec using decoder 194
                                             // 11605:   }
  4, 13,                                     // 11610:   case 0x4: {
  OPC_CheckField, 16, 5, 0,                  // 11612:    check Inst[20:16] == 0x0
  OPC_CheckField, 6, 5, 0,                   // 11616:    check Inst[10:6] == 0x0
  OPC_Decode, 144, 10, 195, 1,               // 11620:    decode to FSQRTS using decoder 195
                                             // 11620:   }
  5, 0,                                      // 11625:   case 0x5: {
  OPC_CheckField, 16, 5, 0,                  // 11627:    check Inst[20:16] == 0x0
  OPC_CheckField, 6, 5, 0,                   // 11631:    check Inst[10:6] == 0x0
  OPC_Decode, 145, 10, 195, 1,               // 11635:    decode to FSQRTS_rec using decoder 195
                                             // 11635:   }
                                             // 11635:   } // switch Inst[2:0]
                                             // 11635:  }
  6, 85,                                     // 11640:  case 0x6: {
  OPC_SwitchField, 0, 3,                     // 11642:   switch Inst[2:0] {
  0, 13,                                     // 11645:   case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 11647:    check Inst[20:16] == 0x0
  OPC_CheckField, 6, 5, 0,                   // 11651:    check Inst[10:6] == 0x0
  OPC_Decode, 242, 9, 195, 1,                // 11655:    decode to FRES using decoder 195
                                             // 11655:   }
  1, 13,                                     // 11660:   case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 11662:    check Inst[20:16] == 0x0
  OPC_CheckField, 6, 5, 0,                   // 11666:    check Inst[10:6] == 0x0
  OPC_Decode, 243, 9, 195, 1,                // 11670:    decode to FRES_rec using decoder 195
                                             // 11670:   }
  2, 9,                                      // 11675:   case 0x2: {
  OPC_CheckField, 11, 5, 0,                  // 11677:    check Inst[15:11] == 0x0
  OPC_Decode, 222, 9, 196, 1,                // 11681:    decode to FMULS using decoder 196
                                             // 11681:   }
  3, 9,                                      // 11686:   case 0x3: {
  OPC_CheckField, 11, 5, 0,                  // 11688:    check Inst[15:11] == 0x0
  OPC_Decode, 223, 9, 196, 1,                // 11692:    decode to FMULS_rec using decoder 196
                                             // 11692:   }
  4, 13,                                     // 11697:   case 0x4: {
  OPC_CheckField, 16, 5, 0,                  // 11699:    check Inst[20:16] == 0x0
  OPC_CheckField, 6, 5, 0,                   // 11703:    check Inst[10:6] == 0x0
  OPC_Decode, 136, 10, 195, 1,               // 11707:    decode to FRSQRTES using decoder 195
                                             // 11707:   }
  5, 0,                                      // 11712:   case 0x5: {
  OPC_CheckField, 16, 5, 0,                  // 11714:    check Inst[20:16] == 0x0
  OPC_CheckField, 6, 5, 0,                   // 11718:    check Inst[10:6] == 0x0
  OPC_Decode, 137, 10, 195, 1,               // 11722:    decode to FRSQRTES_rec using decoder 195
                                             // 11722:   }
                                             // 11722:   } // switch Inst[2:0]
                                             // 11722:  }
  7, 0,                                      // 11727:  case 0x7: {
  OPC_SwitchField, 0, 3,                     // 11729:   switch Inst[2:0] {
  0, 5,                                      // 11732:   case 0x0: {
  OPC_Decode, 218, 9, 197, 1,                // 11734:    decode to FMSUBS using decoder 197
                                             // 11734:   }
  1, 5,                                      // 11739:   case 0x1: {
  OPC_Decode, 219, 9, 197, 1,                // 11741:    decode to FMSUBS_rec using decoder 197
                                             // 11741:   }
  2, 5,                                      // 11746:   case 0x2: {
  OPC_Decode, 212, 9, 197, 1,                // 11748:    decode to FMADDS using decoder 197
                                             // 11748:   }
  3, 5,                                      // 11753:   case 0x3: {
  OPC_Decode, 213, 9, 197, 1,                // 11755:    decode to FMADDS_rec using decoder 197
                                             // 11755:   }
  4, 5,                                      // 11760:   case 0x4: {
  OPC_Decode, 238, 9, 197, 1,                // 11762:    decode to FNMSUBS using decoder 197
                                             // 11762:   }
  5, 5,                                      // 11767:   case 0x5: {
  OPC_Decode, 239, 9, 197, 1,                // 11769:    decode to FNMSUBS_rec using decoder 197
                                             // 11769:   }
  6, 5,                                      // 11774:   case 0x6: {
  OPC_Decode, 234, 9, 197, 1,                // 11776:    decode to FNMADDS using decoder 197
                                             // 11776:   }
  7, 0,                                      // 11781:   case 0x7: {
  OPC_Decode, 235, 9, 197, 1,                // 11783:    decode to FNMADDS_rec using decoder 197
                                             // 11783:   }
                                             // 11783:   } // switch Inst[2:0]
                                             // 11783:  }
                                             // 11783:  } // switch Inst[5:3]
                                             // 11783: }
  60, 146, 21,                               // 11788: case 0x3c: {
  OPC_SwitchField, 4, 2,                     // 11791:  switch Inst[5:4] {
  0, 227, 4,                                 // 11794:  case 0x0: {
  OPC_SwitchField, 6, 5,                     // 11797:   switch Inst[10:6] {
  0, 17,                                     // 11800:   case 0x0: {
  OPC_SwitchField, 3, 1,                     // 11802:    switch Inst[3] {
  0, 5,                                      // 11805:    case 0x0: {
  OPC_Decode, 189, 20, 198, 1,               // 11807:     decode to XSADDSP using decoder 198
                                             // 11807:    }
  1, 0,                                      // 11812:    case 0x1: {
  OPC_Decode, 244, 20, 199, 1,               // 11814:     decode to XSMADDASP using decoder 199
                                             // 11814:    }
                                             // 11814:    } // switch Inst[3]
                                             // 11814:   }
  1, 17,                                     // 11819:   case 0x1: {
  OPC_SwitchField, 3, 1,                     // 11821:    switch Inst[3] {
  0, 5,                                      // 11824:    case 0x0: {
  OPC_Decode, 187, 21, 198, 1,               // 11826:     decode to XSSUBSP using decoder 198
                                             // 11826:    }
  1, 0,                                      // 11831:    case 0x1: {
  OPC_Decode, 246, 20, 199, 1,               // 11833:     decode to XSMADDMSP using decoder 199
                                             // 11833:    }
                                             // 11833:    } // switch Inst[3]
                                             // 11833:   }
  2, 17,                                     // 11838:   case 0x2: {
  OPC_SwitchField, 3, 1,                     // 11840:    switch Inst[3] {
  0, 5,                                      // 11843:    case 0x0: {
  OPC_Decode, 142, 21, 198, 1,               // 11845:     decode to XSMULSP using decoder 198
                                             // 11845:    }
  1, 0,                                      // 11850:    case 0x1: {
  OPC_Decode, 134, 21, 199, 1,               // 11852:     decode to XSMSUBASP using decoder 199
                                             // 11852:    }
                                             // 11852:    } // switch Inst[3]
                                             // 11852:   }
  3, 17,                                     // 11857:   case 0x3: {
  OPC_SwitchField, 3, 1,                     // 11859:    switch Inst[3] {
  0, 5,                                      // 11862:    case 0x0: {
  OPC_Decode, 240, 20, 198, 1,               // 11864:     decode to XSDIVSP using decoder 198
                                             // 11864:    }
  1, 0,                                      // 11869:    case 0x1: {
  OPC_Decode, 136, 21, 199, 1,               // 11871:     decode to XSMSUBMSP using decoder 199
                                             // 11871:    }
                                             // 11871:    } // switch Inst[3]
                                             // 11871:   }
  4, 17,                                     // 11876:   case 0x4: {
  OPC_SwitchField, 3, 1,                     // 11878:    switch Inst[3] {
  0, 5,                                      // 11881:    case 0x0: {
  OPC_Decode, 186, 20, 200, 1,               // 11883:     decode to XSADDDP using decoder 200
                                             // 11883:    }
  1, 0,                                      // 11888:    case 0x1: {
  OPC_Decode, 243, 20, 201, 1,               // 11890:     decode to XSMADDADP using decoder 201
                                             // 11890:    }
                                             // 11890:    } // switch Inst[3]
                                             // 11890:   }
  5, 17,                                     // 11895:   case 0x5: {
  OPC_SwitchField, 3, 1,                     // 11897:    switch Inst[3] {
  0, 5,                                      // 11900:    case 0x0: {
  OPC_Decode, 184, 21, 200, 1,               // 11902:     decode to XSSUBDP using decoder 200
                                             // 11902:    }
  1, 0,                                      // 11907:    case 0x1: {
  OPC_Decode, 245, 20, 201, 1,               // 11909:     decode to XSMADDMDP using decoder 201
                                             // 11909:    }
                                             // 11909:    } // switch Inst[3]
                                             // 11909:   }
  6, 17,                                     // 11914:   case 0x6: {
  OPC_SwitchField, 3, 1,                     // 11916:    switch Inst[3] {
  0, 5,                                      // 11919:    case 0x0: {
  OPC_Decode, 139, 21, 200, 1,               // 11921:     decode to XSMULDP using decoder 200
                                             // 11921:    }
  1, 0,                                      // 11926:    case 0x1: {
  OPC_Decode, 133, 21, 201, 1,               // 11928:     decode to XSMSUBADP using decoder 201
                                             // 11928:    }
                                             // 11928:    } // switch Inst[3]
                                             // 11928:   }
  7, 17,                                     // 11933:   case 0x7: {
  OPC_SwitchField, 3, 1,                     // 11935:    switch Inst[3] {
  0, 5,                                      // 11938:    case 0x0: {
  OPC_Decode, 237, 20, 200, 1,               // 11940:     decode to XSDIVDP using decoder 200
                                             // 11940:    }
  1, 0,                                      // 11945:    case 0x1: {
  OPC_Decode, 135, 21, 201, 1,               // 11947:     decode to XSMSUBMDP using decoder 201
                                             // 11947:    }
                                             // 11947:    } // switch Inst[3]
                                             // 11947:   }
  8, 17,                                     // 11952:   case 0x8: {
  OPC_SwitchField, 3, 1,                     // 11954:    switch Inst[3] {
  0, 5,                                      // 11957:    case 0x0: {
  OPC_Decode, 200, 21, 180, 1,               // 11959:     decode to XVADDSP using decoder 180
                                             // 11959:    }
  1, 0,                                      // 11964:    case 0x1: {
  OPC_Decode, 174, 22, 202, 1,               // 11966:     decode to XVMADDASP using decoder 202
                                             // 11966:    }
                                             // 11966:    } // switch Inst[3]
                                             // 11966:   }
  9, 17,                                     // 11971:   case 0x9: {
  OPC_SwitchField, 3, 1,                     // 11973:    switch Inst[3] {
  0, 5,                                      // 11976:    case 0x0: {
  OPC_Decode, 223, 22, 180, 1,               // 11978:     decode to XVSUBSP using decoder 180
                                             // 11978:    }
  1, 0,                                      // 11983:    case 0x1: {
  OPC_Decode, 176, 22, 202, 1,               // 11985:     decode to XVMADDMSP using decoder 202
                                             // 11985:    }
                                             // 11985:    } // switch Inst[3]
                                             // 11985:   }
  10, 17,                                    // 11990:   case 0xa: {
  OPC_SwitchField, 3, 1,                     // 11992:    switch Inst[3] {
  0, 5,                                      // 11995:    case 0x0: {
  OPC_Decode, 190, 22, 180, 1,               // 11997:     decode to XVMULSP using decoder 180
                                             // 11997:    }
  1, 0,                                      // 12002:    case 0x1: {
  OPC_Decode, 182, 22, 202, 1,               // 12004:     decode to XVMSUBASP using decoder 202
                                             // 12004:    }
                                             // 12004:    } // switch Inst[3]
                                             // 12004:   }
  11, 17,                                    // 12009:   case 0xb: {
  OPC_SwitchField, 3, 1,                     // 12011:    switch Inst[3] {
  0, 5,                                      // 12014:    case 0x0: {
  OPC_Decode, 250, 21, 180, 1,               // 12016:     decode to XVDIVSP using decoder 180
                                             // 12016:    }
  1, 0,                                      // 12021:    case 0x1: {
  OPC_Decode, 184, 22, 202, 1,               // 12023:     decode to XVMSUBMSP using decoder 202
                                             // 12023:    }
                                             // 12023:    } // switch Inst[3]
                                             // 12023:   }
  12, 17,                                    // 12028:   case 0xc: {
  OPC_SwitchField, 3, 1,                     // 12030:    switch Inst[3] {
  0, 5,                                      // 12033:    case 0x0: {
  OPC_Decode, 199, 21, 180, 1,               // 12035:     decode to XVADDDP using decoder 180
                                             // 12035:    }
  1, 0,                                      // 12040:    case 0x1: {
  OPC_Decode, 173, 22, 202, 1,               // 12042:     decode to XVMADDADP using decoder 202
                                             // 12042:    }
                                             // 12042:    } // switch Inst[3]
                                             // 12042:   }
  13, 17,                                    // 12047:   case 0xd: {
  OPC_SwitchField, 3, 1,                     // 12049:    switch Inst[3] {
  0, 5,                                      // 12052:    case 0x0: {
  OPC_Decode, 222, 22, 180, 1,               // 12054:     decode to XVSUBDP using decoder 180
                                             // 12054:    }
  1, 0,                                      // 12059:    case 0x1: {
  OPC_Decode, 175, 22, 202, 1,               // 12061:     decode to XVMADDMDP using decoder 202
                                             // 12061:    }
                                             // 12061:    } // switch Inst[3]
                                             // 12061:   }
  14, 17,                                    // 12066:   case 0xe: {
  OPC_SwitchField, 3, 1,                     // 12068:    switch Inst[3] {
  0, 5,                                      // 12071:    case 0x0: {
  OPC_Decode, 185, 22, 180, 1,               // 12073:     decode to XVMULDP using decoder 180
                                             // 12073:    }
  1, 0,                                      // 12078:    case 0x1: {
  OPC_Decode, 181, 22, 202, 1,               // 12080:     decode to XVMSUBADP using decoder 202
                                             // 12080:    }
                                             // 12080:    } // switch Inst[3]
                                             // 12080:   }
  15, 17,                                    // 12085:   case 0xf: {
  OPC_SwitchField, 3, 1,                     // 12087:    switch Inst[3] {
  0, 5,                                      // 12090:    case 0x0: {
  OPC_Decode, 249, 21, 180, 1,               // 12092:     decode to XVDIVDP using decoder 180
                                             // 12092:    }
  1, 0,                                      // 12097:    case 0x1: {
  OPC_Decode, 183, 22, 202, 1,               // 12099:     decode to XVMSUBMDP using decoder 202
                                             // 12099:    }
                                             // 12099:    } // switch Inst[3]
                                             // 12099:   }
  16, 17,                                    // 12104:   case 0x10: {
  OPC_SwitchField, 3, 1,                     // 12106:    switch Inst[3] {
  0, 5,                                      // 12109:    case 0x0: {
  OPC_Decode, 249, 20, 200, 1,               // 12111:     decode to XSMAXCDP using decoder 200
                                             // 12111:    }
  1, 0,                                      // 12116:    case 0x1: {
  OPC_Decode, 149, 21, 199, 1,               // 12118:     decode to XSNMADDASP using decoder 199
                                             // 12118:    }
                                             // 12118:    } // switch Inst[3]
                                             // 12118:   }
  17, 17,                                    // 12123:   case 0x11: {
  OPC_SwitchField, 3, 1,                     // 12125:    switch Inst[3] {
  0, 5,                                      // 12128:    case 0x0: {
  OPC_Decode, 129, 21, 200, 1,               // 12130:     decode to XSMINCDP using decoder 200
                                             // 12130:    }
  1, 0,                                      // 12135:    case 0x1: {
  OPC_Decode, 151, 21, 199, 1,               // 12137:     decode to XSNMADDMSP using decoder 199
                                             // 12137:    }
                                             // 12137:    } // switch Inst[3]
                                             // 12137:   }
  18, 17,                                    // 12142:   case 0x12: {
  OPC_SwitchField, 3, 1,                     // 12144:    switch Inst[3] {
  0, 5,                                      // 12147:    case 0x0: {
  OPC_Decode, 252, 20, 203, 1,               // 12149:     decode to XSMAXJDP using decoder 203
                                             // 12149:    }
  1, 0,                                      // 12154:    case 0x1: {
  OPC_Decode, 155, 21, 199, 1,               // 12156:     decode to XSNMSUBASP using decoder 199
                                             // 12156:    }
                                             // 12156:    } // switch Inst[3]
                                             // 12156:   }
  19, 17,                                    // 12161:   case 0x13: {
  OPC_SwitchField, 3, 1,                     // 12163:    switch Inst[3] {
  0, 5,                                      // 12166:    case 0x0: {
  OPC_Decode, 132, 21, 203, 1,               // 12168:     decode to XSMINJDP using decoder 203
                                             // 12168:    }
  1, 0,                                      // 12173:    case 0x1: {
  OPC_Decode, 157, 21, 199, 1,               // 12175:     decode to XSNMSUBMSP using decoder 199
                                             // 12175:    }
                                             // 12175:    } // switch Inst[3]
                                             // 12175:   }
  20, 17,                                    // 12180:   case 0x14: {
  OPC_SwitchField, 3, 1,                     // 12182:    switch Inst[3] {
  0, 5,                                      // 12185:    case 0x0: {
  OPC_Decode, 251, 20, 200, 1,               // 12187:     decode to XSMAXDP using decoder 200
                                             // 12187:    }
  1, 0,                                      // 12192:    case 0x1: {
  OPC_Decode, 148, 21, 201, 1,               // 12194:     decode to XSNMADDADP using decoder 201
                                             // 12194:    }
                                             // 12194:    } // switch Inst[3]
                                             // 12194:   }
  21, 17,                                    // 12199:   case 0x15: {
  OPC_SwitchField, 3, 1,                     // 12201:    switch Inst[3] {
  0, 5,                                      // 12204:    case 0x0: {
  OPC_Decode, 131, 21, 200, 1,               // 12206:     decode to XSMINDP using decoder 200
                                             // 12206:    }
  1, 0,                                      // 12211:    case 0x1: {
  OPC_Decode, 150, 21, 201, 1,               // 12213:     decode to XSNMADDMDP using decoder 201
                                             // 12213:    }
                                             // 12213:    } // switch Inst[3]
                                             // 12213:   }
  22, 17,                                    // 12218:   case 0x16: {
  OPC_SwitchField, 3, 1,                     // 12220:    switch Inst[3] {
  0, 5,                                      // 12223:    case 0x0: {
  OPC_Decode, 204, 20, 200, 1,               // 12225:     decode to XSCPSGNDP using decoder 200
                                             // 12225:    }
  1, 0,                                      // 12230:    case 0x1: {
  OPC_Decode, 154, 21, 201, 1,               // 12232:     decode to XSNMSUBADP using decoder 201
                                             // 12232:    }
                                             // 12232:    } // switch Inst[3]
                                             // 12232:   }
  23, 17,                                    // 12237:   case 0x17: {
  OPC_SwitchField, 3, 1,                     // 12239:    switch Inst[3] {
  0, 5,                                      // 12242:    case 0x0: {
  OPC_Decode, 212, 22, 180, 1,               // 12244:     decode to XVRLW using decoder 180
                                             // 12244:    }
  1, 0,                                      // 12249:    case 0x1: {
  OPC_Decode, 156, 21, 201, 1,               // 12251:     decode to XSNMSUBMDP using decoder 201
                                             // 12251:    }
                                             // 12251:    } // switch Inst[3]
                                             // 12251:   }
  24, 17,                                    // 12256:   case 0x18: {
  OPC_SwitchField, 3, 1,                     // 12258:    switch Inst[3] {
  0, 5,                                      // 12261:    case 0x0: {
  OPC_Decode, 178, 22, 180, 1,               // 12263:     decode to XVMAXSP using decoder 180
                                             // 12263:    }
  1, 0,                                      // 12268:    case 0x1: {
  OPC_Decode, 198, 22, 202, 1,               // 12270:     decode to XVNMADDASP using decoder 202
                                             // 12270:    }
                                             // 12270:    } // switch Inst[3]
                                             // 12270:   }
  25, 17,                                    // 12275:   case 0x19: {
  OPC_SwitchField, 3, 1,                     // 12277:    switch Inst[3] {
  0, 5,                                      // 12280:    case 0x0: {
  OPC_Decode, 180, 22, 180, 1,               // 12282:     decode to XVMINSP using decoder 180
                                             // 12282:    }
  1, 0,                                      // 12287:    case 0x1: {
  OPC_Decode, 200, 22, 202, 1,               // 12289:     decode to XVNMADDMSP using decoder 202
                                             // 12289:    }
                                             // 12289:    } // switch Inst[3]
                                             // 12289:   }
  26, 17,                                    // 12294:   case 0x1a: {
  OPC_SwitchField, 3, 1,                     // 12296:    switch Inst[3] {
  0, 5,                                      // 12299:    case 0x0: {
  OPC_Decode, 226, 21, 180, 1,               // 12301:     decode to XVCPSGNSP using decoder 180
                                             // 12301:    }
  1, 0,                                      // 12306:    case 0x1: {
  OPC_Decode, 202, 22, 202, 1,               // 12308:     decode to XVNMSUBASP using decoder 202
                                             // 12308:    }
                                             // 12308:    } // switch Inst[3]
                                             // 12308:   }
  27, 17,                                    // 12313:   case 0x1b: {
  OPC_SwitchField, 3, 1,                     // 12315:    switch Inst[3] {
  0, 5,                                      // 12318:    case 0x0: {
  OPC_Decode, 172, 22, 180, 1,               // 12320:     decode to XVIEXPSP using decoder 180
                                             // 12320:    }
  1, 0,                                      // 12325:    case 0x1: {
  OPC_Decode, 204, 22, 202, 1,               // 12327:     decode to XVNMSUBMSP using decoder 202
                                             // 12327:    }
                                             // 12327:    } // switch Inst[3]
                                             // 12327:   }
  28, 17,                                    // 12332:   case 0x1c: {
  OPC_SwitchField, 3, 1,                     // 12334:    switch Inst[3] {
  0, 5,                                      // 12337:    case 0x0: {
  OPC_Decode, 177, 22, 180, 1,               // 12339:     decode to XVMAXDP using decoder 180
                                             // 12339:    }
  1, 0,                                      // 12344:    case 0x1: {
  OPC_Decode, 197, 22, 202, 1,               // 12346:     decode to XVNMADDADP using decoder 202
                                             // 12346:    }
                                             // 12346:    } // switch Inst[3]
                                             // 12346:   }
  29, 17,                                    // 12351:   case 0x1d: {
  OPC_SwitchField, 3, 1,                     // 12353:    switch Inst[3] {
  0, 5,                                      // 12356:    case 0x0: {
  OPC_Decode, 179, 22, 180, 1,               // 12358:     decode to XVMINDP using decoder 180
                                             // 12358:    }
  1, 0,                                      // 12363:    case 0x1: {
  OPC_Decode, 199, 22, 202, 1,               // 12365:     decode to XVNMADDMDP using decoder 202
                                             // 12365:    }
                                             // 12365:    } // switch Inst[3]
                                             // 12365:   }
  30, 17,                                    // 12370:   case 0x1e: {
  OPC_SwitchField, 3, 1,                     // 12372:    switch Inst[3] {
  0, 5,                                      // 12375:    case 0x0: {
  OPC_Decode, 225, 21, 180, 1,               // 12377:     decode to XVCPSGNDP using decoder 180
                                             // 12377:    }
  1, 0,                                      // 12382:    case 0x1: {
  OPC_Decode, 201, 22, 202, 1,               // 12384:     decode to XVNMSUBADP using decoder 202
                                             // 12384:    }
                                             // 12384:    } // switch Inst[3]
                                             // 12384:   }
  31, 0,                                     // 12389:   case 0x1f: {
  OPC_SwitchField, 3, 1,                     // 12391:    switch Inst[3] {
  0, 5,                                      // 12394:    case 0x0: {
  OPC_Decode, 171, 22, 180, 1,               // 12396:     decode to XVIEXPDP using decoder 180
                                             // 12396:    }
  1, 0,                                      // 12401:    case 0x1: {
  OPC_Decode, 203, 22, 202, 1,               // 12403:     decode to XVNMSUBMDP using decoder 202
                                             // 12403:    }
                                             // 12403:    } // switch Inst[3]
                                             // 12403:   }
                                             // 12403:   } // switch Inst[10:6]
                                             // 12403:  }
  1, 178, 5,                                 // 12408:  case 0x1: {
  OPC_SwitchField, 6, 2,                     // 12411:   switch Inst[7:6] {
  0, 153, 1,                                 // 12414:   case 0x0: {
  OPC_SwitchField, 3, 1,                     // 12417:    switch Inst[3] {
  0, 79,                                     // 12420:    case 0x0: {
  OPC_SwitchField, 10, 1,                    // 12422:     switch Inst[10] {
  0, 5,                                      // 12425:     case 0x0: {
  OPC_Decode, 157, 23, 204, 1,               // 12427:      decode to XXSLDWI using decoder 204
                                             // 12427:     }
  1, 0,                                      // 12432:     case 0x1: {
  OPC_SwitchField, 8, 2,                     // 12434:      switch Inst[9:8] {
  0, 5,                                      // 12437:      case 0x0: {
  OPC_Decode, 128, 23, 180, 1,               // 12439:       decode to XXLAND using decoder 180
                                             // 12439:      }
  1, 5,                                      // 12444:      case 0x1: {
  OPC_Decode, 133, 23, 180, 1,               // 12446:       decode to XXLNOR using decoder 180
                                             // 12446:      }
  2, 5,                                      // 12451:      case 0x2: {
  OPC_Decode, 238, 22, 205, 1,               // 12453:       decode to XXAESENCP using decoder 205
                                             // 12453:      }
  3, 0,                                      // 12458:      case 0x3: {
  OPC_SwitchField, 16, 1,                    // 12460:       switch Inst[16] {
  0, 17,                                     // 12463:       case 0x0: {
  OPC_CheckField, 21, 2, 0,                  // 12465:        check Inst[22:21] == 0x0
  OPC_CheckField, 11, 1, 0,                  // 12469:        check Inst[11] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 12473:        check Inst[0] == 0x0
  OPC_Decode, 200, 6, 206, 1,                // 12477:        decode to DMXXEXTFDMR512 using decoder 206
                                             // 12477:       }
  1, 0,                                      // 12482:       case 0x1: {
  OPC_CheckField, 21, 2, 0,                  // 12484:        check Inst[22:21] == 0x0
  OPC_CheckField, 11, 1, 0,                  // 12488:        check Inst[11] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 12492:        check Inst[0] == 0x0
  OPC_Decode, 201, 6, 207, 1,                // 12496:        decode to DMXXEXTFDMR512_HI using decoder 207
                                             // 12496:       }
                                             // 12496:       } // switch Inst[16]
                                             // 12496:      }
                                             // 12496:      } // switch Inst[9:8]
                                             // 12496:     }
                                             // 12496:     } // switch Inst[10]
                                             // 12496:    }
  1, 0,                                      // 12501:    case 0x1: {
  OPC_SwitchField, 8, 3,                     // 12503:     switch Inst[10:8] {
  0, 5,                                      // 12506:     case 0x0: {
  OPC_Decode, 192, 20, 203, 1,               // 12508:      decode to XSCMPEQDP using decoder 203
                                             // 12508:     }
  1, 13,                                     // 12513:     case 0x1: {
  OPC_CheckField, 21, 2, 0,                  // 12515:      check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 12519:      check Inst[0] == 0x0
  OPC_Decode, 202, 20, 208, 1,               // 12523:      decode to XSCMPUDP using decoder 208
                                             // 12523:     }
  2, 5,                                      // 12528:     case 0x2: {
  OPC_Decode, 215, 21, 180, 1,               // 12530:      decode to XVCMPEQSP using decoder 180
                                             // 12530:     }
  3, 5,                                      // 12535:     case 0x3: {
  OPC_Decode, 213, 21, 180, 1,               // 12537:      decode to XVCMPEQDP using decoder 180
                                             // 12537:     }
  4, 5,                                      // 12542:     case 0x4: {
  OPC_Decode, 202, 21, 180, 1,               // 12544:      decode to XVADDUWM using decoder 180
                                             // 12544:     }
  5, 5,                                      // 12549:     case 0x5: {
  OPC_Decode, 192, 22, 180, 1,               // 12551:      decode to XVMULUWM using decoder 180
                                             // 12551:     }
  6, 5,                                      // 12556:     case 0x6: {
  OPC_Decode, 216, 21, 180, 1,               // 12558:      decode to XVCMPEQSP_rec using decoder 180
                                             // 12558:     }
  7, 0,                                      // 12563:     case 0x7: {
  OPC_Decode, 214, 21, 180, 1,               // 12565:      decode to XVCMPEQDP_rec using decoder 180
                                             // 12565:     }
                                             // 12565:     } // switch Inst[10:8]
                                             // 12565:    }
                                             // 12565:    } // switch Inst[3]
                                             // 12565:   }
  1, 153, 1,                                 // 12570:   case 0x1: {
  OPC_SwitchField, 3, 1,                     // 12573:    switch Inst[3] {
  0, 79,                                     // 12576:    case 0x0: {
  OPC_SwitchField, 10, 1,                    // 12578:     switch Inst[10] {
  0, 5,                                      // 12581:     case 0x0: {
  OPC_Decode, 151, 23, 204, 1,               // 12583:      decode to XXPERMDI using decoder 204
                                             // 12583:     }
  1, 0,                                      // 12588:     case 0x1: {
  OPC_SwitchField, 8, 2,                     // 12590:      switch Inst[9:8] {
  0, 5,                                      // 12593:      case 0x0: {
  OPC_Decode, 129, 23, 180, 1,               // 12595:       decode to XXLANDC using decoder 180
                                             // 12595:      }
  1, 5,                                      // 12600:      case 0x1: {
  OPC_Decode, 135, 23, 180, 1,               // 12602:       decode to XXLORC using decoder 180
                                             // 12602:      }
  2, 5,                                      // 12607:      case 0x2: {
  OPC_Decode, 237, 22, 205, 1,               // 12609:       decode to XXAESDECP using decoder 205
                                             // 12609:      }
  3, 0,                                      // 12614:      case 0x3: {
  OPC_SwitchField, 16, 1,                    // 12616:       switch Inst[16] {
  0, 17,                                     // 12619:       case 0x0: {
  OPC_CheckField, 21, 2, 0,                  // 12621:        check Inst[22:21] == 0x0
  OPC_CheckField, 11, 1, 0,                  // 12625:        check Inst[11] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 12629:        check Inst[0] == 0x0
  OPC_Decode, 203, 6, 209, 1,                // 12633:        decode to DMXXINSTDMR512 using decoder 209
                                             // 12633:       }
  1, 0,                                      // 12638:       case 0x1: {
  OPC_CheckField, 21, 2, 0,                  // 12640:        check Inst[22:21] == 0x0
  OPC_CheckField, 11, 1, 0,                  // 12644:        check Inst[11] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 12648:        check Inst[0] == 0x0
  OPC_Decode, 204, 6, 210, 1,                // 12652:        decode to DMXXINSTDMR512_HI using decoder 210
                                             // 12652:       }
                                             // 12652:       } // switch Inst[16]
                                             // 12652:      }
                                             // 12652:      } // switch Inst[9:8]
                                             // 12652:     }
                                             // 12652:     } // switch Inst[10]
                                             // 12652:    }
  1, 0,                                      // 12657:    case 0x1: {
  OPC_SwitchField, 8, 3,                     // 12659:     switch Inst[10:8] {
  0, 5,                                      // 12662:     case 0x0: {
  OPC_Decode, 198, 20, 203, 1,               // 12664:      decode to XSCMPGTDP using decoder 203
                                             // 12664:     }
  1, 13,                                     // 12669:     case 0x1: {
  OPC_CheckField, 21, 2, 0,                  // 12671:      check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 12675:      check Inst[0] == 0x0
  OPC_Decode, 200, 20, 208, 1,               // 12679:      decode to XSCMPODP using decoder 208
                                             // 12679:     }
  2, 5,                                      // 12684:     case 0x2: {
  OPC_Decode, 223, 21, 180, 1,               // 12686:      decode to XVCMPGTSP using decoder 180
                                             // 12686:     }
  3, 5,                                      // 12691:     case 0x3: {
  OPC_Decode, 221, 21, 180, 1,               // 12693:      decode to XVCMPGTDP using decoder 180
                                             // 12693:     }
  4, 5,                                      // 12698:     case 0x4: {
  OPC_Decode, 201, 21, 180, 1,               // 12700:      decode to XVADDUHM using decoder 180
                                             // 12700:     }
  5, 5,                                      // 12705:     case 0x5: {
  OPC_Decode, 191, 22, 180, 1,               // 12707:      decode to XVMULUHM using decoder 180
                                             // 12707:     }
  6, 5,                                      // 12712:     case 0x6: {
  OPC_Decode, 224, 21, 180, 1,               // 12714:      decode to XVCMPGTSP_rec using decoder 180
                                             // 12714:     }
  7, 0,                                      // 12719:     case 0x7: {
  OPC_Decode, 222, 21, 180, 1,               // 12721:      decode to XVCMPGTDP_rec using decoder 180
                                             // 12721:     }
                                             // 12721:     } // switch Inst[10:8]
                                             // 12721:    }
                                             // 12721:    } // switch Inst[3]
                                             // 12721:   }
  2, 211, 1,                                 // 12726:   case 0x2: {
  OPC_SwitchField, 8, 3,                     // 12729:    switch Inst[10:8] {
  0, 17,                                     // 12732:    case 0x0: {
  OPC_SwitchField, 3, 1,                     // 12734:     switch Inst[3] {
  0, 5,                                      // 12737:     case 0x0: {
  OPC_Decode, 143, 23, 180, 1,               // 12739:      decode to XXMRGHW using decoder 180
                                             // 12739:     }
  1, 0,                                      // 12744:     case 0x1: {
  OPC_Decode, 196, 20, 203, 1,               // 12746:      decode to XSCMPGEDP using decoder 203
                                             // 12746:     }
                                             // 12746:     } // switch Inst[3]
                                             // 12746:    }
  1, 9,                                      // 12751:    case 0x1: {
  OPC_CheckField, 3, 1, 0,                   // 12753:     check Inst[3] == 0x0
  OPC_Decode, 144, 23, 180, 1,               // 12757:     decode to XXMRGLW using decoder 180
                                             // 12757:    }
  2, 33,                                     // 12762:    case 0x2: {
  OPC_SwitchField, 3, 1,                     // 12764:     switch Inst[3] {
  0, 21,                                     // 12767:     case 0x0: {
  OPC_SwitchField, 2, 1,                     // 12769:      switch Inst[2] {
  0, 9,                                      // 12772:      case 0x0: {
  OPC_CheckField, 18, 3, 0,                  // 12774:       check Inst[20:18] == 0x0
  OPC_Decode, 163, 23, 211, 1,               // 12778:       decode to XXSPLTW using decoder 211
                                             // 12778:      }
  1, 0,                                      // 12783:      case 0x1: {
  OPC_Decode, 249, 22, 212, 1,               // 12785:       decode to XXEXTRACTUW using decoder 212
                                             // 12785:      }
                                             // 12785:      } // switch Inst[2]
                                             // 12785:     }
  1, 0,                                      // 12790:     case 0x1: {
  OPC_Decode, 219, 21, 180, 1,               // 12792:      decode to XVCMPGESP using decoder 180
                                             // 12792:     }
                                             // 12792:     } // switch Inst[3]
                                             // 12792:    }
  3, 17,                                     // 12797:    case 0x3: {
  OPC_SwitchField, 3, 1,                     // 12799:     switch Inst[3] {
  0, 5,                                      // 12802:     case 0x0: {
  OPC_Decode, 189, 22, 180, 1,               // 12804:      decode to XVMULHUW using decoder 180
                                             // 12804:     }
  1, 0,                                      // 12809:     case 0x1: {
  OPC_Decode, 217, 21, 180, 1,               // 12811:      decode to XVCMPGEDP using decoder 180
                                             // 12811:     }
                                             // 12811:     } // switch Inst[3]
                                             // 12811:    }
  4, 17,                                     // 12816:    case 0x4: {
  OPC_SwitchField, 3, 1,                     // 12818:     switch Inst[3] {
  0, 5,                                      // 12821:     case 0x0: {
  OPC_Decode, 134, 23, 180, 1,               // 12823:      decode to XXLOR using decoder 180
                                             // 12823:     }
  1, 0,                                      // 12828:     case 0x1: {
  OPC_Decode, 225, 22, 180, 1,               // 12830:      decode to XVSUBUWM using decoder 180
                                             // 12830:     }
                                             // 12830:     } // switch Inst[3]
                                             // 12830:    }
  5, 17,                                     // 12835:    case 0x5: {
  OPC_SwitchField, 3, 1,                     // 12837:     switch Inst[3] {
  0, 5,                                      // 12840:     case 0x0: {
  OPC_Decode, 132, 23, 180, 1,               // 12842:      decode to XXLNAND using decoder 180
                                             // 12842:     }
  1, 0,                                      // 12847:     case 0x1: {
  OPC_Decode, 187, 22, 180, 1,               // 12849:      decode to XVMULHSW using decoder 180
                                             // 12849:     }
                                             // 12849:     } // switch Inst[3]
                                             // 12849:    }
  6, 37,                                     // 12854:    case 0x6: {
  OPC_SwitchField, 3, 1,                     // 12856:     switch Inst[3] {
  0, 25,                                     // 12859:     case 0x0: {
  OPC_SwitchField, 2, 1,                     // 12861:      switch Inst[2] {
  0, 5,                                      // 12864:      case 0x0: {
  OPC_Decode, 239, 22, 213, 1,               // 12866:       decode to XXAESGENLKP using decoder 213
                                             // 12866:      }
  1, 0,                                      // 12871:      case 0x1: {
  OPC_CheckField, 21, 2, 0,                  // 12873:       check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 12877:       check Inst[0] == 0x0
  OPC_Decode, 206, 6, 214, 1,                // 12881:       decode to DMXXSHAPAD using decoder 214
                                             // 12881:      }
                                             // 12881:      } // switch Inst[2]
                                             // 12881:     }
  1, 0,                                      // 12886:     case 0x1: {
  OPC_Decode, 220, 21, 180, 1,               // 12888:      decode to XVCMPGESP_rec using decoder 180
                                             // 12888:     }
                                             // 12888:     } // switch Inst[3]
                                             // 12888:    }
  7, 0,                                      // 12893:    case 0x7: {
  OPC_SwitchField, 3, 1,                     // 12895:     switch Inst[3] {
  0, 33,                                     // 12898:     case 0x0: {
  OPC_SwitchField, 2, 1,                     // 12900:      switch Inst[2] {
  0, 13,                                     // 12903:      case 0x0: {
  OPC_CheckField, 17, 6, 0,                  // 12905:       check Inst[22:17] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 12909:       check Inst[0] == 0x0
  OPC_Decode, 199, 6, 215, 1,                // 12913:       decode to DMXXEXTFDMR256 using decoder 215
                                             // 12913:      }
  1, 0,                                      // 12918:      case 0x1: {
  OPC_CheckField, 17, 6, 0,                  // 12920:       check Inst[22:17] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 12924:       check Inst[0] == 0x0
  OPC_Decode, 202, 6, 216, 1,                // 12928:       decode to DMXXINSTDMR256 using decoder 216
                                             // 12928:      }
                                             // 12928:      } // switch Inst[2]
                                             // 12928:     }
  1, 0,                                      // 12933:     case 0x1: {
  OPC_Decode, 218, 21, 180, 1,               // 12935:      decode to XVCMPGEDP_rec using decoder 180
                                             // 12935:     }
                                             // 12935:     } // switch Inst[3]
                                             // 12935:    }
                                             // 12935:    } // switch Inst[10:8]
                                             // 12935:   }
  3, 0,                                      // 12940:   case 0x3: {
  OPC_SwitchField, 9, 2,                     // 12942:    switch Inst[10:9] {
  0, 41,                                     // 12945:    case 0x0: {
  OPC_SwitchField, 3, 1,                     // 12947:     switch Inst[3] {
  0, 17,                                     // 12950:     case 0x0: {
  OPC_SwitchField, 8, 1,                     // 12952:      switch Inst[8] {
  0, 5,                                      // 12955:      case 0x0: {
  OPC_Decode, 150, 23, 217, 1,               // 12957:       decode to XXPERM using decoder 217
                                             // 12957:      }
  1, 0,                                      // 12962:      case 0x1: {
  OPC_Decode, 153, 23, 217, 1,               // 12964:       decode to XXPERMR using decoder 217
                                             // 12964:      }
                                             // 12964:      } // switch Inst[8]
                                             // 12964:     }
  1, 0,                                      // 12969:     case 0x1: {
  OPC_CheckField, 21, 2, 0,                  // 12971:      check Inst[22:21] == 0x0
  OPC_CheckField, 8, 1, 1,                   // 12975:      check Inst[8] == 0x1
  OPC_CheckField, 0, 1, 0,                   // 12979:      check Inst[0] == 0x0
  OPC_Decode, 194, 20, 208, 1,               // 12983:      decode to XSCMPEXPDP using decoder 208
                                             // 12983:     }
                                             // 12983:     } // switch Inst[3]
                                             // 12983:    }
  1, 57,                                     // 12988:    case 0x1: {
  OPC_SwitchField, 8, 1,                     // 12990:     switch Inst[8] {
  0, 41,                                     // 12993:     case 0x0: {
  OPC_SwitchField, 2, 2,                     // 12995:      switch Inst[3:2] {
  0, 29,                                     // 12998:      case 0x0: {
  OPC_SwitchField, 19, 2,                    // 13000:       switch Inst[20:19] {
  0, 9,                                      // 13003:       case 0x0: {
  OPC_CheckField, 1, 1, 0,                   // 13005:        check Inst[1] == 0x0
  OPC_Decode, 160, 23, 218, 1,               // 13009:        decode to XXSPLTIB using decoder 218
                                             // 13009:       }
  3, 0,                                      // 13014:       case 0x3: {
  OPC_CheckField, 16, 3, 7,                  // 13016:        check Inst[18:16] == 0x7
  OPC_CheckField, 1, 1, 0,                   // 13020:        check Inst[1] == 0x0
  OPC_Decode, 193, 11, 219, 1,               // 13024:        decode to LXVKQ using decoder 219
                                             // 13024:       }
                                             // 13024:       } // switch Inst[20:19]
                                             // 13024:      }
  1, 0,                                      // 13029:      case 0x1: {
  OPC_Decode, 255, 22, 220, 1,               // 13031:       decode to XXINSERTW using decoder 220
                                             // 13031:      }
                                             // 13031:      } // switch Inst[3:2]
                                             // 13031:     }
  1, 0,                                      // 13036:     case 0x1: {
  OPC_CheckField, 3, 1, 0,                   // 13038:      check Inst[3] == 0x0
  OPC_Decode, 188, 22, 180, 1,               // 13042:      decode to XVMULHUH using decoder 180
                                             // 13042:     }
                                             // 13042:     } // switch Inst[8]
                                             // 13042:    }
  2, 41,                                     // 13047:    case 0x2: {
  OPC_SwitchField, 3, 1,                     // 13049:     switch Inst[3] {
  0, 17,                                     // 13052:     case 0x0: {
  OPC_SwitchField, 8, 1,                     // 13054:      switch Inst[8] {
  0, 5,                                      // 13057:      case 0x0: {
  OPC_Decode, 137, 23, 180, 1,               // 13059:       decode to XXLXOR using decoder 180
                                             // 13059:      }
  1, 0,                                      // 13064:      case 0x1: {
  OPC_Decode, 130, 23, 180, 1,               // 13066:       decode to XXLEQV using decoder 180
                                             // 13066:      }
                                             // 13066:      } // switch Inst[8]
                                             // 13066:     }
  1, 0,                                      // 13071:     case 0x1: {
  OPC_SwitchField, 8, 1,                     // 13073:      switch Inst[8] {
  0, 5,                                      // 13076:      case 0x0: {
  OPC_Decode, 224, 22, 180, 1,               // 13078:       decode to XVSUBUHM using decoder 180
                                             // 13078:      }
  1, 0,                                      // 13083:      case 0x1: {
  OPC_Decode, 186, 22, 180, 1,               // 13085:       decode to XVMULHSH using decoder 180
                                             // 13085:      }
                                             // 13085:      } // switch Inst[8]
                                             // 13085:     }
                                             // 13085:     } // switch Inst[3]
                                             // 13085:    }
  3, 0,                                      // 13090:    case 0x3: {
  OPC_CheckField, 3, 1, 0,                   // 13092:     check Inst[3] == 0x0
  OPC_Decode, 254, 22, 221, 1,               // 13096:     decode to XXGFMUL128 using decoder 221
                                             // 13096:    }
                                             // 13096:    } // switch Inst[10:9]
                                             // 13096:   }
                                             // 13096:   } // switch Inst[7:6]
                                             // 13096:  }
  2, 234, 10,                                // 13101:  case 0x2: {
  OPC_SwitchField, 7, 4,                     // 13104:   switch Inst[10:7] {
  0, 45,                                     // 13107:   case 0x0: {
  OPC_SwitchField, 2, 2,                     // 13109:    switch Inst[3:2] {
  2, 25,                                     // 13112:    case 0x2: {
  OPC_SwitchField, 6, 1,                     // 13114:     switch Inst[6] {
  0, 9,                                      // 13117:     case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 13119:      check Inst[20:16] == 0x0
  OPC_Decode, 179, 21, 222, 1,               // 13123:      decode to XSRSQRTESP using decoder 222
                                             // 13123:     }
  1, 0,                                      // 13128:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 13130:      check Inst[20:16] == 0x0
  OPC_Decode, 173, 21, 222, 1,               // 13134:      decode to XSRESP using decoder 222
                                             // 13134:     }
                                             // 13134:     } // switch Inst[6]
                                             // 13134:    }
  3, 0,                                      // 13139:    case 0x3: {
  OPC_CheckField, 16, 5, 0,                  // 13141:     check Inst[20:16] == 0x0
  OPC_CheckField, 6, 1, 0,                   // 13145:     check Inst[6] == 0x0
  OPC_Decode, 183, 21, 222, 1,               // 13149:     decode to XSSQRTSP using decoder 222
                                             // 13149:    }
                                             // 13149:    } // switch Inst[3:2]
                                             // 13149:   }
  2, 99,                                     // 13154:   case 0x2: {
  OPC_SwitchField, 2, 2,                     // 13156:    switch Inst[3:2] {
  0, 25,                                     // 13159:    case 0x0: {
  OPC_SwitchField, 6, 1,                     // 13161:     switch Inst[6] {
  0, 9,                                      // 13164:     case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 13166:      check Inst[20:16] == 0x0
  OPC_Decode, 216, 20, 223, 1,               // 13170:      decode to XSCVDPUXWS using decoder 223
                                             // 13170:     }
  1, 0,                                      // 13175:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 13177:      check Inst[20:16] == 0x0
  OPC_Decode, 212, 20, 223, 1,               // 13181:      decode to XSCVDPSXWS using decoder 223
                                             // 13181:     }
                                             // 13181:     } // switch Inst[6]
                                             // 13181:    }
  1, 25,                                     // 13186:    case 0x1: {
  OPC_SwitchField, 6, 1,                     // 13188:     switch Inst[6] {
  0, 9,                                      // 13191:     case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 13193:      check Inst[20:16] == 0x0
  OPC_Decode, 160, 21, 223, 1,               // 13197:      decode to XSRDPI using decoder 223
                                             // 13197:     }
  1, 0,                                      // 13202:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 13204:      check Inst[20:16] == 0x0
  OPC_Decode, 164, 21, 223, 1,               // 13208:      decode to XSRDPIZ using decoder 223
                                             // 13208:     }
                                             // 13208:     } // switch Inst[6]
                                             // 13208:    }
  2, 25,                                     // 13213:    case 0x2: {
  OPC_SwitchField, 6, 1,                     // 13215:     switch Inst[6] {
  0, 9,                                      // 13218:     case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 13220:      check Inst[20:16] == 0x0
  OPC_Decode, 178, 21, 223, 1,               // 13224:      decode to XSRSQRTEDP using decoder 223
                                             // 13224:     }
  1, 0,                                      // 13229:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 13231:      check Inst[20:16] == 0x0
  OPC_Decode, 172, 21, 223, 1,               // 13235:      decode to XSREDP using decoder 223
                                             // 13235:     }
                                             // 13235:     } // switch Inst[6]
                                             // 13235:    }
  3, 0,                                      // 13240:    case 0x3: {
  OPC_CheckField, 16, 5, 0,                  // 13242:     check Inst[20:16] == 0x0
  OPC_CheckField, 6, 1, 0,                   // 13246:     check Inst[6] == 0x0
  OPC_Decode, 180, 21, 223, 1,               // 13250:     decode to XSSQRTDP using decoder 223
                                             // 13250:    }
                                             // 13250:    } // switch Inst[3:2]
                                             // 13250:   }
  3, 89,                                     // 13255:   case 0x3: {
  OPC_SwitchField, 3, 1,                     // 13257:    switch Inst[3] {
  0, 33,                                     // 13260:    case 0x0: {
  OPC_SwitchField, 6, 1,                     // 13262:     switch Inst[6] {
  0, 13,                                     // 13265:     case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 13267:      check Inst[20:16] == 0x0
  OPC_CheckField, 2, 1, 1,                   // 13271:      check Inst[2] == 0x1
  OPC_Decode, 163, 21, 223, 1,               // 13275:      decode to XSRDPIP using decoder 223
                                             // 13275:     }
  1, 0,                                      // 13280:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 13282:      check Inst[20:16] == 0x0
  OPC_CheckField, 2, 1, 1,                   // 13286:      check Inst[2] == 0x1
  OPC_Decode, 162, 21, 223, 1,               // 13290:      decode to XSRDPIM using decoder 223
                                             // 13290:     }
                                             // 13290:     } // switch Inst[6]
                                             // 13290:    }
  1, 0,                                      // 13295:    case 0x1: {
  OPC_SwitchField, 6, 1,                     // 13297:     switch Inst[6] {
  0, 29,                                     // 13300:     case 0x0: {
  OPC_SwitchField, 2, 1,                     // 13302:      switch Inst[2] {
  0, 13,                                     // 13305:      case 0x0: {
  OPC_CheckField, 16, 7, 0,                  // 13307:       check Inst[22:16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 13311:       check Inst[0] == 0x0
  OPC_Decode, 189, 21, 224, 1,               // 13315:       decode to XSTSQRTDP using decoder 224
                                             // 13315:      }
  1, 0,                                      // 13320:      case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 13322:       check Inst[20:16] == 0x0
  OPC_Decode, 161, 21, 223, 1,               // 13326:       decode to XSRDPIC using decoder 223
                                             // 13326:      }
                                             // 13326:      } // switch Inst[2]
                                             // 13326:     }
  1, 0,                                      // 13331:     case 0x1: {
  OPC_CheckField, 21, 2, 0,                  // 13333:      check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 13337:      check Inst[0] == 0x0
  OPC_Decode, 188, 21, 208, 1,               // 13341:      decode to XSTDIVDP using decoder 208
                                             // 13341:     }
                                             // 13341:     } // switch Inst[6]
                                             // 13341:    }
                                             // 13341:    } // switch Inst[3]
                                             // 13341:   }
  4, 99,                                     // 13346:   case 0x4: {
  OPC_SwitchField, 2, 2,                     // 13348:    switch Inst[3:2] {
  0, 25,                                     // 13351:    case 0x0: {
  OPC_SwitchField, 6, 1,                     // 13353:     switch Inst[6] {
  0, 9,                                      // 13356:     case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 13358:      check Inst[20:16] == 0x0
  OPC_Decode, 240, 21, 225, 1,               // 13362:      decode to XVCVSPUXWS using decoder 225
                                             // 13362:     }
  1, 0,                                      // 13367:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 13369:      check Inst[20:16] == 0x0
  OPC_Decode, 238, 21, 225, 1,               // 13373:      decode to XVCVSPSXWS using decoder 225
                                             // 13373:     }
                                             // 13373:     } // switch Inst[6]
                                             // 13373:    }
  1, 25,                                     // 13378:    case 0x1: {
  OPC_SwitchField, 6, 1,                     // 13380:     switch Inst[6] {
  0, 9,                                      // 13383:     case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 13385:      check Inst[20:16] == 0x0
  OPC_Decode, 213, 22, 225, 1,               // 13389:      decode to XVRSPI using decoder 225
                                             // 13389:     }
  1, 0,                                      // 13394:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 13396:      check Inst[20:16] == 0x0
  OPC_Decode, 217, 22, 225, 1,               // 13400:      decode to XVRSPIZ using decoder 225
                                             // 13400:     }
                                             // 13400:     } // switch Inst[6]
                                             // 13400:    }
  2, 25,                                     // 13405:    case 0x2: {
  OPC_SwitchField, 6, 1,                     // 13407:     switch Inst[6] {
  0, 9,                                      // 13410:     case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 13412:      check Inst[20:16] == 0x0
  OPC_Decode, 219, 22, 225, 1,               // 13416:      decode to XVRSQRTESP using decoder 225
                                             // 13416:     }
  1, 0,                                      // 13421:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 13423:      check Inst[20:16] == 0x0
  OPC_Decode, 211, 22, 225, 1,               // 13427:      decode to XVRESP using decoder 225
                                             // 13427:     }
                                             // 13427:     } // switch Inst[6]
                                             // 13427:    }
  3, 0,                                      // 13432:    case 0x3: {
  OPC_CheckField, 16, 5, 0,                  // 13434:     check Inst[20:16] == 0x0
  OPC_CheckField, 6, 1, 0,                   // 13438:     check Inst[6] == 0x0
  OPC_Decode, 221, 22, 225, 1,               // 13442:     decode to XVSQRTSP using decoder 225
                                             // 13442:    }
                                             // 13442:    } // switch Inst[3:2]
                                             // 13442:   }
  5, 113,                                    // 13447:   case 0x5: {
  OPC_SwitchField, 3, 1,                     // 13449:    switch Inst[3] {
  0, 57,                                     // 13452:    case 0x0: {
  OPC_SwitchField, 2, 1,                     // 13454:     switch Inst[2] {
  0, 25,                                     // 13457:     case 0x0: {
  OPC_SwitchField, 6, 1,                     // 13459:      switch Inst[6] {
  0, 9,                                      // 13462:      case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 13464:       check Inst[20:16] == 0x0
  OPC_Decode, 248, 21, 225, 1,               // 13468:       decode to XVCVUXWSP using decoder 225
                                             // 13468:      }
  1, 0,                                      // 13473:      case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 13475:       check Inst[20:16] == 0x0
  OPC_Decode, 244, 21, 225, 1,               // 13479:       decode to XVCVSXWSP using decoder 225
                                             // 13479:      }
                                             // 13479:      } // switch Inst[6]
                                             // 13479:     }
  1, 0,                                      // 13484:     case 0x1: {
  OPC_SwitchField, 6, 1,                     // 13486:      switch Inst[6] {
  0, 9,                                      // 13489:      case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 13491:       check Inst[20:16] == 0x0
  OPC_Decode, 216, 22, 225, 1,               // 13495:       decode to XVRSPIP using decoder 225
                                             // 13495:      }
  1, 0,                                      // 13500:      case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 13502:       check Inst[20:16] == 0x0
  OPC_Decode, 215, 22, 225, 1,               // 13506:       decode to XVRSPIM using decoder 225
                                             // 13506:      }
                                             // 13506:      } // switch Inst[6]
                                             // 13506:     }
                                             // 13506:     } // switch Inst[2]
                                             // 13506:    }
  1, 0,                                      // 13511:    case 0x1: {
  OPC_SwitchField, 6, 1,                     // 13513:     switch Inst[6] {
  0, 29,                                     // 13516:     case 0x0: {
  OPC_SwitchField, 2, 1,                     // 13518:      switch Inst[2] {
  0, 13,                                     // 13521:      case 0x0: {
  OPC_CheckField, 16, 7, 0,                  // 13523:       check Inst[22:16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 13527:       check Inst[0] == 0x0
  OPC_Decode, 230, 22, 226, 1,               // 13531:       decode to XVTSQRTSP using decoder 226
                                             // 13531:      }
  1, 0,                                      // 13536:      case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 13538:       check Inst[20:16] == 0x0
  OPC_Decode, 214, 22, 225, 1,               // 13542:       decode to XVRSPIC using decoder 225
                                             // 13542:      }
                                             // 13542:      } // switch Inst[2]
                                             // 13542:     }
  1, 0,                                      // 13547:     case 0x1: {
  OPC_CheckField, 21, 2, 0,                  // 13549:      check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 13553:      check Inst[0] == 0x0
  OPC_Decode, 227, 22, 227, 1,               // 13557:      decode to XVTDIVSP using decoder 227
                                             // 13557:     }
                                             // 13557:     } // switch Inst[6]
                                             // 13557:    }
                                             // 13557:    } // switch Inst[3]
                                             // 13557:   }
  6, 99,                                     // 13562:   case 0x6: {
  OPC_SwitchField, 2, 2,                     // 13564:    switch Inst[3:2] {
  0, 25,                                     // 13567:    case 0x0: {
  OPC_SwitchField, 6, 1,                     // 13569:     switch Inst[6] {
  0, 9,                                      // 13572:     case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 13574:      check Inst[20:16] == 0x0
  OPC_Decode, 232, 21, 225, 1,               // 13578:      decode to XVCVDPUXWS using decoder 225
                                             // 13578:     }
  1, 0,                                      // 13583:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 13585:      check Inst[20:16] == 0x0
  OPC_Decode, 230, 21, 225, 1,               // 13589:      decode to XVCVDPSXWS using decoder 225
                                             // 13589:     }
                                             // 13589:     } // switch Inst[6]
                                             // 13589:    }
  1, 25,                                     // 13594:    case 0x1: {
  OPC_SwitchField, 6, 1,                     // 13596:     switch Inst[6] {
  0, 9,                                      // 13599:     case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 13601:      check Inst[20:16] == 0x0
  OPC_Decode, 205, 22, 225, 1,               // 13605:      decode to XVRDPI using decoder 225
                                             // 13605:     }
  1, 0,                                      // 13610:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 13612:      check Inst[20:16] == 0x0
  OPC_Decode, 209, 22, 225, 1,               // 13616:      decode to XVRDPIZ using decoder 225
                                             // 13616:     }
                                             // 13616:     } // switch Inst[6]
                                             // 13616:    }
  2, 25,                                     // 13621:    case 0x2: {
  OPC_SwitchField, 6, 1,                     // 13623:     switch Inst[6] {
  0, 9,                                      // 13626:     case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 13628:      check Inst[20:16] == 0x0
  OPC_Decode, 218, 22, 225, 1,               // 13632:      decode to XVRSQRTEDP using decoder 225
                                             // 13632:     }
  1, 0,                                      // 13637:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 13639:      check Inst[20:16] == 0x0
  OPC_Decode, 210, 22, 225, 1,               // 13643:      decode to XVREDP using decoder 225
                                             // 13643:     }
                                             // 13643:     } // switch Inst[6]
                                             // 13643:    }
  3, 0,                                      // 13648:    case 0x3: {
  OPC_CheckField, 16, 5, 0,                  // 13650:     check Inst[20:16] == 0x0
  OPC_CheckField, 6, 1, 0,                   // 13654:     check Inst[6] == 0x0
  OPC_Decode, 220, 22, 225, 1,               // 13658:     decode to XVSQRTDP using decoder 225
                                             // 13658:    }
                                             // 13658:    } // switch Inst[3:2]
                                             // 13658:   }
  7, 113,                                    // 13663:   case 0x7: {
  OPC_SwitchField, 3, 1,                     // 13665:    switch Inst[3] {
  0, 57,                                     // 13668:    case 0x0: {
  OPC_SwitchField, 2, 1,                     // 13670:     switch Inst[2] {
  0, 25,                                     // 13673:     case 0x0: {
  OPC_SwitchField, 6, 1,                     // 13675:      switch Inst[6] {
  0, 9,                                      // 13678:      case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 13680:       check Inst[20:16] == 0x0
  OPC_Decode, 247, 21, 225, 1,               // 13684:       decode to XVCVUXWDP using decoder 225
                                             // 13684:      }
  1, 0,                                      // 13689:      case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 13691:       check Inst[20:16] == 0x0
  OPC_Decode, 243, 21, 225, 1,               // 13695:       decode to XVCVSXWDP using decoder 225
                                             // 13695:      }
                                             // 13695:      } // switch Inst[6]
                                             // 13695:     }
  1, 0,                                      // 13700:     case 0x1: {
  OPC_SwitchField, 6, 1,                     // 13702:      switch Inst[6] {
  0, 9,                                      // 13705:      case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 13707:       check Inst[20:16] == 0x0
  OPC_Decode, 208, 22, 225, 1,               // 13711:       decode to XVRDPIP using decoder 225
                                             // 13711:      }
  1, 0,                                      // 13716:      case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 13718:       check Inst[20:16] == 0x0
  OPC_Decode, 207, 22, 225, 1,               // 13722:       decode to XVRDPIM using decoder 225
                                             // 13722:      }
                                             // 13722:      } // switch Inst[6]
                                             // 13722:     }
                                             // 13722:     } // switch Inst[2]
                                             // 13722:    }
  1, 0,                                      // 13727:    case 0x1: {
  OPC_SwitchField, 6, 1,                     // 13729:     switch Inst[6] {
  0, 29,                                     // 13732:     case 0x0: {
  OPC_SwitchField, 2, 1,                     // 13734:      switch Inst[2] {
  0, 13,                                     // 13737:      case 0x0: {
  OPC_CheckField, 16, 7, 0,                  // 13739:       check Inst[22:16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 13743:       check Inst[0] == 0x0
  OPC_Decode, 229, 22, 226, 1,               // 13747:       decode to XVTSQRTDP using decoder 226
                                             // 13747:      }
  1, 0,                                      // 13752:      case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 13754:       check Inst[20:16] == 0x0
  OPC_Decode, 206, 22, 225, 1,               // 13758:       decode to XVRDPIC using decoder 225
                                             // 13758:      }
                                             // 13758:      } // switch Inst[2]
                                             // 13758:     }
  1, 0,                                      // 13763:     case 0x1: {
  OPC_CheckField, 21, 2, 0,                  // 13765:      check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 13769:      check Inst[0] == 0x0
  OPC_Decode, 226, 22, 227, 1,               // 13773:      decode to XVTDIVDP using decoder 227
                                             // 13773:     }
                                             // 13773:     } // switch Inst[6]
                                             // 13773:    }
                                             // 13773:    } // switch Inst[3]
                                             // 13773:   }
  8, 45,                                     // 13778:   case 0x8: {
  OPC_SwitchField, 2, 2,                     // 13780:    switch Inst[3:2] {
  1, 25,                                     // 13783:    case 0x1: {
  OPC_SwitchField, 6, 1,                     // 13785:     switch Inst[6] {
  0, 9,                                      // 13788:     case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 13790:      check Inst[20:16] == 0x0
  OPC_Decode, 208, 20, 223, 1,               // 13794:      decode to XSCVDPSP using decoder 223
                                             // 13794:     }
  1, 0,                                      // 13799:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 13801:      check Inst[20:16] == 0x0
  OPC_Decode, 177, 21, 228, 1,               // 13805:      decode to XSRSP using decoder 228
                                             // 13805:     }
                                             // 13805:     } // switch Inst[6]
                                             // 13805:    }
  3, 0,                                      // 13810:    case 0x3: {
  OPC_CheckField, 16, 5, 0,                  // 13812:     check Inst[20:16] == 0x0
  OPC_CheckField, 6, 1, 0,                   // 13816:     check Inst[6] == 0x0
  OPC_Decode, 209, 20, 229, 1,               // 13820:     decode to XSCVDPSPN using decoder 229
                                             // 13820:    }
                                             // 13820:    } // switch Inst[3:2]
                                             // 13820:   }
  9, 45,                                     // 13825:   case 0x9: {
  OPC_SwitchField, 2, 2,                     // 13827:    switch Inst[3:2] {
  0, 25,                                     // 13830:    case 0x0: {
  OPC_SwitchField, 6, 1,                     // 13832:     switch Inst[6] {
  0, 9,                                      // 13835:     case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 13837:      check Inst[20:16] == 0x0
  OPC_Decode, 236, 20, 228, 1,               // 13841:      decode to XSCVUXDSP using decoder 228
                                             // 13841:     }
  1, 0,                                      // 13846:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 13848:      check Inst[20:16] == 0x0
  OPC_Decode, 232, 20, 228, 1,               // 13852:      decode to XSCVSXDSP using decoder 228
                                             // 13852:     }
                                             // 13852:     } // switch Inst[6]
                                             // 13852:    }
  2, 0,                                      // 13857:    case 0x2: {
  OPC_CheckField, 6, 1, 0,                   // 13859:     check Inst[6] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 13863:     check Inst[0] == 0x0
  OPC_Decode, 192, 21, 230, 1,               // 13867:     decode to XSTSTDCSP using decoder 230
                                             // 13867:    }
                                             // 13867:    } // switch Inst[3:2]
                                             // 13867:   }
  10, 118,                                   // 13872:   case 0xa: {
  OPC_SwitchField, 16, 5,                    // 13874:    switch Inst[20:16] {
  0, 64,                                     // 13877:    case 0x0: {
  OPC_SwitchField, 2, 2,                     // 13879:     switch Inst[3:2] {
  0, 17,                                     // 13882:     case 0x0: {
  OPC_SwitchField, 6, 1,                     // 13884:      switch Inst[6] {
  0, 5,                                      // 13887:      case 0x0: {
  OPC_Decode, 214, 20, 223, 1,               // 13889:       decode to XSCVDPUXDS using decoder 223
                                             // 13889:      }
  1, 0,                                      // 13894:      case 0x1: {
  OPC_Decode, 210, 20, 223, 1,               // 13896:       decode to XSCVDPSXDS using decoder 223
                                             // 13896:      }
                                             // 13896:      } // switch Inst[6]
                                             // 13896:     }
  1, 17,                                     // 13901:     case 0x1: {
  OPC_SwitchField, 6, 1,                     // 13903:      switch Inst[6] {
  0, 5,                                      // 13906:      case 0x0: {
  OPC_Decode, 228, 20, 223, 1,               // 13908:       decode to XSCVSPDP using decoder 223
                                             // 13908:      }
  1, 0,                                      // 13913:      case 0x1: {
  OPC_Decode, 182, 20, 223, 1,               // 13915:       decode to XSABSDP using decoder 223
                                             // 13915:      }
                                             // 13915:      } // switch Inst[6]
                                             // 13915:     }
  3, 0,                                      // 13920:     case 0x3: {
  OPC_SwitchField, 6, 1,                     // 13922:      switch Inst[6] {
  0, 5,                                      // 13925:      case 0x0: {
  OPC_Decode, 229, 20, 231, 1,               // 13927:       decode to XSCVSPDPN using decoder 231
                                             // 13927:      }
  1, 0,                                      // 13932:      case 0x1: {
  OPC_CheckField, 0, 1, 0,                   // 13934:       check Inst[0] == 0x0
  OPC_Decode, 193, 21, 232, 1,               // 13938:       decode to XSXEXPDP using decoder 232
                                             // 13938:      }
                                             // 13938:      } // switch Inst[6]
                                             // 13938:     }
                                             // 13938:     } // switch Inst[3:2]
                                             // 13938:    }
  1, 17,                                     // 13943:    case 0x1: {
  OPC_CheckField, 6, 1, 1,                   // 13945:     check Inst[6] == 0x1
  OPC_CheckField, 2, 2, 3,                   // 13949:     check Inst[3:2] == 0x3
  OPC_CheckField, 0, 1, 0,                   // 13953:     check Inst[0] == 0x0
  OPC_Decode, 195, 21, 232, 1,               // 13957:     decode to XSXSIGDP using decoder 232
                                             // 13957:    }
  16, 13,                                    // 13962:    case 0x10: {
  OPC_CheckField, 6, 1, 1,                   // 13964:     check Inst[6] == 0x1
  OPC_CheckField, 2, 2, 3,                   // 13968:     check Inst[3:2] == 0x3
  OPC_Decode, 218, 20, 223, 1,               // 13972:     decode to XSCVHPDP using decoder 223
                                             // 13972:    }
  17, 0,                                     // 13977:    case 0x11: {
  OPC_CheckField, 6, 1, 1,                   // 13979:     check Inst[6] == 0x1
  OPC_CheckField, 2, 2, 3,                   // 13983:     check Inst[3:2] == 0x3
  OPC_Decode, 206, 20, 223, 1,               // 13987:     decode to XSCVDPHP using decoder 223
                                             // 13987:    }
                                             // 13987:    } // switch Inst[20:16]
                                             // 13987:   }
  11, 72,                                    // 13992:   case 0xb: {
  OPC_SwitchField, 2, 2,                     // 13994:    switch Inst[3:2] {
  0, 25,                                     // 13997:    case 0x0: {
  OPC_SwitchField, 6, 1,                     // 13999:     switch Inst[6] {
  0, 9,                                      // 14002:     case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 14004:      check Inst[20:16] == 0x0
  OPC_Decode, 235, 20, 223, 1,               // 14008:      decode to XSCVUXDDP using decoder 223
                                             // 14008:     }
  1, 0,                                      // 14013:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 14015:      check Inst[20:16] == 0x0
  OPC_Decode, 231, 20, 223, 1,               // 14019:      decode to XSCVSXDDP using decoder 223
                                             // 14019:     }
                                             // 14019:     } // switch Inst[6]
                                             // 14019:    }
  1, 25,                                     // 14024:    case 0x1: {
  OPC_SwitchField, 6, 1,                     // 14026:     switch Inst[6] {
  0, 9,                                      // 14029:     case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 14031:      check Inst[20:16] == 0x0
  OPC_Decode, 143, 21, 223, 1,               // 14035:      decode to XSNABSDP using decoder 223
                                             // 14035:     }
  1, 0,                                      // 14040:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 14042:      check Inst[20:16] == 0x0
  OPC_Decode, 146, 21, 223, 1,               // 14046:      decode to XSNEGDP using decoder 223
                                             // 14046:     }
                                             // 14046:     } // switch Inst[6]
                                             // 14046:    }
  2, 0,                                      // 14051:    case 0x2: {
  OPC_CheckField, 6, 1, 0,                   // 14053:     check Inst[6] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 14057:     check Inst[0] == 0x0
  OPC_Decode, 190, 21, 233, 1,               // 14061:     decode to XSTSTDCDP using decoder 233
                                             // 14061:    }
                                             // 14061:    } // switch Inst[3:2]
                                             // 14061:   }
  12, 57,                                    // 14066:   case 0xc: {
  OPC_SwitchField, 2, 2,                     // 14068:    switch Inst[3:2] {
  0, 25,                                     // 14071:    case 0x0: {
  OPC_SwitchField, 6, 1,                     // 14073:     switch Inst[6] {
  0, 9,                                      // 14076:     case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 14078:      check Inst[20:16] == 0x0
  OPC_Decode, 239, 21, 225, 1,               // 14082:      decode to XVCVSPUXDS using decoder 225
                                             // 14082:     }
  1, 0,                                      // 14087:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 14089:      check Inst[20:16] == 0x0
  OPC_Decode, 237, 21, 225, 1,               // 14093:      decode to XVCVSPSXDS using decoder 225
                                             // 14093:     }
                                             // 14093:     } // switch Inst[6]
                                             // 14093:    }
  1, 0,                                      // 14098:    case 0x1: {
  OPC_SwitchField, 6, 1,                     // 14100:     switch Inst[6] {
  0, 9,                                      // 14103:     case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 14105:      check Inst[20:16] == 0x0
  OPC_Decode, 228, 21, 225, 1,               // 14109:      decode to XVCVDPSP using decoder 225
                                             // 14109:     }
  1, 0,                                      // 14114:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 14116:      check Inst[20:16] == 0x0
  OPC_Decode, 198, 21, 225, 1,               // 14120:      decode to XVABSSP using decoder 225
                                             // 14120:     }
                                             // 14120:     } // switch Inst[6]
                                             // 14120:    }
                                             // 14120:    } // switch Inst[3:2]
                                             // 14120:   }
  13, 69,                                    // 14125:   case 0xd: {
  OPC_SwitchField, 3, 1,                     // 14127:    switch Inst[3] {
  0, 57,                                     // 14130:    case 0x0: {
  OPC_SwitchField, 2, 1,                     // 14132:     switch Inst[2] {
  0, 25,                                     // 14135:     case 0x0: {
  OPC_SwitchField, 6, 1,                     // 14137:      switch Inst[6] {
  0, 9,                                      // 14140:      case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 14142:       check Inst[20:16] == 0x0
  OPC_Decode, 246, 21, 225, 1,               // 14146:       decode to XVCVUXDSP using decoder 225
                                             // 14146:      }
  1, 0,                                      // 14151:      case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 14153:       check Inst[20:16] == 0x0
  OPC_Decode, 242, 21, 225, 1,               // 14157:       decode to XVCVSXDSP using decoder 225
                                             // 14157:      }
                                             // 14157:      } // switch Inst[6]
                                             // 14157:     }
  1, 0,                                      // 14162:     case 0x1: {
  OPC_SwitchField, 6, 1,                     // 14164:      switch Inst[6] {
  0, 9,                                      // 14167:      case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 14169:       check Inst[20:16] == 0x0
  OPC_Decode, 194, 22, 225, 1,               // 14173:       decode to XVNABSSP using decoder 225
                                             // 14173:      }
  1, 0,                                      // 14178:      case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 14180:       check Inst[20:16] == 0x0
  OPC_Decode, 196, 22, 225, 1,               // 14184:       decode to XVNEGSP using decoder 225
                                             // 14184:      }
                                             // 14184:      } // switch Inst[6]
                                             // 14184:     }
                                             // 14184:     } // switch Inst[2]
                                             // 14184:    }
  1, 0,                                      // 14189:    case 0x1: {
  OPC_Decode, 232, 22, 234, 1,               // 14191:     decode to XVTSTDCSP using decoder 234
                                             // 14191:    }
                                             // 14191:    } // switch Inst[3]
                                             // 14191:   }
  14, 220, 1,                                // 14196:   case 0xe: {
  OPC_SwitchField, 2, 2,                     // 14199:    switch Inst[3:2] {
  0, 25,                                     // 14202:    case 0x0: {
  OPC_SwitchField, 6, 1,                     // 14204:     switch Inst[6] {
  0, 9,                                      // 14207:     case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 14209:      check Inst[20:16] == 0x0
  OPC_Decode, 231, 21, 225, 1,               // 14213:      decode to XVCVDPUXDS using decoder 225
                                             // 14213:     }
  1, 0,                                      // 14218:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 14220:      check Inst[20:16] == 0x0
  OPC_Decode, 229, 21, 225, 1,               // 14224:      decode to XVCVDPSXDS using decoder 225
                                             // 14224:     }
                                             // 14224:     } // switch Inst[6]
                                             // 14224:    }
  1, 25,                                     // 14229:    case 0x1: {
  OPC_SwitchField, 6, 1,                     // 14231:     switch Inst[6] {
  0, 9,                                      // 14234:     case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 14236:      check Inst[20:16] == 0x0
  OPC_Decode, 235, 21, 225, 1,               // 14240:      decode to XVCVSPDP using decoder 225
                                             // 14240:     }
  1, 0,                                      // 14245:     case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 14247:      check Inst[20:16] == 0x0
  OPC_Decode, 197, 21, 225, 1,               // 14251:      decode to XVABSDP using decoder 225
                                             // 14251:     }
                                             // 14251:     } // switch Inst[6]
                                             // 14251:    }
  2, 41,                                     // 14256:    case 0x2: {
  OPC_SwitchField, 1, 1,                     // 14258:     switch Inst[1] {
  0, 17,                                     // 14261:     case 0x0: {
  OPC_SwitchField, 6, 1,                     // 14263:      switch Inst[6] {
  0, 5,                                      // 14266:      case 0x0: {
  OPC_Decode, 250, 22, 235, 1,               // 14268:       decode to XXGENPCVBM using decoder 235
                                             // 14268:      }
  1, 0,                                      // 14273:      case 0x1: {
  OPC_Decode, 253, 22, 235, 1,               // 14275:       decode to XXGENPCVWM using decoder 235
                                             // 14275:      }
                                             // 14275:      } // switch Inst[6]
                                             // 14275:     }
  1, 0,                                      // 14280:     case 0x1: {
  OPC_SwitchField, 6, 1,                     // 14282:      switch Inst[6] {
  0, 5,                                      // 14285:      case 0x0: {
  OPC_Decode, 252, 22, 235, 1,               // 14287:       decode to XXGENPCVHM using decoder 235
                                             // 14287:      }
  1, 0,                                      // 14292:      case 0x1: {
  OPC_Decode, 251, 22, 235, 1,               // 14294:       decode to XXGENPCVDM using decoder 235
                                             // 14294:      }
                                             // 14294:      } // switch Inst[6]
                                             // 14294:     }
                                             // 14294:     } // switch Inst[1]
                                             // 14294:    }
  3, 0,                                      // 14299:    case 0x3: {
  OPC_SwitchField, 6, 1,                     // 14301:     switch Inst[6] {
  0, 9,                                      // 14304:     case 0x0: {
  OPC_CheckField, 1, 1, 0,                   // 14306:      check Inst[1] == 0x0
  OPC_Decode, 241, 20, 236, 1,               // 14310:      decode to XSIEXPDP using decoder 236
                                             // 14310:     }
  1, 0,                                      // 14315:     case 0x1: {
  OPC_SwitchField, 16, 5,                    // 14317:      switch Inst[20:16] {
  0, 5,                                      // 14320:      case 0x0: {
  OPC_Decode, 233, 22, 225, 1,               // 14322:       decode to XVXEXPDP using decoder 225
                                             // 14322:      }
  1, 5,                                      // 14327:      case 0x1: {
  OPC_Decode, 235, 22, 225, 1,               // 14329:       decode to XVXSIGDP using decoder 225
                                             // 14329:      }
  2, 13,                                     // 14334:      case 0x2: {
  OPC_CheckField, 21, 2, 0,                  // 14336:       check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 14340:       check Inst[0] == 0x0
  OPC_Decode, 228, 22, 226, 1,               // 14344:       decode to XVTLSBB using decoder 226
                                             // 14344:      }
  7, 5,                                      // 14349:      case 0x7: {
  OPC_Decode, 245, 22, 225, 1,               // 14351:       decode to XXBRH using decoder 225
                                             // 14351:      }
  8, 5,                                      // 14356:      case 0x8: {
  OPC_Decode, 234, 22, 225, 1,               // 14358:       decode to XVXEXPSP using decoder 225
                                             // 14358:      }
  9, 5,                                      // 14363:      case 0x9: {
  OPC_Decode, 236, 22, 225, 1,               // 14365:       decode to XVXSIGSP using decoder 225
                                             // 14365:      }
  15, 5,                                     // 14370:      case 0xf: {
  OPC_Decode, 247, 22, 225, 1,               // 14372:       decode to XXBRW using decoder 225
                                             // 14372:      }
  16, 5,                                     // 14377:      case 0x10: {
  OPC_Decode, 227, 21, 225, 1,               // 14379:       decode to XVCVBF16SPN using decoder 225
                                             // 14379:      }
  17, 5,                                     // 14384:      case 0x11: {
  OPC_Decode, 234, 21, 225, 1,               // 14386:       decode to XVCVSPBF16 using decoder 225
                                             // 14386:      }
  23, 5,                                     // 14391:      case 0x17: {
  OPC_Decode, 244, 22, 225, 1,               // 14393:       decode to XXBRD using decoder 225
                                             // 14393:      }
  24, 5,                                     // 14398:      case 0x18: {
  OPC_Decode, 233, 21, 225, 1,               // 14400:       decode to XVCVHPSP using decoder 225
                                             // 14400:      }
  25, 5,                                     // 14405:      case 0x19: {
  OPC_Decode, 236, 21, 225, 1,               // 14407:       decode to XVCVSPHP using decoder 225
                                             // 14407:      }
  31, 0,                                     // 14412:      case 0x1f: {
  OPC_Decode, 246, 22, 225, 1,               // 14414:       decode to XXBRQ using decoder 225
                                             // 14414:      }
                                             // 14414:      } // switch Inst[20:16]
                                             // 14414:     }
                                             // 14414:     } // switch Inst[6]
                                             // 14414:    }
                                             // 14414:    } // switch Inst[3:2]
                                             // 14414:   }
  15, 0,                                     // 14419:   case 0xf: {
  OPC_SwitchField, 3, 1,                     // 14421:    switch Inst[3] {
  0, 57,                                     // 14424:    case 0x0: {
  OPC_SwitchField, 2, 1,                     // 14426:     switch Inst[2] {
  0, 25,                                     // 14429:     case 0x0: {
  OPC_SwitchField, 6, 1,                     // 14431:      switch Inst[6] {
  0, 9,                                      // 14434:      case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 14436:       check Inst[20:16] == 0x0
  OPC_Decode, 245, 21, 225, 1,               // 14440:       decode to XVCVUXDDP using decoder 225
                                             // 14440:      }
  1, 0,                                      // 14445:      case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 14447:       check Inst[20:16] == 0x0
  OPC_Decode, 241, 21, 225, 1,               // 14451:       decode to XVCVSXDDP using decoder 225
                                             // 14451:      }
                                             // 14451:      } // switch Inst[6]
                                             // 14451:     }
  1, 0,                                      // 14456:     case 0x1: {
  OPC_SwitchField, 6, 1,                     // 14458:      switch Inst[6] {
  0, 9,                                      // 14461:      case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 14463:       check Inst[20:16] == 0x0
  OPC_Decode, 193, 22, 225, 1,               // 14467:       decode to XVNABSDP using decoder 225
                                             // 14467:      }
  1, 0,                                      // 14472:      case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 14474:       check Inst[20:16] == 0x0
  OPC_Decode, 195, 22, 225, 1,               // 14478:       decode to XVNEGDP using decoder 225
                                             // 14478:      }
                                             // 14478:      } // switch Inst[6]
                                             // 14478:     }
                                             // 14478:     } // switch Inst[2]
                                             // 14478:    }
  1, 0,                                      // 14483:    case 0x1: {
  OPC_Decode, 231, 22, 234, 1,               // 14485:     decode to XVTSTDCDP using decoder 234
                                             // 14485:    }
                                             // 14485:    } // switch Inst[3]
                                             // 14485:   }
                                             // 14485:   } // switch Inst[10:7]
                                             // 14485:  }
  3, 0,                                      // 14490:  case 0x3: {
  OPC_Decode, 155, 23, 237, 1,               // 14492:   decode to XXSEL using decoder 237
                                             // 14492:  }
                                             // 14492:  } // switch Inst[5:4]
                                             // 14492: }
  61, 36,                                    // 14497: case 0x3d: {
  OPC_SwitchField, 0, 2,                     // 14499:  switch Inst[1:0] {
  1, 17,                                     // 14502:  case 0x1: {
  OPC_SwitchField, 2, 1,                     // 14504:   switch Inst[2] {
  0, 5,                                      // 14507:   case 0x0: {
  OPC_Decode, 188, 11, 238, 1,               // 14509:    decode to LXV using decoder 238
                                             // 14509:   }
  1, 0,                                      // 14514:   case 0x1: {
  OPC_Decode, 157, 16, 238, 1,               // 14516:    decode to STXV using decoder 238
                                             // 14516:   }
                                             // 14516:   } // switch Inst[2]
                                             // 14516:  }
  2, 5,                                      // 14521:  case 0x2: {
  OPC_Decode, 148, 16, 168, 1,               // 14523:   decode to STXSD using decoder 168
                                             // 14523:  }
  3, 0,                                      // 14528:  case 0x3: {
  OPC_Decode, 155, 16, 168, 1,               // 14530:   decode to STXSSP using decoder 168
                                             // 14530:  }
                                             // 14530:  } // switch Inst[1:0]
                                             // 14530: }
  62, 24,                                    // 14535: case 0x3e: {
  OPC_SwitchField, 0, 2,                     // 14537:  switch Inst[1:0] {
  0, 5,                                      // 14540:  case 0x0: {
  OPC_Decode, 210, 15, 169, 1,               // 14542:   decode to STD using decoder 169
                                             // 14542:  }
  1, 5,                                      // 14547:  case 0x1: {
  OPC_Decode, 215, 15, 239, 1,               // 14549:   decode to STDU using decoder 239
                                             // 14549:  }
  2, 0,                                      // 14554:  case 0x2: {
  OPC_Decode, 251, 15, 240, 1,               // 14556:   decode to STQ using decoder 240
                                             // 14556:  }
                                             // 14556:  } // switch Inst[1:0]
                                             // 14556: }
  63, 0,                                     // 14561: case 0x3f: {
  OPC_SwitchField, 0, 6,                     // 14563:  switch Inst[5:0] {
  0, 61,                                     // 14566:  case 0x0: {
  OPC_SwitchField, 6, 5,                     // 14568:   switch Inst[10:6] {
  0, 9,                                      // 14571:   case 0x0: {
  OPC_CheckField, 21, 2, 0,                  // 14573:    check Inst[22:21] == 0x0
  OPC_Decode, 185, 9, 241, 1,                // 14577:    decode to FCMPUS using decoder 241
                                             // 14577:   }
  1, 9,                                      // 14582:   case 0x1: {
  OPC_CheckField, 21, 2, 0,                  // 14584:    check Inst[22:21] == 0x0
  OPC_Decode, 183, 9, 241, 1,                // 14588:    decode to FCMPOS using decoder 241
                                             // 14588:   }
  2, 12,                                     // 14593:   case 0x2: {
  OPC_CheckField, 21, 2, 0,                  // 14595:    check Inst[22:21] == 0x0
  OPC_CheckField, 11, 7, 0,                  // 14599:    check Inst[17:11] == 0x0
  OPC_Decode, 216, 11, 51,                   // 14603:    decode to MCRFS using decoder 51
                                             // 14603:   }
  4, 9,                                      // 14607:   case 0x4: {
  OPC_CheckField, 21, 2, 0,                  // 14609:    check Inst[22:21] == 0x0
  OPC_Decode, 151, 10, 179, 1,               // 14613:    decode to FTDIV using decoder 179
                                             // 14613:   }
  5, 0,                                      // 14618:   case 0x5: {
  OPC_CheckField, 16, 7, 0,                  // 14620:    check Inst[22:16] == 0x0
  OPC_Decode, 152, 10, 242, 1,               // 14624:    decode to FTSQRT using decoder 242
                                             // 14624:   }
                                             // 14624:   } // switch Inst[10:6]
                                             // 14624:  }
  4, 134, 2,                                 // 14629:  case 0x4: {
  OPC_SwitchField, 6, 4,                     // 14632:   switch Inst[9:6] {
  0, 17,                                     // 14635:   case 0x0: {
  OPC_SwitchField, 10, 1,                    // 14637:    switch Inst[10] {
  0, 5,                                      // 14640:    case 0x0: {
  OPC_Decode, 220, 5, 243, 1,                // 14642:     decode to DADDQ using decoder 243
                                             // 14642:    }
  1, 0,                                      // 14647:    case 0x1: {
  OPC_Decode, 250, 6, 243, 1,                // 14649:     decode to DSUBQ using decoder 243
                                             // 14649:    }
                                             // 14649:    } // switch Inst[10]
                                             // 14649:   }
  1, 17,                                     // 14654:   case 0x1: {
  OPC_SwitchField, 10, 1,                    // 14656:    switch Inst[10] {
  0, 5,                                      // 14659:    case 0x0: {
  OPC_Decode, 182, 6, 243, 1,                // 14661:     decode to DMULQ using decoder 243
                                             // 14661:    }
  1, 0,                                      // 14666:    case 0x1: {
  OPC_Decode, 134, 6, 243, 1,                // 14668:     decode to DDIVQ using decoder 243
                                             // 14668:    }
                                             // 14668:    } // switch Inst[10]
                                             // 14668:   }
  2, 5,                                      // 14673:   case 0x2: {
  OPC_Decode, 232, 6, 244, 1,                // 14675:    decode to DSCLIQ using decoder 244
                                             // 14675:   }
  3, 5,                                      // 14680:   case 0x3: {
  OPC_Decode, 236, 6, 244, 1,                // 14682:    decode to DSCRIQ using decoder 244
                                             // 14682:   }
  4, 25,                                     // 14687:   case 0x4: {
  OPC_SwitchField, 10, 1,                    // 14689:    switch Inst[10] {
  0, 9,                                      // 14692:    case 0x0: {
  OPC_CheckField, 21, 2, 0,                  // 14694:     check Inst[22:21] == 0x0
  OPC_Decode, 245, 5, 245, 1,                // 14698:     decode to DCMPOQ using decoder 245
                                             // 14698:    }
  1, 0,                                      // 14703:    case 0x1: {
  OPC_CheckField, 21, 2, 0,                  // 14705:     check Inst[22:21] == 0x0
  OPC_Decode, 247, 5, 245, 1,                // 14709:     decode to DCMPUQ using decoder 245
                                             // 14709:    }
                                             // 14709:    } // switch Inst[10]
                                             // 14709:   }
  5, 25,                                     // 14714:   case 0x5: {
  OPC_SwitchField, 10, 1,                    // 14716:    switch Inst[10] {
  0, 9,                                      // 14719:    case 0x0: {
  OPC_CheckField, 21, 2, 0,                  // 14721:     check Inst[22:21] == 0x0
  OPC_Decode, 130, 7, 245, 1,                // 14725:     decode to DTSTEXQ using decoder 245
                                             // 14725:    }
  1, 0,                                      // 14730:    case 0x1: {
  OPC_CheckField, 21, 2, 0,                  // 14732:     check Inst[22:21] == 0x0
  OPC_Decode, 134, 7, 246, 1,                // 14736:     decode to DTSTSFQ using decoder 246
                                             // 14736:    }
                                             // 14736:    } // switch Inst[10]
                                             // 14736:   }
  6, 9,                                      // 14741:   case 0x6: {
  OPC_CheckField, 21, 2, 0,                  // 14743:    check Inst[22:21] == 0x0
  OPC_Decode, 254, 6, 247, 1,                // 14747:    decode to DTSTDCQ using decoder 247
                                             // 14747:   }
  7, 9,                                      // 14752:   case 0x7: {
  OPC_CheckField, 21, 2, 0,                  // 14754:    check Inst[22:21] == 0x0
  OPC_Decode, 128, 7, 247, 1,                // 14758:    decode to DTSTDGQ using decoder 247
                                             // 14758:   }
  8, 25,                                     // 14763:   case 0x8: {
  OPC_SwitchField, 10, 1,                    // 14765:    switch Inst[10] {
  0, 9,                                      // 14768:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 14770:     check Inst[20:16] == 0x0
  OPC_Decode, 255, 5, 248, 1,                // 14774:     decode to DCTQPQ using decoder 248
                                             // 14774:    }
  1, 0,                                      // 14779:    case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 14781:     check Inst[20:16] == 0x0
  OPC_Decode, 215, 6, 249, 1,                // 14785:     decode to DRDPQ using decoder 249
                                             // 14785:    }
                                             // 14785:    } // switch Inst[10]
                                             // 14785:   }
  9, 25,                                     // 14790:   case 0x9: {
  OPC_SwitchField, 10, 1,                    // 14792:    switch Inst[10] {
  0, 9,                                      // 14795:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 14797:     check Inst[20:16] == 0x0
  OPC_Decode, 251, 5, 250, 1,                // 14801:     decode to DCTFIXQ using decoder 250
                                             // 14801:    }
  1, 0,                                      // 14806:    case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 14808:     check Inst[20:16] == 0x0
  OPC_Decode, 240, 5, 248, 1,                // 14812:     decode to DCFFIXQ using decoder 248
                                             // 14812:    }
                                             // 14812:    } // switch Inst[10]
                                             // 14812:   }
  10, 25,                                    // 14817:   case 0xa: {
  OPC_SwitchField, 10, 1,                    // 14819:    switch Inst[10] {
  0, 9,                                      // 14822:    case 0x0: {
  OPC_CheckField, 16, 3, 0,                  // 14824:     check Inst[18:16] == 0x0
  OPC_Decode, 130, 6, 251, 1,                // 14828:     decode to DDEDPDQ using decoder 251
                                             // 14828:    }
  1, 0,                                      // 14833:    case 0x1: {
  OPC_CheckField, 16, 4, 0,                  // 14835:     check Inst[19:16] == 0x0
  OPC_Decode, 138, 6, 252, 1,                // 14839:     decode to DENBCDQ using decoder 252
                                             // 14839:    }
                                             // 14839:    } // switch Inst[10]
                                             // 14839:   }
  11, 21,                                    // 14844:   case 0xb: {
  OPC_SwitchField, 10, 1,                    // 14846:    switch Inst[10] {
  0, 9,                                      // 14849:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 14851:     check Inst[20:16] == 0x0
  OPC_Decode, 136, 7, 250, 1,                // 14855:     decode to DXEXQ using decoder 250
                                             // 14855:    }
  1, 0,                                      // 14860:    case 0x1: {
  OPC_Decode, 142, 6, 253, 1,                // 14862:     decode to DIEXQ using decoder 253
                                             // 14862:    }
                                             // 14862:    } // switch Inst[10]
                                             // 14862:   }
  15, 0,                                     // 14867:   case 0xf: {
  OPC_SwitchField, 16, 5,                    // 14869:    switch Inst[20:16] {
  0, 9,                                      // 14872:    case 0x0: {
  OPC_CheckField, 10, 1, 1,                  // 14874:     check Inst[10] == 0x1
  OPC_Decode, 241, 5, 254, 1,                // 14878:     decode to DCFFIXQQ using decoder 254
                                             // 14878:    }
  1, 0,                                      // 14883:    case 0x1: {
  OPC_CheckField, 10, 1, 1,                  // 14885:     check Inst[10] == 0x1
  OPC_Decode, 252, 5, 255, 1,                // 14889:     decode to DCTFIXQQ using decoder 255
                                             // 14889:    }
                                             // 14889:    } // switch Inst[20:16]
                                             // 14889:   }
                                             // 14889:   } // switch Inst[9:6]
                                             // 14889:  }
  5, 159, 1,                                 // 14894:  case 0x5: {
  OPC_SwitchField, 6, 4,                     // 14897:   switch Inst[9:6] {
  0, 17,                                     // 14900:   case 0x0: {
  OPC_SwitchField, 10, 1,                    // 14902:    switch Inst[10] {
  0, 5,                                      // 14905:    case 0x0: {
  OPC_Decode, 221, 5, 243, 1,                // 14907:     decode to DADDQ_rec using decoder 243
                                             // 14907:    }
  1, 0,                                      // 14912:    case 0x1: {
  OPC_Decode, 251, 6, 243, 1,                // 14914:     decode to DSUBQ_rec using decoder 243
                                             // 14914:    }
                                             // 14914:    } // switch Inst[10]
                                             // 14914:   }
  1, 17,                                     // 14919:   case 0x1: {
  OPC_SwitchField, 10, 1,                    // 14921:    switch Inst[10] {
  0, 5,                                      // 14924:    case 0x0: {
  OPC_Decode, 183, 6, 243, 1,                // 14926:     decode to DMULQ_rec using decoder 243
                                             // 14926:    }
  1, 0,                                      // 14931:    case 0x1: {
  OPC_Decode, 135, 6, 243, 1,                // 14933:     decode to DDIVQ_rec using decoder 243
                                             // 14933:    }
                                             // 14933:    } // switch Inst[10]
                                             // 14933:   }
  2, 5,                                      // 14938:   case 0x2: {
  OPC_Decode, 233, 6, 244, 1,                // 14940:    decode to DSCLIQ_rec using decoder 244
                                             // 14940:   }
  3, 5,                                      // 14945:   case 0x3: {
  OPC_Decode, 237, 6, 244, 1,                // 14947:    decode to DSCRIQ_rec using decoder 244
                                             // 14947:   }
  8, 25,                                     // 14952:   case 0x8: {
  OPC_SwitchField, 10, 1,                    // 14954:    switch Inst[10] {
  0, 9,                                      // 14957:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 14959:     check Inst[20:16] == 0x0
  OPC_Decode, 128, 6, 248, 1,                // 14963:     decode to DCTQPQ_rec using decoder 248
                                             // 14963:    }
  1, 0,                                      // 14968:    case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 14970:     check Inst[20:16] == 0x0
  OPC_Decode, 216, 6, 249, 1,                // 14974:     decode to DRDPQ_rec using decoder 249
                                             // 14974:    }
                                             // 14974:    } // switch Inst[10]
                                             // 14974:   }
  9, 25,                                     // 14979:   case 0x9: {
  OPC_SwitchField, 10, 1,                    // 14981:    switch Inst[10] {
  0, 9,                                      // 14984:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 14986:     check Inst[20:16] == 0x0
  OPC_Decode, 253, 5, 250, 1,                // 14990:     decode to DCTFIXQ_rec using decoder 250
                                             // 14990:    }
  1, 0,                                      // 14995:    case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 14997:     check Inst[20:16] == 0x0
  OPC_Decode, 242, 5, 248, 1,                // 15001:     decode to DCFFIXQ_rec using decoder 248
                                             // 15001:    }
                                             // 15001:    } // switch Inst[10]
                                             // 15001:   }
  10, 25,                                    // 15006:   case 0xa: {
  OPC_SwitchField, 10, 1,                    // 15008:    switch Inst[10] {
  0, 9,                                      // 15011:    case 0x0: {
  OPC_CheckField, 16, 3, 0,                  // 15013:     check Inst[18:16] == 0x0
  OPC_Decode, 131, 6, 251, 1,                // 15017:     decode to DDEDPDQ_rec using decoder 251
                                             // 15017:    }
  1, 0,                                      // 15022:    case 0x1: {
  OPC_CheckField, 16, 4, 0,                  // 15024:     check Inst[19:16] == 0x0
  OPC_Decode, 139, 6, 252, 1,                // 15028:     decode to DENBCDQ_rec using decoder 252
                                             // 15028:    }
                                             // 15028:    } // switch Inst[10]
                                             // 15028:   }
  11, 0,                                     // 15033:   case 0xb: {
  OPC_SwitchField, 10, 1,                    // 15035:    switch Inst[10] {
  0, 9,                                      // 15038:    case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 15040:     check Inst[20:16] == 0x0
  OPC_Decode, 137, 7, 250, 1,                // 15044:     decode to DXEXQ_rec using decoder 250
                                             // 15044:    }
  1, 0,                                      // 15049:    case 0x1: {
  OPC_Decode, 143, 6, 253, 1,                // 15051:     decode to DIEXQ_rec using decoder 253
                                             // 15051:    }
                                             // 15051:    } // switch Inst[10]
                                             // 15051:   }
                                             // 15051:   } // switch Inst[9:6]
                                             // 15051:  }
  6, 61,                                     // 15056:  case 0x6: {
  OPC_SwitchField, 6, 3,                     // 15058:   switch Inst[8:6] {
  0, 5,                                      // 15061:   case 0x0: {
  OPC_Decode, 212, 6, 128, 2,                // 15063:    decode to DQUAQ using decoder 256
                                             // 15063:   }
  1, 5,                                      // 15068:   case 0x1: {
  OPC_Decode, 226, 6, 129, 2,                // 15070:    decode to DRRNDQ using decoder 257
                                             // 15070:   }
  2, 5,                                      // 15075:   case 0x2: {
  OPC_Decode, 209, 6, 130, 2,                // 15077:    decode to DQUAIQ using decoder 258
                                             // 15077:   }
  3, 9,                                      // 15082:   case 0x3: {
  OPC_CheckField, 17, 4, 0,                  // 15084:    check Inst[20:17] == 0x0
  OPC_Decode, 222, 6, 131, 2,                // 15088:    decode to DRINTXQ using decoder 259
                                             // 15088:   }
  5, 13,                                     // 15093:   case 0x5: {
  OPC_CheckField, 22, 1, 0,                  // 15095:    check Inst[22] == 0x0
  OPC_CheckField, 9, 2, 2,                   // 15099:    check Inst[10:9] == 0x2
  OPC_Decode, 133, 7, 132, 2,                // 15103:    decode to DTSTSFIQ using decoder 260
                                             // 15103:   }
  7, 0,                                      // 15108:   case 0x7: {
  OPC_CheckField, 17, 4, 0,                  // 15110:    check Inst[20:17] == 0x0
  OPC_Decode, 218, 6, 131, 2,                // 15114:    decode to DRINTNQ using decoder 259
                                             // 15114:   }
                                             // 15114:   } // switch Inst[8:6]
                                             // 15114:  }
  7, 46,                                     // 15119:  case 0x7: {
  OPC_SwitchField, 6, 3,                     // 15121:   switch Inst[8:6] {
  0, 5,                                      // 15124:   case 0x0: {
  OPC_Decode, 213, 6, 128, 2,                // 15126:    decode to DQUAQ_rec using decoder 256
                                             // 15126:   }
  1, 5,                                      // 15131:   case 0x1: {
  OPC_Decode, 227, 6, 129, 2,                // 15133:    decode to DRRNDQ_rec using decoder 257
                                             // 15133:   }
  2, 5,                                      // 15138:   case 0x2: {
  OPC_Decode, 210, 6, 130, 2,                // 15140:    decode to DQUAIQ_rec using decoder 258
                                             // 15140:   }
  3, 9,                                      // 15145:   case 0x3: {
  OPC_CheckField, 17, 4, 0,                  // 15147:    check Inst[20:17] == 0x0
  OPC_Decode, 223, 6, 131, 2,                // 15151:    decode to DRINTXQ_rec using decoder 259
                                             // 15151:   }
  7, 0,                                      // 15156:   case 0x7: {
  OPC_CheckField, 17, 4, 0,                  // 15158:    check Inst[20:17] == 0x0
  OPC_Decode, 219, 6, 131, 2,                // 15162:    decode to DRINTNQ_rec using decoder 259
                                             // 15162:   }
                                             // 15162:   } // switch Inst[8:6]
                                             // 15162:  }
  8, 129, 2,                                 // 15167:  case 0x8: {
  OPC_SwitchField, 6, 5,                     // 15170:   switch Inst[10:6] {
  0, 4,                                      // 15173:   case 0x0: {
  OPC_Decode, 187, 20, 3,                    // 15175:    decode to XSADDQP using decoder 3
                                             // 15175:   }
  1, 4,                                      // 15179:   case 0x1: {
  OPC_Decode, 140, 21, 3,                    // 15181:    decode to XSMULQP using decoder 3
                                             // 15181:   }
  2, 4,                                      // 15185:   case 0x2: {
  OPC_Decode, 193, 20, 3,                    // 15187:    decode to XSCMPEQQP using decoder 3
                                             // 15187:   }
  3, 4,                                      // 15191:   case 0x3: {
  OPC_Decode, 205, 20, 3,                    // 15193:    decode to XSCPSGNQP using decoder 3
                                             // 15193:   }
  4, 8,                                      // 15197:   case 0x4: {
  OPC_CheckField, 21, 2, 0,                  // 15199:    check Inst[22:21] == 0x0
  OPC_Decode, 201, 20, 6,                    // 15203:    decode to XSCMPOQP using decoder 6
                                             // 15203:   }
  5, 8,                                      // 15207:   case 0x5: {
  OPC_CheckField, 21, 2, 0,                  // 15209:    check Inst[22:21] == 0x0
  OPC_Decode, 195, 20, 6,                    // 15213:    decode to XSCMPEXPQP using decoder 6
                                             // 15213:   }
  6, 4,                                      // 15217:   case 0x6: {
  OPC_Decode, 197, 20, 3,                    // 15219:    decode to XSCMPGEQP using decoder 3
                                             // 15219:   }
  7, 4,                                      // 15223:   case 0x7: {
  OPC_Decode, 199, 20, 3,                    // 15225:    decode to XSCMPGTQP using decoder 3
                                             // 15225:   }
  12, 5,                                     // 15229:   case 0xc: {
  OPC_Decode, 247, 20, 133, 2,               // 15231:    decode to XSMADDQP using decoder 261
                                             // 15231:   }
  13, 5,                                     // 15236:   case 0xd: {
  OPC_Decode, 137, 21, 133, 2,               // 15238:    decode to XSMSUBQP using decoder 261
                                             // 15238:   }
  14, 5,                                     // 15243:   case 0xe: {
  OPC_Decode, 152, 21, 133, 2,               // 15245:    decode to XSNMADDQP using decoder 261
                                             // 15245:   }
  15, 5,                                     // 15250:   case 0xf: {
  OPC_Decode, 158, 21, 133, 2,               // 15252:    decode to XSNMSUBQP using decoder 261
                                             // 15252:   }
  16, 4,                                     // 15257:   case 0x10: {
  OPC_Decode, 185, 21, 3,                    // 15259:    decode to XSSUBQP using decoder 3
                                             // 15259:   }
  17, 4,                                     // 15263:   case 0x11: {
  OPC_Decode, 238, 20, 3,                    // 15265:    decode to XSDIVQP using decoder 3
                                             // 15265:   }
  20, 8,                                     // 15269:   case 0x14: {
  OPC_CheckField, 21, 2, 0,                  // 15271:    check Inst[22:21] == 0x0
  OPC_Decode, 203, 20, 6,                    // 15275:    decode to XSCMPUQP using decoder 6
                                             // 15275:   }
  21, 4,                                     // 15279:   case 0x15: {
  OPC_Decode, 250, 20, 3,                    // 15281:    decode to XSMAXCQP using decoder 3
                                             // 15281:   }
  22, 5,                                     // 15285:   case 0x16: {
  OPC_Decode, 191, 21, 134, 2,               // 15287:    decode to XSTSTDCQP using decoder 262
                                             // 15287:   }
  23, 4,                                     // 15292:   case 0x17: {
  OPC_Decode, 130, 21, 3,                    // 15294:    decode to XSMINCQP using decoder 3
                                             // 15294:   }
  25, 39,                                    // 15298:   case 0x19: {
  OPC_SwitchField, 16, 5,                    // 15300:    switch Inst[20:16] {
  0, 4,                                      // 15303:    case 0x0: {
  OPC_Decode, 183, 20, 7,                    // 15305:     decode to XSABSQP using decoder 7
                                             // 15305:    }
  2, 4,                                      // 15309:    case 0x2: {
  OPC_Decode, 194, 21, 7,                    // 15311:     decode to XSXEXPQP using decoder 7
                                             // 15311:    }
  8, 4,                                      // 15315:    case 0x8: {
  OPC_Decode, 145, 21, 7,                    // 15317:     decode to XSNABSQP using decoder 7
                                             // 15317:    }
  16, 4,                                     // 15321:    case 0x10: {
  OPC_Decode, 147, 21, 7,                    // 15323:     decode to XSNEGQP using decoder 7
                                             // 15323:    }
  18, 4,                                     // 15327:    case 0x12: {
  OPC_Decode, 196, 21, 7,                    // 15329:     decode to XSXSIGQP using decoder 7
                                             // 15329:    }
  27, 0,                                     // 15333:    case 0x1b: {
  OPC_Decode, 181, 21, 7,                    // 15335:     decode to XSSQRTQP using decoder 7
                                             // 15335:    }
                                             // 15335:    } // switch Inst[20:16]
                                             // 15335:   }
  26, 79,                                    // 15339:   case 0x1a: {
  OPC_SwitchField, 16, 5,                    // 15341:    switch Inst[20:16] {
  0, 4,                                      // 15344:    case 0x0: {
  OPC_Decode, 225, 20, 7,                    // 15346:     decode to XSCVQPUQZ using decoder 7
                                             // 15346:    }
  1, 4,                                      // 15350:    case 0x1: {
  OPC_Decode, 226, 20, 7,                    // 15352:     decode to XSCVQPUWZ using decoder 7
                                             // 15352:    }
  2, 5,                                      // 15356:    case 0x2: {
  OPC_Decode, 233, 20, 135, 2,               // 15358:     decode to XSCVUDQP using decoder 263
                                             // 15358:    }
  3, 4,                                      // 15363:    case 0x3: {
  OPC_Decode, 234, 20, 7,                    // 15365:     decode to XSCVUQQP using decoder 7
                                             // 15365:    }
  8, 4,                                      // 15369:    case 0x8: {
  OPC_Decode, 222, 20, 7,                    // 15371:     decode to XSCVQPSQZ using decoder 7
                                             // 15371:    }
  9, 4,                                      // 15375:    case 0x9: {
  OPC_Decode, 223, 20, 7,                    // 15377:     decode to XSCVQPSWZ using decoder 7
                                             // 15377:    }
  10, 5,                                     // 15381:    case 0xa: {
  OPC_Decode, 227, 20, 135, 2,               // 15383:     decode to XSCVSDQP using decoder 263
                                             // 15383:    }
  11, 4,                                     // 15388:    case 0xb: {
  OPC_Decode, 230, 20, 7,                    // 15390:     decode to XSCVSQQP using decoder 7
                                             // 15390:    }
  17, 4,                                     // 15394:    case 0x11: {
  OPC_Decode, 224, 20, 7,                    // 15396:     decode to XSCVQPUDZ using decoder 7
                                             // 15396:    }
  20, 5,                                     // 15400:    case 0x14: {
  OPC_Decode, 219, 20, 136, 2,               // 15402:     decode to XSCVQPDP using decoder 264
                                             // 15402:    }
  22, 5,                                     // 15407:    case 0x16: {
  OPC_Decode, 207, 20, 135, 2,               // 15409:     decode to XSCVDPQP using decoder 263
                                             // 15409:    }
  25, 0,                                     // 15414:    case 0x19: {
  OPC_Decode, 221, 20, 7,                    // 15416:     decode to XSCVQPSDZ using decoder 7
                                             // 15416:    }
                                             // 15416:    } // switch Inst[20:16]
                                             // 15416:   }
  27, 0,                                     // 15420:   case 0x1b: {
  OPC_Decode, 242, 20, 137, 2,               // 15422:    decode to XSIEXPQP using decoder 265
                                             // 15422:   }
                                             // 15422:   } // switch Inst[10:6]
                                             // 15422:  }
  9, 76,                                     // 15427:  case 0x9: {
  OPC_SwitchField, 6, 5,                     // 15429:   switch Inst[10:6] {
  0, 4,                                      // 15432:   case 0x0: {
  OPC_Decode, 188, 20, 3,                    // 15434:    decode to XSADDQPO using decoder 3
                                             // 15434:   }
  1, 4,                                      // 15438:   case 0x1: {
  OPC_Decode, 141, 21, 3,                    // 15440:    decode to XSMULQPO using decoder 3
                                             // 15440:   }
  12, 5,                                     // 15444:   case 0xc: {
  OPC_Decode, 248, 20, 133, 2,               // 15446:    decode to XSMADDQPO using decoder 261
                                             // 15446:   }
  13, 5,                                     // 15451:   case 0xd: {
  OPC_Decode, 138, 21, 133, 2,               // 15453:    decode to XSMSUBQPO using decoder 261
                                             // 15453:   }
  14, 5,                                     // 15458:   case 0xe: {
  OPC_Decode, 153, 21, 133, 2,               // 15460:    decode to XSNMADDQPO using decoder 261
                                             // 15460:   }
  15, 5,                                     // 15465:   case 0xf: {
  OPC_Decode, 159, 21, 133, 2,               // 15467:    decode to XSNMSUBQPO using decoder 261
                                             // 15467:   }
  16, 4,                                     // 15472:   case 0x10: {
  OPC_Decode, 186, 21, 3,                    // 15474:    decode to XSSUBQPO using decoder 3
                                             // 15474:   }
  17, 4,                                     // 15478:   case 0x11: {
  OPC_Decode, 239, 20, 3,                    // 15480:    decode to XSDIVQPO using decoder 3
                                             // 15480:   }
  25, 8,                                     // 15484:   case 0x19: {
  OPC_CheckField, 16, 5, 27,                 // 15486:    check Inst[20:16] == 0x1b
  OPC_Decode, 182, 21, 7,                    // 15490:    decode to XSSQRTQPO using decoder 7
                                             // 15490:   }
  26, 0,                                     // 15494:   case 0x1a: {
  OPC_CheckField, 16, 5, 20,                 // 15496:    check Inst[20:16] == 0x14
  OPC_Decode, 220, 20, 136, 2,               // 15500:    decode to XSCVQPDPO using decoder 264
                                             // 15500:   }
                                             // 15500:   } // switch Inst[10:6]
                                             // 15500:  }
  10, 25,                                    // 15505:  case 0xa: {
  OPC_SwitchField, 6, 3,                     // 15507:   switch Inst[8:6] {
  0, 9,                                      // 15510:   case 0x0: {
  OPC_CheckField, 17, 4, 0,                  // 15512:    check Inst[20:17] == 0x0
  OPC_Decode, 174, 21, 138, 2,               // 15516:    decode to XSRQPI using decoder 266
                                             // 15516:   }
  1, 0,                                      // 15521:   case 0x1: {
  OPC_CheckField, 17, 4, 0,                  // 15523:    check Inst[20:17] == 0x0
  OPC_Decode, 176, 21, 138, 2,               // 15527:    decode to XSRQPXP using decoder 266
                                             // 15527:   }
                                             // 15527:   } // switch Inst[8:6]
                                             // 15527:  }
  11, 13,                                    // 15532:  case 0xb: {
  OPC_CheckField, 17, 4, 0,                  // 15534:   check Inst[20:17] == 0x0
  OPC_CheckField, 6, 3, 0,                   // 15538:   check Inst[8:6] == 0x0
  OPC_Decode, 175, 21, 138, 2,               // 15542:   decode to XSRQPIX using decoder 266
                                             // 15542:  }
  12, 36,                                    // 15547:  case 0xc: {
  OPC_SwitchField, 6, 6,                     // 15549:   switch Inst[11:6] {
  1, 9,                                      // 15552:   case 0x1: {
  OPC_CheckField, 12, 9, 0,                  // 15554:    check Inst[20:12] == 0x0
  OPC_Decode, 139, 12, 148, 1,               // 15558:    decode to MTFSB1 using decoder 148
                                             // 15558:   }
  2, 9,                                      // 15563:   case 0x2: {
  OPC_CheckField, 12, 9, 0,                  // 15565:    check Inst[20:12] == 0x0
  OPC_Decode, 138, 12, 148, 1,               // 15569:    decode to MTFSB0 using decoder 148
                                             // 15569:   }
  4, 0,                                      // 15574:   case 0x4: {
  OPC_CheckField, 17, 6, 0,                  // 15576:    check Inst[22:17] == 0x0
  OPC_Decode, 141, 12, 139, 2,               // 15580:    decode to MTFSFI using decoder 267
                                             // 15580:   }
                                             // 15580:   } // switch Inst[11:6]
                                             // 15580:  }
  13, 13,                                    // 15585:  case 0xd: {
  OPC_CheckField, 17, 6, 0,                  // 15587:   check Inst[22:17] == 0x0
  OPC_CheckField, 6, 6, 4,                   // 15591:   check Inst[11:6] == 0x4
  OPC_Decode, 142, 12, 140, 2,               // 15595:   decode to MTFSFI_rec using decoder 268
                                             // 15595:  }
  14, 84,                                    // 15600:  case 0xe: {
  OPC_SwitchField, 6, 5,                     // 15602:   switch Inst[10:6] {
  18, 72,                                    // 15605:   case 0x12: {
  OPC_SwitchField, 16, 5,                    // 15607:    switch Inst[20:16] {
  0, 9,                                      // 15610:    case 0x0: {
  OPC_CheckField, 11, 5, 0,                  // 15612:     check Inst[15:11] == 0x0
  OPC_Decode, 224, 11, 141, 2,               // 15616:     decode to MFFS using decoder 269
                                             // 15616:    }
  1, 9,                                      // 15621:    case 0x1: {
  OPC_CheckField, 11, 5, 0,                  // 15623:     check Inst[15:11] == 0x0
  OPC_Decode, 227, 11, 141, 2,               // 15627:     decode to MFFSCE using decoder 269
                                             // 15627:    }
  20, 5,                                     // 15632:    case 0x14: {
  OPC_Decode, 225, 11, 172, 1,               // 15634:     decode to MFFSCDRN using decoder 172
                                             // 15634:    }
  21, 9,                                     // 15639:    case 0x15: {
  OPC_CheckField, 14, 2, 0,                  // 15641:     check Inst[15:14] == 0x0
  OPC_Decode, 226, 11, 142, 2,               // 15645:     decode to MFFSCDRNI using decoder 270
                                             // 15645:    }
  22, 5,                                     // 15650:    case 0x16: {
  OPC_Decode, 228, 11, 172, 1,               // 15652:     decode to MFFSCRN using decoder 172
                                             // 15652:    }
  23, 9,                                     // 15657:    case 0x17: {
  OPC_CheckField, 13, 3, 0,                  // 15659:     check Inst[15:13] == 0x0
  OPC_Decode, 229, 11, 143, 2,               // 15663:     decode to MFFSCRNI using decoder 271
                                             // 15663:    }
  24, 0,                                     // 15668:    case 0x18: {
  OPC_CheckField, 11, 5, 0,                  // 15670:     check Inst[15:11] == 0x0
  OPC_Decode, 230, 11, 141, 2,               // 15674:     decode to MFFSL using decoder 269
                                             // 15674:    }
                                             // 15674:    } // switch Inst[20:16]
                                             // 15674:   }
  22, 0,                                     // 15679:   case 0x16: {
  OPC_Decode, 140, 12, 144, 2,               // 15681:    decode to MTFSF using decoder 272
                                             // 15681:   }
                                             // 15681:   } // switch Inst[10:6]
                                             // 15681:  }
  15, 21,                                    // 15686:  case 0xf: {
  OPC_SwitchField, 6, 5,                     // 15688:   switch Inst[10:6] {
  18, 9,                                     // 15691:   case 0x12: {
  OPC_CheckField, 11, 10, 0,                 // 15693:    check Inst[20:11] == 0x0
  OPC_Decode, 231, 11, 141, 2,               // 15697:    decode to MFFS_rec using decoder 269
                                             // 15697:   }
  22, 0,                                     // 15702:   case 0x16: {
  OPC_Decode, 144, 12, 144, 2,               // 15704:    decode to MTFSF_rec using decoder 272
                                             // 15704:   }
                                             // 15704:   } // switch Inst[10:6]
                                             // 15704:  }
  16, 98,                                    // 15709:  case 0x10: {
  OPC_SwitchField, 6, 5,                     // 15711:   switch Inst[10:6] {
  0, 5,                                      // 15714:   case 0x0: {
  OPC_Decode, 188, 9, 194, 1,                // 15716:    decode to FCPSGNS using decoder 194
                                             // 15716:   }
  1, 9,                                      // 15721:   case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 15723:    check Inst[20:16] == 0x0
  OPC_Decode, 231, 9, 195, 1,                // 15727:    decode to FNEGS using decoder 195
                                             // 15727:   }
  2, 9,                                      // 15732:   case 0x2: {
  OPC_CheckField, 16, 5, 0,                  // 15734:    check Inst[20:16] == 0x0
  OPC_Decode, 215, 9, 195, 1,                // 15738:    decode to FMR using decoder 195
                                             // 15738:   }
  4, 9,                                      // 15743:   case 0x4: {
  OPC_CheckField, 16, 5, 0,                  // 15745:    check Inst[20:16] == 0x0
  OPC_Decode, 227, 9, 195, 1,                // 15749:    decode to FNABSS using decoder 195
                                             // 15749:   }
  8, 9,                                      // 15754:   case 0x8: {
  OPC_CheckField, 16, 5, 0,                  // 15756:    check Inst[20:16] == 0x0
  OPC_Decode, 167, 9, 195, 1,                // 15760:    decode to FABSS using decoder 195
                                             // 15760:   }
  12, 9,                                     // 15765:   case 0xc: {
  OPC_CheckField, 16, 5, 0,                  // 15767:    check Inst[20:16] == 0x0
  OPC_Decode, 251, 9, 195, 1,                // 15771:    decode to FRINS using decoder 195
                                             // 15771:   }
  13, 9,                                     // 15776:   case 0xd: {
  OPC_CheckField, 16, 5, 0,                  // 15778:    check Inst[20:16] == 0x0
  OPC_Decode, 131, 10, 195, 1,               // 15782:    decode to FRIZS using decoder 195
                                             // 15782:   }
  14, 9,                                     // 15787:   case 0xe: {
  OPC_CheckField, 16, 5, 0,                  // 15789:    check Inst[20:16] == 0x0
  OPC_Decode, 255, 9, 195, 1,                // 15793:    decode to FRIPS using decoder 195
                                             // 15793:   }
  15, 0,                                     // 15798:   case 0xf: {
  OPC_CheckField, 16, 5, 0,                  // 15800:    check Inst[20:16] == 0x0
  OPC_Decode, 247, 9, 195, 1,                // 15804:    decode to FRIMS using decoder 195
                                             // 15804:   }
                                             // 15804:   } // switch Inst[10:6]
                                             // 15804:  }
  17, 98,                                    // 15809:  case 0x11: {
  OPC_SwitchField, 6, 5,                     // 15811:   switch Inst[10:6] {
  0, 5,                                      // 15814:   case 0x0: {
  OPC_Decode, 189, 9, 194, 1,                // 15816:    decode to FCPSGNS_rec using decoder 194
                                             // 15816:   }
  1, 9,                                      // 15821:   case 0x1: {
  OPC_CheckField, 16, 5, 0,                  // 15823:    check Inst[20:16] == 0x0
  OPC_Decode, 232, 9, 195, 1,                // 15827:    decode to FNEGS_rec using decoder 195
                                             // 15827:   }
  2, 9,                                      // 15832:   case 0x2: {
  OPC_CheckField, 16, 5, 0,                  // 15834:    check Inst[20:16] == 0x0
  OPC_Decode, 216, 9, 195, 1,                // 15838:    decode to FMR_rec using decoder 195
                                             // 15838:   }
  4, 9,                                      // 15843:   case 0x4: {
  OPC_CheckField, 16, 5, 0,                  // 15845:    check Inst[20:16] == 0x0
  OPC_Decode, 228, 9, 195, 1,                // 15849:    decode to FNABSS_rec using decoder 195
                                             // 15849:   }
  8, 9,                                      // 15854:   case 0x8: {
  OPC_CheckField, 16, 5, 0,                  // 15856:    check Inst[20:16] == 0x0
  OPC_Decode, 168, 9, 195, 1,                // 15860:    decode to FABSS_rec using decoder 195
                                             // 15860:   }
  12, 9,                                     // 15865:   case 0xc: {
  OPC_CheckField, 16, 5, 0,                  // 15867:    check Inst[20:16] == 0x0
  OPC_Decode, 252, 9, 195, 1,                // 15871:    decode to FRINS_rec using decoder 195
                                             // 15871:   }
  13, 9,                                     // 15876:   case 0xd: {
  OPC_CheckField, 16, 5, 0,                  // 15878:    check Inst[20:16] == 0x0
  OPC_Decode, 132, 10, 195, 1,               // 15882:    decode to FRIZS_rec using decoder 195
                                             // 15882:   }
  14, 9,                                     // 15887:   case 0xe: {
  OPC_CheckField, 16, 5, 0,                  // 15889:    check Inst[20:16] == 0x0
  OPC_Decode, 128, 10, 195, 1,               // 15893:    decode to FRIPS_rec using decoder 195
                                             // 15893:   }
  15, 0,                                     // 15898:   case 0xf: {
  OPC_CheckField, 16, 5, 0,                  // 15900:    check Inst[20:16] == 0x0
  OPC_Decode, 248, 9, 195, 1,                // 15904:    decode to FRIMS_rec using decoder 195
                                             // 15904:   }
                                             // 15904:   } // switch Inst[10:6]
                                             // 15904:  }
  24, 13,                                    // 15909:  case 0x18: {
  OPC_CheckField, 16, 5, 0,                  // 15911:   check Inst[20:16] == 0x0
  OPC_CheckField, 6, 5, 0,                   // 15915:   check Inst[10:6] == 0x0
  OPC_Decode, 133, 10, 193, 1,               // 15919:   decode to FRSP using decoder 193
                                             // 15919:  }
  25, 13,                                    // 15924:  case 0x19: {
  OPC_CheckField, 16, 5, 0,                  // 15926:   check Inst[20:16] == 0x0
  OPC_CheckField, 6, 5, 0,                   // 15930:   check Inst[10:6] == 0x0
  OPC_Decode, 134, 10, 193, 1,               // 15934:   decode to FRSP_rec using decoder 193
                                             // 15934:  }
  28, 69,                                    // 15939:  case 0x1c: {
  OPC_SwitchField, 6, 5,                     // 15941:   switch Inst[10:6] {
  0, 9,                                      // 15944:   case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 15946:    check Inst[20:16] == 0x0
  OPC_Decode, 198, 9, 172, 1,                // 15950:    decode to FCTIW using decoder 172
                                             // 15950:   }
  4, 9,                                      // 15955:   case 0x4: {
  OPC_CheckField, 16, 5, 0,                  // 15957:    check Inst[20:16] == 0x0
  OPC_Decode, 199, 9, 172, 1,                // 15961:    decode to FCTIWU using decoder 172
                                             // 15961:   }
  25, 9,                                     // 15966:   case 0x19: {
  OPC_CheckField, 16, 5, 0,                  // 15968:    check Inst[20:16] == 0x0
  OPC_Decode, 190, 9, 172, 1,                // 15972:    decode to FCTID using decoder 172
                                             // 15972:   }
  26, 9,                                     // 15977:   case 0x1a: {
  OPC_CheckField, 16, 5, 0,                  // 15979:    check Inst[20:16] == 0x0
  OPC_Decode, 174, 9, 172, 1,                // 15983:    decode to FCFID using decoder 172
                                             // 15983:   }
  29, 9,                                     // 15988:   case 0x1d: {
  OPC_CheckField, 16, 5, 0,                  // 15990:    check Inst[20:16] == 0x0
  OPC_Decode, 191, 9, 172, 1,                // 15994:    decode to FCTIDU using decoder 172
                                             // 15994:   }
  30, 0,                                     // 15999:   case 0x1e: {
  OPC_CheckField, 16, 5, 0,                  // 16001:    check Inst[20:16] == 0x0
  OPC_Decode, 177, 9, 172, 1,                // 16005:    decode to FCFIDU using decoder 172
                                             // 16005:   }
                                             // 16005:   } // switch Inst[10:6]
                                             // 16005:  }
  29, 69,                                    // 16010:  case 0x1d: {
  OPC_SwitchField, 6, 5,                     // 16012:   switch Inst[10:6] {
  0, 9,                                      // 16015:   case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 16017:    check Inst[20:16] == 0x0
  OPC_Decode, 205, 9, 172, 1,                // 16021:    decode to FCTIW_rec using decoder 172
                                             // 16021:   }
  4, 9,                                      // 16026:   case 0x4: {
  OPC_CheckField, 16, 5, 0,                  // 16028:    check Inst[20:16] == 0x0
  OPC_Decode, 202, 9, 172, 1,                // 16032:    decode to FCTIWU_rec using decoder 172
                                             // 16032:   }
  25, 9,                                     // 16037:   case 0x19: {
  OPC_CheckField, 16, 5, 0,                  // 16039:    check Inst[20:16] == 0x0
  OPC_Decode, 197, 9, 172, 1,                // 16043:    decode to FCTID_rec using decoder 172
                                             // 16043:   }
  26, 9,                                     // 16048:   case 0x1a: {
  OPC_CheckField, 16, 5, 0,                  // 16050:    check Inst[20:16] == 0x0
  OPC_Decode, 181, 9, 172, 1,                // 16054:    decode to FCFID_rec using decoder 172
                                             // 16054:   }
  29, 9,                                     // 16059:   case 0x1d: {
  OPC_CheckField, 16, 5, 0,                  // 16061:    check Inst[20:16] == 0x0
  OPC_Decode, 194, 9, 172, 1,                // 16065:    decode to FCTIDU_rec using decoder 172
                                             // 16065:   }
  30, 0,                                     // 16070:   case 0x1e: {
  OPC_CheckField, 16, 5, 0,                  // 16072:    check Inst[20:16] == 0x0
  OPC_Decode, 180, 9, 172, 1,                // 16076:    decode to FCFIDU_rec using decoder 172
                                             // 16076:   }
                                             // 16076:   } // switch Inst[10:6]
                                             // 16076:  }
  30, 47,                                    // 16081:  case 0x1e: {
  OPC_SwitchField, 6, 5,                     // 16083:   switch Inst[10:6] {
  0, 9,                                      // 16086:   case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 16088:    check Inst[20:16] == 0x0
  OPC_Decode, 203, 9, 172, 1,                // 16092:    decode to FCTIWZ using decoder 172
                                             // 16092:   }
  4, 9,                                      // 16097:   case 0x4: {
  OPC_CheckField, 16, 5, 0,                  // 16099:    check Inst[20:16] == 0x0
  OPC_Decode, 200, 9, 172, 1,                // 16103:    decode to FCTIWUZ using decoder 172
                                             // 16103:   }
  25, 9,                                     // 16108:   case 0x19: {
  OPC_CheckField, 16, 5, 0,                  // 16110:    check Inst[20:16] == 0x0
  OPC_Decode, 195, 9, 172, 1,                // 16114:    decode to FCTIDZ using decoder 172
                                             // 16114:   }
  29, 0,                                     // 16119:   case 0x1d: {
  OPC_CheckField, 16, 5, 0,                  // 16121:    check Inst[20:16] == 0x0
  OPC_Decode, 192, 9, 172, 1,                // 16125:    decode to FCTIDUZ using decoder 172
                                             // 16125:   }
                                             // 16125:   } // switch Inst[10:6]
                                             // 16125:  }
  31, 47,                                    // 16130:  case 0x1f: {
  OPC_SwitchField, 6, 5,                     // 16132:   switch Inst[10:6] {
  0, 9,                                      // 16135:   case 0x0: {
  OPC_CheckField, 16, 5, 0,                  // 16137:    check Inst[20:16] == 0x0
  OPC_Decode, 204, 9, 172, 1,                // 16141:    decode to FCTIWZ_rec using decoder 172
                                             // 16141:   }
  4, 9,                                      // 16146:   case 0x4: {
  OPC_CheckField, 16, 5, 0,                  // 16148:    check Inst[20:16] == 0x0
  OPC_Decode, 201, 9, 172, 1,                // 16152:    decode to FCTIWUZ_rec using decoder 172
                                             // 16152:   }
  25, 9,                                     // 16157:   case 0x19: {
  OPC_CheckField, 16, 5, 0,                  // 16159:    check Inst[20:16] == 0x0
  OPC_Decode, 196, 9, 172, 1,                // 16163:    decode to FCTIDZ_rec using decoder 172
                                             // 16163:   }
  29, 0,                                     // 16168:   case 0x1d: {
  OPC_CheckField, 16, 5, 0,                  // 16170:    check Inst[20:16] == 0x0
  OPC_Decode, 193, 9, 172, 1,                // 16174:    decode to FCTIDUZ_rec using decoder 172
                                             // 16174:   }
                                             // 16174:   } // switch Inst[10:6]
                                             // 16174:  }
  36, 9,                                     // 16179:  case 0x24: {
  OPC_CheckField, 6, 5, 0,                   // 16181:   check Inst[10:6] == 0x0
  OPC_Decode, 206, 9, 171, 1,                // 16185:   decode to FDIV using decoder 171
                                             // 16185:  }
  37, 9,                                     // 16190:  case 0x25: {
  OPC_CheckField, 6, 5, 0,                   // 16192:   check Inst[10:6] == 0x0
  OPC_Decode, 209, 9, 171, 1,                // 16196:   decode to FDIV_rec using decoder 171
                                             // 16196:  }
  40, 9,                                     // 16201:  case 0x28: {
  OPC_CheckField, 6, 5, 0,                   // 16203:   check Inst[10:6] == 0x0
  OPC_Decode, 147, 10, 171, 1,               // 16207:   decode to FSUB using decoder 171
                                             // 16207:  }
  41, 9,                                     // 16212:  case 0x29: {
  OPC_CheckField, 6, 5, 0,                   // 16214:   check Inst[10:6] == 0x0
  OPC_Decode, 150, 10, 171, 1,               // 16218:   decode to FSUB_rec using decoder 171
                                             // 16218:  }
  42, 9,                                     // 16223:  case 0x2a: {
  OPC_CheckField, 6, 5, 0,                   // 16225:   check Inst[10:6] == 0x0
  OPC_Decode, 169, 9, 171, 1,                // 16229:   decode to FADD using decoder 171
                                             // 16229:  }
  43, 9,                                     // 16234:  case 0x2b: {
  OPC_CheckField, 6, 5, 0,                   // 16236:   check Inst[10:6] == 0x0
  OPC_Decode, 172, 9, 171, 1,                // 16240:   decode to FADD_rec using decoder 171
                                             // 16240:  }
  44, 13,                                    // 16245:  case 0x2c: {
  OPC_CheckField, 16, 5, 0,                  // 16247:   check Inst[20:16] == 0x0
  OPC_CheckField, 6, 5, 0,                   // 16251:   check Inst[10:6] == 0x0
  OPC_Decode, 143, 10, 172, 1,               // 16255:   decode to FSQRT using decoder 172
                                             // 16255:  }
  45, 13,                                    // 16260:  case 0x2d: {
  OPC_CheckField, 16, 5, 0,                  // 16262:   check Inst[20:16] == 0x0
  OPC_CheckField, 6, 5, 0,                   // 16266:   check Inst[10:6] == 0x0
  OPC_Decode, 146, 10, 172, 1,               // 16270:   decode to FSQRT_rec using decoder 172
                                             // 16270:  }
  46, 5,                                     // 16275:  case 0x2e: {
  OPC_Decode, 141, 10, 145, 2,               // 16277:   decode to FSELS using decoder 273
                                             // 16277:  }
  47, 5,                                     // 16282:  case 0x2f: {
  OPC_Decode, 142, 10, 145, 2,               // 16284:   decode to FSELS_rec using decoder 273
                                             // 16284:  }
  48, 13,                                    // 16289:  case 0x30: {
  OPC_CheckField, 16, 5, 0,                  // 16291:   check Inst[20:16] == 0x0
  OPC_CheckField, 6, 5, 0,                   // 16295:   check Inst[10:6] == 0x0
  OPC_Decode, 241, 9, 172, 1,                // 16299:   decode to FRE using decoder 172
                                             // 16299:  }
  49, 13,                                    // 16304:  case 0x31: {
  OPC_CheckField, 16, 5, 0,                  // 16306:   check Inst[20:16] == 0x0
  OPC_CheckField, 6, 5, 0,                   // 16310:   check Inst[10:6] == 0x0
  OPC_Decode, 244, 9, 172, 1,                // 16314:   decode to FRE_rec using decoder 172
                                             // 16314:  }
  50, 9,                                     // 16319:  case 0x32: {
  OPC_CheckField, 11, 5, 0,                  // 16321:   check Inst[15:11] == 0x0
  OPC_Decode, 221, 9, 146, 2,                // 16325:   decode to FMUL using decoder 274
                                             // 16325:  }
  51, 9,                                     // 16330:  case 0x33: {
  OPC_CheckField, 11, 5, 0,                  // 16332:   check Inst[15:11] == 0x0
  OPC_Decode, 224, 9, 146, 2,                // 16336:   decode to FMUL_rec using decoder 274
                                             // 16336:  }
  52, 13,                                    // 16341:  case 0x34: {
  OPC_CheckField, 16, 5, 0,                  // 16343:   check Inst[20:16] == 0x0
  OPC_CheckField, 6, 5, 0,                   // 16347:   check Inst[10:6] == 0x0
  OPC_Decode, 135, 10, 172, 1,               // 16351:   decode to FRSQRTE using decoder 172
                                             // 16351:  }
  53, 13,                                    // 16356:  case 0x35: {
  OPC_CheckField, 16, 5, 0,                  // 16358:   check Inst[20:16] == 0x0
  OPC_CheckField, 6, 5, 0,                   // 16362:   check Inst[10:6] == 0x0
  OPC_Decode, 138, 10, 172, 1,               // 16366:   decode to FRSQRTE_rec using decoder 172
                                             // 16366:  }
  56, 5,                                     // 16371:  case 0x38: {
  OPC_Decode, 217, 9, 147, 2,                // 16373:   decode to FMSUB using decoder 275
                                             // 16373:  }
  57, 5,                                     // 16378:  case 0x39: {
  OPC_Decode, 220, 9, 147, 2,                // 16380:   decode to FMSUB_rec using decoder 275
                                             // 16380:  }
  58, 5,                                     // 16385:  case 0x3a: {
  OPC_Decode, 211, 9, 147, 2,                // 16387:   decode to FMADD using decoder 275
                                             // 16387:  }
  59, 5,                                     // 16392:  case 0x3b: {
  OPC_Decode, 214, 9, 147, 2,                // 16394:   decode to FMADD_rec using decoder 275
                                             // 16394:  }
  60, 5,                                     // 16399:  case 0x3c: {
  OPC_Decode, 237, 9, 147, 2,                // 16401:   decode to FNMSUB using decoder 275
                                             // 16401:  }
  61, 5,                                     // 16406:  case 0x3d: {
  OPC_Decode, 240, 9, 147, 2,                // 16408:   decode to FNMSUB_rec using decoder 275
                                             // 16408:  }
  62, 5,                                     // 16413:  case 0x3e: {
  OPC_Decode, 233, 9, 147, 2,                // 16415:   decode to FNMADD using decoder 275
                                             // 16415:  }
  63, 0,                                     // 16420:  case 0x3f: {
  OPC_Decode, 236, 9, 147, 2,                // 16422:   decode to FNMADD_rec using decoder 275
                                             // 16422:  }
                                             // 16422:  } // switch Inst[5:0]
                                             // 16422: }
                                             // 16422: } // switch Inst[31:26]
};
static const uint8_t DecoderTableSPE32[3347] = {
  OPC_SwitchField, 3, 8,                     //    0: switch Inst[10:3] {
  64, 47,                                    //    3: case 0x40: {
  OPC_SwitchField, 0, 3,                     //    5:  switch Inst[2:0] {
  0, 9,                                      //    8:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  //   10:   check Inst[31:26] == 0x4
  OPC_Decode, 212, 7, 148, 2,                //   14:   decode to EVADDW using decoder 276
                                             //   14:  }
  2, 9,                                      //   19:  case 0x2: {
  OPC_CheckField, 26, 6, 4,                  //   21:   check Inst[31:26] == 0x4
  OPC_Decode, 207, 7, 149, 2,                //   25:   decode to EVADDIW using decoder 277
                                             //   25:  }
  4, 9,                                      //   30:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  //   32:   check Inst[31:26] == 0x4
  OPC_Decode, 142, 9, 148, 2,                //   36:   decode to EVSUBFW using decoder 276
                                             //   36:  }
  6, 0,                                      //   41:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  //   43:   check Inst[31:26] == 0x4
  OPC_Decode, 143, 9, 150, 2,                //   47:   decode to EVSUBIFW using decoder 278
                                             //   47:  }
                                             //   47:  } // switch Inst[2:0]
                                             //   47: }
  65, 118,                                   //   52: case 0x41: {
  OPC_SwitchField, 0, 3,                     //   54:  switch Inst[2:0] {
  0, 13,                                     //   57:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  //   59:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  //   63:   check Inst[15:11] == 0x0
  OPC_Decode, 206, 7, 151, 2,                //   67:   decode to EVABS using decoder 279
                                             //   67:  }
  1, 13,                                     //   72:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  //   74:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  //   78:   check Inst[15:11] == 0x0
  OPC_Decode, 236, 8, 151, 2,                //   82:   decode to EVNEG using decoder 279
                                             //   82:  }
  2, 13,                                     //   87:  case 0x2: {
  OPC_CheckField, 26, 6, 4,                  //   89:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  //   93:   check Inst[15:11] == 0x0
  OPC_Decode, 225, 7, 151, 2,                //   97:   decode to EVEXTSB using decoder 279
                                             //   97:  }
  3, 13,                                     //  102:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  //  104:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  //  108:   check Inst[15:11] == 0x0
  OPC_Decode, 226, 7, 151, 2,                //  112:   decode to EVEXTSH using decoder 279
                                             //  112:  }
  4, 13,                                     //  117:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  //  119:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  //  123:   check Inst[15:11] == 0x0
  OPC_Decode, 242, 8, 151, 2,                //  127:   decode to EVRNDW using decoder 279
                                             //  127:  }
  5, 13,                                     //  132:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  //  134:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  //  138:   check Inst[15:11] == 0x0
  OPC_Decode, 221, 7, 151, 2,                //  142:   decode to EVCNTLZW using decoder 279
                                             //  142:  }
  6, 13,                                     //  147:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  //  149:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  //  153:   check Inst[15:11] == 0x0
  OPC_Decode, 220, 7, 151, 2,                //  157:   decode to EVCNTLSW using decoder 279
                                             //  157:  }
  7, 0,                                      //  162:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  //  164:   check Inst[31:26] == 0x4
  OPC_Decode, 164, 5, 81,                    //  168:   decode to BRINC using decoder 81
                                             //  168:  }
                                             //  168:  } // switch Inst[2:0]
                                             //  168: }
  66, 47,                                    //  172: case 0x42: {
  OPC_SwitchField, 0, 3,                     //  174:  switch Inst[2:0] {
  1, 9,                                      //  177:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  //  179:   check Inst[31:26] == 0x4
  OPC_Decode, 213, 7, 148, 2,                //  183:   decode to EVAND using decoder 276
                                             //  183:  }
  2, 9,                                      //  188:  case 0x2: {
  OPC_CheckField, 26, 6, 4,                  //  190:   check Inst[31:26] == 0x4
  OPC_Decode, 214, 7, 148, 2,                //  194:   decode to EVANDC using decoder 276
                                             //  194:  }
  6, 9,                                      //  199:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  //  201:   check Inst[31:26] == 0x4
  OPC_Decode, 144, 9, 148, 2,                //  205:   decode to EVXOR using decoder 276
                                             //  205:  }
  7, 0,                                      //  210:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  //  212:   check Inst[31:26] == 0x4
  OPC_Decode, 238, 8, 148, 2,                //  216:   decode to EVOR using decoder 276
                                             //  216:  }
                                             //  216:  } // switch Inst[2:0]
                                             //  216: }
  67, 47,                                    //  221: case 0x43: {
  OPC_SwitchField, 0, 3,                     //  223:  switch Inst[2:0] {
  0, 9,                                      //  226:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  //  228:   check Inst[31:26] == 0x4
  OPC_Decode, 237, 8, 148, 2,                //  232:   decode to EVNOR using decoder 276
                                             //  232:  }
  1, 9,                                      //  237:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  //  239:   check Inst[31:26] == 0x4
  OPC_Decode, 224, 7, 148, 2,                //  243:   decode to EVEQV using decoder 276
                                             //  243:  }
  3, 9,                                      //  248:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  //  250:   check Inst[31:26] == 0x4
  OPC_Decode, 239, 8, 148, 2,                //  254:   decode to EVORC using decoder 276
                                             //  254:  }
  6, 0,                                      //  259:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  //  261:   check Inst[31:26] == 0x4
  OPC_Decode, 235, 8, 148, 2,                //  265:   decode to EVNAND using decoder 276
                                             //  265:  }
                                             //  265:  } // switch Inst[2:0]
                                             //  265: }
  68, 69,                                    //  270: case 0x44: {
  OPC_SwitchField, 0, 3,                     //  272:  switch Inst[2:0] {
  0, 9,                                      //  275:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  //  277:   check Inst[31:26] == 0x4
  OPC_Decode, 251, 8, 148, 2,                //  281:   decode to EVSRWU using decoder 276
                                             //  281:  }
  1, 9,                                      //  286:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  //  288:   check Inst[31:26] == 0x4
  OPC_Decode, 250, 8, 148, 2,                //  292:   decode to EVSRWS using decoder 276
                                             //  292:  }
  2, 9,                                      //  297:  case 0x2: {
  OPC_CheckField, 26, 6, 4,                  //  299:   check Inst[31:26] == 0x4
  OPC_Decode, 249, 8, 149, 2,                //  303:   decode to EVSRWIU using decoder 277
                                             //  303:  }
  3, 9,                                      //  308:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  //  310:   check Inst[31:26] == 0x4
  OPC_Decode, 248, 8, 149, 2,                //  314:   decode to EVSRWIS using decoder 277
                                             //  314:  }
  4, 9,                                      //  319:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  //  321:   check Inst[31:26] == 0x4
  OPC_Decode, 244, 8, 148, 2,                //  325:   decode to EVSLW using decoder 276
                                             //  325:  }
  6, 0,                                      //  330:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  //  332:   check Inst[31:26] == 0x4
  OPC_Decode, 245, 8, 149, 2,                //  336:   decode to EVSLWI using decoder 277
                                             //  336:  }
                                             //  336:  } // switch Inst[2:0]
                                             //  336: }
  69, 99,                                    //  341: case 0x45: {
  OPC_SwitchField, 0, 3,                     //  343:  switch Inst[2:0] {
  0, 9,                                      //  346:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  //  348:   check Inst[31:26] == 0x4
  OPC_Decode, 240, 8, 148, 2,                //  352:   decode to EVRLW using decoder 276
                                             //  352:  }
  1, 13,                                     //  357:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  //  359:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  //  363:   check Inst[15:11] == 0x0
  OPC_Decode, 247, 8, 152, 2,                //  367:   decode to EVSPLATI using decoder 280
                                             //  367:  }
  2, 9,                                      //  372:  case 0x2: {
  OPC_CheckField, 26, 6, 4,                  //  374:   check Inst[31:26] == 0x4
  OPC_Decode, 241, 8, 149, 2,                //  378:   decode to EVRLWI using decoder 277
                                             //  378:  }
  3, 13,                                     //  383:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  //  385:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  //  389:   check Inst[15:11] == 0x0
  OPC_Decode, 246, 8, 152, 2,                //  393:   decode to EVSPLATFI using decoder 280
                                             //  393:  }
  4, 9,                                      //  398:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  //  400:   check Inst[31:26] == 0x4
  OPC_Decode, 144, 8, 148, 2,                //  404:   decode to EVMERGEHI using decoder 276
                                             //  404:  }
  5, 9,                                      //  409:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  //  411:   check Inst[31:26] == 0x4
  OPC_Decode, 146, 8, 153, 2,                //  415:   decode to EVMERGELO using decoder 281
                                             //  415:  }
  6, 9,                                      //  420:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  //  422:   check Inst[31:26] == 0x4
  OPC_Decode, 145, 8, 148, 2,                //  426:   decode to EVMERGEHILO using decoder 276
                                             //  426:  }
  7, 0,                                      //  431:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  //  433:   check Inst[31:26] == 0x4
  OPC_Decode, 147, 8, 148, 2,                //  437:   decode to EVMERGELOHI using decoder 276
                                             //  437:  }
                                             //  437:  } // switch Inst[2:0]
                                             //  437: }
  70, 78,                                    //  442: case 0x46: {
  OPC_SwitchField, 0, 3,                     //  444:  switch Inst[2:0] {
  0, 13,                                     //  447:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  //  449:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  //  453:   check Inst[22:21] == 0x0
  OPC_Decode, 217, 7, 154, 2,                //  457:   decode to EVCMPGTU using decoder 282
                                             //  457:  }
  1, 13,                                     //  462:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  //  464:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  //  468:   check Inst[22:21] == 0x0
  OPC_Decode, 216, 7, 154, 2,                //  472:   decode to EVCMPGTS using decoder 282
                                             //  472:  }
  2, 13,                                     //  477:  case 0x2: {
  OPC_CheckField, 26, 6, 4,                  //  479:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  //  483:   check Inst[22:21] == 0x0
  OPC_Decode, 219, 7, 154, 2,                //  487:   decode to EVCMPLTU using decoder 282
                                             //  487:  }
  3, 13,                                     //  492:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  //  494:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  //  498:   check Inst[22:21] == 0x0
  OPC_Decode, 218, 7, 154, 2,                //  502:   decode to EVCMPLTS using decoder 282
                                             //  502:  }
  4, 0,                                      //  507:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  //  509:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  //  513:   check Inst[22:21] == 0x0
  OPC_Decode, 215, 7, 154, 2,                //  517:   decode to EVCMPEQ using decoder 282
                                             //  517:  }
                                             //  517:  } // switch Inst[2:0]
                                             //  517: }
  79, 9,                                     //  522: case 0x4f: {
  OPC_CheckField, 26, 6, 4,                  //  524:  check Inst[31:26] == 0x4
  OPC_Decode, 243, 8, 155, 2,                //  528:  decode to EVSEL using decoder 283
                                             //  528: }
  80, 70,                                    //  533: case 0x50: {
  OPC_SwitchField, 0, 3,                     //  535:  switch Inst[2:0] {
  0, 9,                                      //  538:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  //  540:   check Inst[31:26] == 0x4
  OPC_Decode, 228, 7, 148, 2,                //  544:   decode to EVFSADD using decoder 276
                                             //  544:  }
  1, 9,                                      //  549:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  //  551:   check Inst[31:26] == 0x4
  OPC_Decode, 246, 7, 148, 2,                //  555:   decode to EVFSSUB using decoder 276
                                             //  555:  }
  4, 13,                                     //  560:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  //  562:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  //  566:   check Inst[15:11] == 0x0
  OPC_Decode, 227, 7, 151, 2,                //  570:   decode to EVFSABS using decoder 279
                                             //  570:  }
  5, 13,                                     //  575:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  //  577:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  //  581:   check Inst[15:11] == 0x0
  OPC_Decode, 244, 7, 151, 2,                //  585:   decode to EVFSNABS using decoder 279
                                             //  585:  }
  6, 0,                                      //  590:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  //  592:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  //  596:   check Inst[15:11] == 0x0
  OPC_Decode, 245, 7, 151, 2,                //  600:   decode to EVFSNEG using decoder 279
                                             //  600:  }
                                             //  600:  } // switch Inst[2:0]
                                             //  600: }
  81, 85,                                    //  605: case 0x51: {
  OPC_SwitchField, 0, 3,                     //  607:  switch Inst[2:0] {
  0, 9,                                      //  610:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  //  612:   check Inst[31:26] == 0x4
  OPC_Decode, 243, 7, 148, 2,                //  616:   decode to EVFSMUL using decoder 276
                                             //  616:  }
  1, 9,                                      //  621:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  //  623:   check Inst[31:26] == 0x4
  OPC_Decode, 242, 7, 148, 2,                //  627:   decode to EVFSDIV using decoder 276
                                             //  627:  }
  2, 13,                                     //  632:  case 0x2: {
  OPC_CheckField, 26, 6, 4,                  //  634:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  //  638:   check Inst[20:16] == 0x0
  OPC_Decode, 232, 7, 156, 2,                //  642:   decode to EVFSCFUI using decoder 284
                                             //  642:  }
  4, 13,                                     //  647:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  //  649:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  //  653:   check Inst[22:21] == 0x0
  OPC_Decode, 234, 7, 154, 2,                //  657:   decode to EVFSCMPGT using decoder 282
                                             //  657:  }
  5, 13,                                     //  662:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  //  664:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  //  668:   check Inst[22:21] == 0x0
  OPC_Decode, 235, 7, 154, 2,                //  672:   decode to EVFSCMPLT using decoder 282
                                             //  672:  }
  6, 0,                                      //  677:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  //  679:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  //  683:   check Inst[22:21] == 0x0
  OPC_Decode, 233, 7, 154, 2,                //  687:   decode to EVFSCMPEQ using decoder 282
                                             //  687:  }
                                             //  687:  } // switch Inst[2:0]
                                             //  687: }
  82, 108,                                   //  692: case 0x52: {
  OPC_SwitchField, 0, 3,                     //  694:  switch Inst[2:0] {
  1, 13,                                     //  697:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  //  699:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  //  703:   check Inst[20:16] == 0x0
  OPC_Decode, 230, 7, 156, 2,                //  707:   decode to EVFSCFSI using decoder 284
                                             //  707:  }
  2, 13,                                     //  712:  case 0x2: {
  OPC_CheckField, 26, 6, 4,                  //  714:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  //  718:   check Inst[20:16] == 0x0
  OPC_Decode, 231, 7, 156, 2,                //  722:   decode to EVFSCFUF using decoder 284
                                             //  722:  }
  3, 13,                                     //  727:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  //  729:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  //  733:   check Inst[20:16] == 0x0
  OPC_Decode, 229, 7, 156, 2,                //  737:   decode to EVFSCFSF using decoder 284
                                             //  737:  }
  4, 13,                                     //  742:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  //  744:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  //  748:   check Inst[20:16] == 0x0
  OPC_Decode, 240, 7, 156, 2,                //  752:   decode to EVFSCTUI using decoder 284
                                             //  752:  }
  5, 13,                                     //  757:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  //  759:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  //  763:   check Inst[20:16] == 0x0
  OPC_Decode, 237, 7, 156, 2,                //  767:   decode to EVFSCTSI using decoder 284
                                             //  767:  }
  6, 13,                                     //  772:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  //  774:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  //  778:   check Inst[20:16] == 0x0
  OPC_Decode, 239, 7, 156, 2,                //  782:   decode to EVFSCTUF using decoder 284
                                             //  782:  }
  7, 0,                                      //  787:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  //  789:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  //  793:   check Inst[20:16] == 0x0
  OPC_Decode, 236, 7, 156, 2,                //  797:   decode to EVFSCTSF using decoder 284
                                             //  797:  }
                                             //  797:  } // switch Inst[2:0]
                                             //  797: }
  83, 78,                                    //  802: case 0x53: {
  OPC_SwitchField, 0, 3,                     //  804:  switch Inst[2:0] {
  0, 13,                                     //  807:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  //  809:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  //  813:   check Inst[20:16] == 0x0
  OPC_Decode, 241, 7, 156, 2,                //  817:   decode to EVFSCTUIZ using decoder 284
                                             //  817:  }
  2, 13,                                     //  822:  case 0x2: {
  OPC_CheckField, 26, 6, 4,                  //  824:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  //  828:   check Inst[20:16] == 0x0
  OPC_Decode, 238, 7, 156, 2,                //  832:   decode to EVFSCTSIZ using decoder 284
                                             //  832:  }
  4, 13,                                     //  837:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  //  839:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  //  843:   check Inst[22:21] == 0x0
  OPC_Decode, 248, 7, 154, 2,                //  847:   decode to EVFSTSTGT using decoder 282
                                             //  847:  }
  5, 13,                                     //  852:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  //  854:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  //  858:   check Inst[22:21] == 0x0
  OPC_Decode, 249, 7, 154, 2,                //  862:   decode to EVFSTSTLT using decoder 282
                                             //  862:  }
  6, 0,                                      //  867:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  //  869:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  //  873:   check Inst[22:21] == 0x0
  OPC_Decode, 247, 7, 154, 2,                //  877:   decode to EVFSTSTEQ using decoder 282
                                             //  877:  }
                                             //  877:  } // switch Inst[2:0]
                                             //  877: }
  88, 65,                                    //  882: case 0x58: {
  OPC_SwitchField, 0, 3,                     //  884:  switch Inst[2:0] {
  0, 8,                                      //  887:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  //  889:   check Inst[31:26] == 0x4
  OPC_Decode, 174, 7, 81,                    //  893:   decode to EFSADD using decoder 81
                                             //  893:  }
  1, 8,                                      //  897:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  //  899:   check Inst[31:26] == 0x4
  OPC_Decode, 193, 7, 81,                    //  903:   decode to EFSSUB using decoder 81
                                             //  903:  }
  4, 12,                                     //  907:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  //  909:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  //  913:   check Inst[15:11] == 0x0
  OPC_Decode, 173, 7, 84,                    //  917:   decode to EFSABS using decoder 84
                                             //  917:  }
  5, 12,                                     //  921:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  //  923:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  //  927:   check Inst[15:11] == 0x0
  OPC_Decode, 191, 7, 84,                    //  931:   decode to EFSNABS using decoder 84
                                             //  931:  }
  6, 0,                                      //  935:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  //  937:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  //  941:   check Inst[15:11] == 0x0
  OPC_Decode, 192, 7, 84,                    //  945:   decode to EFSNEG using decoder 84
                                             //  945:  }
                                             //  945:  } // switch Inst[2:0]
                                             //  945: }
  89, 80,                                    //  949: case 0x59: {
  OPC_SwitchField, 0, 3,                     //  951:  switch Inst[2:0] {
  0, 8,                                      //  954:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  //  956:   check Inst[31:26] == 0x4
  OPC_Decode, 190, 7, 81,                    //  960:   decode to EFSMUL using decoder 81
                                             //  960:  }
  1, 8,                                      //  964:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  //  966:   check Inst[31:26] == 0x4
  OPC_Decode, 189, 7, 81,                    //  970:   decode to EFSDIV using decoder 81
                                             //  970:  }
  4, 12,                                     //  974:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  //  976:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  //  980:   check Inst[22:21] == 0x0
  OPC_Decode, 181, 7, 63,                    //  984:   decode to EFSCMPGT using decoder 63
                                             //  984:  }
  5, 12,                                     //  988:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  //  990:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  //  994:   check Inst[22:21] == 0x0
  OPC_Decode, 182, 7, 63,                    //  998:   decode to EFSCMPLT using decoder 63
                                             //  998:  }
  6, 12,                                     // 1002:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  // 1004:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  // 1008:   check Inst[22:21] == 0x0
  OPC_Decode, 180, 7, 63,                    // 1012:   decode to EFSCMPEQ using decoder 63
                                             // 1012:  }
  7, 0,                                      // 1016:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  // 1018:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1022:   check Inst[20:16] == 0x0
  OPC_Decode, 175, 7, 157, 2,                // 1026:   decode to EFSCFD using decoder 285
                                             // 1026:  }
                                             // 1026:  } // switch Inst[2:0]
                                             // 1026: }
  90, 116,                                   // 1031: case 0x5a: {
  OPC_SwitchField, 0, 3,                     // 1033:  switch Inst[2:0] {
  0, 12,                                     // 1036:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 1038:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1042:   check Inst[20:16] == 0x0
  OPC_Decode, 179, 7, 118,                   // 1046:   decode to EFSCFUI using decoder 118
                                             // 1046:  }
  1, 12,                                     // 1050:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 1052:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1056:   check Inst[20:16] == 0x0
  OPC_Decode, 177, 7, 118,                   // 1060:   decode to EFSCFSI using decoder 118
                                             // 1060:  }
  2, 12,                                     // 1064:  case 0x2: {
  OPC_CheckField, 26, 6, 4,                  // 1066:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1070:   check Inst[20:16] == 0x0
  OPC_Decode, 178, 7, 118,                   // 1074:   decode to EFSCFUF using decoder 118
                                             // 1074:  }
  3, 12,                                     // 1078:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 1080:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1084:   check Inst[20:16] == 0x0
  OPC_Decode, 176, 7, 118,                   // 1088:   decode to EFSCFSF using decoder 118
                                             // 1088:  }
  4, 12,                                     // 1092:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 1094:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1098:   check Inst[20:16] == 0x0
  OPC_Decode, 187, 7, 118,                   // 1102:   decode to EFSCTUI using decoder 118
                                             // 1102:  }
  5, 12,                                     // 1106:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 1108:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1112:   check Inst[20:16] == 0x0
  OPC_Decode, 184, 7, 118,                   // 1116:   decode to EFSCTSI using decoder 118
                                             // 1116:  }
  6, 13,                                     // 1120:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  // 1122:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1126:   check Inst[20:16] == 0x0
  OPC_Decode, 186, 7, 158, 2,                // 1130:   decode to EFSCTUF using decoder 286
                                             // 1130:  }
  7, 0,                                      // 1135:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  // 1137:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1141:   check Inst[20:16] == 0x0
  OPC_Decode, 183, 7, 118,                   // 1145:   decode to EFSCTSF using decoder 118
                                             // 1145:  }
                                             // 1145:  } // switch Inst[2:0]
                                             // 1145: }
  91, 76,                                    // 1149: case 0x5b: {
  OPC_SwitchField, 0, 3,                     // 1151:  switch Inst[2:0] {
  0, 12,                                     // 1154:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 1156:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1160:   check Inst[20:16] == 0x0
  OPC_Decode, 188, 7, 118,                   // 1164:   decode to EFSCTUIZ using decoder 118
                                             // 1164:  }
  2, 12,                                     // 1168:  case 0x2: {
  OPC_CheckField, 26, 6, 4,                  // 1170:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1174:   check Inst[20:16] == 0x0
  OPC_Decode, 185, 7, 118,                   // 1178:   decode to EFSCTSIZ using decoder 118
                                             // 1178:  }
  4, 13,                                     // 1182:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 1184:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  // 1188:   check Inst[22:21] == 0x0
  OPC_Decode, 195, 7, 154, 2,                // 1192:   decode to EFSTSTGT using decoder 282
                                             // 1192:  }
  5, 13,                                     // 1197:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 1199:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  // 1203:   check Inst[22:21] == 0x0
  OPC_Decode, 196, 7, 154, 2,                // 1207:   decode to EFSTSTLT using decoder 282
                                             // 1207:  }
  6, 0,                                      // 1212:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  // 1214:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  // 1218:   check Inst[22:21] == 0x0
  OPC_Decode, 194, 7, 154, 2,                // 1222:   decode to EFSTSTEQ using decoder 282
                                             // 1222:  }
                                             // 1222:  } // switch Inst[2:0]
                                             // 1222: }
  92, 100,                                   // 1227: case 0x5c: {
  OPC_SwitchField, 0, 3,                     // 1229:  switch Inst[2:0] {
  0, 9,                                      // 1232:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 1234:   check Inst[31:26] == 0x4
  OPC_Decode, 146, 7, 148, 2,                // 1238:   decode to EFDADD using decoder 276
                                             // 1238:  }
  1, 9,                                      // 1243:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 1245:   check Inst[31:26] == 0x4
  OPC_Decode, 169, 7, 148, 2,                // 1249:   decode to EFDSUB using decoder 276
                                             // 1249:  }
  2, 13,                                     // 1254:  case 0x2: {
  OPC_CheckField, 26, 6, 4,                  // 1256:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1260:   check Inst[20:16] == 0x0
  OPC_Decode, 153, 7, 158, 2,                // 1264:   decode to EFDCFUID using decoder 286
                                             // 1264:  }
  3, 13,                                     // 1269:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 1271:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1275:   check Inst[20:16] == 0x0
  OPC_Decode, 150, 7, 158, 2,                // 1279:   decode to EFDCFSID using decoder 286
                                             // 1279:  }
  4, 13,                                     // 1284:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 1286:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  // 1290:   check Inst[15:11] == 0x0
  OPC_Decode, 145, 7, 151, 2,                // 1294:   decode to EFDABS using decoder 279
                                             // 1294:  }
  5, 13,                                     // 1299:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 1301:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  // 1305:   check Inst[15:11] == 0x0
  OPC_Decode, 167, 7, 151, 2,                // 1309:   decode to EFDNABS using decoder 279
                                             // 1309:  }
  6, 0,                                      // 1314:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  // 1316:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  // 1320:   check Inst[15:11] == 0x0
  OPC_Decode, 168, 7, 151, 2,                // 1324:   decode to EFDNEG using decoder 279
                                             // 1324:  }
                                             // 1324:  } // switch Inst[2:0]
                                             // 1324: }
  93, 115,                                   // 1329: case 0x5d: {
  OPC_SwitchField, 0, 3,                     // 1331:  switch Inst[2:0] {
  0, 9,                                      // 1334:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 1336:   check Inst[31:26] == 0x4
  OPC_Decode, 166, 7, 148, 2,                // 1340:   decode to EFDMUL using decoder 276
                                             // 1340:  }
  1, 9,                                      // 1345:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 1347:   check Inst[31:26] == 0x4
  OPC_Decode, 165, 7, 148, 2,                // 1351:   decode to EFDDIV using decoder 276
                                             // 1351:  }
  2, 13,                                     // 1356:  case 0x2: {
  OPC_CheckField, 26, 6, 4,                  // 1358:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1362:   check Inst[20:16] == 0x0
  OPC_Decode, 163, 7, 157, 2,                // 1366:   decode to EFDCTUIDZ using decoder 285
                                             // 1366:  }
  3, 13,                                     // 1371:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 1373:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1377:   check Inst[20:16] == 0x0
  OPC_Decode, 159, 7, 157, 2,                // 1381:   decode to EFDCTSIDZ using decoder 285
                                             // 1381:  }
  4, 13,                                     // 1386:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 1388:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  // 1392:   check Inst[22:21] == 0x0
  OPC_Decode, 155, 7, 154, 2,                // 1396:   decode to EFDCMPGT using decoder 282
                                             // 1396:  }
  5, 13,                                     // 1401:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 1403:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  // 1407:   check Inst[22:21] == 0x0
  OPC_Decode, 156, 7, 154, 2,                // 1411:   decode to EFDCMPLT using decoder 282
                                             // 1411:  }
  6, 13,                                     // 1416:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  // 1418:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  // 1422:   check Inst[22:21] == 0x0
  OPC_Decode, 154, 7, 154, 2,                // 1426:   decode to EFDCMPEQ using decoder 282
                                             // 1426:  }
  7, 0,                                      // 1431:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  // 1433:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1437:   check Inst[20:16] == 0x0
  OPC_Decode, 147, 7, 158, 2,                // 1441:   decode to EFDCFS using decoder 286
                                             // 1441:  }
                                             // 1441:  } // switch Inst[2:0]
                                             // 1441: }
  94, 123,                                   // 1446: case 0x5e: {
  OPC_SwitchField, 0, 3,                     // 1448:  switch Inst[2:0] {
  0, 13,                                     // 1451:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 1453:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1457:   check Inst[20:16] == 0x0
  OPC_Decode, 152, 7, 158, 2,                // 1461:   decode to EFDCFUI using decoder 286
                                             // 1461:  }
  1, 13,                                     // 1466:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 1468:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1472:   check Inst[20:16] == 0x0
  OPC_Decode, 149, 7, 158, 2,                // 1476:   decode to EFDCFSI using decoder 286
                                             // 1476:  }
  2, 13,                                     // 1481:  case 0x2: {
  OPC_CheckField, 26, 6, 4,                  // 1483:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1487:   check Inst[20:16] == 0x0
  OPC_Decode, 151, 7, 158, 2,                // 1491:   decode to EFDCFUF using decoder 286
                                             // 1491:  }
  3, 13,                                     // 1496:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 1498:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1502:   check Inst[20:16] == 0x0
  OPC_Decode, 148, 7, 158, 2,                // 1506:   decode to EFDCFSF using decoder 286
                                             // 1506:  }
  4, 13,                                     // 1511:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 1513:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1517:   check Inst[20:16] == 0x0
  OPC_Decode, 162, 7, 157, 2,                // 1521:   decode to EFDCTUI using decoder 285
                                             // 1521:  }
  5, 13,                                     // 1526:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 1528:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1532:   check Inst[20:16] == 0x0
  OPC_Decode, 158, 7, 157, 2,                // 1536:   decode to EFDCTSI using decoder 285
                                             // 1536:  }
  6, 13,                                     // 1541:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  // 1543:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1547:   check Inst[20:16] == 0x0
  OPC_Decode, 161, 7, 158, 2,                // 1551:   decode to EFDCTUF using decoder 286
                                             // 1551:  }
  7, 0,                                      // 1556:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  // 1558:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1562:   check Inst[20:16] == 0x0
  OPC_Decode, 157, 7, 158, 2,                // 1566:   decode to EFDCTSF using decoder 286
                                             // 1566:  }
                                             // 1566:  } // switch Inst[2:0]
                                             // 1566: }
  95, 78,                                    // 1571: case 0x5f: {
  OPC_SwitchField, 0, 3,                     // 1573:  switch Inst[2:0] {
  0, 13,                                     // 1576:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 1578:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1582:   check Inst[20:16] == 0x0
  OPC_Decode, 164, 7, 157, 2,                // 1586:   decode to EFDCTUIZ using decoder 285
                                             // 1586:  }
  2, 13,                                     // 1591:  case 0x2: {
  OPC_CheckField, 26, 6, 4,                  // 1593:   check Inst[31:26] == 0x4
  OPC_CheckField, 16, 5, 0,                  // 1597:   check Inst[20:16] == 0x0
  OPC_Decode, 160, 7, 157, 2,                // 1601:   decode to EFDCTSIZ using decoder 285
                                             // 1601:  }
  4, 13,                                     // 1606:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 1608:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  // 1612:   check Inst[22:21] == 0x0
  OPC_Decode, 171, 7, 154, 2,                // 1616:   decode to EFDTSTGT using decoder 282
                                             // 1616:  }
  5, 13,                                     // 1621:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 1623:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  // 1627:   check Inst[22:21] == 0x0
  OPC_Decode, 172, 7, 154, 2,                // 1631:   decode to EFDTSTLT using decoder 282
                                             // 1631:  }
  6, 0,                                      // 1636:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  // 1638:   check Inst[31:26] == 0x4
  OPC_CheckField, 21, 2, 0,                  // 1642:   check Inst[22:21] == 0x0
  OPC_Decode, 170, 7, 154, 2,                // 1646:   decode to EFDTSTEQ using decoder 282
                                             // 1646:  }
                                             // 1646:  } // switch Inst[2:0]
                                             // 1646: }
  96, 69,                                    // 1651: case 0x60: {
  OPC_SwitchField, 0, 3,                     // 1653:  switch Inst[2:0] {
  0, 9,                                      // 1656:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 1658:   check Inst[31:26] == 0x4
  OPC_Decode, 251, 7, 159, 2,                // 1662:   decode to EVLDDX using decoder 287
                                             // 1662:  }
  1, 9,                                      // 1667:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 1669:   check Inst[31:26] == 0x4
  OPC_Decode, 250, 7, 160, 2,                // 1673:   decode to EVLDD using decoder 288
                                             // 1673:  }
  2, 9,                                      // 1678:  case 0x2: {
  OPC_CheckField, 26, 6, 4,                  // 1680:   check Inst[31:26] == 0x4
  OPC_Decode, 255, 7, 159, 2,                // 1684:   decode to EVLDWX using decoder 287
                                             // 1684:  }
  3, 9,                                      // 1689:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 1691:   check Inst[31:26] == 0x4
  OPC_Decode, 254, 7, 160, 2,                // 1695:   decode to EVLDW using decoder 288
                                             // 1695:  }
  4, 9,                                      // 1700:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 1702:   check Inst[31:26] == 0x4
  OPC_Decode, 253, 7, 159, 2,                // 1706:   decode to EVLDHX using decoder 287
                                             // 1706:  }
  5, 0,                                      // 1711:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 1713:   check Inst[31:26] == 0x4
  OPC_Decode, 252, 7, 160, 2,                // 1717:   decode to EVLDH using decoder 288
                                             // 1717:  }
                                             // 1717:  } // switch Inst[2:0]
                                             // 1717: }
  97, 69,                                    // 1722: case 0x61: {
  OPC_SwitchField, 0, 3,                     // 1724:  switch Inst[2:0] {
  0, 9,                                      // 1727:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 1729:   check Inst[31:26] == 0x4
  OPC_Decode, 129, 8, 159, 2,                // 1733:   decode to EVLHHESPLATX using decoder 287
                                             // 1733:  }
  1, 9,                                      // 1738:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 1740:   check Inst[31:26] == 0x4
  OPC_Decode, 128, 8, 161, 2,                // 1744:   decode to EVLHHESPLAT using decoder 289
                                             // 1744:  }
  4, 9,                                      // 1749:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 1751:   check Inst[31:26] == 0x4
  OPC_Decode, 133, 8, 159, 2,                // 1755:   decode to EVLHHOUSPLATX using decoder 287
                                             // 1755:  }
  5, 9,                                      // 1760:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 1762:   check Inst[31:26] == 0x4
  OPC_Decode, 132, 8, 161, 2,                // 1766:   decode to EVLHHOUSPLAT using decoder 289
                                             // 1766:  }
  6, 9,                                      // 1771:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  // 1773:   check Inst[31:26] == 0x4
  OPC_Decode, 131, 8, 159, 2,                // 1777:   decode to EVLHHOSSPLATX using decoder 287
                                             // 1777:  }
  7, 0,                                      // 1782:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  // 1784:   check Inst[31:26] == 0x4
  OPC_Decode, 130, 8, 161, 2,                // 1788:   decode to EVLHHOSSPLAT using decoder 289
                                             // 1788:  }
                                             // 1788:  } // switch Inst[2:0]
                                             // 1788: }
  98, 69,                                    // 1793: case 0x62: {
  OPC_SwitchField, 0, 3,                     // 1795:  switch Inst[2:0] {
  0, 9,                                      // 1798:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 1800:   check Inst[31:26] == 0x4
  OPC_Decode, 135, 8, 159, 2,                // 1804:   decode to EVLWHEX using decoder 287
                                             // 1804:  }
  1, 9,                                      // 1809:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 1811:   check Inst[31:26] == 0x4
  OPC_Decode, 134, 8, 162, 2,                // 1815:   decode to EVLWHE using decoder 290
                                             // 1815:  }
  4, 9,                                      // 1820:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 1822:   check Inst[31:26] == 0x4
  OPC_Decode, 139, 8, 159, 2,                // 1826:   decode to EVLWHOUX using decoder 287
                                             // 1826:  }
  5, 9,                                      // 1831:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 1833:   check Inst[31:26] == 0x4
  OPC_Decode, 138, 8, 162, 2,                // 1837:   decode to EVLWHOU using decoder 290
                                             // 1837:  }
  6, 9,                                      // 1842:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  // 1844:   check Inst[31:26] == 0x4
  OPC_Decode, 137, 8, 159, 2,                // 1848:   decode to EVLWHOSX using decoder 287
                                             // 1848:  }
  7, 0,                                      // 1853:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  // 1855:   check Inst[31:26] == 0x4
  OPC_Decode, 136, 8, 162, 2,                // 1859:   decode to EVLWHOS using decoder 290
                                             // 1859:  }
                                             // 1859:  } // switch Inst[2:0]
                                             // 1859: }
  99, 47,                                    // 1864: case 0x63: {
  OPC_SwitchField, 0, 3,                     // 1866:  switch Inst[2:0] {
  0, 9,                                      // 1869:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 1871:   check Inst[31:26] == 0x4
  OPC_Decode, 143, 8, 159, 2,                // 1875:   decode to EVLWWSPLATX using decoder 287
                                             // 1875:  }
  1, 9,                                      // 1880:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 1882:   check Inst[31:26] == 0x4
  OPC_Decode, 142, 8, 162, 2,                // 1886:   decode to EVLWWSPLAT using decoder 290
                                             // 1886:  }
  4, 9,                                      // 1891:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 1893:   check Inst[31:26] == 0x4
  OPC_Decode, 141, 8, 159, 2,                // 1897:   decode to EVLWHSPLATX using decoder 287
                                             // 1897:  }
  5, 0,                                      // 1902:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 1904:   check Inst[31:26] == 0x4
  OPC_Decode, 140, 8, 162, 2,                // 1908:   decode to EVLWHSPLAT using decoder 290
                                             // 1908:  }
                                             // 1908:  } // switch Inst[2:0]
                                             // 1908: }
  100, 69,                                   // 1913: case 0x64: {
  OPC_SwitchField, 0, 3,                     // 1915:  switch Inst[2:0] {
  0, 9,                                      // 1918:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 1920:   check Inst[31:26] == 0x4
  OPC_Decode, 253, 8, 159, 2,                // 1924:   decode to EVSTDDX using decoder 287
                                             // 1924:  }
  1, 9,                                      // 1929:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 1931:   check Inst[31:26] == 0x4
  OPC_Decode, 252, 8, 160, 2,                // 1935:   decode to EVSTDD using decoder 288
                                             // 1935:  }
  2, 9,                                      // 1940:  case 0x2: {
  OPC_CheckField, 26, 6, 4,                  // 1942:   check Inst[31:26] == 0x4
  OPC_Decode, 129, 9, 159, 2,                // 1946:   decode to EVSTDWX using decoder 287
                                             // 1946:  }
  3, 9,                                      // 1951:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 1953:   check Inst[31:26] == 0x4
  OPC_Decode, 128, 9, 160, 2,                // 1957:   decode to EVSTDW using decoder 288
                                             // 1957:  }
  4, 9,                                      // 1962:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 1964:   check Inst[31:26] == 0x4
  OPC_Decode, 255, 8, 159, 2,                // 1968:   decode to EVSTDHX using decoder 287
                                             // 1968:  }
  5, 0,                                      // 1973:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 1975:   check Inst[31:26] == 0x4
  OPC_Decode, 254, 8, 160, 2,                // 1979:   decode to EVSTDH using decoder 288
                                             // 1979:  }
                                             // 1979:  } // switch Inst[2:0]
                                             // 1979: }
  102, 47,                                   // 1984: case 0x66: {
  OPC_SwitchField, 0, 3,                     // 1986:  switch Inst[2:0] {
  0, 9,                                      // 1989:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 1991:   check Inst[31:26] == 0x4
  OPC_Decode, 131, 9, 159, 2,                // 1995:   decode to EVSTWHEX using decoder 287
                                             // 1995:  }
  1, 9,                                      // 2000:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 2002:   check Inst[31:26] == 0x4
  OPC_Decode, 130, 9, 162, 2,                // 2006:   decode to EVSTWHE using decoder 290
                                             // 2006:  }
  4, 9,                                      // 2011:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 2013:   check Inst[31:26] == 0x4
  OPC_Decode, 133, 9, 159, 2,                // 2017:   decode to EVSTWHOX using decoder 287
                                             // 2017:  }
  5, 0,                                      // 2022:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 2024:   check Inst[31:26] == 0x4
  OPC_Decode, 132, 9, 162, 2,                // 2028:   decode to EVSTWHO using decoder 290
                                             // 2028:  }
                                             // 2028:  } // switch Inst[2:0]
                                             // 2028: }
  103, 47,                                   // 2033: case 0x67: {
  OPC_SwitchField, 0, 3,                     // 2035:  switch Inst[2:0] {
  0, 9,                                      // 2038:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 2040:   check Inst[31:26] == 0x4
  OPC_Decode, 135, 9, 159, 2,                // 2044:   decode to EVSTWWEX using decoder 287
                                             // 2044:  }
  1, 9,                                      // 2049:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 2051:   check Inst[31:26] == 0x4
  OPC_Decode, 134, 9, 162, 2,                // 2055:   decode to EVSTWWE using decoder 290
                                             // 2055:  }
  4, 9,                                      // 2060:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 2062:   check Inst[31:26] == 0x4
  OPC_Decode, 137, 9, 159, 2,                // 2066:   decode to EVSTWWOX using decoder 287
                                             // 2066:  }
  5, 0,                                      // 2071:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 2073:   check Inst[31:26] == 0x4
  OPC_Decode, 136, 9, 162, 2,                // 2077:   decode to EVSTWWO using decoder 290
                                             // 2077:  }
                                             // 2077:  } // switch Inst[2:0]
                                             // 2077: }
  128, 1, 25,                                // 2082: case 0x80: {
  OPC_SwitchField, 0, 3,                     // 2085:  switch Inst[2:0] {
  3, 9,                                      // 2088:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 2090:   check Inst[31:26] == 0x4
  OPC_Decode, 162, 8, 148, 2,                // 2094:   decode to EVMHESSF using decoder 276
                                             // 2094:  }
  7, 0,                                      // 2099:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  // 2101:   check Inst[31:26] == 0x4
  OPC_Decode, 188, 8, 148, 2,                // 2105:   decode to EVMHOSSF using decoder 276
                                             // 2105:  }
                                             // 2105:  } // switch Inst[2:0]
                                             // 2105: }
  129, 1, 69,                                // 2110: case 0x81: {
  OPC_SwitchField, 0, 3,                     // 2113:  switch Inst[2:0] {
  0, 9,                                      // 2116:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 2118:   check Inst[31:26] == 0x4
  OPC_Decode, 168, 8, 148, 2,                // 2122:   decode to EVMHEUMI using decoder 276
                                             // 2122:  }
  1, 9,                                      // 2127:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 2129:   check Inst[31:26] == 0x4
  OPC_Decode, 158, 8, 148, 2,                // 2133:   decode to EVMHESMI using decoder 276
                                             // 2133:  }
  3, 9,                                      // 2138:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 2140:   check Inst[31:26] == 0x4
  OPC_Decode, 154, 8, 148, 2,                // 2144:   decode to EVMHESMF using decoder 276
                                             // 2144:  }
  4, 9,                                      // 2149:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 2151:   check Inst[31:26] == 0x4
  OPC_Decode, 194, 8, 148, 2,                // 2155:   decode to EVMHOUMI using decoder 276
                                             // 2155:  }
  5, 9,                                      // 2160:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 2162:   check Inst[31:26] == 0x4
  OPC_Decode, 184, 8, 148, 2,                // 2166:   decode to EVMHOSMI using decoder 276
                                             // 2166:  }
  7, 0,                                      // 2171:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  // 2173:   check Inst[31:26] == 0x4
  OPC_Decode, 180, 8, 148, 2,                // 2177:   decode to EVMHOSMF using decoder 276
                                             // 2177:  }
                                             // 2177:  } // switch Inst[2:0]
                                             // 2177: }
  132, 1, 25,                                // 2182: case 0x84: {
  OPC_SwitchField, 0, 3,                     // 2185:  switch Inst[2:0] {
  3, 9,                                      // 2188:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 2190:   check Inst[31:26] == 0x4
  OPC_Decode, 163, 8, 148, 2,                // 2194:   decode to EVMHESSFA using decoder 276
                                             // 2194:  }
  7, 0,                                      // 2199:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  // 2201:   check Inst[31:26] == 0x4
  OPC_Decode, 189, 8, 148, 2,                // 2205:   decode to EVMHOSSFA using decoder 276
                                             // 2205:  }
                                             // 2205:  } // switch Inst[2:0]
                                             // 2205: }
  133, 1, 69,                                // 2210: case 0x85: {
  OPC_SwitchField, 0, 3,                     // 2213:  switch Inst[2:0] {
  0, 9,                                      // 2216:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 2218:   check Inst[31:26] == 0x4
  OPC_Decode, 169, 8, 148, 2,                // 2222:   decode to EVMHEUMIA using decoder 276
                                             // 2222:  }
  1, 9,                                      // 2227:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 2229:   check Inst[31:26] == 0x4
  OPC_Decode, 159, 8, 148, 2,                // 2233:   decode to EVMHESMIA using decoder 276
                                             // 2233:  }
  3, 9,                                      // 2238:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 2240:   check Inst[31:26] == 0x4
  OPC_Decode, 155, 8, 148, 2,                // 2244:   decode to EVMHESMFA using decoder 276
                                             // 2244:  }
  4, 9,                                      // 2249:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 2251:   check Inst[31:26] == 0x4
  OPC_Decode, 195, 8, 148, 2,                // 2255:   decode to EVMHOUMIA using decoder 276
                                             // 2255:  }
  5, 9,                                      // 2260:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 2262:   check Inst[31:26] == 0x4
  OPC_Decode, 185, 8, 148, 2,                // 2266:   decode to EVMHOSMIA using decoder 276
                                             // 2266:  }
  7, 0,                                      // 2271:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  // 2273:   check Inst[31:26] == 0x4
  OPC_Decode, 181, 8, 148, 2,                // 2277:   decode to EVMHOSMFA using decoder 276
                                             // 2277:  }
                                             // 2277:  } // switch Inst[2:0]
                                             // 2277: }
  136, 1, 13,                                // 2282: case 0x88: {
  OPC_CheckField, 26, 6, 4,                  // 2285:  check Inst[31:26] == 0x4
  OPC_CheckField, 0, 3, 7,                   // 2289:  check Inst[2:0] == 0x7
  OPC_Decode, 205, 8, 148, 2,                // 2293:  decode to EVMWHSSF using decoder 276
                                             // 2293: }
  137, 1, 47,                                // 2298: case 0x89: {
  OPC_SwitchField, 0, 3,                     // 2301:  switch Inst[2:0] {
  0, 9,                                      // 2304:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 2306:   check Inst[31:26] == 0x4
  OPC_Decode, 213, 8, 148, 2,                // 2310:   decode to EVMWLUMI using decoder 276
                                             // 2310:  }
  4, 9,                                      // 2315:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 2317:   check Inst[31:26] == 0x4
  OPC_Decode, 207, 8, 148, 2,                // 2321:   decode to EVMWHUMI using decoder 276
                                             // 2321:  }
  5, 9,                                      // 2326:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 2328:   check Inst[31:26] == 0x4
  OPC_Decode, 203, 8, 148, 2,                // 2332:   decode to EVMWHSMI using decoder 276
                                             // 2332:  }
  7, 0,                                      // 2337:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  // 2339:   check Inst[31:26] == 0x4
  OPC_Decode, 201, 8, 148, 2,                // 2343:   decode to EVMWHSMF using decoder 276
                                             // 2343:  }
                                             // 2343:  } // switch Inst[2:0]
                                             // 2343: }
  138, 1, 13,                                // 2348: case 0x8a: {
  OPC_CheckField, 26, 6, 4,                  // 2351:  check Inst[31:26] == 0x4
  OPC_CheckField, 0, 3, 3,                   // 2355:  check Inst[2:0] == 0x3
  OPC_Decode, 227, 8, 148, 2,                // 2359:  decode to EVMWSSF using decoder 276
                                             // 2359: }
  139, 1, 36,                                // 2364: case 0x8b: {
  OPC_SwitchField, 0, 3,                     // 2367:  switch Inst[2:0] {
  0, 9,                                      // 2370:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 2372:   check Inst[31:26] == 0x4
  OPC_Decode, 231, 8, 148, 2,                // 2376:   decode to EVMWUMI using decoder 276
                                             // 2376:  }
  1, 9,                                      // 2381:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 2383:   check Inst[31:26] == 0x4
  OPC_Decode, 223, 8, 148, 2,                // 2387:   decode to EVMWSMI using decoder 276
                                             // 2387:  }
  3, 0,                                      // 2392:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 2394:   check Inst[31:26] == 0x4
  OPC_Decode, 219, 8, 148, 2,                // 2398:   decode to EVMWSMF using decoder 276
                                             // 2398:  }
                                             // 2398:  } // switch Inst[2:0]
                                             // 2398: }
  140, 1, 13,                                // 2403: case 0x8c: {
  OPC_CheckField, 26, 6, 4,                  // 2406:  check Inst[31:26] == 0x4
  OPC_CheckField, 0, 3, 7,                   // 2410:  check Inst[2:0] == 0x7
  OPC_Decode, 206, 8, 148, 2,                // 2414:  decode to EVMWHSSFA using decoder 276
                                             // 2414: }
  141, 1, 47,                                // 2419: case 0x8d: {
  OPC_SwitchField, 0, 3,                     // 2422:  switch Inst[2:0] {
  0, 9,                                      // 2425:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 2427:   check Inst[31:26] == 0x4
  OPC_Decode, 214, 8, 148, 2,                // 2431:   decode to EVMWLUMIA using decoder 276
                                             // 2431:  }
  4, 9,                                      // 2436:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 2438:   check Inst[31:26] == 0x4
  OPC_Decode, 208, 8, 148, 2,                // 2442:   decode to EVMWHUMIA using decoder 276
                                             // 2442:  }
  5, 9,                                      // 2447:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 2449:   check Inst[31:26] == 0x4
  OPC_Decode, 204, 8, 148, 2,                // 2453:   decode to EVMWHSMIA using decoder 276
                                             // 2453:  }
  7, 0,                                      // 2458:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  // 2460:   check Inst[31:26] == 0x4
  OPC_Decode, 202, 8, 148, 2,                // 2464:   decode to EVMWHSMFA using decoder 276
                                             // 2464:  }
                                             // 2464:  } // switch Inst[2:0]
                                             // 2464: }
  142, 1, 13,                                // 2469: case 0x8e: {
  OPC_CheckField, 26, 6, 4,                  // 2472:  check Inst[31:26] == 0x4
  OPC_CheckField, 0, 3, 3,                   // 2476:  check Inst[2:0] == 0x3
  OPC_Decode, 228, 8, 148, 2,                // 2480:  decode to EVMWSSFA using decoder 276
                                             // 2480: }
  143, 1, 36,                                // 2485: case 0x8f: {
  OPC_SwitchField, 0, 3,                     // 2488:  switch Inst[2:0] {
  0, 9,                                      // 2491:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 2493:   check Inst[31:26] == 0x4
  OPC_Decode, 232, 8, 148, 2,                // 2497:   decode to EVMWUMIA using decoder 276
                                             // 2497:  }
  1, 9,                                      // 2502:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 2504:   check Inst[31:26] == 0x4
  OPC_Decode, 224, 8, 148, 2,                // 2508:   decode to EVMWSMIA using decoder 276
                                             // 2508:  }
  3, 0,                                      // 2513:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 2515:   check Inst[31:26] == 0x4
  OPC_Decode, 220, 8, 148, 2,                // 2519:   decode to EVMWSMFA using decoder 276
                                             // 2519:  }
                                             // 2519:  } // switch Inst[2:0]
                                             // 2519: }
  152, 1, 100,                               // 2524: case 0x98: {
  OPC_SwitchField, 0, 3,                     // 2527:  switch Inst[2:0] {
  0, 13,                                     // 2530:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 2532:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  // 2536:   check Inst[15:11] == 0x0
  OPC_Decode, 211, 7, 151, 2,                // 2540:   decode to EVADDUSIAAW using decoder 279
                                             // 2540:  }
  1, 13,                                     // 2545:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 2547:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  // 2551:   check Inst[15:11] == 0x0
  OPC_Decode, 209, 7, 151, 2,                // 2555:   decode to EVADDSSIAAW using decoder 279
                                             // 2555:  }
  2, 13,                                     // 2560:  case 0x2: {
  OPC_CheckField, 26, 6, 4,                  // 2562:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  // 2566:   check Inst[15:11] == 0x0
  OPC_Decode, 141, 9, 151, 2,                // 2570:   decode to EVSUBFUSIAAW using decoder 279
                                             // 2570:  }
  3, 13,                                     // 2575:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 2577:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  // 2581:   check Inst[15:11] == 0x0
  OPC_Decode, 139, 9, 151, 2,                // 2585:   decode to EVSUBFSSIAAW using decoder 279
                                             // 2585:  }
  4, 13,                                     // 2590:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 2592:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  // 2596:   check Inst[15:11] == 0x0
  OPC_Decode, 200, 8, 151, 2,                // 2600:   decode to EVMRA using decoder 279
                                             // 2600:  }
  6, 9,                                      // 2605:  case 0x6: {
  OPC_CheckField, 26, 6, 4,                  // 2607:   check Inst[31:26] == 0x4
  OPC_Decode, 222, 7, 148, 2,                // 2611:   decode to EVDIVWS using decoder 276
                                             // 2611:  }
  7, 0,                                      // 2616:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  // 2618:   check Inst[31:26] == 0x4
  OPC_Decode, 223, 7, 148, 2,                // 2622:   decode to EVDIVWU using decoder 276
                                             // 2622:  }
                                             // 2622:  } // switch Inst[2:0]
                                             // 2622: }
  153, 1, 63,                                // 2627: case 0x99: {
  OPC_SwitchField, 0, 3,                     // 2630:  switch Inst[2:0] {
  0, 13,                                     // 2633:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 2635:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  // 2639:   check Inst[15:11] == 0x0
  OPC_Decode, 210, 7, 151, 2,                // 2643:   decode to EVADDUMIAAW using decoder 279
                                             // 2643:  }
  1, 13,                                     // 2648:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 2650:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  // 2654:   check Inst[15:11] == 0x0
  OPC_Decode, 208, 7, 151, 2,                // 2658:   decode to EVADDSMIAAW using decoder 279
                                             // 2658:  }
  2, 13,                                     // 2663:  case 0x2: {
  OPC_CheckField, 26, 6, 4,                  // 2665:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  // 2669:   check Inst[15:11] == 0x0
  OPC_Decode, 140, 9, 151, 2,                // 2673:   decode to EVSUBFUMIAAW using decoder 279
                                             // 2673:  }
  3, 0,                                      // 2678:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 2680:   check Inst[31:26] == 0x4
  OPC_CheckField, 11, 5, 0,                  // 2684:   check Inst[15:11] == 0x0
  OPC_Decode, 138, 9, 151, 2,                // 2688:   decode to EVSUBFSMIAAW using decoder 279
                                             // 2688:  }
                                             // 2688:  } // switch Inst[2:0]
                                             // 2688: }
  160, 1, 69,                                // 2693: case 0xa0: {
  OPC_SwitchField, 0, 3,                     // 2696:  switch Inst[2:0] {
  0, 9,                                      // 2699:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 2701:   check Inst[31:26] == 0x4
  OPC_Decode, 172, 8, 148, 2,                // 2705:   decode to EVMHEUSIAAW using decoder 276
                                             // 2705:  }
  1, 9,                                      // 2710:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 2712:   check Inst[31:26] == 0x4
  OPC_Decode, 166, 8, 148, 2,                // 2716:   decode to EVMHESSIAAW using decoder 276
                                             // 2716:  }
  3, 9,                                      // 2721:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 2723:   check Inst[31:26] == 0x4
  OPC_Decode, 164, 8, 148, 2,                // 2727:   decode to EVMHESSFAAW using decoder 276
                                             // 2727:  }
  4, 9,                                      // 2732:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 2734:   check Inst[31:26] == 0x4
  OPC_Decode, 198, 8, 148, 2,                // 2738:   decode to EVMHOUSIAAW using decoder 276
                                             // 2738:  }
  5, 9,                                      // 2743:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 2745:   check Inst[31:26] == 0x4
  OPC_Decode, 192, 8, 148, 2,                // 2749:   decode to EVMHOSSIAAW using decoder 276
                                             // 2749:  }
  7, 0,                                      // 2754:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  // 2756:   check Inst[31:26] == 0x4
  OPC_Decode, 190, 8, 148, 2,                // 2760:   decode to EVMHOSSFAAW using decoder 276
                                             // 2760:  }
                                             // 2760:  } // switch Inst[2:0]
                                             // 2760: }
  161, 1, 69,                                // 2765: case 0xa1: {
  OPC_SwitchField, 0, 3,                     // 2768:  switch Inst[2:0] {
  0, 9,                                      // 2771:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 2773:   check Inst[31:26] == 0x4
  OPC_Decode, 170, 8, 148, 2,                // 2777:   decode to EVMHEUMIAAW using decoder 276
                                             // 2777:  }
  1, 9,                                      // 2782:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 2784:   check Inst[31:26] == 0x4
  OPC_Decode, 160, 8, 148, 2,                // 2788:   decode to EVMHESMIAAW using decoder 276
                                             // 2788:  }
  3, 9,                                      // 2793:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 2795:   check Inst[31:26] == 0x4
  OPC_Decode, 156, 8, 148, 2,                // 2799:   decode to EVMHESMFAAW using decoder 276
                                             // 2799:  }
  4, 9,                                      // 2804:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 2806:   check Inst[31:26] == 0x4
  OPC_Decode, 196, 8, 148, 2,                // 2810:   decode to EVMHOUMIAAW using decoder 276
                                             // 2810:  }
  5, 9,                                      // 2815:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 2817:   check Inst[31:26] == 0x4
  OPC_Decode, 186, 8, 148, 2,                // 2821:   decode to EVMHOSMIAAW using decoder 276
                                             // 2821:  }
  7, 0,                                      // 2826:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  // 2828:   check Inst[31:26] == 0x4
  OPC_Decode, 182, 8, 148, 2,                // 2832:   decode to EVMHOSMFAAW using decoder 276
                                             // 2832:  }
                                             // 2832:  } // switch Inst[2:0]
                                             // 2832: }
  165, 1, 69,                                // 2837: case 0xa5: {
  OPC_SwitchField, 0, 3,                     // 2840:  switch Inst[2:0] {
  0, 9,                                      // 2843:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 2845:   check Inst[31:26] == 0x4
  OPC_Decode, 152, 8, 148, 2,                // 2849:   decode to EVMHEGUMIAA using decoder 276
                                             // 2849:  }
  1, 9,                                      // 2854:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 2856:   check Inst[31:26] == 0x4
  OPC_Decode, 150, 8, 148, 2,                // 2860:   decode to EVMHEGSMIAA using decoder 276
                                             // 2860:  }
  3, 9,                                      // 2865:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 2867:   check Inst[31:26] == 0x4
  OPC_Decode, 148, 8, 148, 2,                // 2871:   decode to EVMHEGSMFAA using decoder 276
                                             // 2871:  }
  4, 9,                                      // 2876:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 2878:   check Inst[31:26] == 0x4
  OPC_Decode, 178, 8, 148, 2,                // 2882:   decode to EVMHOGUMIAA using decoder 276
                                             // 2882:  }
  5, 9,                                      // 2887:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 2889:   check Inst[31:26] == 0x4
  OPC_Decode, 176, 8, 148, 2,                // 2893:   decode to EVMHOGSMIAA using decoder 276
                                             // 2893:  }
  7, 0,                                      // 2898:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  // 2900:   check Inst[31:26] == 0x4
  OPC_Decode, 174, 8, 148, 2,                // 2904:   decode to EVMHOGSMFAA using decoder 276
                                             // 2904:  }
                                             // 2904:  } // switch Inst[2:0]
                                             // 2904: }
  168, 1, 25,                                // 2909: case 0xa8: {
  OPC_SwitchField, 0, 3,                     // 2912:  switch Inst[2:0] {
  0, 9,                                      // 2915:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 2917:   check Inst[31:26] == 0x4
  OPC_Decode, 217, 8, 148, 2,                // 2921:   decode to EVMWLUSIAAW using decoder 276
                                             // 2921:  }
  1, 0,                                      // 2926:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 2928:   check Inst[31:26] == 0x4
  OPC_Decode, 211, 8, 148, 2,                // 2932:   decode to EVMWLSSIAAW using decoder 276
                                             // 2932:  }
                                             // 2932:  } // switch Inst[2:0]
                                             // 2932: }
  169, 1, 25,                                // 2937: case 0xa9: {
  OPC_SwitchField, 0, 3,                     // 2940:  switch Inst[2:0] {
  0, 9,                                      // 2943:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 2945:   check Inst[31:26] == 0x4
  OPC_Decode, 215, 8, 148, 2,                // 2949:   decode to EVMWLUMIAAW using decoder 276
                                             // 2949:  }
  1, 0,                                      // 2954:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 2956:   check Inst[31:26] == 0x4
  OPC_Decode, 209, 8, 148, 2,                // 2960:   decode to EVMWLSMIAAW using decoder 276
                                             // 2960:  }
                                             // 2960:  } // switch Inst[2:0]
                                             // 2960: }
  170, 1, 13,                                // 2965: case 0xaa: {
  OPC_CheckField, 26, 6, 4,                  // 2968:  check Inst[31:26] == 0x4
  OPC_CheckField, 0, 3, 3,                   // 2972:  check Inst[2:0] == 0x3
  OPC_Decode, 229, 8, 148, 2,                // 2976:  decode to EVMWSSFAA using decoder 276
                                             // 2976: }
  171, 1, 36,                                // 2981: case 0xab: {
  OPC_SwitchField, 0, 3,                     // 2984:  switch Inst[2:0] {
  0, 9,                                      // 2987:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 2989:   check Inst[31:26] == 0x4
  OPC_Decode, 233, 8, 148, 2,                // 2993:   decode to EVMWUMIAA using decoder 276
                                             // 2993:  }
  1, 9,                                      // 2998:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 3000:   check Inst[31:26] == 0x4
  OPC_Decode, 225, 8, 148, 2,                // 3004:   decode to EVMWSMIAA using decoder 276
                                             // 3004:  }
  3, 0,                                      // 3009:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 3011:   check Inst[31:26] == 0x4
  OPC_Decode, 221, 8, 148, 2,                // 3015:   decode to EVMWSMFAA using decoder 276
                                             // 3015:  }
                                             // 3015:  } // switch Inst[2:0]
                                             // 3015: }
  176, 1, 69,                                // 3020: case 0xb0: {
  OPC_SwitchField, 0, 3,                     // 3023:  switch Inst[2:0] {
  0, 9,                                      // 3026:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 3028:   check Inst[31:26] == 0x4
  OPC_Decode, 173, 8, 148, 2,                // 3032:   decode to EVMHEUSIANW using decoder 276
                                             // 3032:  }
  1, 9,                                      // 3037:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 3039:   check Inst[31:26] == 0x4
  OPC_Decode, 167, 8, 148, 2,                // 3043:   decode to EVMHESSIANW using decoder 276
                                             // 3043:  }
  3, 9,                                      // 3048:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 3050:   check Inst[31:26] == 0x4
  OPC_Decode, 165, 8, 148, 2,                // 3054:   decode to EVMHESSFANW using decoder 276
                                             // 3054:  }
  4, 9,                                      // 3059:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 3061:   check Inst[31:26] == 0x4
  OPC_Decode, 199, 8, 148, 2,                // 3065:   decode to EVMHOUSIANW using decoder 276
                                             // 3065:  }
  5, 9,                                      // 3070:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 3072:   check Inst[31:26] == 0x4
  OPC_Decode, 193, 8, 148, 2,                // 3076:   decode to EVMHOSSIANW using decoder 276
                                             // 3076:  }
  7, 0,                                      // 3081:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  // 3083:   check Inst[31:26] == 0x4
  OPC_Decode, 191, 8, 148, 2,                // 3087:   decode to EVMHOSSFANW using decoder 276
                                             // 3087:  }
                                             // 3087:  } // switch Inst[2:0]
                                             // 3087: }
  177, 1, 69,                                // 3092: case 0xb1: {
  OPC_SwitchField, 0, 3,                     // 3095:  switch Inst[2:0] {
  0, 9,                                      // 3098:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 3100:   check Inst[31:26] == 0x4
  OPC_Decode, 171, 8, 148, 2,                // 3104:   decode to EVMHEUMIANW using decoder 276
                                             // 3104:  }
  1, 9,                                      // 3109:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 3111:   check Inst[31:26] == 0x4
  OPC_Decode, 161, 8, 148, 2,                // 3115:   decode to EVMHESMIANW using decoder 276
                                             // 3115:  }
  3, 9,                                      // 3120:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 3122:   check Inst[31:26] == 0x4
  OPC_Decode, 157, 8, 148, 2,                // 3126:   decode to EVMHESMFANW using decoder 276
                                             // 3126:  }
  4, 9,                                      // 3131:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 3133:   check Inst[31:26] == 0x4
  OPC_Decode, 197, 8, 148, 2,                // 3137:   decode to EVMHOUMIANW using decoder 276
                                             // 3137:  }
  5, 9,                                      // 3142:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 3144:   check Inst[31:26] == 0x4
  OPC_Decode, 187, 8, 148, 2,                // 3148:   decode to EVMHOSMIANW using decoder 276
                                             // 3148:  }
  7, 0,                                      // 3153:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  // 3155:   check Inst[31:26] == 0x4
  OPC_Decode, 183, 8, 148, 2,                // 3159:   decode to EVMHOSMFANW using decoder 276
                                             // 3159:  }
                                             // 3159:  } // switch Inst[2:0]
                                             // 3159: }
  181, 1, 69,                                // 3164: case 0xb5: {
  OPC_SwitchField, 0, 3,                     // 3167:  switch Inst[2:0] {
  0, 9,                                      // 3170:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 3172:   check Inst[31:26] == 0x4
  OPC_Decode, 153, 8, 148, 2,                // 3176:   decode to EVMHEGUMIAN using decoder 276
                                             // 3176:  }
  1, 9,                                      // 3181:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 3183:   check Inst[31:26] == 0x4
  OPC_Decode, 151, 8, 148, 2,                // 3187:   decode to EVMHEGSMIAN using decoder 276
                                             // 3187:  }
  3, 9,                                      // 3192:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 3194:   check Inst[31:26] == 0x4
  OPC_Decode, 149, 8, 148, 2,                // 3198:   decode to EVMHEGSMFAN using decoder 276
                                             // 3198:  }
  4, 9,                                      // 3203:  case 0x4: {
  OPC_CheckField, 26, 6, 4,                  // 3205:   check Inst[31:26] == 0x4
  OPC_Decode, 179, 8, 148, 2,                // 3209:   decode to EVMHOGUMIAN using decoder 276
                                             // 3209:  }
  5, 9,                                      // 3214:  case 0x5: {
  OPC_CheckField, 26, 6, 4,                  // 3216:   check Inst[31:26] == 0x4
  OPC_Decode, 177, 8, 148, 2,                // 3220:   decode to EVMHOGSMIAN using decoder 276
                                             // 3220:  }
  7, 0,                                      // 3225:  case 0x7: {
  OPC_CheckField, 26, 6, 4,                  // 3227:   check Inst[31:26] == 0x4
  OPC_Decode, 175, 8, 148, 2,                // 3231:   decode to EVMHOGSMFAN using decoder 276
                                             // 3231:  }
                                             // 3231:  } // switch Inst[2:0]
                                             // 3231: }
  184, 1, 25,                                // 3236: case 0xb8: {
  OPC_SwitchField, 0, 3,                     // 3239:  switch Inst[2:0] {
  0, 9,                                      // 3242:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 3244:   check Inst[31:26] == 0x4
  OPC_Decode, 218, 8, 148, 2,                // 3248:   decode to EVMWLUSIANW using decoder 276
                                             // 3248:  }
  1, 0,                                      // 3253:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 3255:   check Inst[31:26] == 0x4
  OPC_Decode, 212, 8, 148, 2,                // 3259:   decode to EVMWLSSIANW using decoder 276
                                             // 3259:  }
                                             // 3259:  } // switch Inst[2:0]
                                             // 3259: }
  185, 1, 25,                                // 3264: case 0xb9: {
  OPC_SwitchField, 0, 3,                     // 3267:  switch Inst[2:0] {
  0, 9,                                      // 3270:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 3272:   check Inst[31:26] == 0x4
  OPC_Decode, 216, 8, 148, 2,                // 3276:   decode to EVMWLUMIANW using decoder 276
                                             // 3276:  }
  1, 0,                                      // 3281:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 3283:   check Inst[31:26] == 0x4
  OPC_Decode, 210, 8, 148, 2,                // 3287:   decode to EVMWLSMIANW using decoder 276
                                             // 3287:  }
                                             // 3287:  } // switch Inst[2:0]
                                             // 3287: }
  186, 1, 13,                                // 3292: case 0xba: {
  OPC_CheckField, 26, 6, 4,                  // 3295:  check Inst[31:26] == 0x4
  OPC_CheckField, 0, 3, 3,                   // 3299:  check Inst[2:0] == 0x3
  OPC_Decode, 230, 8, 148, 2,                // 3303:  decode to EVMWSSFAN using decoder 276
                                             // 3303: }
  187, 1, 0,                                 // 3308: case 0xbb: {
  OPC_SwitchField, 0, 3,                     // 3311:  switch Inst[2:0] {
  0, 9,                                      // 3314:  case 0x0: {
  OPC_CheckField, 26, 6, 4,                  // 3316:   check Inst[31:26] == 0x4
  OPC_Decode, 234, 8, 148, 2,                // 3320:   decode to EVMWUMIAN using decoder 276
                                             // 3320:  }
  1, 9,                                      // 3325:  case 0x1: {
  OPC_CheckField, 26, 6, 4,                  // 3327:   check Inst[31:26] == 0x4
  OPC_Decode, 226, 8, 148, 2,                // 3331:   decode to EVMWSMIAN using decoder 276
                                             // 3331:  }
  3, 0,                                      // 3336:  case 0x3: {
  OPC_CheckField, 26, 6, 4,                  // 3338:   check Inst[31:26] == 0x4
  OPC_Decode, 222, 8, 148, 2,                // 3342:   decode to EVMWSMFAN using decoder 276
                                             // 3342:  }
                                             // 3342:  } // switch Inst[2:0]
                                             // 3342: }
                                             // 3342: } // switch Inst[10:3]
};
static const uint8_t DecoderTable64[1965] = {
  OPC_SwitchField, 27, 5,                    //    0: switch Inst[31:27] {
  7, 62,                                     //    3: case 0x7: {
  OPC_SwitchField, 26, 1,                    //    5:  switch Inst[26] {
  0, 30,                                     //    8:  case 0x0: {
  OPC_SwitchField, 50, 14,                   //   10:   switch Inst[63:50] {
  128, 3, 16,                                //   13:   case 0x180: {
  OPC_Scope, 9,                              //   16:    try {
  OPC_CheckField, 16, 5, 0,                  //   18:     check Inst[20:16] == 0x0
  OPC_Decode, 153, 13, 163, 2,               //   22:     decode to PLI using decoder 291
                                             //   22:    } else try {
  OPC_Decode, 230, 12, 164, 2,               //   27:     decode to PADDI using decoder 292
                                             //   27:    }
                                             //   27:   }
  132, 3, 0,                                 //   32:   case 0x184: {
  OPC_Decode, 238, 12, 165, 2,               //   35:    decode to PADDIpc using decoder 293
                                             //   35:   }
                                             //   35:   } // switch Inst[63:50]
                                             //   35:  }
  1, 0,                                      //   40:  case 0x1: {
  OPC_SwitchField, 52, 1,                    //   42:   switch Inst[52] {
  0, 9,                                      //   45:   case 0x0: {
  OPC_CheckField, 55, 9, 12,                 //   47:    check Inst[63:55] == 0xc
  OPC_Decode, 233, 12, 166, 2,               //   51:    decode to PADDIS using decoder 294
                                             //   51:   }
  1, 0,                                      //   56:   case 0x1: {
  OPC_CheckField, 55, 9, 12,                 //   58:    check Inst[63:55] == 0xc
  OPC_Decode, 236, 12, 167, 2,               //   62:    decode to PADDISpc using decoder 295
                                             //   62:   }
                                             //   62:   } // switch Inst[52]
                                             //   62:  }
                                             //   62:  } // switch Inst[26]
                                             //   62: }
  16, 125,                                   //   67: case 0x10: {
  OPC_SwitchField, 50, 14,                   //   69:  switch Inst[63:50] {
  192, 2, 95,                                //   72:  case 0x140: {
  OPC_SwitchField, 26, 1,                    //   75:   switch Inst[26] {
  0, 41,                                     //   78:   case 0x0: {
  OPC_SwitchField, 18, 3,                    //   80:    switch Inst[20:18] {
  0, 9,                                      //   83:    case 0x0: {
  OPC_CheckField, 48, 2, 0,                  //   85:     check Inst[49:48] == 0x0
  OPC_Decode, 159, 23, 168, 2,               //   89:     decode to XXSPLTI32DX using decoder 296
                                             //   89:    }
  1, 0,                                      //   94:    case 0x1: {
  OPC_SwitchField, 17, 1,                    //   96:     switch Inst[17] {
  0, 9,                                      //   99:     case 0x0: {
  OPC_CheckField, 48, 2, 0,                  //  101:      check Inst[49:48] == 0x0
  OPC_Decode, 161, 23, 169, 2,               //  105:      decode to XXSPLTIDP using decoder 297
                                             //  105:     }
  1, 0,                                      //  110:     case 0x1: {
  OPC_CheckField, 48, 2, 0,                  //  112:      check Inst[49:48] == 0x0
  OPC_Decode, 162, 23, 169, 2,               //  116:      decode to XXSPLTIW using decoder 297
                                             //  116:     }
                                             //  116:     } // switch Inst[17]
                                             //  116:    }
                                             //  116:    } // switch Inst[20:18]
                                             //  116:   }
  1, 0,                                      //  121:   case 0x1: {
  OPC_SwitchField, 4, 2,                     //  123:    switch Inst[5:4] {
  0, 9,                                      //  126:    case 0x0: {
  OPC_CheckField, 32, 18, 0,                 //  128:     check Inst[49:32] == 0x0
  OPC_Decode, 240, 22, 237, 1,               //  132:     decode to XXBLENDVB using decoder 237
                                             //  132:    }
  1, 9,                                      //  137:    case 0x1: {
  OPC_CheckField, 32, 18, 0,                 //  139:     check Inst[49:32] == 0x0
  OPC_Decode, 242, 22, 237, 1,               //  143:     decode to XXBLENDVH using decoder 237
                                             //  143:    }
  2, 9,                                      //  148:    case 0x2: {
  OPC_CheckField, 32, 18, 0,                 //  150:     check Inst[49:32] == 0x0
  OPC_Decode, 243, 22, 237, 1,               //  154:     decode to XXBLENDVW using decoder 237
                                             //  154:    }
  3, 0,                                      //  159:    case 0x3: {
  OPC_CheckField, 32, 18, 0,                 //  161:     check Inst[49:32] == 0x0
  OPC_Decode, 241, 22, 237, 1,               //  165:     decode to XXBLENDVD using decoder 237
                                             //  165:    }
                                             //  165:    } // switch Inst[5:4]
                                             //  165:   }
                                             //  165:   } // switch Inst[26]
                                             //  165:  }
  128, 3, 9,                                 //  170:  case 0x180: {
  OPC_CheckField, 26, 1, 0,                  //  173:   check Inst[26] == 0x0
  OPC_Decode, 163, 13, 170, 2,               //  177:   decode to PLWZ using decoder 298
                                             //  177:  }
  132, 3, 0,                                 //  182:  case 0x184: {
  OPC_CheckField, 26, 1, 0,                  //  185:   check Inst[26] == 0x0
  OPC_Decode, 170, 13, 171, 2,               //  189:   decode to PLWZpc using decoder 299
                                             //  189:  }
                                             //  189:  } // switch Inst[63:50]
                                             //  189: }
  17, 84,                                    //  194: case 0x11: {
  OPC_SwitchField, 52, 12,                   //  196:  switch Inst[63:52] {
  80, 49,                                    //  199:  case 0x50: {
  OPC_SwitchField, 5, 1,                     //  201:   switch Inst[5] {
  0, 33,                                     //  204:   case 0x0: {
  OPC_SwitchField, 4, 1,                     //  206:    switch Inst[4] {
  0, 13,                                     //  209:    case 0x0: {
  OPC_CheckField, 35, 17, 0,                 //  211:     check Inst[51:35] == 0x0
  OPC_CheckField, 26, 1, 0,                  //  215:     check Inst[26] == 0x0
  OPC_Decode, 154, 23, 172, 2,               //  219:     decode to XXPERMX using decoder 300
                                             //  219:    }
  1, 0,                                      //  224:    case 0x1: {
  OPC_CheckField, 40, 12, 0,                 //  226:     check Inst[51:40] == 0x0
  OPC_CheckField, 26, 1, 0,                  //  230:     check Inst[26] == 0x0
  OPC_Decode, 248, 22, 173, 2,               //  234:     decode to XXEVAL using decoder 301
                                             //  234:    }
                                             //  234:    } // switch Inst[4]
                                             //  234:   }
  1, 0,                                      //  239:   case 0x1: {
  OPC_CheckField, 26, 1, 0,                  //  241:    check Inst[26] == 0x0
  OPC_Decode, 167, 23, 174, 2,               //  245:    decode to XXSSUMUDMCEXT using decoder 302
                                             //  245:   }
                                             //  245:   } // switch Inst[5]
                                             //  245:  }
  96, 13,                                    //  250:  case 0x60: {
  OPC_CheckField, 50, 2, 0,                  //  252:   check Inst[51:50] == 0x0
  OPC_CheckField, 26, 1, 0,                  //  256:   check Inst[26] == 0x0
  OPC_Decode, 245, 12, 170, 2,               //  260:   decode to PLBZ using decoder 298
                                             //  260:  }
  97, 0,                                     //  265:  case 0x61: {
  OPC_CheckField, 50, 2, 0,                  //  267:   check Inst[51:50] == 0x0
  OPC_CheckField, 26, 1, 0,                  //  271:   check Inst[26] == 0x0
  OPC_Decode, 252, 12, 171, 2,               //  275:   decode to PLBZpc using decoder 299
                                             //  275:  }
                                             //  275:  } // switch Inst[63:52]
                                             //  275: }
  18, 27,                                    //  280: case 0x12: {
  OPC_SwitchField, 50, 14,                   //  282:  switch Inst[63:50] {
  128, 3, 9,                                 //  285:  case 0x180: {
  OPC_CheckField, 26, 1, 0,                  //  288:   check Inst[26] == 0x0
  OPC_Decode, 172, 14, 170, 2,               //  292:   decode to PSTW using decoder 298
                                             //  292:  }
  132, 3, 0,                                 //  297:  case 0x184: {
  OPC_CheckField, 26, 1, 0,                  //  300:   check Inst[26] == 0x0
  OPC_Decode, 179, 14, 171, 2,               //  304:   decode to PSTWpc using decoder 299
                                             //  304:  }
                                             //  304:  } // switch Inst[63:50]
                                             //  304: }
  19, 27,                                    //  309: case 0x13: {
  OPC_SwitchField, 50, 14,                   //  311:  switch Inst[63:50] {
  128, 3, 9,                                 //  314:  case 0x180: {
  OPC_CheckField, 26, 1, 0,                  //  317:   check Inst[26] == 0x0
  OPC_Decode, 144, 14, 170, 2,               //  321:   decode to PSTB using decoder 298
                                             //  321:  }
  132, 3, 0,                                 //  326:  case 0x184: {
  OPC_CheckField, 26, 1, 0,                  //  329:   check Inst[26] == 0x0
  OPC_Decode, 151, 14, 171, 2,               //  333:   decode to PSTBpc using decoder 299
                                             //  333:  }
                                             //  333:  } // switch Inst[63:50]
                                             //  333: }
  20, 51,                                    //  338: case 0x14: {
  OPC_SwitchField, 50, 14,                   //  340:  switch Inst[63:50] {
  128, 2, 9,                                 //  343:  case 0x100: {
  OPC_CheckField, 26, 1, 1,                  //  346:   check Inst[26] == 0x1
  OPC_Decode, 155, 13, 170, 2,               //  350:   decode to PLWA using decoder 298
                                             //  350:  }
  132, 2, 9,                                 //  355:  case 0x104: {
  OPC_CheckField, 26, 1, 1,                  //  358:   check Inst[26] == 0x1
  OPC_Decode, 162, 13, 171, 2,               //  362:   decode to PLWApc using decoder 299
                                             //  362:  }
  128, 3, 9,                                 //  367:  case 0x180: {
  OPC_CheckField, 26, 1, 0,                  //  370:   check Inst[26] == 0x0
  OPC_Decode, 145, 13, 170, 2,               //  374:   decode to PLHZ using decoder 298
                                             //  374:  }
  132, 3, 0,                                 //  379:  case 0x184: {
  OPC_CheckField, 26, 1, 0,                  //  382:   check Inst[26] == 0x0
  OPC_Decode, 152, 13, 171, 2,               //  386:   decode to PLHZpc using decoder 299
                                             //  386:  }
                                             //  386:  } // switch Inst[63:50]
                                             //  386: }
  21, 67,                                    //  391: case 0x15: {
  OPC_SwitchField, 50, 14,                   //  393:  switch Inst[63:50] {
  128, 2, 17,                                //  396:  case 0x100: {
  OPC_SwitchField, 26, 1,                    //  399:   switch Inst[26] {
  0, 5,                                      //  402:   case 0x0: {
  OPC_Decode, 171, 13, 175, 2,               //  404:    decode to PLXSD using decoder 303
                                             //  404:   }
  1, 0,                                      //  409:   case 0x1: {
  OPC_Decode, 175, 13, 175, 2,               //  411:    decode to PLXSSP using decoder 303
                                             //  411:   }
                                             //  411:   } // switch Inst[26]
                                             //  411:  }
  132, 2, 17,                                //  416:  case 0x104: {
  OPC_SwitchField, 26, 1,                    //  419:   switch Inst[26] {
  0, 5,                                      //  422:   case 0x0: {
  OPC_Decode, 174, 13, 176, 2,               //  424:    decode to PLXSDpc using decoder 304
                                             //  424:   }
  1, 0,                                      //  429:   case 0x1: {
  OPC_Decode, 178, 13, 176, 2,               //  431:    decode to PLXSSPpc using decoder 304
                                             //  431:   }
                                             //  431:   } // switch Inst[26]
                                             //  431:  }
  128, 3, 9,                                 //  436:  case 0x180: {
  OPC_CheckField, 26, 1, 0,                  //  439:   check Inst[26] == 0x0
  OPC_Decode, 137, 13, 170, 2,               //  443:   decode to PLHA using decoder 298
                                             //  443:  }
  132, 3, 0,                                 //  448:  case 0x184: {
  OPC_CheckField, 26, 1, 0,                  //  451:   check Inst[26] == 0x0
  OPC_Decode, 144, 13, 171, 2,               //  455:   decode to PLHApc using decoder 299
                                             //  455:  }
                                             //  455:  } // switch Inst[63:50]
                                             //  455: }
  22, 27,                                    //  460: case 0x16: {
  OPC_SwitchField, 50, 14,                   //  462:  switch Inst[63:50] {
  128, 3, 9,                                 //  465:  case 0x180: {
  OPC_CheckField, 26, 1, 0,                  //  468:   check Inst[26] == 0x0
  OPC_Decode, 164, 14, 170, 2,               //  472:   decode to PSTH using decoder 298
                                             //  472:  }
  132, 3, 0,                                 //  477:  case 0x184: {
  OPC_CheckField, 26, 1, 0,                  //  480:   check Inst[26] == 0x0
  OPC_Decode, 171, 14, 171, 2,               //  484:   decode to PSTHpc using decoder 299
                                             //  484:  }
                                             //  484:  } // switch Inst[63:50]
                                             //  484: }
  23, 45,                                    //  489: case 0x17: {
  OPC_SwitchField, 26, 1,                    //  491:  switch Inst[26] {
  0, 19,                                     //  494:  case 0x0: {
  OPC_SwitchField, 50, 14,                   //  496:   switch Inst[63:50] {
  128, 2, 5,                                 //  499:   case 0x100: {
  OPC_Decode, 180, 14, 175, 2,               //  502:    decode to PSTXSD using decoder 303
                                             //  502:   }
  132, 2, 0,                                 //  507:   case 0x104: {
  OPC_Decode, 183, 14, 176, 2,               //  510:    decode to PSTXSDpc using decoder 304
                                             //  510:   }
                                             //  510:   } // switch Inst[63:50]
                                             //  510:  }
  1, 0,                                      //  515:  case 0x1: {
  OPC_SwitchField, 50, 14,                   //  517:   switch Inst[63:50] {
  128, 2, 5,                                 //  520:   case 0x100: {
  OPC_Decode, 184, 14, 175, 2,               //  523:    decode to PSTXSSP using decoder 303
                                             //  523:   }
  132, 2, 0,                                 //  528:   case 0x104: {
  OPC_Decode, 187, 14, 176, 2,               //  531:    decode to PSTXSSPpc using decoder 304
                                             //  531:   }
                                             //  531:   } // switch Inst[63:50]
                                             //  531:  }
                                             //  531:  } // switch Inst[26]
                                             //  531: }
  24, 27,                                    //  536: case 0x18: {
  OPC_SwitchField, 50, 14,                   //  538:  switch Inst[63:50] {
  128, 3, 9,                                 //  541:  case 0x180: {
  OPC_CheckField, 26, 1, 0,                  //  544:   check Inst[26] == 0x0
  OPC_Decode, 133, 13, 177, 2,               //  548:   decode to PLFS using decoder 305
                                             //  548:  }
  132, 3, 0,                                 //  553:  case 0x184: {
  OPC_CheckField, 26, 1, 0,                  //  556:   check Inst[26] == 0x0
  OPC_Decode, 136, 13, 178, 2,               //  560:   decode to PLFSpc using decoder 306
                                             //  560:  }
                                             //  560:  } // switch Inst[63:50]
                                             //  560: }
  25, 43,                                    //  565: case 0x19: {
  OPC_SwitchField, 50, 14,                   //  567:  switch Inst[63:50] {
  128, 2, 5,                                 //  570:  case 0x100: {
  OPC_Decode, 179, 13, 179, 2,               //  573:   decode to PLXV using decoder 307
                                             //  573:  }
  132, 2, 5,                                 //  578:  case 0x104: {
  OPC_Decode, 186, 13, 180, 2,               //  581:   decode to PLXVpc using decoder 308
                                             //  581:  }
  128, 3, 9,                                 //  586:  case 0x180: {
  OPC_CheckField, 26, 1, 0,                  //  589:   check Inst[26] == 0x0
  OPC_Decode, 129, 13, 181, 2,               //  593:   decode to PLFD using decoder 309
                                             //  593:  }
  132, 3, 0,                                 //  598:  case 0x184: {
  OPC_CheckField, 26, 1, 0,                  //  601:   check Inst[26] == 0x0
  OPC_Decode, 132, 13, 182, 2,               //  605:   decode to PLFDpc using decoder 310
                                             //  605:  }
                                             //  605:  } // switch Inst[63:50]
                                             //  605: }
  26, 27,                                    //  610: case 0x1a: {
  OPC_SwitchField, 50, 14,                   //  612:  switch Inst[63:50] {
  128, 3, 9,                                 //  615:  case 0x180: {
  OPC_CheckField, 26, 1, 0,                  //  618:   check Inst[26] == 0x0
  OPC_Decode, 160, 14, 177, 2,               //  622:   decode to PSTFS using decoder 305
                                             //  622:  }
  132, 3, 0,                                 //  627:  case 0x184: {
  OPC_CheckField, 26, 1, 0,                  //  630:   check Inst[26] == 0x0
  OPC_Decode, 163, 14, 178, 2,               //  634:   decode to PSTFSpc using decoder 306
                                             //  634:  }
                                             //  634:  } // switch Inst[63:50]
                                             //  634: }
  27, 43,                                    //  639: case 0x1b: {
  OPC_SwitchField, 50, 14,                   //  641:  switch Inst[63:50] {
  128, 2, 5,                                 //  644:  case 0x100: {
  OPC_Decode, 188, 14, 179, 2,               //  647:   decode to PSTXV using decoder 307
                                             //  647:  }
  132, 2, 5,                                 //  652:  case 0x104: {
  OPC_Decode, 195, 14, 180, 2,               //  655:   decode to PSTXVpc using decoder 308
                                             //  655:  }
  128, 3, 9,                                 //  660:  case 0x180: {
  OPC_CheckField, 26, 1, 0,                  //  663:   check Inst[26] == 0x0
  OPC_Decode, 156, 14, 181, 2,               //  667:   decode to PSTFD using decoder 309
                                             //  667:  }
  132, 3, 0,                                 //  672:  case 0x184: {
  OPC_CheckField, 26, 1, 0,                  //  675:   check Inst[26] == 0x0
  OPC_Decode, 159, 14, 182, 2,               //  679:   decode to PSTFDpc using decoder 310
                                             //  679:  }
                                             //  679:  } // switch Inst[63:50]
                                             //  679: }
  28, 27,                                    //  684: case 0x1c: {
  OPC_SwitchField, 50, 14,                   //  686:  switch Inst[63:50] {
  128, 2, 9,                                 //  689:  case 0x100: {
  OPC_CheckField, 26, 1, 1,                  //  692:   check Inst[26] == 0x1
  OPC_Decode, 253, 12, 183, 2,               //  696:   decode to PLD using decoder 311
                                             //  696:  }
  132, 2, 0,                                 //  701:  case 0x104: {
  OPC_CheckField, 26, 1, 1,                  //  704:   check Inst[26] == 0x1
  OPC_Decode, 128, 13, 184, 2,               //  708:   decode to PLDpc using decoder 312
                                             //  708:  }
                                             //  708:  } // switch Inst[63:50]
                                             //  708: }
  29, 167, 9,                                //  713: case 0x1d: {
  OPC_SwitchField, 50, 14,                   //  716:  switch Inst[63:50] {
  128, 2, 9,                                 //  719:  case 0x100: {
  OPC_CheckField, 26, 1, 0,                  //  722:   check Inst[26] == 0x0
  OPC_Decode, 180, 13, 185, 2,               //  726:   decode to PLXVP using decoder 313
                                             //  726:  }
  132, 2, 9,                                 //  731:  case 0x104: {
  OPC_CheckField, 26, 1, 0,                  //  734:   check Inst[26] == 0x0
  OPC_Decode, 183, 13, 186, 2,               //  738:   decode to PLXVPpc using decoder 314
                                             //  738:  }
  228, 3, 0,                                 //  743:  case 0x1e4: {
  OPC_SwitchField, 3, 8,                     //  746:   switch Inst[10:3] {
  2, 25,                                     //  749:   case 0x2: {
  OPC_CheckField, 48, 2, 0,                  //  751:    check Inst[49:48] == 0x0
  OPC_CheckField, 40, 4, 0,                  //  755:    check Inst[43:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  //  759:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  //  763:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  767:    check Inst[0] == 0x0
  OPC_Decode, 253, 13, 187, 2,               //  771:    decode to PMXVI8GER4PP using decoder 315
                                             //  771:   }
  3, 25,                                     //  776:   case 0x3: {
  OPC_CheckField, 48, 2, 0,                  //  778:    check Inst[49:48] == 0x0
  OPC_CheckField, 40, 4, 0,                  //  782:    check Inst[43:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  //  786:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  //  790:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  794:    check Inst[0] == 0x0
  OPC_Decode, 252, 13, 188, 2,               //  798:    decode to PMXVI8GER4 using decoder 316
                                             //  798:   }
  10, 25,                                    //  803:   case 0xa: {
  OPC_CheckField, 48, 2, 0,                  //  805:    check Inst[49:48] == 0x0
  OPC_CheckField, 26, 1, 1,                  //  809:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  //  813:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  //  817:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  821:    check Inst[0] == 0x0
  OPC_Decode, 198, 13, 189, 2,               //  825:    decode to PMDMXVI8GERX4PP using decoder 317
                                             //  825:   }
  11, 25,                                    //  830:   case 0xb: {
  OPC_CheckField, 48, 2, 0,                  //  832:    check Inst[49:48] == 0x0
  OPC_CheckField, 26, 1, 1,                  //  836:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  //  840:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  //  844:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  848:    check Inst[0] == 0x0
  OPC_Decode, 197, 13, 190, 2,               //  852:    decode to PMDMXVI8GERX4 using decoder 318
                                             //  852:   }
  18, 25,                                    //  857:   case 0x12: {
  OPC_CheckField, 48, 2, 0,                  //  859:    check Inst[49:48] == 0x0
  OPC_CheckField, 40, 6, 0,                  //  863:    check Inst[45:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  //  867:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  //  871:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  875:    check Inst[0] == 0x0
  OPC_Decode, 214, 13, 191, 2,               //  879:    decode to PMXVF16GER2PP using decoder 319
                                             //  879:   }
  19, 25,                                    //  884:   case 0x13: {
  OPC_CheckField, 48, 2, 0,                  //  886:    check Inst[49:48] == 0x0
  OPC_CheckField, 40, 6, 0,                  //  890:    check Inst[45:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  //  894:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  //  898:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  902:    check Inst[0] == 0x0
  OPC_Decode, 210, 13, 192, 2,               //  906:    decode to PMXVF16GER2 using decoder 320
                                             //  906:   }
  26, 21,                                    //  911:   case 0x1a: {
  OPC_CheckField, 40, 10, 0,                 //  913:    check Inst[49:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  //  917:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  //  921:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  925:    check Inst[0] == 0x0
  OPC_Decode, 224, 13, 193, 2,               //  929:    decode to PMXVF32GERPP using decoder 321
                                             //  929:   }
  27, 21,                                    //  934:   case 0x1b: {
  OPC_CheckField, 40, 10, 0,                 //  936:    check Inst[49:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  //  940:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  //  944:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  948:    check Inst[0] == 0x0
  OPC_Decode, 220, 13, 194, 2,               //  952:    decode to PMXVF32GER using decoder 322
                                             //  952:   }
  34, 21,                                    //  957:   case 0x22: {
  OPC_CheckField, 48, 2, 0,                  //  959:    check Inst[49:48] == 0x0
  OPC_CheckField, 26, 1, 1,                  //  963:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  //  967:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  971:    check Inst[0] == 0x0
  OPC_Decode, 249, 13, 195, 2,               //  975:    decode to PMXVI4GER8PP using decoder 323
                                             //  975:   }
  35, 21,                                    //  980:   case 0x23: {
  OPC_CheckField, 48, 2, 0,                  //  982:    check Inst[49:48] == 0x0
  OPC_CheckField, 26, 1, 1,                  //  986:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  //  990:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   //  994:    check Inst[0] == 0x0
  OPC_Decode, 248, 13, 196, 2,               //  998:    decode to PMXVI4GER8 using decoder 324
                                             //  998:   }
  42, 25,                                    // 1003:   case 0x2a: {
  OPC_CheckField, 48, 2, 0,                  // 1005:    check Inst[49:48] == 0x0
  OPC_CheckField, 40, 6, 0,                  // 1009:    check Inst[45:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1013:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1017:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1021:    check Inst[0] == 0x0
  OPC_Decode, 243, 13, 191, 2,               // 1025:    decode to PMXVI16GER2SPP using decoder 319
                                             // 1025:   }
  43, 25,                                    // 1030:   case 0x2b: {
  OPC_CheckField, 48, 2, 0,                  // 1032:    check Inst[49:48] == 0x0
  OPC_CheckField, 40, 6, 0,                  // 1036:    check Inst[45:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1040:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1044:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1048:    check Inst[0] == 0x0
  OPC_Decode, 242, 13, 192, 2,               // 1052:    decode to PMXVI16GER2S using decoder 320
                                             // 1052:   }
  50, 25,                                    // 1057:   case 0x32: {
  OPC_CheckField, 48, 2, 0,                  // 1059:    check Inst[49:48] == 0x0
  OPC_CheckField, 40, 6, 0,                  // 1063:    check Inst[45:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1067:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1071:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1075:    check Inst[0] == 0x0
  OPC_Decode, 204, 13, 191, 2,               // 1079:    decode to PMXVBF16GER2PP using decoder 319
                                             // 1079:   }
  51, 25,                                    // 1084:   case 0x33: {
  OPC_CheckField, 48, 2, 0,                  // 1086:    check Inst[49:48] == 0x0
  OPC_CheckField, 40, 6, 0,                  // 1090:    check Inst[45:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1094:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1098:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1102:    check Inst[0] == 0x0
  OPC_Decode, 200, 13, 192, 2,               // 1106:    decode to PMXVBF16GER2 using decoder 320
                                             // 1106:   }
  58, 25,                                    // 1111:   case 0x3a: {
  OPC_CheckField, 40, 10, 0,                 // 1113:    check Inst[49:40] == 0x0
  OPC_CheckField, 32, 2, 0,                  // 1117:    check Inst[33:32] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1121:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1125:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1129:    check Inst[0] == 0x0
  OPC_Decode, 234, 13, 197, 2,               // 1133:    decode to PMXVF64GERPP using decoder 325
                                             // 1133:   }
  59, 25,                                    // 1138:   case 0x3b: {
  OPC_CheckField, 40, 10, 0,                 // 1140:    check Inst[49:40] == 0x0
  OPC_CheckField, 32, 2, 0,                  // 1144:    check Inst[33:32] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1148:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1152:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1156:    check Inst[0] == 0x0
  OPC_Decode, 230, 13, 198, 2,               // 1160:    decode to PMXVF64GER using decoder 326
                                             // 1160:   }
  66, 29,                                    // 1165:   case 0x42: {
  OPC_CheckField, 48, 2, 0,                  // 1167:    check Inst[49:48] == 0x0
  OPC_CheckField, 44, 2, 0,                  // 1171:    check Inst[45:44] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1175:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1179:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 1183:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1187:    check Inst[0] == 0x0
  OPC_Decode, 196, 13, 199, 2,               // 1191:    decode to PMDMXVF16GERX2PP using decoder 327
                                             // 1191:   }
  67, 29,                                    // 1196:   case 0x43: {
  OPC_CheckField, 48, 2, 0,                  // 1198:    check Inst[49:48] == 0x0
  OPC_CheckField, 44, 2, 0,                  // 1202:    check Inst[45:44] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1206:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1210:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 1214:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1218:    check Inst[0] == 0x0
  OPC_Decode, 192, 13, 200, 2,               // 1222:    decode to PMDMXVF16GERX2 using decoder 328
                                             // 1222:   }
  74, 29,                                    // 1227:   case 0x4a: {
  OPC_CheckField, 48, 2, 0,                  // 1229:    check Inst[49:48] == 0x0
  OPC_CheckField, 44, 2, 0,                  // 1233:    check Inst[45:44] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1237:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1241:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 1245:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1249:    check Inst[0] == 0x0
  OPC_Decode, 191, 13, 199, 2,               // 1253:    decode to PMDMXVBF16GERX2PP using decoder 327
                                             // 1253:   }
  75, 25,                                    // 1258:   case 0x4b: {
  OPC_CheckField, 48, 2, 0,                  // 1260:    check Inst[49:48] == 0x0
  OPC_CheckField, 40, 6, 0,                  // 1264:    check Inst[45:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1268:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1272:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1276:    check Inst[0] == 0x0
  OPC_Decode, 240, 13, 192, 2,               // 1280:    decode to PMXVI16GER2 using decoder 320
                                             // 1280:   }
  82, 25,                                    // 1285:   case 0x52: {
  OPC_CheckField, 48, 2, 0,                  // 1287:    check Inst[49:48] == 0x0
  OPC_CheckField, 40, 6, 0,                  // 1291:    check Inst[45:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1295:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1299:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1303:    check Inst[0] == 0x0
  OPC_Decode, 212, 13, 191, 2,               // 1307:    decode to PMXVF16GER2NP using decoder 319
                                             // 1307:   }
  83, 29,                                    // 1312:   case 0x53: {
  OPC_CheckField, 48, 2, 0,                  // 1314:    check Inst[49:48] == 0x0
  OPC_CheckField, 44, 2, 0,                  // 1318:    check Inst[45:44] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1322:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1326:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 1330:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1334:    check Inst[0] == 0x0
  OPC_Decode, 194, 13, 199, 2,               // 1338:    decode to PMDMXVF16GERX2NP using decoder 327
                                             // 1338:   }
  90, 21,                                    // 1343:   case 0x5a: {
  OPC_CheckField, 40, 10, 0,                 // 1345:    check Inst[49:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1349:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1353:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1357:    check Inst[0] == 0x0
  OPC_Decode, 222, 13, 193, 2,               // 1361:    decode to PMXVF32GERNP using decoder 321
                                             // 1361:   }
  91, 29,                                    // 1366:   case 0x5b: {
  OPC_CheckField, 48, 2, 0,                  // 1368:    check Inst[49:48] == 0x0
  OPC_CheckField, 44, 2, 0,                  // 1372:    check Inst[45:44] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1376:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1380:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 1384:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1388:    check Inst[0] == 0x0
  OPC_Decode, 187, 13, 200, 2,               // 1392:    decode to PMDMXVBF16GERX2 using decoder 328
                                             // 1392:   }
  98, 25,                                    // 1397:   case 0x62: {
  OPC_CheckField, 48, 2, 0,                  // 1399:    check Inst[49:48] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1403:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1407:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 1411:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1415:    check Inst[0] == 0x0
  OPC_Decode, 199, 13, 189, 2,               // 1419:    decode to PMDMXVI8GERX4SPP using decoder 317
                                             // 1419:   }
  99, 25,                                    // 1424:   case 0x63: {
  OPC_CheckField, 48, 2, 0,                  // 1426:    check Inst[49:48] == 0x0
  OPC_CheckField, 40, 4, 0,                  // 1430:    check Inst[43:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1434:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1438:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1442:    check Inst[0] == 0x0
  OPC_Decode, 254, 13, 187, 2,               // 1446:    decode to PMXVI8GER4SPP using decoder 315
                                             // 1446:   }
  107, 25,                                   // 1451:   case 0x6b: {
  OPC_CheckField, 48, 2, 0,                  // 1453:    check Inst[49:48] == 0x0
  OPC_CheckField, 40, 6, 0,                  // 1457:    check Inst[45:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1461:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1465:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1469:    check Inst[0] == 0x0
  OPC_Decode, 241, 13, 191, 2,               // 1473:    decode to PMXVI16GER2PP using decoder 319
                                             // 1473:   }
  114, 25,                                   // 1478:   case 0x72: {
  OPC_CheckField, 48, 2, 0,                  // 1480:    check Inst[49:48] == 0x0
  OPC_CheckField, 40, 6, 0,                  // 1484:    check Inst[45:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1488:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1492:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1496:    check Inst[0] == 0x0
  OPC_Decode, 202, 13, 191, 2,               // 1500:    decode to PMXVBF16GER2NP using decoder 319
                                             // 1500:   }
  115, 29,                                   // 1505:   case 0x73: {
  OPC_CheckField, 48, 2, 0,                  // 1507:    check Inst[49:48] == 0x0
  OPC_CheckField, 44, 2, 0,                  // 1511:    check Inst[45:44] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1515:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1519:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 1523:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1527:    check Inst[0] == 0x0
  OPC_Decode, 189, 13, 199, 2,               // 1531:    decode to PMDMXVBF16GERX2NP using decoder 327
                                             // 1531:   }
  122, 25,                                   // 1536:   case 0x7a: {
  OPC_CheckField, 40, 10, 0,                 // 1538:    check Inst[49:40] == 0x0
  OPC_CheckField, 32, 2, 0,                  // 1542:    check Inst[33:32] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1546:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1550:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1554:    check Inst[0] == 0x0
  OPC_Decode, 232, 13, 197, 2,               // 1558:    decode to PMXVF64GERNP using decoder 325
                                             // 1558:   }
  146, 1, 25,                                // 1563:   case 0x92: {
  OPC_CheckField, 48, 2, 0,                  // 1566:    check Inst[49:48] == 0x0
  OPC_CheckField, 40, 6, 0,                  // 1570:    check Inst[45:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1574:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1578:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1582:    check Inst[0] == 0x0
  OPC_Decode, 213, 13, 191, 2,               // 1586:    decode to PMXVF16GER2PN using decoder 319
                                             // 1586:   }
  147, 1, 29,                                // 1591:   case 0x93: {
  OPC_CheckField, 48, 2, 0,                  // 1594:    check Inst[49:48] == 0x0
  OPC_CheckField, 44, 2, 0,                  // 1598:    check Inst[45:44] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1602:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1606:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 1610:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1614:    check Inst[0] == 0x0
  OPC_Decode, 195, 13, 199, 2,               // 1618:    decode to PMDMXVF16GERX2PN using decoder 327
                                             // 1618:   }
  154, 1, 21,                                // 1623:   case 0x9a: {
  OPC_CheckField, 40, 10, 0,                 // 1626:    check Inst[49:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1630:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1634:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1638:    check Inst[0] == 0x0
  OPC_Decode, 223, 13, 193, 2,               // 1642:    decode to PMXVF32GERPN using decoder 321
                                             // 1642:   }
  178, 1, 25,                                // 1647:   case 0xb2: {
  OPC_CheckField, 48, 2, 0,                  // 1650:    check Inst[49:48] == 0x0
  OPC_CheckField, 40, 6, 0,                  // 1654:    check Inst[45:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1658:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1662:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1666:    check Inst[0] == 0x0
  OPC_Decode, 203, 13, 191, 2,               // 1670:    decode to PMXVBF16GER2PN using decoder 319
                                             // 1670:   }
  179, 1, 29,                                // 1675:   case 0xb3: {
  OPC_CheckField, 48, 2, 0,                  // 1678:    check Inst[49:48] == 0x0
  OPC_CheckField, 44, 2, 0,                  // 1682:    check Inst[45:44] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1686:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1690:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 1694:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1698:    check Inst[0] == 0x0
  OPC_Decode, 190, 13, 199, 2,               // 1702:    decode to PMDMXVBF16GERX2PN using decoder 327
                                             // 1702:   }
  186, 1, 25,                                // 1707:   case 0xba: {
  OPC_CheckField, 40, 10, 0,                 // 1710:    check Inst[49:40] == 0x0
  OPC_CheckField, 32, 2, 0,                  // 1714:    check Inst[33:32] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1718:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1722:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1726:    check Inst[0] == 0x0
  OPC_Decode, 233, 13, 197, 2,               // 1730:    decode to PMXVF64GERPN using decoder 325
                                             // 1730:   }
  202, 1, 29,                                // 1735:   case 0xca: {
  OPC_CheckField, 48, 2, 0,                  // 1738:    check Inst[49:48] == 0x0
  OPC_CheckField, 44, 2, 0,                  // 1742:    check Inst[45:44] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1746:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1750:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 1754:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1758:    check Inst[0] == 0x0
  OPC_Decode, 193, 13, 199, 2,               // 1762:    decode to PMDMXVF16GERX2NN using decoder 327
                                             // 1762:   }
  210, 1, 25,                                // 1767:   case 0xd2: {
  OPC_CheckField, 48, 2, 0,                  // 1770:    check Inst[49:48] == 0x0
  OPC_CheckField, 40, 6, 0,                  // 1774:    check Inst[45:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1778:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1782:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1786:    check Inst[0] == 0x0
  OPC_Decode, 211, 13, 191, 2,               // 1790:    decode to PMXVF16GER2NN using decoder 319
                                             // 1790:   }
  218, 1, 21,                                // 1795:   case 0xda: {
  OPC_CheckField, 40, 10, 0,                 // 1798:    check Inst[49:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1802:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1806:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1810:    check Inst[0] == 0x0
  OPC_Decode, 221, 13, 193, 2,               // 1814:    decode to PMXVF32GERNN using decoder 321
                                             // 1814:   }
  234, 1, 29,                                // 1819:   case 0xea: {
  OPC_CheckField, 48, 2, 0,                  // 1822:    check Inst[49:48] == 0x0
  OPC_CheckField, 44, 2, 0,                  // 1826:    check Inst[45:44] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1830:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1834:    check Inst[22:21] == 0x0
  OPC_CheckField, 16, 1, 0,                  // 1838:    check Inst[16] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1842:    check Inst[0] == 0x0
  OPC_Decode, 188, 13, 199, 2,               // 1846:    decode to PMDMXVBF16GERX2NN using decoder 327
                                             // 1846:   }
  242, 1, 25,                                // 1851:   case 0xf2: {
  OPC_CheckField, 48, 2, 0,                  // 1854:    check Inst[49:48] == 0x0
  OPC_CheckField, 40, 6, 0,                  // 1858:    check Inst[45:40] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1862:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1866:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1870:    check Inst[0] == 0x0
  OPC_Decode, 201, 13, 191, 2,               // 1874:    decode to PMXVBF16GER2NN using decoder 319
                                             // 1874:   }
  250, 1, 0,                                 // 1879:   case 0xfa: {
  OPC_CheckField, 40, 10, 0,                 // 1882:    check Inst[49:40] == 0x0
  OPC_CheckField, 32, 2, 0,                  // 1886:    check Inst[33:32] == 0x0
  OPC_CheckField, 26, 1, 1,                  // 1890:    check Inst[26] == 0x1
  OPC_CheckField, 21, 2, 0,                  // 1894:    check Inst[22:21] == 0x0
  OPC_CheckField, 0, 1, 0,                   // 1898:    check Inst[0] == 0x0
  OPC_Decode, 231, 13, 197, 2,               // 1902:    decode to PMXVF64GERNN using decoder 325
                                             // 1902:   }
                                             // 1902:   } // switch Inst[10:3]
                                             // 1902:  }
                                             // 1902:  } // switch Inst[63:50]
                                             // 1902: }
  30, 27,                                    // 1907: case 0x1e: {
  OPC_SwitchField, 50, 14,                   // 1909:  switch Inst[63:50] {
  128, 2, 9,                                 // 1912:  case 0x100: {
  OPC_CheckField, 26, 1, 1,                  // 1915:   check Inst[26] == 0x1
  OPC_Decode, 152, 14, 183, 2,               // 1919:   decode to PSTD using decoder 311
                                             // 1919:  }
  132, 2, 0,                                 // 1924:  case 0x104: {
  OPC_CheckField, 26, 1, 1,                  // 1927:   check Inst[26] == 0x1
  OPC_Decode, 155, 14, 184, 2,               // 1931:   decode to PSTDpc using decoder 312
                                             // 1931:  }
                                             // 1931:  } // switch Inst[63:50]
                                             // 1931: }
  31, 0,                                     // 1936: case 0x1f: {
  OPC_SwitchField, 50, 14,                   // 1938:  switch Inst[63:50] {
  128, 2, 9,                                 // 1941:  case 0x100: {
  OPC_CheckField, 26, 1, 0,                  // 1944:   check Inst[26] == 0x0
  OPC_Decode, 189, 14, 185, 2,               // 1948:   decode to PSTXVP using decoder 313
                                             // 1948:  }
  132, 2, 0,                                 // 1953:  case 0x104: {
  OPC_CheckField, 26, 1, 0,                  // 1956:   check Inst[26] == 0x0
  OPC_Decode, 192, 14, 186, 2,               // 1960:   decode to PSTXVPpc using decoder 314
                                             // 1960:  }
                                             // 1960:  } // switch Inst[63:50]
                                             // 1960: }
                                             // 1960: } // switch Inst[31:27]
};
// Handling 329 cases.
template <typename InsnType>
static DecodeStatus decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) {
  DecodeComplete = true;
  using TmpType = std::conditional_t<std::is_integral<InsnType>::value, InsnType, uint64_t>;
  TmpType tmp;
  switch (Idx) {
  default: llvm_unreachable("Invalid decoder index!");
  case 0:
    return S;
  case 1:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 2:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 3:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 4:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 5:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 9, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 6:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 7:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 8:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 9, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 9:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 10:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 11:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 3);
    if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 12:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 13:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 14:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 15:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 15, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 16:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 17:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 18:
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 19:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 20:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 21:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 22:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeSImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 23:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 24:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 3);
    if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 25:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 26:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 27:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 28:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 29:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 30:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 31:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1);
    tmp |= fieldFromInstruction(insn, 6, 10) << 6;
    tmp |= fieldFromInstruction(insn, 16, 5) << 1;
    if (!Check(S, decodeUImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 32:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 6, 3);
    if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 33:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 6, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 34:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 6, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 35:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 6, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 36:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 6, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 37:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 6, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 38:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 6, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 39:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 21, 1) << 4;
    tmp |= fieldFromInstruction(insn, 22, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 4, 12);
    if (!Check(S, decodeDispRIX16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 40:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 41:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    if (!Check(S, decodeUImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 42:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    if (!Check(S, decodeUImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 43:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 44:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 45:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 46:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRC_NOR0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 47:
    tmp = fieldFromInstruction(insn, 2, 14);
    if (!Check(S, decodeCondBrTarget(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 48:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 2, 14);
    if (!Check(S, decodeCondBrTarget(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 49:
    tmp = fieldFromInstruction(insn, 5, 7);
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 50:
    tmp = fieldFromInstruction(insn, 2, 24);
    if (!Check(S, decodeDirectBrTarget(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 51:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 18, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 52:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 53:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1);
    tmp |= fieldFromInstruction(insn, 6, 10) << 6;
    tmp |= fieldFromInstruction(insn, 16, 5) << 1;
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 54:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 2);
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 55:
    tmp = fieldFromInstruction(insn, 11, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 56:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 6, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 1, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 57:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 6, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 1, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 58:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 6, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 1, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 59:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    if (!Check(S, decodeUImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 60:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 5, 1) << 5;
    tmp |= fieldFromInstruction(insn, 6, 5);
    if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 61:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 5, 1) << 5;
    tmp |= fieldFromInstruction(insn, 6, 5);
    if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 62:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 5, 1) << 5;
    tmp |= fieldFromInstruction(insn, 6, 5);
    if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 63:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 64:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 65:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 18, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 66:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 67:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 68:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 69:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 70:
    tmp = fieldFromInstruction(insn, 15, 1);
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 71:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 11, 5) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 72:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 73:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 74:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 75:
    tmp = fieldFromInstruction(insn, 21, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 76:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 77:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8pRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8pRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 78:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 79:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 80:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 81:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 82:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 83:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 10, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 84:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 85:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 9, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 86:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 87:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 88:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 89:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 21, 1) << 4;
    tmp |= fieldFromInstruction(insn, 22, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 90:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 91:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 21, 1) << 4;
    tmp |= fieldFromInstruction(insn, 22, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 92:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 10);
    if (!Check(S, decodeUImmOperand<10>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 93:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 11, 5) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    MI.addOperand(MCOperand::createImm(tmp));
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 94:
    tmp = fieldFromInstruction(insn, 21, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 95:
    tmp = fieldFromInstruction(insn, 25, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 96:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 97:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 98:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRC_NOR0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 6, 5);
    if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 99:
    tmp = fieldFromInstruction(insn, 12, 8);
    MI.addOperand(MCOperand::createImm(tmp));
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 100:
    tmp = fieldFromInstruction(insn, 12, 8);
    if (!Check(S, decodeCRBitMOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 101:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 102:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 103:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 104:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 13, 3);
    if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 105:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 13, 3);
    if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 106:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 13, 3);
    if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 107:
    tmp = fieldFromInstruction(insn, 24, 2);
    if (!Check(S, DecodeDMRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 24, 2);
    if (!Check(S, DecodeDMRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 108:
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 18, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 109:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 110:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 12, 8);
    if (!Check(S, decodeCRBitMOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 111:
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 18, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 17, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 112:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 113:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 114:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 115:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 116:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 117:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 118:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 119:
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 120:
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 121:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 122:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 123:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RC_NOX0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 124:
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, decodeDispRIHashOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 125:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 126:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 1);
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 127:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 128:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 129:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 130:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 131:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8pRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 132:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 133:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 134:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 135:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 136:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 137:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 138:
    tmp = fieldFromInstruction(insn, 21, 2);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 139:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 140:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 141:
    tmp = fieldFromInstruction(insn, 21, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 142:
    tmp = fieldFromInstruction(insn, 21, 3);
    if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 143:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 144:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 145:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 146:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 147:
    tmp = fieldFromInstruction(insn, 21, 2);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 148:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 149:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 150:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 151:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 152:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 153:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 154:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 155:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 156:
    tmp = fieldFromInstruction(insn, 21, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 157:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 158:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    MI.addOperand(MCOperand::createImm(tmp));
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 159:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    MI.addOperand(MCOperand::createImm(tmp));
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 160:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    MI.addOperand(MCOperand::createImm(tmp));
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 161:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    MI.addOperand(MCOperand::createImm(tmp));
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 162:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    MI.addOperand(MCOperand::createImm(tmp));
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 163:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    MI.addOperand(MCOperand::createImm(tmp));
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 164:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    MI.addOperand(MCOperand::createImm(tmp));
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 165:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    MI.addOperand(MCOperand::createImm(tmp));
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 166:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 16);
    MI.addOperand(MCOperand::createImm(tmp));
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 167:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8pRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 4, 12);
    if (!Check(S, decodeDispRIX16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 168:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 2, 14);
    if (!Check(S, decodeDispRIXOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 169:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 2, 14);
    if (!Check(S, decodeDispRIXOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 170:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 2, 14);
    if (!Check(S, decodeDispRIXOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 171:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 172:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 173:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 9, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 174:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 10, 6);
    if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 175:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 19, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 176:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 20, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 177:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeSImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 9, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 178:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 9, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 179:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 180:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 181:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 6);
    if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 182:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 10, 6);
    if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 183:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 8, 3);
    if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 184:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 10, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 9, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 8, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 185:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 9, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 8, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 186:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 10, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 187:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 188:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 4;
    tmp |= fieldFromInstruction(insn, 17, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 189:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeVSRpEvenOperands(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 190:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 191:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 4;
    tmp |= fieldFromInstruction(insn, 17, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 192:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeVSRpEvenOperands(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 193:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 194:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 195:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 196:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 6, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 197:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 6, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 198:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 199:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 200:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 201:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 202:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 203:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 204:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 8, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 205:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 21, 1) << 4;
    tmp |= fieldFromInstruction(insn, 22, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 4;
    tmp |= fieldFromInstruction(insn, 17, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 4;
    tmp |= fieldFromInstruction(insn, 12, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 11, 1) << 1;
    tmp |= fieldFromInstruction(insn, 16, 1);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 206:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 4;
    tmp |= fieldFromInstruction(insn, 17, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 4;
    tmp |= fieldFromInstruction(insn, 12, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeWACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 207:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 4;
    tmp |= fieldFromInstruction(insn, 17, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 4;
    tmp |= fieldFromInstruction(insn, 12, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeWACC_HIRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 208:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 209:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeWACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 4;
    tmp |= fieldFromInstruction(insn, 17, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 4;
    tmp |= fieldFromInstruction(insn, 12, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 210:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeWACC_HIRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 4;
    tmp |= fieldFromInstruction(insn, 17, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 4;
    tmp |= fieldFromInstruction(insn, 12, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 211:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 212:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 213:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 21, 1) << 4;
    tmp |= fieldFromInstruction(insn, 22, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 4;
    tmp |= fieldFromInstruction(insn, 12, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 11, 1) << 1;
    tmp |= fieldFromInstruction(insn, 16, 1);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 214:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 19, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 18, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 215:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 4;
    tmp |= fieldFromInstruction(insn, 12, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeDMRROWpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 11, 1) << 1;
    tmp |= fieldFromInstruction(insn, 16, 1);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 216:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeDMRROWpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 4;
    tmp |= fieldFromInstruction(insn, 12, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 11, 1) << 1;
    tmp |= fieldFromInstruction(insn, 16, 1);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 217:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 218:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 8);
    if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 219:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 220:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 221:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 8, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 222:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 223:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 224:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 225:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 226:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 227:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 228:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 229:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 230:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 7);
    if (!Check(S, decodeUImmOperand<7>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 231:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 232:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 233:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 7);
    if (!Check(S, decodeUImmOperand<7>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 234:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 6, 1) << 6;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeUImmOperand<7>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 235:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeSImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 236:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 237:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 3, 1) << 5;
    tmp |= fieldFromInstruction(insn, 6, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 238:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 3, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 4, 12);
    if (!Check(S, decodeDispRIX16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 239:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 2, 14);
    if (!Check(S, decodeDispRIXOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 240:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8pRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 2, 14);
    if (!Check(S, decodeDispRIXOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 241:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 242:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 243:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 244:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 10, 6);
    if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 245:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 246:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 247:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 10, 6);
    if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 248:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 249:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 250:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 251:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 19, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 252:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 20, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 253:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 254:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 255:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 256:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 9, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 257:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 9, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 258:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeSImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 9, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 259:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 9, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 260:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 6);
    if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 261:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 262:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 7);
    if (!Check(S, decodeUImmOperand<7>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 263:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 264:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 265:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 266:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 9, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 267:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 12, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 1);
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 268:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 12, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 269:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 270:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 3);
    if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 271:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 272:
    tmp = fieldFromInstruction(insn, 17, 8);
    MI.addOperand(MCOperand::createImm(tmp));
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 25, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 1);
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 273:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 6, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 274:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 6, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 275:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 6, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 276:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 277:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 278:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 279:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 280:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeSImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 281:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 282:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 283:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 0, 3);
    if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 284:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 285:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 286:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 287:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 288:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, decodeDispSPE8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 289:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, decodeDispSPE2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 290:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 11, 5);
    if (!Check(S, decodeDispSPE4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 291:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 18) << 16;
    if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 292:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRC_NOR0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 18) << 16;
    if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 293:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 18) << 16;
    if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 294:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeGPRC_NOR0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 16) << 16;
    if (!Check(S, decodeSImmOperand<32>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 295:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 16) << 16;
    if (!Check(S, decodeSImmOperand<32>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 296:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 16, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 16, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 17, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 16) << 16;
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 297:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 16, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 16) << 16;
    MI.addOperand(MCOperand::createImm(tmp));
    return S;
  case 298:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 18) << 16;
    if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 299:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 18) << 16;
    if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 300:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 3, 1) << 5;
    tmp |= fieldFromInstruction(insn, 6, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 32, 3);
    if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 301:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 3, 1) << 5;
    tmp |= fieldFromInstruction(insn, 6, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 32, 8);
    if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 302:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 1) << 5;
    tmp |= fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 3, 1) << 5;
    tmp |= fieldFromInstruction(insn, 6, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 4, 1);
    if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 303:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 18) << 16;
    if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 304:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeVFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 18) << 16;
    if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 305:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 18) << 16;
    if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 306:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 18) << 16;
    if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 307:
    tmp = fieldFromInstruction(insn, 21, 6);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 18) << 16;
    if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 308:
    tmp = fieldFromInstruction(insn, 21, 6);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 18) << 16;
    if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 309:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 18) << 16;
    if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 310:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 18) << 16;
    if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 311:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 18) << 16;
    if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 312:
    tmp = fieldFromInstruction(insn, 21, 5);
    if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 18) << 16;
    if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 313:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 21, 1) << 4;
    tmp |= fieldFromInstruction(insn, 22, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 18) << 16;
    if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 314:
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 21, 1) << 4;
    tmp |= fieldFromInstruction(insn, 22, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 0, 16);
    tmp |= fieldFromInstruction(insn, 32, 18) << 16;
    if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 315:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 36, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 32, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 44, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 316:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 36, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 32, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 44, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 317:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 4;
    tmp |= fieldFromInstruction(insn, 17, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 36, 8);
    if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 32, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 44, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 318:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 4;
    tmp |= fieldFromInstruction(insn, 17, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 36, 8);
    if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 32, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 44, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 319:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 36, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 32, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 46, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 320:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 36, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 32, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 46, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 321:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 36, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 32, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 322:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 36, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 32, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 323:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 36, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 32, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 40, 8);
    if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 324:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 36, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 32, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 40, 8);
    if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 325:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeVSRpEvenOperands(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 36, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 34, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 326:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 5;
    tmp |= fieldFromInstruction(insn, 16, 5);
    if (!Check(S, decodeVSRpEvenOperands(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 36, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 34, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 327:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 4;
    tmp |= fieldFromInstruction(insn, 17, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 36, 8);
    if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 32, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 46, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  case 328:
    tmp = fieldFromInstruction(insn, 23, 3);
    if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 2, 1) << 4;
    tmp |= fieldFromInstruction(insn, 17, 4);
    if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = 0x0;
    tmp |= fieldFromInstruction(insn, 1, 1) << 5;
    tmp |= fieldFromInstruction(insn, 11, 5);
    if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 36, 8);
    if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 32, 4);
    if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    tmp = fieldFromInstruction(insn, 46, 2);
    if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
    return S;
  }
}

template <typename InsnType>
static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
                                      InsnType insn, uint64_t Address,
                                      const MCDisassembler *DisAsm,
                                      const MCSubtargetInfo &STI) {
  const uint8_t *Ptr = DecodeTable;

  SmallVector<const uint8_t *, 8> ScopeStack;
  DecodeStatus S = MCDisassembler::Success;
  while (true) {
    ptrdiff_t Loc = Ptr - DecodeTable;
    const uint8_t DecoderOp = *Ptr++;
    switch (DecoderOp) {
    default:
      errs() << Loc << ": Unexpected decode table opcode: "
             << (int)DecoderOp << '\n';
      return MCDisassembler::Fail;
    case OPC_Scope: {
      unsigned NumToSkip = decodeULEB128AndIncUnsafe(Ptr);
      const uint8_t *SkipTo = Ptr + NumToSkip;
      ScopeStack.push_back(SkipTo);
      LLVM_DEBUG(dbgs() << Loc << ": OPC_Scope(" << SkipTo - DecodeTable
                        << ")\n");
      continue;
    }
    case OPC_SwitchField: {
      // Decode the start value.
      unsigned Start = decodeULEB128AndIncUnsafe(Ptr);
      unsigned Len = *Ptr++;
      uint64_t FieldValue = fieldFromInstruction(insn, Start, Len);
      uint64_t CaseValue;
      unsigned CaseSize;
      while (true) {
        CaseValue = decodeULEB128AndIncUnsafe(Ptr);
        CaseSize = decodeULEB128AndIncUnsafe(Ptr);
        if (FieldValue == CaseValue || !CaseSize)
          break;
        Ptr += CaseSize;
      }
      if (FieldValue == CaseValue) {
        LLVM_DEBUG(dbgs() << Loc << ": OPC_SwitchField(" << Start << ", " << Len
                          << "): " << FieldValue << '\n');
        continue;
      }
      break;
    }
    case OPC_CheckField: {
      // Decode the start value.
      unsigned Start = decodeULEB128AndIncUnsafe(Ptr);
      unsigned Len = *Ptr;
      uint64_t FieldValue = fieldFromInstruction(insn, Start, Len);
      // Decode the field value.
      unsigned PtrLen = 0;
      uint64_t ExpectedValue = decodeULEB128(++Ptr, &PtrLen);
      Ptr += PtrLen;
      bool Failed = ExpectedValue != FieldValue;

      LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckField(" << Start << ", " << Len
                        << ", " << ExpectedValue << "): FieldValue = "
                        << FieldValue << ", ExpectedValue = " << ExpectedValue
                        << ": " << (Failed ? "FAIL, " : "PASS\n"););
      if (!Failed)
        continue;
      break;
    }
    case OPC_Decode: {
      // Decode the Opcode value.
      unsigned Opc = decodeULEB128AndIncUnsafe(Ptr);
      unsigned DecodeIdx = decodeULEB128AndIncUnsafe(Ptr);

      MI.clear();
      MI.setOpcode(Opc);
      bool DecodeComplete;
      S = decodeToMCInst(DecodeIdx, S, insn, MI, Address, DisAsm,
                         DecodeComplete);
      LLVM_DEBUG(dbgs() << Loc << ": OPC_Decode: opcode " << Opc
                        << ", using decoder " << DecodeIdx << ": "
                        << (S ? "PASS, " : "FAIL, "));

      if (DecodeComplete) {
        LLVM_DEBUG(dbgs() << "decoding complete\n");
        return S;
      }
      assert(S == MCDisassembler::Fail);
      // Reset decode status. This also drops a SoftFail status that could be
      // set before the decode attempt.
      S = MCDisassembler::Success;
      break;
    }
    }
    if (ScopeStack.empty()) {
      LLVM_DEBUG(dbgs() << "returning Fail\n");
      return MCDisassembler::Fail;
    }
    Ptr = ScopeStack.pop_back_val();
    LLVM_DEBUG(dbgs() << "continuing at " << Ptr - DecodeTable << '\n');
  }
  llvm_unreachable("bogosity detected in disassembler state machine!");
}


} // namespace
