/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Machine Code Emitter                                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

uint64_t LoongArchMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
    SmallVectorImpl<MCFixup> &Fixups,
    const MCSubtargetInfo &STI) const {
  static const uint64_t InstBits[] = {
    UINT64_C(3145728),	// ADC_B
    UINT64_C(3244032),	// ADC_D
    UINT64_C(3178496),	// ADC_H
    UINT64_C(3211264),	// ADC_W
    UINT64_C(46137344),	// ADDI_D
    UINT64_C(41943040),	// ADDI_W
    UINT64_C(2719744),	// ADDU12I_D
    UINT64_C(2686976),	// ADDU12I_W
    UINT64_C(268435456),	// ADDU16I_D
    UINT64_C(1081344),	// ADD_D
    UINT64_C(1048576),	// ADD_W
    UINT64_C(2883584),	// ALSL_D
    UINT64_C(262144),	// ALSL_W
    UINT64_C(393216),	// ALSL_WU
    UINT64_C(945618944),	// AMADD_B
    UINT64_C(945913856),	// AMADD_D
    UINT64_C(945651712),	// AMADD_H
    UINT64_C(945881088),	// AMADD_W
    UINT64_C(945750016),	// AMADD__DB_B
    UINT64_C(946503680),	// AMADD__DB_D
    UINT64_C(945782784),	// AMADD__DB_H
    UINT64_C(946470912),	// AMADD__DB_W
    UINT64_C(945979392),	// AMAND_D
    UINT64_C(945946624),	// AMAND_W
    UINT64_C(946569216),	// AMAND__DB_D
    UINT64_C(946536448),	// AMAND__DB_W
    UINT64_C(945291264),	// AMCAS_B
    UINT64_C(945389568),	// AMCAS_D
    UINT64_C(945324032),	// AMCAS_H
    UINT64_C(945356800),	// AMCAS_W
    UINT64_C(945422336),	// AMCAS__DB_B
    UINT64_C(945520640),	// AMCAS__DB_D
    UINT64_C(945455104),	// AMCAS__DB_H
    UINT64_C(945487872),	// AMCAS__DB_W
    UINT64_C(946176000),	// AMMAX_D
    UINT64_C(946307072),	// AMMAX_DU
    UINT64_C(946143232),	// AMMAX_W
    UINT64_C(946274304),	// AMMAX_WU
    UINT64_C(946765824),	// AMMAX__DB_D
    UINT64_C(946896896),	// AMMAX__DB_DU
    UINT64_C(946733056),	// AMMAX__DB_W
    UINT64_C(946864128),	// AMMAX__DB_WU
    UINT64_C(946241536),	// AMMIN_D
    UINT64_C(946372608),	// AMMIN_DU
    UINT64_C(946208768),	// AMMIN_W
    UINT64_C(946339840),	// AMMIN_WU
    UINT64_C(946831360),	// AMMIN__DB_D
    UINT64_C(946962432),	// AMMIN__DB_DU
    UINT64_C(946798592),	// AMMIN__DB_W
    UINT64_C(946929664),	// AMMIN__DB_WU
    UINT64_C(946044928),	// AMOR_D
    UINT64_C(946012160),	// AMOR_W
    UINT64_C(946634752),	// AMOR__DB_D
    UINT64_C(946601984),	// AMOR__DB_W
    UINT64_C(945553408),	// AMSWAP_B
    UINT64_C(945848320),	// AMSWAP_D
    UINT64_C(945586176),	// AMSWAP_H
    UINT64_C(945815552),	// AMSWAP_W
    UINT64_C(945684480),	// AMSWAP__DB_B
    UINT64_C(946438144),	// AMSWAP__DB_D
    UINT64_C(945717248),	// AMSWAP__DB_H
    UINT64_C(946405376),	// AMSWAP__DB_W
    UINT64_C(946110464),	// AMXOR_D
    UINT64_C(946077696),	// AMXOR_W
    UINT64_C(946700288),	// AMXOR__DB_D
    UINT64_C(946667520),	// AMXOR__DB_W
    UINT64_C(1343488),	// AND
    UINT64_C(54525952),	// ANDI
    UINT64_C(1474560),	// ANDN
    UINT64_C(3670032),	// ARMADC_W
    UINT64_C(3604496),	// ARMADD_W
    UINT64_C(3735568),	// ARMAND_W
    UINT64_C(6029376),	// ARMMFFLAG
    UINT64_C(3555328),	// ARMMOVE
    UINT64_C(4177950),	// ARMMOV_D
    UINT64_C(4177949),	// ARMMOV_W
    UINT64_C(6029408),	// ARMMTFLAG
    UINT64_C(4177948),	// ARMNOT_W
    UINT64_C(3768336),	// ARMOR_W
    UINT64_C(4063248),	// ARMROTRI_W
    UINT64_C(3932176),	// ARMROTR_W
    UINT64_C(4177951),	// ARMRRX_W
    UINT64_C(3702800),	// ARMSBC_W
    UINT64_C(3964944),	// ARMSLLI_W
    UINT64_C(3833872),	// ARMSLL_W
    UINT64_C(4030480),	// ARMSRAI_W
    UINT64_C(3899408),	// ARMSRA_W
    UINT64_C(3997712),	// ARMSRLI_W
    UINT64_C(3866640),	// ARMSRL_W
    UINT64_C(3637264),	// ARMSUB_W
    UINT64_C(3801104),	// ARMXOR_W
    UINT64_C(98304),	// ASRTGT_D
    UINT64_C(65536),	// ASRTLE_D
    UINT64_C(1342177280),	// B
    UINT64_C(1207959552),	// BCEQZ
    UINT64_C(1207959808),	// BCNEZ
    UINT64_C(1476395008),	// BEQ
    UINT64_C(1073741824),	// BEQZ
    UINT64_C(1677721600),	// BGE
    UINT64_C(1811939328),	// BGEU
    UINT64_C(18432),	// BITREV_4B
    UINT64_C(19456),	// BITREV_8B
    UINT64_C(21504),	// BITREV_D
    UINT64_C(20480),	// BITREV_W
    UINT64_C(1409286144),	// BL
    UINT64_C(1610612736),	// BLT
    UINT64_C(1744830464),	// BLTU
    UINT64_C(1543503872),	// BNE
    UINT64_C(1140850688),	// BNEZ
    UINT64_C(2752512),	// BREAK
    UINT64_C(8388608),	// BSTRINS_D
    UINT64_C(6291456),	// BSTRINS_W
    UINT64_C(12582912),	// BSTRPICK_D
    UINT64_C(6324224),	// BSTRPICK_W
    UINT64_C(786432),	// BYTEPICK_D
    UINT64_C(524288),	// BYTEPICK_W
    UINT64_C(100663296),	// CACOP
    UINT64_C(8192),	// CLO_D
    UINT64_C(4096),	// CLO_W
    UINT64_C(9216),	// CLZ_D
    UINT64_C(5120),	// CLZ_W
    UINT64_C(27648),	// CPUCFG
    UINT64_C(2490368),	// CRCC_W_B_W
    UINT64_C(2588672),	// CRCC_W_D_W
    UINT64_C(2523136),	// CRCC_W_H_W
    UINT64_C(2555904),	// CRCC_W_W_W
    UINT64_C(2359296),	// CRC_W_B_W
    UINT64_C(2457600),	// CRC_W_D_W
    UINT64_C(2392064),	// CRC_W_H_W
    UINT64_C(2424832),	// CRC_W_W_W
    UINT64_C(67108864),	// CSRRD
    UINT64_C(67108896),	// CSRWR
    UINT64_C(67108864),	// CSRXCHG
    UINT64_C(10240),	// CTO_D
    UINT64_C(6144),	// CTO_W
    UINT64_C(11264),	// CTZ_D
    UINT64_C(7168),	// CTZ_W
    UINT64_C(946995200),	// DBAR
    UINT64_C(2785280),	// DBCL
    UINT64_C(2228224),	// DIV_D
    UINT64_C(2293760),	// DIV_DU
    UINT64_C(2097152),	// DIV_W
    UINT64_C(2162688),	// DIV_WU
    UINT64_C(105396224),	// ERTN
    UINT64_C(23552),	// EXT_W_B
    UINT64_C(22528),	// EXT_W_H
    UINT64_C(18089984),	// FABS_D
    UINT64_C(18088960),	// FABS_S
    UINT64_C(16842752),	// FADD_D
    UINT64_C(16809984),	// FADD_S
    UINT64_C(18102272),	// FCLASS_D
    UINT64_C(18101248),	// FCLASS_S
    UINT64_C(203423744),	// FCMP_CAF_D
    UINT64_C(202375168),	// FCMP_CAF_S
    UINT64_C(203554816),	// FCMP_CEQ_D
    UINT64_C(202506240),	// FCMP_CEQ_S
    UINT64_C(203620352),	// FCMP_CLE_D
    UINT64_C(202571776),	// FCMP_CLE_S
    UINT64_C(203489280),	// FCMP_CLT_D
    UINT64_C(202440704),	// FCMP_CLT_S
    UINT64_C(203948032),	// FCMP_CNE_D
    UINT64_C(202899456),	// FCMP_CNE_S
    UINT64_C(204079104),	// FCMP_COR_D
    UINT64_C(203030528),	// FCMP_COR_S
    UINT64_C(203816960),	// FCMP_CUEQ_D
    UINT64_C(202768384),	// FCMP_CUEQ_S
    UINT64_C(203882496),	// FCMP_CULE_D
    UINT64_C(202833920),	// FCMP_CULE_S
    UINT64_C(203751424),	// FCMP_CULT_D
    UINT64_C(202702848),	// FCMP_CULT_S
    UINT64_C(204210176),	// FCMP_CUNE_D
    UINT64_C(203161600),	// FCMP_CUNE_S
    UINT64_C(203685888),	// FCMP_CUN_D
    UINT64_C(202637312),	// FCMP_CUN_S
    UINT64_C(203456512),	// FCMP_SAF_D
    UINT64_C(202407936),	// FCMP_SAF_S
    UINT64_C(203587584),	// FCMP_SEQ_D
    UINT64_C(202539008),	// FCMP_SEQ_S
    UINT64_C(203653120),	// FCMP_SLE_D
    UINT64_C(202604544),	// FCMP_SLE_S
    UINT64_C(203522048),	// FCMP_SLT_D
    UINT64_C(202473472),	// FCMP_SLT_S
    UINT64_C(203980800),	// FCMP_SNE_D
    UINT64_C(202932224),	// FCMP_SNE_S
    UINT64_C(204111872),	// FCMP_SOR_D
    UINT64_C(203063296),	// FCMP_SOR_S
    UINT64_C(203849728),	// FCMP_SUEQ_D
    UINT64_C(202801152),	// FCMP_SUEQ_S
    UINT64_C(203915264),	// FCMP_SULE_D
    UINT64_C(202866688),	// FCMP_SULE_S
    UINT64_C(203784192),	// FCMP_SULT_D
    UINT64_C(202735616),	// FCMP_SULT_S
    UINT64_C(204242944),	// FCMP_SUNE_D
    UINT64_C(203194368),	// FCMP_SUNE_S
    UINT64_C(203718656),	// FCMP_SUN_D
    UINT64_C(202670080),	// FCMP_SUN_S
    UINT64_C(18022400),	// FCOPYSIGN_D
    UINT64_C(17989632),	// FCOPYSIGN_S
    UINT64_C(18153472),	// FCVT_D_LD
    UINT64_C(18424832),	// FCVT_D_S
    UINT64_C(18145280),	// FCVT_LD_D
    UINT64_C(18421760),	// FCVT_S_D
    UINT64_C(18146304),	// FCVT_UD_D
    UINT64_C(17235968),	// FDIV_D
    UINT64_C(17203200),	// FDIV_S
    UINT64_C(18688000),	// FFINT_D_L
    UINT64_C(18685952),	// FFINT_D_W
    UINT64_C(18683904),	// FFINT_S_L
    UINT64_C(18681856),	// FFINT_S_W
    UINT64_C(947159040),	// FLDGT_D
    UINT64_C(947126272),	// FLDGT_S
    UINT64_C(947224576),	// FLDLE_D
    UINT64_C(947191808),	// FLDLE_S
    UINT64_C(942931968),	// FLDX_D
    UINT64_C(942669824),	// FLDX_S
    UINT64_C(729808896),	// FLD_D
    UINT64_C(721420288),	// FLD_S
    UINT64_C(18098176),	// FLOGB_D
    UINT64_C(18097152),	// FLOGB_S
    UINT64_C(136314880),	// FMADD_D
    UINT64_C(135266304),	// FMADD_S
    UINT64_C(17629184),	// FMAXA_D
    UINT64_C(17596416),	// FMAXA_S
    UINT64_C(17367040),	// FMAX_D
    UINT64_C(17334272),	// FMAX_S
    UINT64_C(17760256),	// FMINA_D
    UINT64_C(17727488),	// FMINA_S
    UINT64_C(17498112),	// FMIN_D
    UINT64_C(17465344),	// FMIN_S
    UINT64_C(18126848),	// FMOV_D
    UINT64_C(18125824),	// FMOV_S
    UINT64_C(140509184),	// FMSUB_D
    UINT64_C(139460608),	// FMSUB_S
    UINT64_C(17104896),	// FMUL_D
    UINT64_C(17072128),	// FMUL_S
    UINT64_C(18094080),	// FNEG_D
    UINT64_C(18093056),	// FNEG_S
    UINT64_C(144703488),	// FNMADD_D
    UINT64_C(143654912),	// FNMADD_S
    UINT64_C(148897792),	// FNMSUB_D
    UINT64_C(147849216),	// FNMSUB_S
    UINT64_C(18118656),	// FRECIPE_D
    UINT64_C(18117632),	// FRECIPE_S
    UINT64_C(18110464),	// FRECIP_D
    UINT64_C(18109440),	// FRECIP_S
    UINT64_C(18761728),	// FRINT_D
    UINT64_C(18760704),	// FRINT_S
    UINT64_C(18122752),	// FRSQRTE_D
    UINT64_C(18121728),	// FRSQRTE_S
    UINT64_C(18114560),	// FRSQRT_D
    UINT64_C(18113536),	// FRSQRT_S
    UINT64_C(17891328),	// FSCALEB_D
    UINT64_C(17858560),	// FSCALEB_S
    UINT64_C(218103808),	// FSEL_xD
    UINT64_C(218103808),	// FSEL_xS
    UINT64_C(18106368),	// FSQRT_D
    UINT64_C(18105344),	// FSQRT_S
    UINT64_C(947290112),	// FSTGT_D
    UINT64_C(947257344),	// FSTGT_S
    UINT64_C(947355648),	// FSTLE_D
    UINT64_C(947322880),	// FSTLE_S
    UINT64_C(943456256),	// FSTX_D
    UINT64_C(943194112),	// FSTX_S
    UINT64_C(734003200),	// FST_D
    UINT64_C(725614592),	// FST_S
    UINT64_C(16973824),	// FSUB_D
    UINT64_C(16941056),	// FSUB_S
    UINT64_C(18491392),	// FTINTRM_L_D
    UINT64_C(18490368),	// FTINTRM_L_S
    UINT64_C(18483200),	// FTINTRM_W_D
    UINT64_C(18482176),	// FTINTRM_W_S
    UINT64_C(18540544),	// FTINTRNE_L_D
    UINT64_C(18539520),	// FTINTRNE_L_S
    UINT64_C(18532352),	// FTINTRNE_W_D
    UINT64_C(18531328),	// FTINTRNE_W_S
    UINT64_C(18507776),	// FTINTRP_L_D
    UINT64_C(18506752),	// FTINTRP_L_S
    UINT64_C(18499584),	// FTINTRP_W_D
    UINT64_C(18498560),	// FTINTRP_W_S
    UINT64_C(18524160),	// FTINTRZ_L_D
    UINT64_C(18523136),	// FTINTRZ_L_S
    UINT64_C(18515968),	// FTINTRZ_W_D
    UINT64_C(18514944),	// FTINTRZ_W_S
    UINT64_C(18556928),	// FTINT_L_D
    UINT64_C(18555904),	// FTINT_L_S
    UINT64_C(18548736),	// FTINT_W_D
    UINT64_C(18547712),	// FTINT_W_S
    UINT64_C(83886080),	// GCSRRD
    UINT64_C(83886112),	// GCSRWR
    UINT64_C(83886080),	// GCSRXCHG
    UINT64_C(105391105),	// GTLBFLUSH
    UINT64_C(2850816),	// HVCL
    UINT64_C(947027968),	// IBAR
    UINT64_C(105414656),	// IDLE
    UINT64_C(105480192),	// INVTLB
    UINT64_C(105381888),	// IOCSRRD_B
    UINT64_C(105384960),	// IOCSRRD_D
    UINT64_C(105382912),	// IOCSRRD_H
    UINT64_C(105383936),	// IOCSRRD_W
    UINT64_C(105385984),	// IOCSRWR_B
    UINT64_C(105389056),	// IOCSRWR_D
    UINT64_C(105387008),	// IOCSRWR_H
    UINT64_C(105388032),	// IOCSRWR_W
    UINT64_C(1275068416),	// JIRL
    UINT64_C(1207960064),	// JISCR0
    UINT64_C(1207960320),	// JISCR1
    UINT64_C(104857600),	// LDDIR
    UINT64_C(947388416),	// LDGT_B
    UINT64_C(947486720),	// LDGT_D
    UINT64_C(947421184),	// LDGT_H
    UINT64_C(947453952),	// LDGT_W
    UINT64_C(947519488),	// LDLE_B
    UINT64_C(947617792),	// LDLE_D
    UINT64_C(947552256),	// LDLE_H
    UINT64_C(947585024),	// LDLE_W
    UINT64_C(780140544),	// LDL_D
    UINT64_C(771751936),	// LDL_W
    UINT64_C(105119744),	// LDPTE
    UINT64_C(637534208),	// LDPTR_D
    UINT64_C(603979776),	// LDPTR_W
    UINT64_C(784334848),	// LDR_D
    UINT64_C(775946240),	// LDR_W
    UINT64_C(939524096),	// LDX_B
    UINT64_C(941621248),	// LDX_BU
    UINT64_C(940310528),	// LDX_D
    UINT64_C(939786240),	// LDX_H
    UINT64_C(941883392),	// LDX_HU
    UINT64_C(940048384),	// LDX_W
    UINT64_C(942145536),	// LDX_WU
    UINT64_C(671088640),	// LD_B
    UINT64_C(704643072),	// LD_BU
    UINT64_C(683671552),	// LD_D
    UINT64_C(675282944),	// LD_H
    UINT64_C(708837376),	// LD_HU
    UINT64_C(679477248),	// LD_W
    UINT64_C(713031680),	// LD_WU
    UINT64_C(945260544),	// LLACQ_D
    UINT64_C(945258496),	// LLACQ_W
    UINT64_C(570425344),	// LL_D
    UINT64_C(536870912),	// LL_W
    UINT64_C(335544320),	// LU12I_W
    UINT64_C(369098752),	// LU32I_D
    UINT64_C(50331648),	// LU52I_D
    UINT64_C(1245184),	// MASKEQZ
    UINT64_C(1277952),	// MASKNEZ
    UINT64_C(2260992),	// MOD_D
    UINT64_C(2326528),	// MOD_DU
    UINT64_C(2129920),	// MOD_W
    UINT64_C(2195456),	// MOD_WU
    UINT64_C(18142208),	// MOVCF2FR_xS
    UINT64_C(18144256),	// MOVCF2GR
    UINT64_C(18139136),	// MOVFCSR2GR
    UINT64_C(18141184),	// MOVFR2CF_xS
    UINT64_C(18135040),	// MOVFR2GR_D
    UINT64_C(18134016),	// MOVFR2GR_S
    UINT64_C(18134016),	// MOVFR2GR_S_64
    UINT64_C(18136064),	// MOVFRH2GR_S
    UINT64_C(18143232),	// MOVGR2CF
    UINT64_C(18137088),	// MOVGR2FCSR
    UINT64_C(18131968),	// MOVGR2FRH_W
    UINT64_C(18130944),	// MOVGR2FR_D
    UINT64_C(18129920),	// MOVGR2FR_W
    UINT64_C(18129920),	// MOVGR2FR_W_64
    UINT64_C(2048),	// MOVGR2SCR
    UINT64_C(3072),	// MOVSCR2GR
    UINT64_C(1966080),	// MULH_D
    UINT64_C(1998848),	// MULH_DU
    UINT64_C(1867776),	// MULH_W
    UINT64_C(1900544),	// MULH_WU
    UINT64_C(2031616),	// MULW_D_W
    UINT64_C(2064384),	// MULW_D_WU
    UINT64_C(1933312),	// MUL_D
    UINT64_C(1835008),	// MUL_W
    UINT64_C(1310720),	// NOR
    UINT64_C(1376256),	// OR
    UINT64_C(58720256),	// ORI
    UINT64_C(1441792),	// ORN
    UINT64_C(402653184),	// PCADDI
    UINT64_C(469762048),	// PCADDU12I
    UINT64_C(503316480),	// PCADDU18I
    UINT64_C(436207616),	// PCALAU12I
    UINT64_C(717225984),	// PRELD
    UINT64_C(942407680),	// PRELDX
    UINT64_C(5251072),	// RCRI_B
    UINT64_C(5308416),	// RCRI_D
    UINT64_C(5259264),	// RCRI_H
    UINT64_C(5275648),	// RCRI_W
    UINT64_C(3407872),	// RCR_B
    UINT64_C(3506176),	// RCR_D
    UINT64_C(3440640),	// RCR_H
    UINT64_C(3473408),	// RCR_W
    UINT64_C(25600),	// RDTIMEH_W
    UINT64_C(24576),	// RDTIMEL_W
    UINT64_C(26624),	// RDTIME_D
    UINT64_C(12288),	// REVB_2H
    UINT64_C(14336),	// REVB_2W
    UINT64_C(13312),	// REVB_4H
    UINT64_C(15360),	// REVB_D
    UINT64_C(16384),	// REVH_2W
    UINT64_C(17408),	// REVH_D
    UINT64_C(4988928),	// ROTRI_B
    UINT64_C(5046272),	// ROTRI_D
    UINT64_C(4997120),	// ROTRI_H
    UINT64_C(5013504),	// ROTRI_W
    UINT64_C(1703936),	// ROTR_B
    UINT64_C(1802240),	// ROTR_D
    UINT64_C(1736704),	// ROTR_H
    UINT64_C(1769472),	// ROTR_W
    UINT64_C(3276800),	// SBC_B
    UINT64_C(3375104),	// SBC_D
    UINT64_C(3309568),	// SBC_H
    UINT64_C(3342336),	// SBC_W
    UINT64_C(945261568),	// SCREL_D
    UINT64_C(945259520),	// SCREL_W
    UINT64_C(587202560),	// SC_D
    UINT64_C(945225728),	// SC_Q
    UINT64_C(553648128),	// SC_W
    UINT64_C(3588096),	// SETARMJ
    UINT64_C(3571712),	// SETX86J
    UINT64_C(30720),	// SETX86LOOPE
    UINT64_C(31744),	// SETX86LOOPNE
    UINT64_C(202375168),	// SET_CFR_FALSE
    UINT64_C(202768384),	// SET_CFR_TRUE
    UINT64_C(4259840),	// SLLI_D
    UINT64_C(4227072),	// SLLI_W
    UINT64_C(1605632),	// SLL_D
    UINT64_C(1507328),	// SLL_W
    UINT64_C(1179648),	// SLT
    UINT64_C(33554432),	// SLTI
    UINT64_C(1212416),	// SLTU
    UINT64_C(37748736),	// SLTUI
    UINT64_C(4784128),	// SRAI_D
    UINT64_C(4751360),	// SRAI_W
    UINT64_C(1671168),	// SRA_D
    UINT64_C(1572864),	// SRA_W
    UINT64_C(4521984),	// SRLI_D
    UINT64_C(4489216),	// SRLI_W
    UINT64_C(1638400),	// SRL_D
    UINT64_C(1540096),	// SRL_W
    UINT64_C(947650560),	// STGT_B
    UINT64_C(947748864),	// STGT_D
    UINT64_C(947683328),	// STGT_H
    UINT64_C(947716096),	// STGT_W
    UINT64_C(947781632),	// STLE_B
    UINT64_C(947879936),	// STLE_D
    UINT64_C(947814400),	// STLE_H
    UINT64_C(947847168),	// STLE_W
    UINT64_C(796917760),	// STL_D
    UINT64_C(788529152),	// STL_W
    UINT64_C(654311424),	// STPTR_D
    UINT64_C(620756992),	// STPTR_W
    UINT64_C(801112064),	// STR_D
    UINT64_C(792723456),	// STR_W
    UINT64_C(940572672),	// STX_B
    UINT64_C(941359104),	// STX_D
    UINT64_C(940834816),	// STX_H
    UINT64_C(941096960),	// STX_W
    UINT64_C(687865856),	// ST_B
    UINT64_C(700448768),	// ST_D
    UINT64_C(692060160),	// ST_H
    UINT64_C(696254464),	// ST_W
    UINT64_C(1146880),	// SUB_D
    UINT64_C(1114112),	// SUB_W
    UINT64_C(2818048),	// SYSCALL
    UINT64_C(105390080),	// TLBCLR
    UINT64_C(105395200),	// TLBFILL
    UINT64_C(105391104),	// TLBFLUSH
    UINT64_C(105393152),	// TLBRD
    UINT64_C(105392128),	// TLBSRCH
    UINT64_C(105394176),	// TLBWR
    UINT64_C(945816576),	// UD
    UINT64_C(1885339648),	// VABSD_B
    UINT64_C(1885470720),	// VABSD_BU
    UINT64_C(1885437952),	// VABSD_D
    UINT64_C(1885569024),	// VABSD_DU
    UINT64_C(1885372416),	// VABSD_H
    UINT64_C(1885503488),	// VABSD_HU
    UINT64_C(1885405184),	// VABSD_W
    UINT64_C(1885536256),	// VABSD_WU
    UINT64_C(1885077504),	// VADDA_B
    UINT64_C(1885175808),	// VADDA_D
    UINT64_C(1885110272),	// VADDA_H
    UINT64_C(1885143040),	// VADDA_W
    UINT64_C(1921646592),	// VADDI_BU
    UINT64_C(1921744896),	// VADDI_DU
    UINT64_C(1921679360),	// VADDI_HU
    UINT64_C(1921712128),	// VADDI_WU
    UINT64_C(1881079808),	// VADDWEV_D_W
    UINT64_C(1882128384),	// VADDWEV_D_WU
    UINT64_C(1883176960),	// VADDWEV_D_WU_W
    UINT64_C(1881014272),	// VADDWEV_H_B
    UINT64_C(1882062848),	// VADDWEV_H_BU
    UINT64_C(1883111424),	// VADDWEV_H_BU_B
    UINT64_C(1881112576),	// VADDWEV_Q_D
    UINT64_C(1882161152),	// VADDWEV_Q_DU
    UINT64_C(1883209728),	// VADDWEV_Q_DU_D
    UINT64_C(1881047040),	// VADDWEV_W_H
    UINT64_C(1882095616),	// VADDWEV_W_HU
    UINT64_C(1883144192),	// VADDWEV_W_HU_H
    UINT64_C(1881341952),	// VADDWOD_D_W
    UINT64_C(1882390528),	// VADDWOD_D_WU
    UINT64_C(1883308032),	// VADDWOD_D_WU_W
    UINT64_C(1881276416),	// VADDWOD_H_B
    UINT64_C(1882324992),	// VADDWOD_H_BU
    UINT64_C(1883242496),	// VADDWOD_H_BU_B
    UINT64_C(1881374720),	// VADDWOD_Q_D
    UINT64_C(1882423296),	// VADDWOD_Q_DU
    UINT64_C(1883340800),	// VADDWOD_Q_DU_D
    UINT64_C(1881309184),	// VADDWOD_W_H
    UINT64_C(1882357760),	// VADDWOD_W_HU
    UINT64_C(1883275264),	// VADDWOD_W_HU_H
    UINT64_C(1879703552),	// VADD_B
    UINT64_C(1879801856),	// VADD_D
    UINT64_C(1879736320),	// VADD_H
    UINT64_C(1898774528),	// VADD_Q
    UINT64_C(1879769088),	// VADD_W
    UINT64_C(1943011328),	// VANDI_B
    UINT64_C(1898446848),	// VANDN_V
    UINT64_C(1898315776),	// VAND_V
    UINT64_C(1885863936),	// VAVGR_B
    UINT64_C(1885995008),	// VAVGR_BU
    UINT64_C(1885962240),	// VAVGR_D
    UINT64_C(1886093312),	// VAVGR_DU
    UINT64_C(1885896704),	// VAVGR_H
    UINT64_C(1886027776),	// VAVGR_HU
    UINT64_C(1885929472),	// VAVGR_W
    UINT64_C(1886060544),	// VAVGR_WU
    UINT64_C(1885601792),	// VAVG_B
    UINT64_C(1885732864),	// VAVG_BU
    UINT64_C(1885700096),	// VAVG_D
    UINT64_C(1885831168),	// VAVG_DU
    UINT64_C(1885634560),	// VAVG_H
    UINT64_C(1885765632),	// VAVG_HU
    UINT64_C(1885667328),	// VAVG_W
    UINT64_C(1885798400),	// VAVG_WU
    UINT64_C(1930436608),	// VBITCLRI_B
    UINT64_C(1930493952),	// VBITCLRI_D
    UINT64_C(1930444800),	// VBITCLRI_H
    UINT64_C(1930461184),	// VBITCLRI_W
    UINT64_C(1896611840),	// VBITCLR_B
    UINT64_C(1896710144),	// VBITCLR_D
    UINT64_C(1896644608),	// VBITCLR_H
    UINT64_C(1896677376),	// VBITCLR_W
    UINT64_C(1930960896),	// VBITREVI_B
    UINT64_C(1931018240),	// VBITREVI_D
    UINT64_C(1930969088),	// VBITREVI_H
    UINT64_C(1930985472),	// VBITREVI_W
    UINT64_C(1896873984),	// VBITREV_B
    UINT64_C(1896972288),	// VBITREV_D
    UINT64_C(1896906752),	// VBITREV_H
    UINT64_C(1896939520),	// VBITREV_W
    UINT64_C(1942224896),	// VBITSELI_B
    UINT64_C(219152384),	// VBITSEL_V
    UINT64_C(1930698752),	// VBITSETI_B
    UINT64_C(1930756096),	// VBITSETI_D
    UINT64_C(1930706944),	// VBITSETI_H
    UINT64_C(1930723328),	// VBITSETI_W
    UINT64_C(1896742912),	// VBITSET_B
    UINT64_C(1896841216),	// VBITSET_D
    UINT64_C(1896775680),	// VBITSET_H
    UINT64_C(1896808448),	// VBITSET_W
    UINT64_C(1921908736),	// VBSLL_V
    UINT64_C(1921941504),	// VBSRL_V
    UINT64_C(1922826240),	// VCLO_B
    UINT64_C(1922829312),	// VCLO_D
    UINT64_C(1922827264),	// VCLO_H
    UINT64_C(1922828288),	// VCLO_W
    UINT64_C(1922830336),	// VCLZ_B
    UINT64_C(1922833408),	// VCLZ_D
    UINT64_C(1922831360),	// VCLZ_H
    UINT64_C(1922832384),	// VCLZ_W
    UINT64_C(1893728256),	// VDIV_B
    UINT64_C(1893990400),	// VDIV_BU
    UINT64_C(1893826560),	// VDIV_D
    UINT64_C(1894088704),	// VDIV_DU
    UINT64_C(1893761024),	// VDIV_H
    UINT64_C(1894023168),	// VDIV_HU
    UINT64_C(1893793792),	// VDIV_W
    UINT64_C(1894055936),	// VDIV_WU
    UINT64_C(1990144000),	// VEXT2XV_DU_BU
    UINT64_C(1990146048),	// VEXT2XV_DU_HU
    UINT64_C(1990147072),	// VEXT2XV_DU_WU
    UINT64_C(1990137856),	// VEXT2XV_D_B
    UINT64_C(1990139904),	// VEXT2XV_D_H
    UINT64_C(1990140928),	// VEXT2XV_D_W
    UINT64_C(1990141952),	// VEXT2XV_HU_BU
    UINT64_C(1990135808),	// VEXT2XV_H_B
    UINT64_C(1990142976),	// VEXT2XV_WU_BU
    UINT64_C(1990145024),	// VEXT2XV_WU_HU
    UINT64_C(1990136832),	// VEXT2XV_W_B
    UINT64_C(1990138880),	// VEXT2XV_W_H
    UINT64_C(1923020800),	// VEXTH_DU_WU
    UINT64_C(1923016704),	// VEXTH_D_W
    UINT64_C(1923018752),	// VEXTH_HU_BU
    UINT64_C(1923014656),	// VEXTH_H_B
    UINT64_C(1923021824),	// VEXTH_QU_DU
    UINT64_C(1923017728),	// VEXTH_Q_D
    UINT64_C(1923019776),	// VEXTH_WU_HU
    UINT64_C(1923015680),	// VEXTH_W_H
    UINT64_C(1930231808),	// VEXTL_QU_DU
    UINT64_C(1929969664),	// VEXTL_Q_D
    UINT64_C(1938554880),	// VEXTRINS_B
    UINT64_C(1937768448),	// VEXTRINS_D
    UINT64_C(1938292736),	// VEXTRINS_H
    UINT64_C(1938030592),	// VEXTRINS_W
    UINT64_C(1899036672),	// VFADD_D
    UINT64_C(1899003904),	// VFADD_S
    UINT64_C(1922881536),	// VFCLASS_D
    UINT64_C(1922880512),	// VFCLASS_S
    UINT64_C(207618048),	// VFCMP_CAF_D
    UINT64_C(206569472),	// VFCMP_CAF_S
    UINT64_C(207749120),	// VFCMP_CEQ_D
    UINT64_C(206700544),	// VFCMP_CEQ_S
    UINT64_C(207814656),	// VFCMP_CLE_D
    UINT64_C(206766080),	// VFCMP_CLE_S
    UINT64_C(207683584),	// VFCMP_CLT_D
    UINT64_C(206635008),	// VFCMP_CLT_S
    UINT64_C(208142336),	// VFCMP_CNE_D
    UINT64_C(207093760),	// VFCMP_CNE_S
    UINT64_C(208273408),	// VFCMP_COR_D
    UINT64_C(207224832),	// VFCMP_COR_S
    UINT64_C(208011264),	// VFCMP_CUEQ_D
    UINT64_C(206962688),	// VFCMP_CUEQ_S
    UINT64_C(208076800),	// VFCMP_CULE_D
    UINT64_C(207028224),	// VFCMP_CULE_S
    UINT64_C(207945728),	// VFCMP_CULT_D
    UINT64_C(206897152),	// VFCMP_CULT_S
    UINT64_C(208404480),	// VFCMP_CUNE_D
    UINT64_C(207355904),	// VFCMP_CUNE_S
    UINT64_C(207880192),	// VFCMP_CUN_D
    UINT64_C(206831616),	// VFCMP_CUN_S
    UINT64_C(207650816),	// VFCMP_SAF_D
    UINT64_C(206602240),	// VFCMP_SAF_S
    UINT64_C(207781888),	// VFCMP_SEQ_D
    UINT64_C(206733312),	// VFCMP_SEQ_S
    UINT64_C(207847424),	// VFCMP_SLE_D
    UINT64_C(206798848),	// VFCMP_SLE_S
    UINT64_C(207716352),	// VFCMP_SLT_D
    UINT64_C(206667776),	// VFCMP_SLT_S
    UINT64_C(208175104),	// VFCMP_SNE_D
    UINT64_C(207126528),	// VFCMP_SNE_S
    UINT64_C(208306176),	// VFCMP_SOR_D
    UINT64_C(207257600),	// VFCMP_SOR_S
    UINT64_C(208044032),	// VFCMP_SUEQ_D
    UINT64_C(206995456),	// VFCMP_SUEQ_S
    UINT64_C(208109568),	// VFCMP_SULE_D
    UINT64_C(207060992),	// VFCMP_SULE_S
    UINT64_C(207978496),	// VFCMP_SULT_D
    UINT64_C(206929920),	// VFCMP_SULT_S
    UINT64_C(208437248),	// VFCMP_SUNE_D
    UINT64_C(207388672),	// VFCMP_SUNE_S
    UINT64_C(207912960),	// VFCMP_SUN_D
    UINT64_C(206864384),	// VFCMP_SUN_S
    UINT64_C(1922954240),	// VFCVTH_D_S
    UINT64_C(1922952192),	// VFCVTH_S_H
    UINT64_C(1922953216),	// VFCVTL_D_S
    UINT64_C(1922951168),	// VFCVTL_S_H
    UINT64_C(1900412928),	// VFCVT_H_S
    UINT64_C(1900445696),	// VFCVT_S_D
    UINT64_C(1899692032),	// VFDIV_D
    UINT64_C(1899659264),	// VFDIV_S
    UINT64_C(1922962432),	// VFFINTH_D_W
    UINT64_C(1922961408),	// VFFINTL_D_W
    UINT64_C(1922959360),	// VFFINT_D_L
    UINT64_C(1922960384),	// VFFINT_D_LU
    UINT64_C(1900544000),	// VFFINT_S_L
    UINT64_C(1922957312),	// VFFINT_S_W
    UINT64_C(1922958336),	// VFFINT_S_WU
    UINT64_C(1922877440),	// VFLOGB_D
    UINT64_C(1922876416),	// VFLOGB_S
    UINT64_C(153092096),	// VFMADD_D
    UINT64_C(152043520),	// VFMADD_S
    UINT64_C(1900085248),	// VFMAXA_D
    UINT64_C(1900052480),	// VFMAXA_S
    UINT64_C(1899823104),	// VFMAX_D
    UINT64_C(1899790336),	// VFMAX_S
    UINT64_C(1900216320),	// VFMINA_D
    UINT64_C(1900183552),	// VFMINA_S
    UINT64_C(1899954176),	// VFMIN_D
    UINT64_C(1899921408),	// VFMIN_S
    UINT64_C(157286400),	// VFMSUB_D
    UINT64_C(156237824),	// VFMSUB_S
    UINT64_C(1899560960),	// VFMUL_D
    UINT64_C(1899528192),	// VFMUL_S
    UINT64_C(161480704),	// VFNMADD_D
    UINT64_C(160432128),	// VFNMADD_S
    UINT64_C(165675008),	// VFNMSUB_D
    UINT64_C(164626432),	// VFNMSUB_S
    UINT64_C(1922897920),	// VFRECIPE_D
    UINT64_C(1922896896),	// VFRECIPE_S
    UINT64_C(1922889728),	// VFRECIP_D
    UINT64_C(1922888704),	// VFRECIP_S
    UINT64_C(1922910208),	// VFRINTRM_D
    UINT64_C(1922909184),	// VFRINTRM_S
    UINT64_C(1922922496),	// VFRINTRNE_D
    UINT64_C(1922921472),	// VFRINTRNE_S
    UINT64_C(1922914304),	// VFRINTRP_D
    UINT64_C(1922913280),	// VFRINTRP_S
    UINT64_C(1922918400),	// VFRINTRZ_D
    UINT64_C(1922917376),	// VFRINTRZ_S
    UINT64_C(1922906112),	// VFRINT_D
    UINT64_C(1922905088),	// VFRINT_S
    UINT64_C(1922902016),	// VFRSQRTE_D
    UINT64_C(1922900992),	// VFRSQRTE_S
    UINT64_C(1922893824),	// VFRSQRT_D
    UINT64_C(1922892800),	// VFRSQRT_S
    UINT64_C(1922695168),	// VFRSTPI_B
    UINT64_C(1922727936),	// VFRSTPI_H
    UINT64_C(1898643456),	// VFRSTP_B
    UINT64_C(1898676224),	// VFRSTP_H
    UINT64_C(1922885632),	// VFSQRT_D
    UINT64_C(1922884608),	// VFSQRT_S
    UINT64_C(1899167744),	// VFSUB_D
    UINT64_C(1899134976),	// VFSUB_S
    UINT64_C(1922991104),	// VFTINTH_L_S
    UINT64_C(1922990080),	// VFTINTL_L_S
    UINT64_C(1922993152),	// VFTINTRMH_L_S
    UINT64_C(1922992128),	// VFTINTRML_L_S
    UINT64_C(1922972672),	// VFTINTRM_L_D
    UINT64_C(1900675072),	// VFTINTRM_W_D
    UINT64_C(1922971648),	// VFTINTRM_W_S
    UINT64_C(1922999296),	// VFTINTRNEH_L_S
    UINT64_C(1922998272),	// VFTINTRNEL_L_S
    UINT64_C(1922978816),	// VFTINTRNE_L_D
    UINT64_C(1900773376),	// VFTINTRNE_W_D
    UINT64_C(1922977792),	// VFTINTRNE_W_S
    UINT64_C(1922995200),	// VFTINTRPH_L_S
    UINT64_C(1922994176),	// VFTINTRPL_L_S
    UINT64_C(1922974720),	// VFTINTRP_L_D
    UINT64_C(1900707840),	// VFTINTRP_W_D
    UINT64_C(1922973696),	// VFTINTRP_W_S
    UINT64_C(1922997248),	// VFTINTRZH_L_S
    UINT64_C(1922996224),	// VFTINTRZL_L_S
    UINT64_C(1922987008),	// VFTINTRZ_LU_D
    UINT64_C(1922976768),	// VFTINTRZ_L_D
    UINT64_C(1922985984),	// VFTINTRZ_WU_S
    UINT64_C(1900740608),	// VFTINTRZ_W_D
    UINT64_C(1922975744),	// VFTINTRZ_W_S
    UINT64_C(1922980864),	// VFTINT_LU_D
    UINT64_C(1922970624),	// VFTINT_L_D
    UINT64_C(1922979840),	// VFTINT_WU_S
    UINT64_C(1900642304),	// VFTINT_W_D
    UINT64_C(1922969600),	// VFTINT_W_S
    UINT64_C(1884880896),	// VHADDW_DU_WU
    UINT64_C(1884618752),	// VHADDW_D_W
    UINT64_C(1884815360),	// VHADDW_HU_BU
    UINT64_C(1884553216),	// VHADDW_H_B
    UINT64_C(1884913664),	// VHADDW_QU_DU
    UINT64_C(1884651520),	// VHADDW_Q_D
    UINT64_C(1884848128),	// VHADDW_WU_HU
    UINT64_C(1884585984),	// VHADDW_W_H
    UINT64_C(1885011968),	// VHSUBW_DU_WU
    UINT64_C(1884749824),	// VHSUBW_D_W
    UINT64_C(1884946432),	// VHSUBW_HU_BU
    UINT64_C(1884684288),	// VHSUBW_H_B
    UINT64_C(1885044736),	// VHSUBW_QU_DU
    UINT64_C(1884782592),	// VHSUBW_Q_D
    UINT64_C(1884979200),	// VHSUBW_WU_HU
    UINT64_C(1884717056),	// VHSUBW_W_H
    UINT64_C(1897660416),	// VILVH_B
    UINT64_C(1897758720),	// VILVH_D
    UINT64_C(1897693184),	// VILVH_H
    UINT64_C(1897725952),	// VILVH_W
    UINT64_C(1897529344),	// VILVL_B
    UINT64_C(1897627648),	// VILVL_D
    UINT64_C(1897562112),	// VILVL_H
    UINT64_C(1897594880),	// VILVL_W
    UINT64_C(1928036352),	// VINSGR2VR_B
    UINT64_C(1928065024),	// VINSGR2VR_D
    UINT64_C(1928052736),	// VINSGR2VR_H
    UINT64_C(1928060928),	// VINSGR2VR_W
    UINT64_C(738197504),	// VLD
    UINT64_C(1944059904),	// VLDI
    UINT64_C(813694976),	// VLDREPL_B
    UINT64_C(806354944),	// VLDREPL_D
    UINT64_C(809500672),	// VLDREPL_H
    UINT64_C(807403520),	// VLDREPL_W
    UINT64_C(943718400),	// VLDX
    UINT64_C(1890385920),	// VMADDWEV_D_W
    UINT64_C(1890910208),	// VMADDWEV_D_WU
    UINT64_C(1891434496),	// VMADDWEV_D_WU_W
    UINT64_C(1890320384),	// VMADDWEV_H_B
    UINT64_C(1890844672),	// VMADDWEV_H_BU
    UINT64_C(1891368960),	// VMADDWEV_H_BU_B
    UINT64_C(1890418688),	// VMADDWEV_Q_D
    UINT64_C(1890942976),	// VMADDWEV_Q_DU
    UINT64_C(1891467264),	// VMADDWEV_Q_DU_D
    UINT64_C(1890353152),	// VMADDWEV_W_H
    UINT64_C(1890877440),	// VMADDWEV_W_HU
    UINT64_C(1891401728),	// VMADDWEV_W_HU_H
    UINT64_C(1890516992),	// VMADDWOD_D_W
    UINT64_C(1891041280),	// VMADDWOD_D_WU
    UINT64_C(1891565568),	// VMADDWOD_D_WU_W
    UINT64_C(1890451456),	// VMADDWOD_H_B
    UINT64_C(1890975744),	// VMADDWOD_H_BU
    UINT64_C(1891500032),	// VMADDWOD_H_BU_B
    UINT64_C(1890549760),	// VMADDWOD_Q_D
    UINT64_C(1891074048),	// VMADDWOD_Q_DU
    UINT64_C(1891598336),	// VMADDWOD_Q_DU_D
    UINT64_C(1890484224),	// VMADDWOD_W_H
    UINT64_C(1891008512),	// VMADDWOD_W_HU
    UINT64_C(1891532800),	// VMADDWOD_W_HU_H
    UINT64_C(1890058240),	// VMADD_B
    UINT64_C(1890156544),	// VMADD_D
    UINT64_C(1890091008),	// VMADD_H
    UINT64_C(1890123776),	// VMADD_W
    UINT64_C(1922039808),	// VMAXI_B
    UINT64_C(1922301952),	// VMAXI_BU
    UINT64_C(1922138112),	// VMAXI_D
    UINT64_C(1922400256),	// VMAXI_DU
    UINT64_C(1922072576),	// VMAXI_H
    UINT64_C(1922334720),	// VMAXI_HU
    UINT64_C(1922105344),	// VMAXI_W
    UINT64_C(1922367488),	// VMAXI_WU
    UINT64_C(1886388224),	// VMAX_B
    UINT64_C(1886650368),	// VMAX_BU
    UINT64_C(1886486528),	// VMAX_D
    UINT64_C(1886748672),	// VMAX_DU
    UINT64_C(1886420992),	// VMAX_H
    UINT64_C(1886683136),	// VMAX_HU
    UINT64_C(1886453760),	// VMAX_W
    UINT64_C(1886715904),	// VMAX_WU
    UINT64_C(1922170880),	// VMINI_B
    UINT64_C(1922433024),	// VMINI_BU
    UINT64_C(1922269184),	// VMINI_D
    UINT64_C(1922531328),	// VMINI_DU
    UINT64_C(1922203648),	// VMINI_H
    UINT64_C(1922465792),	// VMINI_HU
    UINT64_C(1922236416),	// VMINI_W
    UINT64_C(1922498560),	// VMINI_WU
    UINT64_C(1886519296),	// VMIN_B
    UINT64_C(1886781440),	// VMIN_BU
    UINT64_C(1886617600),	// VMIN_D
    UINT64_C(1886879744),	// VMIN_DU
    UINT64_C(1886552064),	// VMIN_H
    UINT64_C(1886814208),	// VMIN_HU
    UINT64_C(1886584832),	// VMIN_W
    UINT64_C(1886846976),	// VMIN_WU
    UINT64_C(1893859328),	// VMOD_B
    UINT64_C(1894121472),	// VMOD_BU
    UINT64_C(1893957632),	// VMOD_D
    UINT64_C(1894219776),	// VMOD_DU
    UINT64_C(1893892096),	// VMOD_H
    UINT64_C(1894154240),	// VMOD_HU
    UINT64_C(1893924864),	// VMOD_W
    UINT64_C(1894187008),	// VMOD_WU
    UINT64_C(1922846720),	// VMSKGEZ_B
    UINT64_C(1922842624),	// VMSKLTZ_B
    UINT64_C(1922845696),	// VMSKLTZ_D
    UINT64_C(1922843648),	// VMSKLTZ_H
    UINT64_C(1922844672),	// VMSKLTZ_W
    UINT64_C(1922850816),	// VMSKNZ_B
    UINT64_C(1890189312),	// VMSUB_B
    UINT64_C(1890287616),	// VMSUB_D
    UINT64_C(1890222080),	// VMSUB_H
    UINT64_C(1890254848),	// VMSUB_W
    UINT64_C(1887830016),	// VMUH_B
    UINT64_C(1887961088),	// VMUH_BU
    UINT64_C(1887928320),	// VMUH_D
    UINT64_C(1888059392),	// VMUH_DU
    UINT64_C(1887862784),	// VMUH_H
    UINT64_C(1887993856),	// VMUH_HU
    UINT64_C(1887895552),	// VMUH_W
    UINT64_C(1888026624),	// VMUH_WU
    UINT64_C(1888550912),	// VMULWEV_D_W
    UINT64_C(1889075200),	// VMULWEV_D_WU
    UINT64_C(1889599488),	// VMULWEV_D_WU_W
    UINT64_C(1888485376),	// VMULWEV_H_B
    UINT64_C(1889009664),	// VMULWEV_H_BU
    UINT64_C(1889533952),	// VMULWEV_H_BU_B
    UINT64_C(1888583680),	// VMULWEV_Q_D
    UINT64_C(1889107968),	// VMULWEV_Q_DU
    UINT64_C(1889632256),	// VMULWEV_Q_DU_D
    UINT64_C(1888518144),	// VMULWEV_W_H
    UINT64_C(1889042432),	// VMULWEV_W_HU
    UINT64_C(1889566720),	// VMULWEV_W_HU_H
    UINT64_C(1888681984),	// VMULWOD_D_W
    UINT64_C(1889206272),	// VMULWOD_D_WU
    UINT64_C(1889730560),	// VMULWOD_D_WU_W
    UINT64_C(1888616448),	// VMULWOD_H_B
    UINT64_C(1889140736),	// VMULWOD_H_BU
    UINT64_C(1889665024),	// VMULWOD_H_BU_B
    UINT64_C(1888714752),	// VMULWOD_Q_D
    UINT64_C(1889239040),	// VMULWOD_Q_DU
    UINT64_C(1889763328),	// VMULWOD_Q_DU_D
    UINT64_C(1888649216),	// VMULWOD_W_H
    UINT64_C(1889173504),	// VMULWOD_W_HU
    UINT64_C(1889697792),	// VMULWOD_W_HU_H
    UINT64_C(1887698944),	// VMUL_B
    UINT64_C(1887797248),	// VMUL_D
    UINT64_C(1887731712),	// VMUL_H
    UINT64_C(1887764480),	// VMUL_W
    UINT64_C(1922838528),	// VNEG_B
    UINT64_C(1922841600),	// VNEG_D
    UINT64_C(1922839552),	// VNEG_H
    UINT64_C(1922840576),	// VNEG_W
    UINT64_C(1943797760),	// VNORI_B
    UINT64_C(1898414080),	// VNOR_V
    UINT64_C(1943273472),	// VORI_B
    UINT64_C(1898479616),	// VORN_V
    UINT64_C(1898348544),	// VOR_V
    UINT64_C(1897267200),	// VPACKEV_B
    UINT64_C(1897365504),	// VPACKEV_D
    UINT64_C(1897299968),	// VPACKEV_H
    UINT64_C(1897332736),	// VPACKEV_W
    UINT64_C(1897398272),	// VPACKOD_B
    UINT64_C(1897496576),	// VPACKOD_D
    UINT64_C(1897431040),	// VPACKOD_H
    UINT64_C(1897463808),	// VPACKOD_W
    UINT64_C(1922834432),	// VPCNT_B
    UINT64_C(1922837504),	// VPCNT_D
    UINT64_C(1922835456),	// VPCNT_H
    UINT64_C(1922836480),	// VPCNT_W
    UINT64_C(1944322048),	// VPERMI_W
    UINT64_C(1897791488),	// VPICKEV_B
    UINT64_C(1897889792),	// VPICKEV_D
    UINT64_C(1897824256),	// VPICKEV_H
    UINT64_C(1897857024),	// VPICKEV_W
    UINT64_C(1897922560),	// VPICKOD_B
    UINT64_C(1898020864),	// VPICKOD_D
    UINT64_C(1897955328),	// VPICKOD_H
    UINT64_C(1897988096),	// VPICKOD_W
    UINT64_C(1928298496),	// VPICKVE2GR_B
    UINT64_C(1928560640),	// VPICKVE2GR_BU
    UINT64_C(1928327168),	// VPICKVE2GR_D
    UINT64_C(1928589312),	// VPICKVE2GR_DU
    UINT64_C(1928314880),	// VPICKVE2GR_H
    UINT64_C(1928577024),	// VPICKVE2GR_HU
    UINT64_C(1928323072),	// VPICKVE2GR_W
    UINT64_C(1928585216),	// VPICKVE2GR_WU
    UINT64_C(1923022848),	// VREPLGR2VR_B
    UINT64_C(1923025920),	// VREPLGR2VR_D
    UINT64_C(1923023872),	// VREPLGR2VR_H
    UINT64_C(1923024896),	// VREPLGR2VR_W
    UINT64_C(1928822784),	// VREPLVEI_B
    UINT64_C(1928851456),	// VREPLVEI_D
    UINT64_C(1928839168),	// VREPLVEI_H
    UINT64_C(1928847360),	// VREPLVEI_W
    UINT64_C(1898053632),	// VREPLVE_B
    UINT64_C(1898151936),	// VREPLVE_D
    UINT64_C(1898086400),	// VREPLVE_H
    UINT64_C(1898119168),	// VREPLVE_W
    UINT64_C(1923096576),	// VROTRI_B
    UINT64_C(1923153920),	// VROTRI_D
    UINT64_C(1923104768),	// VROTRI_H
    UINT64_C(1923121152),	// VROTRI_W
    UINT64_C(1894645760),	// VROTR_B
    UINT64_C(1894744064),	// VROTR_D
    UINT64_C(1894678528),	// VROTR_H
    UINT64_C(1894711296),	// VROTR_W
    UINT64_C(1883635712),	// VSADD_B
    UINT64_C(1883897856),	// VSADD_BU
    UINT64_C(1883734016),	// VSADD_D
    UINT64_C(1883996160),	// VSADD_DU
    UINT64_C(1883668480),	// VSADD_H
    UINT64_C(1883930624),	// VSADD_HU
    UINT64_C(1883701248),	// VSADD_W
    UINT64_C(1883963392),	// VSADD_WU
    UINT64_C(1931747328),	// VSAT_B
    UINT64_C(1932009472),	// VSAT_BU
    UINT64_C(1931804672),	// VSAT_D
    UINT64_C(1932066816),	// VSAT_DU
    UINT64_C(1931755520),	// VSAT_H
    UINT64_C(1932017664),	// VSAT_HU
    UINT64_C(1931771904),	// VSAT_W
    UINT64_C(1932034048),	// VSAT_WU
    UINT64_C(1920991232),	// VSEQI_B
    UINT64_C(1921089536),	// VSEQI_D
    UINT64_C(1921024000),	// VSEQI_H
    UINT64_C(1921056768),	// VSEQI_W
    UINT64_C(1879048192),	// VSEQ_B
    UINT64_C(1879146496),	// VSEQ_D
    UINT64_C(1879080960),	// VSEQ_H
    UINT64_C(1879113728),	// VSEQ_W
    UINT64_C(1922871296),	// VSETALLNEZ_B
    UINT64_C(1922874368),	// VSETALLNEZ_D
    UINT64_C(1922872320),	// VSETALLNEZ_H
    UINT64_C(1922873344),	// VSETALLNEZ_W
    UINT64_C(1922867200),	// VSETANYEQZ_B
    UINT64_C(1922870272),	// VSETANYEQZ_D
    UINT64_C(1922868224),	// VSETANYEQZ_H
    UINT64_C(1922869248),	// VSETANYEQZ_W
    UINT64_C(1922865152),	// VSETEQZ_V
    UINT64_C(1922866176),	// VSETNEZ_V
    UINT64_C(1938817024),	// VSHUF4I_B
    UINT64_C(1939603456),	// VSHUF4I_D
    UINT64_C(1939079168),	// VSHUF4I_H
    UINT64_C(1939341312),	// VSHUF4I_W
    UINT64_C(223346688),	// VSHUF_B
    UINT64_C(1903919104),	// VSHUF_D
    UINT64_C(1903853568),	// VSHUF_H
    UINT64_C(1903886336),	// VSHUF_W
    UINT64_C(1898840064),	// VSIGNCOV_B
    UINT64_C(1898938368),	// VSIGNCOV_D
    UINT64_C(1898872832),	// VSIGNCOV_H
    UINT64_C(1898905600),	// VSIGNCOV_W
    UINT64_C(1921122304),	// VSLEI_B
    UINT64_C(1921253376),	// VSLEI_BU
    UINT64_C(1921220608),	// VSLEI_D
    UINT64_C(1921351680),	// VSLEI_DU
    UINT64_C(1921155072),	// VSLEI_H
    UINT64_C(1921286144),	// VSLEI_HU
    UINT64_C(1921187840),	// VSLEI_W
    UINT64_C(1921318912),	// VSLEI_WU
    UINT64_C(1879179264),	// VSLE_B
    UINT64_C(1879310336),	// VSLE_BU
    UINT64_C(1879277568),	// VSLE_D
    UINT64_C(1879408640),	// VSLE_DU
    UINT64_C(1879212032),	// VSLE_H
    UINT64_C(1879343104),	// VSLE_HU
    UINT64_C(1879244800),	// VSLE_W
    UINT64_C(1879375872),	// VSLE_WU
    UINT64_C(1932271616),	// VSLLI_B
    UINT64_C(1932328960),	// VSLLI_D
    UINT64_C(1932279808),	// VSLLI_H
    UINT64_C(1932296192),	// VSLLI_W
    UINT64_C(1930199040),	// VSLLWIL_DU_WU
    UINT64_C(1929936896),	// VSLLWIL_D_W
    UINT64_C(1930174464),	// VSLLWIL_HU_BU
    UINT64_C(1929912320),	// VSLLWIL_H_B
    UINT64_C(1930182656),	// VSLLWIL_WU_HU
    UINT64_C(1929920512),	// VSLLWIL_W_H
    UINT64_C(1894252544),	// VSLL_B
    UINT64_C(1894350848),	// VSLL_D
    UINT64_C(1894285312),	// VSLL_H
    UINT64_C(1894318080),	// VSLL_W
    UINT64_C(1921384448),	// VSLTI_B
    UINT64_C(1921515520),	// VSLTI_BU
    UINT64_C(1921482752),	// VSLTI_D
    UINT64_C(1921613824),	// VSLTI_DU
    UINT64_C(1921417216),	// VSLTI_H
    UINT64_C(1921548288),	// VSLTI_HU
    UINT64_C(1921449984),	// VSLTI_W
    UINT64_C(1921581056),	// VSLTI_WU
    UINT64_C(1879441408),	// VSLT_B
    UINT64_C(1879572480),	// VSLT_BU
    UINT64_C(1879539712),	// VSLT_D
    UINT64_C(1879670784),	// VSLT_DU
    UINT64_C(1879474176),	// VSLT_H
    UINT64_C(1879605248),	// VSLT_HU
    UINT64_C(1879506944),	// VSLT_W
    UINT64_C(1879638016),	// VSLT_WU
    UINT64_C(1932795904),	// VSRAI_B
    UINT64_C(1932853248),	// VSRAI_D
    UINT64_C(1932804096),	// VSRAI_H
    UINT64_C(1932820480),	// VSRAI_W
    UINT64_C(1935163392),	// VSRANI_B_H
    UINT64_C(1935278080),	// VSRANI_D_Q
    UINT64_C(1935179776),	// VSRANI_H_W
    UINT64_C(1935212544),	// VSRANI_W_D
    UINT64_C(1895202816),	// VSRAN_B_H
    UINT64_C(1895235584),	// VSRAN_H_W
    UINT64_C(1895268352),	// VSRAN_W_D
    UINT64_C(1923620864),	// VSRARI_B
    UINT64_C(1923678208),	// VSRARI_D
    UINT64_C(1923629056),	// VSRARI_H
    UINT64_C(1923645440),	// VSRARI_W
    UINT64_C(1935425536),	// VSRARNI_B_H
    UINT64_C(1935540224),	// VSRARNI_D_Q
    UINT64_C(1935441920),	// VSRARNI_H_W
    UINT64_C(1935474688),	// VSRARNI_W_D
    UINT64_C(1895464960),	// VSRARN_B_H
    UINT64_C(1895497728),	// VSRARN_H_W
    UINT64_C(1895530496),	// VSRARN_W_D
    UINT64_C(1894907904),	// VSRAR_B
    UINT64_C(1895006208),	// VSRAR_D
    UINT64_C(1894940672),	// VSRAR_H
    UINT64_C(1894973440),	// VSRAR_W
    UINT64_C(1894514688),	// VSRA_B
    UINT64_C(1894612992),	// VSRA_D
    UINT64_C(1894547456),	// VSRA_H
    UINT64_C(1894580224),	// VSRA_W
    UINT64_C(1932533760),	// VSRLI_B
    UINT64_C(1932591104),	// VSRLI_D
    UINT64_C(1932541952),	// VSRLI_H
    UINT64_C(1932558336),	// VSRLI_W
    UINT64_C(1933590528),	// VSRLNI_B_H
    UINT64_C(1933705216),	// VSRLNI_D_Q
    UINT64_C(1933606912),	// VSRLNI_H_W
    UINT64_C(1933639680),	// VSRLNI_W_D
    UINT64_C(1895071744),	// VSRLN_B_H
    UINT64_C(1895104512),	// VSRLN_H_W
    UINT64_C(1895137280),	// VSRLN_W_D
    UINT64_C(1923358720),	// VSRLRI_B
    UINT64_C(1923416064),	// VSRLRI_D
    UINT64_C(1923366912),	// VSRLRI_H
    UINT64_C(1923383296),	// VSRLRI_W
    UINT64_C(1933852672),	// VSRLRNI_B_H
    UINT64_C(1933967360),	// VSRLRNI_D_Q
    UINT64_C(1933869056),	// VSRLRNI_H_W
    UINT64_C(1933901824),	// VSRLRNI_W_D
    UINT64_C(1895333888),	// VSRLRN_B_H
    UINT64_C(1895366656),	// VSRLRN_H_W
    UINT64_C(1895399424),	// VSRLRN_W_D
    UINT64_C(1894776832),	// VSRLR_B
    UINT64_C(1894875136),	// VSRLR_D
    UINT64_C(1894809600),	// VSRLR_H
    UINT64_C(1894842368),	// VSRLR_W
    UINT64_C(1894383616),	// VSRL_B
    UINT64_C(1894481920),	// VSRL_D
    UINT64_C(1894416384),	// VSRL_H
    UINT64_C(1894449152),	// VSRL_W
    UINT64_C(1935949824),	// VSSRANI_BU_H
    UINT64_C(1935687680),	// VSSRANI_B_H
    UINT64_C(1936064512),	// VSSRANI_DU_Q
    UINT64_C(1935802368),	// VSSRANI_D_Q
    UINT64_C(1935966208),	// VSSRANI_HU_W
    UINT64_C(1935704064),	// VSSRANI_H_W
    UINT64_C(1935998976),	// VSSRANI_WU_D
    UINT64_C(1935736832),	// VSSRANI_W_D
    UINT64_C(1896251392),	// VSSRAN_BU_H
    UINT64_C(1895727104),	// VSSRAN_B_H
    UINT64_C(1896284160),	// VSSRAN_HU_W
    UINT64_C(1895759872),	// VSSRAN_H_W
    UINT64_C(1896316928),	// VSSRAN_WU_D
    UINT64_C(1895792640),	// VSSRAN_W_D
    UINT64_C(1936474112),	// VSSRARNI_BU_H
    UINT64_C(1936211968),	// VSSRARNI_B_H
    UINT64_C(1936588800),	// VSSRARNI_DU_Q
    UINT64_C(1936326656),	// VSSRARNI_D_Q
    UINT64_C(1936490496),	// VSSRARNI_HU_W
    UINT64_C(1936228352),	// VSSRARNI_H_W
    UINT64_C(1936523264),	// VSSRARNI_WU_D
    UINT64_C(1936261120),	// VSSRARNI_W_D
    UINT64_C(1896513536),	// VSSRARN_BU_H
    UINT64_C(1895989248),	// VSSRARN_B_H
    UINT64_C(1896546304),	// VSSRARN_HU_W
    UINT64_C(1896022016),	// VSSRARN_H_W
    UINT64_C(1896579072),	// VSSRARN_WU_D
    UINT64_C(1896054784),	// VSSRARN_W_D
    UINT64_C(1934376960),	// VSSRLNI_BU_H
    UINT64_C(1934114816),	// VSSRLNI_B_H
    UINT64_C(1934491648),	// VSSRLNI_DU_Q
    UINT64_C(1934229504),	// VSSRLNI_D_Q
    UINT64_C(1934393344),	// VSSRLNI_HU_W
    UINT64_C(1934131200),	// VSSRLNI_H_W
    UINT64_C(1934426112),	// VSSRLNI_WU_D
    UINT64_C(1934163968),	// VSSRLNI_W_D
    UINT64_C(1896120320),	// VSSRLN_BU_H
    UINT64_C(1895596032),	// VSSRLN_B_H
    UINT64_C(1896153088),	// VSSRLN_HU_W
    UINT64_C(1895628800),	// VSSRLN_H_W
    UINT64_C(1896185856),	// VSSRLN_WU_D
    UINT64_C(1895661568),	// VSSRLN_W_D
    UINT64_C(1934901248),	// VSSRLRNI_BU_H
    UINT64_C(1934639104),	// VSSRLRNI_B_H
    UINT64_C(1935015936),	// VSSRLRNI_DU_Q
    UINT64_C(1934753792),	// VSSRLRNI_D_Q
    UINT64_C(1934917632),	// VSSRLRNI_HU_W
    UINT64_C(1934655488),	// VSSRLRNI_H_W
    UINT64_C(1934950400),	// VSSRLRNI_WU_D
    UINT64_C(1934688256),	// VSSRLRNI_W_D
    UINT64_C(1896382464),	// VSSRLRN_BU_H
    UINT64_C(1895858176),	// VSSRLRN_B_H
    UINT64_C(1896415232),	// VSSRLRN_HU_W
    UINT64_C(1895890944),	// VSSRLRN_H_W
    UINT64_C(1896448000),	// VSSRLRN_WU_D
    UINT64_C(1895923712),	// VSSRLRN_W_D
    UINT64_C(1883766784),	// VSSUB_B
    UINT64_C(1884028928),	// VSSUB_BU
    UINT64_C(1883865088),	// VSSUB_D
    UINT64_C(1884127232),	// VSSUB_DU
    UINT64_C(1883799552),	// VSSUB_H
    UINT64_C(1884061696),	// VSSUB_HU
    UINT64_C(1883832320),	// VSSUB_W
    UINT64_C(1884094464),	// VSSUB_WU
    UINT64_C(742391808),	// VST
    UINT64_C(830472192),	// VSTELM_B
    UINT64_C(823132160),	// VSTELM_D
    UINT64_C(826277888),	// VSTELM_H
    UINT64_C(824180736),	// VSTELM_W
    UINT64_C(943980544),	// VSTX
    UINT64_C(1921777664),	// VSUBI_BU
    UINT64_C(1921875968),	// VSUBI_DU
    UINT64_C(1921810432),	// VSUBI_HU
    UINT64_C(1921843200),	// VSUBI_WU
    UINT64_C(1881210880),	// VSUBWEV_D_W
    UINT64_C(1882259456),	// VSUBWEV_D_WU
    UINT64_C(1881145344),	// VSUBWEV_H_B
    UINT64_C(1882193920),	// VSUBWEV_H_BU
    UINT64_C(1881243648),	// VSUBWEV_Q_D
    UINT64_C(1882292224),	// VSUBWEV_Q_DU
    UINT64_C(1881178112),	// VSUBWEV_W_H
    UINT64_C(1882226688),	// VSUBWEV_W_HU
    UINT64_C(1881473024),	// VSUBWOD_D_W
    UINT64_C(1882521600),	// VSUBWOD_D_WU
    UINT64_C(1881407488),	// VSUBWOD_H_B
    UINT64_C(1882456064),	// VSUBWOD_H_BU
    UINT64_C(1881505792),	// VSUBWOD_Q_D
    UINT64_C(1882554368),	// VSUBWOD_Q_DU
    UINT64_C(1881440256),	// VSUBWOD_W_H
    UINT64_C(1882488832),	// VSUBWOD_W_HU
    UINT64_C(1879834624),	// VSUB_B
    UINT64_C(1879932928),	// VSUB_D
    UINT64_C(1879867392),	// VSUB_H
    UINT64_C(1898807296),	// VSUB_Q
    UINT64_C(1879900160),	// VSUB_W
    UINT64_C(1943535616),	// VXORI_B
    UINT64_C(1898381312),	// VXOR_V
    UINT64_C(4128780),	// X86ADC_B
    UINT64_C(4128783),	// X86ADC_D
    UINT64_C(4128781),	// X86ADC_H
    UINT64_C(4128782),	// X86ADC_W
    UINT64_C(4128772),	// X86ADD_B
    UINT64_C(4128775),	// X86ADD_D
    UINT64_C(4128769),	// X86ADD_DU
    UINT64_C(4128773),	// X86ADD_H
    UINT64_C(4128774),	// X86ADD_W
    UINT64_C(4128768),	// X86ADD_WU
    UINT64_C(4161552),	// X86AND_B
    UINT64_C(4161555),	// X86AND_D
    UINT64_C(4161553),	// X86AND_H
    UINT64_C(4161554),	// X86AND_W
    UINT64_C(32808),	// X86CLRTM
    UINT64_C(32809),	// X86DECTOP
    UINT64_C(32772),	// X86DEC_B
    UINT64_C(32775),	// X86DEC_D
    UINT64_C(32773),	// X86DEC_H
    UINT64_C(32774),	// X86DEC_W
    UINT64_C(32777),	// X86INCTOP
    UINT64_C(32768),	// X86INC_B
    UINT64_C(32771),	// X86INC_D
    UINT64_C(32769),	// X86INC_H
    UINT64_C(32770),	// X86INC_W
    UINT64_C(6029312),	// X86MFFLAG
    UINT64_C(29696),	// X86MFTOP
    UINT64_C(6029344),	// X86MTFLAG
    UINT64_C(28672),	// X86MTTOP
    UINT64_C(4096000),	// X86MUL_B
    UINT64_C(4096004),	// X86MUL_BU
    UINT64_C(4096003),	// X86MUL_D
    UINT64_C(4096007),	// X86MUL_DU
    UINT64_C(4096001),	// X86MUL_H
    UINT64_C(4096005),	// X86MUL_HU
    UINT64_C(4096002),	// X86MUL_W
    UINT64_C(4096006),	// X86MUL_WU
    UINT64_C(4161556),	// X86OR_B
    UINT64_C(4161559),	// X86OR_D
    UINT64_C(4161557),	// X86OR_H
    UINT64_C(4161558),	// X86OR_W
    UINT64_C(5513240),	// X86RCLI_B
    UINT64_C(5570587),	// X86RCLI_D
    UINT64_C(5521433),	// X86RCLI_H
    UINT64_C(5537818),	// X86RCLI_W
    UINT64_C(4161548),	// X86RCL_B
    UINT64_C(4161551),	// X86RCL_D
    UINT64_C(4161549),	// X86RCL_H
    UINT64_C(4161550),	// X86RCL_W
    UINT64_C(5513232),	// X86RCRI_B
    UINT64_C(5570579),	// X86RCRI_D
    UINT64_C(5521425),	// X86RCRI_H
    UINT64_C(5537810),	// X86RCRI_W
    UINT64_C(4161544),	// X86RCR_B
    UINT64_C(4161547),	// X86RCR_D
    UINT64_C(4161545),	// X86RCR_H
    UINT64_C(4161546),	// X86RCR_W
    UINT64_C(5513236),	// X86ROTLI_B
    UINT64_C(5570583),	// X86ROTLI_D
    UINT64_C(5521429),	// X86ROTLI_H
    UINT64_C(5537814),	// X86ROTLI_W
    UINT64_C(4161540),	// X86ROTL_B
    UINT64_C(4161543),	// X86ROTL_D
    UINT64_C(4161541),	// X86ROTL_H
    UINT64_C(4161542),	// X86ROTL_W
    UINT64_C(5513228),	// X86ROTRI_B
    UINT64_C(5570575),	// X86ROTRI_D
    UINT64_C(5521421),	// X86ROTRI_H
    UINT64_C(5537806),	// X86ROTRI_W
    UINT64_C(4161536),	// X86ROTR_B
    UINT64_C(4161538),	// X86ROTR_D
    UINT64_C(4161537),	// X86ROTR_H
    UINT64_C(4161539),	// X86ROTR_W
    UINT64_C(4128784),	// X86SBC_B
    UINT64_C(4128787),	// X86SBC_D
    UINT64_C(4128785),	// X86SBC_H
    UINT64_C(4128786),	// X86SBC_W
    UINT64_C(5767168),	// X86SETTAG
    UINT64_C(32776),	// X86SETTM
    UINT64_C(5513216),	// X86SLLI_B
    UINT64_C(5570563),	// X86SLLI_D
    UINT64_C(5521409),	// X86SLLI_H
    UINT64_C(5537794),	// X86SLLI_W
    UINT64_C(4128788),	// X86SLL_B
    UINT64_C(4128791),	// X86SLL_D
    UINT64_C(4128789),	// X86SLL_H
    UINT64_C(4128790),	// X86SLL_W
    UINT64_C(5513224),	// X86SRAI_B
    UINT64_C(5570571),	// X86SRAI_D
    UINT64_C(5521417),	// X86SRAI_H
    UINT64_C(5537802),	// X86SRAI_W
    UINT64_C(4128796),	// X86SRA_B
    UINT64_C(4128799),	// X86SRA_D
    UINT64_C(4128797),	// X86SRA_H
    UINT64_C(4128798),	// X86SRA_W
    UINT64_C(5513220),	// X86SRLI_B
    UINT64_C(5570567),	// X86SRLI_D
    UINT64_C(5521413),	// X86SRLI_H
    UINT64_C(5537798),	// X86SRLI_W
    UINT64_C(4128792),	// X86SRL_B
    UINT64_C(4128795),	// X86SRL_D
    UINT64_C(4128793),	// X86SRL_H
    UINT64_C(4128794),	// X86SRL_W
    UINT64_C(4128776),	// X86SUB_B
    UINT64_C(4128779),	// X86SUB_D
    UINT64_C(4128771),	// X86SUB_DU
    UINT64_C(4128777),	// X86SUB_H
    UINT64_C(4128778),	// X86SUB_W
    UINT64_C(4128770),	// X86SUB_WU
    UINT64_C(4161560),	// X86XOR_B
    UINT64_C(4161563),	// X86XOR_D
    UINT64_C(4161561),	// X86XOR_H
    UINT64_C(4161562),	// X86XOR_W
    UINT64_C(1409024),	// XOR
    UINT64_C(62914560),	// XORI
    UINT64_C(1952448512),	// XVABSD_B
    UINT64_C(1952579584),	// XVABSD_BU
    UINT64_C(1952546816),	// XVABSD_D
    UINT64_C(1952677888),	// XVABSD_DU
    UINT64_C(1952481280),	// XVABSD_H
    UINT64_C(1952612352),	// XVABSD_HU
    UINT64_C(1952514048),	// XVABSD_W
    UINT64_C(1952645120),	// XVABSD_WU
    UINT64_C(1952186368),	// XVADDA_B
    UINT64_C(1952284672),	// XVADDA_D
    UINT64_C(1952219136),	// XVADDA_H
    UINT64_C(1952251904),	// XVADDA_W
    UINT64_C(1988755456),	// XVADDI_BU
    UINT64_C(1988853760),	// XVADDI_DU
    UINT64_C(1988788224),	// XVADDI_HU
    UINT64_C(1988820992),	// XVADDI_WU
    UINT64_C(1948188672),	// XVADDWEV_D_W
    UINT64_C(1949237248),	// XVADDWEV_D_WU
    UINT64_C(1950285824),	// XVADDWEV_D_WU_W
    UINT64_C(1948123136),	// XVADDWEV_H_B
    UINT64_C(1949171712),	// XVADDWEV_H_BU
    UINT64_C(1950220288),	// XVADDWEV_H_BU_B
    UINT64_C(1948221440),	// XVADDWEV_Q_D
    UINT64_C(1949270016),	// XVADDWEV_Q_DU
    UINT64_C(1950318592),	// XVADDWEV_Q_DU_D
    UINT64_C(1948155904),	// XVADDWEV_W_H
    UINT64_C(1949204480),	// XVADDWEV_W_HU
    UINT64_C(1950253056),	// XVADDWEV_W_HU_H
    UINT64_C(1948450816),	// XVADDWOD_D_W
    UINT64_C(1949499392),	// XVADDWOD_D_WU
    UINT64_C(1950416896),	// XVADDWOD_D_WU_W
    UINT64_C(1948385280),	// XVADDWOD_H_B
    UINT64_C(1949433856),	// XVADDWOD_H_BU
    UINT64_C(1950351360),	// XVADDWOD_H_BU_B
    UINT64_C(1948483584),	// XVADDWOD_Q_D
    UINT64_C(1949532160),	// XVADDWOD_Q_DU
    UINT64_C(1950449664),	// XVADDWOD_Q_DU_D
    UINT64_C(1948418048),	// XVADDWOD_W_H
    UINT64_C(1949466624),	// XVADDWOD_W_HU
    UINT64_C(1950384128),	// XVADDWOD_W_HU_H
    UINT64_C(1946812416),	// XVADD_B
    UINT64_C(1946910720),	// XVADD_D
    UINT64_C(1946845184),	// XVADD_H
    UINT64_C(1965883392),	// XVADD_Q
    UINT64_C(1946877952),	// XVADD_W
    UINT64_C(2010120192),	// XVANDI_B
    UINT64_C(1965555712),	// XVANDN_V
    UINT64_C(1965424640),	// XVAND_V
    UINT64_C(1952972800),	// XVAVGR_B
    UINT64_C(1953103872),	// XVAVGR_BU
    UINT64_C(1953071104),	// XVAVGR_D
    UINT64_C(1953202176),	// XVAVGR_DU
    UINT64_C(1953005568),	// XVAVGR_H
    UINT64_C(1953136640),	// XVAVGR_HU
    UINT64_C(1953038336),	// XVAVGR_W
    UINT64_C(1953169408),	// XVAVGR_WU
    UINT64_C(1952710656),	// XVAVG_B
    UINT64_C(1952841728),	// XVAVG_BU
    UINT64_C(1952808960),	// XVAVG_D
    UINT64_C(1952940032),	// XVAVG_DU
    UINT64_C(1952743424),	// XVAVG_H
    UINT64_C(1952874496),	// XVAVG_HU
    UINT64_C(1952776192),	// XVAVG_W
    UINT64_C(1952907264),	// XVAVG_WU
    UINT64_C(1997545472),	// XVBITCLRI_B
    UINT64_C(1997602816),	// XVBITCLRI_D
    UINT64_C(1997553664),	// XVBITCLRI_H
    UINT64_C(1997570048),	// XVBITCLRI_W
    UINT64_C(1963720704),	// XVBITCLR_B
    UINT64_C(1963819008),	// XVBITCLR_D
    UINT64_C(1963753472),	// XVBITCLR_H
    UINT64_C(1963786240),	// XVBITCLR_W
    UINT64_C(1998069760),	// XVBITREVI_B
    UINT64_C(1998127104),	// XVBITREVI_D
    UINT64_C(1998077952),	// XVBITREVI_H
    UINT64_C(1998094336),	// XVBITREVI_W
    UINT64_C(1963982848),	// XVBITREV_B
    UINT64_C(1964081152),	// XVBITREV_D
    UINT64_C(1964015616),	// XVBITREV_H
    UINT64_C(1964048384),	// XVBITREV_W
    UINT64_C(2009333760),	// XVBITSELI_B
    UINT64_C(220200960),	// XVBITSEL_V
    UINT64_C(1997807616),	// XVBITSETI_B
    UINT64_C(1997864960),	// XVBITSETI_D
    UINT64_C(1997815808),	// XVBITSETI_H
    UINT64_C(1997832192),	// XVBITSETI_W
    UINT64_C(1963851776),	// XVBITSET_B
    UINT64_C(1963950080),	// XVBITSET_D
    UINT64_C(1963884544),	// XVBITSET_H
    UINT64_C(1963917312),	// XVBITSET_W
    UINT64_C(1989017600),	// XVBSLL_V
    UINT64_C(1989050368),	// XVBSRL_V
    UINT64_C(1989935104),	// XVCLO_B
    UINT64_C(1989938176),	// XVCLO_D
    UINT64_C(1989936128),	// XVCLO_H
    UINT64_C(1989937152),	// XVCLO_W
    UINT64_C(1989939200),	// XVCLZ_B
    UINT64_C(1989942272),	// XVCLZ_D
    UINT64_C(1989940224),	// XVCLZ_H
    UINT64_C(1989941248),	// XVCLZ_W
    UINT64_C(1960837120),	// XVDIV_B
    UINT64_C(1961099264),	// XVDIV_BU
    UINT64_C(1960935424),	// XVDIV_D
    UINT64_C(1961197568),	// XVDIV_DU
    UINT64_C(1960869888),	// XVDIV_H
    UINT64_C(1961132032),	// XVDIV_HU
    UINT64_C(1960902656),	// XVDIV_W
    UINT64_C(1961164800),	// XVDIV_WU
    UINT64_C(1990129664),	// XVEXTH_DU_WU
    UINT64_C(1990125568),	// XVEXTH_D_W
    UINT64_C(1990127616),	// XVEXTH_HU_BU
    UINT64_C(1990123520),	// XVEXTH_H_B
    UINT64_C(1990130688),	// XVEXTH_QU_DU
    UINT64_C(1990126592),	// XVEXTH_Q_D
    UINT64_C(1990128640),	// XVEXTH_WU_HU
    UINT64_C(1990124544),	// XVEXTH_W_H
    UINT64_C(1997340672),	// XVEXTL_QU_DU
    UINT64_C(1997078528),	// XVEXTL_Q_D
    UINT64_C(2005663744),	// XVEXTRINS_B
    UINT64_C(2004877312),	// XVEXTRINS_D
    UINT64_C(2005401600),	// XVEXTRINS_H
    UINT64_C(2005139456),	// XVEXTRINS_W
    UINT64_C(1966145536),	// XVFADD_D
    UINT64_C(1966112768),	// XVFADD_S
    UINT64_C(1989990400),	// XVFCLASS_D
    UINT64_C(1989989376),	// XVFCLASS_S
    UINT64_C(211812352),	// XVFCMP_CAF_D
    UINT64_C(210763776),	// XVFCMP_CAF_S
    UINT64_C(211943424),	// XVFCMP_CEQ_D
    UINT64_C(210894848),	// XVFCMP_CEQ_S
    UINT64_C(212008960),	// XVFCMP_CLE_D
    UINT64_C(210960384),	// XVFCMP_CLE_S
    UINT64_C(211877888),	// XVFCMP_CLT_D
    UINT64_C(210829312),	// XVFCMP_CLT_S
    UINT64_C(212336640),	// XVFCMP_CNE_D
    UINT64_C(211288064),	// XVFCMP_CNE_S
    UINT64_C(212467712),	// XVFCMP_COR_D
    UINT64_C(211419136),	// XVFCMP_COR_S
    UINT64_C(212205568),	// XVFCMP_CUEQ_D
    UINT64_C(211156992),	// XVFCMP_CUEQ_S
    UINT64_C(212271104),	// XVFCMP_CULE_D
    UINT64_C(211222528),	// XVFCMP_CULE_S
    UINT64_C(212140032),	// XVFCMP_CULT_D
    UINT64_C(211091456),	// XVFCMP_CULT_S
    UINT64_C(212598784),	// XVFCMP_CUNE_D
    UINT64_C(211550208),	// XVFCMP_CUNE_S
    UINT64_C(212074496),	// XVFCMP_CUN_D
    UINT64_C(211025920),	// XVFCMP_CUN_S
    UINT64_C(211845120),	// XVFCMP_SAF_D
    UINT64_C(210796544),	// XVFCMP_SAF_S
    UINT64_C(211976192),	// XVFCMP_SEQ_D
    UINT64_C(210927616),	// XVFCMP_SEQ_S
    UINT64_C(212041728),	// XVFCMP_SLE_D
    UINT64_C(210993152),	// XVFCMP_SLE_S
    UINT64_C(211910656),	// XVFCMP_SLT_D
    UINT64_C(210862080),	// XVFCMP_SLT_S
    UINT64_C(212369408),	// XVFCMP_SNE_D
    UINT64_C(211320832),	// XVFCMP_SNE_S
    UINT64_C(212500480),	// XVFCMP_SOR_D
    UINT64_C(211451904),	// XVFCMP_SOR_S
    UINT64_C(212238336),	// XVFCMP_SUEQ_D
    UINT64_C(211189760),	// XVFCMP_SUEQ_S
    UINT64_C(212303872),	// XVFCMP_SULE_D
    UINT64_C(211255296),	// XVFCMP_SULE_S
    UINT64_C(212172800),	// XVFCMP_SULT_D
    UINT64_C(211124224),	// XVFCMP_SULT_S
    UINT64_C(212631552),	// XVFCMP_SUNE_D
    UINT64_C(211582976),	// XVFCMP_SUNE_S
    UINT64_C(212107264),	// XVFCMP_SUN_D
    UINT64_C(211058688),	// XVFCMP_SUN_S
    UINT64_C(1990063104),	// XVFCVTH_D_S
    UINT64_C(1990061056),	// XVFCVTH_S_H
    UINT64_C(1990062080),	// XVFCVTL_D_S
    UINT64_C(1990060032),	// XVFCVTL_S_H
    UINT64_C(1967521792),	// XVFCVT_H_S
    UINT64_C(1967554560),	// XVFCVT_S_D
    UINT64_C(1966800896),	// XVFDIV_D
    UINT64_C(1966768128),	// XVFDIV_S
    UINT64_C(1990071296),	// XVFFINTH_D_W
    UINT64_C(1990070272),	// XVFFINTL_D_W
    UINT64_C(1990068224),	// XVFFINT_D_L
    UINT64_C(1990069248),	// XVFFINT_D_LU
    UINT64_C(1967652864),	// XVFFINT_S_L
    UINT64_C(1990066176),	// XVFFINT_S_W
    UINT64_C(1990067200),	// XVFFINT_S_WU
    UINT64_C(1989986304),	// XVFLOGB_D
    UINT64_C(1989985280),	// XVFLOGB_S
    UINT64_C(169869312),	// XVFMADD_D
    UINT64_C(168820736),	// XVFMADD_S
    UINT64_C(1967194112),	// XVFMAXA_D
    UINT64_C(1967161344),	// XVFMAXA_S
    UINT64_C(1966931968),	// XVFMAX_D
    UINT64_C(1966899200),	// XVFMAX_S
    UINT64_C(1967325184),	// XVFMINA_D
    UINT64_C(1967292416),	// XVFMINA_S
    UINT64_C(1967063040),	// XVFMIN_D
    UINT64_C(1967030272),	// XVFMIN_S
    UINT64_C(174063616),	// XVFMSUB_D
    UINT64_C(173015040),	// XVFMSUB_S
    UINT64_C(1966669824),	// XVFMUL_D
    UINT64_C(1966637056),	// XVFMUL_S
    UINT64_C(178257920),	// XVFNMADD_D
    UINT64_C(177209344),	// XVFNMADD_S
    UINT64_C(182452224),	// XVFNMSUB_D
    UINT64_C(181403648),	// XVFNMSUB_S
    UINT64_C(1990006784),	// XVFRECIPE_D
    UINT64_C(1990005760),	// XVFRECIPE_S
    UINT64_C(1989998592),	// XVFRECIP_D
    UINT64_C(1989997568),	// XVFRECIP_S
    UINT64_C(1990019072),	// XVFRINTRM_D
    UINT64_C(1990018048),	// XVFRINTRM_S
    UINT64_C(1990031360),	// XVFRINTRNE_D
    UINT64_C(1990030336),	// XVFRINTRNE_S
    UINT64_C(1990023168),	// XVFRINTRP_D
    UINT64_C(1990022144),	// XVFRINTRP_S
    UINT64_C(1990027264),	// XVFRINTRZ_D
    UINT64_C(1990026240),	// XVFRINTRZ_S
    UINT64_C(1990014976),	// XVFRINT_D
    UINT64_C(1990013952),	// XVFRINT_S
    UINT64_C(1990010880),	// XVFRSQRTE_D
    UINT64_C(1990009856),	// XVFRSQRTE_S
    UINT64_C(1990002688),	// XVFRSQRT_D
    UINT64_C(1990001664),	// XVFRSQRT_S
    UINT64_C(1989804032),	// XVFRSTPI_B
    UINT64_C(1989836800),	// XVFRSTPI_H
    UINT64_C(1965752320),	// XVFRSTP_B
    UINT64_C(1965785088),	// XVFRSTP_H
    UINT64_C(1989994496),	// XVFSQRT_D
    UINT64_C(1989993472),	// XVFSQRT_S
    UINT64_C(1966276608),	// XVFSUB_D
    UINT64_C(1966243840),	// XVFSUB_S
    UINT64_C(1990099968),	// XVFTINTH_L_S
    UINT64_C(1990098944),	// XVFTINTL_L_S
    UINT64_C(1990102016),	// XVFTINTRMH_L_S
    UINT64_C(1990100992),	// XVFTINTRML_L_S
    UINT64_C(1990081536),	// XVFTINTRM_L_D
    UINT64_C(1967783936),	// XVFTINTRM_W_D
    UINT64_C(1990080512),	// XVFTINTRM_W_S
    UINT64_C(1990108160),	// XVFTINTRNEH_L_S
    UINT64_C(1990107136),	// XVFTINTRNEL_L_S
    UINT64_C(1990087680),	// XVFTINTRNE_L_D
    UINT64_C(1967882240),	// XVFTINTRNE_W_D
    UINT64_C(1990086656),	// XVFTINTRNE_W_S
    UINT64_C(1990104064),	// XVFTINTRPH_L_S
    UINT64_C(1990103040),	// XVFTINTRPL_L_S
    UINT64_C(1990083584),	// XVFTINTRP_L_D
    UINT64_C(1967816704),	// XVFTINTRP_W_D
    UINT64_C(1990082560),	// XVFTINTRP_W_S
    UINT64_C(1990106112),	// XVFTINTRZH_L_S
    UINT64_C(1990105088),	// XVFTINTRZL_L_S
    UINT64_C(1990095872),	// XVFTINTRZ_LU_D
    UINT64_C(1990085632),	// XVFTINTRZ_L_D
    UINT64_C(1990094848),	// XVFTINTRZ_WU_S
    UINT64_C(1967849472),	// XVFTINTRZ_W_D
    UINT64_C(1990084608),	// XVFTINTRZ_W_S
    UINT64_C(1990089728),	// XVFTINT_LU_D
    UINT64_C(1990079488),	// XVFTINT_L_D
    UINT64_C(1990088704),	// XVFTINT_WU_S
    UINT64_C(1967751168),	// XVFTINT_W_D
    UINT64_C(1990078464),	// XVFTINT_W_S
    UINT64_C(1951989760),	// XVHADDW_DU_WU
    UINT64_C(1951727616),	// XVHADDW_D_W
    UINT64_C(1951924224),	// XVHADDW_HU_BU
    UINT64_C(1951662080),	// XVHADDW_H_B
    UINT64_C(1952022528),	// XVHADDW_QU_DU
    UINT64_C(1951760384),	// XVHADDW_Q_D
    UINT64_C(1951956992),	// XVHADDW_WU_HU
    UINT64_C(1951694848),	// XVHADDW_W_H
    UINT64_C(1990164480),	// XVHSELI_D
    UINT64_C(1952120832),	// XVHSUBW_DU_WU
    UINT64_C(1951858688),	// XVHSUBW_D_W
    UINT64_C(1952055296),	// XVHSUBW_HU_BU
    UINT64_C(1951793152),	// XVHSUBW_H_B
    UINT64_C(1952153600),	// XVHSUBW_QU_DU
    UINT64_C(1951891456),	// XVHSUBW_Q_D
    UINT64_C(1952088064),	// XVHSUBW_WU_HU
    UINT64_C(1951825920),	// XVHSUBW_W_H
    UINT64_C(1964769280),	// XVILVH_B
    UINT64_C(1964867584),	// XVILVH_D
    UINT64_C(1964802048),	// XVILVH_H
    UINT64_C(1964834816),	// XVILVH_W
    UINT64_C(1964638208),	// XVILVL_B
    UINT64_C(1964736512),	// XVILVL_D
    UINT64_C(1964670976),	// XVILVL_H
    UINT64_C(1964703744),	// XVILVL_W
    UINT64_C(1995169792),	// XVINSGR2VR_D
    UINT64_C(1995161600),	// XVINSGR2VR_W
    UINT64_C(1996480512),	// XVINSVE0_D
    UINT64_C(1996472320),	// XVINSVE0_W
    UINT64_C(746586112),	// XVLD
    UINT64_C(2011168768),	// XVLDI
    UINT64_C(847249408),	// XVLDREPL_B
    UINT64_C(839909376),	// XVLDREPL_D
    UINT64_C(843055104),	// XVLDREPL_H
    UINT64_C(840957952),	// XVLDREPL_W
    UINT64_C(944242688),	// XVLDX
    UINT64_C(1957494784),	// XVMADDWEV_D_W
    UINT64_C(1958019072),	// XVMADDWEV_D_WU
    UINT64_C(1958543360),	// XVMADDWEV_D_WU_W
    UINT64_C(1957429248),	// XVMADDWEV_H_B
    UINT64_C(1957953536),	// XVMADDWEV_H_BU
    UINT64_C(1958477824),	// XVMADDWEV_H_BU_B
    UINT64_C(1957527552),	// XVMADDWEV_Q_D
    UINT64_C(1958051840),	// XVMADDWEV_Q_DU
    UINT64_C(1958576128),	// XVMADDWEV_Q_DU_D
    UINT64_C(1957462016),	// XVMADDWEV_W_H
    UINT64_C(1957986304),	// XVMADDWEV_W_HU
    UINT64_C(1958510592),	// XVMADDWEV_W_HU_H
    UINT64_C(1957625856),	// XVMADDWOD_D_W
    UINT64_C(1958150144),	// XVMADDWOD_D_WU
    UINT64_C(1958674432),	// XVMADDWOD_D_WU_W
    UINT64_C(1957560320),	// XVMADDWOD_H_B
    UINT64_C(1958084608),	// XVMADDWOD_H_BU
    UINT64_C(1958608896),	// XVMADDWOD_H_BU_B
    UINT64_C(1957658624),	// XVMADDWOD_Q_D
    UINT64_C(1958182912),	// XVMADDWOD_Q_DU
    UINT64_C(1958707200),	// XVMADDWOD_Q_DU_D
    UINT64_C(1957593088),	// XVMADDWOD_W_H
    UINT64_C(1958117376),	// XVMADDWOD_W_HU
    UINT64_C(1958641664),	// XVMADDWOD_W_HU_H
    UINT64_C(1957167104),	// XVMADD_B
    UINT64_C(1957265408),	// XVMADD_D
    UINT64_C(1957199872),	// XVMADD_H
    UINT64_C(1957232640),	// XVMADD_W
    UINT64_C(1989148672),	// XVMAXI_B
    UINT64_C(1989410816),	// XVMAXI_BU
    UINT64_C(1989246976),	// XVMAXI_D
    UINT64_C(1989509120),	// XVMAXI_DU
    UINT64_C(1989181440),	// XVMAXI_H
    UINT64_C(1989443584),	// XVMAXI_HU
    UINT64_C(1989214208),	// XVMAXI_W
    UINT64_C(1989476352),	// XVMAXI_WU
    UINT64_C(1953497088),	// XVMAX_B
    UINT64_C(1953759232),	// XVMAX_BU
    UINT64_C(1953595392),	// XVMAX_D
    UINT64_C(1953857536),	// XVMAX_DU
    UINT64_C(1953529856),	// XVMAX_H
    UINT64_C(1953792000),	// XVMAX_HU
    UINT64_C(1953562624),	// XVMAX_W
    UINT64_C(1953824768),	// XVMAX_WU
    UINT64_C(1989279744),	// XVMINI_B
    UINT64_C(1989541888),	// XVMINI_BU
    UINT64_C(1989378048),	// XVMINI_D
    UINT64_C(1989640192),	// XVMINI_DU
    UINT64_C(1989312512),	// XVMINI_H
    UINT64_C(1989574656),	// XVMINI_HU
    UINT64_C(1989345280),	// XVMINI_W
    UINT64_C(1989607424),	// XVMINI_WU
    UINT64_C(1953628160),	// XVMIN_B
    UINT64_C(1953890304),	// XVMIN_BU
    UINT64_C(1953726464),	// XVMIN_D
    UINT64_C(1953988608),	// XVMIN_DU
    UINT64_C(1953660928),	// XVMIN_H
    UINT64_C(1953923072),	// XVMIN_HU
    UINT64_C(1953693696),	// XVMIN_W
    UINT64_C(1953955840),	// XVMIN_WU
    UINT64_C(1960968192),	// XVMOD_B
    UINT64_C(1961230336),	// XVMOD_BU
    UINT64_C(1961066496),	// XVMOD_D
    UINT64_C(1961328640),	// XVMOD_DU
    UINT64_C(1961000960),	// XVMOD_H
    UINT64_C(1961263104),	// XVMOD_HU
    UINT64_C(1961033728),	// XVMOD_W
    UINT64_C(1961295872),	// XVMOD_WU
    UINT64_C(1989955584),	// XVMSKGEZ_B
    UINT64_C(1989951488),	// XVMSKLTZ_B
    UINT64_C(1989954560),	// XVMSKLTZ_D
    UINT64_C(1989952512),	// XVMSKLTZ_H
    UINT64_C(1989953536),	// XVMSKLTZ_W
    UINT64_C(1989959680),	// XVMSKNZ_B
    UINT64_C(1957298176),	// XVMSUB_B
    UINT64_C(1957396480),	// XVMSUB_D
    UINT64_C(1957330944),	// XVMSUB_H
    UINT64_C(1957363712),	// XVMSUB_W
    UINT64_C(1954938880),	// XVMUH_B
    UINT64_C(1955069952),	// XVMUH_BU
    UINT64_C(1955037184),	// XVMUH_D
    UINT64_C(1955168256),	// XVMUH_DU
    UINT64_C(1954971648),	// XVMUH_H
    UINT64_C(1955102720),	// XVMUH_HU
    UINT64_C(1955004416),	// XVMUH_W
    UINT64_C(1955135488),	// XVMUH_WU
    UINT64_C(1955659776),	// XVMULWEV_D_W
    UINT64_C(1956184064),	// XVMULWEV_D_WU
    UINT64_C(1956708352),	// XVMULWEV_D_WU_W
    UINT64_C(1955594240),	// XVMULWEV_H_B
    UINT64_C(1956118528),	// XVMULWEV_H_BU
    UINT64_C(1956642816),	// XVMULWEV_H_BU_B
    UINT64_C(1955692544),	// XVMULWEV_Q_D
    UINT64_C(1956216832),	// XVMULWEV_Q_DU
    UINT64_C(1956741120),	// XVMULWEV_Q_DU_D
    UINT64_C(1955627008),	// XVMULWEV_W_H
    UINT64_C(1956151296),	// XVMULWEV_W_HU
    UINT64_C(1956675584),	// XVMULWEV_W_HU_H
    UINT64_C(1955790848),	// XVMULWOD_D_W
    UINT64_C(1956315136),	// XVMULWOD_D_WU
    UINT64_C(1956839424),	// XVMULWOD_D_WU_W
    UINT64_C(1955725312),	// XVMULWOD_H_B
    UINT64_C(1956249600),	// XVMULWOD_H_BU
    UINT64_C(1956773888),	// XVMULWOD_H_BU_B
    UINT64_C(1955823616),	// XVMULWOD_Q_D
    UINT64_C(1956347904),	// XVMULWOD_Q_DU
    UINT64_C(1956872192),	// XVMULWOD_Q_DU_D
    UINT64_C(1955758080),	// XVMULWOD_W_H
    UINT64_C(1956282368),	// XVMULWOD_W_HU
    UINT64_C(1956806656),	// XVMULWOD_W_HU_H
    UINT64_C(1954807808),	// XVMUL_B
    UINT64_C(1954906112),	// XVMUL_D
    UINT64_C(1954840576),	// XVMUL_H
    UINT64_C(1954873344),	// XVMUL_W
    UINT64_C(1989947392),	// XVNEG_B
    UINT64_C(1989950464),	// XVNEG_D
    UINT64_C(1989948416),	// XVNEG_H
    UINT64_C(1989949440),	// XVNEG_W
    UINT64_C(2010906624),	// XVNORI_B
    UINT64_C(1965522944),	// XVNOR_V
    UINT64_C(2010382336),	// XVORI_B
    UINT64_C(1965588480),	// XVORN_V
    UINT64_C(1965457408),	// XVOR_V
    UINT64_C(1964376064),	// XVPACKEV_B
    UINT64_C(1964474368),	// XVPACKEV_D
    UINT64_C(1964408832),	// XVPACKEV_H
    UINT64_C(1964441600),	// XVPACKEV_W
    UINT64_C(1964507136),	// XVPACKOD_B
    UINT64_C(1964605440),	// XVPACKOD_D
    UINT64_C(1964539904),	// XVPACKOD_H
    UINT64_C(1964572672),	// XVPACKOD_W
    UINT64_C(1989943296),	// XVPCNT_B
    UINT64_C(1989946368),	// XVPCNT_D
    UINT64_C(1989944320),	// XVPCNT_H
    UINT64_C(1989945344),	// XVPCNT_W
    UINT64_C(2011693056),	// XVPERMI_D
    UINT64_C(2011955200),	// XVPERMI_Q
    UINT64_C(2011430912),	// XVPERMI_W
    UINT64_C(1971126272),	// XVPERM_W
    UINT64_C(1964900352),	// XVPICKEV_B
    UINT64_C(1964998656),	// XVPICKEV_D
    UINT64_C(1964933120),	// XVPICKEV_H
    UINT64_C(1964965888),	// XVPICKEV_W
    UINT64_C(1965031424),	// XVPICKOD_B
    UINT64_C(1965129728),	// XVPICKOD_D
    UINT64_C(1965064192),	// XVPICKOD_H
    UINT64_C(1965096960),	// XVPICKOD_W
    UINT64_C(1995431936),	// XVPICKVE2GR_D
    UINT64_C(1995694080),	// XVPICKVE2GR_DU
    UINT64_C(1995423744),	// XVPICKVE2GR_W
    UINT64_C(1995685888),	// XVPICKVE2GR_WU
    UINT64_C(1996742656),	// XVPICKVE_D
    UINT64_C(1996734464),	// XVPICKVE_W
    UINT64_C(1995931648),	// XVREPL128VEI_B
    UINT64_C(1995960320),	// XVREPL128VEI_D
    UINT64_C(1995948032),	// XVREPL128VEI_H
    UINT64_C(1995956224),	// XVREPL128VEI_W
    UINT64_C(1990131712),	// XVREPLGR2VR_B
    UINT64_C(1990134784),	// XVREPLGR2VR_D
    UINT64_C(1990132736),	// XVREPLGR2VR_H
    UINT64_C(1990133760),	// XVREPLGR2VR_W
    UINT64_C(1996947456),	// XVREPLVE0_B
    UINT64_C(1997004800),	// XVREPLVE0_D
    UINT64_C(1996980224),	// XVREPLVE0_H
    UINT64_C(1997008896),	// XVREPLVE0_Q
    UINT64_C(1996996608),	// XVREPLVE0_W
    UINT64_C(1965162496),	// XVREPLVE_B
    UINT64_C(1965260800),	// XVREPLVE_D
    UINT64_C(1965195264),	// XVREPLVE_H
    UINT64_C(1965228032),	// XVREPLVE_W
    UINT64_C(1990205440),	// XVROTRI_B
    UINT64_C(1990262784),	// XVROTRI_D
    UINT64_C(1990213632),	// XVROTRI_H
    UINT64_C(1990230016),	// XVROTRI_W
    UINT64_C(1961754624),	// XVROTR_B
    UINT64_C(1961852928),	// XVROTR_D
    UINT64_C(1961787392),	// XVROTR_H
    UINT64_C(1961820160),	// XVROTR_W
    UINT64_C(1950744576),	// XVSADD_B
    UINT64_C(1951006720),	// XVSADD_BU
    UINT64_C(1950842880),	// XVSADD_D
    UINT64_C(1951105024),	// XVSADD_DU
    UINT64_C(1950777344),	// XVSADD_H
    UINT64_C(1951039488),	// XVSADD_HU
    UINT64_C(1950810112),	// XVSADD_W
    UINT64_C(1951072256),	// XVSADD_WU
    UINT64_C(1998856192),	// XVSAT_B
    UINT64_C(1999118336),	// XVSAT_BU
    UINT64_C(1998913536),	// XVSAT_D
    UINT64_C(1999175680),	// XVSAT_DU
    UINT64_C(1998864384),	// XVSAT_H
    UINT64_C(1999126528),	// XVSAT_HU
    UINT64_C(1998880768),	// XVSAT_W
    UINT64_C(1999142912),	// XVSAT_WU
    UINT64_C(1988100096),	// XVSEQI_B
    UINT64_C(1988198400),	// XVSEQI_D
    UINT64_C(1988132864),	// XVSEQI_H
    UINT64_C(1988165632),	// XVSEQI_W
    UINT64_C(1946157056),	// XVSEQ_B
    UINT64_C(1946255360),	// XVSEQ_D
    UINT64_C(1946189824),	// XVSEQ_H
    UINT64_C(1946222592),	// XVSEQ_W
    UINT64_C(1989980160),	// XVSETALLNEZ_B
    UINT64_C(1989983232),	// XVSETALLNEZ_D
    UINT64_C(1989981184),	// XVSETALLNEZ_H
    UINT64_C(1989982208),	// XVSETALLNEZ_W
    UINT64_C(1989976064),	// XVSETANYEQZ_B
    UINT64_C(1989979136),	// XVSETANYEQZ_D
    UINT64_C(1989977088),	// XVSETANYEQZ_H
    UINT64_C(1989978112),	// XVSETANYEQZ_W
    UINT64_C(1989974016),	// XVSETEQZ_V
    UINT64_C(1989975040),	// XVSETNEZ_V
    UINT64_C(2005925888),	// XVSHUF4I_B
    UINT64_C(2006712320),	// XVSHUF4I_D
    UINT64_C(2006188032),	// XVSHUF4I_H
    UINT64_C(2006450176),	// XVSHUF4I_W
    UINT64_C(224395264),	// XVSHUF_B
    UINT64_C(1971027968),	// XVSHUF_D
    UINT64_C(1970962432),	// XVSHUF_H
    UINT64_C(1970995200),	// XVSHUF_W
    UINT64_C(1965948928),	// XVSIGNCOV_B
    UINT64_C(1966047232),	// XVSIGNCOV_D
    UINT64_C(1965981696),	// XVSIGNCOV_H
    UINT64_C(1966014464),	// XVSIGNCOV_W
    UINT64_C(1988231168),	// XVSLEI_B
    UINT64_C(1988362240),	// XVSLEI_BU
    UINT64_C(1988329472),	// XVSLEI_D
    UINT64_C(1988460544),	// XVSLEI_DU
    UINT64_C(1988263936),	// XVSLEI_H
    UINT64_C(1988395008),	// XVSLEI_HU
    UINT64_C(1988296704),	// XVSLEI_W
    UINT64_C(1988427776),	// XVSLEI_WU
    UINT64_C(1946288128),	// XVSLE_B
    UINT64_C(1946419200),	// XVSLE_BU
    UINT64_C(1946386432),	// XVSLE_D
    UINT64_C(1946517504),	// XVSLE_DU
    UINT64_C(1946320896),	// XVSLE_H
    UINT64_C(1946451968),	// XVSLE_HU
    UINT64_C(1946353664),	// XVSLE_W
    UINT64_C(1946484736),	// XVSLE_WU
    UINT64_C(1999380480),	// XVSLLI_B
    UINT64_C(1999437824),	// XVSLLI_D
    UINT64_C(1999388672),	// XVSLLI_H
    UINT64_C(1999405056),	// XVSLLI_W
    UINT64_C(1997307904),	// XVSLLWIL_DU_WU
    UINT64_C(1997045760),	// XVSLLWIL_D_W
    UINT64_C(1997283328),	// XVSLLWIL_HU_BU
    UINT64_C(1997021184),	// XVSLLWIL_H_B
    UINT64_C(1997291520),	// XVSLLWIL_WU_HU
    UINT64_C(1997029376),	// XVSLLWIL_W_H
    UINT64_C(1961361408),	// XVSLL_B
    UINT64_C(1961459712),	// XVSLL_D
    UINT64_C(1961394176),	// XVSLL_H
    UINT64_C(1961426944),	// XVSLL_W
    UINT64_C(1988493312),	// XVSLTI_B
    UINT64_C(1988624384),	// XVSLTI_BU
    UINT64_C(1988591616),	// XVSLTI_D
    UINT64_C(1988722688),	// XVSLTI_DU
    UINT64_C(1988526080),	// XVSLTI_H
    UINT64_C(1988657152),	// XVSLTI_HU
    UINT64_C(1988558848),	// XVSLTI_W
    UINT64_C(1988689920),	// XVSLTI_WU
    UINT64_C(1946550272),	// XVSLT_B
    UINT64_C(1946681344),	// XVSLT_BU
    UINT64_C(1946648576),	// XVSLT_D
    UINT64_C(1946779648),	// XVSLT_DU
    UINT64_C(1946583040),	// XVSLT_H
    UINT64_C(1946714112),	// XVSLT_HU
    UINT64_C(1946615808),	// XVSLT_W
    UINT64_C(1946746880),	// XVSLT_WU
    UINT64_C(1999904768),	// XVSRAI_B
    UINT64_C(1999962112),	// XVSRAI_D
    UINT64_C(1999912960),	// XVSRAI_H
    UINT64_C(1999929344),	// XVSRAI_W
    UINT64_C(2002272256),	// XVSRANI_B_H
    UINT64_C(2002386944),	// XVSRANI_D_Q
    UINT64_C(2002288640),	// XVSRANI_H_W
    UINT64_C(2002321408),	// XVSRANI_W_D
    UINT64_C(1962311680),	// XVSRAN_B_H
    UINT64_C(1962344448),	// XVSRAN_H_W
    UINT64_C(1962377216),	// XVSRAN_W_D
    UINT64_C(1990729728),	// XVSRARI_B
    UINT64_C(1990787072),	// XVSRARI_D
    UINT64_C(1990737920),	// XVSRARI_H
    UINT64_C(1990754304),	// XVSRARI_W
    UINT64_C(2002534400),	// XVSRARNI_B_H
    UINT64_C(2002649088),	// XVSRARNI_D_Q
    UINT64_C(2002550784),	// XVSRARNI_H_W
    UINT64_C(2002583552),	// XVSRARNI_W_D
    UINT64_C(1962573824),	// XVSRARN_B_H
    UINT64_C(1962606592),	// XVSRARN_H_W
    UINT64_C(1962639360),	// XVSRARN_W_D
    UINT64_C(1962016768),	// XVSRAR_B
    UINT64_C(1962115072),	// XVSRAR_D
    UINT64_C(1962049536),	// XVSRAR_H
    UINT64_C(1962082304),	// XVSRAR_W
    UINT64_C(1961623552),	// XVSRA_B
    UINT64_C(1961721856),	// XVSRA_D
    UINT64_C(1961656320),	// XVSRA_H
    UINT64_C(1961689088),	// XVSRA_W
    UINT64_C(1999642624),	// XVSRLI_B
    UINT64_C(1999699968),	// XVSRLI_D
    UINT64_C(1999650816),	// XVSRLI_H
    UINT64_C(1999667200),	// XVSRLI_W
    UINT64_C(2000699392),	// XVSRLNI_B_H
    UINT64_C(2000814080),	// XVSRLNI_D_Q
    UINT64_C(2000715776),	// XVSRLNI_H_W
    UINT64_C(2000748544),	// XVSRLNI_W_D
    UINT64_C(1962180608),	// XVSRLN_B_H
    UINT64_C(1962213376),	// XVSRLN_H_W
    UINT64_C(1962246144),	// XVSRLN_W_D
    UINT64_C(1990467584),	// XVSRLRI_B
    UINT64_C(1990524928),	// XVSRLRI_D
    UINT64_C(1990475776),	// XVSRLRI_H
    UINT64_C(1990492160),	// XVSRLRI_W
    UINT64_C(2000961536),	// XVSRLRNI_B_H
    UINT64_C(2001076224),	// XVSRLRNI_D_Q
    UINT64_C(2000977920),	// XVSRLRNI_H_W
    UINT64_C(2001010688),	// XVSRLRNI_W_D
    UINT64_C(1962442752),	// XVSRLRN_B_H
    UINT64_C(1962475520),	// XVSRLRN_H_W
    UINT64_C(1962508288),	// XVSRLRN_W_D
    UINT64_C(1961885696),	// XVSRLR_B
    UINT64_C(1961984000),	// XVSRLR_D
    UINT64_C(1961918464),	// XVSRLR_H
    UINT64_C(1961951232),	// XVSRLR_W
    UINT64_C(1961492480),	// XVSRL_B
    UINT64_C(1961590784),	// XVSRL_D
    UINT64_C(1961525248),	// XVSRL_H
    UINT64_C(1961558016),	// XVSRL_W
    UINT64_C(2003058688),	// XVSSRANI_BU_H
    UINT64_C(2002796544),	// XVSSRANI_B_H
    UINT64_C(2003173376),	// XVSSRANI_DU_Q
    UINT64_C(2002911232),	// XVSSRANI_D_Q
    UINT64_C(2003075072),	// XVSSRANI_HU_W
    UINT64_C(2002812928),	// XVSSRANI_H_W
    UINT64_C(2003107840),	// XVSSRANI_WU_D
    UINT64_C(2002845696),	// XVSSRANI_W_D
    UINT64_C(1963360256),	// XVSSRAN_BU_H
    UINT64_C(1962835968),	// XVSSRAN_B_H
    UINT64_C(1963393024),	// XVSSRAN_HU_W
    UINT64_C(1962868736),	// XVSSRAN_H_W
    UINT64_C(1963425792),	// XVSSRAN_WU_D
    UINT64_C(1962901504),	// XVSSRAN_W_D
    UINT64_C(2003582976),	// XVSSRARNI_BU_H
    UINT64_C(2003320832),	// XVSSRARNI_B_H
    UINT64_C(2003697664),	// XVSSRARNI_DU_Q
    UINT64_C(2003435520),	// XVSSRARNI_D_Q
    UINT64_C(2003599360),	// XVSSRARNI_HU_W
    UINT64_C(2003337216),	// XVSSRARNI_H_W
    UINT64_C(2003632128),	// XVSSRARNI_WU_D
    UINT64_C(2003369984),	// XVSSRARNI_W_D
    UINT64_C(1963622400),	// XVSSRARN_BU_H
    UINT64_C(1963098112),	// XVSSRARN_B_H
    UINT64_C(1963655168),	// XVSSRARN_HU_W
    UINT64_C(1963130880),	// XVSSRARN_H_W
    UINT64_C(1963687936),	// XVSSRARN_WU_D
    UINT64_C(1963163648),	// XVSSRARN_W_D
    UINT64_C(2001485824),	// XVSSRLNI_BU_H
    UINT64_C(2001223680),	// XVSSRLNI_B_H
    UINT64_C(2001600512),	// XVSSRLNI_DU_Q
    UINT64_C(2001338368),	// XVSSRLNI_D_Q
    UINT64_C(2001502208),	// XVSSRLNI_HU_W
    UINT64_C(2001240064),	// XVSSRLNI_H_W
    UINT64_C(2001534976),	// XVSSRLNI_WU_D
    UINT64_C(2001272832),	// XVSSRLNI_W_D
    UINT64_C(1963229184),	// XVSSRLN_BU_H
    UINT64_C(1962704896),	// XVSSRLN_B_H
    UINT64_C(1963261952),	// XVSSRLN_HU_W
    UINT64_C(1962737664),	// XVSSRLN_H_W
    UINT64_C(1963294720),	// XVSSRLN_WU_D
    UINT64_C(1962770432),	// XVSSRLN_W_D
    UINT64_C(2002010112),	// XVSSRLRNI_BU_H
    UINT64_C(2001747968),	// XVSSRLRNI_B_H
    UINT64_C(2002124800),	// XVSSRLRNI_DU_Q
    UINT64_C(2001862656),	// XVSSRLRNI_D_Q
    UINT64_C(2002026496),	// XVSSRLRNI_HU_W
    UINT64_C(2001764352),	// XVSSRLRNI_H_W
    UINT64_C(2002059264),	// XVSSRLRNI_WU_D
    UINT64_C(2001797120),	// XVSSRLRNI_W_D
    UINT64_C(1963491328),	// XVSSRLRN_BU_H
    UINT64_C(1962967040),	// XVSSRLRN_B_H
    UINT64_C(1963524096),	// XVSSRLRN_HU_W
    UINT64_C(1962999808),	// XVSSRLRN_H_W
    UINT64_C(1963556864),	// XVSSRLRN_WU_D
    UINT64_C(1963032576),	// XVSSRLRN_W_D
    UINT64_C(1950875648),	// XVSSUB_B
    UINT64_C(1951137792),	// XVSSUB_BU
    UINT64_C(1950973952),	// XVSSUB_D
    UINT64_C(1951236096),	// XVSSUB_DU
    UINT64_C(1950908416),	// XVSSUB_H
    UINT64_C(1951170560),	// XVSSUB_HU
    UINT64_C(1950941184),	// XVSSUB_W
    UINT64_C(1951203328),	// XVSSUB_WU
    UINT64_C(750780416),	// XVST
    UINT64_C(864026624),	// XVSTELM_B
    UINT64_C(856686592),	// XVSTELM_D
    UINT64_C(859832320),	// XVSTELM_H
    UINT64_C(857735168),	// XVSTELM_W
    UINT64_C(944504832),	// XVSTX
    UINT64_C(1988886528),	// XVSUBI_BU
    UINT64_C(1988984832),	// XVSUBI_DU
    UINT64_C(1988919296),	// XVSUBI_HU
    UINT64_C(1988952064),	// XVSUBI_WU
    UINT64_C(1948319744),	// XVSUBWEV_D_W
    UINT64_C(1949368320),	// XVSUBWEV_D_WU
    UINT64_C(1948254208),	// XVSUBWEV_H_B
    UINT64_C(1949302784),	// XVSUBWEV_H_BU
    UINT64_C(1948352512),	// XVSUBWEV_Q_D
    UINT64_C(1949401088),	// XVSUBWEV_Q_DU
    UINT64_C(1948286976),	// XVSUBWEV_W_H
    UINT64_C(1949335552),	// XVSUBWEV_W_HU
    UINT64_C(1948581888),	// XVSUBWOD_D_W
    UINT64_C(1949630464),	// XVSUBWOD_D_WU
    UINT64_C(1948516352),	// XVSUBWOD_H_B
    UINT64_C(1949564928),	// XVSUBWOD_H_BU
    UINT64_C(1948614656),	// XVSUBWOD_Q_D
    UINT64_C(1949663232),	// XVSUBWOD_Q_DU
    UINT64_C(1948549120),	// XVSUBWOD_W_H
    UINT64_C(1949597696),	// XVSUBWOD_W_HU
    UINT64_C(1946943488),	// XVSUB_B
    UINT64_C(1947041792),	// XVSUB_D
    UINT64_C(1946976256),	// XVSUB_H
    UINT64_C(1965916160),	// XVSUB_Q
    UINT64_C(1947009024),	// XVSUB_W
    UINT64_C(2010644480),	// XVXORI_B
    UINT64_C(1965490176),	// XVXOR_V
  };
  constexpr unsigned FirstSupportedOpcode = 445;

  const unsigned opcode = MI.getOpcode();
  if (opcode < FirstSupportedOpcode)
    reportUnsupportedInst(MI);
  unsigned TableIndex = opcode - FirstSupportedOpcode;
  uint64_t Value = InstBits[TableIndex];
  uint64_t op = 0;
  (void)op;  // suppress warning
  switch (opcode) {
    case LoongArch::ERTN:
    case LoongArch::GTLBFLUSH:
    case LoongArch::TLBCLR:
    case LoongArch::TLBFILL:
    case LoongArch::TLBFLUSH:
    case LoongArch::TLBRD:
    case LoongArch::TLBSRCH:
    case LoongArch::TLBWR:
    case LoongArch::X86CLRTM:
    case LoongArch::X86DECTOP:
    case LoongArch::X86INCTOP:
    case LoongArch::X86SETTM: {
      break;
    }
    case LoongArch::FSEL_xD:
    case LoongArch::FSEL_xS: {
      // op: ca
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 15;
      // op: fk
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: fj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::SET_CFR_FALSE:
    case LoongArch::SET_CFR_TRUE: {
      // op: cd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case LoongArch::CSRRD:
    case LoongArch::GCSRRD: {
      // op: csr_num
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3fff) << 10;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::CSRWR:
    case LoongArch::GCSRWR: {
      // op: csr_num
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3fff) << 10;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::CSRXCHG:
    case LoongArch::GCSRXCHG: {
      // op: csr_num
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3fff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::FMADD_D:
    case LoongArch::FMADD_S:
    case LoongArch::FMSUB_D:
    case LoongArch::FMSUB_S:
    case LoongArch::FNMADD_D:
    case LoongArch::FNMADD_S:
    case LoongArch::FNMSUB_D:
    case LoongArch::FNMSUB_S: {
      // op: fa
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 15;
      // op: fk
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: fj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::FABS_D:
    case LoongArch::FABS_S:
    case LoongArch::FCLASS_D:
    case LoongArch::FCLASS_S:
    case LoongArch::FCVT_D_S:
    case LoongArch::FCVT_LD_D:
    case LoongArch::FCVT_S_D:
    case LoongArch::FCVT_UD_D:
    case LoongArch::FFINT_D_L:
    case LoongArch::FFINT_D_W:
    case LoongArch::FFINT_S_L:
    case LoongArch::FFINT_S_W:
    case LoongArch::FLOGB_D:
    case LoongArch::FLOGB_S:
    case LoongArch::FNEG_D:
    case LoongArch::FNEG_S:
    case LoongArch::FRECIPE_D:
    case LoongArch::FRECIPE_S:
    case LoongArch::FRECIP_D:
    case LoongArch::FRECIP_S:
    case LoongArch::FRINT_D:
    case LoongArch::FRINT_S:
    case LoongArch::FRSQRTE_D:
    case LoongArch::FRSQRTE_S:
    case LoongArch::FRSQRT_D:
    case LoongArch::FRSQRT_S:
    case LoongArch::FSQRT_D:
    case LoongArch::FSQRT_S:
    case LoongArch::FTINTRM_L_D:
    case LoongArch::FTINTRM_L_S:
    case LoongArch::FTINTRM_W_D:
    case LoongArch::FTINTRM_W_S:
    case LoongArch::FTINTRNE_L_D:
    case LoongArch::FTINTRNE_L_S:
    case LoongArch::FTINTRNE_W_D:
    case LoongArch::FTINTRNE_W_S:
    case LoongArch::FTINTRP_L_D:
    case LoongArch::FTINTRP_L_S:
    case LoongArch::FTINTRP_W_D:
    case LoongArch::FTINTRP_W_S:
    case LoongArch::FTINTRZ_L_D:
    case LoongArch::FTINTRZ_L_S:
    case LoongArch::FTINTRZ_W_D:
    case LoongArch::FTINTRZ_W_S:
    case LoongArch::FTINT_L_D:
    case LoongArch::FTINT_L_S:
    case LoongArch::FTINT_W_D:
    case LoongArch::FTINT_W_S: {
      // op: fj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::FCMP_CAF_D:
    case LoongArch::FCMP_CAF_S:
    case LoongArch::FCMP_CEQ_D:
    case LoongArch::FCMP_CEQ_S:
    case LoongArch::FCMP_CLE_D:
    case LoongArch::FCMP_CLE_S:
    case LoongArch::FCMP_CLT_D:
    case LoongArch::FCMP_CLT_S:
    case LoongArch::FCMP_CNE_D:
    case LoongArch::FCMP_CNE_S:
    case LoongArch::FCMP_COR_D:
    case LoongArch::FCMP_COR_S:
    case LoongArch::FCMP_CUEQ_D:
    case LoongArch::FCMP_CUEQ_S:
    case LoongArch::FCMP_CULE_D:
    case LoongArch::FCMP_CULE_S:
    case LoongArch::FCMP_CULT_D:
    case LoongArch::FCMP_CULT_S:
    case LoongArch::FCMP_CUNE_D:
    case LoongArch::FCMP_CUNE_S:
    case LoongArch::FCMP_CUN_D:
    case LoongArch::FCMP_CUN_S:
    case LoongArch::FCMP_SAF_D:
    case LoongArch::FCMP_SAF_S:
    case LoongArch::FCMP_SEQ_D:
    case LoongArch::FCMP_SEQ_S:
    case LoongArch::FCMP_SLE_D:
    case LoongArch::FCMP_SLE_S:
    case LoongArch::FCMP_SLT_D:
    case LoongArch::FCMP_SLT_S:
    case LoongArch::FCMP_SNE_D:
    case LoongArch::FCMP_SNE_S:
    case LoongArch::FCMP_SOR_D:
    case LoongArch::FCMP_SOR_S:
    case LoongArch::FCMP_SUEQ_D:
    case LoongArch::FCMP_SUEQ_S:
    case LoongArch::FCMP_SULE_D:
    case LoongArch::FCMP_SULE_S:
    case LoongArch::FCMP_SULT_D:
    case LoongArch::FCMP_SULT_S:
    case LoongArch::FCMP_SUNE_D:
    case LoongArch::FCMP_SUNE_S:
    case LoongArch::FCMP_SUN_D:
    case LoongArch::FCMP_SUN_S: {
      // op: fk
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: fj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: cd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case LoongArch::FADD_D:
    case LoongArch::FADD_S:
    case LoongArch::FCOPYSIGN_D:
    case LoongArch::FCOPYSIGN_S:
    case LoongArch::FCVT_D_LD:
    case LoongArch::FDIV_D:
    case LoongArch::FDIV_S:
    case LoongArch::FMAXA_D:
    case LoongArch::FMAXA_S:
    case LoongArch::FMAX_D:
    case LoongArch::FMAX_S:
    case LoongArch::FMINA_D:
    case LoongArch::FMINA_S:
    case LoongArch::FMIN_D:
    case LoongArch::FMIN_S:
    case LoongArch::FMUL_D:
    case LoongArch::FMUL_S:
    case LoongArch::FSCALEB_D:
    case LoongArch::FSCALEB_S:
    case LoongArch::FSUB_D:
    case LoongArch::FSUB_S: {
      // op: fk
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: fj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VPICKVE2GR_D:
    case LoongArch::VPICKVE2GR_DU: {
      // op: imm1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 10;
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VREPLVEI_D: {
      // op: imm1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 10;
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVREPL128VEI_D: {
      // op: imm1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 10;
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VINSGR2VR_D: {
      // op: imm1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VSTELM_D: {
      // op: imm1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 18;
      // op: imm8
      op = getImmOpValueAsr<3>(MI, 2, Fixups, STI);
      Value |= (op & 0xff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VLDREPL_W: {
      // op: imm10
      op = getImmOpValueAsr<2>(MI, 2, Fixups, STI);
      Value |= (op & 0x3ff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVLDREPL_W: {
      // op: imm10
      op = getImmOpValueAsr<2>(MI, 2, Fixups, STI);
      Value |= (op & 0x3ff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VLDREPL_H: {
      // op: imm11
      op = getImmOpValueAsr<1>(MI, 2, Fixups, STI);
      Value |= (op & 0x7ff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVLDREPL_H: {
      // op: imm11
      op = getImmOpValueAsr<1>(MI, 2, Fixups, STI);
      Value |= (op & 0x7ff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::FLD_D:
    case LoongArch::FLD_S:
    case LoongArch::FST_D:
    case LoongArch::FST_S: {
      // op: imm12
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xfff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::PRELD: {
      // op: imm12
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xfff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm5
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::CACOP: {
      // op: imm12
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xfff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: op
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::ADDI_D:
    case LoongArch::ADDI_W:
    case LoongArch::ANDI:
    case LoongArch::LDL_D:
    case LoongArch::LDL_W:
    case LoongArch::LDR_D:
    case LoongArch::LDR_W:
    case LoongArch::LD_B:
    case LoongArch::LD_BU:
    case LoongArch::LD_D:
    case LoongArch::LD_H:
    case LoongArch::LD_HU:
    case LoongArch::LD_W:
    case LoongArch::LD_WU:
    case LoongArch::LU52I_D:
    case LoongArch::ORI:
    case LoongArch::SLTI:
    case LoongArch::SLTUI:
    case LoongArch::STL_D:
    case LoongArch::STL_W:
    case LoongArch::STR_D:
    case LoongArch::STR_W:
    case LoongArch::ST_B:
    case LoongArch::ST_D:
    case LoongArch::ST_H:
    case LoongArch::ST_W:
    case LoongArch::XORI: {
      // op: imm12
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xfff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VLD:
    case LoongArch::VLDREPL_B:
    case LoongArch::VST: {
      // op: imm12
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xfff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVLD:
    case LoongArch::XVLDREPL_B:
    case LoongArch::XVST: {
      // op: imm12
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xfff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VLDI: {
      // op: imm13
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1fff) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVLDI: {
      // op: imm13
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1fff) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::LDPTR_D:
    case LoongArch::LDPTR_W:
    case LoongArch::LL_D:
    case LoongArch::LL_W:
    case LoongArch::STPTR_D:
    case LoongArch::STPTR_W: {
      // op: imm14
      op = getImmOpValueAsr<2>(MI, 2, Fixups, STI);
      Value |= (op & 0x3fff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::SC_D:
    case LoongArch::SC_W: {
      // op: imm14
      op = getImmOpValueAsr<2>(MI, 3, Fixups, STI);
      Value |= (op & 0x3fff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::BREAK:
    case LoongArch::DBAR:
    case LoongArch::DBCL:
    case LoongArch::HVCL:
    case LoongArch::IBAR:
    case LoongArch::IDLE:
    case LoongArch::SYSCALL: {
      // op: imm15
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7fff);
      break;
    }
    case LoongArch::BEQ:
    case LoongArch::BGE:
    case LoongArch::BGEU:
    case LoongArch::BLT:
    case LoongArch::BLTU:
    case LoongArch::BNE: {
      // op: imm16
      op = getImmOpValueAsr<2>(MI, 2, Fixups, STI);
      Value |= (op & 0xffff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::JIRL: {
      // op: imm16
      op = getImmOpValueAsr<2>(MI, 2, Fixups, STI);
      Value |= (op & 0xffff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::ADDU16I_D: {
      // op: imm16
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xffff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::ALSL_D:
    case LoongArch::ALSL_W:
    case LoongArch::ALSL_WU: {
      // op: imm2
      op = getImmOpValueSub1(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 15;
      // op: rk
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VPICKVE2GR_W:
    case LoongArch::VPICKVE2GR_WU: {
      // op: imm2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3) << 10;
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VREPLVEI_W: {
      // op: imm2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3) << 10;
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVPICKVE2GR_D:
    case LoongArch::XVPICKVE2GR_DU: {
      // op: imm2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3) << 10;
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVPICKVE_D:
    case LoongArch::XVREPL128VEI_W: {
      // op: imm2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3) << 10;
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VINSGR2VR_W: {
      // op: imm2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVINSGR2VR_D: {
      // op: imm2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVINSVE0_D: {
      // op: imm2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 10;
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::BYTEPICK_W: {
      // op: imm2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 15;
      // op: rk
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VSTELM_W: {
      // op: imm2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 18;
      // op: imm8
      op = getImmOpValueAsr<2>(MI, 2, Fixups, STI);
      Value |= (op & 0xff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVSTELM_D: {
      // op: imm2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 18;
      // op: imm8
      op = getImmOpValueAsr<3>(MI, 2, Fixups, STI);
      Value |= (op & 0xff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::LU12I_W:
    case LoongArch::PCADDI:
    case LoongArch::PCADDU12I:
    case LoongArch::PCADDU18I:
    case LoongArch::PCALAU12I: {
      // op: imm20
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xfffff) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::LU32I_D: {
      // op: imm20
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xfffff) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::JISCR0:
    case LoongArch::JISCR1: {
      // op: imm21
      op = getImmOpValueAsr<2>(MI, 0, Fixups, STI);
      Value |= (op & 0xffff) << 10;
      Value |= (op & 0x1f0000) >> 16;
      break;
    }
    case LoongArch::BCEQZ:
    case LoongArch::BCNEZ: {
      // op: imm21
      op = getImmOpValueAsr<2>(MI, 1, Fixups, STI);
      Value |= (op & 0xffff) << 10;
      Value |= (op & 0x1f0000) >> 16;
      // op: cj
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case LoongArch::BEQZ:
    case LoongArch::BNEZ: {
      // op: imm21
      op = getImmOpValueAsr<2>(MI, 1, Fixups, STI);
      Value |= (op & 0xffff) << 10;
      Value |= (op & 0x1f0000) >> 16;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case LoongArch::B:
    case LoongArch::BL: {
      // op: imm26
      op = getImmOpValueAsr<2>(MI, 0, Fixups, STI);
      Value |= (op & 0xffff) << 10;
      Value |= (op & 0x3ff0000) >> 16;
      break;
    }
    case LoongArch::X86RCLI_B:
    case LoongArch::X86RCRI_B:
    case LoongArch::X86ROTLI_B:
    case LoongArch::X86ROTRI_B:
    case LoongArch::X86SLLI_B:
    case LoongArch::X86SRAI_B:
    case LoongArch::X86SRLI_B: {
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case LoongArch::RCRI_B:
    case LoongArch::ROTRI_B: {
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VPICKVE2GR_H:
    case LoongArch::VPICKVE2GR_HU: {
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VBITCLRI_B:
    case LoongArch::VBITREVI_B:
    case LoongArch::VBITSETI_B:
    case LoongArch::VREPLVEI_H:
    case LoongArch::VROTRI_B:
    case LoongArch::VSAT_B:
    case LoongArch::VSAT_BU:
    case LoongArch::VSLLI_B:
    case LoongArch::VSLLWIL_HU_BU:
    case LoongArch::VSLLWIL_H_B:
    case LoongArch::VSRAI_B:
    case LoongArch::VSRARI_B:
    case LoongArch::VSRLI_B:
    case LoongArch::VSRLRI_B: {
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVPICKVE2GR_W:
    case LoongArch::XVPICKVE2GR_WU: {
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVBITCLRI_B:
    case LoongArch::XVBITREVI_B:
    case LoongArch::XVBITSETI_B:
    case LoongArch::XVPICKVE_W:
    case LoongArch::XVREPL128VEI_H:
    case LoongArch::XVROTRI_B:
    case LoongArch::XVSAT_B:
    case LoongArch::XVSAT_BU:
    case LoongArch::XVSLLI_B:
    case LoongArch::XVSLLWIL_HU_BU:
    case LoongArch::XVSLLWIL_H_B:
    case LoongArch::XVSRAI_B:
    case LoongArch::XVSRARI_B:
    case LoongArch::XVSRLI_B:
    case LoongArch::XVSRLRI_B: {
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VINSGR2VR_H: {
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVINSGR2VR_W: {
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVINSVE0_W: {
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::BYTEPICK_D: {
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 15;
      // op: rk
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VSTELM_H: {
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 18;
      // op: imm8
      op = getImmOpValueAsr<1>(MI, 2, Fixups, STI);
      Value |= (op & 0xff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVSTELM_W: {
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 18;
      // op: imm8
      op = getImmOpValueAsr<2>(MI, 2, Fixups, STI);
      Value |= (op & 0xff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::SETARMJ:
    case LoongArch::SETX86J: {
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 10;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::ARMMOV_D:
    case LoongArch::ARMMOV_W:
    case LoongArch::ARMNOT_W:
    case LoongArch::ARMRRX_W:
    case LoongArch::X86RCLI_H:
    case LoongArch::X86RCRI_H:
    case LoongArch::X86ROTLI_H:
    case LoongArch::X86ROTRI_H:
    case LoongArch::X86SLLI_H:
    case LoongArch::X86SRAI_H:
    case LoongArch::X86SRLI_H: {
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case LoongArch::ARMMOVE:
    case LoongArch::RCRI_H:
    case LoongArch::ROTRI_H: {
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VPICKVE2GR_B:
    case LoongArch::VPICKVE2GR_BU: {
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 10;
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VBITCLRI_H:
    case LoongArch::VBITREVI_H:
    case LoongArch::VBITSETI_H:
    case LoongArch::VREPLVEI_B:
    case LoongArch::VROTRI_H:
    case LoongArch::VSAT_H:
    case LoongArch::VSAT_HU:
    case LoongArch::VSLLI_H:
    case LoongArch::VSLLWIL_WU_HU:
    case LoongArch::VSLLWIL_W_H:
    case LoongArch::VSRAI_H:
    case LoongArch::VSRARI_H:
    case LoongArch::VSRLI_H:
    case LoongArch::VSRLRI_H: {
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 10;
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVBITCLRI_H:
    case LoongArch::XVBITREVI_H:
    case LoongArch::XVBITSETI_H:
    case LoongArch::XVREPL128VEI_B:
    case LoongArch::XVROTRI_H:
    case LoongArch::XVSAT_H:
    case LoongArch::XVSAT_HU:
    case LoongArch::XVSLLI_H:
    case LoongArch::XVSLLWIL_WU_HU:
    case LoongArch::XVSLLWIL_W_H:
    case LoongArch::XVSRAI_H:
    case LoongArch::XVSRARI_H:
    case LoongArch::XVSRLI_H:
    case LoongArch::XVSRLRI_H: {
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 10;
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::ARMADC_W:
    case LoongArch::ARMADD_W:
    case LoongArch::ARMAND_W:
    case LoongArch::ARMOR_W:
    case LoongArch::ARMROTR_W:
    case LoongArch::ARMSBC_W:
    case LoongArch::ARMSLL_W:
    case LoongArch::ARMSRA_W:
    case LoongArch::ARMSRL_W:
    case LoongArch::ARMSUB_W:
    case LoongArch::ARMXOR_W: {
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf);
      // op: rk
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case LoongArch::VINSGR2VR_B: {
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VSRANI_B_H:
    case LoongArch::VSRARNI_B_H:
    case LoongArch::VSRLNI_B_H:
    case LoongArch::VSRLRNI_B_H:
    case LoongArch::VSSRANI_BU_H:
    case LoongArch::VSSRANI_B_H:
    case LoongArch::VSSRARNI_BU_H:
    case LoongArch::VSSRARNI_B_H:
    case LoongArch::VSSRLNI_BU_H:
    case LoongArch::VSSRLNI_B_H:
    case LoongArch::VSSRLRNI_BU_H:
    case LoongArch::VSSRLRNI_B_H: {
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 10;
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVSRANI_B_H:
    case LoongArch::XVSRARNI_B_H:
    case LoongArch::XVSRLNI_B_H:
    case LoongArch::XVSRLRNI_B_H:
    case LoongArch::XVSSRANI_BU_H:
    case LoongArch::XVSSRANI_B_H:
    case LoongArch::XVSSRARNI_BU_H:
    case LoongArch::XVSSRARNI_B_H:
    case LoongArch::XVSSRLNI_BU_H:
    case LoongArch::XVSSRLNI_B_H:
    case LoongArch::XVSSRLRNI_BU_H:
    case LoongArch::XVSSRLRNI_B_H: {
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 10;
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVSTELM_H: {
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 18;
      // op: imm8
      op = getImmOpValueAsr<1>(MI, 2, Fixups, STI);
      Value |= (op & 0xff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VSTELM_B: {
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 18;
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::UD: {
      // op: imm5
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::X86RCLI_W:
    case LoongArch::X86RCRI_W:
    case LoongArch::X86ROTLI_W:
    case LoongArch::X86ROTRI_W:
    case LoongArch::X86SLLI_W:
    case LoongArch::X86SRAI_W:
    case LoongArch::X86SRLI_W: {
      // op: imm5
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case LoongArch::ARMROTRI_W:
    case LoongArch::ARMSLLI_W:
    case LoongArch::ARMSRAI_W:
    case LoongArch::ARMSRLI_W: {
      // op: imm5
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf);
      break;
    }
    case LoongArch::ADDU12I_D:
    case LoongArch::ADDU12I_W:
    case LoongArch::RCRI_W:
    case LoongArch::ROTRI_W:
    case LoongArch::SLLI_W:
    case LoongArch::SRAI_W:
    case LoongArch::SRLI_W: {
      // op: imm5
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VADDI_BU:
    case LoongArch::VADDI_DU:
    case LoongArch::VADDI_HU:
    case LoongArch::VADDI_WU:
    case LoongArch::VBITCLRI_W:
    case LoongArch::VBITREVI_W:
    case LoongArch::VBITSETI_W:
    case LoongArch::VBSLL_V:
    case LoongArch::VBSRL_V:
    case LoongArch::VMAXI_B:
    case LoongArch::VMAXI_BU:
    case LoongArch::VMAXI_D:
    case LoongArch::VMAXI_DU:
    case LoongArch::VMAXI_H:
    case LoongArch::VMAXI_HU:
    case LoongArch::VMAXI_W:
    case LoongArch::VMAXI_WU:
    case LoongArch::VMINI_B:
    case LoongArch::VMINI_BU:
    case LoongArch::VMINI_D:
    case LoongArch::VMINI_DU:
    case LoongArch::VMINI_H:
    case LoongArch::VMINI_HU:
    case LoongArch::VMINI_W:
    case LoongArch::VMINI_WU:
    case LoongArch::VROTRI_W:
    case LoongArch::VSAT_W:
    case LoongArch::VSAT_WU:
    case LoongArch::VSEQI_B:
    case LoongArch::VSEQI_D:
    case LoongArch::VSEQI_H:
    case LoongArch::VSEQI_W:
    case LoongArch::VSLEI_B:
    case LoongArch::VSLEI_BU:
    case LoongArch::VSLEI_D:
    case LoongArch::VSLEI_DU:
    case LoongArch::VSLEI_H:
    case LoongArch::VSLEI_HU:
    case LoongArch::VSLEI_W:
    case LoongArch::VSLEI_WU:
    case LoongArch::VSLLI_W:
    case LoongArch::VSLLWIL_DU_WU:
    case LoongArch::VSLLWIL_D_W:
    case LoongArch::VSLTI_B:
    case LoongArch::VSLTI_BU:
    case LoongArch::VSLTI_D:
    case LoongArch::VSLTI_DU:
    case LoongArch::VSLTI_H:
    case LoongArch::VSLTI_HU:
    case LoongArch::VSLTI_W:
    case LoongArch::VSLTI_WU:
    case LoongArch::VSRAI_W:
    case LoongArch::VSRARI_W:
    case LoongArch::VSRLI_W:
    case LoongArch::VSRLRI_W:
    case LoongArch::VSUBI_BU:
    case LoongArch::VSUBI_DU:
    case LoongArch::VSUBI_HU:
    case LoongArch::VSUBI_WU: {
      // op: imm5
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVADDI_BU:
    case LoongArch::XVADDI_DU:
    case LoongArch::XVADDI_HU:
    case LoongArch::XVADDI_WU:
    case LoongArch::XVBITCLRI_W:
    case LoongArch::XVBITREVI_W:
    case LoongArch::XVBITSETI_W:
    case LoongArch::XVBSLL_V:
    case LoongArch::XVBSRL_V:
    case LoongArch::XVHSELI_D:
    case LoongArch::XVMAXI_B:
    case LoongArch::XVMAXI_BU:
    case LoongArch::XVMAXI_D:
    case LoongArch::XVMAXI_DU:
    case LoongArch::XVMAXI_H:
    case LoongArch::XVMAXI_HU:
    case LoongArch::XVMAXI_W:
    case LoongArch::XVMAXI_WU:
    case LoongArch::XVMINI_B:
    case LoongArch::XVMINI_BU:
    case LoongArch::XVMINI_D:
    case LoongArch::XVMINI_DU:
    case LoongArch::XVMINI_H:
    case LoongArch::XVMINI_HU:
    case LoongArch::XVMINI_W:
    case LoongArch::XVMINI_WU:
    case LoongArch::XVROTRI_W:
    case LoongArch::XVSAT_W:
    case LoongArch::XVSAT_WU:
    case LoongArch::XVSEQI_B:
    case LoongArch::XVSEQI_D:
    case LoongArch::XVSEQI_H:
    case LoongArch::XVSEQI_W:
    case LoongArch::XVSLEI_B:
    case LoongArch::XVSLEI_BU:
    case LoongArch::XVSLEI_D:
    case LoongArch::XVSLEI_DU:
    case LoongArch::XVSLEI_H:
    case LoongArch::XVSLEI_HU:
    case LoongArch::XVSLEI_W:
    case LoongArch::XVSLEI_WU:
    case LoongArch::XVSLLI_W:
    case LoongArch::XVSLLWIL_DU_WU:
    case LoongArch::XVSLLWIL_D_W:
    case LoongArch::XVSLTI_B:
    case LoongArch::XVSLTI_BU:
    case LoongArch::XVSLTI_D:
    case LoongArch::XVSLTI_DU:
    case LoongArch::XVSLTI_H:
    case LoongArch::XVSLTI_HU:
    case LoongArch::XVSLTI_W:
    case LoongArch::XVSLTI_WU:
    case LoongArch::XVSRAI_W:
    case LoongArch::XVSRARI_W:
    case LoongArch::XVSRLI_W:
    case LoongArch::XVSRLRI_W:
    case LoongArch::XVSUBI_BU:
    case LoongArch::XVSUBI_DU:
    case LoongArch::XVSUBI_HU:
    case LoongArch::XVSUBI_WU: {
      // op: imm5
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VFRSTPI_B:
    case LoongArch::VFRSTPI_H:
    case LoongArch::VSRANI_H_W:
    case LoongArch::VSRARNI_H_W:
    case LoongArch::VSRLNI_H_W:
    case LoongArch::VSRLRNI_H_W:
    case LoongArch::VSSRANI_HU_W:
    case LoongArch::VSSRANI_H_W:
    case LoongArch::VSSRARNI_HU_W:
    case LoongArch::VSSRARNI_H_W:
    case LoongArch::VSSRLNI_HU_W:
    case LoongArch::VSSRLNI_H_W:
    case LoongArch::VSSRLRNI_HU_W:
    case LoongArch::VSSRLRNI_H_W: {
      // op: imm5
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVFRSTPI_B:
    case LoongArch::XVFRSTPI_H:
    case LoongArch::XVSRANI_H_W:
    case LoongArch::XVSRARNI_H_W:
    case LoongArch::XVSRLNI_H_W:
    case LoongArch::XVSRLRNI_H_W:
    case LoongArch::XVSSRANI_HU_W:
    case LoongArch::XVSSRANI_H_W:
    case LoongArch::XVSSRARNI_HU_W:
    case LoongArch::XVSSRARNI_H_W:
    case LoongArch::XVSSRLNI_HU_W:
    case LoongArch::XVSSRLNI_H_W:
    case LoongArch::XVSSRLRNI_HU_W:
    case LoongArch::XVSSRLRNI_H_W: {
      // op: imm5
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVSTELM_B: {
      // op: imm5
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 18;
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::X86RCLI_D:
    case LoongArch::X86RCRI_D:
    case LoongArch::X86ROTLI_D:
    case LoongArch::X86ROTRI_D:
    case LoongArch::X86SLLI_D:
    case LoongArch::X86SRAI_D:
    case LoongArch::X86SRLI_D: {
      // op: imm6
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case LoongArch::RCRI_D:
    case LoongArch::ROTRI_D:
    case LoongArch::SLLI_D:
    case LoongArch::SRAI_D:
    case LoongArch::SRLI_D: {
      // op: imm6
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VBITCLRI_D:
    case LoongArch::VBITREVI_D:
    case LoongArch::VBITSETI_D:
    case LoongArch::VROTRI_D:
    case LoongArch::VSAT_D:
    case LoongArch::VSAT_DU:
    case LoongArch::VSLLI_D:
    case LoongArch::VSRAI_D:
    case LoongArch::VSRARI_D:
    case LoongArch::VSRLI_D:
    case LoongArch::VSRLRI_D: {
      // op: imm6
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3f) << 10;
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVBITCLRI_D:
    case LoongArch::XVBITREVI_D:
    case LoongArch::XVBITSETI_D:
    case LoongArch::XVROTRI_D:
    case LoongArch::XVSAT_D:
    case LoongArch::XVSAT_DU:
    case LoongArch::XVSLLI_D:
    case LoongArch::XVSRAI_D:
    case LoongArch::XVSRARI_D:
    case LoongArch::XVSRLI_D:
    case LoongArch::XVSRLRI_D: {
      // op: imm6
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3f) << 10;
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VSRANI_W_D:
    case LoongArch::VSRARNI_W_D:
    case LoongArch::VSRLNI_W_D:
    case LoongArch::VSRLRNI_W_D:
    case LoongArch::VSSRANI_WU_D:
    case LoongArch::VSSRANI_W_D:
    case LoongArch::VSSRARNI_WU_D:
    case LoongArch::VSSRARNI_W_D:
    case LoongArch::VSSRLNI_WU_D:
    case LoongArch::VSSRLNI_W_D:
    case LoongArch::VSSRLRNI_WU_D:
    case LoongArch::VSSRLRNI_W_D: {
      // op: imm6
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3f) << 10;
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVSRANI_W_D:
    case LoongArch::XVSRARNI_W_D:
    case LoongArch::XVSRLNI_W_D:
    case LoongArch::XVSRLRNI_W_D:
    case LoongArch::XVSSRANI_WU_D:
    case LoongArch::XVSSRANI_W_D:
    case LoongArch::XVSSRARNI_WU_D:
    case LoongArch::XVSSRARNI_W_D:
    case LoongArch::XVSSRLNI_WU_D:
    case LoongArch::XVSSRLNI_W_D:
    case LoongArch::XVSSRLRNI_WU_D:
    case LoongArch::XVSSRLRNI_W_D: {
      // op: imm6
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3f) << 10;
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VSRANI_D_Q:
    case LoongArch::VSRARNI_D_Q:
    case LoongArch::VSRLNI_D_Q:
    case LoongArch::VSRLRNI_D_Q:
    case LoongArch::VSSRANI_DU_Q:
    case LoongArch::VSSRANI_D_Q:
    case LoongArch::VSSRARNI_DU_Q:
    case LoongArch::VSSRARNI_D_Q:
    case LoongArch::VSSRLNI_DU_Q:
    case LoongArch::VSSRLNI_D_Q:
    case LoongArch::VSSRLRNI_DU_Q:
    case LoongArch::VSSRLRNI_D_Q: {
      // op: imm7
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7f) << 10;
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVSRANI_D_Q:
    case LoongArch::XVSRARNI_D_Q:
    case LoongArch::XVSRLNI_D_Q:
    case LoongArch::XVSRLRNI_D_Q:
    case LoongArch::XVSSRANI_DU_Q:
    case LoongArch::XVSSRANI_D_Q:
    case LoongArch::XVSSRARNI_DU_Q:
    case LoongArch::XVSSRARNI_D_Q:
    case LoongArch::XVSSRLNI_DU_Q:
    case LoongArch::XVSSRLNI_D_Q:
    case LoongArch::XVSSRLRNI_DU_Q:
    case LoongArch::XVSSRLRNI_D_Q: {
      // op: imm7
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7f) << 10;
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::ARMMFFLAG:
    case LoongArch::ARMMTFLAG:
    case LoongArch::X86MFFLAG:
    case LoongArch::X86MTFLAG: {
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xff) << 10;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::X86SETTAG: {
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xff) << 10;
      // op: imm5
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::LDDIR: {
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VANDI_B:
    case LoongArch::VNORI_B:
    case LoongArch::VORI_B:
    case LoongArch::VSHUF4I_B:
    case LoongArch::VSHUF4I_H:
    case LoongArch::VSHUF4I_W:
    case LoongArch::VXORI_B: {
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xff) << 10;
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVANDI_B:
    case LoongArch::XVNORI_B:
    case LoongArch::XVORI_B:
    case LoongArch::XVPERMI_D:
    case LoongArch::XVSHUF4I_B:
    case LoongArch::XVSHUF4I_H:
    case LoongArch::XVSHUF4I_W:
    case LoongArch::XVXORI_B: {
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xff) << 10;
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VBITSELI_B:
    case LoongArch::VEXTRINS_B:
    case LoongArch::VEXTRINS_D:
    case LoongArch::VEXTRINS_H:
    case LoongArch::VEXTRINS_W:
    case LoongArch::VPERMI_W:
    case LoongArch::VSHUF4I_D: {
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xff) << 10;
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVBITSELI_B:
    case LoongArch::XVEXTRINS_B:
    case LoongArch::XVEXTRINS_D:
    case LoongArch::XVEXTRINS_H:
    case LoongArch::XVEXTRINS_W:
    case LoongArch::XVPERMI_Q:
    case LoongArch::XVPERMI_W:
    case LoongArch::XVSHUF4I_D: {
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xff) << 10;
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VLDREPL_D: {
      // op: imm9
      op = getImmOpValueAsr<3>(MI, 2, Fixups, STI);
      Value |= (op & 0x1ff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVLDREPL_D: {
      // op: imm9
      op = getImmOpValueAsr<3>(MI, 2, Fixups, STI);
      Value |= (op & 0x1ff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::BSTRPICK_D: {
      // op: msbd
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3f) << 16;
      // op: lsbd
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::BSTRINS_D: {
      // op: msbd
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3f) << 16;
      // op: lsbd
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x3f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::BSTRPICK_W: {
      // op: msbw
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: lsbw
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::BSTRINS_W: {
      // op: msbw
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: lsbw
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::X86MTTOP: {
      // op: ptr
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case LoongArch::X86MFTOP: {
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::X86DEC_B:
    case LoongArch::X86DEC_D:
    case LoongArch::X86DEC_H:
    case LoongArch::X86DEC_W:
    case LoongArch::X86INC_B:
    case LoongArch::X86INC_D:
    case LoongArch::X86INC_H:
    case LoongArch::X86INC_W: {
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case LoongArch::BITREV_4B:
    case LoongArch::BITREV_8B:
    case LoongArch::BITREV_D:
    case LoongArch::BITREV_W:
    case LoongArch::CLO_D:
    case LoongArch::CLO_W:
    case LoongArch::CLZ_D:
    case LoongArch::CLZ_W:
    case LoongArch::CPUCFG:
    case LoongArch::CTO_D:
    case LoongArch::CTO_W:
    case LoongArch::CTZ_D:
    case LoongArch::CTZ_W:
    case LoongArch::EXT_W_B:
    case LoongArch::EXT_W_H:
    case LoongArch::IOCSRRD_B:
    case LoongArch::IOCSRRD_D:
    case LoongArch::IOCSRRD_H:
    case LoongArch::IOCSRRD_W:
    case LoongArch::IOCSRWR_B:
    case LoongArch::IOCSRWR_D:
    case LoongArch::IOCSRWR_H:
    case LoongArch::IOCSRWR_W:
    case LoongArch::LLACQ_D:
    case LoongArch::LLACQ_W:
    case LoongArch::RDTIMEH_W:
    case LoongArch::RDTIMEL_W:
    case LoongArch::RDTIME_D:
    case LoongArch::REVB_2H:
    case LoongArch::REVB_2W:
    case LoongArch::REVB_4H:
    case LoongArch::REVB_D:
    case LoongArch::REVH_2W:
    case LoongArch::REVH_D:
    case LoongArch::SETX86LOOPE:
    case LoongArch::SETX86LOOPNE: {
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::MOVGR2SCR: {
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: sd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3);
      break;
    }
    case LoongArch::VREPLGR2VR_B:
    case LoongArch::VREPLGR2VR_D:
    case LoongArch::VREPLGR2VR_H:
    case LoongArch::VREPLGR2VR_W: {
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVREPLGR2VR_B:
    case LoongArch::XVREPLGR2VR_D:
    case LoongArch::XVREPLGR2VR_H:
    case LoongArch::XVREPLGR2VR_W: {
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::SCREL_D:
    case LoongArch::SCREL_W: {
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::INVTLB: {
      // op: rk
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: op
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::ASRTGT_D:
    case LoongArch::ASRTLE_D:
    case LoongArch::X86ADC_B:
    case LoongArch::X86ADC_D:
    case LoongArch::X86ADC_H:
    case LoongArch::X86ADC_W:
    case LoongArch::X86ADD_B:
    case LoongArch::X86ADD_D:
    case LoongArch::X86ADD_DU:
    case LoongArch::X86ADD_H:
    case LoongArch::X86ADD_W:
    case LoongArch::X86ADD_WU:
    case LoongArch::X86AND_B:
    case LoongArch::X86AND_D:
    case LoongArch::X86AND_H:
    case LoongArch::X86AND_W:
    case LoongArch::X86MUL_B:
    case LoongArch::X86MUL_BU:
    case LoongArch::X86MUL_D:
    case LoongArch::X86MUL_DU:
    case LoongArch::X86MUL_H:
    case LoongArch::X86MUL_HU:
    case LoongArch::X86MUL_W:
    case LoongArch::X86MUL_WU:
    case LoongArch::X86OR_B:
    case LoongArch::X86OR_D:
    case LoongArch::X86OR_H:
    case LoongArch::X86OR_W:
    case LoongArch::X86RCL_B:
    case LoongArch::X86RCL_D:
    case LoongArch::X86RCL_H:
    case LoongArch::X86RCL_W:
    case LoongArch::X86RCR_B:
    case LoongArch::X86RCR_D:
    case LoongArch::X86RCR_H:
    case LoongArch::X86RCR_W:
    case LoongArch::X86ROTL_B:
    case LoongArch::X86ROTL_D:
    case LoongArch::X86ROTL_H:
    case LoongArch::X86ROTL_W:
    case LoongArch::X86ROTR_B:
    case LoongArch::X86ROTR_D:
    case LoongArch::X86ROTR_H:
    case LoongArch::X86ROTR_W:
    case LoongArch::X86SBC_B:
    case LoongArch::X86SBC_D:
    case LoongArch::X86SBC_H:
    case LoongArch::X86SBC_W:
    case LoongArch::X86SLL_B:
    case LoongArch::X86SLL_D:
    case LoongArch::X86SLL_H:
    case LoongArch::X86SLL_W:
    case LoongArch::X86SRA_B:
    case LoongArch::X86SRA_D:
    case LoongArch::X86SRA_H:
    case LoongArch::X86SRA_W:
    case LoongArch::X86SRL_B:
    case LoongArch::X86SRL_D:
    case LoongArch::X86SRL_H:
    case LoongArch::X86SRL_W:
    case LoongArch::X86SUB_B:
    case LoongArch::X86SUB_D:
    case LoongArch::X86SUB_DU:
    case LoongArch::X86SUB_H:
    case LoongArch::X86SUB_W:
    case LoongArch::X86SUB_WU:
    case LoongArch::X86XOR_B:
    case LoongArch::X86XOR_D:
    case LoongArch::X86XOR_H:
    case LoongArch::X86XOR_W: {
      // op: rk
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case LoongArch::AMADD_B:
    case LoongArch::AMADD_D:
    case LoongArch::AMADD_H:
    case LoongArch::AMADD_W:
    case LoongArch::AMADD__DB_B:
    case LoongArch::AMADD__DB_D:
    case LoongArch::AMADD__DB_H:
    case LoongArch::AMADD__DB_W:
    case LoongArch::AMAND_D:
    case LoongArch::AMAND_W:
    case LoongArch::AMAND__DB_D:
    case LoongArch::AMAND__DB_W:
    case LoongArch::AMMAX_D:
    case LoongArch::AMMAX_DU:
    case LoongArch::AMMAX_W:
    case LoongArch::AMMAX_WU:
    case LoongArch::AMMAX__DB_D:
    case LoongArch::AMMAX__DB_DU:
    case LoongArch::AMMAX__DB_W:
    case LoongArch::AMMAX__DB_WU:
    case LoongArch::AMMIN_D:
    case LoongArch::AMMIN_DU:
    case LoongArch::AMMIN_W:
    case LoongArch::AMMIN_WU:
    case LoongArch::AMMIN__DB_D:
    case LoongArch::AMMIN__DB_DU:
    case LoongArch::AMMIN__DB_W:
    case LoongArch::AMMIN__DB_WU:
    case LoongArch::AMOR_D:
    case LoongArch::AMOR_W:
    case LoongArch::AMOR__DB_D:
    case LoongArch::AMOR__DB_W:
    case LoongArch::AMSWAP_B:
    case LoongArch::AMSWAP_D:
    case LoongArch::AMSWAP_H:
    case LoongArch::AMSWAP_W:
    case LoongArch::AMSWAP__DB_B:
    case LoongArch::AMSWAP__DB_D:
    case LoongArch::AMSWAP__DB_H:
    case LoongArch::AMSWAP__DB_W:
    case LoongArch::AMXOR_D:
    case LoongArch::AMXOR_W:
    case LoongArch::AMXOR__DB_D:
    case LoongArch::AMXOR__DB_W: {
      // op: rk
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::FLDGT_D:
    case LoongArch::FLDGT_S:
    case LoongArch::FLDLE_D:
    case LoongArch::FLDLE_S:
    case LoongArch::FLDX_D:
    case LoongArch::FLDX_S:
    case LoongArch::FSTGT_D:
    case LoongArch::FSTGT_S:
    case LoongArch::FSTLE_D:
    case LoongArch::FSTLE_S:
    case LoongArch::FSTX_D:
    case LoongArch::FSTX_S: {
      // op: rk
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: fd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::PRELDX: {
      // op: rk
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm5
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::ADC_B:
    case LoongArch::ADC_D:
    case LoongArch::ADC_H:
    case LoongArch::ADC_W:
    case LoongArch::ADD_D:
    case LoongArch::ADD_W:
    case LoongArch::AND:
    case LoongArch::ANDN:
    case LoongArch::CRCC_W_B_W:
    case LoongArch::CRCC_W_D_W:
    case LoongArch::CRCC_W_H_W:
    case LoongArch::CRCC_W_W_W:
    case LoongArch::CRC_W_B_W:
    case LoongArch::CRC_W_D_W:
    case LoongArch::CRC_W_H_W:
    case LoongArch::CRC_W_W_W:
    case LoongArch::DIV_D:
    case LoongArch::DIV_DU:
    case LoongArch::DIV_W:
    case LoongArch::DIV_WU:
    case LoongArch::LDGT_B:
    case LoongArch::LDGT_D:
    case LoongArch::LDGT_H:
    case LoongArch::LDGT_W:
    case LoongArch::LDLE_B:
    case LoongArch::LDLE_D:
    case LoongArch::LDLE_H:
    case LoongArch::LDLE_W:
    case LoongArch::LDX_B:
    case LoongArch::LDX_BU:
    case LoongArch::LDX_D:
    case LoongArch::LDX_H:
    case LoongArch::LDX_HU:
    case LoongArch::LDX_W:
    case LoongArch::LDX_WU:
    case LoongArch::MASKEQZ:
    case LoongArch::MASKNEZ:
    case LoongArch::MOD_D:
    case LoongArch::MOD_DU:
    case LoongArch::MOD_W:
    case LoongArch::MOD_WU:
    case LoongArch::MULH_D:
    case LoongArch::MULH_DU:
    case LoongArch::MULH_W:
    case LoongArch::MULH_WU:
    case LoongArch::MULW_D_W:
    case LoongArch::MULW_D_WU:
    case LoongArch::MUL_D:
    case LoongArch::MUL_W:
    case LoongArch::NOR:
    case LoongArch::OR:
    case LoongArch::ORN:
    case LoongArch::RCR_B:
    case LoongArch::RCR_D:
    case LoongArch::RCR_H:
    case LoongArch::RCR_W:
    case LoongArch::ROTR_B:
    case LoongArch::ROTR_D:
    case LoongArch::ROTR_H:
    case LoongArch::ROTR_W:
    case LoongArch::SBC_B:
    case LoongArch::SBC_D:
    case LoongArch::SBC_H:
    case LoongArch::SBC_W:
    case LoongArch::SLL_D:
    case LoongArch::SLL_W:
    case LoongArch::SLT:
    case LoongArch::SLTU:
    case LoongArch::SRA_D:
    case LoongArch::SRA_W:
    case LoongArch::SRL_D:
    case LoongArch::SRL_W:
    case LoongArch::STGT_B:
    case LoongArch::STGT_D:
    case LoongArch::STGT_H:
    case LoongArch::STGT_W:
    case LoongArch::STLE_B:
    case LoongArch::STLE_D:
    case LoongArch::STLE_H:
    case LoongArch::STLE_W:
    case LoongArch::STX_B:
    case LoongArch::STX_D:
    case LoongArch::STX_H:
    case LoongArch::STX_W:
    case LoongArch::SUB_D:
    case LoongArch::SUB_W:
    case LoongArch::XOR: {
      // op: rk
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VLDX:
    case LoongArch::VSTX: {
      // op: rk
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVLDX:
    case LoongArch::XVSTX: {
      // op: rk
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::AMCAS_B:
    case LoongArch::AMCAS_D:
    case LoongArch::AMCAS_H:
    case LoongArch::AMCAS_W:
    case LoongArch::AMCAS__DB_B:
    case LoongArch::AMCAS__DB_D:
    case LoongArch::AMCAS__DB_H:
    case LoongArch::AMCAS__DB_W:
    case LoongArch::SC_Q: {
      // op: rk
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VREPLVE_B:
    case LoongArch::VREPLVE_D:
    case LoongArch::VREPLVE_H:
    case LoongArch::VREPLVE_W: {
      // op: rk
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVREPLVE_B:
    case LoongArch::XVREPLVE_D:
    case LoongArch::XVREPLVE_H:
    case LoongArch::XVREPLVE_W: {
      // op: rk
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::LDPTE: {
      // op: seq
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xff) << 10;
      // op: rj
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case LoongArch::MOVSCR2GR: {
      // op: sj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3) << 5;
      // op: rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::FMOV_D:
    case LoongArch::FMOV_S:
    case LoongArch::MOVCF2FR_xS:
    case LoongArch::MOVCF2GR:
    case LoongArch::MOVFCSR2GR:
    case LoongArch::MOVFR2CF_xS:
    case LoongArch::MOVFR2GR_D:
    case LoongArch::MOVFR2GR_S:
    case LoongArch::MOVFR2GR_S_64:
    case LoongArch::MOVFRH2GR_S:
    case LoongArch::MOVGR2CF:
    case LoongArch::MOVGR2FCSR:
    case LoongArch::MOVGR2FR_D:
    case LoongArch::MOVGR2FR_W:
    case LoongArch::MOVGR2FR_W_64: {
      // op: src
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: dst
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::MOVGR2FRH_W: {
      // op: src
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: dst
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VBITSEL_V:
    case LoongArch::VFMADD_D:
    case LoongArch::VFMADD_S:
    case LoongArch::VFMSUB_D:
    case LoongArch::VFMSUB_S:
    case LoongArch::VFNMADD_D:
    case LoongArch::VFNMADD_S:
    case LoongArch::VFNMSUB_D:
    case LoongArch::VFNMSUB_S:
    case LoongArch::VSHUF_B: {
      // op: va
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 15;
      // op: vk
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VSETALLNEZ_B:
    case LoongArch::VSETALLNEZ_D:
    case LoongArch::VSETALLNEZ_H:
    case LoongArch::VSETALLNEZ_W:
    case LoongArch::VSETANYEQZ_B:
    case LoongArch::VSETANYEQZ_D:
    case LoongArch::VSETANYEQZ_H:
    case LoongArch::VSETANYEQZ_W:
    case LoongArch::VSETEQZ_V:
    case LoongArch::VSETNEZ_V: {
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: cd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case LoongArch::VCLO_B:
    case LoongArch::VCLO_D:
    case LoongArch::VCLO_H:
    case LoongArch::VCLO_W:
    case LoongArch::VCLZ_B:
    case LoongArch::VCLZ_D:
    case LoongArch::VCLZ_H:
    case LoongArch::VCLZ_W:
    case LoongArch::VEXTH_DU_WU:
    case LoongArch::VEXTH_D_W:
    case LoongArch::VEXTH_HU_BU:
    case LoongArch::VEXTH_H_B:
    case LoongArch::VEXTH_QU_DU:
    case LoongArch::VEXTH_Q_D:
    case LoongArch::VEXTH_WU_HU:
    case LoongArch::VEXTH_W_H:
    case LoongArch::VEXTL_QU_DU:
    case LoongArch::VEXTL_Q_D:
    case LoongArch::VFCLASS_D:
    case LoongArch::VFCLASS_S:
    case LoongArch::VFCVTH_D_S:
    case LoongArch::VFCVTH_S_H:
    case LoongArch::VFCVTL_D_S:
    case LoongArch::VFCVTL_S_H:
    case LoongArch::VFFINTH_D_W:
    case LoongArch::VFFINTL_D_W:
    case LoongArch::VFFINT_D_L:
    case LoongArch::VFFINT_D_LU:
    case LoongArch::VFFINT_S_W:
    case LoongArch::VFFINT_S_WU:
    case LoongArch::VFLOGB_D:
    case LoongArch::VFLOGB_S:
    case LoongArch::VFRECIPE_D:
    case LoongArch::VFRECIPE_S:
    case LoongArch::VFRECIP_D:
    case LoongArch::VFRECIP_S:
    case LoongArch::VFRINTRM_D:
    case LoongArch::VFRINTRM_S:
    case LoongArch::VFRINTRNE_D:
    case LoongArch::VFRINTRNE_S:
    case LoongArch::VFRINTRP_D:
    case LoongArch::VFRINTRP_S:
    case LoongArch::VFRINTRZ_D:
    case LoongArch::VFRINTRZ_S:
    case LoongArch::VFRINT_D:
    case LoongArch::VFRINT_S:
    case LoongArch::VFRSQRTE_D:
    case LoongArch::VFRSQRTE_S:
    case LoongArch::VFRSQRT_D:
    case LoongArch::VFRSQRT_S:
    case LoongArch::VFSQRT_D:
    case LoongArch::VFSQRT_S:
    case LoongArch::VFTINTH_L_S:
    case LoongArch::VFTINTL_L_S:
    case LoongArch::VFTINTRMH_L_S:
    case LoongArch::VFTINTRML_L_S:
    case LoongArch::VFTINTRM_L_D:
    case LoongArch::VFTINTRM_W_S:
    case LoongArch::VFTINTRNEH_L_S:
    case LoongArch::VFTINTRNEL_L_S:
    case LoongArch::VFTINTRNE_L_D:
    case LoongArch::VFTINTRNE_W_S:
    case LoongArch::VFTINTRPH_L_S:
    case LoongArch::VFTINTRPL_L_S:
    case LoongArch::VFTINTRP_L_D:
    case LoongArch::VFTINTRP_W_S:
    case LoongArch::VFTINTRZH_L_S:
    case LoongArch::VFTINTRZL_L_S:
    case LoongArch::VFTINTRZ_LU_D:
    case LoongArch::VFTINTRZ_L_D:
    case LoongArch::VFTINTRZ_WU_S:
    case LoongArch::VFTINTRZ_W_S:
    case LoongArch::VFTINT_LU_D:
    case LoongArch::VFTINT_L_D:
    case LoongArch::VFTINT_WU_S:
    case LoongArch::VFTINT_W_S:
    case LoongArch::VMSKGEZ_B:
    case LoongArch::VMSKLTZ_B:
    case LoongArch::VMSKLTZ_D:
    case LoongArch::VMSKLTZ_H:
    case LoongArch::VMSKLTZ_W:
    case LoongArch::VMSKNZ_B:
    case LoongArch::VNEG_B:
    case LoongArch::VNEG_D:
    case LoongArch::VNEG_H:
    case LoongArch::VNEG_W:
    case LoongArch::VPCNT_B:
    case LoongArch::VPCNT_D:
    case LoongArch::VPCNT_H:
    case LoongArch::VPCNT_W: {
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VABSD_B:
    case LoongArch::VABSD_BU:
    case LoongArch::VABSD_D:
    case LoongArch::VABSD_DU:
    case LoongArch::VABSD_H:
    case LoongArch::VABSD_HU:
    case LoongArch::VABSD_W:
    case LoongArch::VABSD_WU:
    case LoongArch::VADDA_B:
    case LoongArch::VADDA_D:
    case LoongArch::VADDA_H:
    case LoongArch::VADDA_W:
    case LoongArch::VADDWEV_D_W:
    case LoongArch::VADDWEV_D_WU:
    case LoongArch::VADDWEV_D_WU_W:
    case LoongArch::VADDWEV_H_B:
    case LoongArch::VADDWEV_H_BU:
    case LoongArch::VADDWEV_H_BU_B:
    case LoongArch::VADDWEV_Q_D:
    case LoongArch::VADDWEV_Q_DU:
    case LoongArch::VADDWEV_Q_DU_D:
    case LoongArch::VADDWEV_W_H:
    case LoongArch::VADDWEV_W_HU:
    case LoongArch::VADDWEV_W_HU_H:
    case LoongArch::VADDWOD_D_W:
    case LoongArch::VADDWOD_D_WU:
    case LoongArch::VADDWOD_D_WU_W:
    case LoongArch::VADDWOD_H_B:
    case LoongArch::VADDWOD_H_BU:
    case LoongArch::VADDWOD_H_BU_B:
    case LoongArch::VADDWOD_Q_D:
    case LoongArch::VADDWOD_Q_DU:
    case LoongArch::VADDWOD_Q_DU_D:
    case LoongArch::VADDWOD_W_H:
    case LoongArch::VADDWOD_W_HU:
    case LoongArch::VADDWOD_W_HU_H:
    case LoongArch::VADD_B:
    case LoongArch::VADD_D:
    case LoongArch::VADD_H:
    case LoongArch::VADD_Q:
    case LoongArch::VADD_W:
    case LoongArch::VANDN_V:
    case LoongArch::VAND_V:
    case LoongArch::VAVGR_B:
    case LoongArch::VAVGR_BU:
    case LoongArch::VAVGR_D:
    case LoongArch::VAVGR_DU:
    case LoongArch::VAVGR_H:
    case LoongArch::VAVGR_HU:
    case LoongArch::VAVGR_W:
    case LoongArch::VAVGR_WU:
    case LoongArch::VAVG_B:
    case LoongArch::VAVG_BU:
    case LoongArch::VAVG_D:
    case LoongArch::VAVG_DU:
    case LoongArch::VAVG_H:
    case LoongArch::VAVG_HU:
    case LoongArch::VAVG_W:
    case LoongArch::VAVG_WU:
    case LoongArch::VBITCLR_B:
    case LoongArch::VBITCLR_D:
    case LoongArch::VBITCLR_H:
    case LoongArch::VBITCLR_W:
    case LoongArch::VBITREV_B:
    case LoongArch::VBITREV_D:
    case LoongArch::VBITREV_H:
    case LoongArch::VBITREV_W:
    case LoongArch::VBITSET_B:
    case LoongArch::VBITSET_D:
    case LoongArch::VBITSET_H:
    case LoongArch::VBITSET_W:
    case LoongArch::VDIV_B:
    case LoongArch::VDIV_BU:
    case LoongArch::VDIV_D:
    case LoongArch::VDIV_DU:
    case LoongArch::VDIV_H:
    case LoongArch::VDIV_HU:
    case LoongArch::VDIV_W:
    case LoongArch::VDIV_WU:
    case LoongArch::VFADD_D:
    case LoongArch::VFADD_S:
    case LoongArch::VFCMP_CAF_D:
    case LoongArch::VFCMP_CAF_S:
    case LoongArch::VFCMP_CEQ_D:
    case LoongArch::VFCMP_CEQ_S:
    case LoongArch::VFCMP_CLE_D:
    case LoongArch::VFCMP_CLE_S:
    case LoongArch::VFCMP_CLT_D:
    case LoongArch::VFCMP_CLT_S:
    case LoongArch::VFCMP_CNE_D:
    case LoongArch::VFCMP_CNE_S:
    case LoongArch::VFCMP_COR_D:
    case LoongArch::VFCMP_COR_S:
    case LoongArch::VFCMP_CUEQ_D:
    case LoongArch::VFCMP_CUEQ_S:
    case LoongArch::VFCMP_CULE_D:
    case LoongArch::VFCMP_CULE_S:
    case LoongArch::VFCMP_CULT_D:
    case LoongArch::VFCMP_CULT_S:
    case LoongArch::VFCMP_CUNE_D:
    case LoongArch::VFCMP_CUNE_S:
    case LoongArch::VFCMP_CUN_D:
    case LoongArch::VFCMP_CUN_S:
    case LoongArch::VFCMP_SAF_D:
    case LoongArch::VFCMP_SAF_S:
    case LoongArch::VFCMP_SEQ_D:
    case LoongArch::VFCMP_SEQ_S:
    case LoongArch::VFCMP_SLE_D:
    case LoongArch::VFCMP_SLE_S:
    case LoongArch::VFCMP_SLT_D:
    case LoongArch::VFCMP_SLT_S:
    case LoongArch::VFCMP_SNE_D:
    case LoongArch::VFCMP_SNE_S:
    case LoongArch::VFCMP_SOR_D:
    case LoongArch::VFCMP_SOR_S:
    case LoongArch::VFCMP_SUEQ_D:
    case LoongArch::VFCMP_SUEQ_S:
    case LoongArch::VFCMP_SULE_D:
    case LoongArch::VFCMP_SULE_S:
    case LoongArch::VFCMP_SULT_D:
    case LoongArch::VFCMP_SULT_S:
    case LoongArch::VFCMP_SUNE_D:
    case LoongArch::VFCMP_SUNE_S:
    case LoongArch::VFCMP_SUN_D:
    case LoongArch::VFCMP_SUN_S:
    case LoongArch::VFCVT_H_S:
    case LoongArch::VFCVT_S_D:
    case LoongArch::VFDIV_D:
    case LoongArch::VFDIV_S:
    case LoongArch::VFFINT_S_L:
    case LoongArch::VFMAXA_D:
    case LoongArch::VFMAXA_S:
    case LoongArch::VFMAX_D:
    case LoongArch::VFMAX_S:
    case LoongArch::VFMINA_D:
    case LoongArch::VFMINA_S:
    case LoongArch::VFMIN_D:
    case LoongArch::VFMIN_S:
    case LoongArch::VFMUL_D:
    case LoongArch::VFMUL_S:
    case LoongArch::VFSUB_D:
    case LoongArch::VFSUB_S:
    case LoongArch::VFTINTRM_W_D:
    case LoongArch::VFTINTRNE_W_D:
    case LoongArch::VFTINTRP_W_D:
    case LoongArch::VFTINTRZ_W_D:
    case LoongArch::VFTINT_W_D:
    case LoongArch::VHADDW_DU_WU:
    case LoongArch::VHADDW_D_W:
    case LoongArch::VHADDW_HU_BU:
    case LoongArch::VHADDW_H_B:
    case LoongArch::VHADDW_QU_DU:
    case LoongArch::VHADDW_Q_D:
    case LoongArch::VHADDW_WU_HU:
    case LoongArch::VHADDW_W_H:
    case LoongArch::VHSUBW_DU_WU:
    case LoongArch::VHSUBW_D_W:
    case LoongArch::VHSUBW_HU_BU:
    case LoongArch::VHSUBW_H_B:
    case LoongArch::VHSUBW_QU_DU:
    case LoongArch::VHSUBW_Q_D:
    case LoongArch::VHSUBW_WU_HU:
    case LoongArch::VHSUBW_W_H:
    case LoongArch::VILVH_B:
    case LoongArch::VILVH_D:
    case LoongArch::VILVH_H:
    case LoongArch::VILVH_W:
    case LoongArch::VILVL_B:
    case LoongArch::VILVL_D:
    case LoongArch::VILVL_H:
    case LoongArch::VILVL_W:
    case LoongArch::VMAX_B:
    case LoongArch::VMAX_BU:
    case LoongArch::VMAX_D:
    case LoongArch::VMAX_DU:
    case LoongArch::VMAX_H:
    case LoongArch::VMAX_HU:
    case LoongArch::VMAX_W:
    case LoongArch::VMAX_WU:
    case LoongArch::VMIN_B:
    case LoongArch::VMIN_BU:
    case LoongArch::VMIN_D:
    case LoongArch::VMIN_DU:
    case LoongArch::VMIN_H:
    case LoongArch::VMIN_HU:
    case LoongArch::VMIN_W:
    case LoongArch::VMIN_WU:
    case LoongArch::VMOD_B:
    case LoongArch::VMOD_BU:
    case LoongArch::VMOD_D:
    case LoongArch::VMOD_DU:
    case LoongArch::VMOD_H:
    case LoongArch::VMOD_HU:
    case LoongArch::VMOD_W:
    case LoongArch::VMOD_WU:
    case LoongArch::VMUH_B:
    case LoongArch::VMUH_BU:
    case LoongArch::VMUH_D:
    case LoongArch::VMUH_DU:
    case LoongArch::VMUH_H:
    case LoongArch::VMUH_HU:
    case LoongArch::VMUH_W:
    case LoongArch::VMUH_WU:
    case LoongArch::VMULWEV_D_W:
    case LoongArch::VMULWEV_D_WU:
    case LoongArch::VMULWEV_D_WU_W:
    case LoongArch::VMULWEV_H_B:
    case LoongArch::VMULWEV_H_BU:
    case LoongArch::VMULWEV_H_BU_B:
    case LoongArch::VMULWEV_Q_D:
    case LoongArch::VMULWEV_Q_DU:
    case LoongArch::VMULWEV_Q_DU_D:
    case LoongArch::VMULWEV_W_H:
    case LoongArch::VMULWEV_W_HU:
    case LoongArch::VMULWEV_W_HU_H:
    case LoongArch::VMULWOD_D_W:
    case LoongArch::VMULWOD_D_WU:
    case LoongArch::VMULWOD_D_WU_W:
    case LoongArch::VMULWOD_H_B:
    case LoongArch::VMULWOD_H_BU:
    case LoongArch::VMULWOD_H_BU_B:
    case LoongArch::VMULWOD_Q_D:
    case LoongArch::VMULWOD_Q_DU:
    case LoongArch::VMULWOD_Q_DU_D:
    case LoongArch::VMULWOD_W_H:
    case LoongArch::VMULWOD_W_HU:
    case LoongArch::VMULWOD_W_HU_H:
    case LoongArch::VMUL_B:
    case LoongArch::VMUL_D:
    case LoongArch::VMUL_H:
    case LoongArch::VMUL_W:
    case LoongArch::VNOR_V:
    case LoongArch::VORN_V:
    case LoongArch::VOR_V:
    case LoongArch::VPACKEV_B:
    case LoongArch::VPACKEV_D:
    case LoongArch::VPACKEV_H:
    case LoongArch::VPACKEV_W:
    case LoongArch::VPACKOD_B:
    case LoongArch::VPACKOD_D:
    case LoongArch::VPACKOD_H:
    case LoongArch::VPACKOD_W:
    case LoongArch::VPICKEV_B:
    case LoongArch::VPICKEV_D:
    case LoongArch::VPICKEV_H:
    case LoongArch::VPICKEV_W:
    case LoongArch::VPICKOD_B:
    case LoongArch::VPICKOD_D:
    case LoongArch::VPICKOD_H:
    case LoongArch::VPICKOD_W:
    case LoongArch::VROTR_B:
    case LoongArch::VROTR_D:
    case LoongArch::VROTR_H:
    case LoongArch::VROTR_W:
    case LoongArch::VSADD_B:
    case LoongArch::VSADD_BU:
    case LoongArch::VSADD_D:
    case LoongArch::VSADD_DU:
    case LoongArch::VSADD_H:
    case LoongArch::VSADD_HU:
    case LoongArch::VSADD_W:
    case LoongArch::VSADD_WU:
    case LoongArch::VSEQ_B:
    case LoongArch::VSEQ_D:
    case LoongArch::VSEQ_H:
    case LoongArch::VSEQ_W:
    case LoongArch::VSIGNCOV_B:
    case LoongArch::VSIGNCOV_D:
    case LoongArch::VSIGNCOV_H:
    case LoongArch::VSIGNCOV_W:
    case LoongArch::VSLE_B:
    case LoongArch::VSLE_BU:
    case LoongArch::VSLE_D:
    case LoongArch::VSLE_DU:
    case LoongArch::VSLE_H:
    case LoongArch::VSLE_HU:
    case LoongArch::VSLE_W:
    case LoongArch::VSLE_WU:
    case LoongArch::VSLL_B:
    case LoongArch::VSLL_D:
    case LoongArch::VSLL_H:
    case LoongArch::VSLL_W:
    case LoongArch::VSLT_B:
    case LoongArch::VSLT_BU:
    case LoongArch::VSLT_D:
    case LoongArch::VSLT_DU:
    case LoongArch::VSLT_H:
    case LoongArch::VSLT_HU:
    case LoongArch::VSLT_W:
    case LoongArch::VSLT_WU:
    case LoongArch::VSRAN_B_H:
    case LoongArch::VSRAN_H_W:
    case LoongArch::VSRAN_W_D:
    case LoongArch::VSRARN_B_H:
    case LoongArch::VSRARN_H_W:
    case LoongArch::VSRARN_W_D:
    case LoongArch::VSRAR_B:
    case LoongArch::VSRAR_D:
    case LoongArch::VSRAR_H:
    case LoongArch::VSRAR_W:
    case LoongArch::VSRA_B:
    case LoongArch::VSRA_D:
    case LoongArch::VSRA_H:
    case LoongArch::VSRA_W:
    case LoongArch::VSRLN_B_H:
    case LoongArch::VSRLN_H_W:
    case LoongArch::VSRLN_W_D:
    case LoongArch::VSRLRN_B_H:
    case LoongArch::VSRLRN_H_W:
    case LoongArch::VSRLRN_W_D:
    case LoongArch::VSRLR_B:
    case LoongArch::VSRLR_D:
    case LoongArch::VSRLR_H:
    case LoongArch::VSRLR_W:
    case LoongArch::VSRL_B:
    case LoongArch::VSRL_D:
    case LoongArch::VSRL_H:
    case LoongArch::VSRL_W:
    case LoongArch::VSSRAN_BU_H:
    case LoongArch::VSSRAN_B_H:
    case LoongArch::VSSRAN_HU_W:
    case LoongArch::VSSRAN_H_W:
    case LoongArch::VSSRAN_WU_D:
    case LoongArch::VSSRAN_W_D:
    case LoongArch::VSSRARN_BU_H:
    case LoongArch::VSSRARN_B_H:
    case LoongArch::VSSRARN_HU_W:
    case LoongArch::VSSRARN_H_W:
    case LoongArch::VSSRARN_WU_D:
    case LoongArch::VSSRARN_W_D:
    case LoongArch::VSSRLN_BU_H:
    case LoongArch::VSSRLN_B_H:
    case LoongArch::VSSRLN_HU_W:
    case LoongArch::VSSRLN_H_W:
    case LoongArch::VSSRLN_WU_D:
    case LoongArch::VSSRLN_W_D:
    case LoongArch::VSSRLRN_BU_H:
    case LoongArch::VSSRLRN_B_H:
    case LoongArch::VSSRLRN_HU_W:
    case LoongArch::VSSRLRN_H_W:
    case LoongArch::VSSRLRN_WU_D:
    case LoongArch::VSSRLRN_W_D:
    case LoongArch::VSSUB_B:
    case LoongArch::VSSUB_BU:
    case LoongArch::VSSUB_D:
    case LoongArch::VSSUB_DU:
    case LoongArch::VSSUB_H:
    case LoongArch::VSSUB_HU:
    case LoongArch::VSSUB_W:
    case LoongArch::VSSUB_WU:
    case LoongArch::VSUBWEV_D_W:
    case LoongArch::VSUBWEV_D_WU:
    case LoongArch::VSUBWEV_H_B:
    case LoongArch::VSUBWEV_H_BU:
    case LoongArch::VSUBWEV_Q_D:
    case LoongArch::VSUBWEV_Q_DU:
    case LoongArch::VSUBWEV_W_H:
    case LoongArch::VSUBWEV_W_HU:
    case LoongArch::VSUBWOD_D_W:
    case LoongArch::VSUBWOD_D_WU:
    case LoongArch::VSUBWOD_H_B:
    case LoongArch::VSUBWOD_H_BU:
    case LoongArch::VSUBWOD_Q_D:
    case LoongArch::VSUBWOD_Q_DU:
    case LoongArch::VSUBWOD_W_H:
    case LoongArch::VSUBWOD_W_HU:
    case LoongArch::VSUB_B:
    case LoongArch::VSUB_D:
    case LoongArch::VSUB_H:
    case LoongArch::VSUB_Q:
    case LoongArch::VSUB_W:
    case LoongArch::VXOR_V: {
      // op: vk
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::VFRSTP_B:
    case LoongArch::VFRSTP_H:
    case LoongArch::VMADDWEV_D_W:
    case LoongArch::VMADDWEV_D_WU:
    case LoongArch::VMADDWEV_D_WU_W:
    case LoongArch::VMADDWEV_H_B:
    case LoongArch::VMADDWEV_H_BU:
    case LoongArch::VMADDWEV_H_BU_B:
    case LoongArch::VMADDWEV_Q_D:
    case LoongArch::VMADDWEV_Q_DU:
    case LoongArch::VMADDWEV_Q_DU_D:
    case LoongArch::VMADDWEV_W_H:
    case LoongArch::VMADDWEV_W_HU:
    case LoongArch::VMADDWEV_W_HU_H:
    case LoongArch::VMADDWOD_D_W:
    case LoongArch::VMADDWOD_D_WU:
    case LoongArch::VMADDWOD_D_WU_W:
    case LoongArch::VMADDWOD_H_B:
    case LoongArch::VMADDWOD_H_BU:
    case LoongArch::VMADDWOD_H_BU_B:
    case LoongArch::VMADDWOD_Q_D:
    case LoongArch::VMADDWOD_Q_DU:
    case LoongArch::VMADDWOD_Q_DU_D:
    case LoongArch::VMADDWOD_W_H:
    case LoongArch::VMADDWOD_W_HU:
    case LoongArch::VMADDWOD_W_HU_H:
    case LoongArch::VMADD_B:
    case LoongArch::VMADD_D:
    case LoongArch::VMADD_H:
    case LoongArch::VMADD_W:
    case LoongArch::VMSUB_B:
    case LoongArch::VMSUB_D:
    case LoongArch::VMSUB_H:
    case LoongArch::VMSUB_W:
    case LoongArch::VSHUF_D:
    case LoongArch::VSHUF_H:
    case LoongArch::VSHUF_W: {
      // op: vk
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: vj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVBITSEL_V:
    case LoongArch::XVFMADD_D:
    case LoongArch::XVFMADD_S:
    case LoongArch::XVFMSUB_D:
    case LoongArch::XVFMSUB_S:
    case LoongArch::XVFNMADD_D:
    case LoongArch::XVFNMADD_S:
    case LoongArch::XVFNMSUB_D:
    case LoongArch::XVFNMSUB_S:
    case LoongArch::XVSHUF_B: {
      // op: xa
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 15;
      // op: xk
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVSETALLNEZ_B:
    case LoongArch::XVSETALLNEZ_D:
    case LoongArch::XVSETALLNEZ_H:
    case LoongArch::XVSETALLNEZ_W:
    case LoongArch::XVSETANYEQZ_B:
    case LoongArch::XVSETANYEQZ_D:
    case LoongArch::XVSETANYEQZ_H:
    case LoongArch::XVSETANYEQZ_W:
    case LoongArch::XVSETEQZ_V:
    case LoongArch::XVSETNEZ_V: {
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: cd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case LoongArch::VEXT2XV_DU_BU:
    case LoongArch::VEXT2XV_DU_HU:
    case LoongArch::VEXT2XV_DU_WU:
    case LoongArch::VEXT2XV_D_B:
    case LoongArch::VEXT2XV_D_H:
    case LoongArch::VEXT2XV_D_W:
    case LoongArch::VEXT2XV_HU_BU:
    case LoongArch::VEXT2XV_H_B:
    case LoongArch::VEXT2XV_WU_BU:
    case LoongArch::VEXT2XV_WU_HU:
    case LoongArch::VEXT2XV_W_B:
    case LoongArch::VEXT2XV_W_H:
    case LoongArch::XVCLO_B:
    case LoongArch::XVCLO_D:
    case LoongArch::XVCLO_H:
    case LoongArch::XVCLO_W:
    case LoongArch::XVCLZ_B:
    case LoongArch::XVCLZ_D:
    case LoongArch::XVCLZ_H:
    case LoongArch::XVCLZ_W:
    case LoongArch::XVEXTH_DU_WU:
    case LoongArch::XVEXTH_D_W:
    case LoongArch::XVEXTH_HU_BU:
    case LoongArch::XVEXTH_H_B:
    case LoongArch::XVEXTH_QU_DU:
    case LoongArch::XVEXTH_Q_D:
    case LoongArch::XVEXTH_WU_HU:
    case LoongArch::XVEXTH_W_H:
    case LoongArch::XVEXTL_QU_DU:
    case LoongArch::XVEXTL_Q_D:
    case LoongArch::XVFCLASS_D:
    case LoongArch::XVFCLASS_S:
    case LoongArch::XVFCVTH_D_S:
    case LoongArch::XVFCVTH_S_H:
    case LoongArch::XVFCVTL_D_S:
    case LoongArch::XVFCVTL_S_H:
    case LoongArch::XVFFINTH_D_W:
    case LoongArch::XVFFINTL_D_W:
    case LoongArch::XVFFINT_D_L:
    case LoongArch::XVFFINT_D_LU:
    case LoongArch::XVFFINT_S_W:
    case LoongArch::XVFFINT_S_WU:
    case LoongArch::XVFLOGB_D:
    case LoongArch::XVFLOGB_S:
    case LoongArch::XVFRECIPE_D:
    case LoongArch::XVFRECIPE_S:
    case LoongArch::XVFRECIP_D:
    case LoongArch::XVFRECIP_S:
    case LoongArch::XVFRINTRM_D:
    case LoongArch::XVFRINTRM_S:
    case LoongArch::XVFRINTRNE_D:
    case LoongArch::XVFRINTRNE_S:
    case LoongArch::XVFRINTRP_D:
    case LoongArch::XVFRINTRP_S:
    case LoongArch::XVFRINTRZ_D:
    case LoongArch::XVFRINTRZ_S:
    case LoongArch::XVFRINT_D:
    case LoongArch::XVFRINT_S:
    case LoongArch::XVFRSQRTE_D:
    case LoongArch::XVFRSQRTE_S:
    case LoongArch::XVFRSQRT_D:
    case LoongArch::XVFRSQRT_S:
    case LoongArch::XVFSQRT_D:
    case LoongArch::XVFSQRT_S:
    case LoongArch::XVFTINTH_L_S:
    case LoongArch::XVFTINTL_L_S:
    case LoongArch::XVFTINTRMH_L_S:
    case LoongArch::XVFTINTRML_L_S:
    case LoongArch::XVFTINTRM_L_D:
    case LoongArch::XVFTINTRM_W_S:
    case LoongArch::XVFTINTRNEH_L_S:
    case LoongArch::XVFTINTRNEL_L_S:
    case LoongArch::XVFTINTRNE_L_D:
    case LoongArch::XVFTINTRNE_W_S:
    case LoongArch::XVFTINTRPH_L_S:
    case LoongArch::XVFTINTRPL_L_S:
    case LoongArch::XVFTINTRP_L_D:
    case LoongArch::XVFTINTRP_W_S:
    case LoongArch::XVFTINTRZH_L_S:
    case LoongArch::XVFTINTRZL_L_S:
    case LoongArch::XVFTINTRZ_LU_D:
    case LoongArch::XVFTINTRZ_L_D:
    case LoongArch::XVFTINTRZ_WU_S:
    case LoongArch::XVFTINTRZ_W_S:
    case LoongArch::XVFTINT_LU_D:
    case LoongArch::XVFTINT_L_D:
    case LoongArch::XVFTINT_WU_S:
    case LoongArch::XVFTINT_W_S:
    case LoongArch::XVMSKGEZ_B:
    case LoongArch::XVMSKLTZ_B:
    case LoongArch::XVMSKLTZ_D:
    case LoongArch::XVMSKLTZ_H:
    case LoongArch::XVMSKLTZ_W:
    case LoongArch::XVMSKNZ_B:
    case LoongArch::XVNEG_B:
    case LoongArch::XVNEG_D:
    case LoongArch::XVNEG_H:
    case LoongArch::XVNEG_W:
    case LoongArch::XVPCNT_B:
    case LoongArch::XVPCNT_D:
    case LoongArch::XVPCNT_H:
    case LoongArch::XVPCNT_W:
    case LoongArch::XVREPLVE0_B:
    case LoongArch::XVREPLVE0_D:
    case LoongArch::XVREPLVE0_H:
    case LoongArch::XVREPLVE0_Q:
    case LoongArch::XVREPLVE0_W: {
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVABSD_B:
    case LoongArch::XVABSD_BU:
    case LoongArch::XVABSD_D:
    case LoongArch::XVABSD_DU:
    case LoongArch::XVABSD_H:
    case LoongArch::XVABSD_HU:
    case LoongArch::XVABSD_W:
    case LoongArch::XVABSD_WU:
    case LoongArch::XVADDA_B:
    case LoongArch::XVADDA_D:
    case LoongArch::XVADDA_H:
    case LoongArch::XVADDA_W:
    case LoongArch::XVADDWEV_D_W:
    case LoongArch::XVADDWEV_D_WU:
    case LoongArch::XVADDWEV_D_WU_W:
    case LoongArch::XVADDWEV_H_B:
    case LoongArch::XVADDWEV_H_BU:
    case LoongArch::XVADDWEV_H_BU_B:
    case LoongArch::XVADDWEV_Q_D:
    case LoongArch::XVADDWEV_Q_DU:
    case LoongArch::XVADDWEV_Q_DU_D:
    case LoongArch::XVADDWEV_W_H:
    case LoongArch::XVADDWEV_W_HU:
    case LoongArch::XVADDWEV_W_HU_H:
    case LoongArch::XVADDWOD_D_W:
    case LoongArch::XVADDWOD_D_WU:
    case LoongArch::XVADDWOD_D_WU_W:
    case LoongArch::XVADDWOD_H_B:
    case LoongArch::XVADDWOD_H_BU:
    case LoongArch::XVADDWOD_H_BU_B:
    case LoongArch::XVADDWOD_Q_D:
    case LoongArch::XVADDWOD_Q_DU:
    case LoongArch::XVADDWOD_Q_DU_D:
    case LoongArch::XVADDWOD_W_H:
    case LoongArch::XVADDWOD_W_HU:
    case LoongArch::XVADDWOD_W_HU_H:
    case LoongArch::XVADD_B:
    case LoongArch::XVADD_D:
    case LoongArch::XVADD_H:
    case LoongArch::XVADD_Q:
    case LoongArch::XVADD_W:
    case LoongArch::XVANDN_V:
    case LoongArch::XVAND_V:
    case LoongArch::XVAVGR_B:
    case LoongArch::XVAVGR_BU:
    case LoongArch::XVAVGR_D:
    case LoongArch::XVAVGR_DU:
    case LoongArch::XVAVGR_H:
    case LoongArch::XVAVGR_HU:
    case LoongArch::XVAVGR_W:
    case LoongArch::XVAVGR_WU:
    case LoongArch::XVAVG_B:
    case LoongArch::XVAVG_BU:
    case LoongArch::XVAVG_D:
    case LoongArch::XVAVG_DU:
    case LoongArch::XVAVG_H:
    case LoongArch::XVAVG_HU:
    case LoongArch::XVAVG_W:
    case LoongArch::XVAVG_WU:
    case LoongArch::XVBITCLR_B:
    case LoongArch::XVBITCLR_D:
    case LoongArch::XVBITCLR_H:
    case LoongArch::XVBITCLR_W:
    case LoongArch::XVBITREV_B:
    case LoongArch::XVBITREV_D:
    case LoongArch::XVBITREV_H:
    case LoongArch::XVBITREV_W:
    case LoongArch::XVBITSET_B:
    case LoongArch::XVBITSET_D:
    case LoongArch::XVBITSET_H:
    case LoongArch::XVBITSET_W:
    case LoongArch::XVDIV_B:
    case LoongArch::XVDIV_BU:
    case LoongArch::XVDIV_D:
    case LoongArch::XVDIV_DU:
    case LoongArch::XVDIV_H:
    case LoongArch::XVDIV_HU:
    case LoongArch::XVDIV_W:
    case LoongArch::XVDIV_WU:
    case LoongArch::XVFADD_D:
    case LoongArch::XVFADD_S:
    case LoongArch::XVFCMP_CAF_D:
    case LoongArch::XVFCMP_CAF_S:
    case LoongArch::XVFCMP_CEQ_D:
    case LoongArch::XVFCMP_CEQ_S:
    case LoongArch::XVFCMP_CLE_D:
    case LoongArch::XVFCMP_CLE_S:
    case LoongArch::XVFCMP_CLT_D:
    case LoongArch::XVFCMP_CLT_S:
    case LoongArch::XVFCMP_CNE_D:
    case LoongArch::XVFCMP_CNE_S:
    case LoongArch::XVFCMP_COR_D:
    case LoongArch::XVFCMP_COR_S:
    case LoongArch::XVFCMP_CUEQ_D:
    case LoongArch::XVFCMP_CUEQ_S:
    case LoongArch::XVFCMP_CULE_D:
    case LoongArch::XVFCMP_CULE_S:
    case LoongArch::XVFCMP_CULT_D:
    case LoongArch::XVFCMP_CULT_S:
    case LoongArch::XVFCMP_CUNE_D:
    case LoongArch::XVFCMP_CUNE_S:
    case LoongArch::XVFCMP_CUN_D:
    case LoongArch::XVFCMP_CUN_S:
    case LoongArch::XVFCMP_SAF_D:
    case LoongArch::XVFCMP_SAF_S:
    case LoongArch::XVFCMP_SEQ_D:
    case LoongArch::XVFCMP_SEQ_S:
    case LoongArch::XVFCMP_SLE_D:
    case LoongArch::XVFCMP_SLE_S:
    case LoongArch::XVFCMP_SLT_D:
    case LoongArch::XVFCMP_SLT_S:
    case LoongArch::XVFCMP_SNE_D:
    case LoongArch::XVFCMP_SNE_S:
    case LoongArch::XVFCMP_SOR_D:
    case LoongArch::XVFCMP_SOR_S:
    case LoongArch::XVFCMP_SUEQ_D:
    case LoongArch::XVFCMP_SUEQ_S:
    case LoongArch::XVFCMP_SULE_D:
    case LoongArch::XVFCMP_SULE_S:
    case LoongArch::XVFCMP_SULT_D:
    case LoongArch::XVFCMP_SULT_S:
    case LoongArch::XVFCMP_SUNE_D:
    case LoongArch::XVFCMP_SUNE_S:
    case LoongArch::XVFCMP_SUN_D:
    case LoongArch::XVFCMP_SUN_S:
    case LoongArch::XVFCVT_H_S:
    case LoongArch::XVFCVT_S_D:
    case LoongArch::XVFDIV_D:
    case LoongArch::XVFDIV_S:
    case LoongArch::XVFFINT_S_L:
    case LoongArch::XVFMAXA_D:
    case LoongArch::XVFMAXA_S:
    case LoongArch::XVFMAX_D:
    case LoongArch::XVFMAX_S:
    case LoongArch::XVFMINA_D:
    case LoongArch::XVFMINA_S:
    case LoongArch::XVFMIN_D:
    case LoongArch::XVFMIN_S:
    case LoongArch::XVFMUL_D:
    case LoongArch::XVFMUL_S:
    case LoongArch::XVFSUB_D:
    case LoongArch::XVFSUB_S:
    case LoongArch::XVFTINTRM_W_D:
    case LoongArch::XVFTINTRNE_W_D:
    case LoongArch::XVFTINTRP_W_D:
    case LoongArch::XVFTINTRZ_W_D:
    case LoongArch::XVFTINT_W_D:
    case LoongArch::XVHADDW_DU_WU:
    case LoongArch::XVHADDW_D_W:
    case LoongArch::XVHADDW_HU_BU:
    case LoongArch::XVHADDW_H_B:
    case LoongArch::XVHADDW_QU_DU:
    case LoongArch::XVHADDW_Q_D:
    case LoongArch::XVHADDW_WU_HU:
    case LoongArch::XVHADDW_W_H:
    case LoongArch::XVHSUBW_DU_WU:
    case LoongArch::XVHSUBW_D_W:
    case LoongArch::XVHSUBW_HU_BU:
    case LoongArch::XVHSUBW_H_B:
    case LoongArch::XVHSUBW_QU_DU:
    case LoongArch::XVHSUBW_Q_D:
    case LoongArch::XVHSUBW_WU_HU:
    case LoongArch::XVHSUBW_W_H:
    case LoongArch::XVILVH_B:
    case LoongArch::XVILVH_D:
    case LoongArch::XVILVH_H:
    case LoongArch::XVILVH_W:
    case LoongArch::XVILVL_B:
    case LoongArch::XVILVL_D:
    case LoongArch::XVILVL_H:
    case LoongArch::XVILVL_W:
    case LoongArch::XVMAX_B:
    case LoongArch::XVMAX_BU:
    case LoongArch::XVMAX_D:
    case LoongArch::XVMAX_DU:
    case LoongArch::XVMAX_H:
    case LoongArch::XVMAX_HU:
    case LoongArch::XVMAX_W:
    case LoongArch::XVMAX_WU:
    case LoongArch::XVMIN_B:
    case LoongArch::XVMIN_BU:
    case LoongArch::XVMIN_D:
    case LoongArch::XVMIN_DU:
    case LoongArch::XVMIN_H:
    case LoongArch::XVMIN_HU:
    case LoongArch::XVMIN_W:
    case LoongArch::XVMIN_WU:
    case LoongArch::XVMOD_B:
    case LoongArch::XVMOD_BU:
    case LoongArch::XVMOD_D:
    case LoongArch::XVMOD_DU:
    case LoongArch::XVMOD_H:
    case LoongArch::XVMOD_HU:
    case LoongArch::XVMOD_W:
    case LoongArch::XVMOD_WU:
    case LoongArch::XVMUH_B:
    case LoongArch::XVMUH_BU:
    case LoongArch::XVMUH_D:
    case LoongArch::XVMUH_DU:
    case LoongArch::XVMUH_H:
    case LoongArch::XVMUH_HU:
    case LoongArch::XVMUH_W:
    case LoongArch::XVMUH_WU:
    case LoongArch::XVMULWEV_D_W:
    case LoongArch::XVMULWEV_D_WU:
    case LoongArch::XVMULWEV_D_WU_W:
    case LoongArch::XVMULWEV_H_B:
    case LoongArch::XVMULWEV_H_BU:
    case LoongArch::XVMULWEV_H_BU_B:
    case LoongArch::XVMULWEV_Q_D:
    case LoongArch::XVMULWEV_Q_DU:
    case LoongArch::XVMULWEV_Q_DU_D:
    case LoongArch::XVMULWEV_W_H:
    case LoongArch::XVMULWEV_W_HU:
    case LoongArch::XVMULWEV_W_HU_H:
    case LoongArch::XVMULWOD_D_W:
    case LoongArch::XVMULWOD_D_WU:
    case LoongArch::XVMULWOD_D_WU_W:
    case LoongArch::XVMULWOD_H_B:
    case LoongArch::XVMULWOD_H_BU:
    case LoongArch::XVMULWOD_H_BU_B:
    case LoongArch::XVMULWOD_Q_D:
    case LoongArch::XVMULWOD_Q_DU:
    case LoongArch::XVMULWOD_Q_DU_D:
    case LoongArch::XVMULWOD_W_H:
    case LoongArch::XVMULWOD_W_HU:
    case LoongArch::XVMULWOD_W_HU_H:
    case LoongArch::XVMUL_B:
    case LoongArch::XVMUL_D:
    case LoongArch::XVMUL_H:
    case LoongArch::XVMUL_W:
    case LoongArch::XVNOR_V:
    case LoongArch::XVORN_V:
    case LoongArch::XVOR_V:
    case LoongArch::XVPACKEV_B:
    case LoongArch::XVPACKEV_D:
    case LoongArch::XVPACKEV_H:
    case LoongArch::XVPACKEV_W:
    case LoongArch::XVPACKOD_B:
    case LoongArch::XVPACKOD_D:
    case LoongArch::XVPACKOD_H:
    case LoongArch::XVPACKOD_W:
    case LoongArch::XVPERM_W:
    case LoongArch::XVPICKEV_B:
    case LoongArch::XVPICKEV_D:
    case LoongArch::XVPICKEV_H:
    case LoongArch::XVPICKEV_W:
    case LoongArch::XVPICKOD_B:
    case LoongArch::XVPICKOD_D:
    case LoongArch::XVPICKOD_H:
    case LoongArch::XVPICKOD_W:
    case LoongArch::XVROTR_B:
    case LoongArch::XVROTR_D:
    case LoongArch::XVROTR_H:
    case LoongArch::XVROTR_W:
    case LoongArch::XVSADD_B:
    case LoongArch::XVSADD_BU:
    case LoongArch::XVSADD_D:
    case LoongArch::XVSADD_DU:
    case LoongArch::XVSADD_H:
    case LoongArch::XVSADD_HU:
    case LoongArch::XVSADD_W:
    case LoongArch::XVSADD_WU:
    case LoongArch::XVSEQ_B:
    case LoongArch::XVSEQ_D:
    case LoongArch::XVSEQ_H:
    case LoongArch::XVSEQ_W:
    case LoongArch::XVSIGNCOV_B:
    case LoongArch::XVSIGNCOV_D:
    case LoongArch::XVSIGNCOV_H:
    case LoongArch::XVSIGNCOV_W:
    case LoongArch::XVSLE_B:
    case LoongArch::XVSLE_BU:
    case LoongArch::XVSLE_D:
    case LoongArch::XVSLE_DU:
    case LoongArch::XVSLE_H:
    case LoongArch::XVSLE_HU:
    case LoongArch::XVSLE_W:
    case LoongArch::XVSLE_WU:
    case LoongArch::XVSLL_B:
    case LoongArch::XVSLL_D:
    case LoongArch::XVSLL_H:
    case LoongArch::XVSLL_W:
    case LoongArch::XVSLT_B:
    case LoongArch::XVSLT_BU:
    case LoongArch::XVSLT_D:
    case LoongArch::XVSLT_DU:
    case LoongArch::XVSLT_H:
    case LoongArch::XVSLT_HU:
    case LoongArch::XVSLT_W:
    case LoongArch::XVSLT_WU:
    case LoongArch::XVSRAN_B_H:
    case LoongArch::XVSRAN_H_W:
    case LoongArch::XVSRAN_W_D:
    case LoongArch::XVSRARN_B_H:
    case LoongArch::XVSRARN_H_W:
    case LoongArch::XVSRARN_W_D:
    case LoongArch::XVSRAR_B:
    case LoongArch::XVSRAR_D:
    case LoongArch::XVSRAR_H:
    case LoongArch::XVSRAR_W:
    case LoongArch::XVSRA_B:
    case LoongArch::XVSRA_D:
    case LoongArch::XVSRA_H:
    case LoongArch::XVSRA_W:
    case LoongArch::XVSRLN_B_H:
    case LoongArch::XVSRLN_H_W:
    case LoongArch::XVSRLN_W_D:
    case LoongArch::XVSRLRN_B_H:
    case LoongArch::XVSRLRN_H_W:
    case LoongArch::XVSRLRN_W_D:
    case LoongArch::XVSRLR_B:
    case LoongArch::XVSRLR_D:
    case LoongArch::XVSRLR_H:
    case LoongArch::XVSRLR_W:
    case LoongArch::XVSRL_B:
    case LoongArch::XVSRL_D:
    case LoongArch::XVSRL_H:
    case LoongArch::XVSRL_W:
    case LoongArch::XVSSRAN_BU_H:
    case LoongArch::XVSSRAN_B_H:
    case LoongArch::XVSSRAN_HU_W:
    case LoongArch::XVSSRAN_H_W:
    case LoongArch::XVSSRAN_WU_D:
    case LoongArch::XVSSRAN_W_D:
    case LoongArch::XVSSRARN_BU_H:
    case LoongArch::XVSSRARN_B_H:
    case LoongArch::XVSSRARN_HU_W:
    case LoongArch::XVSSRARN_H_W:
    case LoongArch::XVSSRARN_WU_D:
    case LoongArch::XVSSRARN_W_D:
    case LoongArch::XVSSRLN_BU_H:
    case LoongArch::XVSSRLN_B_H:
    case LoongArch::XVSSRLN_HU_W:
    case LoongArch::XVSSRLN_H_W:
    case LoongArch::XVSSRLN_WU_D:
    case LoongArch::XVSSRLN_W_D:
    case LoongArch::XVSSRLRN_BU_H:
    case LoongArch::XVSSRLRN_B_H:
    case LoongArch::XVSSRLRN_HU_W:
    case LoongArch::XVSSRLRN_H_W:
    case LoongArch::XVSSRLRN_WU_D:
    case LoongArch::XVSSRLRN_W_D:
    case LoongArch::XVSSUB_B:
    case LoongArch::XVSSUB_BU:
    case LoongArch::XVSSUB_D:
    case LoongArch::XVSSUB_DU:
    case LoongArch::XVSSUB_H:
    case LoongArch::XVSSUB_HU:
    case LoongArch::XVSSUB_W:
    case LoongArch::XVSSUB_WU:
    case LoongArch::XVSUBWEV_D_W:
    case LoongArch::XVSUBWEV_D_WU:
    case LoongArch::XVSUBWEV_H_B:
    case LoongArch::XVSUBWEV_H_BU:
    case LoongArch::XVSUBWEV_Q_D:
    case LoongArch::XVSUBWEV_Q_DU:
    case LoongArch::XVSUBWEV_W_H:
    case LoongArch::XVSUBWEV_W_HU:
    case LoongArch::XVSUBWOD_D_W:
    case LoongArch::XVSUBWOD_D_WU:
    case LoongArch::XVSUBWOD_H_B:
    case LoongArch::XVSUBWOD_H_BU:
    case LoongArch::XVSUBWOD_Q_D:
    case LoongArch::XVSUBWOD_Q_DU:
    case LoongArch::XVSUBWOD_W_H:
    case LoongArch::XVSUBWOD_W_HU:
    case LoongArch::XVSUB_B:
    case LoongArch::XVSUB_D:
    case LoongArch::XVSUB_H:
    case LoongArch::XVSUB_Q:
    case LoongArch::XVSUB_W:
    case LoongArch::XVXOR_V: {
      // op: xk
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case LoongArch::XVFRSTP_B:
    case LoongArch::XVFRSTP_H:
    case LoongArch::XVMADDWEV_D_W:
    case LoongArch::XVMADDWEV_D_WU:
    case LoongArch::XVMADDWEV_D_WU_W:
    case LoongArch::XVMADDWEV_H_B:
    case LoongArch::XVMADDWEV_H_BU:
    case LoongArch::XVMADDWEV_H_BU_B:
    case LoongArch::XVMADDWEV_Q_D:
    case LoongArch::XVMADDWEV_Q_DU:
    case LoongArch::XVMADDWEV_Q_DU_D:
    case LoongArch::XVMADDWEV_W_H:
    case LoongArch::XVMADDWEV_W_HU:
    case LoongArch::XVMADDWEV_W_HU_H:
    case LoongArch::XVMADDWOD_D_W:
    case LoongArch::XVMADDWOD_D_WU:
    case LoongArch::XVMADDWOD_D_WU_W:
    case LoongArch::XVMADDWOD_H_B:
    case LoongArch::XVMADDWOD_H_BU:
    case LoongArch::XVMADDWOD_H_BU_B:
    case LoongArch::XVMADDWOD_Q_D:
    case LoongArch::XVMADDWOD_Q_DU:
    case LoongArch::XVMADDWOD_Q_DU_D:
    case LoongArch::XVMADDWOD_W_H:
    case LoongArch::XVMADDWOD_W_HU:
    case LoongArch::XVMADDWOD_W_HU_H:
    case LoongArch::XVMADD_B:
    case LoongArch::XVMADD_D:
    case LoongArch::XVMADD_H:
    case LoongArch::XVMADD_W:
    case LoongArch::XVMSUB_B:
    case LoongArch::XVMSUB_D:
    case LoongArch::XVMSUB_H:
    case LoongArch::XVMSUB_W:
    case LoongArch::XVSHUF_D:
    case LoongArch::XVSHUF_H:
    case LoongArch::XVSHUF_W: {
      // op: xk
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: xj
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: xd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
  default:
    reportUnsupportedInst(MI);
  }
  return Value;
}

#ifdef GET_OPERAND_BIT_OFFSET
#undef GET_OPERAND_BIT_OFFSET

uint32_t LoongArchMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
    unsigned OpNum,
    const MCSubtargetInfo &STI) const {
  switch (MI.getOpcode()) {
    case LoongArch::ERTN:
    case LoongArch::GTLBFLUSH:
    case LoongArch::TLBCLR:
    case LoongArch::TLBFILL:
    case LoongArch::TLBFLUSH:
    case LoongArch::TLBRD:
    case LoongArch::TLBSRCH:
    case LoongArch::TLBWR:
    case LoongArch::X86CLRTM:
    case LoongArch::X86DECTOP:
    case LoongArch::X86INCTOP:
    case LoongArch::X86SETTM: {
      break;
    }
    case LoongArch::SET_CFR_FALSE:
    case LoongArch::SET_CFR_TRUE: {
      switch (OpNum) {
      case 0:
        // op: cd
        return 0;
      }
      break;
    }
    case LoongArch::BREAK:
    case LoongArch::DBAR:
    case LoongArch::DBCL:
    case LoongArch::HVCL:
    case LoongArch::IBAR:
    case LoongArch::IDLE:
    case LoongArch::SYSCALL: {
      switch (OpNum) {
      case 0:
        // op: imm15
        return 0;
      }
      break;
    }
    case LoongArch::JISCR0:
    case LoongArch::JISCR1: {
      switch (OpNum) {
      case 0:
        // op: imm21
        return 0;
      }
      break;
    }
    case LoongArch::B:
    case LoongArch::BL: {
      switch (OpNum) {
      case 0:
        // op: imm26
        return 0;
      }
      break;
    }
    case LoongArch::UD: {
      switch (OpNum) {
      case 0:
        // op: imm5
        return 0;
      }
      break;
    }
    case LoongArch::X86MTTOP: {
      switch (OpNum) {
      case 0:
        // op: ptr
        return 5;
      }
      break;
    }
    case LoongArch::X86MFTOP: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::X86DEC_B:
    case LoongArch::X86DEC_D:
    case LoongArch::X86DEC_H:
    case LoongArch::X86DEC_W:
    case LoongArch::X86INC_B:
    case LoongArch::X86INC_D:
    case LoongArch::X86INC_H:
    case LoongArch::X86INC_W: {
      switch (OpNum) {
      case 0:
        // op: rj
        return 5;
      }
      break;
    }
    case LoongArch::INVTLB: {
      switch (OpNum) {
      case 0:
        // op: rk
        return 10;
      case 1:
        // op: rj
        return 5;
      case 2:
        // op: op
        return 0;
      }
      break;
    }
    case LoongArch::CSRRD:
    case LoongArch::GCSRRD: {
      switch (OpNum) {
      case 1:
        // op: csr_num
        return 10;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::FABS_D:
    case LoongArch::FABS_S:
    case LoongArch::FCLASS_D:
    case LoongArch::FCLASS_S:
    case LoongArch::FCVT_D_S:
    case LoongArch::FCVT_LD_D:
    case LoongArch::FCVT_S_D:
    case LoongArch::FCVT_UD_D:
    case LoongArch::FFINT_D_L:
    case LoongArch::FFINT_D_W:
    case LoongArch::FFINT_S_L:
    case LoongArch::FFINT_S_W:
    case LoongArch::FLOGB_D:
    case LoongArch::FLOGB_S:
    case LoongArch::FNEG_D:
    case LoongArch::FNEG_S:
    case LoongArch::FRECIPE_D:
    case LoongArch::FRECIPE_S:
    case LoongArch::FRECIP_D:
    case LoongArch::FRECIP_S:
    case LoongArch::FRINT_D:
    case LoongArch::FRINT_S:
    case LoongArch::FRSQRTE_D:
    case LoongArch::FRSQRTE_S:
    case LoongArch::FRSQRT_D:
    case LoongArch::FRSQRT_S:
    case LoongArch::FSQRT_D:
    case LoongArch::FSQRT_S:
    case LoongArch::FTINTRM_L_D:
    case LoongArch::FTINTRM_L_S:
    case LoongArch::FTINTRM_W_D:
    case LoongArch::FTINTRM_W_S:
    case LoongArch::FTINTRNE_L_D:
    case LoongArch::FTINTRNE_L_S:
    case LoongArch::FTINTRNE_W_D:
    case LoongArch::FTINTRNE_W_S:
    case LoongArch::FTINTRP_L_D:
    case LoongArch::FTINTRP_L_S:
    case LoongArch::FTINTRP_W_D:
    case LoongArch::FTINTRP_W_S:
    case LoongArch::FTINTRZ_L_D:
    case LoongArch::FTINTRZ_L_S:
    case LoongArch::FTINTRZ_W_D:
    case LoongArch::FTINTRZ_W_S:
    case LoongArch::FTINT_L_D:
    case LoongArch::FTINT_L_S:
    case LoongArch::FTINT_W_D:
    case LoongArch::FTINT_W_S: {
      switch (OpNum) {
      case 1:
        // op: fj
        return 5;
      case 0:
        // op: fd
        return 0;
      }
      break;
    }
    case LoongArch::VLDI: {
      switch (OpNum) {
      case 1:
        // op: imm13
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVLDI: {
      switch (OpNum) {
      case 1:
        // op: imm13
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::LU12I_W:
    case LoongArch::PCADDI:
    case LoongArch::PCADDU12I:
    case LoongArch::PCADDU18I:
    case LoongArch::PCALAU12I: {
      switch (OpNum) {
      case 1:
        // op: imm20
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::BCEQZ:
    case LoongArch::BCNEZ: {
      switch (OpNum) {
      case 1:
        // op: imm21
        return 0;
      case 0:
        // op: cj
        return 5;
      }
      break;
    }
    case LoongArch::BEQZ:
    case LoongArch::BNEZ: {
      switch (OpNum) {
      case 1:
        // op: imm21
        return 0;
      case 0:
        // op: rj
        return 5;
      }
      break;
    }
    case LoongArch::X86RCLI_B:
    case LoongArch::X86RCRI_B:
    case LoongArch::X86ROTLI_B:
    case LoongArch::X86ROTRI_B:
    case LoongArch::X86SLLI_B:
    case LoongArch::X86SRAI_B:
    case LoongArch::X86SRLI_B: {
      switch (OpNum) {
      case 1:
        // op: imm3
        return 10;
      case 0:
        // op: rj
        return 5;
      }
      break;
    }
    case LoongArch::SETARMJ:
    case LoongArch::SETX86J: {
      switch (OpNum) {
      case 1:
        // op: imm4
        return 10;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::ARMMOV_D:
    case LoongArch::ARMMOV_W:
    case LoongArch::ARMNOT_W:
    case LoongArch::ARMRRX_W:
    case LoongArch::X86RCLI_H:
    case LoongArch::X86RCRI_H:
    case LoongArch::X86ROTLI_H:
    case LoongArch::X86ROTRI_H:
    case LoongArch::X86SLLI_H:
    case LoongArch::X86SRAI_H:
    case LoongArch::X86SRLI_H: {
      switch (OpNum) {
      case 1:
        // op: imm4
        return 10;
      case 0:
        // op: rj
        return 5;
      }
      break;
    }
    case LoongArch::ARMROTRI_W:
    case LoongArch::ARMSLLI_W:
    case LoongArch::ARMSRAI_W:
    case LoongArch::ARMSRLI_W: {
      switch (OpNum) {
      case 1:
        // op: imm5
        return 10;
      case 0:
        // op: rj
        return 5;
      case 2:
        // op: imm4
        return 0;
      }
      break;
    }
    case LoongArch::X86RCLI_W:
    case LoongArch::X86RCRI_W:
    case LoongArch::X86ROTLI_W:
    case LoongArch::X86ROTRI_W:
    case LoongArch::X86SLLI_W:
    case LoongArch::X86SRAI_W:
    case LoongArch::X86SRLI_W: {
      switch (OpNum) {
      case 1:
        // op: imm5
        return 10;
      case 0:
        // op: rj
        return 5;
      }
      break;
    }
    case LoongArch::X86RCLI_D:
    case LoongArch::X86RCRI_D:
    case LoongArch::X86ROTLI_D:
    case LoongArch::X86ROTRI_D:
    case LoongArch::X86SLLI_D:
    case LoongArch::X86SRAI_D:
    case LoongArch::X86SRLI_D: {
      switch (OpNum) {
      case 1:
        // op: imm6
        return 10;
      case 0:
        // op: rj
        return 5;
      }
      break;
    }
    case LoongArch::ARMMFFLAG:
    case LoongArch::ARMMTFLAG:
    case LoongArch::X86MFFLAG:
    case LoongArch::X86MTFLAG: {
      switch (OpNum) {
      case 1:
        // op: imm8
        return 10;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::BITREV_4B:
    case LoongArch::BITREV_8B:
    case LoongArch::BITREV_D:
    case LoongArch::BITREV_W:
    case LoongArch::CLO_D:
    case LoongArch::CLO_W:
    case LoongArch::CLZ_D:
    case LoongArch::CLZ_W:
    case LoongArch::CPUCFG:
    case LoongArch::CTO_D:
    case LoongArch::CTO_W:
    case LoongArch::CTZ_D:
    case LoongArch::CTZ_W:
    case LoongArch::EXT_W_B:
    case LoongArch::EXT_W_H:
    case LoongArch::IOCSRRD_B:
    case LoongArch::IOCSRRD_D:
    case LoongArch::IOCSRRD_H:
    case LoongArch::IOCSRRD_W:
    case LoongArch::IOCSRWR_B:
    case LoongArch::IOCSRWR_D:
    case LoongArch::IOCSRWR_H:
    case LoongArch::IOCSRWR_W:
    case LoongArch::LLACQ_D:
    case LoongArch::LLACQ_W:
    case LoongArch::RDTIMEH_W:
    case LoongArch::RDTIMEL_W:
    case LoongArch::RDTIME_D:
    case LoongArch::REVB_2H:
    case LoongArch::REVB_2W:
    case LoongArch::REVB_4H:
    case LoongArch::REVB_D:
    case LoongArch::REVH_2W:
    case LoongArch::REVH_D:
    case LoongArch::SETX86LOOPE:
    case LoongArch::SETX86LOOPNE: {
      switch (OpNum) {
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::MOVGR2SCR: {
      switch (OpNum) {
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: sd
        return 0;
      }
      break;
    }
    case LoongArch::VREPLGR2VR_B:
    case LoongArch::VREPLGR2VR_D:
    case LoongArch::VREPLGR2VR_H:
    case LoongArch::VREPLGR2VR_W: {
      switch (OpNum) {
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVREPLGR2VR_B:
    case LoongArch::XVREPLGR2VR_D:
    case LoongArch::XVREPLGR2VR_H:
    case LoongArch::XVREPLGR2VR_W: {
      switch (OpNum) {
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::ASRTGT_D:
    case LoongArch::ASRTLE_D:
    case LoongArch::X86ADC_B:
    case LoongArch::X86ADC_D:
    case LoongArch::X86ADC_H:
    case LoongArch::X86ADC_W:
    case LoongArch::X86ADD_B:
    case LoongArch::X86ADD_D:
    case LoongArch::X86ADD_DU:
    case LoongArch::X86ADD_H:
    case LoongArch::X86ADD_W:
    case LoongArch::X86ADD_WU:
    case LoongArch::X86AND_B:
    case LoongArch::X86AND_D:
    case LoongArch::X86AND_H:
    case LoongArch::X86AND_W:
    case LoongArch::X86MUL_B:
    case LoongArch::X86MUL_BU:
    case LoongArch::X86MUL_D:
    case LoongArch::X86MUL_DU:
    case LoongArch::X86MUL_H:
    case LoongArch::X86MUL_HU:
    case LoongArch::X86MUL_W:
    case LoongArch::X86MUL_WU:
    case LoongArch::X86OR_B:
    case LoongArch::X86OR_D:
    case LoongArch::X86OR_H:
    case LoongArch::X86OR_W:
    case LoongArch::X86RCL_B:
    case LoongArch::X86RCL_D:
    case LoongArch::X86RCL_H:
    case LoongArch::X86RCL_W:
    case LoongArch::X86RCR_B:
    case LoongArch::X86RCR_D:
    case LoongArch::X86RCR_H:
    case LoongArch::X86RCR_W:
    case LoongArch::X86ROTL_B:
    case LoongArch::X86ROTL_D:
    case LoongArch::X86ROTL_H:
    case LoongArch::X86ROTL_W:
    case LoongArch::X86ROTR_B:
    case LoongArch::X86ROTR_D:
    case LoongArch::X86ROTR_H:
    case LoongArch::X86ROTR_W:
    case LoongArch::X86SBC_B:
    case LoongArch::X86SBC_D:
    case LoongArch::X86SBC_H:
    case LoongArch::X86SBC_W:
    case LoongArch::X86SLL_B:
    case LoongArch::X86SLL_D:
    case LoongArch::X86SLL_H:
    case LoongArch::X86SLL_W:
    case LoongArch::X86SRA_B:
    case LoongArch::X86SRA_D:
    case LoongArch::X86SRA_H:
    case LoongArch::X86SRA_W:
    case LoongArch::X86SRL_B:
    case LoongArch::X86SRL_D:
    case LoongArch::X86SRL_H:
    case LoongArch::X86SRL_W:
    case LoongArch::X86SUB_B:
    case LoongArch::X86SUB_D:
    case LoongArch::X86SUB_DU:
    case LoongArch::X86SUB_H:
    case LoongArch::X86SUB_W:
    case LoongArch::X86SUB_WU:
    case LoongArch::X86XOR_B:
    case LoongArch::X86XOR_D:
    case LoongArch::X86XOR_H:
    case LoongArch::X86XOR_W: {
      switch (OpNum) {
      case 1:
        // op: rk
        return 10;
      case 0:
        // op: rj
        return 5;
      }
      break;
    }
    case LoongArch::AMADD_B:
    case LoongArch::AMADD_D:
    case LoongArch::AMADD_H:
    case LoongArch::AMADD_W:
    case LoongArch::AMADD__DB_B:
    case LoongArch::AMADD__DB_D:
    case LoongArch::AMADD__DB_H:
    case LoongArch::AMADD__DB_W:
    case LoongArch::AMAND_D:
    case LoongArch::AMAND_W:
    case LoongArch::AMAND__DB_D:
    case LoongArch::AMAND__DB_W:
    case LoongArch::AMMAX_D:
    case LoongArch::AMMAX_DU:
    case LoongArch::AMMAX_W:
    case LoongArch::AMMAX_WU:
    case LoongArch::AMMAX__DB_D:
    case LoongArch::AMMAX__DB_DU:
    case LoongArch::AMMAX__DB_W:
    case LoongArch::AMMAX__DB_WU:
    case LoongArch::AMMIN_D:
    case LoongArch::AMMIN_DU:
    case LoongArch::AMMIN_W:
    case LoongArch::AMMIN_WU:
    case LoongArch::AMMIN__DB_D:
    case LoongArch::AMMIN__DB_DU:
    case LoongArch::AMMIN__DB_W:
    case LoongArch::AMMIN__DB_WU:
    case LoongArch::AMOR_D:
    case LoongArch::AMOR_W:
    case LoongArch::AMOR__DB_D:
    case LoongArch::AMOR__DB_W:
    case LoongArch::AMSWAP_B:
    case LoongArch::AMSWAP_D:
    case LoongArch::AMSWAP_H:
    case LoongArch::AMSWAP_W:
    case LoongArch::AMSWAP__DB_B:
    case LoongArch::AMSWAP__DB_D:
    case LoongArch::AMSWAP__DB_H:
    case LoongArch::AMSWAP__DB_W:
    case LoongArch::AMXOR_D:
    case LoongArch::AMXOR_W:
    case LoongArch::AMXOR__DB_D:
    case LoongArch::AMXOR__DB_W: {
      switch (OpNum) {
      case 1:
        // op: rk
        return 10;
      case 2:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::LDPTE: {
      switch (OpNum) {
      case 1:
        // op: seq
        return 10;
      case 0:
        // op: rj
        return 5;
      }
      break;
    }
    case LoongArch::MOVSCR2GR: {
      switch (OpNum) {
      case 1:
        // op: sj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::FMOV_D:
    case LoongArch::FMOV_S:
    case LoongArch::MOVCF2FR_xS:
    case LoongArch::MOVCF2GR:
    case LoongArch::MOVFCSR2GR:
    case LoongArch::MOVFR2CF_xS:
    case LoongArch::MOVFR2GR_D:
    case LoongArch::MOVFR2GR_S:
    case LoongArch::MOVFR2GR_S_64:
    case LoongArch::MOVFRH2GR_S:
    case LoongArch::MOVGR2CF:
    case LoongArch::MOVGR2FCSR:
    case LoongArch::MOVGR2FR_D:
    case LoongArch::MOVGR2FR_W:
    case LoongArch::MOVGR2FR_W_64: {
      switch (OpNum) {
      case 1:
        // op: src
        return 5;
      case 0:
        // op: dst
        return 0;
      }
      break;
    }
    case LoongArch::VSETALLNEZ_B:
    case LoongArch::VSETALLNEZ_D:
    case LoongArch::VSETALLNEZ_H:
    case LoongArch::VSETALLNEZ_W:
    case LoongArch::VSETANYEQZ_B:
    case LoongArch::VSETANYEQZ_D:
    case LoongArch::VSETANYEQZ_H:
    case LoongArch::VSETANYEQZ_W:
    case LoongArch::VSETEQZ_V:
    case LoongArch::VSETNEZ_V: {
      switch (OpNum) {
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: cd
        return 0;
      }
      break;
    }
    case LoongArch::VCLO_B:
    case LoongArch::VCLO_D:
    case LoongArch::VCLO_H:
    case LoongArch::VCLO_W:
    case LoongArch::VCLZ_B:
    case LoongArch::VCLZ_D:
    case LoongArch::VCLZ_H:
    case LoongArch::VCLZ_W:
    case LoongArch::VEXTH_DU_WU:
    case LoongArch::VEXTH_D_W:
    case LoongArch::VEXTH_HU_BU:
    case LoongArch::VEXTH_H_B:
    case LoongArch::VEXTH_QU_DU:
    case LoongArch::VEXTH_Q_D:
    case LoongArch::VEXTH_WU_HU:
    case LoongArch::VEXTH_W_H:
    case LoongArch::VEXTL_QU_DU:
    case LoongArch::VEXTL_Q_D:
    case LoongArch::VFCLASS_D:
    case LoongArch::VFCLASS_S:
    case LoongArch::VFCVTH_D_S:
    case LoongArch::VFCVTH_S_H:
    case LoongArch::VFCVTL_D_S:
    case LoongArch::VFCVTL_S_H:
    case LoongArch::VFFINTH_D_W:
    case LoongArch::VFFINTL_D_W:
    case LoongArch::VFFINT_D_L:
    case LoongArch::VFFINT_D_LU:
    case LoongArch::VFFINT_S_W:
    case LoongArch::VFFINT_S_WU:
    case LoongArch::VFLOGB_D:
    case LoongArch::VFLOGB_S:
    case LoongArch::VFRECIPE_D:
    case LoongArch::VFRECIPE_S:
    case LoongArch::VFRECIP_D:
    case LoongArch::VFRECIP_S:
    case LoongArch::VFRINTRM_D:
    case LoongArch::VFRINTRM_S:
    case LoongArch::VFRINTRNE_D:
    case LoongArch::VFRINTRNE_S:
    case LoongArch::VFRINTRP_D:
    case LoongArch::VFRINTRP_S:
    case LoongArch::VFRINTRZ_D:
    case LoongArch::VFRINTRZ_S:
    case LoongArch::VFRINT_D:
    case LoongArch::VFRINT_S:
    case LoongArch::VFRSQRTE_D:
    case LoongArch::VFRSQRTE_S:
    case LoongArch::VFRSQRT_D:
    case LoongArch::VFRSQRT_S:
    case LoongArch::VFSQRT_D:
    case LoongArch::VFSQRT_S:
    case LoongArch::VFTINTH_L_S:
    case LoongArch::VFTINTL_L_S:
    case LoongArch::VFTINTRMH_L_S:
    case LoongArch::VFTINTRML_L_S:
    case LoongArch::VFTINTRM_L_D:
    case LoongArch::VFTINTRM_W_S:
    case LoongArch::VFTINTRNEH_L_S:
    case LoongArch::VFTINTRNEL_L_S:
    case LoongArch::VFTINTRNE_L_D:
    case LoongArch::VFTINTRNE_W_S:
    case LoongArch::VFTINTRPH_L_S:
    case LoongArch::VFTINTRPL_L_S:
    case LoongArch::VFTINTRP_L_D:
    case LoongArch::VFTINTRP_W_S:
    case LoongArch::VFTINTRZH_L_S:
    case LoongArch::VFTINTRZL_L_S:
    case LoongArch::VFTINTRZ_LU_D:
    case LoongArch::VFTINTRZ_L_D:
    case LoongArch::VFTINTRZ_WU_S:
    case LoongArch::VFTINTRZ_W_S:
    case LoongArch::VFTINT_LU_D:
    case LoongArch::VFTINT_L_D:
    case LoongArch::VFTINT_WU_S:
    case LoongArch::VFTINT_W_S:
    case LoongArch::VMSKGEZ_B:
    case LoongArch::VMSKLTZ_B:
    case LoongArch::VMSKLTZ_D:
    case LoongArch::VMSKLTZ_H:
    case LoongArch::VMSKLTZ_W:
    case LoongArch::VMSKNZ_B:
    case LoongArch::VNEG_B:
    case LoongArch::VNEG_D:
    case LoongArch::VNEG_H:
    case LoongArch::VNEG_W:
    case LoongArch::VPCNT_B:
    case LoongArch::VPCNT_D:
    case LoongArch::VPCNT_H:
    case LoongArch::VPCNT_W: {
      switch (OpNum) {
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVSETALLNEZ_B:
    case LoongArch::XVSETALLNEZ_D:
    case LoongArch::XVSETALLNEZ_H:
    case LoongArch::XVSETALLNEZ_W:
    case LoongArch::XVSETANYEQZ_B:
    case LoongArch::XVSETANYEQZ_D:
    case LoongArch::XVSETANYEQZ_H:
    case LoongArch::XVSETANYEQZ_W:
    case LoongArch::XVSETEQZ_V:
    case LoongArch::XVSETNEZ_V: {
      switch (OpNum) {
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: cd
        return 0;
      }
      break;
    }
    case LoongArch::VEXT2XV_DU_BU:
    case LoongArch::VEXT2XV_DU_HU:
    case LoongArch::VEXT2XV_DU_WU:
    case LoongArch::VEXT2XV_D_B:
    case LoongArch::VEXT2XV_D_H:
    case LoongArch::VEXT2XV_D_W:
    case LoongArch::VEXT2XV_HU_BU:
    case LoongArch::VEXT2XV_H_B:
    case LoongArch::VEXT2XV_WU_BU:
    case LoongArch::VEXT2XV_WU_HU:
    case LoongArch::VEXT2XV_W_B:
    case LoongArch::VEXT2XV_W_H:
    case LoongArch::XVCLO_B:
    case LoongArch::XVCLO_D:
    case LoongArch::XVCLO_H:
    case LoongArch::XVCLO_W:
    case LoongArch::XVCLZ_B:
    case LoongArch::XVCLZ_D:
    case LoongArch::XVCLZ_H:
    case LoongArch::XVCLZ_W:
    case LoongArch::XVEXTH_DU_WU:
    case LoongArch::XVEXTH_D_W:
    case LoongArch::XVEXTH_HU_BU:
    case LoongArch::XVEXTH_H_B:
    case LoongArch::XVEXTH_QU_DU:
    case LoongArch::XVEXTH_Q_D:
    case LoongArch::XVEXTH_WU_HU:
    case LoongArch::XVEXTH_W_H:
    case LoongArch::XVEXTL_QU_DU:
    case LoongArch::XVEXTL_Q_D:
    case LoongArch::XVFCLASS_D:
    case LoongArch::XVFCLASS_S:
    case LoongArch::XVFCVTH_D_S:
    case LoongArch::XVFCVTH_S_H:
    case LoongArch::XVFCVTL_D_S:
    case LoongArch::XVFCVTL_S_H:
    case LoongArch::XVFFINTH_D_W:
    case LoongArch::XVFFINTL_D_W:
    case LoongArch::XVFFINT_D_L:
    case LoongArch::XVFFINT_D_LU:
    case LoongArch::XVFFINT_S_W:
    case LoongArch::XVFFINT_S_WU:
    case LoongArch::XVFLOGB_D:
    case LoongArch::XVFLOGB_S:
    case LoongArch::XVFRECIPE_D:
    case LoongArch::XVFRECIPE_S:
    case LoongArch::XVFRECIP_D:
    case LoongArch::XVFRECIP_S:
    case LoongArch::XVFRINTRM_D:
    case LoongArch::XVFRINTRM_S:
    case LoongArch::XVFRINTRNE_D:
    case LoongArch::XVFRINTRNE_S:
    case LoongArch::XVFRINTRP_D:
    case LoongArch::XVFRINTRP_S:
    case LoongArch::XVFRINTRZ_D:
    case LoongArch::XVFRINTRZ_S:
    case LoongArch::XVFRINT_D:
    case LoongArch::XVFRINT_S:
    case LoongArch::XVFRSQRTE_D:
    case LoongArch::XVFRSQRTE_S:
    case LoongArch::XVFRSQRT_D:
    case LoongArch::XVFRSQRT_S:
    case LoongArch::XVFSQRT_D:
    case LoongArch::XVFSQRT_S:
    case LoongArch::XVFTINTH_L_S:
    case LoongArch::XVFTINTL_L_S:
    case LoongArch::XVFTINTRMH_L_S:
    case LoongArch::XVFTINTRML_L_S:
    case LoongArch::XVFTINTRM_L_D:
    case LoongArch::XVFTINTRM_W_S:
    case LoongArch::XVFTINTRNEH_L_S:
    case LoongArch::XVFTINTRNEL_L_S:
    case LoongArch::XVFTINTRNE_L_D:
    case LoongArch::XVFTINTRNE_W_S:
    case LoongArch::XVFTINTRPH_L_S:
    case LoongArch::XVFTINTRPL_L_S:
    case LoongArch::XVFTINTRP_L_D:
    case LoongArch::XVFTINTRP_W_S:
    case LoongArch::XVFTINTRZH_L_S:
    case LoongArch::XVFTINTRZL_L_S:
    case LoongArch::XVFTINTRZ_LU_D:
    case LoongArch::XVFTINTRZ_L_D:
    case LoongArch::XVFTINTRZ_WU_S:
    case LoongArch::XVFTINTRZ_W_S:
    case LoongArch::XVFTINT_LU_D:
    case LoongArch::XVFTINT_L_D:
    case LoongArch::XVFTINT_WU_S:
    case LoongArch::XVFTINT_W_S:
    case LoongArch::XVMSKGEZ_B:
    case LoongArch::XVMSKLTZ_B:
    case LoongArch::XVMSKLTZ_D:
    case LoongArch::XVMSKLTZ_H:
    case LoongArch::XVMSKLTZ_W:
    case LoongArch::XVMSKNZ_B:
    case LoongArch::XVNEG_B:
    case LoongArch::XVNEG_D:
    case LoongArch::XVNEG_H:
    case LoongArch::XVNEG_W:
    case LoongArch::XVPCNT_B:
    case LoongArch::XVPCNT_D:
    case LoongArch::XVPCNT_H:
    case LoongArch::XVPCNT_W:
    case LoongArch::XVREPLVE0_B:
    case LoongArch::XVREPLVE0_D:
    case LoongArch::XVREPLVE0_H:
    case LoongArch::XVREPLVE0_Q:
    case LoongArch::XVREPLVE0_W: {
      switch (OpNum) {
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::CSRWR:
    case LoongArch::GCSRWR: {
      switch (OpNum) {
      case 2:
        // op: csr_num
        return 10;
      case 1:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::FCMP_CAF_D:
    case LoongArch::FCMP_CAF_S:
    case LoongArch::FCMP_CEQ_D:
    case LoongArch::FCMP_CEQ_S:
    case LoongArch::FCMP_CLE_D:
    case LoongArch::FCMP_CLE_S:
    case LoongArch::FCMP_CLT_D:
    case LoongArch::FCMP_CLT_S:
    case LoongArch::FCMP_CNE_D:
    case LoongArch::FCMP_CNE_S:
    case LoongArch::FCMP_COR_D:
    case LoongArch::FCMP_COR_S:
    case LoongArch::FCMP_CUEQ_D:
    case LoongArch::FCMP_CUEQ_S:
    case LoongArch::FCMP_CULE_D:
    case LoongArch::FCMP_CULE_S:
    case LoongArch::FCMP_CULT_D:
    case LoongArch::FCMP_CULT_S:
    case LoongArch::FCMP_CUNE_D:
    case LoongArch::FCMP_CUNE_S:
    case LoongArch::FCMP_CUN_D:
    case LoongArch::FCMP_CUN_S:
    case LoongArch::FCMP_SAF_D:
    case LoongArch::FCMP_SAF_S:
    case LoongArch::FCMP_SEQ_D:
    case LoongArch::FCMP_SEQ_S:
    case LoongArch::FCMP_SLE_D:
    case LoongArch::FCMP_SLE_S:
    case LoongArch::FCMP_SLT_D:
    case LoongArch::FCMP_SLT_S:
    case LoongArch::FCMP_SNE_D:
    case LoongArch::FCMP_SNE_S:
    case LoongArch::FCMP_SOR_D:
    case LoongArch::FCMP_SOR_S:
    case LoongArch::FCMP_SUEQ_D:
    case LoongArch::FCMP_SUEQ_S:
    case LoongArch::FCMP_SULE_D:
    case LoongArch::FCMP_SULE_S:
    case LoongArch::FCMP_SULT_D:
    case LoongArch::FCMP_SULT_S:
    case LoongArch::FCMP_SUNE_D:
    case LoongArch::FCMP_SUNE_S:
    case LoongArch::FCMP_SUN_D:
    case LoongArch::FCMP_SUN_S: {
      switch (OpNum) {
      case 2:
        // op: fk
        return 10;
      case 1:
        // op: fj
        return 5;
      case 0:
        // op: cd
        return 0;
      }
      break;
    }
    case LoongArch::FADD_D:
    case LoongArch::FADD_S:
    case LoongArch::FCOPYSIGN_D:
    case LoongArch::FCOPYSIGN_S:
    case LoongArch::FCVT_D_LD:
    case LoongArch::FDIV_D:
    case LoongArch::FDIV_S:
    case LoongArch::FMAXA_D:
    case LoongArch::FMAXA_S:
    case LoongArch::FMAX_D:
    case LoongArch::FMAX_S:
    case LoongArch::FMINA_D:
    case LoongArch::FMINA_S:
    case LoongArch::FMIN_D:
    case LoongArch::FMIN_S:
    case LoongArch::FMUL_D:
    case LoongArch::FMUL_S:
    case LoongArch::FSCALEB_D:
    case LoongArch::FSCALEB_S:
    case LoongArch::FSUB_D:
    case LoongArch::FSUB_S: {
      switch (OpNum) {
      case 2:
        // op: fk
        return 10;
      case 1:
        // op: fj
        return 5;
      case 0:
        // op: fd
        return 0;
      }
      break;
    }
    case LoongArch::VPICKVE2GR_D:
    case LoongArch::VPICKVE2GR_DU: {
      switch (OpNum) {
      case 2:
        // op: imm1
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VREPLVEI_D: {
      switch (OpNum) {
      case 2:
        // op: imm1
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVREPL128VEI_D: {
      switch (OpNum) {
      case 2:
        // op: imm1
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VLDREPL_W: {
      switch (OpNum) {
      case 2:
        // op: imm10
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVLDREPL_W: {
      switch (OpNum) {
      case 2:
        // op: imm10
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VLDREPL_H: {
      switch (OpNum) {
      case 2:
        // op: imm11
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVLDREPL_H: {
      switch (OpNum) {
      case 2:
        // op: imm11
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::FLD_D:
    case LoongArch::FLD_S:
    case LoongArch::FST_D:
    case LoongArch::FST_S: {
      switch (OpNum) {
      case 2:
        // op: imm12
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: fd
        return 0;
      }
      break;
    }
    case LoongArch::PRELD: {
      switch (OpNum) {
      case 2:
        // op: imm12
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: imm5
        return 0;
      }
      break;
    }
    case LoongArch::CACOP: {
      switch (OpNum) {
      case 2:
        // op: imm12
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: op
        return 0;
      }
      break;
    }
    case LoongArch::ADDI_D:
    case LoongArch::ADDI_W:
    case LoongArch::ANDI:
    case LoongArch::LDL_D:
    case LoongArch::LDL_W:
    case LoongArch::LDR_D:
    case LoongArch::LDR_W:
    case LoongArch::LD_B:
    case LoongArch::LD_BU:
    case LoongArch::LD_D:
    case LoongArch::LD_H:
    case LoongArch::LD_HU:
    case LoongArch::LD_W:
    case LoongArch::LD_WU:
    case LoongArch::LU52I_D:
    case LoongArch::ORI:
    case LoongArch::SLTI:
    case LoongArch::SLTUI:
    case LoongArch::STL_D:
    case LoongArch::STL_W:
    case LoongArch::STR_D:
    case LoongArch::STR_W:
    case LoongArch::ST_B:
    case LoongArch::ST_D:
    case LoongArch::ST_H:
    case LoongArch::ST_W:
    case LoongArch::XORI: {
      switch (OpNum) {
      case 2:
        // op: imm12
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VLD:
    case LoongArch::VLDREPL_B:
    case LoongArch::VST: {
      switch (OpNum) {
      case 2:
        // op: imm12
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVLD:
    case LoongArch::XVLDREPL_B:
    case LoongArch::XVST: {
      switch (OpNum) {
      case 2:
        // op: imm12
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::LDPTR_D:
    case LoongArch::LDPTR_W:
    case LoongArch::LL_D:
    case LoongArch::LL_W:
    case LoongArch::STPTR_D:
    case LoongArch::STPTR_W: {
      switch (OpNum) {
      case 2:
        // op: imm14
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::BEQ:
    case LoongArch::BGE:
    case LoongArch::BGEU:
    case LoongArch::BLT:
    case LoongArch::BLTU:
    case LoongArch::BNE: {
      switch (OpNum) {
      case 2:
        // op: imm16
        return 10;
      case 0:
        // op: rj
        return 5;
      case 1:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::ADDU16I_D:
    case LoongArch::JIRL: {
      switch (OpNum) {
      case 2:
        // op: imm16
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VPICKVE2GR_W:
    case LoongArch::VPICKVE2GR_WU: {
      switch (OpNum) {
      case 2:
        // op: imm2
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VREPLVEI_W: {
      switch (OpNum) {
      case 2:
        // op: imm2
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVPICKVE2GR_D:
    case LoongArch::XVPICKVE2GR_DU: {
      switch (OpNum) {
      case 2:
        // op: imm2
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::XVPICKVE_D:
    case LoongArch::XVREPL128VEI_W: {
      switch (OpNum) {
      case 2:
        // op: imm2
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::LU32I_D: {
      switch (OpNum) {
      case 2:
        // op: imm20
        return 5;
      case 1:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::RCRI_B:
    case LoongArch::ROTRI_B: {
      switch (OpNum) {
      case 2:
        // op: imm3
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VPICKVE2GR_H:
    case LoongArch::VPICKVE2GR_HU: {
      switch (OpNum) {
      case 2:
        // op: imm3
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VBITCLRI_B:
    case LoongArch::VBITREVI_B:
    case LoongArch::VBITSETI_B:
    case LoongArch::VREPLVEI_H:
    case LoongArch::VROTRI_B:
    case LoongArch::VSAT_B:
    case LoongArch::VSAT_BU:
    case LoongArch::VSLLI_B:
    case LoongArch::VSLLWIL_HU_BU:
    case LoongArch::VSLLWIL_H_B:
    case LoongArch::VSRAI_B:
    case LoongArch::VSRARI_B:
    case LoongArch::VSRLI_B:
    case LoongArch::VSRLRI_B: {
      switch (OpNum) {
      case 2:
        // op: imm3
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVPICKVE2GR_W:
    case LoongArch::XVPICKVE2GR_WU: {
      switch (OpNum) {
      case 2:
        // op: imm3
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::XVBITCLRI_B:
    case LoongArch::XVBITREVI_B:
    case LoongArch::XVBITSETI_B:
    case LoongArch::XVPICKVE_W:
    case LoongArch::XVREPL128VEI_H:
    case LoongArch::XVROTRI_B:
    case LoongArch::XVSAT_B:
    case LoongArch::XVSAT_BU:
    case LoongArch::XVSLLI_B:
    case LoongArch::XVSLLWIL_HU_BU:
    case LoongArch::XVSLLWIL_H_B:
    case LoongArch::XVSRAI_B:
    case LoongArch::XVSRARI_B:
    case LoongArch::XVSRLI_B:
    case LoongArch::XVSRLRI_B: {
      switch (OpNum) {
      case 2:
        // op: imm3
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::ARMADC_W:
    case LoongArch::ARMADD_W:
    case LoongArch::ARMAND_W:
    case LoongArch::ARMOR_W:
    case LoongArch::ARMROTR_W:
    case LoongArch::ARMSBC_W:
    case LoongArch::ARMSLL_W:
    case LoongArch::ARMSRA_W:
    case LoongArch::ARMSRL_W:
    case LoongArch::ARMSUB_W:
    case LoongArch::ARMXOR_W: {
      switch (OpNum) {
      case 2:
        // op: imm4
        return 0;
      case 1:
        // op: rk
        return 10;
      case 0:
        // op: rj
        return 5;
      }
      break;
    }
    case LoongArch::ARMMOVE:
    case LoongArch::RCRI_H:
    case LoongArch::ROTRI_H: {
      switch (OpNum) {
      case 2:
        // op: imm4
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VPICKVE2GR_B:
    case LoongArch::VPICKVE2GR_BU: {
      switch (OpNum) {
      case 2:
        // op: imm4
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VBITCLRI_H:
    case LoongArch::VBITREVI_H:
    case LoongArch::VBITSETI_H:
    case LoongArch::VREPLVEI_B:
    case LoongArch::VROTRI_H:
    case LoongArch::VSAT_H:
    case LoongArch::VSAT_HU:
    case LoongArch::VSLLI_H:
    case LoongArch::VSLLWIL_WU_HU:
    case LoongArch::VSLLWIL_W_H:
    case LoongArch::VSRAI_H:
    case LoongArch::VSRARI_H:
    case LoongArch::VSRLI_H:
    case LoongArch::VSRLRI_H: {
      switch (OpNum) {
      case 2:
        // op: imm4
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVBITCLRI_H:
    case LoongArch::XVBITREVI_H:
    case LoongArch::XVBITSETI_H:
    case LoongArch::XVREPL128VEI_B:
    case LoongArch::XVROTRI_H:
    case LoongArch::XVSAT_H:
    case LoongArch::XVSAT_HU:
    case LoongArch::XVSLLI_H:
    case LoongArch::XVSLLWIL_WU_HU:
    case LoongArch::XVSLLWIL_W_H:
    case LoongArch::XVSRAI_H:
    case LoongArch::XVSRARI_H:
    case LoongArch::XVSRLI_H:
    case LoongArch::XVSRLRI_H: {
      switch (OpNum) {
      case 2:
        // op: imm4
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::ADDU12I_D:
    case LoongArch::ADDU12I_W:
    case LoongArch::RCRI_W:
    case LoongArch::ROTRI_W:
    case LoongArch::SLLI_W:
    case LoongArch::SRAI_W:
    case LoongArch::SRLI_W: {
      switch (OpNum) {
      case 2:
        // op: imm5
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VADDI_BU:
    case LoongArch::VADDI_DU:
    case LoongArch::VADDI_HU:
    case LoongArch::VADDI_WU:
    case LoongArch::VBITCLRI_W:
    case LoongArch::VBITREVI_W:
    case LoongArch::VBITSETI_W:
    case LoongArch::VBSLL_V:
    case LoongArch::VBSRL_V:
    case LoongArch::VMAXI_B:
    case LoongArch::VMAXI_BU:
    case LoongArch::VMAXI_D:
    case LoongArch::VMAXI_DU:
    case LoongArch::VMAXI_H:
    case LoongArch::VMAXI_HU:
    case LoongArch::VMAXI_W:
    case LoongArch::VMAXI_WU:
    case LoongArch::VMINI_B:
    case LoongArch::VMINI_BU:
    case LoongArch::VMINI_D:
    case LoongArch::VMINI_DU:
    case LoongArch::VMINI_H:
    case LoongArch::VMINI_HU:
    case LoongArch::VMINI_W:
    case LoongArch::VMINI_WU:
    case LoongArch::VROTRI_W:
    case LoongArch::VSAT_W:
    case LoongArch::VSAT_WU:
    case LoongArch::VSEQI_B:
    case LoongArch::VSEQI_D:
    case LoongArch::VSEQI_H:
    case LoongArch::VSEQI_W:
    case LoongArch::VSLEI_B:
    case LoongArch::VSLEI_BU:
    case LoongArch::VSLEI_D:
    case LoongArch::VSLEI_DU:
    case LoongArch::VSLEI_H:
    case LoongArch::VSLEI_HU:
    case LoongArch::VSLEI_W:
    case LoongArch::VSLEI_WU:
    case LoongArch::VSLLI_W:
    case LoongArch::VSLLWIL_DU_WU:
    case LoongArch::VSLLWIL_D_W:
    case LoongArch::VSLTI_B:
    case LoongArch::VSLTI_BU:
    case LoongArch::VSLTI_D:
    case LoongArch::VSLTI_DU:
    case LoongArch::VSLTI_H:
    case LoongArch::VSLTI_HU:
    case LoongArch::VSLTI_W:
    case LoongArch::VSLTI_WU:
    case LoongArch::VSRAI_W:
    case LoongArch::VSRARI_W:
    case LoongArch::VSRLI_W:
    case LoongArch::VSRLRI_W:
    case LoongArch::VSUBI_BU:
    case LoongArch::VSUBI_DU:
    case LoongArch::VSUBI_HU:
    case LoongArch::VSUBI_WU: {
      switch (OpNum) {
      case 2:
        // op: imm5
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVADDI_BU:
    case LoongArch::XVADDI_DU:
    case LoongArch::XVADDI_HU:
    case LoongArch::XVADDI_WU:
    case LoongArch::XVBITCLRI_W:
    case LoongArch::XVBITREVI_W:
    case LoongArch::XVBITSETI_W:
    case LoongArch::XVBSLL_V:
    case LoongArch::XVBSRL_V:
    case LoongArch::XVHSELI_D:
    case LoongArch::XVMAXI_B:
    case LoongArch::XVMAXI_BU:
    case LoongArch::XVMAXI_D:
    case LoongArch::XVMAXI_DU:
    case LoongArch::XVMAXI_H:
    case LoongArch::XVMAXI_HU:
    case LoongArch::XVMAXI_W:
    case LoongArch::XVMAXI_WU:
    case LoongArch::XVMINI_B:
    case LoongArch::XVMINI_BU:
    case LoongArch::XVMINI_D:
    case LoongArch::XVMINI_DU:
    case LoongArch::XVMINI_H:
    case LoongArch::XVMINI_HU:
    case LoongArch::XVMINI_W:
    case LoongArch::XVMINI_WU:
    case LoongArch::XVROTRI_W:
    case LoongArch::XVSAT_W:
    case LoongArch::XVSAT_WU:
    case LoongArch::XVSEQI_B:
    case LoongArch::XVSEQI_D:
    case LoongArch::XVSEQI_H:
    case LoongArch::XVSEQI_W:
    case LoongArch::XVSLEI_B:
    case LoongArch::XVSLEI_BU:
    case LoongArch::XVSLEI_D:
    case LoongArch::XVSLEI_DU:
    case LoongArch::XVSLEI_H:
    case LoongArch::XVSLEI_HU:
    case LoongArch::XVSLEI_W:
    case LoongArch::XVSLEI_WU:
    case LoongArch::XVSLLI_W:
    case LoongArch::XVSLLWIL_DU_WU:
    case LoongArch::XVSLLWIL_D_W:
    case LoongArch::XVSLTI_B:
    case LoongArch::XVSLTI_BU:
    case LoongArch::XVSLTI_D:
    case LoongArch::XVSLTI_DU:
    case LoongArch::XVSLTI_H:
    case LoongArch::XVSLTI_HU:
    case LoongArch::XVSLTI_W:
    case LoongArch::XVSLTI_WU:
    case LoongArch::XVSRAI_W:
    case LoongArch::XVSRARI_W:
    case LoongArch::XVSRLI_W:
    case LoongArch::XVSRLRI_W:
    case LoongArch::XVSUBI_BU:
    case LoongArch::XVSUBI_DU:
    case LoongArch::XVSUBI_HU:
    case LoongArch::XVSUBI_WU: {
      switch (OpNum) {
      case 2:
        // op: imm5
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::RCRI_D:
    case LoongArch::ROTRI_D:
    case LoongArch::SLLI_D:
    case LoongArch::SRAI_D:
    case LoongArch::SRLI_D: {
      switch (OpNum) {
      case 2:
        // op: imm6
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VBITCLRI_D:
    case LoongArch::VBITREVI_D:
    case LoongArch::VBITSETI_D:
    case LoongArch::VROTRI_D:
    case LoongArch::VSAT_D:
    case LoongArch::VSAT_DU:
    case LoongArch::VSLLI_D:
    case LoongArch::VSRAI_D:
    case LoongArch::VSRARI_D:
    case LoongArch::VSRLI_D:
    case LoongArch::VSRLRI_D: {
      switch (OpNum) {
      case 2:
        // op: imm6
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVBITCLRI_D:
    case LoongArch::XVBITREVI_D:
    case LoongArch::XVBITSETI_D:
    case LoongArch::XVROTRI_D:
    case LoongArch::XVSAT_D:
    case LoongArch::XVSAT_DU:
    case LoongArch::XVSLLI_D:
    case LoongArch::XVSRAI_D:
    case LoongArch::XVSRARI_D:
    case LoongArch::XVSRLI_D:
    case LoongArch::XVSRLRI_D: {
      switch (OpNum) {
      case 2:
        // op: imm6
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::X86SETTAG: {
      switch (OpNum) {
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: imm5
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::LDDIR: {
      switch (OpNum) {
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VANDI_B:
    case LoongArch::VNORI_B:
    case LoongArch::VORI_B:
    case LoongArch::VSHUF4I_B:
    case LoongArch::VSHUF4I_H:
    case LoongArch::VSHUF4I_W:
    case LoongArch::VXORI_B: {
      switch (OpNum) {
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVANDI_B:
    case LoongArch::XVNORI_B:
    case LoongArch::XVORI_B:
    case LoongArch::XVPERMI_D:
    case LoongArch::XVSHUF4I_B:
    case LoongArch::XVSHUF4I_H:
    case LoongArch::XVSHUF4I_W:
    case LoongArch::XVXORI_B: {
      switch (OpNum) {
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VLDREPL_D: {
      switch (OpNum) {
      case 2:
        // op: imm9
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVLDREPL_D: {
      switch (OpNum) {
      case 2:
        // op: imm9
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::BSTRPICK_D: {
      switch (OpNum) {
      case 2:
        // op: msbd
        return 16;
      case 3:
        // op: lsbd
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::BSTRPICK_W: {
      switch (OpNum) {
      case 2:
        // op: msbw
        return 16;
      case 3:
        // op: lsbw
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::SCREL_D:
    case LoongArch::SCREL_W: {
      switch (OpNum) {
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::FLDGT_D:
    case LoongArch::FLDGT_S:
    case LoongArch::FLDLE_D:
    case LoongArch::FLDLE_S:
    case LoongArch::FLDX_D:
    case LoongArch::FLDX_S:
    case LoongArch::FSTGT_D:
    case LoongArch::FSTGT_S:
    case LoongArch::FSTLE_D:
    case LoongArch::FSTLE_S:
    case LoongArch::FSTX_D:
    case LoongArch::FSTX_S: {
      switch (OpNum) {
      case 2:
        // op: rk
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: fd
        return 0;
      }
      break;
    }
    case LoongArch::PRELDX: {
      switch (OpNum) {
      case 2:
        // op: rk
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: imm5
        return 0;
      }
      break;
    }
    case LoongArch::ADC_B:
    case LoongArch::ADC_D:
    case LoongArch::ADC_H:
    case LoongArch::ADC_W:
    case LoongArch::ADD_D:
    case LoongArch::ADD_W:
    case LoongArch::AND:
    case LoongArch::ANDN:
    case LoongArch::CRCC_W_B_W:
    case LoongArch::CRCC_W_D_W:
    case LoongArch::CRCC_W_H_W:
    case LoongArch::CRCC_W_W_W:
    case LoongArch::CRC_W_B_W:
    case LoongArch::CRC_W_D_W:
    case LoongArch::CRC_W_H_W:
    case LoongArch::CRC_W_W_W:
    case LoongArch::DIV_D:
    case LoongArch::DIV_DU:
    case LoongArch::DIV_W:
    case LoongArch::DIV_WU:
    case LoongArch::LDGT_B:
    case LoongArch::LDGT_D:
    case LoongArch::LDGT_H:
    case LoongArch::LDGT_W:
    case LoongArch::LDLE_B:
    case LoongArch::LDLE_D:
    case LoongArch::LDLE_H:
    case LoongArch::LDLE_W:
    case LoongArch::LDX_B:
    case LoongArch::LDX_BU:
    case LoongArch::LDX_D:
    case LoongArch::LDX_H:
    case LoongArch::LDX_HU:
    case LoongArch::LDX_W:
    case LoongArch::LDX_WU:
    case LoongArch::MASKEQZ:
    case LoongArch::MASKNEZ:
    case LoongArch::MOD_D:
    case LoongArch::MOD_DU:
    case LoongArch::MOD_W:
    case LoongArch::MOD_WU:
    case LoongArch::MULH_D:
    case LoongArch::MULH_DU:
    case LoongArch::MULH_W:
    case LoongArch::MULH_WU:
    case LoongArch::MULW_D_W:
    case LoongArch::MULW_D_WU:
    case LoongArch::MUL_D:
    case LoongArch::MUL_W:
    case LoongArch::NOR:
    case LoongArch::OR:
    case LoongArch::ORN:
    case LoongArch::RCR_B:
    case LoongArch::RCR_D:
    case LoongArch::RCR_H:
    case LoongArch::RCR_W:
    case LoongArch::ROTR_B:
    case LoongArch::ROTR_D:
    case LoongArch::ROTR_H:
    case LoongArch::ROTR_W:
    case LoongArch::SBC_B:
    case LoongArch::SBC_D:
    case LoongArch::SBC_H:
    case LoongArch::SBC_W:
    case LoongArch::SLL_D:
    case LoongArch::SLL_W:
    case LoongArch::SLT:
    case LoongArch::SLTU:
    case LoongArch::SRA_D:
    case LoongArch::SRA_W:
    case LoongArch::SRL_D:
    case LoongArch::SRL_W:
    case LoongArch::STGT_B:
    case LoongArch::STGT_D:
    case LoongArch::STGT_H:
    case LoongArch::STGT_W:
    case LoongArch::STLE_B:
    case LoongArch::STLE_D:
    case LoongArch::STLE_H:
    case LoongArch::STLE_W:
    case LoongArch::STX_B:
    case LoongArch::STX_D:
    case LoongArch::STX_H:
    case LoongArch::STX_W:
    case LoongArch::SUB_D:
    case LoongArch::SUB_W:
    case LoongArch::XOR: {
      switch (OpNum) {
      case 2:
        // op: rk
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VLDX:
    case LoongArch::VSTX: {
      switch (OpNum) {
      case 2:
        // op: rk
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVLDX:
    case LoongArch::XVSTX: {
      switch (OpNum) {
      case 2:
        // op: rk
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VREPLVE_B:
    case LoongArch::VREPLVE_D:
    case LoongArch::VREPLVE_H:
    case LoongArch::VREPLVE_W: {
      switch (OpNum) {
      case 2:
        // op: rk
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVREPLVE_B:
    case LoongArch::XVREPLVE_D:
    case LoongArch::XVREPLVE_H:
    case LoongArch::XVREPLVE_W: {
      switch (OpNum) {
      case 2:
        // op: rk
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::AMCAS_B:
    case LoongArch::AMCAS_D:
    case LoongArch::AMCAS_H:
    case LoongArch::AMCAS_W:
    case LoongArch::AMCAS__DB_B:
    case LoongArch::AMCAS__DB_D:
    case LoongArch::AMCAS__DB_H:
    case LoongArch::AMCAS__DB_W:
    case LoongArch::SC_Q: {
      switch (OpNum) {
      case 2:
        // op: rk
        return 10;
      case 3:
        // op: rj
        return 5;
      case 1:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::MOVGR2FRH_W: {
      switch (OpNum) {
      case 2:
        // op: src
        return 5;
      case 1:
        // op: dst
        return 0;
      }
      break;
    }
    case LoongArch::VABSD_B:
    case LoongArch::VABSD_BU:
    case LoongArch::VABSD_D:
    case LoongArch::VABSD_DU:
    case LoongArch::VABSD_H:
    case LoongArch::VABSD_HU:
    case LoongArch::VABSD_W:
    case LoongArch::VABSD_WU:
    case LoongArch::VADDA_B:
    case LoongArch::VADDA_D:
    case LoongArch::VADDA_H:
    case LoongArch::VADDA_W:
    case LoongArch::VADDWEV_D_W:
    case LoongArch::VADDWEV_D_WU:
    case LoongArch::VADDWEV_D_WU_W:
    case LoongArch::VADDWEV_H_B:
    case LoongArch::VADDWEV_H_BU:
    case LoongArch::VADDWEV_H_BU_B:
    case LoongArch::VADDWEV_Q_D:
    case LoongArch::VADDWEV_Q_DU:
    case LoongArch::VADDWEV_Q_DU_D:
    case LoongArch::VADDWEV_W_H:
    case LoongArch::VADDWEV_W_HU:
    case LoongArch::VADDWEV_W_HU_H:
    case LoongArch::VADDWOD_D_W:
    case LoongArch::VADDWOD_D_WU:
    case LoongArch::VADDWOD_D_WU_W:
    case LoongArch::VADDWOD_H_B:
    case LoongArch::VADDWOD_H_BU:
    case LoongArch::VADDWOD_H_BU_B:
    case LoongArch::VADDWOD_Q_D:
    case LoongArch::VADDWOD_Q_DU:
    case LoongArch::VADDWOD_Q_DU_D:
    case LoongArch::VADDWOD_W_H:
    case LoongArch::VADDWOD_W_HU:
    case LoongArch::VADDWOD_W_HU_H:
    case LoongArch::VADD_B:
    case LoongArch::VADD_D:
    case LoongArch::VADD_H:
    case LoongArch::VADD_Q:
    case LoongArch::VADD_W:
    case LoongArch::VANDN_V:
    case LoongArch::VAND_V:
    case LoongArch::VAVGR_B:
    case LoongArch::VAVGR_BU:
    case LoongArch::VAVGR_D:
    case LoongArch::VAVGR_DU:
    case LoongArch::VAVGR_H:
    case LoongArch::VAVGR_HU:
    case LoongArch::VAVGR_W:
    case LoongArch::VAVGR_WU:
    case LoongArch::VAVG_B:
    case LoongArch::VAVG_BU:
    case LoongArch::VAVG_D:
    case LoongArch::VAVG_DU:
    case LoongArch::VAVG_H:
    case LoongArch::VAVG_HU:
    case LoongArch::VAVG_W:
    case LoongArch::VAVG_WU:
    case LoongArch::VBITCLR_B:
    case LoongArch::VBITCLR_D:
    case LoongArch::VBITCLR_H:
    case LoongArch::VBITCLR_W:
    case LoongArch::VBITREV_B:
    case LoongArch::VBITREV_D:
    case LoongArch::VBITREV_H:
    case LoongArch::VBITREV_W:
    case LoongArch::VBITSET_B:
    case LoongArch::VBITSET_D:
    case LoongArch::VBITSET_H:
    case LoongArch::VBITSET_W:
    case LoongArch::VDIV_B:
    case LoongArch::VDIV_BU:
    case LoongArch::VDIV_D:
    case LoongArch::VDIV_DU:
    case LoongArch::VDIV_H:
    case LoongArch::VDIV_HU:
    case LoongArch::VDIV_W:
    case LoongArch::VDIV_WU:
    case LoongArch::VFADD_D:
    case LoongArch::VFADD_S:
    case LoongArch::VFCMP_CAF_D:
    case LoongArch::VFCMP_CAF_S:
    case LoongArch::VFCMP_CEQ_D:
    case LoongArch::VFCMP_CEQ_S:
    case LoongArch::VFCMP_CLE_D:
    case LoongArch::VFCMP_CLE_S:
    case LoongArch::VFCMP_CLT_D:
    case LoongArch::VFCMP_CLT_S:
    case LoongArch::VFCMP_CNE_D:
    case LoongArch::VFCMP_CNE_S:
    case LoongArch::VFCMP_COR_D:
    case LoongArch::VFCMP_COR_S:
    case LoongArch::VFCMP_CUEQ_D:
    case LoongArch::VFCMP_CUEQ_S:
    case LoongArch::VFCMP_CULE_D:
    case LoongArch::VFCMP_CULE_S:
    case LoongArch::VFCMP_CULT_D:
    case LoongArch::VFCMP_CULT_S:
    case LoongArch::VFCMP_CUNE_D:
    case LoongArch::VFCMP_CUNE_S:
    case LoongArch::VFCMP_CUN_D:
    case LoongArch::VFCMP_CUN_S:
    case LoongArch::VFCMP_SAF_D:
    case LoongArch::VFCMP_SAF_S:
    case LoongArch::VFCMP_SEQ_D:
    case LoongArch::VFCMP_SEQ_S:
    case LoongArch::VFCMP_SLE_D:
    case LoongArch::VFCMP_SLE_S:
    case LoongArch::VFCMP_SLT_D:
    case LoongArch::VFCMP_SLT_S:
    case LoongArch::VFCMP_SNE_D:
    case LoongArch::VFCMP_SNE_S:
    case LoongArch::VFCMP_SOR_D:
    case LoongArch::VFCMP_SOR_S:
    case LoongArch::VFCMP_SUEQ_D:
    case LoongArch::VFCMP_SUEQ_S:
    case LoongArch::VFCMP_SULE_D:
    case LoongArch::VFCMP_SULE_S:
    case LoongArch::VFCMP_SULT_D:
    case LoongArch::VFCMP_SULT_S:
    case LoongArch::VFCMP_SUNE_D:
    case LoongArch::VFCMP_SUNE_S:
    case LoongArch::VFCMP_SUN_D:
    case LoongArch::VFCMP_SUN_S:
    case LoongArch::VFCVT_H_S:
    case LoongArch::VFCVT_S_D:
    case LoongArch::VFDIV_D:
    case LoongArch::VFDIV_S:
    case LoongArch::VFFINT_S_L:
    case LoongArch::VFMAXA_D:
    case LoongArch::VFMAXA_S:
    case LoongArch::VFMAX_D:
    case LoongArch::VFMAX_S:
    case LoongArch::VFMINA_D:
    case LoongArch::VFMINA_S:
    case LoongArch::VFMIN_D:
    case LoongArch::VFMIN_S:
    case LoongArch::VFMUL_D:
    case LoongArch::VFMUL_S:
    case LoongArch::VFSUB_D:
    case LoongArch::VFSUB_S:
    case LoongArch::VFTINTRM_W_D:
    case LoongArch::VFTINTRNE_W_D:
    case LoongArch::VFTINTRP_W_D:
    case LoongArch::VFTINTRZ_W_D:
    case LoongArch::VFTINT_W_D:
    case LoongArch::VHADDW_DU_WU:
    case LoongArch::VHADDW_D_W:
    case LoongArch::VHADDW_HU_BU:
    case LoongArch::VHADDW_H_B:
    case LoongArch::VHADDW_QU_DU:
    case LoongArch::VHADDW_Q_D:
    case LoongArch::VHADDW_WU_HU:
    case LoongArch::VHADDW_W_H:
    case LoongArch::VHSUBW_DU_WU:
    case LoongArch::VHSUBW_D_W:
    case LoongArch::VHSUBW_HU_BU:
    case LoongArch::VHSUBW_H_B:
    case LoongArch::VHSUBW_QU_DU:
    case LoongArch::VHSUBW_Q_D:
    case LoongArch::VHSUBW_WU_HU:
    case LoongArch::VHSUBW_W_H:
    case LoongArch::VILVH_B:
    case LoongArch::VILVH_D:
    case LoongArch::VILVH_H:
    case LoongArch::VILVH_W:
    case LoongArch::VILVL_B:
    case LoongArch::VILVL_D:
    case LoongArch::VILVL_H:
    case LoongArch::VILVL_W:
    case LoongArch::VMAX_B:
    case LoongArch::VMAX_BU:
    case LoongArch::VMAX_D:
    case LoongArch::VMAX_DU:
    case LoongArch::VMAX_H:
    case LoongArch::VMAX_HU:
    case LoongArch::VMAX_W:
    case LoongArch::VMAX_WU:
    case LoongArch::VMIN_B:
    case LoongArch::VMIN_BU:
    case LoongArch::VMIN_D:
    case LoongArch::VMIN_DU:
    case LoongArch::VMIN_H:
    case LoongArch::VMIN_HU:
    case LoongArch::VMIN_W:
    case LoongArch::VMIN_WU:
    case LoongArch::VMOD_B:
    case LoongArch::VMOD_BU:
    case LoongArch::VMOD_D:
    case LoongArch::VMOD_DU:
    case LoongArch::VMOD_H:
    case LoongArch::VMOD_HU:
    case LoongArch::VMOD_W:
    case LoongArch::VMOD_WU:
    case LoongArch::VMUH_B:
    case LoongArch::VMUH_BU:
    case LoongArch::VMUH_D:
    case LoongArch::VMUH_DU:
    case LoongArch::VMUH_H:
    case LoongArch::VMUH_HU:
    case LoongArch::VMUH_W:
    case LoongArch::VMUH_WU:
    case LoongArch::VMULWEV_D_W:
    case LoongArch::VMULWEV_D_WU:
    case LoongArch::VMULWEV_D_WU_W:
    case LoongArch::VMULWEV_H_B:
    case LoongArch::VMULWEV_H_BU:
    case LoongArch::VMULWEV_H_BU_B:
    case LoongArch::VMULWEV_Q_D:
    case LoongArch::VMULWEV_Q_DU:
    case LoongArch::VMULWEV_Q_DU_D:
    case LoongArch::VMULWEV_W_H:
    case LoongArch::VMULWEV_W_HU:
    case LoongArch::VMULWEV_W_HU_H:
    case LoongArch::VMULWOD_D_W:
    case LoongArch::VMULWOD_D_WU:
    case LoongArch::VMULWOD_D_WU_W:
    case LoongArch::VMULWOD_H_B:
    case LoongArch::VMULWOD_H_BU:
    case LoongArch::VMULWOD_H_BU_B:
    case LoongArch::VMULWOD_Q_D:
    case LoongArch::VMULWOD_Q_DU:
    case LoongArch::VMULWOD_Q_DU_D:
    case LoongArch::VMULWOD_W_H:
    case LoongArch::VMULWOD_W_HU:
    case LoongArch::VMULWOD_W_HU_H:
    case LoongArch::VMUL_B:
    case LoongArch::VMUL_D:
    case LoongArch::VMUL_H:
    case LoongArch::VMUL_W:
    case LoongArch::VNOR_V:
    case LoongArch::VORN_V:
    case LoongArch::VOR_V:
    case LoongArch::VPACKEV_B:
    case LoongArch::VPACKEV_D:
    case LoongArch::VPACKEV_H:
    case LoongArch::VPACKEV_W:
    case LoongArch::VPACKOD_B:
    case LoongArch::VPACKOD_D:
    case LoongArch::VPACKOD_H:
    case LoongArch::VPACKOD_W:
    case LoongArch::VPICKEV_B:
    case LoongArch::VPICKEV_D:
    case LoongArch::VPICKEV_H:
    case LoongArch::VPICKEV_W:
    case LoongArch::VPICKOD_B:
    case LoongArch::VPICKOD_D:
    case LoongArch::VPICKOD_H:
    case LoongArch::VPICKOD_W:
    case LoongArch::VROTR_B:
    case LoongArch::VROTR_D:
    case LoongArch::VROTR_H:
    case LoongArch::VROTR_W:
    case LoongArch::VSADD_B:
    case LoongArch::VSADD_BU:
    case LoongArch::VSADD_D:
    case LoongArch::VSADD_DU:
    case LoongArch::VSADD_H:
    case LoongArch::VSADD_HU:
    case LoongArch::VSADD_W:
    case LoongArch::VSADD_WU:
    case LoongArch::VSEQ_B:
    case LoongArch::VSEQ_D:
    case LoongArch::VSEQ_H:
    case LoongArch::VSEQ_W:
    case LoongArch::VSIGNCOV_B:
    case LoongArch::VSIGNCOV_D:
    case LoongArch::VSIGNCOV_H:
    case LoongArch::VSIGNCOV_W:
    case LoongArch::VSLE_B:
    case LoongArch::VSLE_BU:
    case LoongArch::VSLE_D:
    case LoongArch::VSLE_DU:
    case LoongArch::VSLE_H:
    case LoongArch::VSLE_HU:
    case LoongArch::VSLE_W:
    case LoongArch::VSLE_WU:
    case LoongArch::VSLL_B:
    case LoongArch::VSLL_D:
    case LoongArch::VSLL_H:
    case LoongArch::VSLL_W:
    case LoongArch::VSLT_B:
    case LoongArch::VSLT_BU:
    case LoongArch::VSLT_D:
    case LoongArch::VSLT_DU:
    case LoongArch::VSLT_H:
    case LoongArch::VSLT_HU:
    case LoongArch::VSLT_W:
    case LoongArch::VSLT_WU:
    case LoongArch::VSRAN_B_H:
    case LoongArch::VSRAN_H_W:
    case LoongArch::VSRAN_W_D:
    case LoongArch::VSRARN_B_H:
    case LoongArch::VSRARN_H_W:
    case LoongArch::VSRARN_W_D:
    case LoongArch::VSRAR_B:
    case LoongArch::VSRAR_D:
    case LoongArch::VSRAR_H:
    case LoongArch::VSRAR_W:
    case LoongArch::VSRA_B:
    case LoongArch::VSRA_D:
    case LoongArch::VSRA_H:
    case LoongArch::VSRA_W:
    case LoongArch::VSRLN_B_H:
    case LoongArch::VSRLN_H_W:
    case LoongArch::VSRLN_W_D:
    case LoongArch::VSRLRN_B_H:
    case LoongArch::VSRLRN_H_W:
    case LoongArch::VSRLRN_W_D:
    case LoongArch::VSRLR_B:
    case LoongArch::VSRLR_D:
    case LoongArch::VSRLR_H:
    case LoongArch::VSRLR_W:
    case LoongArch::VSRL_B:
    case LoongArch::VSRL_D:
    case LoongArch::VSRL_H:
    case LoongArch::VSRL_W:
    case LoongArch::VSSRAN_BU_H:
    case LoongArch::VSSRAN_B_H:
    case LoongArch::VSSRAN_HU_W:
    case LoongArch::VSSRAN_H_W:
    case LoongArch::VSSRAN_WU_D:
    case LoongArch::VSSRAN_W_D:
    case LoongArch::VSSRARN_BU_H:
    case LoongArch::VSSRARN_B_H:
    case LoongArch::VSSRARN_HU_W:
    case LoongArch::VSSRARN_H_W:
    case LoongArch::VSSRARN_WU_D:
    case LoongArch::VSSRARN_W_D:
    case LoongArch::VSSRLN_BU_H:
    case LoongArch::VSSRLN_B_H:
    case LoongArch::VSSRLN_HU_W:
    case LoongArch::VSSRLN_H_W:
    case LoongArch::VSSRLN_WU_D:
    case LoongArch::VSSRLN_W_D:
    case LoongArch::VSSRLRN_BU_H:
    case LoongArch::VSSRLRN_B_H:
    case LoongArch::VSSRLRN_HU_W:
    case LoongArch::VSSRLRN_H_W:
    case LoongArch::VSSRLRN_WU_D:
    case LoongArch::VSSRLRN_W_D:
    case LoongArch::VSSUB_B:
    case LoongArch::VSSUB_BU:
    case LoongArch::VSSUB_D:
    case LoongArch::VSSUB_DU:
    case LoongArch::VSSUB_H:
    case LoongArch::VSSUB_HU:
    case LoongArch::VSSUB_W:
    case LoongArch::VSSUB_WU:
    case LoongArch::VSUBWEV_D_W:
    case LoongArch::VSUBWEV_D_WU:
    case LoongArch::VSUBWEV_H_B:
    case LoongArch::VSUBWEV_H_BU:
    case LoongArch::VSUBWEV_Q_D:
    case LoongArch::VSUBWEV_Q_DU:
    case LoongArch::VSUBWEV_W_H:
    case LoongArch::VSUBWEV_W_HU:
    case LoongArch::VSUBWOD_D_W:
    case LoongArch::VSUBWOD_D_WU:
    case LoongArch::VSUBWOD_H_B:
    case LoongArch::VSUBWOD_H_BU:
    case LoongArch::VSUBWOD_Q_D:
    case LoongArch::VSUBWOD_Q_DU:
    case LoongArch::VSUBWOD_W_H:
    case LoongArch::VSUBWOD_W_HU:
    case LoongArch::VSUB_B:
    case LoongArch::VSUB_D:
    case LoongArch::VSUB_H:
    case LoongArch::VSUB_Q:
    case LoongArch::VSUB_W:
    case LoongArch::VXOR_V: {
      switch (OpNum) {
      case 2:
        // op: vk
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVABSD_B:
    case LoongArch::XVABSD_BU:
    case LoongArch::XVABSD_D:
    case LoongArch::XVABSD_DU:
    case LoongArch::XVABSD_H:
    case LoongArch::XVABSD_HU:
    case LoongArch::XVABSD_W:
    case LoongArch::XVABSD_WU:
    case LoongArch::XVADDA_B:
    case LoongArch::XVADDA_D:
    case LoongArch::XVADDA_H:
    case LoongArch::XVADDA_W:
    case LoongArch::XVADDWEV_D_W:
    case LoongArch::XVADDWEV_D_WU:
    case LoongArch::XVADDWEV_D_WU_W:
    case LoongArch::XVADDWEV_H_B:
    case LoongArch::XVADDWEV_H_BU:
    case LoongArch::XVADDWEV_H_BU_B:
    case LoongArch::XVADDWEV_Q_D:
    case LoongArch::XVADDWEV_Q_DU:
    case LoongArch::XVADDWEV_Q_DU_D:
    case LoongArch::XVADDWEV_W_H:
    case LoongArch::XVADDWEV_W_HU:
    case LoongArch::XVADDWEV_W_HU_H:
    case LoongArch::XVADDWOD_D_W:
    case LoongArch::XVADDWOD_D_WU:
    case LoongArch::XVADDWOD_D_WU_W:
    case LoongArch::XVADDWOD_H_B:
    case LoongArch::XVADDWOD_H_BU:
    case LoongArch::XVADDWOD_H_BU_B:
    case LoongArch::XVADDWOD_Q_D:
    case LoongArch::XVADDWOD_Q_DU:
    case LoongArch::XVADDWOD_Q_DU_D:
    case LoongArch::XVADDWOD_W_H:
    case LoongArch::XVADDWOD_W_HU:
    case LoongArch::XVADDWOD_W_HU_H:
    case LoongArch::XVADD_B:
    case LoongArch::XVADD_D:
    case LoongArch::XVADD_H:
    case LoongArch::XVADD_Q:
    case LoongArch::XVADD_W:
    case LoongArch::XVANDN_V:
    case LoongArch::XVAND_V:
    case LoongArch::XVAVGR_B:
    case LoongArch::XVAVGR_BU:
    case LoongArch::XVAVGR_D:
    case LoongArch::XVAVGR_DU:
    case LoongArch::XVAVGR_H:
    case LoongArch::XVAVGR_HU:
    case LoongArch::XVAVGR_W:
    case LoongArch::XVAVGR_WU:
    case LoongArch::XVAVG_B:
    case LoongArch::XVAVG_BU:
    case LoongArch::XVAVG_D:
    case LoongArch::XVAVG_DU:
    case LoongArch::XVAVG_H:
    case LoongArch::XVAVG_HU:
    case LoongArch::XVAVG_W:
    case LoongArch::XVAVG_WU:
    case LoongArch::XVBITCLR_B:
    case LoongArch::XVBITCLR_D:
    case LoongArch::XVBITCLR_H:
    case LoongArch::XVBITCLR_W:
    case LoongArch::XVBITREV_B:
    case LoongArch::XVBITREV_D:
    case LoongArch::XVBITREV_H:
    case LoongArch::XVBITREV_W:
    case LoongArch::XVBITSET_B:
    case LoongArch::XVBITSET_D:
    case LoongArch::XVBITSET_H:
    case LoongArch::XVBITSET_W:
    case LoongArch::XVDIV_B:
    case LoongArch::XVDIV_BU:
    case LoongArch::XVDIV_D:
    case LoongArch::XVDIV_DU:
    case LoongArch::XVDIV_H:
    case LoongArch::XVDIV_HU:
    case LoongArch::XVDIV_W:
    case LoongArch::XVDIV_WU:
    case LoongArch::XVFADD_D:
    case LoongArch::XVFADD_S:
    case LoongArch::XVFCMP_CAF_D:
    case LoongArch::XVFCMP_CAF_S:
    case LoongArch::XVFCMP_CEQ_D:
    case LoongArch::XVFCMP_CEQ_S:
    case LoongArch::XVFCMP_CLE_D:
    case LoongArch::XVFCMP_CLE_S:
    case LoongArch::XVFCMP_CLT_D:
    case LoongArch::XVFCMP_CLT_S:
    case LoongArch::XVFCMP_CNE_D:
    case LoongArch::XVFCMP_CNE_S:
    case LoongArch::XVFCMP_COR_D:
    case LoongArch::XVFCMP_COR_S:
    case LoongArch::XVFCMP_CUEQ_D:
    case LoongArch::XVFCMP_CUEQ_S:
    case LoongArch::XVFCMP_CULE_D:
    case LoongArch::XVFCMP_CULE_S:
    case LoongArch::XVFCMP_CULT_D:
    case LoongArch::XVFCMP_CULT_S:
    case LoongArch::XVFCMP_CUNE_D:
    case LoongArch::XVFCMP_CUNE_S:
    case LoongArch::XVFCMP_CUN_D:
    case LoongArch::XVFCMP_CUN_S:
    case LoongArch::XVFCMP_SAF_D:
    case LoongArch::XVFCMP_SAF_S:
    case LoongArch::XVFCMP_SEQ_D:
    case LoongArch::XVFCMP_SEQ_S:
    case LoongArch::XVFCMP_SLE_D:
    case LoongArch::XVFCMP_SLE_S:
    case LoongArch::XVFCMP_SLT_D:
    case LoongArch::XVFCMP_SLT_S:
    case LoongArch::XVFCMP_SNE_D:
    case LoongArch::XVFCMP_SNE_S:
    case LoongArch::XVFCMP_SOR_D:
    case LoongArch::XVFCMP_SOR_S:
    case LoongArch::XVFCMP_SUEQ_D:
    case LoongArch::XVFCMP_SUEQ_S:
    case LoongArch::XVFCMP_SULE_D:
    case LoongArch::XVFCMP_SULE_S:
    case LoongArch::XVFCMP_SULT_D:
    case LoongArch::XVFCMP_SULT_S:
    case LoongArch::XVFCMP_SUNE_D:
    case LoongArch::XVFCMP_SUNE_S:
    case LoongArch::XVFCMP_SUN_D:
    case LoongArch::XVFCMP_SUN_S:
    case LoongArch::XVFCVT_H_S:
    case LoongArch::XVFCVT_S_D:
    case LoongArch::XVFDIV_D:
    case LoongArch::XVFDIV_S:
    case LoongArch::XVFFINT_S_L:
    case LoongArch::XVFMAXA_D:
    case LoongArch::XVFMAXA_S:
    case LoongArch::XVFMAX_D:
    case LoongArch::XVFMAX_S:
    case LoongArch::XVFMINA_D:
    case LoongArch::XVFMINA_S:
    case LoongArch::XVFMIN_D:
    case LoongArch::XVFMIN_S:
    case LoongArch::XVFMUL_D:
    case LoongArch::XVFMUL_S:
    case LoongArch::XVFSUB_D:
    case LoongArch::XVFSUB_S:
    case LoongArch::XVFTINTRM_W_D:
    case LoongArch::XVFTINTRNE_W_D:
    case LoongArch::XVFTINTRP_W_D:
    case LoongArch::XVFTINTRZ_W_D:
    case LoongArch::XVFTINT_W_D:
    case LoongArch::XVHADDW_DU_WU:
    case LoongArch::XVHADDW_D_W:
    case LoongArch::XVHADDW_HU_BU:
    case LoongArch::XVHADDW_H_B:
    case LoongArch::XVHADDW_QU_DU:
    case LoongArch::XVHADDW_Q_D:
    case LoongArch::XVHADDW_WU_HU:
    case LoongArch::XVHADDW_W_H:
    case LoongArch::XVHSUBW_DU_WU:
    case LoongArch::XVHSUBW_D_W:
    case LoongArch::XVHSUBW_HU_BU:
    case LoongArch::XVHSUBW_H_B:
    case LoongArch::XVHSUBW_QU_DU:
    case LoongArch::XVHSUBW_Q_D:
    case LoongArch::XVHSUBW_WU_HU:
    case LoongArch::XVHSUBW_W_H:
    case LoongArch::XVILVH_B:
    case LoongArch::XVILVH_D:
    case LoongArch::XVILVH_H:
    case LoongArch::XVILVH_W:
    case LoongArch::XVILVL_B:
    case LoongArch::XVILVL_D:
    case LoongArch::XVILVL_H:
    case LoongArch::XVILVL_W:
    case LoongArch::XVMAX_B:
    case LoongArch::XVMAX_BU:
    case LoongArch::XVMAX_D:
    case LoongArch::XVMAX_DU:
    case LoongArch::XVMAX_H:
    case LoongArch::XVMAX_HU:
    case LoongArch::XVMAX_W:
    case LoongArch::XVMAX_WU:
    case LoongArch::XVMIN_B:
    case LoongArch::XVMIN_BU:
    case LoongArch::XVMIN_D:
    case LoongArch::XVMIN_DU:
    case LoongArch::XVMIN_H:
    case LoongArch::XVMIN_HU:
    case LoongArch::XVMIN_W:
    case LoongArch::XVMIN_WU:
    case LoongArch::XVMOD_B:
    case LoongArch::XVMOD_BU:
    case LoongArch::XVMOD_D:
    case LoongArch::XVMOD_DU:
    case LoongArch::XVMOD_H:
    case LoongArch::XVMOD_HU:
    case LoongArch::XVMOD_W:
    case LoongArch::XVMOD_WU:
    case LoongArch::XVMUH_B:
    case LoongArch::XVMUH_BU:
    case LoongArch::XVMUH_D:
    case LoongArch::XVMUH_DU:
    case LoongArch::XVMUH_H:
    case LoongArch::XVMUH_HU:
    case LoongArch::XVMUH_W:
    case LoongArch::XVMUH_WU:
    case LoongArch::XVMULWEV_D_W:
    case LoongArch::XVMULWEV_D_WU:
    case LoongArch::XVMULWEV_D_WU_W:
    case LoongArch::XVMULWEV_H_B:
    case LoongArch::XVMULWEV_H_BU:
    case LoongArch::XVMULWEV_H_BU_B:
    case LoongArch::XVMULWEV_Q_D:
    case LoongArch::XVMULWEV_Q_DU:
    case LoongArch::XVMULWEV_Q_DU_D:
    case LoongArch::XVMULWEV_W_H:
    case LoongArch::XVMULWEV_W_HU:
    case LoongArch::XVMULWEV_W_HU_H:
    case LoongArch::XVMULWOD_D_W:
    case LoongArch::XVMULWOD_D_WU:
    case LoongArch::XVMULWOD_D_WU_W:
    case LoongArch::XVMULWOD_H_B:
    case LoongArch::XVMULWOD_H_BU:
    case LoongArch::XVMULWOD_H_BU_B:
    case LoongArch::XVMULWOD_Q_D:
    case LoongArch::XVMULWOD_Q_DU:
    case LoongArch::XVMULWOD_Q_DU_D:
    case LoongArch::XVMULWOD_W_H:
    case LoongArch::XVMULWOD_W_HU:
    case LoongArch::XVMULWOD_W_HU_H:
    case LoongArch::XVMUL_B:
    case LoongArch::XVMUL_D:
    case LoongArch::XVMUL_H:
    case LoongArch::XVMUL_W:
    case LoongArch::XVNOR_V:
    case LoongArch::XVORN_V:
    case LoongArch::XVOR_V:
    case LoongArch::XVPACKEV_B:
    case LoongArch::XVPACKEV_D:
    case LoongArch::XVPACKEV_H:
    case LoongArch::XVPACKEV_W:
    case LoongArch::XVPACKOD_B:
    case LoongArch::XVPACKOD_D:
    case LoongArch::XVPACKOD_H:
    case LoongArch::XVPACKOD_W:
    case LoongArch::XVPERM_W:
    case LoongArch::XVPICKEV_B:
    case LoongArch::XVPICKEV_D:
    case LoongArch::XVPICKEV_H:
    case LoongArch::XVPICKEV_W:
    case LoongArch::XVPICKOD_B:
    case LoongArch::XVPICKOD_D:
    case LoongArch::XVPICKOD_H:
    case LoongArch::XVPICKOD_W:
    case LoongArch::XVROTR_B:
    case LoongArch::XVROTR_D:
    case LoongArch::XVROTR_H:
    case LoongArch::XVROTR_W:
    case LoongArch::XVSADD_B:
    case LoongArch::XVSADD_BU:
    case LoongArch::XVSADD_D:
    case LoongArch::XVSADD_DU:
    case LoongArch::XVSADD_H:
    case LoongArch::XVSADD_HU:
    case LoongArch::XVSADD_W:
    case LoongArch::XVSADD_WU:
    case LoongArch::XVSEQ_B:
    case LoongArch::XVSEQ_D:
    case LoongArch::XVSEQ_H:
    case LoongArch::XVSEQ_W:
    case LoongArch::XVSIGNCOV_B:
    case LoongArch::XVSIGNCOV_D:
    case LoongArch::XVSIGNCOV_H:
    case LoongArch::XVSIGNCOV_W:
    case LoongArch::XVSLE_B:
    case LoongArch::XVSLE_BU:
    case LoongArch::XVSLE_D:
    case LoongArch::XVSLE_DU:
    case LoongArch::XVSLE_H:
    case LoongArch::XVSLE_HU:
    case LoongArch::XVSLE_W:
    case LoongArch::XVSLE_WU:
    case LoongArch::XVSLL_B:
    case LoongArch::XVSLL_D:
    case LoongArch::XVSLL_H:
    case LoongArch::XVSLL_W:
    case LoongArch::XVSLT_B:
    case LoongArch::XVSLT_BU:
    case LoongArch::XVSLT_D:
    case LoongArch::XVSLT_DU:
    case LoongArch::XVSLT_H:
    case LoongArch::XVSLT_HU:
    case LoongArch::XVSLT_W:
    case LoongArch::XVSLT_WU:
    case LoongArch::XVSRAN_B_H:
    case LoongArch::XVSRAN_H_W:
    case LoongArch::XVSRAN_W_D:
    case LoongArch::XVSRARN_B_H:
    case LoongArch::XVSRARN_H_W:
    case LoongArch::XVSRARN_W_D:
    case LoongArch::XVSRAR_B:
    case LoongArch::XVSRAR_D:
    case LoongArch::XVSRAR_H:
    case LoongArch::XVSRAR_W:
    case LoongArch::XVSRA_B:
    case LoongArch::XVSRA_D:
    case LoongArch::XVSRA_H:
    case LoongArch::XVSRA_W:
    case LoongArch::XVSRLN_B_H:
    case LoongArch::XVSRLN_H_W:
    case LoongArch::XVSRLN_W_D:
    case LoongArch::XVSRLRN_B_H:
    case LoongArch::XVSRLRN_H_W:
    case LoongArch::XVSRLRN_W_D:
    case LoongArch::XVSRLR_B:
    case LoongArch::XVSRLR_D:
    case LoongArch::XVSRLR_H:
    case LoongArch::XVSRLR_W:
    case LoongArch::XVSRL_B:
    case LoongArch::XVSRL_D:
    case LoongArch::XVSRL_H:
    case LoongArch::XVSRL_W:
    case LoongArch::XVSSRAN_BU_H:
    case LoongArch::XVSSRAN_B_H:
    case LoongArch::XVSSRAN_HU_W:
    case LoongArch::XVSSRAN_H_W:
    case LoongArch::XVSSRAN_WU_D:
    case LoongArch::XVSSRAN_W_D:
    case LoongArch::XVSSRARN_BU_H:
    case LoongArch::XVSSRARN_B_H:
    case LoongArch::XVSSRARN_HU_W:
    case LoongArch::XVSSRARN_H_W:
    case LoongArch::XVSSRARN_WU_D:
    case LoongArch::XVSSRARN_W_D:
    case LoongArch::XVSSRLN_BU_H:
    case LoongArch::XVSSRLN_B_H:
    case LoongArch::XVSSRLN_HU_W:
    case LoongArch::XVSSRLN_H_W:
    case LoongArch::XVSSRLN_WU_D:
    case LoongArch::XVSSRLN_W_D:
    case LoongArch::XVSSRLRN_BU_H:
    case LoongArch::XVSSRLRN_B_H:
    case LoongArch::XVSSRLRN_HU_W:
    case LoongArch::XVSSRLRN_H_W:
    case LoongArch::XVSSRLRN_WU_D:
    case LoongArch::XVSSRLRN_W_D:
    case LoongArch::XVSSUB_B:
    case LoongArch::XVSSUB_BU:
    case LoongArch::XVSSUB_D:
    case LoongArch::XVSSUB_DU:
    case LoongArch::XVSSUB_H:
    case LoongArch::XVSSUB_HU:
    case LoongArch::XVSSUB_W:
    case LoongArch::XVSSUB_WU:
    case LoongArch::XVSUBWEV_D_W:
    case LoongArch::XVSUBWEV_D_WU:
    case LoongArch::XVSUBWEV_H_B:
    case LoongArch::XVSUBWEV_H_BU:
    case LoongArch::XVSUBWEV_Q_D:
    case LoongArch::XVSUBWEV_Q_DU:
    case LoongArch::XVSUBWEV_W_H:
    case LoongArch::XVSUBWEV_W_HU:
    case LoongArch::XVSUBWOD_D_W:
    case LoongArch::XVSUBWOD_D_WU:
    case LoongArch::XVSUBWOD_H_B:
    case LoongArch::XVSUBWOD_H_BU:
    case LoongArch::XVSUBWOD_Q_D:
    case LoongArch::XVSUBWOD_Q_DU:
    case LoongArch::XVSUBWOD_W_H:
    case LoongArch::XVSUBWOD_W_HU:
    case LoongArch::XVSUB_B:
    case LoongArch::XVSUB_D:
    case LoongArch::XVSUB_H:
    case LoongArch::XVSUB_Q:
    case LoongArch::XVSUB_W:
    case LoongArch::XVXOR_V: {
      switch (OpNum) {
      case 2:
        // op: xk
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::FSEL_xD:
    case LoongArch::FSEL_xS: {
      switch (OpNum) {
      case 3:
        // op: ca
        return 15;
      case 2:
        // op: fk
        return 10;
      case 1:
        // op: fj
        return 5;
      case 0:
        // op: fd
        return 0;
      }
      break;
    }
    case LoongArch::CSRXCHG:
    case LoongArch::GCSRXCHG: {
      switch (OpNum) {
      case 3:
        // op: csr_num
        return 10;
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::FMADD_D:
    case LoongArch::FMADD_S:
    case LoongArch::FMSUB_D:
    case LoongArch::FMSUB_S:
    case LoongArch::FNMADD_D:
    case LoongArch::FNMADD_S:
    case LoongArch::FNMSUB_D:
    case LoongArch::FNMSUB_S: {
      switch (OpNum) {
      case 3:
        // op: fa
        return 15;
      case 2:
        // op: fk
        return 10;
      case 1:
        // op: fj
        return 5;
      case 0:
        // op: fd
        return 0;
      }
      break;
    }
    case LoongArch::VINSGR2VR_D: {
      switch (OpNum) {
      case 3:
        // op: imm1
        return 10;
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::VSTELM_D: {
      switch (OpNum) {
      case 3:
        // op: imm1
        return 18;
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::SC_D:
    case LoongArch::SC_W: {
      switch (OpNum) {
      case 3:
        // op: imm14
        return 10;
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VINSGR2VR_W: {
      switch (OpNum) {
      case 3:
        // op: imm2
        return 10;
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVINSGR2VR_D: {
      switch (OpNum) {
      case 3:
        // op: imm2
        return 10;
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::XVINSVE0_D: {
      switch (OpNum) {
      case 3:
        // op: imm2
        return 10;
      case 2:
        // op: xj
        return 5;
      case 1:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::ALSL_D:
    case LoongArch::ALSL_W:
    case LoongArch::ALSL_WU:
    case LoongArch::BYTEPICK_W: {
      switch (OpNum) {
      case 3:
        // op: imm2
        return 15;
      case 2:
        // op: rk
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VSTELM_W: {
      switch (OpNum) {
      case 3:
        // op: imm2
        return 18;
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVSTELM_D: {
      switch (OpNum) {
      case 3:
        // op: imm2
        return 18;
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VINSGR2VR_H: {
      switch (OpNum) {
      case 3:
        // op: imm3
        return 10;
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVINSGR2VR_W: {
      switch (OpNum) {
      case 3:
        // op: imm3
        return 10;
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::XVINSVE0_W: {
      switch (OpNum) {
      case 3:
        // op: imm3
        return 10;
      case 2:
        // op: xj
        return 5;
      case 1:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::BYTEPICK_D: {
      switch (OpNum) {
      case 3:
        // op: imm3
        return 15;
      case 2:
        // op: rk
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VSTELM_H: {
      switch (OpNum) {
      case 3:
        // op: imm3
        return 18;
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVSTELM_W: {
      switch (OpNum) {
      case 3:
        // op: imm3
        return 18;
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VINSGR2VR_B: {
      switch (OpNum) {
      case 3:
        // op: imm4
        return 10;
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::VSRANI_B_H:
    case LoongArch::VSRARNI_B_H:
    case LoongArch::VSRLNI_B_H:
    case LoongArch::VSRLRNI_B_H:
    case LoongArch::VSSRANI_BU_H:
    case LoongArch::VSSRANI_B_H:
    case LoongArch::VSSRARNI_BU_H:
    case LoongArch::VSSRARNI_B_H:
    case LoongArch::VSSRLNI_BU_H:
    case LoongArch::VSSRLNI_B_H:
    case LoongArch::VSSRLRNI_BU_H:
    case LoongArch::VSSRLRNI_B_H: {
      switch (OpNum) {
      case 3:
        // op: imm4
        return 10;
      case 2:
        // op: vj
        return 5;
      case 1:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVSRANI_B_H:
    case LoongArch::XVSRARNI_B_H:
    case LoongArch::XVSRLNI_B_H:
    case LoongArch::XVSRLRNI_B_H:
    case LoongArch::XVSSRANI_BU_H:
    case LoongArch::XVSSRANI_B_H:
    case LoongArch::XVSSRARNI_BU_H:
    case LoongArch::XVSSRARNI_B_H:
    case LoongArch::XVSSRLNI_BU_H:
    case LoongArch::XVSSRLNI_B_H:
    case LoongArch::XVSSRLRNI_BU_H:
    case LoongArch::XVSSRLRNI_B_H: {
      switch (OpNum) {
      case 3:
        // op: imm4
        return 10;
      case 2:
        // op: xj
        return 5;
      case 1:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VSTELM_B: {
      switch (OpNum) {
      case 3:
        // op: imm4
        return 18;
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVSTELM_H: {
      switch (OpNum) {
      case 3:
        // op: imm4
        return 18;
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VFRSTPI_B:
    case LoongArch::VFRSTPI_H:
    case LoongArch::VSRANI_H_W:
    case LoongArch::VSRARNI_H_W:
    case LoongArch::VSRLNI_H_W:
    case LoongArch::VSRLRNI_H_W:
    case LoongArch::VSSRANI_HU_W:
    case LoongArch::VSSRANI_H_W:
    case LoongArch::VSSRARNI_HU_W:
    case LoongArch::VSSRARNI_H_W:
    case LoongArch::VSSRLNI_HU_W:
    case LoongArch::VSSRLNI_H_W:
    case LoongArch::VSSRLRNI_HU_W:
    case LoongArch::VSSRLRNI_H_W: {
      switch (OpNum) {
      case 3:
        // op: imm5
        return 10;
      case 2:
        // op: vj
        return 5;
      case 1:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVFRSTPI_B:
    case LoongArch::XVFRSTPI_H:
    case LoongArch::XVSRANI_H_W:
    case LoongArch::XVSRARNI_H_W:
    case LoongArch::XVSRLNI_H_W:
    case LoongArch::XVSRLRNI_H_W:
    case LoongArch::XVSSRANI_HU_W:
    case LoongArch::XVSSRANI_H_W:
    case LoongArch::XVSSRARNI_HU_W:
    case LoongArch::XVSSRARNI_H_W:
    case LoongArch::XVSSRLNI_HU_W:
    case LoongArch::XVSSRLNI_H_W:
    case LoongArch::XVSSRLRNI_HU_W:
    case LoongArch::XVSSRLRNI_H_W: {
      switch (OpNum) {
      case 3:
        // op: imm5
        return 10;
      case 2:
        // op: xj
        return 5;
      case 1:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::XVSTELM_B: {
      switch (OpNum) {
      case 3:
        // op: imm5
        return 18;
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VSRANI_W_D:
    case LoongArch::VSRARNI_W_D:
    case LoongArch::VSRLNI_W_D:
    case LoongArch::VSRLRNI_W_D:
    case LoongArch::VSSRANI_WU_D:
    case LoongArch::VSSRANI_W_D:
    case LoongArch::VSSRARNI_WU_D:
    case LoongArch::VSSRARNI_W_D:
    case LoongArch::VSSRLNI_WU_D:
    case LoongArch::VSSRLNI_W_D:
    case LoongArch::VSSRLRNI_WU_D:
    case LoongArch::VSSRLRNI_W_D: {
      switch (OpNum) {
      case 3:
        // op: imm6
        return 10;
      case 2:
        // op: vj
        return 5;
      case 1:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVSRANI_W_D:
    case LoongArch::XVSRARNI_W_D:
    case LoongArch::XVSRLNI_W_D:
    case LoongArch::XVSRLRNI_W_D:
    case LoongArch::XVSSRANI_WU_D:
    case LoongArch::XVSSRANI_W_D:
    case LoongArch::XVSSRARNI_WU_D:
    case LoongArch::XVSSRARNI_W_D:
    case LoongArch::XVSSRLNI_WU_D:
    case LoongArch::XVSSRLNI_W_D:
    case LoongArch::XVSSRLRNI_WU_D:
    case LoongArch::XVSSRLRNI_W_D: {
      switch (OpNum) {
      case 3:
        // op: imm6
        return 10;
      case 2:
        // op: xj
        return 5;
      case 1:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VSRANI_D_Q:
    case LoongArch::VSRARNI_D_Q:
    case LoongArch::VSRLNI_D_Q:
    case LoongArch::VSRLRNI_D_Q:
    case LoongArch::VSSRANI_DU_Q:
    case LoongArch::VSSRANI_D_Q:
    case LoongArch::VSSRARNI_DU_Q:
    case LoongArch::VSSRARNI_D_Q:
    case LoongArch::VSSRLNI_DU_Q:
    case LoongArch::VSSRLNI_D_Q:
    case LoongArch::VSSRLRNI_DU_Q:
    case LoongArch::VSSRLRNI_D_Q: {
      switch (OpNum) {
      case 3:
        // op: imm7
        return 10;
      case 2:
        // op: vj
        return 5;
      case 1:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVSRANI_D_Q:
    case LoongArch::XVSRARNI_D_Q:
    case LoongArch::XVSRLNI_D_Q:
    case LoongArch::XVSRLRNI_D_Q:
    case LoongArch::XVSSRANI_DU_Q:
    case LoongArch::XVSSRANI_D_Q:
    case LoongArch::XVSSRARNI_DU_Q:
    case LoongArch::XVSSRARNI_D_Q:
    case LoongArch::XVSSRLNI_DU_Q:
    case LoongArch::XVSSRLNI_D_Q:
    case LoongArch::XVSSRLRNI_DU_Q:
    case LoongArch::XVSSRLRNI_D_Q: {
      switch (OpNum) {
      case 3:
        // op: imm7
        return 10;
      case 2:
        // op: xj
        return 5;
      case 1:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VBITSELI_B:
    case LoongArch::VEXTRINS_B:
    case LoongArch::VEXTRINS_D:
    case LoongArch::VEXTRINS_H:
    case LoongArch::VEXTRINS_W:
    case LoongArch::VPERMI_W:
    case LoongArch::VSHUF4I_D: {
      switch (OpNum) {
      case 3:
        // op: imm8
        return 10;
      case 2:
        // op: vj
        return 5;
      case 1:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVBITSELI_B:
    case LoongArch::XVEXTRINS_B:
    case LoongArch::XVEXTRINS_D:
    case LoongArch::XVEXTRINS_H:
    case LoongArch::XVEXTRINS_W:
    case LoongArch::XVPERMI_Q:
    case LoongArch::XVPERMI_W:
    case LoongArch::XVSHUF4I_D: {
      switch (OpNum) {
      case 3:
        // op: imm8
        return 10;
      case 2:
        // op: xj
        return 5;
      case 1:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::BSTRINS_D: {
      switch (OpNum) {
      case 3:
        // op: msbd
        return 16;
      case 4:
        // op: lsbd
        return 10;
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::BSTRINS_W: {
      switch (OpNum) {
      case 3:
        // op: msbw
        return 16;
      case 4:
        // op: lsbw
        return 10;
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VBITSEL_V:
    case LoongArch::VFMADD_D:
    case LoongArch::VFMADD_S:
    case LoongArch::VFMSUB_D:
    case LoongArch::VFMSUB_S:
    case LoongArch::VFNMADD_D:
    case LoongArch::VFNMADD_S:
    case LoongArch::VFNMSUB_D:
    case LoongArch::VFNMSUB_S:
    case LoongArch::VSHUF_B: {
      switch (OpNum) {
      case 3:
        // op: va
        return 15;
      case 2:
        // op: vk
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::VFRSTP_B:
    case LoongArch::VFRSTP_H:
    case LoongArch::VMADDWEV_D_W:
    case LoongArch::VMADDWEV_D_WU:
    case LoongArch::VMADDWEV_D_WU_W:
    case LoongArch::VMADDWEV_H_B:
    case LoongArch::VMADDWEV_H_BU:
    case LoongArch::VMADDWEV_H_BU_B:
    case LoongArch::VMADDWEV_Q_D:
    case LoongArch::VMADDWEV_Q_DU:
    case LoongArch::VMADDWEV_Q_DU_D:
    case LoongArch::VMADDWEV_W_H:
    case LoongArch::VMADDWEV_W_HU:
    case LoongArch::VMADDWEV_W_HU_H:
    case LoongArch::VMADDWOD_D_W:
    case LoongArch::VMADDWOD_D_WU:
    case LoongArch::VMADDWOD_D_WU_W:
    case LoongArch::VMADDWOD_H_B:
    case LoongArch::VMADDWOD_H_BU:
    case LoongArch::VMADDWOD_H_BU_B:
    case LoongArch::VMADDWOD_Q_D:
    case LoongArch::VMADDWOD_Q_DU:
    case LoongArch::VMADDWOD_Q_DU_D:
    case LoongArch::VMADDWOD_W_H:
    case LoongArch::VMADDWOD_W_HU:
    case LoongArch::VMADDWOD_W_HU_H:
    case LoongArch::VMADD_B:
    case LoongArch::VMADD_D:
    case LoongArch::VMADD_H:
    case LoongArch::VMADD_W:
    case LoongArch::VMSUB_B:
    case LoongArch::VMSUB_D:
    case LoongArch::VMSUB_H:
    case LoongArch::VMSUB_W:
    case LoongArch::VSHUF_D:
    case LoongArch::VSHUF_H:
    case LoongArch::VSHUF_W: {
      switch (OpNum) {
      case 3:
        // op: vk
        return 10;
      case 2:
        // op: vj
        return 5;
      case 1:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVBITSEL_V:
    case LoongArch::XVFMADD_D:
    case LoongArch::XVFMADD_S:
    case LoongArch::XVFMSUB_D:
    case LoongArch::XVFMSUB_S:
    case LoongArch::XVFNMADD_D:
    case LoongArch::XVFNMADD_S:
    case LoongArch::XVFNMSUB_D:
    case LoongArch::XVFNMSUB_S:
    case LoongArch::XVSHUF_B: {
      switch (OpNum) {
      case 3:
        // op: xa
        return 15;
      case 2:
        // op: xk
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::XVFRSTP_B:
    case LoongArch::XVFRSTP_H:
    case LoongArch::XVMADDWEV_D_W:
    case LoongArch::XVMADDWEV_D_WU:
    case LoongArch::XVMADDWEV_D_WU_W:
    case LoongArch::XVMADDWEV_H_B:
    case LoongArch::XVMADDWEV_H_BU:
    case LoongArch::XVMADDWEV_H_BU_B:
    case LoongArch::XVMADDWEV_Q_D:
    case LoongArch::XVMADDWEV_Q_DU:
    case LoongArch::XVMADDWEV_Q_DU_D:
    case LoongArch::XVMADDWEV_W_H:
    case LoongArch::XVMADDWEV_W_HU:
    case LoongArch::XVMADDWEV_W_HU_H:
    case LoongArch::XVMADDWOD_D_W:
    case LoongArch::XVMADDWOD_D_WU:
    case LoongArch::XVMADDWOD_D_WU_W:
    case LoongArch::XVMADDWOD_H_B:
    case LoongArch::XVMADDWOD_H_BU:
    case LoongArch::XVMADDWOD_H_BU_B:
    case LoongArch::XVMADDWOD_Q_D:
    case LoongArch::XVMADDWOD_Q_DU:
    case LoongArch::XVMADDWOD_Q_DU_D:
    case LoongArch::XVMADDWOD_W_H:
    case LoongArch::XVMADDWOD_W_HU:
    case LoongArch::XVMADDWOD_W_HU_H:
    case LoongArch::XVMADD_B:
    case LoongArch::XVMADD_D:
    case LoongArch::XVMADD_H:
    case LoongArch::XVMADD_W:
    case LoongArch::XVMSUB_B:
    case LoongArch::XVMSUB_D:
    case LoongArch::XVMSUB_H:
    case LoongArch::XVMSUB_W:
    case LoongArch::XVSHUF_D:
    case LoongArch::XVSHUF_H:
    case LoongArch::XVSHUF_W: {
      switch (OpNum) {
      case 3:
        // op: xk
        return 10;
      case 2:
        // op: xj
        return 5;
      case 1:
        // op: xd
        return 0;
      }
      break;
    }
  default:
    reportUnsupportedInst(MI);
  }
  reportUnsupportedOperand(MI, OpNum);
}

#endif // GET_OPERAND_BIT_OFFSET

