/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register and Register Classes Information                           *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

namespace llvm {

extern const MCRegisterClass NVPTXMCRegisterClasses[];

static const MVT::SimpleValueType VTLists[] = {
  /* 0 */ MVT::i1, MVT::Other,
  /* 2 */ MVT::i32, MVT::Other,
  /* 4 */ MVT::i128, MVT::Other,
  /* 6 */ MVT::i16, MVT::f16, MVT::bf16, MVT::Other,
  /* 10 */ MVT::i32, MVT::v2f16, MVT::v2bf16, MVT::v2i16, MVT::v4i8, MVT::f32, MVT::Other,
  /* 17 */ MVT::i64, MVT::v2i32, MVT::v2f32, MVT::f64, MVT::Other,
};

static const char *SubRegIndexNameTable[] = { "" };

static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
  { 65535, 65535 },
  { 65535, 65535 },
};


static const LaneBitmask SubRegIndexLaneMaskTable[] = {
  LaneBitmask::getAll(),
 };



static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
  // Mode = 0 (Default)
  { 1, 1, 8, /*VTLists+*/0 },    // B1
  { 16, 16, 16, /*VTLists+*/6 },    // B16
  { 32, 32, 32, /*VTLists+*/2 },    // SpecialRegs
  { 32, 32, 32, /*VTLists+*/10 },    // B32
  { 32, 32, 32, /*VTLists+*/10 },    // B32_and_SpecialRegs
  { 64, 64, 64, /*VTLists+*/17 },    // B64
  { 128, 128, 128, /*VTLists+*/4 },    // B128
  // Mode = 1 (NVPTX64)
  { 1, 1, 8, /*VTLists+*/0 },    // B1
  { 16, 16, 16, /*VTLists+*/6 },    // B16
  { 32, 32, 32, /*VTLists+*/2 },    // SpecialRegs
  { 32, 32, 32, /*VTLists+*/10 },    // B32
  { 32, 32, 32, /*VTLists+*/10 },    // B32_and_SpecialRegs
  { 64, 64, 64, /*VTLists+*/17 },    // B64
  { 128, 128, 128, /*VTLists+*/4 },    // B128
};
static const uint32_t B1SubClassMask[] = {
  0x00000001, 
};

static const uint32_t B16SubClassMask[] = {
  0x00000002, 
};

static const uint32_t SpecialRegsSubClassMask[] = {
  0x00000014, 
};

static const uint32_t B32SubClassMask[] = {
  0x00000018, 
};

static const uint32_t B32_and_SpecialRegsSubClassMask[] = {
  0x00000010, 
};

static const uint32_t B64SubClassMask[] = {
  0x00000020, 
};

static const uint32_t B128SubClassMask[] = {
  0x00000040, 
};

static const uint16_t SuperRegIdxSeqs[] = {
  /* 0 */ 0,
};

static unsigned const B32_and_SpecialRegsSuperclasses[] = {
  NVPTX::SpecialRegsRegClassID,
  NVPTX::B32RegClassID,
};


namespace NVPTX {   // Register class instances
  extern const TargetRegisterClass B1RegClass = {
    &NVPTXMCRegisterClasses[B1RegClassID],
    B1SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass B16RegClass = {
    &NVPTXMCRegisterClasses[B16RegClassID],
    B16SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass SpecialRegsRegClass = {
    &NVPTXMCRegisterClasses[SpecialRegsRegClassID],
    SpecialRegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass B32RegClass = {
    &NVPTXMCRegisterClasses[B32RegClassID],
    B32SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass B32_and_SpecialRegsRegClass = {
    &NVPTXMCRegisterClasses[B32_and_SpecialRegsRegClassID],
    B32_and_SpecialRegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    B32_and_SpecialRegsSuperclasses,  2,
    nullptr
  };

  extern const TargetRegisterClass B64RegClass = {
    &NVPTXMCRegisterClasses[B64RegClassID],
    B64SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass B128RegClass = {
    &NVPTXMCRegisterClasses[B128RegClassID],
    B128SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

} // end namespace NVPTX

namespace {
  const TargetRegisterClass *const RegisterClasses[] = {
    &NVPTX::B1RegClass,
    &NVPTX::B16RegClass,
    &NVPTX::SpecialRegsRegClass,
    &NVPTX::B32RegClass,
    &NVPTX::B32_and_SpecialRegsRegClass,
    &NVPTX::B64RegClass,
    &NVPTX::B128RegClass,
  };
} // end anonymous namespace

static const uint8_t CostPerUseTable[] = { 
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };


static const bool InAllocatableClassTable[] = { 
false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };


static const TargetRegisterInfoDesc NVPTXRegInfoDesc = { // Extra Descriptors
CostPerUseTable, 1, InAllocatableClassTable};

/// Get the weight in units of pressure for this register class.
const RegClassWeight &NVPTXGenRegisterInfo::
getRegClassWeight(const TargetRegisterClass *RC) const {
  static const RegClassWeight RCWeightTable[] = {
    {1, 5},  	// B1
    {1, 5},  	// B16
    {1, 35},  	// SpecialRegs
    {1, 7},  	// B32
    {1, 2},  	// B32_and_SpecialRegs
    {1, 7},  	// B64
    {1, 5},  	// B128
  };
  return RCWeightTable[RC->getID()];
}

/// Get the weight in units of pressure for this register unit.
unsigned NVPTXGenRegisterInfo::
getRegUnitWeight(MCRegUnit RegUnit) const {
  assert(static_cast<unsigned>(RegUnit) < 62 && "invalid register unit");
  // All register units have unit weight.
  return 1;
}


// Get the number of dimensions of register pressure.
unsigned NVPTXGenRegisterInfo::getNumRegPressureSets() const {
  return 8;
}

// Get the name of this register unit pressure set.
const char *NVPTXGenRegisterInfo::
getRegPressureSetName(unsigned Idx) const {
  static const char *PressureNameTable[] = {
    "B32_and_SpecialRegs",
    "B1",
    "B16",
    "B128",
    "B32",
    "B64",
    "SpecialRegs",
    "SpecialRegs_with_B32",
  };
  return PressureNameTable[Idx];
}

// Get the register unit pressure limit for this dimension.
// This limit must be adjusted dynamically for reserved registers.
unsigned NVPTXGenRegisterInfo::
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
  static const uint8_t PressureLimitTable[] = {
    2,  	// 0: B32_and_SpecialRegs
    5,  	// 1: B1
    5,  	// 2: B16
    5,  	// 3: B128
    7,  	// 4: B32
    7,  	// 5: B64
    35,  	// 6: SpecialRegs
    40,  	// 7: SpecialRegs_with_B32
  };
  return PressureLimitTable[Idx];
}

/// Table of pressure sets per register class or unit.
static const int RCSetsTable[] = {
  /* 0 */ 1, -1,
  /* 2 */ 2, -1,
  /* 4 */ 3, -1,
  /* 6 */ 5, -1,
  /* 8 */ 4, 7, -1,
  /* 11 */ 0, 4, 6, 7, -1,
};

/// Get the dimensions of register pressure impacted by this register class.
/// Returns a -1 terminated array of pressure set IDs
const int *NVPTXGenRegisterInfo::
getRegClassPressureSets(const TargetRegisterClass *RC) const {
  static const uint8_t RCSetStartTable[] = {
    0,2,13,8,11,6,4,};
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
}

/// Get the dimensions of register pressure impacted by this register unit.
/// Returns a -1 terminated array of pressure set IDs
const int *NVPTXGenRegisterInfo::
getRegUnitPressureSets(MCRegUnit RegUnit) const {
  assert(static_cast<unsigned>(RegUnit) < 62 && "invalid register unit");
  static const uint8_t RUSetStartTable[] = {
    13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,0,0,0,0,0,8,8,8,8,8,6,6,6,6,6,4,4,4,4,4,2,2,2,2,2,11,6,11,6,};
  return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
}

extern const MCRegisterDesc NVPTXRegDesc[];
extern const int16_t NVPTXRegDiffLists[];
extern const LaneBitmask NVPTXLaneMaskLists[];
extern const char NVPTXRegStrings[];
extern const char NVPTXRegClassStrings[];
extern const MCPhysReg NVPTXRegUnitRoots[][2];
extern const uint16_t NVPTXSubRegIdxLists[];
extern const uint16_t NVPTXRegEncodingTable[];
NVPTXGenRegisterInfo::
NVPTXGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
      unsigned PC, unsigned HwMode)
  : TargetRegisterInfo(&NVPTXRegInfoDesc, RegisterClasses, RegisterClasses+7,
             SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
             LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
  InitMCRegisterInfo(NVPTXRegDesc, 63, RA, PC,
                     NVPTXMCRegisterClasses, 7,
                     NVPTXRegUnitRoots,
                     62,
                     NVPTXRegDiffLists,
                     NVPTXLaneMaskLists,
                     NVPTXRegStrings,
                     NVPTXRegClassStrings,
                     NVPTXSubRegIdxLists,
                     1,
                     NVPTXRegEncodingTable);

}



ArrayRef<const uint32_t *> NVPTXGenRegisterInfo::getRegMasks() const {
  return {};
}

bool NVPTXGenRegisterInfo::
isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool NVPTXGenRegisterInfo::
isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
  return
      false;
}

bool NVPTXGenRegisterInfo::
isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool NVPTXGenRegisterInfo::
isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool NVPTXGenRegisterInfo::
isConstantPhysReg(MCRegister PhysReg) const {
  return
      false;
}

ArrayRef<const char *> NVPTXGenRegisterInfo::getRegMaskNames() const {
  return {};
}

const NVPTXFrameLowering *
NVPTXGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
  return static_cast<const NVPTXFrameLowering *>(
      MF.getSubtarget().getFrameLowering());
}

} // end namespace llvm

